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Training Manual

50PV450 Plasma Display

Advanced Single Scan Troubleshooting 50" Class Full HD 1080p Plasma TV (49.9" diagonally)

Published April 25th, 201 1 Updated June 17th, 201 1 (See Last Page for Updates)

Overview of Topics to be Discussed
Preliminary: Contact Information, Preliminary Matters Specifications Information Matters, Specifications, Plasma Overview, General Troubleshooting Steps, Disassembly Instructions, Voltage and Signal Distribution Troubleshooting: Circuit Board Operation, Troubleshooting and Alignment of : • Switch Mode Power Supply • Y SUS B d Y-SUS Board • Y-Drive Boards (1 Upper and 1 Lower). • Z-SUS Board • Control Board • X Drive Boards (3) • Main Board: • Front IR/Intelligent Sensor • Interconnect Diagram: 11X17 Foldout Section used as a quick reference sheet. 2 May 201 50PV450 1 Plasma
Drives 15 TCPs (5 per/board). Each TCP drives 384 vertical electrodes. Uses a Z-SUB Board for panel drive connection. No “VS On” command input to SMPS from the Main Board.

Preliminary Matters

50PV450 Pl Plasma Di l Display
Section 1
This Section will cover Contact Information and remind the Technician of Important Safety Precautions for the Customer’s Safety as well as the Technician’s and the Equipment. Basic Troubleshooting Techniques which can save time and money sometimes can be overlooked. These techniques will also be presented. This Section will get the Technician familiar with the Disassembly, Identification and Layout of the Plasma Display Panel. At the end of this Section the Technician should be able to Identify the Circuit th d f thi S ti th T h i i h ld b bl t Id tif th Ci it Boards and have the ability and knowledge necessary to safely remove and replace any Circuit Board or Assembly.

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Plasma

Huntsville. Connector s.com http://www. AL. oduc c u es and ea u es Interconnect Diagrams.webex. Dimensions. LG Electronics Alabama.200 Training Manuals. 35813.4.com http://lgtechassist. Also available on the Plasma Page: PDP Panel Alignment Handbook.com/ilearn New: 2010 Models Wireless Ready Software Downloads Presentations with Audio/Video and Screen Marks http://136.us.LG Contact Information Customer Service (and Part Sales) Technical Support (and Part Sales) USA Website (GSFS) Customer Service Website Knowledgebase Website LG Web Training LG CS Learning Academy (800) 243-0000 (800) 847 7597 847-7597 http://gsfs-america. 201 James Record Road.166.lge. Co ec o IDs. e s o s.com http://ln.lgservice.lge.com https://lge. 4 May 201 50PV450 1 Plasma . Plasma Control Board ROM Update (Jig required) Published May 2011 by LG Technical Support and Training . Start-Up Sequence. e co ec ag a s. Schematics with Navigational Bookmarks. Inc. Product Pictures a d Features. Owner’s Guides.

straps. disconnect the power immediately after performing the necessary checks Also be aware that many household products present a weight hazard checks. under no circumstances should the original design be modified or altered without permission from LG Electronics. injury. hazard. screws. In any attempt to repair a major Product. Unauthorized modifications will not only void the warranty but may lead to property damage or user injury warranty. nor can it assume any liability in conjunction with its use. If wires. and mechanical systems. seller maintains no liability for the interpretation of this information. nuts. disconnect the power before servicing this product. electronic devices. clips. If electrical power is required for diagnosis or test purposes. or washers used to complete a ground path are removed for service.Preliminary Matters (The Fine Print) IMPORTANT SAFETY NOTICE The information in this training manual is intended for use by persons possessing an adequate background in electrical equipment. they must be returned to their original positions and properly fastened. When servicing this product. personal injury and property damage can result The manufacturer or Product result. At least two people should be involved in the installation or servicing of such devices. CAUTION To avoid personal injury. 5 May 201 50PV450 1 Plasma . Failure to consider the weight of an product could result in physical injury.

pursuant to Part 15 of the FCC Rules. Regulatory Information R l I f i This equipment has been tested and found to comply with the limits for a Class B digital device. which can be determined by turning the equipment off and on. However. When repackaging a failed electronic device in an anti-static bag.Preliminary Matters (The Fine Print) ESD Notice (Electrostatic Static Discharge) Today’s sophisticated electronics are electrostatic discharge (ESD) sensitive. Alternatively. may cause harmful interference to radio communications. you can touch your finger repeatedly to a ground connection point or unpainted metal in the product. if not installed and used in accordance with the instruction manual. ESD can weaken or damage the electronics in a manner that renders them inoperative or reduces the time until their next failure. observe these same precautions. This equipment generates. Before removing a replacement part from its package. Increase the separation between the equipment and the receiver. touch the anti-static bag to a ground connection point or package unpainted metal in the product. there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception. 6 May 201 50PV450 1 Plasma . and. f and can radiate radio frequency energy. or consult the dealer or an experienced radio/TV technician for help. Connect an ESD wrist strap to a ground connection point or unpainted metal in the product. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a residential installation. the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Handle the electronic control assembly by its edges only. Connect the equipment to an outlet on a different circuit than that to which the receiver is connected. uses.

New Plasma Models have thinner Display Panels and Frames than previous models. The Plasma television should be transported vertically NOT horizontally. 5.Safety and Handling. Be cautious of lost screws and other metal objects to prevent a possible short in the circuitry. Example: Y-SUS or Y-Drive Board Failure. Check the appearance of the Replacement Panel and Circuit Boards for both physical damage and part number accuracy. Y SUS Z SUS Boards Always adjust to the specified voltage level (+/. Checking Points Safety & Handling Regulations 1. 3. Refer to the Voltage Sticker on the Panel when making adjustments on the Power Supply Y-SUS and Z-SUS Boards.½ volt) unless otherwise specified. etc. Approximately 10 minute pre-run time is required before any adjustments are performed. 3 4. Mal-discharge on screen. 5 6. Check the model label. 8. Be careful when lifting Plasma Display’s because flexing the panel may damage the frame mounts or panel. Exercise care when making voltage and waveform checks to prevent costly short circuits from damaging the unit. 3. Verify model names and board model matches. 7. 9. 5. The PDP Module must be carried by two people. Supply. Always carry vertical NOT horizontal. Checking Points to be Considered 1. Check details of defective condition and history. Refer to the silk screening on the Switch Mode Power Supply for proper Voltage and Current listings and manufacturer’s cautions. 2. 7 May 201 50PV450 1 Plasma . 2. C-MOS circuits are used extensively for processing the Drive Signals and should be protected from static electricity electricity. Be cautious of electric shock from the PDP module since the PDP module uses high voltage. 10. check that the Power Supply and Drive Circuits are completely discharged because of residual current stored before Circuit Board removal.

Smell. •Isolate To further isolate the failure. Always confirm the supplies are not only the proper level but be sure they are noise free. 8 May 201 50PV450 1 Plasma . If the supplies are missing check the resistance for possible short circuits. Use your senses Sight. it is a quick indication of Standby Voltage. check for the proper waveforms with the Oscilloscope to make a final determination of the failure. Localize. •Correct The final step is to correct the problem. Listen for frequency changes which may occur with a Power Supply load failure. Make all necessary adjustments and lastly always perform a Safety AC Leakage Test before returning the product back to the Customer. Touch and Hearing. remember to observe the Front Power Indicator LED. •Localize After carefully checking the symptom and determining the circuits to be checked and after giving a thorough examination using your senses the first check should always be the DC Supply Voltages to those circuits under test. Look for correct Amplitude Phasing and Timing of the signals also check for the proper Duty Cycle of the signals.Basic Troubleshooting Steps Define. Sometimes “glitches” or “road bumps” will be an indication of an imminent failure. Be careful of ESD and make sure to check the DC Supplies for proper levels. Isolate and Correct •Define Look at the symptom carefully and determine what circuits could be causing the failure. Look for burned parts and check for possible overheated components. Capacitors will sometimes leak dielectric material and give off a distinct odor. if lit. listen for the “click” of a relay closing.

HDMI input shield.5K/10watt resistor in parallel with a 0. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. PC input shield. the reading must be infinite.5mA. AV connections. there is possibility of shock hazard and the set must be p checked and repaired before it is returned to the customer.) and the exposed metallic parts. Connect one lead of an ohm-meter to the AC plug prongs tied together and touch the other lead one at a time to any exposed metallic part on the set.AC Leakage Test Procedure Leakage Current Cold Check (Antenna Cold Check) p g .2MΩ. If the exposed metallic part has a return path to the chassis. If an abnormality exists it must be corrected before the receiver is returned to the customer. Such as the antenna terminal.75 lt which corresponds to 0. Leakage Current Hot Check (See figure) Plug the AC cord directly into the AC outlet. When the exposed metal has no return path to the chassis. Do not use a line isolation transformer during this check. In case any measurement is out of the limits specified. LAN jack. etc. Any lt A voltage measured must not exceed 0 75 volt RMS d t t d 0.15uF capacitor between a known good earth ground (Water Pipe. Check to be sure the AC Outlet is wired correctly and use the Receptacle Ground 9 May 201 50PV450 1 Plasma . connect an electrical jumper across the two AC plug prongs. Conduit. Connect 1. the measurement resistance should be between 1MΩ and 5 2MΩ 5. j p With the instrument AC plug removed from an AC source. etc.

50PV450 PRODUCT INFORMATION SECTION This section of the manual will discuss the specifications of the 50PV450 Ad Advanced Single Scan Plasma Display Television. d Si l S Pl Di l T l i i 10 May 201 50PV450 1 Plasma .

9" diagonal) • T Sli Frame TruSlim F • 600Hz Max Sub Field Driving • Full HD 1080p Resolution • ENERGY STAR® Qualified • Picture Wizard II • Intelligent Sensor gy g • Smart Energy Saving • ISFccc® Ready For Full Spec cat o s o u Specifications See the Specification Sheet 1 1 May 201 50PV450 1 Plasma .50PV450 Specifications 1080P PLASMA HDTV 50" Class (49.

50PV450 Logo Familiarization FULL HD RESOLUTION 1080P HD Resolution Pixels: 1920 (H) × 1080 (V) Enjoy twice the picture quality of standard HDTV with almost double the pixel resolution. Sensor) Save Energy. Draws less than 1 Watt in stand by. Those that have earned the ENERGY STAR use as much as 60% less energy to perform these functions. (Turns on Intelligent Sensor). Save Money It reduces the plasma display’s power consumption. Save Energy. Clear Voice Clearer dialogue sound Automatically enhances and amplifies the sound of the human voice frequency range to provide high-quality dialogue when background noise swells. The default factory setting complies with the Energy Star requirements and is adjusted to the comfortable level to be viewed at home. Save Money Home electronic products use energy when they're off to power features like clock displays and remote controls. Less energy means you pay less on your energy bill. 12 May 201 50PV450 1 Plasma . Just imagine a Blu-ray disc or video game seen on your new LG Full HD 1080p TV. See sharper details like never before. while providing the same performance at the same price as less-efficient models.

8 sub-field/frame) No smeared images during fast motion scenes Original Image 10 Sub Fields Per Frame Sub Field firing occurs using wall charge and polarity differences between Y-SUS and Z-SUS signals.600Hz Sub Field Driving (600 Hz Sub Field Driving) • • 600 Hz Sub Field Driving is achieved by using 10 sub-fields per frame process (vs. Comp. 13 May 201 50PV450 1 Plasma .

50PV450 Remote Control p/n AKB72914053 TOP PORTION BOTTOM PORTION 14 May 201 50PV450 1 Plasma .

50PV450 Rear and Side Input Jacks USB port for Software Upgrades. Music and Photos SIDE INPUTS AC In USB HDMI 3 Composite Video/Audio REAR INPUTS 15 May 201 50PV450 1 Plasma .

bin) into the root of the Jump Drive. Currently Installed Version Software Version found on the USB Flash Drive File found on the USB Flash Drive 2) Copy new software (xxx. Do not turn off Power. insert USB flash drive. 3) With TV turned on. Software Files are now available from LGTechassist.Generic Plasma USB Automatic Software Download Instructions 1) Download the Software File. Highlight Start Press Select * CAUTION: Do not remove AC power or the USB Flash Drive. 7) Do not unplug until unit has automatically restarted. 8) When download is completed. 4) You can see the message “TV Software Upgrade” (See figure on right) 5) Cursor left and highlight "START" Button and push “Enter” button using the remote control. during the upgrade process. 6) You can see the download progress Bar Bar. you will see “COMPLETE”.com 16 May 201 50PV450 1 Plasma . 9) Your TV will be restarted automatically. ) . Make sure you have the correct software file.

Manual Software Download: Prepare the Jump Drive as described in the “USB Automatic Download” section and insert it into the USB port. Press the “FAV” key 7 times to bring up the first screen for Manual Download Screen (Expert Mode) FAV Mode). Press the “FAV” key 7 times Location of files found On the Jump Drive Scroll down and highlight “Options” Highlight the Software update file the highlight “Start” and press “SELECT” to begin the download process. WARNING: Use extreme Caution when using the Manual “Forced” Download Menu. Bring up the Customer’s Menu and scroll to “OPTIONS”. (Nothing should be highlighted on the right side). 17 May 201 50PV450 1 Plasma . Any file can be downloaded when selected and may cause the Main board to become inoperative if the incorrect file was selected.

Accessing the Host Diagnostic Screen Use the Host Diagnostic screen to investigate the signal quality of a problem channel. 4) Press the (1) Key 5 to 8 times. 1) Place Television on the digital channel that ) g may be showing problems. 2) Bring up the Customer’s Menu. Highlight “CHANNEL”. The Host Diagnostics screen appears. DTV SNR: Digital Television Signal to Noise Ratio Over the Air: 8VSB (Above 20 is good) Cable Digital: QAM 64 (Above 24 is good) Cable Digital: QAM 256 (Above 30 is good) 18 May 201 50PV450 1 Plasma . 3) The “CHANNEL” Menu appears. Press “ENTER” on the remote.

Accessing the Service Menu To access the Service Menu. 1) You must have either Service Remote. 4) Enter the Password. Enter. 0000 te . Note: If 0000 does not work use 0413. ) Note: A Password is required to enter the Se ce e u Service Menu. 105-201M MKJ39170828 May 201 50PV450 1 Plasma . ) p/n 105-201M or p/n MKJ39170828 2) Press “In-Start” 3) A Password screen appears.

Bass EQ 8. EPA 3. : 50PV45*-U* V3. DTV SNR 11. AREA OPTION : 2. SYNC LEVEL 10.05(0x05) RGB : OK YPbPr(SD) : OK YPbPr(HD) : OK EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK) Intelligent Sensor Software Version Country Group : 0. Software Version Unit’s Total Time To Reset press “In Stop” MODEL S/W VER UTT ADC CAL. AUTO TEST 5.0 :2 Sensor V0. POWER ERROR HISTORY 6 USA ON 9600 ON ON ON 20 May 2011 50PV450 Plasma . TOOL OPTION : 1. BAUD RATE 6.04. POWER OFF HISTORY 4.50PV450 Service Menu First Page Bring up the Service Menu using the Service Remote And pressing “In-Start” enter password 0413. CHANNEL MUTE 9. AUDIO EQ 7.

50PV450 Power Off History MODEL S/W VER UTT ADC CAL. SYNC LEVEL 10.05(0x05) POWER OFF HISTORY LAST HISTORY1 LAST HISTORY2 LAST HISTORY3 LAST HISTORY4 LAST HISTORY5 AC DET OFF NO SIGNAL OFF NO SIGNAL OFF ------------------------- RGB : OK YPbPr(SD) : OK YPbPr(HD) : OK EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK) : 0. : 50PV45*-U* V3. CHANNEL MUTE 9. EPA 3. AUDIO EQ 7.0 :2 Sensor V0. Bass EQ 8. DTV SNR 11.04. POWER ERROR HISTORY 6 USA ON 9600 ON ON ON RCU OFF KEY OFF 2HOUR OFF NO SIGNAL OFF AC DEC OFF 5VMNT OFF TVLINK OFF CLEAR ALL : : : : : : : 0 0 0 2 1 0 0 21 May 2011 50PV450 Plasma . POWER OFF HISTORY 4. TOOL OPTION : 1. AUTO TEST 5. AREA OPTION : 2. BAUD RATE 6.

AREA OPTION : ON 2.04.0 :2 Sensor V0. : 50PV45*-U* V3. POWER ERROR HISTORY DTV SNR DTV SNR : 33 Signal to Noise Ratio 8VSB (Above 20 is good) QAM 64 (Above 24 is good) QAM 256 (Above 30 is good) 22 May 2011 50PV450 Plasma .50PV450 DTV SNR Screen MODEL S/W VER UTT ADC CAL. BAUD RATE ON 6. AUTO TEST 9600 5. POWER OFF HISTORY 4. CHANNEL MUTE 9. DTV SNR Cursor Right 11.05(0x05) RGB : OK YPbPr(SD) : OK YPbPr(HD) : OK EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK) : 6 0. EPA 3. AUDIO EQ ON 7. SYNC LEVEL Highlight and 10. TOOL OPTION : USA 1. Bass EQ ON 8.

: 50PV45*-U* V3. DTV SNR 11.05(0x05) LAST HISTORY1 LAST HISTORY2 LAST HISTORY3 PFC_DET Error 5V OVP 5V UVP 17V OVP 17V UVP M5V OVP M5V UVP VS OCP VS OVP VS UVP VA OCP VA OVP VA UVP CLEAR ALL VA UVP VS OCP ------------0 0 0 0 0 0 0 1 0 0 0 0 1 RGB : OK YPbPr(SD) : OK YPbPr(HD) : OK EDID : RGB(OK) HDMI(1:0K 2:0K 3:OK) : 0. SYNC LEVEL 10. EPA 3. AUTO TEST 5. CHANNEL MUTE 9. TOOL OPTION : 1. AUDIO EQ 7. AREA OPTION : 2.50PV450 Power Error History MODEL S/W VER UTT ADC CAL. POWER ERROR HISTORY 6 USA ON 9600 ON ON ON 23 May 2011 50PV450 Plasma .0 :2 POWER ERROR HISTORY Sensor V0. Bass EQ 8.04. BAUD RATE 6. POWER OFF HISTORY 4.

press the Cursor Right key. ADC CALIBRATION 1. 1MIN TIMER CONTROL 12. Phase Noise Control 11. 2/B ADJUST 4. Over Modulation Control 17. EDID data is downloaded. Touch Sensitivity Setting 16. EDID D/L 5. DEBUG MODE 9. MODULE CONTROL 8. UART DOWNLOAD 7. ADC ADJUST 2. EDID D/L HDMI1 OK OK OK OK OK : ON : : : : : : : OFF ON OFF OFF 20 OFF 0 HDMI2 HDMI3 HDMI4 RGB START : 1 : OFF 24 May 2011 50PV450 Plasma .50PV450 Adjust Menu: Downloading EDID Data 1) Press “ADJ” key. PLL Tracking Speed 15. DVI/HDMI Switch 14. Atten RF Signal 3) In the EDID D/L screen. Password is required 2) Scroll down and select item 4 EDID D/L 0. 15Min Forced Off 10. 2HOUR OFF 6. SUB B/V ADJUST 3. Lip Sync Adjust(DTV) 13.

PS Mode 4. UART DOWNLOAD 7. 2HOUR OFF 6. Rom Download 35. DPS Control 5. Gama 3. 2. DVI/HDMI Switch 14. PLL Tracking Speed 15. ADC CALIBRATION 1. Touch Sensitivity Setting 16. AV PC Mode 1. Lip Sync Adjust(DTV) 13. PC ON. Press the right cursor key once and 5 seconds later the pix appears. 0. Atten RF Signal Must leave Adj. DEBUG MODE 9. ISM Control 2. Phase Noise Control 11. 0. Menu and return to update Temp. highlight and cursor right. MODULE CONTROL 8. 1MIN TIMER CONTROL 12. Module Name Module Rom Ver. Item 7 is the Module Control. 25 May 2011 50PV450 Plasma . 15Min Forced Off 10.5 Celsius 50R3 50R3_3DA1E0 : : : : : : AV AUTO 0 13 OFF OFF Temperature of the Panel Software Version AUTO. Over Modulation Control 17. 2/B ADJUST 4. OFF 1. ADC ADJUST 2. 3 Fixed ON ON : 1 : OFF ROM Download when changed to ON blacks out the screen. MODULE CONTROL : ON : : : : : : : OFF ON OFF OFF 20 OFF 0 Module Temp. EDID D/L 5.50PV450 Adjust Menu: Module Control Shows Control Board Information Press the “ADJ” key on the service remote to bring up the Adjust Menu then enter the password. SUB B/V ADJUST 3.

MODULE CONTROL 8. PLL Tracking Speed 15.50PV450 Lip Sync Screens 0. Phase Noise Control 11. UART DOWNLOAD 7. 15Min Forced Off 10. 26 May 2011 50PV450 Plasma . Left to decrease. 2HOUR OFF 6. 2/B ADJUST 4. Over Modulation Control 17. Atten RF Signal : ON : : : : : : : OFF ON OFF OFF 20 OFF 0 : 1 : OFF Use the Right or Left cursor key to change. ADC ADJUST 2. EDID D/L 5. DEBUG MODE 9. Right to increase. SUB B/V ADJUST 3. Touch Sensitivity Setting 16. DVI/HDMI Switch 14. ADC CALIBRATION 1. 1MIN TIMER CONTROL 12. Lip Sync Adjust(DTV) 13.

6mm Weight: 27 May 2011 50PV450 Plasma .62mm 15-3/4" 400mm Model No.50PV450 Dimensions There must be at least 4 inches of Clearance on all sides 46-5/16" 1176.8mm 30-5/16" 769.02mm 23-1/8" Center Center 588. Label 28" 711.01mm 5-15/16" 135mm 15-1/8" 384mm Center 14" 355.2 Watts (Stand-By) 65.6mm 15-3/4" 400mm 2" 50.4 lbs without Stand 11-3/8" 289.2mm Remove 4 screws to remove stand for wall mount 7-3/16" 182mm 2-5/16" 58.5 lbs with Stand 60. Serial No.42mm 20-1/2" 520mm Max Watts 270W Power Consumption: Typical: 145W <0.

the layout of the printed circuit boards and be able to identify each board. Upon completion of this section the Technician will have a better understanding of the disassembly procedures. Layout and Circuit Board Identification of the 50PV450 Advanced Single Scan Plasma Display Panel Panel.DISASSEMBLY SECTION This section of the manual will discuss Disassembly. board 28 May 201 50PV450 1 Plasma .

(The Stand does not need to be removed). PAY CLOSE ATTENTION TO THE TYPE.Removing the Back Cover Caution: Back is metal. SIZE AND LENGTH Of the screws when replacing the back cover. Improper type can damage the front. 29 May 201 50PV450 1 Plasma . it has sharp edges To remove the back cover remove the 29 screws cover. Indicated by the arrows.

Circuit Board Layout FPC F Identifying the Circuit Boards Panel Voltage and Panel ID Label Y-Drive Upper FPC FPC FPC FPC FPC FPC FPC FPC C Z-SUS Power Supply (SMPS) Y-SUS Y SUS Z-SUB Control Main Board M i B d Y-Drive Lower TCP Heat Sink AC In FPC FPC Left “X” Center “X” Right “X” Side Input (part of main) IR/LED Board Soft Touch S ft T h Keypad Invisible Speaker Invisible Speaker 30 April 201 1 50PV450 Plasma .

ASLGB 50Inch 1920X1080) P101 p/n: EBR69839101 Z-SUB Board p/n: EBR71728001 P102 P811 P218 P214 P210 P215 P111 P112 P121 P221 P211 P212 P213 p/n: EBR69839201 SMPS POWER SUPPLY Board p/n: EAY62171101 Top row Odd Back row Even P103 Z-SUS Board P203 P201 p/n: EBR71727901 P204 P205 P201 P206 P101 P102 P103 P104 Y-SUS Board p/n: EBR69839001 P202 P201 SC101 P813 L N P102 n/c P217 P216 P213 P102 P203 P105 P101 P2 LVDS P202 CONTROL Board P31 P104 AC In P701 P301 P704 P801 P203 P203 Y-DRIVE LOWER Board p/n: P102 EBR71727801 P204 p/n: EBU60952917 EBR72942909 MAIN Board P121 P100 P201 P101 LEFT X Board p/n: EBR71728101 P202 P203 P204 P110 P120 P320 P205 p/n: EBR71728401 P202 P310 CENTER X P321 P204 P205 P320 P310 P201 P202 RIGHT X Board p/n: EBR71728501 P203 P204 P205 P201 P100 P203 FT IR J1 IR Front “Soft Switch” Key Pad Speakers (Front Right) p/n: EAB62028901 p/n: EBR72650101 Speakers (Front Left) p/n: EAB62028901 31 May 2011 50PV450 Plasma .50PV450 Connector Identification Diagram Y-DRIVE UPPER Board PANEL p/n: EAJ61527904 (PDP50R30000.ASLGB 50Inch 1920X1080) p/n: EAJ61527931 (PDP50R30000.

Remove the 7 screws holding the SMPS in place. -Vy and Z-bias as well. Behind each board are Rubber pieces that act as a cushion. Switch Mode Power Supply Board Removal Disconnect the following connectors: P811. Remove the 3 screws holding either of the Y-Drive Boards in place. When replacing. They may make the board stick when removing. ll Note: The Y-SUS does not come with the connectors Board Standoff Y-Drive Boards Removal between the Y-SUS and Y-Drive Disconnect the following Flexible Ribbon Connectors P101~P104 and/or P201~P204: Disconnect the following Connectors P213 and P121/P221 by pressing in on the locking mechanism and lifting upward. be sure to readjust the Va/Vs voltages in accordance with the Panel Label. Do not run the set with these connectors removed. -Vy and Z-Bias as well. 213 Remove the 9 screws holding the Y-SUS in place. re-confirm VSC. Remove the board. When replacing. be sure to readjust the Va/Vs voltages in accordance with the Panel Label. P813 and SC101. Confirm VSC. P218. Remove the Y-Drive Board. P215. Remove the Y-SUS board by lifting up slightly and the carefully unseating connectors P214. Y-SUS Board Removal Note: The Y-SUS does not come with the connectors between the Y-SUS and Y-Drive Disconnect the following connectors: P218 P210 and Ribbon Cables P102 and 213. The board must be lifted slightly to clear these collars. Also. 32 May 201 50PV450 1 Plasma . Note: Y-SUS. P217 and P218 by sliding the Y-SUS to the right while gently prying the connectors apart. Do not run the set with P213 or P121/P221 removed. Z-SUS and Y-Drive Boards are mounted on board stand-offs that have a small collar. Lift up slightly.Disassembly Procedure for Circuit Board Removal Note: Remove AC Power before doing any circuit board removal procedures. then slide Collar to the left while gently prying the connectors apart.

Main Board Removal Remove connectors: P701 LVDS (flip the locking tab upward and pulling out the ribbon cable). Remove the 3 screws holding the board in place.Disassembly Procedure for Circuit Board Removal (Continued) Z-SUS Board Removal Disconnect the following connectors: P203 and P201 by lifting up the locking mechanism and unseating. lifting them up slightly and pulling the FPC out of the connector. Z-SUB Board Removal Disconnect the following connectors: P101. (Note: Chocolate piece behind upper left of board. P205 and P206 from the Z-SUB board and remove the board. P105. place. and P801. P102 and P103 by pulling the locking mechanism to the right and remove the flexible ribbon cables. Front IR / Key Pad / Intelligent Sensor Board Front IR / Intelligent Sensor and Key Pad Board: (Not Removable) attached to front glass. P704. LVDS P2 P105 and P101 P102 P104 Remove the 4 screws holding the Control board in place Lift up and P101. be sure to readjust the Va/Vs voltages in accordance with the Panel Label. P301. move to new board). Remove the 7 screws holding the board in place. Lift up slightly to clear the screw stand-offs and pull the Z-SUS to the left to unseat P204. -Vy and Z-bias as well. there i a d th Main b d th is decorative metal around th b tt ti t l d the bottom l ft side th t must b removed. P102. 33 May 201 50PV450 1 Plasma . Lift the board up slightly and slide to the right while unseating P204. P205 and P206. Control Board Removal Remove the following ribbon cables by flipping the locking tab upward and pulling out the ribbon cables. Confirm VS. Note: After removing the M i board. Remove the board. P2. When replacing. P31 LVDS. R l left id that t be d Release th the metal tabs that go through the Main board to remove the piece. P104. Remove the Z-SUB board. Remove the 4 screws holding the Main board in place and Remove the board.

(Note: The top screws were removed when the back was taken off). Make sure to use at least two people for this process so as not to flex the panel glass. removed) To remove the heat sink. Note: There is a Left and a Right brace. A. Remove the Stand (4 Stand Screws were removed during back removal). Remove the 13 screws holding the Heat Sink. E. Remove the 5 screws holding the defective X-Drive board in place. Refer to next 3 pages for disassembly and precautions. Also. lift up to release the tacky Chocolate (heat transfer material) and slide the heat sink to the left to clear the connector wires on the right side. (Warning: Never run the set with this heat sink removed). Note: There may be pieces of conductive tape that may need to be removed. Remove the Back Cover. Remove the Vertical support Braces.X Drive Circuit Board Removal Remove AC and Lay the Television down carefully on a padded surface. (3 Screws per/bracket) 1 Plastic tap thread and 2 Metal thread. Recheck VA / VS / VSC / -VY / Z-Bias. C. pp (5 ) p Remove the Stand Metal Support Bracket ( Screws) 2 Plastic tap thread and 3 Metal thread. 34 May 201 50PV450 1 Plasma . CENTER AND RIGHT REMOVAL: Disconnect all TCP ribbon cables from the defective X-Drive board and all other Ribbon cables going to the b d th board. X-DRIVE LEFT. Remove the board. Reassemble in reverse order. note that there are several pieces of Chocolate heat transfer material attached all the way across the underside of the heat sink. B. D.

Getting to the X Circuit Boards Stand B k t Bl St d Bracket Blowup D Left D Right Warning: Never run the TV with the TCP Heat Sink removed Ground Wire E Heat Sink C B Remove the tape. 35 May 201 50PV450 1 Plasma .

It may stick. Disconnect connector P121 Va from the Y-SUS to Left X Only Disconnect Va from Left to Center and Center to Right X Boards P120 to P220 Left to Center X P221 to P320 Center to Right X Carefully lift the TCP ribbon up and off.Left . P110 P210 P310 Are all the same Remove tape (if present) and Gently pry the locking mechanism upward and remove the ribbon cable f from the connector. Center and Right X Drive Connector Removal From the Control Board to the X-Boards. There may be tape on these connectors connectors. Gently lift the locking mechanism upward on all TCP connectors Left X: P201~205 L ft X P201 205 Center X: P201~205 Cushion (Chocolate) Right X: P201~205 And pull the TCP from the connector. be careful not to crack TCP stick TCP. (See next page for precautions) Removing Connectors to the TCPs. TCP Flexible ribbon cable connector 36 May 201 50PV450 1 Plasma .

TCP (Tape Carrier Package) Generic Removal Precautions Lift up the locking mechanism as shown to p g release the ribbon cable.) Separate the TCP Ribbon Cable from the connector as shown. be Very Careful when lifting up on the TCP ribbon cable cable. (The Lock can be easily damaged. Tab Tab Chocolate 37 May 201 50PV450 1 Plasma . They have t b lift d up slightly to pull h to be lifted li htl t ll the Ribbon Cable out. Note: TCP is usually stuck down to the Chocolate heat transfer material. Fil b il d d Handle with care. TCP Film can be easily damaged. The TCP Ribbon Cable has two small tabs on each side which help secure it into the connector. and needs to be handled carefully.

Center and Right X Drive Removal Remove the screws indicated from the X-Board being removed. All X-Boards pass R G B signals to 5 TCP’s across the bottom of the panel. G. TCP s panel 38 May 201 50PV450 1 Plasma . R.Left.

The technician should then be able to troubleshoot a circuit board failure. Control Board. At the end of this Section the technician should understand the operation of each circuit board and how to adjust the controls.CIRCUIT OPERATION. Y-SUS Board and the Z-SUS Board. Main Board and the X Drive Boards. Z-SUS Board. TROUBLESHOOTING AND CIRCUIT ALIGNMENT SECTION 50PV450 Plasma Display This Section will cover Circuit Operation. Alignment of the Power Supply. replace the defective circuit and perform all necessary adjustments. Y-SUS Board. Troubleshooting of the Power Supply. 39 May 201 50PV450 1 Plasma . Y-Drive Boards.

3V FPCs Speakers 3. Va Note: Va not used by Y-SUS only fused and routed to the X-Board SMPS Board AC Det and Error Not Used SK101 P813 AC Input Filter Set in Stand By: STB +3.3V Va P210 P232 3. AC Det. Va.1V SMPS TURN ON SEQUENCE Step 1: RL ON: 17V. Va and M5V to Y-SUS.77V. 18V Scan Data. 17V to Main Board Vs. FG P201 Y-SUS Board P217 Floating Gnd (FG) Y-Scan P216 Floating Gnd (FG) Y-Scan P213 Scan Data.3V P100 P320 P310 IR.47V Run: +STB 5.50PV450 Signal and Voltage Distribution Block Y Drive Upper FPCs P101 FG Voltages measured from Floating Ground P214 Floating Gnd (FG) FG10. -VY Clk. Vs.3V RUN 5V_MST Turn On Commands Out Operational voltages In. Clk P203 P102 P201 P211 P202 P212 P203 P213 P204 M5V Logic Signals To Y-SUS and Y-Drive P105 P2 18V / M5V Z Drive Control Signals P103 P202 18V / M5V Note: 18V not used by Control CONTROL Board P31 P101 P104 P102 Z-SUB Display Enable P701 LVDS Video STBY/RUN STBY_3. When VS arrives: VSC. Error. +5V.3V Va 3. Vs Z-Drive FPCs Z-SUS Board P101 P102 P103 P201 P101 P102 FPCs P221 FG5V When M5V arrives FG10.9V. P203 P301 3.AC_Det.47V) SMPS OUTPUT VOLTAGES IN RUN STBY_5V. Error. Sustain Va MAIN Board RGB Logic Signals 3.3V RGB Logic Signals 3.9V P215 Floating Gnd (FG) Y-Scan P218 P113 P811 P203 SMPS OUTPUT VOLTAGES IN STBY STBY_5V (3. Step 2: M_On: M5V. Display Panel Horizontal Electrodes Sustain Vs P102 P111 P103 P112 P104 FG5V P121 M5V. +5V.3V P704 P801 Y Drive Lower Display Panel Horizontal Electrodes Reset. FG23. . Intelligent Sensor P101 Soft Touch Keys X-Board-Left P122 P110 P120 P220 P211 P311 P331 X-Board-Center P221 X-Board-Right P101 P102 P103 P104 P105 P301 P302 P303 P304 P305 P301 P302 P303 P304 P305 Display Panel Vertical Address (Colored Cell Address) 40 May 2011 50PV450 Plasma .

Va. (12) Panel Model Name (13) Max. 41 May 201 50PV450 1 Plasma . (4) Adjusting Voltage DC.Panel Label Explanation (1) (2) (3) (4) (5) (6) (7) (10) (11) (12) (13) (14) (15) (8) (9) (1) Panel Model Name (2) Bar Code (3) Manufacture No. Watt (Full White) (14) Max. Volts (15) Max Amps Max. Vs (5) Adjusting Voltage (Set Up / -Vy / Vsc / Ve / Vzb) (6) Trade name of LG Electronics (7) Manufactured date (Year & Month) (8) Warning (9) TUV Approval Mark (Not Used) (10) UL Approval Mark (11) UL Approval No.

Adjustment Notice All adjustments (DC or Waveform) are adjusted in WHITE WASH. VA (Always do first) 2) Y-SUS: Adjust –Vy. C 1) SMPS. Y-SUS or Z-SUS board is replaced. the Voltage Label MUST be followed. Set-Down The Waveform adjustment is only necessary 1) When the Y-SUS board is replaced 2) When a “Mal-Discharge” problem is encountered 3) When any abnormal picture issue is encountered Remember. Select “Options”. Check Va/Vs since the SMPS does not come with new panel 3) A Picture issue is encountered 4) As a general rule of thumb when ever the back is removed ADJUSTMENT ORDER “IMPORTANT” DC VOLTAGE ADJUSTMENTS C O G S S 1) POWER SUPPLY: VS. 2) Panel is replaced. It is critical that the DC Voltage adjustments be checked when. VSC 3) Z-SUS: Adjust Z-Bias (VZB) WAVEFORM ADJUSTMENTS 1) Y-SUS: Set-Up. 42 May 201 50PV450 1 Plasma . it is specific to the panel’s needs. Customer’s Menu. select “ISM” select “WHITE WASH”. Power Supply Set-Up -Vy Vsc Ve ZBias Panel “Rear View” All label references are from a specific panel panel. They are not the same for every panel encountered.

(It may vary in your specific model number). • DC Voltages developed on the SMPS • Adjustments VA and VS. for the correct voltage levels for the VA and VS supplies as these voltages will vary from Panel to Panel even on the same Model. On the following pages. SMPS P/N EAY62171101 Check th ilk Ch k the silk screen label on th t center of th P l b l the top t f the Power S Supply b d t id tif th correct part l board to identify the t t number. f th P t ti t bl h ti th Switch Mode P S l Upon completion of the section the technician will have a better understanding of the operation of the Power Supply Circuit and will be able to locate test points needed for troubleshooting and alignments. we will examine the Operation of this Power Supply.SWITCH MODE POWER SUPPLY SECTION This S ti Thi Section of the Presentation covers troubleshooting the S it h M d Power Supply. 43 May 201 50PV450 1 Plasma . Always refer to the Voltage Sticker on the back of the panel. located at the upper Center.

Switch Mode Power Supply Overview SMPS p/n: EAY62171101 The Switch Mode Power Supply Board Outputs to the : VS Drives the Display Panel’s Horizontal Electrodes. Use “Full White Raster” 100 IRE VS VA VR901 VR501 44 May 201 50PV450 1 Plasma . AC D t and E D t Main Board 17V 5V Adjustments There are 2 adjustments located on the Power Supply Board VA and VS. STBY 5V Microprocessor Circuits Audio B+ Supply. fused then to the X-Boards. Used to develop Bias Voltages on the Y-SUS. Tuner B+ Circuits Signal Processing Circuits AC_Det d Error_Det. (Not used by Y-SUS). All adjustments are made referenced to Chassis Ground. Z-SUS Boards. Y-SUS Board VA M5V Y-SUS Delivers VS to Z-SUS Board VS Drives the Display Panel’s Horizontal Electrodes. p g . Primarily responsible for Display Panel Vertical Electrodes. The M5V is pre-adjusted and fixed. To Y-SUS.

D102 RL103 D101 F101 10A/250V P813 J63 J26 5. AC In P701 n/c 45 May 2011 50PV450 Plasma .A.0A STBY5V (5V) = 1A VS 201~207V = 1.8A 17V= 1A 5.6A VA 55V = 2.84V 2.02V 5. Note b: The M-On command turns on M5V.53V Gnd 2.28V 4.44V a 5.A.14V Gnd 4. Va and Vs.46V Gnd Gnd a 17V 0V e VS Diode Gnd Open 3.13V Gnd 3. the power supply turn on automatically. Note d: AC Det line is not used.73V Board Connected or 0.1V = 3. If opened.1V Open 2.17V Gnd 17V Note a: The RL_On command turns on the 17V. / 130 Max Watt : 360 W (Full White) VS Adj VR901 F801 4A/250V VA P813 "SMPS" to P301 "Main" Pin 18 17 16 15 13-14 9-12 8 5-7 3-4 1-2 Stby Gnd b M_On 0V ad AC_Det 0V a RL_ON 0V Stby_5V 3.1V STBY 390V Run Label Auto_Gnd VA Adj VR502 Hot Ground F302 2.1V 17V Note c: The Error Det line is not used in this model.72V Disconnected VA TP VS TP P811 Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.06V 3.0A M5V (5.50PV450 SMPS Layout Drawing Example Panel Label: P811 1) VS 2) VS 3) n/c 4) Gnd 5) Gnd 6) VA 7) M5V VS or VA Diode Check Open with Board Disconnected or Open with Board Connected M5V Diode Check 0.06V F302/F801 160.1V) = 2.5A/250V POWER SUPPLY p/n: EAY62171101 CURRENT LABEL Input: 100~240V 50/60Hz 4.28V 5. Note e: Pin 18 is grounded on the Main. +5V.5A PDP Module MAX 360W Run Gnd 3.47V Gnd Gnd ac Error_Det 3. Error_Det and AC_DET. / -190 / 150 / N.1V 0.

1V Stby 390V Run 2.1V Stby 390V Run 4Amp/250V SMPS p/n: EAY62171101 VS Source VS VR901 VA Source VA VR501 Fuse F302 160.Power Supply Circuit Layout P811 To Y-SUS Fuse F801 160. 5V Source RL103 Main Fuse F101 10Amp/250V P701 n/a AC Input SC 101 To MAIN P813 46 May 201 50PV450 1 Plasma .5Amp/250V Bridge Rectifiers 17V Source PFC C Circuit STBY 5V.

2V) on M_ON Line to the SMPS at P813 Pin ) 17 which is sensed by the Controller IC701. (VA pins 6 and VS pins 1 and 2) Note: The Va is fused (FS203) on the Y SUS then routed out P203 pins 4 5 to the X-Board 2). meaning it turns on the power supply via commands sent from the Main board. When RL_ON Wh RL ON arrives.14V). turning on the M5V line and outputs at P811 pin 7 to the Y-SUS board.9V RUN).Power Supply Basic Operation AC Voltage is supplied to the SMPS Board at Connector SC101 from the AC Input assembly. it outputs a high (2. The 17V (17V) Audio supply outputs to the Main board at P813 pins 1 and 2 and used for Audio processing.87V STBY and 4. The RL-ON command also turns on the 17V (Audio B+) which is also sent to the Main Board. When the Microprocessor (IC1 on the Main Board) receives a “POWER ON“ Command from either the Power button or the Remote IR Signal.47V RUN 5. The next step is for the Microprocessor on the Main Board to output a high ( p p p g (3.4V) called RL_ON at Pin 15 of P301 to P813 on the SMPS. In this state. th run voltage +5V source b i the lt becomes active and i sent t th M i B d via P813 (+5 1V at ti d is t to the Main Board i (+5. the TV will attempt to turn on. routed to the two Bridge Rectifiers D101 and D102 which then route the primary voltage to the PFC circuit (Power Factor Controller). and sent to P301 to the Main Board. AUTO GND Pin 18 of P813: This pin is grounded on the Main board. (Note there is no VS On Command in this set).1V t pin 5. The (Error Det) from the SMPS Board to the Main Board can be measured at pin 8 of P813 (2. Vs is routed out of the Y-SUS P218 pins 4-5 to P203 on the Z-SUS where it is fused by FS201. This command g g ( ) causes the Relay Circuit to close Relay RL103 bringing the PFC circuit up to full power by increasing the 160V standby to 390V run which can be read measuring voltage at Fuse F302 and F801 (390V) from “Hot” Ground.1V source supply (which during run measures 390V measured from the primary fuses F801 and F302). The Controller (IC701) also uses the M_ON line to turn on the VA and the VS supplies. but will shut right back off. the Controller (IC701) works in the normal mode. This supply is also used to generate all other voltages on the SMPS SMPS. VS is output at P811 to the Y-SUS board P210. by rectifying a small sample of the A/C Line and routed to the Controller (IC701) where it outputs at P813 pin 16 (4. When it is grounded. the Controller turns on the power supply in stages automatically. When AUTO GND is floated (opened). A load is necessary to perform a good test of the SMPS if the Main board is suspect. If missing. but it is not used. it pulls up and places the Controller (IC701) into the Auto mode.4V) called AC_DET. 6 and 7). 47 May 201 50PV450 1 Plasma . Standby 5V is developed from 160. Y-SUS 4-5 X Board Left. AC Detection (AC Det) is generated on the SMPS. The STBY5V (standby) is B+ for the Controller chip on the back of the SMPS board (IC701) and output at P813 pins 13 and 14 then sent to the Main board for Microprocessor (IC600) operation (STBY 3.

3VST 5 Error Relay Det.1V In Run (Relay On) Primary side is 390V AC In (SMPS) Stand By 5V Reg STBY 3. Mutes Audio Not Used 17V Audio IC801 Multiple Regulators 7 8 At point 3 TV is in Stand-By state.9V Floating Gnd 7 18V / M5V Y DRIVE Upper 7 5VFG Reg 5VFG Y DRIVE Lower M5V 7 3. It is Energy Star Compliant. On Microprocessor M_On 7 4 2 3 MAIN Board Power On Remote or Key Pad X Board Va Left 8 2 4 Front IR Board X Board Va Center 8 X Board Right STBY 5V IC1 Soft Touch Key Pad Power Key Remote Power Key 48 May 2011 50PV450 Plasma . Stand By Error Det. AC Det. 5V 5V 17V M5V 7 CONTROL M5V 18V 7 7 7 3. Less than 1 Watt 18V / M5V 7 10.3V Reg 6 2 6 RL On 6 6 Y-SUS M_On 8 Z-SUS 10.14V RL On 3rd Relays 9 Vs Reg Vs 1 AC Det +5V Regulator RL On 1st 7 M5V Reg M5V Va Vs 5 17V Reg 2nd 8 Va Reg 8 Va 7 9 Vs 9 Vs 9 Vs AC Det.3V 7 7 Va 8 3.50PV450 Television Turn On Sequence F302 F801 In Stand-By Primary side is 160.3V 7 5VFG 3.9VFG Reg 18V Reg 5 Error Det.3V Reg IC302 Reset C108 & R62 3.47V RUN 5.

Y SUS X Drive (3) Vs: Voltage for Sustain sent to the Y-SUS and then to the Z-SUS) used for amplification voltage driving the horizontal electrodes. The FG10 9V is routed to the upper Y-Drive board and Z-SUS FG10. it develops 2 additional voltages.8V for internal use and 3. The Reset circuit (C108 and R62) is energized when 3.4V when the set turns on by the Relay-On Command. When the M5V from the SMPS through the Y-SUS arrives on the Control board. This also starts the ( pp _ y )p p 12Mhz Oscillator (X1) however.3V which is routed down to the each X-Board for each TCP’s low voltage processing voltage. 49 May 201 50PV450 1 Plasma . AC Det is not used in this set.9V regulated down to FG5V and used by both the upper and lower Y-Drive boards for the low voltage processing voltage.Turn On Sequence Text The text below is related to the previous page. The 18V is routed through the Control board to the Z-SUS. (2) Va: (Voltage for Address) For amplification voltage for the TCPs driving the vertical electrodes. On the Y-SUS. when M5V arrives. Lower Y-Drive and Z-SUS Board. the control develops 3. (Voltage routed through the Y-SUS then to the X-Drive boards. STBY 5V (Stepped down to 3.3V_ST by IC302) powers on the Microprocessor IC1 on the Main board. it develops 3 voltages: FG23V. When Vs arrives on the Y-SUS. At power on the 1st output from the Microprocessor (IC1) is the Relay On command called (RL-ON) which turns on the following SMPS supplies: +5V for Video Processing 17V for Audio Amplification.3V and 1. however if missing it will Mute the Audio. Y-SUS Board. The SMPS (+5V) creates a signal called (ERROR DET) and is sent to the Main Board but it is not used by the Main board. On the Main board the 17V is sent to the Audio Amp (IC801).9V (FG=Floating Ground) and 18V. but rises to 4. (The M5V is routed through the Y-SUS to the Control Board then to the Z-SUS and through the Y-SUS to the Lower Y-Drive).3V_ST arrives. FG10. The 2nd output from the Microprocessor is the (M_ON) command which turns on (3) supplies: (1) M5V (Monitor 5V): For the Control Board. the Microprocessor is not functional until after it is Reset. AC Det is 0V when the set is in Stand-By. -Vy and VSC which are adjustable.

50 May 201 50PV450 1 Plasma . / 130 Max Watt : 360 W (Full White) VA Voltage VS Voltage Vs Adjust: Place voltmeter on VS TP. Va Adjust: Place voltmeter on VA TP. Adjust VR901 until the reading j g matches your Panel’s label.A. / -190 / 150 / N.Power Supply Va and Vs Adjustments Important: Use the Panel Label Not this book for all voltage adjustments adjustments. Adjust VR502 until the reading j g matches your Panel’s label. Use Full White Raster “White Wash” Va TP or P811 Pin 5 Vs TP or P811 Pin 1 or 2 Example Voltage Label Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.A.

attach one end to Vs and the other end to ground. Note: To be 100% sure.0A M5V (5. Pins 100W 1 or 2 P811 VS VS VS n/c Gnd Gnd Va M5V VA TP VS TP F801 4A/250V Note: Always test the SMPS under a load using the 2 light bulbs. 51 May 2011 50PV450 Plasma . VS Adj VR901 CURRENT LABEL Input: 100~240V 50/60Hz 4. 1) With Main Board connected.6 and 7 for (+5.6A VA 55V = 2. If the light bulbs turn on and VS is the correct voltage.1V) = 2.8A 17V= 1A 5. AC_DET WILL NOT be present until set comes on. If this test is successful and all other voltages are generated. Abnormal operational conditions may result if not loaded. you would need to read the current handling capabilities of each power supply listed on the silk screen on the SMPS and place each supply voltage under the appropriate load.5A PDP Module MAX 360W 100W Gnd VA Adj VR502 Pins 4 or 5 Hot Ground POWER SUPPLY p/n: EAY62171101 P811 Check Pins 1 or 2 for Vs voltage Check Pins 6 for Va voltage Check Pins 7 for M5V voltage F302 2.22V) Check Pin 8 for Error Det (4.47V and will be 5.14V when the set turns on.Power Supply Static Test with Light Bulb Load Using two 100 Watt light bulbs.94V) Check Pins 13 or 14 for 5V SBY (4. but it’s not used. STBY 5V will be 3. press power.1V = 3. Any time AC is applied to the SMPS. it will Mute the Audio. Apply AC to SC101. 2) Without Main Board connected SMPS will turn on automatically. but it’s not used. you can be fairly assured the power supply is OK. allow the SMPS to run for several minutes to be sure it will operate under load.5A/250V P813 RL103 Check Pins 1 or 2 For 17V (17V) F101 10A/250V P813 AC In P701 n/c Check Pin 5.94V) Note: To turn on the Power Supply. Error line WILL NOT be present until set comes on.0A STBY5V (5V) = 1A VS 201~207V = 1.94V) Check Pin 16 for AC Det (4. If AC_DET is missing to the Main board.

T return th SMPS to the normal B di ti P500.1V) become active (Not Used). i i d To t the t th l state for this test procedure. Use the holes on the connector P500 (Main Board side) to insert the resistors and jumper lead. This Power Supply can be powered on sequentially to test the Controller Chip IC701 operational capabilities and for troubleshooting purposes. P811 (M5V pin 7) 52 May 201 50PV450 1 Plasma . (See first step A below). this pin must be grounded. By disconnecting P500 pin 18 is opened. (4. TEST CONDITIONS: Connector going to the Y-SUS P811 is disconnected. plug or resistor. (C) Add a 100Ω ¼ watt resistor from any 5V line to M_ON to make the (Monitor) M5V. (A) Ground the Auto Gnd Line (Pin 18) will allow the supply to be powered up one section at a time.Power Supply Static Test (Forcing on the SMPS in stages) WARNING: Remove AC when adding or removing any jumper. P811 (VS pins 1 and 2) and (VA pins 6) 6).06V) and Error_Det (4. Note: Leave previous installed 100Ω resistor in place when adding the next resistor. VS and VA lines operational. When the supply is operational in its normal state the Auto Ground line at Pin 18 of P813 is held at ground by the Main Board. (B) Add a 100Ω ¼ watt resistor from 5V Standby to RL_ON and the 17V and 5V Run Lines on P813 will become active Also AC-Det (4 06V) active. P500 on the Main board disconnected (coming in on P813). Connect (2) 100 Watt light bulbs in series between VS and Ground Ground.

44V 0.28V 5. Error_Det and AC_DET. Voltages and Diode Check Identification. Va and Vs.84V 2. If opened.1V Open 2.86V 0V 4.22V Gnd 17V M_ON AC Det ad a 5V 17V RL_ON STBY_5V Gnd G d Error_Det a 5. supply turns on automatically.02V 5.46V Gnd 0V Run Gnd 3.P813 SMPS Connector Identification. but shut off.47V Gnd G d 3. 53 May 201 50PV450 1 Plasma .94V 5. M-On c Note: The Error Det line is not used in this model.94V Gnd G d 4. e Note: Pin 18 is grounded on the Main. rows of pins. b Note: The M On command turns on M5V.1V Gnd a 17V a Note: The RL_On command turns on the 17V. the TV will attempt to turn on.06V 1 Label Auto_Gnd b STBY Gnd 0V 0V 0V 3.94V 0V 4. Note: This connector has two d Note: AC Det if missing. P813 Connector “SMPS" to “Main" P500 Pin 18 17 16 15 13-14 9-12 9 12 8 5-7 3-4 34 1_2 ac e P813 Diode Open Open 3.28V 4.53V Gnd G d 2. DVM in Diode Mode.13V Gnd 3.14V Gnd G d 4. Diode Mode Readings taken with all connectors Disconnected.06V 3. the power Odd on top row.17V Gnd 17V No Load 4. +5V.

P811 and SC101 SMPS Connector Identification. DVM in Diode Mode.38V 1 * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. Voltages and Diode Check Identification. SC101 AC INPUT Connector SC101 Pin Number L and N Standby 120VAC Run 120VAC Diode Mode Open P811 "Power Supply“ to Y-SUS “P210” P811 Pin 1~2 1 2 3 4~5 6 7 Label Vs V n/c Gnd Va M5V Run *201V n/c Gnd *55V 5.0V Diode Check Open O n/c Gnd Open 1. 54 May 201 50PV450 1 Plasma .

9V Used on the Y-Drive boards (Measured from Floating Gnd) FG 23. Also routed out to the Z-SUS pp ( ) M5V Supplies Bias to Y-SUS. Also. Upon completion of the Section the technician will have a better understanding of the operation of the circuit and will be able to locate test points needed for troubleshooting and alignments. FG23.Y-SUS BOARD SECTION (Overview) Y-SUS Board develops the Y-Scan drive signal to the Y-Drive boards.77V and 18V generated when M5V arrives on the board. -VY Sets the Negative excursion of Reset in the Drive Waveform VSC Sets the amplitude of the complex waveform. g • Adjustments • DC Voltage and Waveform Checks • Diode Mode Measurements Operating Voltages SMPS Supplied VA VS M5V VA supplies the Panel’s Vertical Electrodes (Routed to the Left X-Board) VS Supplies the Panel’s Horizontal Electrodes.77V Used in the Development of the Drive Waveform ( p (Measured from Floating Gnd) g ) -Vy and VSC generated when Vs arrives on the board. M5V is routed to the Lower Y-Drive for the data buffers. This Section of the Presentation will cover alignment and troubleshooting the Y-SUS Board.9V. FG10. 55 May 201 50PV450 1 Plasma . in this set. Y-SUS Developed -VY VR501 VSC VR500 V SET UP VR402 V SET DN VR401 18V Floating Ground FG 10. (From Y-SUS routed to the Control Board then Z-SUS). (Also routed to the Control Board then routed to the Z-SUS board). SET UP sets amplitude of the Top Ramp of Reset in the Drive Waveform SET DOWN sets the Pitch of the Bottom Ramp for Reset in the Waveform Used internally to develop the Y-Scan signal.

9V/23.9V Logic Logic signals needed to scan the panel Y-Drive Upper Board Distributes Receive Y-Scan Waveform FG5V Y-Drive Lower Board Receive Y-Scan Waveform Display Panel Logic signals needed to generate drive waveform and Scan the Panel 56 May 201 50PV450 1 Plasma .SMPS Distributes Vs Z-SUS Board Simplified Block Diagram of Y-Sustain Board Y-SUS Board VA Distributes Vs. Vs from SMPS Control Board Distributes VA VS Circuits generate Y-Sustain Waveform Generates Vsc and -Vy from M5V by DC/DC Converters Also controls Set Up/Down M5V Left X Board FETs amplify Y-Sustain Waveform Generates Floating Ground g 10. Va.77V by DC/DC Converters Distributes FG10. Va and M5V Distributes 18V / M5V Distributes 18V and M5V Receive M5V.Y-SUS Block Diagram Power Supply Board .

Damage will occur.9V Pins 1-2 P214 To Y-Drive Upper FS203 (VS) 6.3A/250V P218 To Z-SUS VS. VS VA and M5V Input from the SMPS P210 VSC R548 VR501 VSC VR500 -Vy P215 To Y-Drive Upper Y-Scan Y Scan Pins 9~12 Or use the Left Side of C540 Y-Scan Pins 1~4 P217 To Y-Drive Lower FS202 (M5V) 10A/125V / FS201 (VA) 4A/125V VR401 Set Dn C540 VR402 Set Up FS501 (18V) 2A/125V Y-Scan Pins 11~12 P216 To Y-Drive Lower 18V (pins 6~8) to Control for Z-SUS M5V (pins 3~5) Ribbon P213 P102 Logic Signals from the Control Board WARNING: Do not run set if P213 is removed.Y-SUS Board Layout -Vy Vy R527 FG10. P203 Va to Left X Board Pins 5~7 57 May 201 50PV450 1 Plasma .

27V DIODE 1. / -190 / 150 / N.196V 1) M5V 2) M5V 3) OC2_B 4) Gnd 5) DATA_B 6) Gnd 7) OC1_B 8) OC2_T 9) Gnd 10) DATA_T 11) Gnd 12) OC1_T 13) Gnd 14) CLK 15) STB Y-SUS EBR69839001 -Vy VSC CTRL_OE should be 0V (5V indicates and problem) P102 P102 6-8) 18V 3-5) M5V P203 P213 To run the 18V and Floating Ground 24V and 10V.74V Gnd 0.38V Open Gnd 1.1V Red lead on FG Open Blk lead on FG D511 10. Ground CTRL_OE and supply 5V to Y-SUS P203 1-2) Gnd 3) n/c 4-5) VA P213 to P213 1) M5V 2) M5V 3) OC2_B 4) Gnd 5) DATA_B 6) Gnd 7) OC_B 8) OC2_T 9) Gnd 10) DATA_T 11) Gnd 12) OC1_T 13) Gnd 14) CLK 15) STB RUN 4.68V 4.A.73V 2.96V 2.A. / 130 Max Watt : 360 W (Full White) J81 Gnd J113 CTRL_OE P216 Pins 11-12 VSCAN Pins 1-10 FGnd P216 Note With No Y-Drives: FG23.85V Gnd 1.85V Gnd 1.85V reads 23.9V VR501 VSC 10.96V 4.85V Gnd 1.85V Open Gnd 1.73V Board Connected or 1.34V FS202 (M5V) 10A / 125V D515 P215 Pins 9-12 VSCAN n/c Pin 8 FGnd Pins 1-7 VSCAN 107V AC RMS IC302 VR401 Set-Dn VScan FGnd FS501 (18V) 2A / 125V FS201 (VA) 4A / 125V P217 Pins 6-12 FGnd n/c Pin 5 VSCAN Pins 1-4 C540 P217 Left Leg C540 TP With no Y-Drive 116V AC RMS 355V p/p With Y-Drives 350V p/p 107V AC RMS Example: VR402 Set-Up Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.77V Gnd 0V Gnd 1. P214 Pins 3-12 FGnd Pins 1-2 FG10.3A / 250V +Vy R527 D502 D503 D505 190VFG 103VFG T500 P218 7-8) Gnd 6) n/c 4-5) VS 3) n/c 1-2) ER P210 7) M5V 6) VA 4-5) Gnd 3) n/c 1-2) VS P210 D512 23.73V Gnd 0V Gnd 1.9VFG J33 D504 158VFG P218 FS203 (VS) 6.77VFG D511 10.85V 1.38V Disconnected FS501 Protects 18V Creation D515 and T502 Diode Check With Board 1.38V 1.8V reads 11.28V Connected or 1.9VFG Diode Check 0.77VFG Diode Check 3.9VFG D512 18.55V Red lead on FG Open Blk lead on FG FS201 Va or FS203 Vs Diode Check reads Open with Board Disconnected or Connected FS202 M5V Diode Check reads 0.31V Disconnected D500 IC500 D501 P214 IC501 T502 VR500 +Vy VSC R548 P215 23.85V FG10.85V Referenced to Chassis Gnd 58 May 2011 50PV450 Plasma .50PZ950 Y-SUS Board Component Layout WARNING: The upper and lower Y-DRIVE Board has to be Removed Completely if P213 is pulled.

/ -190 / 150 / N.A.1/2V) 2) Adjust VSC (VR501) to Panel’s Label voltage (+/. Set screen to “White Wash”. 1) Adjust –Vy (VR500) to Panel’s Label voltage (+/.A. this is the “Heat Run” mode.VSC and -VY Adjustments CAUTION: Use the actual panel label and not the book for exact voltage settings.1/2V) VR501 VSC Adj Location: Center Top Left of board + R527 -Vy TP Location: Top Right of board 59 May 201 50PV450 1 - + VR500 -Vy Adj Plasma . / 130 Max Watt : 360 W (Full White) -Vy Voltage Reads Positive R548 VSC TP -Vy Voltages Reads Positive VSC Set should run for 10 minutes. These are DC level Voltage Adjustments j p This is just for example Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.

make sure there are no lines left to right in the screen picture. If by accident the land is torn and the run lifted.Y-Scan Signal Overview Y-Drive Upper Test Point Just above 2nd Buffer from bottom Overall signal observed 2mS/div 107VRMS 560V p/p Blanking Blanking NOTE: The Waveform Test Points are fragile. Basically any output pin to any of the FPC to the panel are OK to use. Adjustment Area X10 Sub Field Firing (600Hz) Video 60 May 201 50PV450 1 Plasma . There is another test point on the Upper Y-Drive board that can be used.

Note this TP (VS_DA) can be used as an (VS DA) External Trigger for scope when locking onto the Y-Scan (Scan) or the Z-Drive signal. This signal can also be used to help lock the scope when observing the LVDS video signals. 61 May 201 50PV450 1 Plasma .Locking on to the Y-Scan Waveform Tip YNote.

Set must be in “WHITE WASH” All other DC Voltage adjustments should have already been made. f st large signal to the right of blanking. Fig 1 shows the signal locked in at 4ms per/div. the adjustment for SET-UP can be made using VR402 and the SET-DN can be made using VR401. Remember. Fig 3: At 100us per/div the area for adjustment of SET-UP or SET-DN is i now easier t recognize. It is outlined within th W i to i i tli d ithi the Waveform.Observing (Capturing) the Y-Scan Signal for Set Up Adjustment YFig 1: Fi 1 As an example of how to lock in to the Y-Scan Waveform. It will make this adjustment easier if you use the Expanded scope “Expanded” mode of your scope. Note the 3 blanking sections. j pointed out within the Waveform The area for adjustment is p Fig 2: At 2mSec per/division. Now only two blanking signals are present present. Adjustment Area Area to expand Adjustment Area Area to p expand Blanking Area to be adjusted Blanking FIG1 4mS FIG2 2mS Expanded from above FIG3 100uS Blanking Expanded from above Area for Set Up Set-Up adjustment 345V p/p FIG4 40uS Area for Set-Dn adjustment 180 uSec 62 May 201 50PV450 1 Plasma . this is the 1 g Fig 4: At 40uSec per/division. the area of the waveform to use for SET-UP or SET-DN is now becoming clear.

(180uSec ± 5uSec) A VR402 ADJUSTMENT LOCATIONS: Center of the board.Set Up and Set Down Adjustments Y-Scan Test Point Upper Y-Drive Y Drive Set must be in “WHITE WASH” All other DC Voltage adjustments should have already been made. 63 May 201 50PV450 1 Plasma . Waveform Test Point Y-Drive Upper or Lower (Waveform TP) VR401 B SET-UP ADJUST: 1) Adjust VR402 and set the (A) portion of the signal to match the waveform above (345V p/p ± 5V) above. SET-DN ADJUST: 2) Adjust VR401 and set the (B) time of the signal to match the waveform above.

select White Wash and adjust correctly.8uSec 64 May 201 50PV450 1 Plasma . Black floor Up Up. Too Low 88.Set Up/Down Adjustments Too High or Low Set Up swing is Minimum 328V p/p Max 358V p/p Set Dn swing is Minimum 73uSec Max 196uSec Normal 180uSec This will cause The bottom of The picture to distort. remove the LVDS from Control board and make necessary adjustments. This will cause The black Portions of the Picture to Lighten. Then reconnect LVDS cable. 40V off the Floor Floor NOTE: If abnormal settings cause excessive brightness then shutdown.

TIP: Do not use C540 Left leg to adjust the Y-Scan signal. Warning: Never run the Y-SUS with P213 removed unless the Y-Drive boards are removed completely. TIP: Use C540 Left leg to check the Y-Scan signal if the Y-Drive boards are removed P/N EBR69839001 65 May 201 50PV450 1 Plasma . This Section of the Presentation will cover troubleshooting the Y-SUS Board.Y-SUS Board Troubleshooting Y-Drive YY-SUS Board develops the Y-Scan drive signal to the Y-Drive boards. The same is true for P221/P121 and the Upper Y Drive Y-Drive.

3V 0.32V 1.89V 4.29V p Open Open Open Open Open Open Open Open Gnd Open Open Open Open Pin Pi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Label L b l DATA_TOP OC1_TOP CLK STB OC1_BTM DATA_BTM OC2_BTM +18V +18V +18V M5V M5V M5V Gnd Gnd Run R 0V 1.P102 Y-SUS Board Ribbon to Control P203 Voltage and Diode Test YP102 "Y-SUS" to P105 "Control" Pin Pi 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Label L b l CTRL_OE OE SUS_UP SUS_DN SET_DN Slope_Rate_Sel Det_Level_Sel Ramp_Slope_Opt1 Run R 0.46V 2.32V 1.34V 18.32V 1 32V 1.35V 1.40V 1.02V 0. DVM in Diode Mode. 66 May 201 50PV450 1 Plasma .2V 0.34V 18.89V Gnd Gnd Diode Ch k Di d Check Open Open Open p Open Open Open Open 1.98V 18.09V 1.05V 0.40V 1.06V 0.13V 2.89V 4.40V Gnd Gnd SET_UP YER_UP YER UP Gnd YER_DN PASS_TOP DELTA_VY_DET OC2_TOP Location: Location Bottom Right of board Diode Mode Readings taken with all connectors Disconnected.02V 0.98V Diode Ch k Di d Check Open 2.06V 0.06V 0.86V Gnd 0V 1.34V 18 34V 4.11V 0 11V Gnd 0.16V 0.84V 2.

P203 Y-SUS Board to Left X-Board P121 Voltage and Diode Test YXLocation: Bottom Right of board P203 P203 "Y-SUS" to "X-Drive Left" P121 Pin 1~2 3 4~5 Label Gnd n/c Va Run Gnd n/c *55V Diode Check Gnd Open Open To Left X-Board * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode. 67 May 201 50PV450 1 Plasma .

38V To SMPS 7 * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected.P210 Y-SUS Board to SMPS P811 Voltage and Diode Test YLocation: Top Right of board P210 P210 "Y-SUS" to "Power Supply" P811 Pin 1~2 3 4~5 6 Label Vs n/c Gnd Va M5V Run *201V n/c Gnd *55V 5. 68 May 201 50PV450 1 Plasma . DVM in Diode Mode.0V Diode Check Open n/c Gnd Open 1.

t d DVM in Diode Mode.85V Gnd 1.P213 Y-SUS Board Connector to P213 Lower Y-Drive (Logic Signals) YTIP: This connector does not come with a new Y-SUS or Y-Drive. P213 P213 Y-SUS to Lower Y-Drive P213 Pin 1 2 3 4 5 6 7 8 9 10 11 12 Label M5V M5V OC2_B Gnd DATA_B Gnd OC1_B OC1 B OC2_T Gnd DATA_T Gnd OC1_T Gnd CLK STB Run 4.73V Gnd 0V Gnd 1.85V Gnd 1.38V 1.27V Diode Check 1. All readings taken from Chassis Ground Y-SUS Board 13 14 15 69 May 201 50PV450 1 Plasma .73V 1 73V 2.77V Gnd 0V Gnd 1.85V 1.96V 2.85V Diode Mode Readings taken with all connectors Di ll t Disconnected.85V Gnd 1.96V 4.74V Gnd 0.85V 1 85V Open Gnd 1.38V Open Gnd 1.68V 4. TIP: Use C540 Left leg to check the Y Scan signal if the Y Drive boards are removed Y-Scan Y-Drive Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.

P213 Y-SUS Board Connector Waveforms YNote: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.9V p/p) Pin 10 (8.67V p/p) Pin 15 (11. P213 P213 Y-SUS to L Y SUS t Lower Y D i P213 Y-Drive Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label M5V M5V OC2_B Gnd DATA_B Gnd G d OC1_B OC2_T Gnd DATA_T Gnd OC1_T Gnd G d CLK STB Pin 3 (19.67V p/p) Pin 14 (9.62V p/p) Pin 12 (9V p/p) Pin 7 (10.47V p/p) Pin 5 (8.15V p/p) All scope settings at 5mSec per/div / 5V per/div All signals taken from Chassis Ground 70 May 201 50PV450 1 Plasma .08V p/p) Pin 8 (10.

55V Red Lead on Floating Gnd Black Lead on Floating Gnd All readings from Floating Ground di f Fl ti G d Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected.P214 Y-SUS Board to Upper Y-Drive P111 Voltage and Diode Test YYLocation: Top Left of board P111 P214 P214 "Y-SUS" to "Upper Y-Drive" P111 Pin Pi 3-12 1-2 Label L b l FGnd FG10. DVM in Diode Mode.89V Diode Ch k Di d Check FGnd Open Diode Ch k Di d Check FGnd 0. 71 May 201 50PV450 1 Plasma .9V Run R FGnd 4.

DVM in Diode Mode.P215 Y-SUS Board to Upper Y-Drive P112 Voltage and Diode Test YYLocation: Bottom Left of board P112 P215 P215 "Y-SUS" to "Upper Y-Drive" P112 Pin 9-12 8 1-7 Label Vscan n/c FGnd Run 107V n/c FGnd Diode Check Open n/c FGnd Diode Check Open n/c FGnd Red Lead on Floating Gnd Black Lead on Floating Gnd All readings from Floating Ground Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected. 72 May 201 50PV450 1 Plasma .

73 May 201 50PV450 1 Plasma . DVM in Diode Mode.P216 Y-SUS Board to Lower Y-Drive P212 Voltage and Diode Test YYLocation: Bottom Left of board P212 P216 P216 "Y-SUS" to "Lower Y-Drive" P212 Pin 11-12 1-10 Label Vscan FGnd Run 107V FGnd Diode Check Open FGnd Diode Check Open FGnd Red Lead on Floating Gnd Black Lead on Floating Gnd All readings from Floating Ground g g Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected.

74 May 201 50PV450 1 Plasma .P217 Y-SUS Board to Lower Y-Drive P211 Voltage and Diode Test YLocation: Bottom Left of board P211 P217 P217 "Y-SUS" to "Lower Y-Drive" P211 Pin 6-12 6 12 5 1-4 Label FGnd FG d n/c Vscan Run FGnd FG d n/c 107V Diode Check FGnd FG d n/c Open Black Lead on Floating Gnd Diode Check FGnd FG d n/c Open Red Lead on Floating Gnd All readings from Floating Ground g g Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.

75 May 201 50PV450 1 Plasma . DVM in Diode Mode.Y-SUS Board P218 to Z-SUS P203 Voltage and Diode Test ZLocation: Top Right of board P218 P218 "Y-SUS" to "Z-SUS" P203 Pin 1~2 3 4~5 6 7~8 Label Gnd n/c +Vs n/c ER_PASS Run Gnd n/c *201V n/c *98V~102V Diode Check Gnd n/c Open n/c Open * Note: This voltage will vary in accordance with Panel Label Diode Mode Readings taken with all connectors Disconnected.

Y-SUS Floating Ground FG10.9V, FG23.77V and 18V Checks
Voltage Measurements for the Y-SUS Board
FG23.77V (Floating Ground). ( g ) Checked at Cathode of D512

Tip: M5V turns on these supplies. P201 FS202 M5V

Floating Ground checks must be measured from Floating Ground. Use pins 3 12 on P214 3~12 Note With No Y-Drives: FG23.77V reads 23.85VFG FG10.9V reads 11.2VFG

J32 10.9V

D511 FG10.9V

T502 FS201 VA D512 FG23.77V D515 FG18.34V
FG10.9V (Floating Ground). Checked at Cathode of D511. Leaves the Y-SUS board to Upper Y-Drive on P214 pins 1 and 2 18V (Chassis Ground). Checked at Cathode of D515. Leaves the Y-SUS board to Control board on P102 pins 6~8

Location

FS501 18V

J81 (CTRL_OE)

Tip: Remove board, Ground J81 (CTRL_OE) Jump any 5V supply to pin 7 of P210 or FS202 and it will turn on these supplies for test.

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Y-SUS (VSC and –Vy) Generation Checks
Voltage Measurements for the Y-SUS Board Tip: VS turns on these supplies, but Floating Gnd 10.9V, 23.77V and Chassis Gnd 18V must be running.

VSC Source Test Point. Used Y-SUS Waveform development. Checked at Cathode Side of D504. Run: 158V Diode check: Open (Black lead on FGnd) 0.49V (Red lead on FGnd) D504 Cathode VSC Source

Location

T500

D505 Cathode +Vy Source

+Vy Source Test Point. Used Y-SUS Waveform development. Checked at Cathode Side D505. Run: 190V Diode check: Open (Black lead on FGnd) 0.56V (Red lead on FGnd)

Floating Ground checks must be measured from Floating Ground. p Use pins 3~12 on P214

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Y-SUS Board Fuse Information
Locations
Board Disconnected Diode Ch k Di d Check readings di FS203 VS or FS201 Va Open Red Lead on FG Open Blk Lead on FG p (FS202) M5V 0.54V Red Lead on FG 1.4V Blk Lead on FG (FS501) 18V 0.62V Red Lead on FG 1.32V Blk Lead on FG

FS203 (VS) 6.3A / 250V

FS202 (M5V) 10A / 125V FS201 (VA) 4A / 125V

Board Connected Diode Check readings FS201 Va or FS203 Vs Open FS202 M5V 0.73V

FS501 (18V) 2A / 125V

FS501 18V 1.28V

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Y-SUS FET Identification and Location J33 P218 D S Q502 G D503 T500 D505 P214 IC501 D501 IC500 HS601 P215 D512 D515 IC302 Q609 Position Direction D610 HS601 Forward Reverse D604.Q607 Q608. (Overload) Q601.45V 0.45V ~ 0.35V ~ 0.45V Circuit No.45V ~ 0.4V ~ 0.55V 0.45V O. (Overload) T502 HS603 D511 Q602 D605 Q610 Q603 Q606 Q607 D610 P102 D609 P203 P213 79 May 2011 50PV450 Plasma P210 D500 .D605 HS602 Forward Reverse D602 HS603 Forward Reverse 0.35V ~ 0.Q612 0.L.L.5V P216 Y-SUS EBR69839001 0.45V ~ 0.Q602 0.L.35V ~ 0.55V O.55V P217 O.45V 0. Q606.Q605 Q610.35V ~ 0. (Overload) Q603.Q609 Q605 Q612 D602 C540 HS602 D608 Q608 D604 Q601 0.

pp regulates it down to FG5V for the upper and routed down to the lower Y-Drive buffers. 80 May 201 50PV450 1 Plasma . This model also does something new. Monitor 5V is sent to the Lower Y-Drive where the low voltage Data Buffer are located. The 50PV450 uses 12 Driver ICs on 2 Y-Drive Boards commonly called “Y-Drive Buffers” but are actually Gate Arrays connected to 1080 horizontal electrodes across the panel.9V and . The Y-Drive Boards receive a waveform (Y-Drive) developed on the Y-SUS board then selects the Y SUS horizontal electrodes sequentially starting at the top and scanning down the panel. Also. Scanning is synchronized by receiving Logic scan signals from the Control board. The upper Y-Drive receives FG10.Y-DRIVE BOARD SECTION Y-Drive Explained Y-DRIVE UPPER (TOP) Y-DRIVE LOWER (BOTTOM) Y-Drive Boards work as a path supplying the Sustain and Reset waveforms which are made in the Y-Sustain board and sent to the Panel through Scan Driver IC’s.

The 5VFG is also sent down to the lower Y-Drive via p pins 1~9 for the lower P121 pins 21~30 to P221 p Y-Drive buffers. The Upper Y-Drive then delivers the 5VFG to all the buffers for their low voltage signal processing circuits. P112 P121 81 May 201 50PV450 1 Plasma . The Upper Y Drive is also responsible for developing Y-Drive the FG5V operational voltage for both Drive boards.Y-Drive Upper Layout PANEL SIDE Y-SUS SIDE p/n: EBR69839101 The upper Y-Drive is responsible for driving the upper half of the panel’s horizontal electrodes with Y-Scan signals through the Panel’s Flexible printed circuits. t d You must remove the Upper Y-Drive board completely. P111 Warning: Never run the Y-SUS with just P121 di ith j t disconnected. (540 horizontal electrodes). It receives FG10.9V from the Y-SUS on P111 pins 11~12 and routs this voltage to IC191 which regulates it down to 5VFG. Can not read pins because they are covered in silicon.

63V 2.9V from the Y-SUS on P111 pins 11~12 and routs this voltage to IC191 which regulates it down to 5VFG. 5VFG D191 Anode 5VFGnd Cathode 10.Y-Drive Upper Floating Ground 5V Regulator (5VFG) Floating Ground checks must be measured from Floating Ground. Use pins 3~12 on P214 Q191 D191 Pin 1 1 3 3 IC191 (1) 5VFG (2) FGnd (3) 10.42V 2.9VFG Diode Check 0. It receives FG10.79V Red Lead on FGnd Blk Lead on FGnd Red Lead on FGnd Blk Lead on FGnd P111 The Upper Y-Drive is also responsible for developing the FG5V operational voltage for both Drive boards.9VFGnd C th d 10 9VFG d A C P112 82 May 201 50PV450 1 Plasma .19V 0.

9V FGnd Run R 4.89V FGnd Diode Ch k Di d Check Open FGnd Diode Ch k Di d Check 0.5V FGnd Red Lead on Floating Gnd Black Lead on Floating Gnd All readings from Floating Ground di f Fl ti G d Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected.P111 Upper Y-Drive to Y-SUS Board P214 Voltage and Diode Test YYLocation: Top Right hand connector P111 P214 Upper Y-Drive P111 to Y-SUS Board P214 Pin Pi 11-12 1-10 Label L b l FG10. DVM in Diode Mode. 83 May 201 50PV450 1 Plasma .

84 May 201 50PV450 1 Plasma . DVM in Diode Mode.54V Red Lead on Floating Gnd Black Lead on Floating Gnd All readings from Floating Ground Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected.P112 Upper Y-Drive to Y-SUS Board P215 Voltage and Diode Test YYLocation: Bottom Left of board P112 P215 Upper Y-Drive P112 to Y-SUS Board P215 Pin 6-12 5 1-4 Label FGnd n/c Vscan Run FGnd n/c 107V Diode Check FGnd n/c Open Diode Check FGnd n/c 1.

97V FG Can not read the pins because they are covered in silicon P121 All voltages are from Floating G lt f Fl ti Ground d 85 May 201 50PV450 1 Plasma .8V 0V FG 4.4V 2.P121 Upper Y-Drive to Lower Y-Drive P221 Voltage and Diode Test YYLocation: Bottom of board P121 "Upper Y Drive to P221 "Lower Y-Drive" Upper Y-Drive" Lower Y Drive Pin 1~4 11 12 13 14 15 16 17~20 21~23 27~30 Label SUS_DN (FG) YSUS_DATA YT_OCR YT_OC1 YT_LE(STB) YT_CLK YT_DATA SUS_DN (FG) FG5V FG5V Run FG 0V 2.2V 2.6V 0.

P213 The Lower Y-Drive is responsible for driving the bottom half of the panel’s 540 horizontal electrodes with Y-Scan signals through the Panel’s Flexible printed circuits. You must remove the Lower and Upper Y-Drive boards completely.Y-Drive Lower Layout PANEL SIDE p/n: EBR69839201 P221 P211 P212 Y-SUS SIDE Warning: Never run the set with just P213 disconnected. (Gate arrays) on pp the upper and lower Y-Drive boards. 86 May 201 50PV450 1 Plasma . Th Y S The Y-Scan logic l i signals are also related to chassis ground and the Data buffers distribute the Y-Scan logic data to all the Buffers. Can not read pins because they are covered in silicon. Another new development is that the lower Y-Drive board receives Chassis Ground and M5V P213 pins 14 and 15 f th D t b ff d for the Data buffers. Never run the set with P221 unplugged unless you remove the Upper Y-Drive board completely. These signals are routed to the Upper Y-Drive through P221 to P121 on the upper. It receives FG5V from the Upper Y-Drive on P221 pins 21~30 from P121 pins 1 9 for the lower 21 30 1~9 Y-Drive buffers low voltage signal processing.

P211 Lower Y-Drive to Y-SUS Board P217 Voltage and Diode Test YYLocation: Bottom Left of board P211 P217 P211 “Lower Y-Drive" to “Y-SUS" P217 Pin 9-12 9 12 8 1-7 Label Vscan V n/c FGnd Run 107V n/c FGnd Diode Check Open O n/c FGnd Black Lead on Floating Gnd Diode Check 1. DVM in Diode Mode.54V 1 54V n/c FGnd Red Lead on Floating Gnd All readings from Floating Ground g g Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected. 87 May 201 50PV450 1 Plasma .

P212 Lower Y-Drive to Y-SUS Board P216 Voltage and Diode Test YYLocation: Bottom Left of board P212 P216 Y-Drive P212 to Y-SUS Board P216 Pin 3-12 1-2 Label FGnd Vscan Run FGnd 107V Diode Check FGnd Open Diode Check FGnd 1. DVM in Diode Mode. 88 May 201 50PV450 1 Plasma .54V Red Lead on Floating Gnd Black Lead on Floating Gnd All readings from Floating Ground g g Y-Drive Upper Y-SUS Board Diode Mode Readings taken with all connectors Disconnected.

6V 0.97V FG Can not read the pins because they are covered in silicon P221 All voltages are from Floating G lt f Fl ti Ground d 89 May 201 50PV450 1 Plasma .P221 Lower Y-Drive to Upper Y-Drive P121 Voltage and Diode Test YYLocation: Top of board P221 "L "Lower Y D i " to P121 "U Y-Drive" t "Upper Y D i " Y-Drive" Pin 1~4 5-9 12 13 14 15 16 17~20 21~23 24~30 Label FG5V FGnd YT_OCR YT_OC1 YT_LE(STB) YT_CLK YT CLK YT_DATA SUS_DN (FG) FG5V SUS_DN (FG) Run 5V 0V 2.8V 0 8V 0V FG 4.2V 2.4V 2.

34V 3 Gnd Gnd Gnd 2 CLK FG 2.08V 10 Gnd Gnd Gnd 9 OC1_B 2.63V 2.08V 7 Gnd Gnd Gnd 6 DATA_T 2.55V 0.55V 0. 90 May 201 50PV450 1 Plasma .63V Gnd 0.08V 12 Gnd Gnd Gnd 11 DATA_B 0V 2.63V Gnd 0.89V 1.2V 2.89V 1.08V 1 STB 4.8V 2.9V 2.08V Red Lead Black Lead on Chassis Gnd on pin Diode Check 0.63V Gnd 0. TIP: Use C540 Left leg to check the Y Scan signal if the Y Drive boards are removed Y-Scan Y-Drive Note: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.9V 13 OC2_B 2.86V 2.P213 Lower Y-Drive to Y-SUS Board P213 Connector (Logic Signals) YYTIP: This connector does not come with a new Y-SUS or Y-Drive. P212 "Y-SUS" to "Lower "Y-Drive" P213 Pin Label Run Diode Check 15 M5V 4.2V Open 8 OC2_T 2.63V Gnd 0.63V Gnd 0.9V 14 M5V 4.63V 0.63V Black Lead on pin P213 P213 Lower Y-Drive Y-SUS Board All voltage readings taken from Chassis Ground Diode Mode Readings taken with all connectors Disconnected.08V 5 Gnd Gnd Gnd 4 OC1_T 0.63V 0. DVM in Diode Mode.

9V p/p) Pin 6 (8.08V p/p) Pin 8 (10.47V p/p) Pin 11 (8.15V p/p) All scope settings at 5mSec per/div / 5V per/div All signals taken from Chassis Ground 91 May 201 50PV450 1 Plasma .67V p/p) Pin 1 (11. P213 P213 Y-SUS to L Y SUS t Lower Y D i P213 Y-Drive Pin Pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Label Label M5V M5V OC2_B Gnd DATA_B DATA B Gnd OC1_B OC2_T Gnd DATA_T Gnd OC1_T OC1 T Gnd CLK STB Pin 13 (19.67V p/p) Pin 2 (9.Lower Y-Drive Board P213 Connector Waveforms YNote: The Lower Y-Drive board receives Monitor 5V from the Y-SUS.62V p/p) Pin 4 (9V p/p) Pin 9 (10.

(See Fig 3) y Gently slide the Ribbon Cable free from the connector. be sure the Tab is seated securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1). Gently Pry Up Here Locking tab in upright position Fig 1 Fig 2 Fig 3 To reinstall the Ribbon Cable. The locking tab must be standing straight up as shown in Fig 2. To T remove the Ribbon C bl f th Ribb Cable from th connector fi t carefully lift the Locking T b f the t first f ll th L ki Tab from the back and tilt it forward ( lift from under the tab as shown in Fig 1). Be sure ribbon tab is released By lifting the ribbon up slightly. Lift up the entire Ribbon Cable gently to release the Tabs on each end.Removing (Panel) Flexible Ribbon Cables from Y-Drive Upper or Lower YPictures are from a different model. carefully slide it back into the slot see ( Fig 3 ). but the process is the same. before removing ribbon. 92 May 201 50PV450 1 Plasma .

p The Locking Tab will offer a greater resistance to closing in the case. 93 May 201 50PV450 1 Plasma . Note the cable is crooked in this case because the Tab on the Ribbon cable was improperly seated at the t t d t th top. You can tell by observing the line of the connector compared to the FPC. Thi can cause bars. Remove the ribbon cable and re-seat it correctly. they should be parallel. lines. This b li intermittent line and other abnormalities in the picture.Incorrectly Seated Y-Drive Flexible Ribbon Cables YThe Ribbon Cable is clearly improperly seated into the connector.

check the pins for shorts or abnormal loads.Y-Drive Buffer Troubleshooting HOW TO CHECK FOR A SHORTED BUFFER IC BACK SIDE FRONT SIDE BUFFER IC FLOATING GROUND (FGnd) Using the “Diode Test” on the DVM. Any of these output lugs can be tested. RED LEAD On BLACK LEAD On “ANY” Floating Ground Output Lug Reads 0.78V y Indicated by white outline Reversing the leads reads Open FRONT SIDE OF Y-DRIVE BOARD 8 Ribbon cables communicating with the Panel’s (Horizontal Panel s Electrodes) totaling 1080 lines determining the Panel’s Vertical resolution pixel count. Look for shorts indicating a defective Buffer IC 94 May 201 50PV450 1 Plasma .

Upon completion of this section the Technician will have a better understanding of the circuit and be able to locate test points needed for troubleshooting and all alignments. Control board does not use the 18V. Z Bias 95 May 201 50PV450 1 Plasma .Z-SUS SECTION This Section of the Presentation will cover troubleshooting the Z-SUS Board Assembly. Locations • • • DC Voltage and Waveform Test Points Z BIAS Alignment Diode Mode Test Points Operating Voltages Power Supply Supplied VS pp y pp M5V Y-SUS Y SUS Supplied Developed on Z-SUS 18V Routed through the Y-SUS then to the Control Board then to the Z-SUS Generated on the Y-SUS then to the Control Board then to the Z-SUS.

Z-SUS Block Diagram
VS

Y-SUS Board
18V M5V M5V

Power Supply Board

Control Board
M5V

18V

Z-SUS board receives VS from the Y-SUS and M5V and 18V routed through the Control board

Receives Logic Signals Via 3 FPC

Circuits generate erase, sustain waveforms
NO IPMs

Generates VZB (Z Bias) 130V

Flexible Printed Circuits

PDP Display Panel P l

Z-SUB

FET Makes Drive waveform
Simplified Block Diagram of Z-SUS (Sustain) Board Z SUS

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Z-SUS Board Component Identification
P203 VS from SMPS FS201 VS 6.3A/250V VZB Adj VR101 Z-SUS Output FETs Z-SUS Waveform Test P i t T t Point J54 No IPMs P204

VZB TP Across R156

Z-SUS Waveform Development FETs

P/N EBR71727901
FS202 M5V 4A/125V

P205 05 M5V from SMPS to the Y-SUS, +18V generated on the Y-SUS are routed through the Control board. Logic Signals generated on the Control board.

To Z-SUB P201 P206

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50PV450 Z-SUS Board Drawing
P203
P203 7-8) Gnd 6) n/c 4-5) VS 3) n/c 1-2) ER
1-2) ER 3) n/c 4-5) VS 6) n/c 7-8) Gnd

57VRMS 100uSec 261V p/p

Example:
Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N.A. / -190 / 150 / N.A. / 130 Max Watt : 360 W (Full White)

VR101 VZB Adj

FS201 (VS) 6.3A / 250V

Q104
VZB TP R156

Q109 Q106 D118

Q113 Q114 D110

VZB (Z Bias)

To run the Z-SUS stand-alone: Jump VS from SMPS to pins 4 or 5 of P203. Jump +5V from SMPS to fuse FS202. Jump 17V from SMPS to J21. Leave Connector P201 connected to Control Board. J54 290V p/p (More square shape).
P201
1-2) 18V 3) n/c 4-5) M5V 6-7) Gnd 8) SUS_DN 9) CTRL_EN 10) SUS_UP 11) VZB2 12) ER_DN 13) VZB1 14) ER_UP 15) ZBIAS 18.34V (n/c) 4.89V Gnd 0.73V 0.06V 0.15V 2.49V 0.1V 2.53V 0.11V 1.89V
ER_UP ER_DN SUS_DN

50V 2MSec 288V p/p

Q102
Gnd Gnd

Z-SUS EBR71727901
P204 D114 Q107 Q110
Z-Drive J54 Waveform

J21 18V

D111 D108 Q103

J16 M5V

FS202 (M5V) 4A / 125V

FS202

P205

P201 P206

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This is only to show the effects of Z-Bias on the waveform.Z-SUS Waveform The Z-SUS (in combination with the Y-SUS) generates a g g g SUSTAIN Signal and an ERASE PULSE for generating SUSTAIN and DISCHARGE in the Panel. Reset Location: Center Right of Z-SUS board Y Drive Waveform Blanking Oscilloscope Connection Point. Z Drive Waveform Blanking VZB VR101 manipulates the offset of the Z-Drive waveform segment. This waveform is supplied to the panel through Z-SUB and then to FPC (Flexible Printed Circuit) connections P201. Right Hand Side Center. P202 and P203. VZB (Z-Bias) voltage 130V ± 1/2V TIP: The Z-Bias (VZB) Adjustment is a DC level adjustment. J54 to check Z Output waveform. This Waveform is just for reference to observe the effects of Z Bias adjustment 99 May 201 50PV450 1 Plasma .

f i t this is the “Heat Run” mode.A.A. Max Watt : 360 W (Full White) VZB (Z-Bias) Read the Voltage Label on the back top center of the panel when adjusting VR101. VZB (Z-Bias) Adjust VR101 Negative Lead VZB (Z Bias) R156 Positive Lead Set h ld S t should run for 10 minutes.Z-Bias (VZB) VR101 Adjustment Location Top Left of Z-SUS Board Example of a voltage label: Model : PDP 50R3### Voltage Setting: 5V/ Va:55/ Vs:201 N. 190 N A / -190 / 150 / N A / 130 N. Adjust VR101 VZ (Z-Bias) while reading across R156 to match your Panel’s Voltage Label (± 1/2V) 100 May 201 50PV450 1 Plasma . Set screen to “White Wash” mode or 100 IRE White input.

DVM in Diode Mode. 101 May 201 50PV450 1 Plasma .P203 Z-SUS Connector to Y-SUS P218 Voltages and Diode Checks ZYVoltage and Diode Mode Measurements P203 "Z-SUS“ to "Y-SUS" P218 Pin 1~2 3 4~5 5 6 7~18 Label ER_PASS n/c +Vs s n/c Gnd Run *98V~102V n/c *201V 0 n/c Gnd Diode Check Open n/c Ope Open n/c Gnd P203 Location: Top Left of Board Pin 1 * Note: This voltage will vary in accordance with Panel Label There are no Stand-By voltages on this connector Diode Mode Readings taken with all connectors Disconnected.

34V n/c 4.P201 Z-SUS Connector to Control P2 Voltages and Diode Checks ZVoltage and Diode Mode Measurements P201 "Z-SUS Board" to P2 "Control" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label +18V +18V n/c +5V (M5V) +5V (M5V) Gnd Gnd SUS_DN CTRL_EN SUS_UP VZB2 ER_DN VZB1 ER_UP ZBIAS Run 18.52V Gnd Gnd Open Open Open Open Open Open p Open Open Pin 1 FS202 M5V 4A/125V J21 18V There are no Stand-By voltages on this connector Diode Mode Readings taken with all connectors Disconnected.06V 0.73V 0.52V 1.15V 2. P201 Location: Bottom Left hand side 102 May 201 50PV450 1 Plasma .52V 1.53V 0.89V 4.89V Gnd Gnd 0. DVM in Diode Mode.1V 2.49V 0.34V 18.9V Diode Check Open Open 1.87V 1.

45V Circuit No.D110.Q110 0.Q113. (Overload) Q102.Q103 0.D118 Forward Reverse HS102 Forward Reverse 0.D111 Q104. Q107.D108.50PV450 Z-SUS Board FET Locations P203 1-2) ER 3) n/c 4-5) VS 6) n/c 7-8) Gnd Z-SUS EBR71727901 FS201 (VS) 6.35V ~ 0.45V O.5V ~ 0.3A / 250V HS10 1 Q109 Q106 D118 Q104 Q113 Q114 D110 Q102 D111 D108 FS202 Q103 HS10 2 P204 D114 Q107 Q110 P205 P201 Position HS101 Direction D114.45V 0.4V ~ 0.Q109 0.35V ~ 0.L.45V P206 103 May 2011 50PV450 Plasma .L.35V ~ 0.Q114 0.6V O.35V ~ 0.55V Q106. (Overload) D109.

input pin. pp y producing 17V or y can substitute voltage matching 17V from an g you g g The Power Supply should be p external source to either pins 1 or 2 on connector P2 on the Control board. leave P105 connected and there will be no need to jump the 17V or the M5V to the Z-SUS. 1) Disconnect P811 5) Turn on the set and check for 221V p/p waveform on Z-SUS Board 2) Disconnect P105 3) Jump STBY5V to FS202 on Z-SUS (M5V Fuse) 4) Jump 17V to jumper J21 on Z-SUS Board Tip: If the DC to DC converter generating 18V is running on the Y-SUS you can jump any 5V to the Y-SUS M5V Y-SUS. Note: The 5V will be routed back to the Control Board for power through the P201 to P2 connector. The Power Supply should be producing M5V or you can substitute Stand-By 5V or any 5V from an external source to the 5V Fuse on the Z-SUS (FS202). 104 May 201 50PV450 1 Plasma .How to Check the Z-SUS Stand-Alone ZStandThe Power Supply should be producing VS or you can substitute voltage matching VS from an external source to either pin 1 or 2 P102 on the Z-SUS board.

• DC Voltage and Waveform Test Points • Diode Mode Test Points Signals Main Board Supplied Panel Control and LVDS (Video) Signals Control Board Generated Y-SUS and Z-SUS Drive Signals (Sustain) Y SUS Z SUS Y-Drive Board Scan Signals (Gate Address) X Board Drive Signals (RGB Address) Operating Voltages Y-SUS Supplied +5V (M5V) Developed on the SMPS +18V (Routed to the Z-SUS) (Not used by the Control Board) Developed on the C Control Board +1. Upon completion of this section the Technician will have a better understanding of the circuit and be able to locate test points needed for troubleshooting.3V (IC53) for the X-Boards (TCPs) 105 May 201 50PV450 1 Plasma .8V (IC52) for internal use.3V (IC51) for LVDS Power +3. Silk screened as IC25. +3.0V (IC61) for internal use +1.CONTROL BOARD SECTION This Section of the Presentation will cover troubleshooting the Control Board Assembly.

Control Board Component Identification p/n: EBR71727801 106 May 201 50PV450 1 Plasma .

04V 1.1V 2.89V 2) 3.49V 0.29V 07) 3.3V) IC53 P104 To Right X Board P31 LVDS 3.28V 08) 3.53V 0.04V IC51 M5V 1.88V 02) Gnd 01) 0.75V 03) 1.89V P102 To Center X Board 3) 4.3V To X-Boards Diode Check All Connectors Connected 0.65V X Board Q1 1-4 (3.85V 6) 1.8V 2) Gnd 3) 4.93V 2) 3.69V P101 Gnd X1 To Left 0.50PV450 Control Board Layout Drawing 18V To Z-SUS (In P105 pins 23-25) (Out P2 pins 14-15) Diode Check All Connectors Connected 1.26V 14-15) 18V 13) n/c 11-12) M5V 9-10) Gnd 08) SUS_DN 07) CTRL_EN 06) SUS_UP 05) VZB2 04) ER_DN 03) VZB1 02) ER_UP 01) ZBIAS 18.29V 06) 3.3V) IC53 L2 C65 1.87V 4) 6.34V (n/c) 4.6769V 107 May 2011 50PV450 Plasma .89V P22 N/C 18V Pins 23-25 M5V Pins 26-28 FL1/FL2 FL5 Diode Check All Connectors Connected 0.06V 0.28V P2 P2 To Z-SUS Board FL5 IC61 M5V IC25 1) 0.3V D1 IC11 1.84V VS-DA TP 1.85V L1 D1 Blinks Indicating Board is Functioning 1.04V C76 3.89V IC25 IC101 IC102 3) 4.3V 1) Gnd IC53 1-4 (3.3V) IC53 C72 4.82V P105 C61 C52 4.46V 8) 2.15V 2.73V To Y-SUS Board 4.89V Gnd 0.84V 3.63V 25 Mhz IC1 CONTROL BOARD p/n: EBR71727801 AUTO Gen To Main Board IC61 05) 3.02V 0.29V 1) Gnd 1.8V Gnd 3.26V 1.11V 1.73V 0.89V FL1/2 1-4 (3.95V 7) 1.85V 5) 4.32V 04) 5.

Control Board Temperature Sensor Location (Chocolate)
The panel is monitored for temperature. The panel’s temperature is transferred through the (Chocolate) to the Temp. Sensor on the back of the board. BACK SIDE OF THE BOARD With Chocolate (Heat Transfer Material) Covering the Temp IC. The Chocolate (Heat Transfer Material) ( ) may stick to the Panel. Be sure to put it in the right place if the board is removed.

CONTROL BOARD LOCATION

Pin 1 IC103 04) 3.3V 03) Gnd 05) Gnd 02) Gnd 06) 3.3V 01) 3.3V

CONTROL BOARD TEMPERATURE SENSOR LOCATION

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Control Board TP Tips
EXTERNAL TRIGGER: (VS_DA) can be used as an External Trigger for your scope when locking onto the Y-Scan or the Z-Drive signal.
VS_DA

AUTO GEN

Auto Gen (Internal Automatic Generator) Short these two pins together to generate patterns on the screen f a Panel Test. for P lT t If patterns do not appear, try removing the LVDS Cable.

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Checking the Crystal X1“Clock” on the Control Board
Check the output of the Oscillator (Crystal) X1. The frequency of the sine wave is 25 MHZ. Missing thi l k i Mi i this clock signal will h lt operation of th panel l ill halt ti f the l drive signals.
Osc. Check: 25Mhz Top Leg

X1

Osc. Check: 25Mhz Bottom Leg

CONTROL BOARD CRYSTAL LOCATION

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IC301.3V to the TCPs.Control Board Signal (Simplified Block Diagram) The Control Board supplies Video Signals to the TCP (Taped Carrier Package) ICs. IC301 Data Buffer IC Resistor Array X-DRIVE BOARD MCM IC1 To Left XBoard To Center X-Board 16 bit words RGB Data Shown 3 Buffer Outputs per TCP 128 Lines per Buffer 384 Lines output Total PANEL There are 15 total TCPs. And the X-Board Data Buffers IC101. If there is a bar defect on the screen. Basic Diagram of Control Board CONTROL BOARD MCM IC1 To Y-SUS DRAM DRAM To ZSUS To Main The Control board also sends 3. it could be a Control Board problem. 5 per/X-Board 5760 Vertical Electrodes 1920 Total Pixels (H) ( ) IC53 3.3V to TCPs To Ri ht T Right X-Board 11 1 May 201 50PV450 1 Plasma . Control Board to X Board Address Signal Flow This Picture shows Signal Flow Distribution to help determine the failure depending on where the problem appears on the screen.

Use Caution when taking Voltage measurements. Note: The +18V is not used by the Control board. is C t l b d it i routed t the t d to th Z-SUS leaving on P2 Pins 14~15. See P105 Connector Voltages and Diode Check from more details. Y-Drive logic signals are simply routed right through the Y-SUS to the Y-Drive boards.Control Board Connector P105 to Y-SUS P102 Information Pins are very close together. Pin P105 Label Silk Screen All the rest are delivering Y-SUS Waveform development and Y-Drive logic signals to the Y-SUS Board. Note: This silk screen and the actual pin function are not correct. Pins 26 through 28 Receive M5V from the Y-SUS. 1 12 May 201 50PV450 1 Plasma . Pins 23 through 25 Receive 18V from the Y-SUS.

98V 18.46V 2.82V 2.06V 0.84V 2.02V 0.82V 2.81V 2. Note: There are no voltages in Stand-By mode Run 0V 1.34V 18. DVM in Diode Mode.86V 2 86V Gnd 0V 1.09V 1.81V 2.13V 2.02V 0.89V 4.81V Gnd 2.89V Gnd Gnd Diode Check 2.11V Gnd 0.05V 0.06V 0.16V 0. 1 13 May 201 50PV450 1 Plasma .34V 18 34V 18.84V 2 84V 2.06V 0 06V 0.98V Open O Open Open Open Open Open Gnd Gnd Run 0.81V 2.84V 2.84V Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Label DATA_TOP OC1_TOP CLK STB OC1_BTM DATA_BTM OC2_BTM +18V +18V +18V M5V M5V M5V Gnd Gnd 1 SET_UP ER_UP Gnd ER_DN BLOCKING DELTA_VY_O OC2_TOP Diode Mode Readings taken with all connectors Disconnected.82V 2. Black lead on Gnd.84V Gnd Gnd Gnd Gnd 2.98V Diode Check 2.89V 4.84V 2.82V 2.2V 0.34V 4.81V 2 81V 2.3V 0.82V 2.Control P105 to Y-SUS P102 Plug Information YP105 "Control" to P102 "Y-SUS" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label CTRL_OE OE SUS_UP SUS_DN SUS DN SET_DN Slope_Rate_Sel Det_Level_Sel Ramp_Slope_Opt R Sl O t Pin 1 on Control is Pin 50 on Y-SUS.83V 2 83V 2.35V 1.

44~49.Control Board LVDS P31 Signals LVDS Cable P31 on Control board shown. 70~73 are video. 60~65. Video Signals from the Main Board to the Control Board are referred to as Low Voltage Differential Signals or LVDS. Example of LVDS Video Signal (613mV p/p) 10Msec LVDS 2Msec 1 Example of Normal Signals measured at 100mV per/div Pins 12~17. Pin 79 is active high when the set is placed into 3D mode. 38~41. The video is delivered in dual 24 bit LVDS format. 67~68 are Clock signals for synchronizing. Their presence can be confirmed with the Oscilloscope by monitoring the LVDS signals with SMPTE Color Bar input. 35~36. Pins are close together. Flip up the locking mechanism to unlock. 28~33. 51~52. Loss of these Signals would confirm the failure is on the Main Board or the LVDS C bl it lf Cable itself. 22~25. 1 14 May 201 50PV450 1 Plasma . Pins 19~20.

2V 1.05V Gnd Gnd 1. Diode Mode Readings taken with all connectors Disconnected.05V 1.05V 1.1.05V Gnd Gnd 1.11V RD1+ 1.Control Board LVDS P31 Connector Voltages and Diode Check P31 LVDS "Control" to P701 "Main" Pin 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 Label Gnd n/c ROM_RX ROM_TX n/c n/c Gnd G d n/c n/c n/c n/c Gnd n/c n/c Gnd n/c n/c n/c / n/c n/c n/c Gnd Gnd n/c n/c n/c n/c Run Diode Check Gnd n/c 3.11V 1.3V 1.1.05V 1.11V 1 11V 1.11V 1.11V 1.05V 1 05V 1.11V 1.3V Gnd Gnd RC1.2V RD1. 1 15 May 201 50PV450 1 Plasma .11V RE1+ 1.05V Gnd 1.2V RCLK1.3V 3.1.2V 1.3V n/c n/c Gnd G d n/c n/c n/c n/c Gnd n/c n/c Gnd n/c n/c n/c / n/c n/c n/c Gnd Gnd n/c n/c n/c n/c Gnd 2.05V 1.05V Gnd 1.05V 1.3V 3.05V Gnd Gnd n/c n/c / n/c n/c 2.5V Gnd Diode Check Gnd 1.05V Gnd 1.3V 0.3V 1.05V 1.3V Gnd 1.3V RB1. Black lead on Gnd.3V Gnd Gnd RCLK1.05V 1.1.55V 2.05V 1.55V Gnd P31 RA1.55V 2.11V RC1 1 11V RC1+ 1.05V 1 05V 1.05V Gnd Pin 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Label Gnd RA2RA2+ RB2RB2+ Gnd RC2RC2 RC2+ Gnd RCLK2RCLK2RD2RD2+ RE2RE2+ Gnd n/c n/c / n/c n/c Module_SDA1 DISP_EN Module_SCL1 PC_SER_DATA Run Gnd 1.11V 3.05V 1. DVM in Diode Mode.05V 1.3V Gnd n/c n/c / n/c n/c 3.3V 2.05V 1.1.05V 1.05V 1.05V Gnd 1.8V 3.05V 1.05V 1.11V RB1+ 1.3V RE1.05V 1 05V 1.05V 1.11V RA1+ 1.05V 1.05V 1.55V 2.05V 1.05V 1.05V Gnd 1.05V 1.05V 1 05V 1.05V 1.1.05V 1.05V Gnd 1.05V 1.05V 1.1.05V 1.23V 3.05V 1.11V n/c n/c Gnd G d 1.05V 1.05V 1.05V 1.55V 2.3V Gnd Gnd 1 PC_SER_CLK Gnd * Indicates video signal Note: There are no voltages in Stand-By mode.05V Pin 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 Label Run Diode Check Gnd n/c n/c Gnd n/c n/c n/c / n/c n/c n/c Gnd Gnd Gnd n/c n/c Gnd n/c n/c n/c / n/c n/c n/c Gnd Gnd Gnd 1.05V Gnd 1.3V Gnd 1.05V 1.

06V 0 06V 0.15V 2.49V 0.9V Diode Check Open Open O 1.34V 18 34V n/c 4.89V 4.89V Gnd Gnd 0. Black lead on Gnd.1V 2.Control Board P2 Connector Pin ID and Voltages Voltage and Diode Mode Measurements for the Control Board.34V 18. Note: There are no voltages in Stand-By mode.87V 1.73V 0. P2 Label P2 "Control" to "Z-SUS Board" P201 Pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Label (+18V) (+18V) n/c M5V M5V Gnd Gnd SUS_DN CTRL_EN CTRL EN SUS_UP VZB2 ER_DN VZB1 ER_UP ZBIAS Run 18.52V Gnd Gnd Open Open Open Open Open Open Open Open P2 18V M5V 1 Diode Mode Readings taken with all connectors Disconnected. 1 16 May 201 50PV450 1 Plasma . DVM in Diode Mode.52V 1.53V 0.52V 1.

The left and right are the B+ route.Control Board (EMI Filter) Explained The two EMI Filters just to the bottom right of P105 and one just to the top left of P2 are surface mount mini devices which shunt high frequencies to ground. FL1. Y-SUS and Control Board. FL2 and FL5 (5V EMI filters) Gnd 5V 5V Gnd G d 1 17 May 201 50PV450 1 Plasma . Each EMI filter has 4 pins as shown in the example. the two side solder points are Chassis Gnd route Gnd. These high frequencies are generated on the SMPS.

36V TCP3_RSDS_A3P 1.36V 1.36V 1.42V 1.36V 1.18V 1.36V 1.18V 1.09V TCP1_RSDS_A3P 1.36V 20 TCP2_RSDS_A2N 1.18V 1.32V Gnd Gnd 1.34V 1.08V Gnd 1.36V TCP2_RSDS_A1N 1.89V 1.18V 1.08V 10 TCP1_RSDS_A2N 1. 1 18 May 201 50PV450 1 Plasma .3V 3.42V 0.P101 Connector "Control Board” to “Left X Board” P110 P101 "Control“ to P110 "X-Left" Pin Label Run Diode Check 1 3.25V Gnd 1.18V 1.18V 1.3V White hash marks count as 5 Note: There are no voltages in y Stand-By mode.25V 1.36V Gnd 27 Gnd Gnd 28 TCP3_RSDS_A3N 1.08V 1.34V 1.25V Gnd 1.08V Open Gnd Gnd 3.08V 1.25V Open 12 TCP1_RSDS_A1N 1.18V Gnd 13 TCP1_RSDS_A1P 1.25V 29 TCP3 RSDS A3P 1 25V 1.36V Gnd 24 Gnd Gnd RSDS_CLK_N1 25 1.25V 3.18V Open 11 TCP1_RSDS_A2P 1.89V 1 89V Gnd Diode Check Open Open Open Gnd Gnd 1.25V 1.25V 1.25V 1.36V 1.18V 22 1.25V 1.18V 3.28V Open 2 3.36V RSDS_CLK_P0 16 1.42V 0.3V 3.32V Gnd 1.36V 21 TCP2_RSDS_A2P 1.32V 1 32V Gnd 1 4 1~4 3.09V Gnd 14 Gnd Gnd RSDS_CLK_N0 15 1.18V 1.3V 3. Black lead on Gnd.25V 1. Diode Mode Readings taken with all connectors Disconnected.18V 1.28V Open 5 n/c n/c n/c 6 n/c n/c n/c 7 Gnd Gnd Gnd 8 TCP1_RSDS_A3N 1.28V Open 3 3.18V Gnd Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Label TCP3_RSDS_A2P TCP3_RSDS_A1N TCP3_RSDS_A1P Gnd TCP4_RSDS_A3N TCP4_RSDS_A3P TCP4_RSDS_A2N TCP4 RSDS A2N TCP4_RSDS_A2P TCP4_RSDS_A1N TCP4_RSDS_A1P Gnd RSDS_CLK_N3 RSDS_CLK_P3 Gnd TCP5_RSDS_A3N TCP5_RSDS_A3P TCP5_RSDS_A2N TCP5_RSDS_A2P TCP5 RSDS A2P TCP5_RSDS_A1N TCP5_RSDS_A1P Gnd STB0 STB1 X_ER_DN0 X_SUS_DN0 CE1_0 CE2_0 P0C0 BLK0 Gnd Run 1.42V 0.32V 1 32V 30 TCP3_RSDS_A2N 1.09V 3.18V TCP2 RSDS A3N 1 18V 18 Gnd 19 TCP2_RSDS_A3P 1.18V 1 18V 1.36V Gnd 1.2V 3.2V 0.32V Gnd 17 Gnd Gnd TCP2_RSDS_A3N 1.25V Gnd 3.09V Gnd 1.34V Gnd RSDS_CLK_P1 26 1.25V 9 3.25V 1 25V 1. DVM in Diode Mode.3V 3.28V Open 4 3.36V 1.36V 1.25V 1.36V 1 36V 3.36V 1.36V 23 TCP2_RSDS_A1P 1.

18V 1.25V 1.36V 1.36V Gnd Gnd 1.36V 1.2V 3.18V 1.36V 1.18V 1.36V 1. P102 "Control“ to P310 "X-Cent" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Label 3.3V 3.2V 0.36V Gnd 1.09V Gnd 1.36V 1.09V Gnd 1.42V 0.25V 1.34V 1.25V 1.28V 3.32V Gnd Gnd 1.25V Diode Check 1.08V Open Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Label Gnd RSDS_CLK_N3 RSDS_CLK_P3 Gnd TCP10_RSDS_A3N TCP10_RSDS_A3P TCP10_RSDS_A2N TCP10_RSDS_A2P TCP10_RSDS_A1N TCP10_RSDS_A1P Gnd STB4 STB5 X_ER_DN2 X_SUS_DN2 CE1_2 CE2_2 P0C1 BLK1 Gnd Run Gnd 1.89V Gnd Diode Check Gnd Gnd 3.08V Gnd 1.08V Gnd 1.25V 1. DVM in Diode Mode.36V 1.18V 1.18V 1.25V Gnd 1.08V Open Open Gnd 3.28V 3.42V 1.36V 1.09V 3.18V 1.18V 1.18V 1.28V 3.25V 1.32V Gnd Open Open Open Gnd Gnd 1.18V 1.18V 1.36V Gnd 1.18V 1.3V n/c n/c Gnd TCP6_RSDS_A3N TCP6_RSDS_A3P TCP6_RSDS_A2N TCP6_RSDS_A2P TCP6_RSDS_A1N TCP6_RSDS_A1P Gnd RSDS_CLK_N0 RSDS_CLK_P0 Gnd TCP7_RSDS_A3N TCP7_RSDS_A3P TCP7_RSDS_A2N Run 3.28V n/c n/c Gnd 1.18V 1.18V 1.36V 1.09V 3.42V 0.32V Gnd Diode Mode Readings taken with all connectors Disconnected.32V Gnd Gnd 1.25V 1.34V 1.25V Gnd 3.3V 3.18V Diode Check Open Open Open Open n/c n/c Gnd 3.36V 1.3V Note: There are no voltages in Stand-By mode.32V Gnd 1.08V Gnd 1.P102 Connector "Control Board” to “Center X Board” P310 White hash marks count as 5 1~4 3.42V 0.25V 1. 1 19 May 201 50PV450 1 Plasma .36V 3.36V 1.36V 1.18V 1.36V Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Label TCP7_RSDS_A2P TCP7_RSDS_A1N TCP7_RSDS_A1P Gnd RSDS_CLK_N1 RSDS_CLK_P1 Gnd TCP8_RSDS_A3N TCP8_RSDS_A3P TCP8_RSDS_A2N TCP8_RSDS_A2P TCP8_RSDS_A1N TCP8_RSDS_A1P Gnd TCP9_RSDS_A3N TCP9_RSDS_A3P TCP9_RSDS_A2N TCP9_RSDS_A2P TCP9_RSDS_A1N TCP9_RSDS_A1P Run 1. Black lead on Gnd.36V 1.25V Gnd 1.34V 1.25V Gnd 1.36V 1.3V 3.89V 1.25V 1.25V 1.25V 1.

32V 1 32V Gnd RSDS_CLK_N11 RSDS_CLK_P11 Gnd TCP15_RSDS_A3N TCP15_RSDS_A3P TCP15 RSDS A2N C 5_ S S_ TCP15_RSDS_A2P TCP15_RSDS_A1N TCP15_RSDS_A1P Gnd STB4 STB5 X_ER_DN2 X_SUS_DN2 CE1_2 CE2_2 P0C1 BLK1 Gnd Diode Mode Readings taken with all connectors Disconnected.36V 1.89V 1.28V 3.08V G d Gnd 1.36V 1.P104 Connector "Control Board” to “Right X Board” P310 White hash marks count as 5 1~4 3.25V 1 25V Gnd 1.3V 3.08V Gnd 1.18V 1 18V 1.36V Gnd Gnd 1.42V 0.34V 1.25V 1.09V Gnd 1.32V G d Gnd Gnd 1.25V 1.18V 1.28V 3. 120 May 201 50PV450 1 Plasma . Run Gnd 1.09V 3.36V 1 36V 1.36V 1.18V 1.09V 3 09V Gnd 1.25V Diode Check 1.25V Gnd 3.18V 1.3V 3.36V 1.18V 1.34V 1.36V 1.18V 1.25V 1.89V 1 89V Gnd Diode Check Gnd Gnd 3.36V Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Label TCP12_RSDS_A2P _ _ TCP12_RSDS_A1N TCP12_RSDS_A1P Gnd RSDS_CLK_N9 RSDS_CLK_P9 G d Gnd TCP13_RSDS_A3N TCP13_RSDS_A3P TCP13_RSDS_A2N TCP13_RSDS_A2P TCP13_RSDS_A1N TCP13_RSDS_A1P TCP13 RSDS A1P Gnd TCP14_RSDS_A3N TCP14_RSDS_A3P TCP14_RSDS_A2N TCP14_RSDS_A2P TCP14_RSDS_A1N TCP14 RSDS A1N TCP14_RSDS_A1P Run 1.18V 1.42V 0.25V 1.3V n/c n/c G d Gnd TCP11_RSDS_A3N TCP11_RSDS_A3P TCP11_RSDS_A2N TCP11_RSDS_A2P TCP11_RSDS_A1N TCP11_RSDS_A1P TCP11 RSDS A1P Gnd RSDS_CLK_NB RSDS_CLK_PB Gnd TCP12_RSDS_A3N TCP12_RSDS_A3P TCP12 RSDS A3P TCP12_RSDS_A2N Run 3.18V 1.25V 1.18V 1.25V 1.08V Open Open Gnd 3.42V 0.09V 3.42V 1.36V 1 36V 1.36V 1.36V G d Gnd 1.36V 1.25V 1 25V Gnd 1.18V 1.18V 1.18V 1.36V 1.3V 3.08V 3 08V Open Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Label Gnd Note: There are no voltages in Stand-By mode.36V Gnd 1.28V 3.2V 3.36V 1.34V 1.28V n/c n/c G d Gnd 1.25V 1.25V 1 25V 1.36V 1.32V Gnd 1.2V 3 2V 0.18V 1.36V 3.32V Gnd Gnd 1.3V P104 "Control“ to P310 "X-Right" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Label 3.08V Gnd 1.25V 1. DVM in Diode Mode.18V Diode Check Open p Open Open Open n/c n/c G d Gnd 3.36V 1.32V Gnd Open Open Open Gnd Gnd 1.25V Gnd 1.18V 8 1. Black lead on Gnd.25V 1.

RIGHT and CENTER) SECTION The following section gives detailed information about the X boards. (Taped Carrier Packages). The X boards are the attachment points for these FPCs. The X-Boards receive their main B+ from: Originally developed on the Switch Mode Power Supply Va (Voltage for Address) is routed through the Y-SUS board and then to the Left X board via P203 pins 4~5. P110 P310 121 May 201 50PV450 1 Plasma . p Then it leaves on P321 and goes to the Right X P320 pins 1~2. These boards have no adjustment. Control board develops 3. g g These boards deliver the Color information signal developed on the Control board to the TCPs. (Flexible Printed Circuits) which are attached directly to the panel. P310 and P310. Va also leaves P120 and is sent to the Center X via P320 pins 1~2.3V (IC53) and routes to each XBoard via ribbon connectors P110. The TCPs are attached to the vertical FPCs.X BOARD (LEFT.

• The X boards have connectors to 15 TCPs. Divide 5760 by 3 to determine the horizontal resolution of the panel (1920). • They route the Logic (Color) signals from the Control board to all of the Taped Carrier Packages (TCPs). g (As viewed from the rear of the set). . the Left. each buffer output 128 pins to the vertical electrodes. then the Left X sends Va to the Center X and then the Center X sends Va to the Right X. Center and the Right . primarily a Data Buffer and some passive voltage dividers. So there are a total of 45 buffers electrodes feeding the panel’s 5760 vertical electrodes. 122 May 201 50PV450 1 Plasma . There are a total of 15 TCPs and each TCP has 3 internal buffers. The three X boards have very little circuitry.X Board Additional Information There are three X boards. • They route Va voltage to all of the Taped Carrier Packages (TCPs). 5 on each X-Board. Va is introduced to the Left X board first. They are basically signal and voltage p g y y g g routing boards.

The Vertical Address buffers (TCP ) h b ff (TCPs) have one heat sink indicated by the arrow. removed Damage to the TCPs will occur and cause a defective panel. It protects all 15 TCPs. 123 May 201 50PV450 1 Plasma .X Board TCP Heat Sink Warning NEVER run the television with this heat sink removed.

3V Diode Check (0.3V Center X Board P310 3. You can only check for continuity back to IC53. Warning: DO NOT attempt to run the set with the Heat Sink over the TCPs removed.3V Left X Board P110 3. P102 and P104 on the Control board.3V test point.3V B+ Check For Connectors P101.3V Diode Check (0.62V) Black L d O 3 3V Di d Ch k (0 33V) Bl k Lead On 3. unless you disconnect VA from the Y-SUS to the Left X-Board. You can also note a Capacitor (C322 here) left side to identify Pin 38.3V leaves on Pins 1~4 of all three connectors.3V. 124 May 201 50PV450 1 Plasma .3V 3 3V 3.98V 3. board see Control board section. use center pin or Top of component. There will a small feed trough off pin 14 and 38 you can use for Test Points.3V for TCPs IC53 on Control Board 3.TCP 3. Checking IC53 for 3. The trace at pins 14 and 38 of each connector. place the Red Lead On 3.3V Gnd G d With all connectors connected.3V 3 3V All Connectors to All TCPs look very similar for the 3. IC53 4.33V) This also test Data ICs on X-Boards 3. you can not run the set with heat sink removed removed.3V in on Pins 57 ~ 60 on any connector from the Control board 3.3V Right X Board P310 3. Example here from P302. 3.

38V) Black Lead On 3.3V Diode Check (Open) Red Lead On 3.58V) This also test Data ICs on X-Boards. This test the Data IC on X-Board. 125 May 201 50PV450 1 Plasma . TCPs connected or disconnected. EC reads 27.3V Gnd Va 1 EC 50 Va2 EC Testing a single X board.3V Diode Check (Open) ( ) ( ) Black Lead On 3.3V 3. Va Data Gnd Gnd 3. as shown below.76V. All TCPs Connected All TCPs Disconnected Red Lead On 3.X Board Layout Primary Circuit Diode Check The three X-Boards have similar circuit layouts for the connections going to the TCPs. EC Diode Test: Red Lead on EC (Open).3V Diode Check (0.3V Diode Check (0. Do not run the set with the heat sink removed. Disconnect VA from all X-Boards by disconnecting Y-SUS. Disconnected for any other board. To Test EC. VA test: Explained on page 131. Black lead on EC (Open).

3V 256 total lines TCP Taped Carrier Package ac age 128 lines 128 lines Chocolate 128 lines Back side of TCP Ribbon 384 li lines t t l (3 b ff total buffers per/TCP) /TCP) 384 Vertical Electrodes TCP Attached directly to Flexible cable Long Black Heat Sink 126 May 201 50PV450 1 Plasma . Note that each ribbon cable has a solid state device called a TCP attached.TCP (Tape Carrier Package) This shows the layout of the bottom ribbon cables connecting to the Panel’s Vertical electrodes. X Drive Board Frame e Rear pane Vertical Add el dress Front panel Horizo t ontal Address Va Y-SUS Board New Type of TCP Logic X_B/D Control Board 3. (Address Bus).

folds Pinches. On the below: On Va2 (0.44V) ( p ) On EC (Open) On the below: On Va (Open) On 3. Cracks.3V (0.3V EC Gnd EC Gnd n/c Data Data Must be checked on flexible cable. Arrives on X boards P110.3V Originates from Control board IC53 center leg leg.3V Va 3.3V (1. etc… + 1 5 10 15 20 25 30 35 40 45 50 127 May 201 50PV450 1 Plasma . P310.42V) On Va (Open) Flexible Printed Ribbon Cable to TCP IC Gnd Gnd Va 3. 59.5V) On 3. 58.15V) On EC (Open) n/c Look for any TCPs being discolored. P310 Pins 57.TCP Testing 50PV450 X Board TCP Connector Distribution Any X Board to Any TCP (L) P101~P105 or (C) P201~P205 or (R) P201~P305 Va: Comes from Y-SUS P203 4~5 Va: Comes In on: Arrives Left X : P121 pins 1~2 Leaves to Center X P120 pins 1~2 Arrives Center X : P320 pins 1~2 Leaves to Right X P321 pins 1~2 Arrives Right X : P320 pins 1~2 3. 60 On Va (0. scratches. Ribbon Damage.

damage. c and d also. etc. pin holes. c) Cause the entire area driven by the TCP to be “All White” or “ALL BLACK”. After a very short time. Green or Blue. e) A dirty contact at the connector can cause b. these ICs will begin to self destruct due to overheating. 3. 128 May 201 50PV450 1 Plasma .3V shorted). (colored noise). This damaged TCP can.TCP Visual Observation. b) Generate abnormal vertical bars. The line can be Red. (at the location of the TCP). a) Cause the Power Supply to shutdown. (VA shorted. “TCP” Taped Carrier Package Look for burns. d) Cause a “Single Pixel Width Line” defect. Damaged TCP Warning: DO NOT attempt to run the set with the Heat Sink over the TCPs removed removed.

P321 and P320 Connector Va from Left to Center to Right X P320. Voltage and Diode Mode Measurement (No Stand-By Voltages) All Connectors are 4 Pin Pin 1-2 3-4 Label VA Gnd Run *55V Gnd Diode Mode Open p Gnd * Note: This voltage will vary in accordance with Panel Label.P120. There are no Stand-By voltages on this connector. P320. Black lead on Gnd. DVM in Diode Mode. 129 May 201 50PV450 1 Plasma . P120 Left X P320 Center X P321 Center X P320 Right X Diode Mode Readings taken with all connectors Disconnected.

On Va (Open) all connectors removed. On Va (Open) all connectors removed. On Va (Open) Y-SUS connector removed. P221 and P320 X Board Connector (VA Diode Check) P120 Left X P320 Center X P321 Center X P320 Right X Va Right 2 pins g p Both Connectors B th C t Gnd Left 2 pins + On Chassis Gnd Va Right 2 pins g p Both Connectors B th C t Gnd Left 2 pins On Chassis Gnd On Va (0. removed TCPs disconnected.P120. P220.42) Y-SUS connector removed. On Va (0.42) all connectors connected. + 130 May 201 50PV450 1 Plasma . TCPs connected. TCPs connected. On Va (Open) all connectors connected. removed TCPs disconnected.

Diode Mode Readings taken with all connectors Disconnected. 131 May 201 50PV450 1 Plasma . DVM in Diode Mode. There are no Stand-By voltages on this connector. Black lead on Gnd.P121 Left X Drive Connector from Y-SUS P203 Information YVoltage and Diode Mode Measurement (No Stand-By Voltages) Heat Sink Removed 1 P121 Connector " X-Drive Left Board" from "Y-SUS” P203 Pin 1-2 3 4-5 Label VA n/c Gnd Run *55V n/c Gnd Diode Mode Open n/c Gnd * Note: This voltage will vary in accordance with Panel Label.

DVM in Diode Mode.2V 3.34V Gnd 1.34V Gnd 1.89V 0. 132 May 201 50PV450 1 Plasma .18V Diode Check Gnd Open Open Open Open Open Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Pin Label Run 1.25V 1 25V 1.3V 28 TCP3_RSDS_A1P 29 TCP3_RSDS_A1N 30 TCP3_RSDS_A2P 31 TCP3_RSDS_A2N 32 TCP3_RSDS_A3P 33 TCP3_RSDS_A3N 34 35 36 37 Gnd RSDS_CLK_P1 RSDS_CLK_N1 Gnd 38 TCP2_RSDS_A1P 39 TCP2_RSDS_A1N 40 TCP2_RSDS_A2P 41 TCP2_RSDS_A2N 42 TCP2 RSDS A3P TCP2_RSDS_A3P 43 TCP2_RSDS_A3N 44 Gnd 57~60 1 57~60 pins 3.18V 1.25V 1.25V 1. Black lead on Gnd.P110 Connector “Left X Board” to “Control” P101 P110 "X-Left" to P101 "Control" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Label Gnd BLK0 P0C0 CE2_0 CE1_0 X_SUS_DN0 X_ER_DN0 STB1 STB0 Gnd TCP5_RSDS_A1P TCP5_RSDS_A1N TCP5_RSDS_A2P TCP5_RSDS_A2N TCP5_RSDS_A3P TCP5_RSDS_A3N Gnd RSDS_CLK_P3 RSDS_CLK_N3 Gnd TCP4_RSDS_A1P TCP4_RSDS_A1N Run Gnd 1.42V 3.18V Gnd n/c n/c 3.34V Gnd 1.28V 3.18V 1.18V Gnd Diode Check Open Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Open Open Open Open Gnd Pin 45 46 47 Label RSDS_CLK_P0 RSDS CLK P0 RSDS_CLK_N0 Gnd Run 1.25V 1.18V Gnd 1.89V 1.42V 0.25V 1.3V 3.28V 3.18V Gnd 1.25V 1.25V 1.08V 1.25V 1.25V 1.18V 1.18V 1.25V 1.3V 3.28V Diode Check Open Open Gnd Open Open Open Open Open Open Gnd Open Open Open Open Open Open 23 TCP4 RSDS A2P TCP4_RSDS_A2P 24 TCP4_RSDS_A2N 25 TCP4_RSDS_A3P 26 TCP4_RSDS_A3N 27 Gnd 48 TCP1_RSDS_A1P 49 TCP1_RSDS_A1N 50 TCP1_RSDS_A2P 51 TCP1_RSDS_A2N 52 TCP1_RSDS_A3P 53 TCP1_RSDS_A3N 54 55 56 57 58 59 60 Gnd n/c n/c 3.25V 1.08V 1.42V 0.25V 1.18V 1.25V 1.2V Gnd 1.18V 1.18V 1.28V 3.08V 1 08V 1.25V 1.25V 1 25V 1.3V 3.18V 1.3V TP White hash marks count as 5 Diode Mode Readings taken with all connectors Disconnected.18V 1.18V Gnd 1.42V 0.

P310 Connector "Center X Board“ to ”Control Board” P102
P310 "X-Cent" to P102 "Control" Pin 1 2 3 4 5 6 7 8 9 10 Label Gnd BLK1 P0C1 CE2_2 CE1_2 X_SUS_DN2 X SUS DN2 X_ER_DN2 STB5 STB4 Gnd Run Gnd 1.89V 1.89V 0.42V 0.42V 0.42V 0 42V 0.42V 3.2V 3.2V Gnd Diode Check Gnd Open Open Open Open Open O Open Open Open Gnd Open Open Open Open Open p Open Gnd Open Open Gnd Open Open Pin Label Run 1.25V 1.18V 1.25V 1.18V Gnd 1.25V 1 25V 1.18V 1.25V 1.18V 1.25V 1.18V 1 18V Gnd 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd Diode Check Open Open Open Open Gnd Open O Open Open Open Open Open Gnd Open Open Gnd Open p Open Open Open Open Open Gnd Pin 45 46 47 Label RSDS_CLK_P0 RSDS_CLK_N0 Gnd Run 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1 25V 1.18V 1.25V 1.18V Gnd n/c n/c 3.28V 3.28V 3.28V 3.28V 3.28V Diode Check Open Open Gnd Open Open Open O Open Open Open Gnd Open Open Open Open Open Open p Open 23 TCP9_RSDS_A2P 24 TCP9_RSDS_A2N 25 TCP9_RSDS_A3P 26 TCP9_RSDS_A3N 27 Gnd

48 TCP6_RSDS_A1P 49 TCP6_RSDS_A1N 50 TCP6 RSDS A2P TCP6_RSDS_A2P 51 TCP6_RSDS_A2N 52 TCP6_RSDS_A3P 53 TCP6_RSDS_A3N 54 55 56 57 58 59 60 60 Gnd n/c n/c 3.3V 3.3V 3.3V 3.3V 3.3V

28 TCP8 RSDS A1P TCP8_RSDS_A1P 29 TCP8_RSDS_A1N 30 TCP8_RSDS_A2P 31 TCP8_RSDS_A2N 32 TCP8_RSDS_A3P 33 TCP8 RSDS A3N TCP8_RSDS_A3N 34 35 36 37 Gnd RSDS_CLK_P1 RSDS_CLK_N1 Gnd

11 TCP10 RSDS A1P 1 25V TCP10_RSDS_A1P 1.25V 12 TCP10_RSDS_A1N 1.18V 13 TCP10_RSDS_A2P 1.25V 14 TCP10_RSDS_A2N 1.18V 15 TCP10_RSDS_A3P 1.25V 16 TCP10_RSDS_A3N 1.18V 17 18 19 20 21 22 Gnd RSDS_CLK_P3 RSDS_CLK_N3 Gnd TCP9_RSDS_A1P TCP9_RSDS_A1N Gnd 1.08V 1.34V Gnd 1.25V 1.18V

38 TCP7_RSDS_A1P 39 TCP7_RSDS_A1N 40 TCP7_RSDS_A2P 41 TCP7_RSDS_A2N 42 TCP7_RSDS_A3P 43 TCP7_RSDS_A3N 44 Gnd

57~60

1

57~60 pins 3.3V TP

White hash marks count as 5 t

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

133

May 201 50PV450 1

Plasma

P310 Connector “Right X Board” to “Control” P104
P310 "X-Right" to P104 "Control"
Pin 1 2 3 4 5 6 7 8 9 10 Label Gnd BLK1 P0C1 CE2_2 CE1_2 X_SUS_DN2 X SUS DN2 X_ER_DN2 STB5 STB4 Gnd Run Gnd 1.89V 1.89V 0.42V 0.42V 0.42V 0 42V 0.42V 3.2V 3.2V Gnd Diode Check Gnd Open Open Open Open Open Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Pin Label Run 1.25V 1.18V 1.25V 1.18V Gnd 1.25V 1 25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1.18V 1.25V 1.18V Gnd Diode Check Open p Open Open Open Gnd Open Open Open Open Open Open Gnd Open Open Gnd Open Open Open Open Open Open Gnd Pin 45 46 47 Label RSDS_CLK_PB RSDS_CLK_NB Gnd Run 1.08V 1.34V Gnd 1.25V 1.18V 1.25V 1 25V 1.18V 1.25V 1.18V Gnd n/c n/c 3.28V 3.28V 3.28V 3.28V Diode Check Open p Open Gnd Open Open Open Open Open Open Gnd Open Open Open Open Open Open 23 TCP14_RSDS_A2P 24 TCP14_RSDS_A2N 25 TCP14_RSDS_A3P 26 TCP14_RSDS_A3N 27 Gnd

48 TCP11_RSDS_A1P 49 TCP11_RSDS_A1N 50 TCP11 RSDS A2P TCP11_RSDS_A2P 51 TCP11_RSDS_A2N 52 TCP11_RSDS_A3P 53 TCP11_RSDS_A3N 54 55 56 57 58 59 60 Gnd n/c n/c 3.3V 3.3V 3.3V 3.3V

28 TCP13 RSDS A1P TCP13_RSDS_A1P 29 TCP13_RSDS_A1N 30 TCP13_RSDS_A2P 31 TCP13_RSDS_A2N 32 TCP13_RSDS_A3P 33 TCP13_RSDS_A3N 34 35 36 37 Gnd RSDS_CLK_P9 RSDS_CLK_N9 Gnd

11 TCP15_RSDS_A1P 1.25V 12 TCP15_RSDS_A1N 1.18V 13 TCP15_RSDS_A2P 1.25V 14 TCP15_RSDS_A2N 1.18V 15 TCP15_RSDS_A3P 1.25V 16 TCP15_RSDS_A3N 1.18V 17 18 19 20 Gnd RSDS_CLK_P11 RSDS_CLK_N11 Gnd Gnd 1.08V 1.34V Gnd

38 TCP12_RSDS_A1P 39 TCP12_RSDS_A1N 40 TCP12_RSDS_A2P 41 TCP12_RSDS_A2N 42 TCP12 RSDS A3P TCP12_RSDS_A3P 43 TCP12_RSDS_A3N 44 Gnd

57~60

1

21 TCP14_RSDS_A1P 1.25V 22 TCP14_RSDS_A1N 1.18V

57~60 pins 3.3V TP

White hash marks count as 5 t

Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.

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MAIN BOARD SECTION
The following section gives detailed information about the Main board. This board contains the Microprocessor, Microprocessor Audio section, video section and all AV inputs It also receives all input signals section inputs. and processes them to be delivered to the Control board via the LVDS cable. The (VSB, 8VSB and QAM) Silicon tuner is located on the Main board. The Main board is also where the television’s software upgrades are accomplished through the USB port. This board has no mechanical adjustments. The Main Board Receives its operational voltage from the SMPS: DURING STAND BY FROM THE SMPS: STAND-BY • STBY 5V (3.4V in STBY and 5.1V during run). DURING RUN FROM THE SMPS (STBY 5V remains): • +5V for Video processing • 17V for Audio amplification

• • • •

Distributes Key_CTL_0 and Key_CTL_1 to the Front IR Board for Front Key Pad detection. Receives Intelligent Sensor data from the Front IR/Key Board (via SCL/SDA). Drives front Power LEDs. Distributes +3.3V_ST and 5V_MST to the Front IR Board.

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Main Board Layout and Identification P701 LVDS P301 to SMPS IC1 Microprocessor Video processor p P704 to Ft IR USB 1 P801 Speakers Silicon Tuner HDMI 2 HDMI 1 HDMI 3 136 May 201 50PV450 1 Plasma .

3VST L313 IC308 1.50PV450 Main (Front and Back) Layout Drawing P301 "Main" to P813 "SMPS" Pin 1-2 3-4 5-7 8 9-12 13-14 15 16 17 18 Stby 0V Gnd 0.7V 6 Gnd Gnd 7 3.1V 2.9V Gnd 5.1V Run 17V Gnd 5.05V Gnd 1.5V P704 "MAIN" to "Front IR" Label STBY Pin IR 1 3.87V Gnd Gnd 3.3V_MST Mstar D1 A2 C A1 IC801 IC402 X1 12Mhz Micro/Video Microprocessor Q304 B EG C S D IC304 Out In OG X402 25Mhz TUNER E Q504 HDMI3 B E C P801 EDID B 4 3 1 2 Audio Amp IC703 D502 E C 3.02V 2.4V 3.2V Gnd Diode OL Gnd 0.1V Gnd Gnd 9 10 3.19V 14 n/c n/c 15 n/c n/c RUN P704 2 IC704 USB 5V PVSB Processor Diode Open Open Open Open Diode Chk 3.24V 1.14V Gnd 1.18V 1.5V R+ 2 0V 8.3_MST 0V 12 0V LED_Blue 13 Touch_Ver_Check 0.8V_TU RGB & Earphone Audio AV IN 2 137 May 2011 50PV450 Plasma .3V_TU IC503 EDID C Q702 A2 A1 B C E Q503 IC602 E B C IC307 2 D504 1.3V 5 LED_Red 2.5V L3 0V 8.9V Gnd 3.75V OL OL IC303 3.1V EYE_SCL 8 EYE_SDA 3.3V 3.875Mhz Q404 123 Q502 CEC FET Q501 A2 A1 C IC504 EDID R L V IC401 Tuner Control 2 123 IC305 3.3V 0V Gnd 3.8V_MST Q302 5V_MST IC202 IC203 IC501 NVRAM HDCP Flash Memory P801 "Main" to "Speakers" Pin Label SBY Run R1 0V 8.6V 2.3V 1.92V OL Gnd P701 MAIN BOARD p/n: EBU60952917 or p/n: EBR72650101 P301 G D2 Q301 B C S E Gnd Out C A1 A2 IC201 DDR IC301 123 2 IC302 3.3V_VDDC In 1 2 3 D 1.19V n/c n/c RS232 Buffer Grayed Out Components are on the back Q303 +3.1V Gnd 3.4V Stby_5V a 0V RL_ON ad AC_Det 0V b 0V M_On e Auto_Gnd Gnd Label a 17V Gnd a 5.3V 3.1V 4.3V 5V 0V 0.1V 3.3V_MST +1.3V 2 Gnd Gnd Key_Ctl_0 3 3.88V 3.3V 4 Key_Ctl_1 3.2V_DVDD Q402 B C B E C D505 A1 C A2 IC502 D501 C B E X401 31.02V 1.18V OL Gnd OL OL Gnd 1.5V L+ 4 0V 8.46V ac Error_Det 2.4V 4.3_VST 11 3.

5V) IC801 D1 C A1 A2 X1 12Mhz Micro/Video Microprocessor X402 25Mhz PVSB Processor P801 CEC FET 4 1 3 2 Audio Amp TUNER E Q402 B C B E C X401 31.50PV450 Main Front Layout Drawing MAIN BOARD p/n: EBU60952917 or p/n: EBR72650101 P701 P301 D2 C A2 A1 IC201 DDR IC203 L313 IC308 1.875Mhz Q502 IC401 Tuner Control Q404 D505 A1 A2 C D501 A1 C A2 R L V AV IN 2 D504 A1 C A2 138 May 2011 50PV450 Plasma .3V_VDDC P704 Flash Memory HDMI3 IC402 Mstar To Speakers (All Pins 8.

1V 1.3V [16] Q402 0V Gnd n/c n/c n/c n/c 0.7V Gnd Tuner SIF Buffer (Digital) 1.50PV450 Main Board Front Side Component Voltages IC203 inbond Serial Pin Flash [1] 3.08V Pin [B] [E] [C] Q404 Pin [B] [E] [C] Q502 Pin [1 B] [ ] [2 S] [3 D] [4 G] Tuner CVBS Buffer (Analog) 1.2V 1.08V [15] [8] 3.3V [7] 1.3V_VDDC Pin Regulator [1] 0.8V* [2] 0V [ ] [3] 5V [4] 6.3V IC308 +1.8V Gnd HDMI CEC Buffer Gnd 3.3V [10] [3] n/c [11] [4] n/c [12] [5] n/c [13] [6] n/c [14] [7] 0.1V [5] 5V [6] 1.3V [9] [2] 3.18V 3.3V [8] 4.29V 3.08V 0.5V *Caused Video to Mute 139 .

8V_TU IC602 RGB & Earphone Audio 140 May 2011 50PV450 Plasma .3V_MST RS232 Buffer D502 E B EDID IC703 2 3 21 IC305 3.50PV450 Main Back Layout Drawing MAIN BOARD p/n: EBU60952917 or p/n: EBR72650101 IC301 321 3.3V_MST Q504 E C B IC304 Out S D Q304 GE B C G O In IC504 EDID 3 21 +1.8V_MST Q302 5V_MST 2 IC303 3.3VST IC302 Out Gnd E B C In S G D Q301 3 2 1 IC704 USB 5V IC501 IC202 HDCP NVRAM 2 1.2V_DVDD Q303 +3.3V_TU IC502 Q501 IC503 C E B C IC307 2 Q702 E B C Q503 E B C EDID 1.

Q503 Q504 Hot Swap 141 .3V Gnd 3.5V) 0V 3.3V n/c n/c 0V 5.28V Q303 3.1V 3.3V 3.50PV450 Main Board Back Side Component Voltages IC202 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC301 Pin [1] [2] [3] IC302 Pin [1] [2] [3] IC303 Pin [1] [2] [3] NVRAM IC304 Gnd Gnd Gnd Gnd 3.5V) (-5.3V with Dig [D] 3.3V Channel urns on 3.3V_PVSB Pin Dig Ch Only [G] 0V Only on [S] 3.3V 5.3V Gnd 3.3V (In) 3.3V (Out) 5.3V 3.5V) (-5.1V (In) 5.3V 3.3V_TU Regulator 2.6V 0V Gnd IC305 Pin [1] [2] [3] IC307 Pin [1] [ ] [2] [3] IC501 Pin [1] [2] [3] [4] [5] [6] [7] [8] HDMI CEC Limiter Pin [A1] 0V [A2] 3.8V_MST Regulator 0.1V (Out) n/c Q702 Pin [B] [C] [E] D502 RS232 Tx Buffer 0.09V (In) 3.28V [C] 3.3V_VST Regulator Gnd 3.2V (Out) [3] 3.3V_PVSB Q301 Driver for 5V_MST Q302 5V_MST Q304 Q501.09V 0V 5.3V 3.3V 0V 5.6V 0V 0V (-5.6V 1. IC504 EDID Data For HDMI Gnd Gnd Gnd Gnd 3.3V (In) HDCP Data EEPROM Gnd Gnd 3.3V_MST Regulator Gnd 3.3V 3.3V (B+) ( ) USB 5V Limiter Gnd 5.3V 3.3V (Out) 5.8V (Out) 3.1V (Out) 5.04V (In) 1.3V 1.3V 3.09V 5.3V 3.8V (Out) ( ) 3.2V_DVDD Reg Pin Dig Ch Only [1] Gnd [2] 1.8V_TU Regulator Gnd 1.1V (In) 3.3V (Out) 5.1V (In) 1.3V (In) 3.6V Gnd 3.3V IC602 Pin [1] [ ] [2] [3] [4] [5] [6] [7] [8] IC502 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC503.09V IC703 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [ ] [16] IC704 Pin [1] [2] [3] [4] [5] [6] [7] [8] RS232 Tx/Rx 3.3V RGB Earphone Amp Gnd Gnd Gnd Gnd 5.

3V on IC306 and 1.Main Board Tuner Explained The Tuner in this set is discreet components (Silicon Tuner) and no longer a self contained unit (can). Check for Tuner B+: 3.8V on IC307 Back Side bottom left hand side Front bottom right hand side 142 May 201 50PV450 1 Plasma .

6V X402 25MHZ X1 MAIN Board Crystal Location Left Side 2.2V p/p 143 May 201 50PV450 1 Plasma .48V 1.49V 1.8V p/p Right Side 4.Main Board Crystal X1 and X402 Check X1 12Mhz X1 1.6V p/p Right Side 3.50V p/p X402 1.58V X1 Runs all the time (Micro C t l) R ll th ti (Mi Crystal) Left Side 2.

88V 3.87V Gnd 3. Diode Mode Check with the Board Disconnected. b Note: The M-On command turns on M5V Va and Vs M5V. Error_Det and AC_DET.6V 2.2V Gnd Diode Check OL Gnd 0. If opened.4V 0V 0V 0V Gnd Run 17V Gnd 5.9V Gnd 5.1V Error_Det Gnd STBY_5V a RL_ON AC Det M_ON ad b e Auto_Gnd The RL_On command turns on the 17V. the power supply turns on automatically.4V 3.1V 2. but shut right back off. +5V.1V 4. Vs. 144 May 201 50PV450 1 Plasma .92V OL Gnd Front pins are odd Back pins are even Pin front 17V Gnd a ac 5. c Note: The Error Det line is not used in this model.02V 2.05V Gnd 1. e Note: Pin 18 is grounded on the Main.Main Board Plug P301 to Power Supply Voltages and Diode Check P301 "Main" to P813 "SMPS" Pin 1_2 34 3-4 5-7 8 9-12 13-14 15 16 17 18 a Note: P301 Label a STBY 0V Gnd 0. DVM in the Diode mode. d Note: AC Det line if missing.46V 2.4V 4. the TV will attempt to turn on.

3V 5V 0V 0.3V 3.3V 1.24V 1. 145 May 201 50PV450 1 Plasma .3V 3.1V Gnd 3.75V OL OL 1 2 3 4 5 6 1 7&8 Intelligent Sensor Stand-By 3.3V 3.3V_Multi is actually +5V_MST 7 8 9 10 11 12 13 Soft Touch Key board sensitivity 14 15 Diode Mode Readings taken with all connectors Disconnected.3V Gnd 3.19V n/c n/c / Run 3.81V 1. DVM in Diode Mode.81V OL Gnd OL OL Gnd 1.Main Board Plug P704 to Ft IR / Soft Touch Key Board Voltage and Diode Mode Measurements for the Main Board P704 "MAIN" to "Front IR" MAIN Front IR Pin Infrared Remote 3&4 Function Buttons Label IR Gnd Key_CTL_0 Key_CTL_1 LED_RED Gnd EYE_SCL EYE_SDA Gnd 3.1V 3.3V_MST LED_BLUE Touch_Ver_Check n/c n/c / STBY 3.1V Gnd 3.1V 3.3V 2.3V 0V Gnd 3.3V 0V 0V 0.7V Gnd 3.3VST 3.19V n/c n/c / Diode Check 3.9V Gnd 3.14V Gnd 1.02V 1.

5V Diode Check Open O Open Open Open 1 Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd.Main Board P801Connector Voltage and Diode Check P801 P801 "Main" to "Speakers" Pin 1 2 3 4 Label RR R+ LL+ SBY 0V 0V 0V 0V Run 8. DVM in Diode Mode.5V 8. 146 May 201 50PV450 1 Plasma .5V 8.5V 8 V 8.

3V_AMP_DVDD made by routing 3.5V Right (-) P801 Right (+) g ( ) Speaker S k Connector Left (-) Left (+) See previous page For P801 Diode Check IC801 Audio Amp Main Board Location 1 I2C Master Clk pin 15 AC_DET pin 19 LRCLK pin 20 TAS_RESET pin 25 DATA pin 23 SCLK pin 24 147 May 201 50PV450 1 Plasma . 41 (Right) +3.3.3V_Normal through L1605 3.3V_AMP_DVDD Arriving Pin 13. 35. 27 From 3. 40. 44.3V_Normal generated by IC505 Note: 3.Main Board IC801Audio Circuit Explanation AUDIO OUT Right – pin 39 Right + pin 36 Left . 45 (Left) Pins 34.pin 1 Left + pin 46 AUDIO B+ 17V Pins 2.3V_MST through a coil L801 or L802 All speaker pins 8.

(2) Pull the Cable from the Connector 148 May 201 50PV450 1 Plasma . lift up the locking mechanism. its best to lift slightly one end.Main Board P701 (Removing the LVDS Cable) (1) Using your fingernail. Since the locking tab is very thin and fragile. back and forth until the tab is released. then work across the locking tab g a little at a time.

Use the Pin cross reference chart on the left because the pins are inverted on the Control Board. Test Points are available. but there are actually 20 pins carrying video. but they are all similar. Input Si ll i il I t Signal SMPT C l B l Color Bar 1 Pin 68 RE2613mV 10MSec p/p per/div Pin 69 RE2+ TIP: Use the Control Board side for measurements.Main Board P701 LVDS Video Signal Checks Pin Pin Ctl Board Main Board 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 50 31 49 32 48 33 47 34 46 35 45 36 44 37 43 38 42 39 41 40 Pin Pin Ctl Board Main Board 40 41 39 42 38 43 37 44 36 45 35 46 34 47 33 48 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 24 57 23 58 22 59 21 60 20 61 19 62 18 63 17 64 16 65 15 66 14 67 13 68 12 69 11 70 10 71 9 72 8 73 7 74 6 75 5 76 4 77 3 78 2 79 1 80 Example Waveforms Taken from P701 pins 68 and 68. Main Board P701 Location 149 May 201 50PV450 1 Plasma .

48V 2.73V Gnd 0. Stand By voltages Note: Use the Control Board for Voltage Measurements.04V 0.Main Board Plug P701 “LVDS” Voltages P701 "Main LVDS" to P31 "Control" Note: For Voltage Measurements.3V Gnd 1.8V 3.2V 1.73V 0.11V 1.73V 0.5V Gnd Gnd 1 Bold Indicates video signal Note: No Stand-By voltages.6V 1.3V 1.44V 0.11V 1. di Diode Mode Readings taken with all connectors Disconnected.73V 0.73V Gnd n/c n/c n/c n/c 2.11V 1.2V 1.73V Gnd 0.73V 0.17V OL OL Gnd G d OL OL OL OL Gnd OL OL Gnd OL OL OL OL OL OL Gnd Gnd OL OL OL Pin 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Label n/c Gnd n/c n/c Gnd n/c n/c / n/c n/c n/c n/c Gnd Gnd RA1RA1+ RB1RB1+ Gnd RC1RC1+ Gnd RCLK1RCLK1RD1RD1+ RE1RE1+ Run n/c Gnd n/c n/c Gnd n/c n/c / n/c n/c n/c n/c Gnd Gnd 1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Label Gnd n/c ROM_RX ROM_TX n/c n/c Gnd G d n/c n/c n/c n/c Gnd n/c n/c Gnd n/c n/c n/c n/c n/c n/c Gnd Gnd n/c n/c n/c Run Gnd n/c 3. use the Control Board.3V 2. 150 May 201 50PV450 1 Plasma .73V Pin 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Label Gnd Gnd RA2RA2+ RB2RB2+ Gnd G d RC2RC2+ Gnd RCLK2RCLK2RD2RD2+ RE2RE2+ Gnd n/c n/c n/c n/c Module_SDA1 DISP_EN _ Module_SCL1 Voltage and Diode Test for the Main Board Run Diode Gnd Gnd 0.11V 1.3V Gnd 1.11V 1.3V PC_SER_CLK 0.73V 0.73V Gnd 0.17V 1.3V Gnd G d 1.73V 0.11V 1.11V 1.11V 1.73V 0.11V 1.73V 0.3V n/c n/c Gnd G d n/c n/c n/c n/c Gnd n/c n/c Gnd n/c n/c n/c n/c n/c n/c Gnd Gnd n/c n/c n/c Diode Gnd OL 1. DVM in Diode Mode.3V 1.3V Gnd n/c n/c n/c n/c 3.3V Gnd 1.3V 1.3V 1.3V 3.73V 1.98V Gnd Gnd Gnd 1.73V 0.73V Gnd G d 0.2V 1.04V 0.2V 1.73V 0.3V PC_SER_DATA 3.73V 1.73V 0.3V Diode OL Gnd OL OL Gnd OL OL OL OL OL OL Gnd Gnd 0.73V 0.11V 1.73V 0. See Pin cross reference table t bl on preceding page.73V 0.6V 0.

Pin 13 is Touch Version Check pin to adjust the sensitivity of the Soft Touch Keys. It arrives on the IR/STKB at P100 pin 11. The IR/STKB board contains the Infrared Remote Receiver. adjustments The IR/STKB receives its operational B+ from the Main Board: • • 3. (Removing the panel allows better access).FRONT IR / SOFT TOUCH KEY BOARD SECTION The following section gives detailed information about the Front IR and Soft Touch Key board (IR/STKB). 3. 151 May 201 50PV450 1 Plasma . This voltage is generated on the Power Supply. It is output on P704 pin 10. It requires a great deal of disassembly to reach. decoder. It arrives on the IR/STKB at P100 pin 10. After removing the bottom metal shield plate. The IR signal is routed back to the Main Board via pin 1.3V_ST from the Main Board. The IR/STKB also has the Power LEDs. Note: The IR/STKB is attached to the Televisions Front Frame. the panel screws must be removed to lift up the panel in order to see the board. This sensor monitors the average room light and configures this information in data form back to the Microprocessor to manipulate brightness and color settings to correspond to room lighting conditions. The Intelligent sensor is driven by 2 separate pins from the Main board SCL/SDA P100 pins 7 and 8. Intelligent Sensor and Soft Touch Key Board decoder This board has no adjustments. The control for the Power LEDs is routed in P100 pins 5 (LED_RED) (LED RED) and 12 (LED BLUE) (LED_BLUE).3V_MST Generated on the Main Board by IC303 and output on P704 pin 11.

Note: The IR/STKB is attached to the Televisions Front Frame.24V 2. the panel screws must be removed to lift up the panel in order to see the board. It requires a great deal of q g disassembly to reach.IR / Soft Touch Key board and Intelligent Sensor Location Assembled Lower Left Side As viewed from rear.85V 2 85V 152 May 201 50PV450 1 Plasma . After removing the bottom metal shield plate. IC102 IR Receiver O G V IC102 IR Receiver Label V: B+ O: Output G: G G Ground d Readings 0V 3. IR Receiver P100 To Main Key Pad D Decoder d Soft Touch Key Pad is part y p of the circuit board.

86V 1 Diode Mode Readings taken with all connectors Disconnected.49V Gnd 3.48V Gnd G d 0.88V 1.88V 1. DVM in Diode Mode.28V 3.55V 3.92V Gnd 3. 153 May 201 50PV450 1 Plasma . Black lead on Gnd.9V 2.45V Gnd G d 3.P901 (IR / STKB and Intelligent Sensor )Voltages and Pin Identification P901 Connector "MAIN Board" To "IR Board" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label SCL SDA Gnd KEY 1 KEY 2 3.49V Gnd 0V 1.28V Gnd 1.34V 0V Gnd 3.26V 3.15V Gnd OL OL Gnd G d 0.28V 3.3V_Normal LED_R/BUZZ Gnd S/T_SCL S/T_SDA STBY 2.26V 3.49V 3.86V 1.28V 3.55V Run 3.5V_ST Gnd LED_B/BUZZ IR Gnd G d +3.53V 2.49V Diode Check 3.55V Gnd 0V 1.49V 3.35V 0V Gnd 3.67V Gnd 1.

21V 1.26V Run R 3.28V 3. Intelligent Sensor Board is generating these Resistance changes when a Soft Touch Key is touched.28V 154 May 201 50PV450 1 Plasma .88V P900 “Main” (No Key Pressed) Pin Pi 3 4 Label L b l KEY 1 KEY 2 STBY 3.26V 3. Power CH (Up) CH (Dn) Input Pin 3 measured from Gnd 2.Soft Touch Key Pad Voltage Checks P1 Voltage Measurements with Soft Touch Key pressed.6V 0.6V 0.4V 0. touched This in turn pulls down the Key 1 and Key 2 lines to be interpreted by the Microprocessor.21V 1. Soft Touch K S ft T h Keys.88V KEY 2 Enter Volume (-) Menu Volume (+) Key 2 Line Pin 4 measured from Gnd 2. Key 1 Line KEY 1 IC100 on the Front IR.4V 0.

Front View Rear View Speaker Connection 155 May 201 50PV450 1 Plasma . 8. The Full Range Speakers point downward.2 ohm.INVISIBLE SPEAKER SYSTEM SECTION Invisible Speaker System Overview (Full Range Speakers) p/n: EAB62028901 The 50PV450 contains the Invisible Speaker system system. Installed Bottom View Anti Rattle Pad Anti Rattle Pad Remove two screws from the bottom Reading across speaker wires. so there are no front viewable speaker grills or air ports.

reading When Printing the Interconnect diagram.INTERCONNECT DIAGRAM (11 X 17 Foldout) SECTION This section shows the Interconnect Diagram called the 1 1X17 foldout that’s available in the Paper and Adobe version of the p Training Manual. i for best lt 156 May 201 50PV450 1 Plasma . Use the Adobe version to zoom in for easier reading. print from the Adobe version and print onto 1 i d i t t 1X17 size paper f b t results.

454V p/p with Y-Drives 386V p/p without Y-Drives To Test Control board: Disconnect all connectors.73V 0.24V 1.3V 3.3V) IC53 P104 To Right X Board IC302 3.52V Gnd Gnd Open Open Open Open Open Open Open Open 15 14 13 12 11 10 9 8 7 6 5 4 3 ER_UP ER_DN SUS_DN J21 18V D111 D108 VA Adj VR502 P214 IC501 P210 T502 VR500 +Vy VSC R548 23.3V) IC53 L2 C65 1.96V 2. IC191 1 5VFG 2 FGnd 3 10. Apply AC.04V 1.74V Gnd 0.26V Gnd X1 0.89V Gnd IC51 FL5 IC61 M5V P2 4.3V in on Pins 57~60 P203 X-Board Center p/n: EBR71728401 P204 P321 Va out on Pins 1~2 P205 P320 Va in on Pins 1~2 P201 P310 3.73V Gnd 0V Gnd 1. J54 290V p/p (More square shape).38V Disconnected FS501 18V Diode Check reads 1. Jump STBY 5V from SMPS P813 Pin 13. see (To Test Power Supply) J113 Y-SUS EBR69839001 P212 FGnd Y-Scan P202 FPC Waveform P213 Scan Data M5V Y-Drive Lower P203 J81 Gnd CTRL_OE CTRL_OE should be 0V (5V indicates a Problem) M5V P216 P102 Ribbon Cable Y-SUS and Y Drive Signals Pins 6-8 (18V) Pins 3-5 (5V) Pins 23-25 (18V) Pins 26-28 (5V) P105 To Y-SUS Board C61 P22 n/c IC101 IC102 3) 4.1V 2.1V STBY 390V Run P2 "Control" to "Z-SUS Board" P201 Diode Open Open 1.18V 1.15V 2.1V OL OL Note a: The RL_On command turns on the 17V.69V P101 P203 "Y-SUS" to "X-Drive Left" P121 P214 "Y-SUS" to "Upper Y-Drive" P111 P215 "Y-SUS" to "Upper Y-Drive" P112 Pin 1-2 3-12 Label FG10.3V in on Pins 57~60 P202 TCP On Va (Open) On 3. Observe Control board LED.13V 2.9VFG D512 FS202 (M5V) 10A / 125V D515 P112 Y-Scan FGnd 18.14V Gnd 1.49V 0.28V Board Connected or 1.9V Gnd 3. if it’s on.50PV450 (50R3 Panel) CIRCUIT INTERCONNECT DIAGRAM P813 "SMPS" to P301 "Main" VR402 Set-up P101 FPC 345V p/p ± 5V 107VRMS P811 "Power Supply" to P210 "Y-SUS" A 0V 100V 2MSec 560V p/p Pin Label Run Diode Open n/c Gnd Open 1. the power supply turn on automatically.3_VST 3.9V FGnd J33 +Vy R527 D502 D505 FS203 (VS) 6.84V 3.52V 1.9V P203 1-2) ER 3) n/c 4-5) VS 6) n/c 7-8) Gnd Connect Scope between Waveform TP J54 on Z board and Gnd. 2 PANEL TEST: Remove LVDS Cable.3V 0.2 3 4.63V 25 Mhz 1.0V VR401 Set-Dn Y-Drive Upper P102 FPC 4~5 6 Pin 1-2 3-4 5-7 8 9-12 13-14 15 16 17 18 WARNING: Remove Y-Drives completely if P213 is removed.875Mhz Q404 123 Q501 CEC FET A2 A1 C 1 2 Q502 IC401 Tuner Control 2 123 IC504 EDID R L V P121 “X Left” to P203 “Y-SUS” Pin 1.38V 1.73V Board Connected or 1.3V Regulator) routed to all X Boards * If the complaint is no video and shorting the points (AutoGen) causes video to appear suspect the Main board or LVDS cable.1V Gnd 3.3V 2.96V 4.27V Diode Check To Left X Board IC1 CONTROL BOARD p/n: EBR71727801 AUTO Gen Ribbon Cable LVDS See 2nd page for Waveforms MAIN BOARD p/n: EBU60952917 or p/n: EBR72650101 P701 P301 Q301 B C E Gnd Out Pin 1-2 3 *4-5 Run Gnd nc VA Voltage Diode Check Gnd nc Open 1-4 (3.85V Gnd 1.3V 3.5 Run VA Voltage nc Gnd Diode Check Open nc Gnd P201 P204 IC305 3. Jump VS from SMPS to Z-SUS P203.85V Gnd 1.3V_VDDC In S P704 "MAIN" to "Front IR" Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Label IR Gnd Key_Ctl_0 Key_Ctl_1 LED_Red Gnd EYE_SCL EYE_SDA Gnd 3.5V P203 Diode Open Open Open Open IC25 1.1V 2.3V 5V 0V 0. Va and Vs.06V Gnd 2.73V 2.9VFG VS Adj VR901 Diode Open n/c Open n/c Gnd Gnd Gnd D110 P811 Q102 Z-SUS EBR71727901 P204 D114 P201 P218 D503 T500 P111 FG10. all voltage should run.89V FGnd Pin 1-7 8 9-12 Label FGnd n/c Vscan Run FGnd n/c 107V P213 "Y-SUS" to "Lower "Y-Drive" P213 Pin 1 2 3 4 5 6 7 8 Label M5V M5V OC2_B Gnd DATA_B Gnd OC1_B OC2_T Gnd DATA_T Gnd OC1_T Gnd CLK STB Run 4.1V 4.85V 1. Apply AC and turn on the Set. FL2.34V 18.77V Gnd 0V Gnd 1.53V OL 3.68V 4.02V D1 IC11 1. Jump Audio B+ from SMPS to J21 on the Z-SUS.52V 1.5V R+ 2 0V 8.85V Gnd 1. If opened. Use RMS information just to check for board activity.8V_TU Ft IR/Key Pad RGB & Earphone Audio AV IN 2 Attached to front glass P121 X-Board Left p/n: EBR71728101 P203 P204 P310 3. Short across Auto Gen TPs to generate a test pattern.26V P203 P213 Chassis Gnd FL1/2 1-4 (3.7V Gnd 3.3A / 250V 57VRms Q106 VZB TP R156 Q113 D118 Q114 57VRMS 50V 2MSec 288V p/p Connect Scope between Waveform TP on Y-Drive and Gnd FS201 Va or FS203 Vs Diode Check reads Open with Board Disconnected or Connected FS202 M5V Diode Check reads 0. Note e: Pin 18 is grounded on the Main.89V Gnd Gnd 0.3V 1.84V Gnd 2. IC303 3.52V Disconnected Z-SUS Signal 100uSec Q109 261V p/p VR101 VZB Adj Q104 FS201 (VS) 6.3V_MST Q402 B C B E C D505 A1 C A2 IC502 D501 C B E E C X401 31.02V 1.3V) IC53 Gnd 3. If all supplies do not run when A/C is applied.3A / 250V D500 IC50 0 F302/F801 160. If missing.85V Open Gnd 1. jump 5V to Fuse FS202.85V L1 D1 Blinks Indicating Board is Functioning 1. P206 P103 Z-SUB BOARD p/n: EBR71728001 P217 With the unit on. FS201 Vs Diode Check reads Open with Board Disconnected or Connected FS202 M5V Diode Check reads 0.9VFG 180uSec ± 5uSec 100V 100uS 560V p/p 7 *Voltage varies with panel label Stby 0V Gnd 0.3V 1) Gnd C72 4.38V Open Gnd 1.2V Gnd Diode 3.31V Disconnected Y-DRIVE UPPER BOARD p/n: EBR69839101 VS VS n/c Gnd Gnd Va M5V VA TP VS TP F801 4A/250V FPC IC191 Waveform 2 1 3 2 VR501 VSC 10. Note b: The M-On command turns on M5V.34V n/c 4.1V Run 17V Gnd 5.4V 4.3V 0V 0V 0.53V 0.77VFG D501 D511 10.19V n/c n/c Diode Chk 3.34V IC302 P215 P121 VR401 Set-Dn VScan FGnd FS501 (18V) 2A / 125V FS201 (VA) 4A / 125V P221 P211 P201 FPC FGnd Y-Scan C540 VR402 Set-Up SMPS Test – Unplug P813 to Main board.5V L3 0V 8.8V_MST FPC Black Lead on Floating Gnd P216 "Y-SUS" to "Lower Y-Drive" P212 Pin 1-10 11-12 Label FGnd Vscan Run FGnd 107V *Voltage varies with panel label Q302 5V_MST IC202 IC203 IC501 HDCP Black Lead on Floating Gnd Black Lead on Floating Gnd Chassis Gnd 9 10 11 12 13 14 15 FPC Use left side of C540 to measure Y-Drive signal without Y-Drive. If present replace the Control Board.3VST L313 IC308 1.93V 2) 3.4V 3.65V Q1 P31 LVDS D2 C A1 A2 1.3V_TU IC503 EDID C P100 Diode Check Va: Open Blk on Gnd. Error_Det and AC_DET. Note d: AC Det if missing TV will attempt to turn on but shuts back off.89V M5V FL1. FL5 18V To Z-SUS (In P105 pins 14-15) (Out P2 pins 14-15) Diode Check All Connectors Connected 1. disconnect P811 to isolate the excessive load.3V (1. Hot Ground F302 2.18V OL Gnd OL OL Gnd 1. Disconnect Y-SUS from Control board and from the Z-SUS.38V B 1~2 3 Vs n/c Gnd Va M5V *201V n/c Gnd *55V 5.1V Gnd 3.1V 3.28V P801 "Main" to "Speakers" Pin Label SBY Run R1 0V 8. check 5V supply. +5V.9V Gnd 5.3V 0V Gnd 3.15V) On EC (Open) X-Board Right p/n: EBR71728501 P205 P202 P203 P204 .75V OL OL G To Ft IR A 1 2 3 D 1.46V ac Error_Det 2.2V_DVDD IC304 Out In OG X402 25Mhz TUNER E Q504 HDMI3 B E C P801 EDID Audio Amp IC703 RS232 Buffer D502 B 4 3 Grayed Out Components are on the back Q303 +3. Q702 A2 A1 B C E Black Lead on Chassis Gnd Y-DRIVE LOWER BOARD p/n: EBR69839201 IR/Key Board p/n: EBR72650101 P110 3.89V 4. most likely Control board is OK.1V 3.73V Board Connected 1.04V C76 3.5V L+ 4 0V 8.5A/ 250V POWER SUPPLY p/n: EAY62171101 J16 M5V Q107 J54 Z-Drive Waveform TP P101 P103 P104 Q103 Q110 P205 P102 P202 P201 FS202 (M5V) 4A / 125V P201 Pins inverted from P2 on Control P104 FPC RL103 F101 10A/250V 2 1 P813 AC In P701 n/c To run Z-SUS stand-alone. Note: LVDS Cable must be removed for Auto Gen to work.9V FGnd Run 4.87V 1.4V Stby_5V a 0V RL_ON ad 0V AC_Det b 0V M_On e Auto_Gnd Gnd Label a 17V Gnd a 5.29V 1) Gnd C52 Gnd 4.84V VS-DA TP 1. if D1 is not on.04V M5V 1.3V in on Pins 57~60 P120 Va out on Pins 1~2 P205 P320 Va in on Pins 1~2 P201 P202 To P704 Main A Q503 IC602 E B C IC307 2 D504 1.3V Gnd 3.3_MST LED_Blue Touch_Ver_Check n/c n/c STBY 3.06V 0. Note c: The Error Det line is not used in this model.19V n/c n/c RUN 3.87V Gnd Gnd 3. Use two (100W) light bulbs in series between Vs and Gnd to place a load on the SMPS. P704 IC704 USB 5V NVRAM Note: IC53 (3.89V 2) 3. P203 "Z-SUS" to "Y-SUS" P218 Pin Label Run 1~2 ER_PASS 98V~102V 3 n/c n/c 4~5 +Vs *201V 6 n/c n/c 7~18 Gnd Gnd *Voltage varies with panel label Pin Label (+15V) (+15V) n/c M5V M5V Gnd Gnd SUS_DN CTRL_EN SUS_UP VZB2 ER_DN VZB1 ER_UP ZBIAS Run 18.3V_MST Flash Memory Mstar D1 A2 C A1 PVSB Processor To Speakers IC801 IC402 X1 12Mhz Micro/Video Microprocessor Q304 B EG C S D +1.85V P102 To Center X Board 3) 4.89V IC201 DDR IC301 12 3 2 IC53 Black Lead on Floating Gnd P217 "Y-SUS" to "Lower Y-Drive" P211 Pin 1-4 5 6-12 Label Vscan n/c FGnd Run 107V n/c FGnd 1-4 (3. See “Auto Gen” on the Control board to perform a Panel Test.

All readings give their Time Base related to scope settings.Video Signal P31 LVDS (Pin 32) 10Msec / 695mV Note: Pin 33 is Same but Inverted Bottom Waveform at 2uSec CLK2_.Video Signal P31 LVDS (Pin 38) 10Msec / 778.Video Signal P31 LVDS (Pin 16) 10Msec / 638mV Note: Pin 17 is Same but Inverted CLK1_. Video Video Video Video Video Video NOTE: LVDS P31 Information There are actually 40 pins carrying Video.Video Signal P31 LVDS (Pin 22) 10Msec / 714.50PV450 LVDS P31 Control Board from P701 Main Board Waveform Samples P31 Control 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P701 Main 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RA1_.Clock Signal P31 LVDS (Pin 35) 10Msec / 716.Video Signal P31 LVDS (Pin 24) 10Msec / 686.6mV Note: Pin 23 is Same but Inverted Bottom Waveform at 2uSec RE1_.Video Signal P31 LVDS (Pin 30) 10Msec / 582.Video Signal RXD TXD RB1_.2mV Note: Pin 39 is Same but Inverted Bottom Waveform at 2uSec Video Video Video Video CLK CLK The reset of the waveforms look very similar to the ones shown.5mV Note: Pin 15 is Same but Inverted RC1_.Video Signal P31 LVDS (Pin 14) 10Msec / 627.Video Signal P31 LVDS (Pin 28) 10Msec / 715.5mV Note: Pin 36 is Same but Inverted Bottom Waveform at 2uSec RD2_. 8 pins are carrying clock signals to the Control board.7mV Note: Pin 29 is Same but Inverted Bottom Waveform at 2uSec RB2_.7mV Note: Pin 25 is Same but Inverted Bottom Waveform at 2uSec RA2_. Disp_En Bottom Waveform at 2uSec Bottom Waveform at 2uSec Bottom Waveform at 2uSec .Clock Signal P31 LVDS (Pin 19) 10Msec / 638mV Note: Pin 20 is Same but Inverted P31 LVDS (Pin 12) 10Msec / 613mV Note: Pin 13 is Same but Inverted Bottom Waveform at 2uSec RD1_.8mV Note: Pin 31 is Same but Inverted Video Video Video Video CLK CLK Video Video Video Video Video Video Bottom Waveform at 2uSec RC2_. WAVEFORMS: Waveforms taken using 1080P SMTP Color Bar input.

09V 0V 5.3V D1 Pin [A1] [A] [A2] D2 Pin [A1] [C] [A2] Reset Speed Up Gnd 0V Gnd LED-R Routing 0V 0.3V 3.3V 3.09V IC703 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] IC704 Pin [1] [2] [3] [4] [5] [6] [7] [8] RS232 Tx/Rx Q301 3.2V 1.54V 5.08V IC308 +1.29V 3.1V 3.1V (In) 1.0V D501 Pin [A1] [A] [A2] B+ Routing to IC502 5.8V_MST Regulator 0.08V 0.3V_MST Regulator Gnd 3.2V_DVDD Reg Pin Dig Ch Only [1] Gnd [2] 1.3V Gnd G d 3.64V Only on y with Dig [C] 0V [E] Gnd Channel Q304 Q501. IC504 EDID Data For HDMI Gnd Gnd Gnd Gnd 3.5V) (-5.5V) (-5.3V (Out) 5.3V_VST Regulator Gnd 3.2V (Out) [3] 3.1V (In) 3.3V 0V 5.55V 0V 50PV450 Main Board (Back Side) Component Voltages IC202 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC301 Pin [1] [2] [3] IC302 Pin [1] [2] [3] NVRAM IC303 Pin [1] [2] [3] IC304 3.55V 0V B+ Routing to IC504 0V 4.3V Gnd 3.6V [C] 0V [E] Gnd 5V_MST Switch 0V 5.6V 0V Gnd Gnd Gnd Gnd G d Gnd 3.3V RGB Earphone Amp Gnd Gnd Gnd Gnd 5.28V [C] 3.1V 4.3V 3.8V (Out) 3.3V 3.09V (In) IC305 Pin [1] [2] [3] IC307 Pin [1] [2] [3] 3.28V D504 Pin [A1] [A] [A2] D505 Pin [A1] [A] [A2] B+ Routing to IC503 5.13V 0.09V 5V Q702 Pin [B] [C] [E] D502 RS232 Tx Buffer 0.3V (Out) 5.3V Channel urns on 3.3V IC503.3V n/c n/c 0V 5.3V n/c n/c n/c n/c 0.3V 1.3V (In) IC602 Pin [1] [2] [3] [4] [5] [6] [7] [8] Pin [1] [2] [3] [4] [5] [6] [7] [8] HDCP Data EEPROM Gnd Gnd 3.5V *Caused Video to Mute Q402 Pin [B] [E] [C] Q404 Pin [B] [E] [C] Q502 Pin [1 B] [2 S] [3 D] [4 G] Tuner CVBS Buffer (Analog) 1.5V) 0V 3. Q503 Q504 Pin [B] [C] [E] Hot Swap Switch for HDMI 0V 0V Gnd .8V (Out) 3.1V (Out) 5.08V 3.3V (In) Q302 Pin [G] [S] [D] Q303 HDMI CEC Limiter Pin [A1] 0V [A2] 3.3V (B+) USB 5V Limiter Gnd 5.04V (In) IC501 Pin [1] [2] [3] [4] [5] [6] [7] [8] IC502 1.1V 4.3V [8] 4.18V 3.8V_TU Regulator Gnd 1.3V_TU Regulator 2.3V (In) 3.09V 5.1V (Out) n/c Driver for 5V_MST Pin Switch Q302 [B] 0.6V 0V 0V (-5.3V_VDDC Pin Regulator [1] 0.8V Gnd HDMI CEC Buffer Gnd 3.3V 0V Gnd n/c n/c n/c n/c 0.3V 3.3V 3.3V (Out) 5.3V_PVSB Pin Switch Q303 [B] 0.6V 1.1V [5] 5V [6] 1.3V [7] 1.1V 1.3V 3.3V 5.3V 3.3V 3.50PV450 Main Board (Front Side) Component Voltages IC203 Pin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [ ] [11] [12] [13] [14] [15] [16] Winbond Serial Flash 3.7V Gnd Tuner SIF Buffer (Digital) 1.6V Gnd 3.1V (In) 5.3V_PVSB Pin Dig Ch Only [G] 0V Only on [S] 3.3V with Dig [D] 3.8V* [2] 0V [3] 5V [4] 6.28V 3.

3. 160 May 201 50PV450 1 Plasma . So only 128 per/buffer. Page 1 “Cover page” added the updated date. There are 3 buffers per/TCP.End of the 50PV450 Presentation This concludes the Presentation Thank You Updates 06/17/2011 1. 2 Page 17 USB does not allow “Video” to be played Video played. 2. Page 126: Corrected the number of lines from the TCP.