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74F269

8-bit bidirectional binary counter


Rev. 6 14 December 2011 Product data sheet

1. General description
The 74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry look-ahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock.

2. Features and benefits


Synchronous counting and loading Built-in look-ahead carry capability Count frequency 115 MHz (typical) Supply current 95 mA (typical)

3. Ordering information
Table 1. Ordering information Package Temperature range N74F269D N74F269DB 0 C to 70 C 0 C to 70 C Name SO24 SSOP24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm Version SOT137-1 SOT340-1 Type number

NXP Semiconductors

74F269
8-bit bidirectional binary counter

4. Functional diagram

24

CTR DIV256 M1 [LOAD] M2 [COUNT] M3 [UP] M4 [DOWN] 14

23 D0 24 1 11 12 13 PE U/D CP CEP CET

22 D1

21 D2

20 D3

18 D4

17 D5

16 D6

15 D7

12 13 11

G5 G6

3, 5, 6 CT = 256 4, 5, 8 CT = 0

2, 3, 5, 6+/C7 2, 3, 5, 6

TC

14
23 22 21 20 1,7D [1] [2] [4] [8] [16] [32] [64] [128] 2 3 4 5 6 8 9 10
001aai980

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 3 4 5 6 8 9 10
001aai979

18 17 16 15

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

74F269

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Product data sheet

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74F269
8-bit bidirectional binary counter

2 D0 23 DETAIL A

Q0

3 D1 22 DETAIL A

Q1

4 D2 21 DETAIL A

Q2

5 D3 20 DETAIL A

Q3

6 D4 18 DETAIL A

Q4

8 D5 17 DETAIL A

Q5

9 D6 16 DETAIL A

Q6

10 D7 15 DETAIL A

Q7

PE CP U/D

24 11 1

CEP CET

12 13

TOGGLE DETAIL A D Q

14

TC

Dn

CP Q

PE

CP

001aal296

Fig 3.

Logic diagram

74F269

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Product data sheet Rev. 6 14 December 2011 4 of 19
74F269

NXP Semiconductors

CP U/D PE D0 D1 D2 D3 D4 D5 D6 D7 PE U/D CP CEP CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC D0 D1 D2 D3 D4 D5 D6 D7 PE U/D CP CEP CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC D0 D1 D2 D3 D4 D5 D6 D7 PE U/D CP CEP CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC D0 D1 D2 D3 D4 D5 D6 D7 PE U/D CP CEP CET Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TC

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least significant 8-bit counter

most significant 8-bit counter


001aal295

8-bit bidirectional binary counter

74F269

Fig 4.

Synchronous multistage counting scheme

NXP Semiconductors

74F269
8-bit bidirectional binary counter

5. Pinning information
5.1 Pinning
74F269
U/D Q0 Q1 Q2 Q3 Q4 GND Q5 Q6 1 2 3 4 5 6 7 8 9 24 PE 23 D0 22 D1 21 D2 20 D3 19 VCC 18 D4 17 D5 16 D6 15 D7 14 TC 13 CET
001aai981

Q7 10 CP 11 CEP 12

Fig 5.

Pin configuration SO24 and SSOP24 package

5.2 Pin description


Table 2. Symbol U/D GND CP CEP CET TC D0 to D7 VCC PE
[1]

Pin description Pin 1 7 11 12 13 14 23, 22, 21, 20, 18, 17, 16, 15 19 24 Description up or down count control input data output ground (0 V) clock input count enable parallel input (active LOW) count enable trickle input (active LOW) terminal count output (active LOW) data input supply voltage parallel enable input (active LOW) Unit load HIGH/LOW 1.0/1.0 50/33 1.0/1.0 1.0/1.0 1.0/1.0 50/33 1.0/1.0 1.0/1.0 Load value[1] HIGH/LOW 20 A/0.6 mA 1.0 mA/20 mA 20 A/0.6 mA 20 A/0.6 mA 20 A/0.6 mA 1.0 mA/20 mA 20 A/0.6 mA 20 A/0.6 mA

Q0 to Q7 2, 3, 4, 5, 6, 8, 9, 10

One FAST Unit Load (UL) is defined as 20 A in HIGH state, 0.6 A in LOW state.

74F269

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74F269
8-bit bidirectional binary counter

6. Functional description
6.1 Function table
Table 3. Function table[1] Input CP Parallel load (Dn to Qn) Count up (increment) Count down (decrement) Hold (do nothing)
[1] H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition qn = Lower case letters indicate state of referenced output prior to the LOW-to-HIGH clock transition X = dont care = LOW-to-HIGH clock transition * = The TC is LOW when CET is LOW and the counter is at terminal count Terminal count up is with all Qn outputs HIGH and terminal count down is with all Qn outputs LOW.

Operating modes

Output U/D X X h I X X CEP X X I I h X CET X X I I I h PE I l h h h h Dn I h X X X X Qn L H count up count down qn qn TC * * * * * H

74F269

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Product data sheet

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74F269
8-bit bidirectional binary counter

PE D0 D1 D2 D3 D4 D5 D6 D7 CP U/D CEP and CET Q0 Q1 Q2 Q3 Q4 Q5 Q7 Q7 TC SEQUENCE 253 LOAD 254 255 0 1 2 INHIBIT 2 1 0 255 254 253
001aal297

COUNT UP

COUNT DOWN

Fig 6.

Typical timing sequence

74F269

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74F269
8-bit bidirectional binary counter

7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VO IIK IO Tamb Tstg
[1] [2]

Parameter supply voltage input voltage output voltage input clamping current output current ambient temperature storage temperature

Conditions
[1]

Min 0.5 0.5 0.5 30 [2]

Max +7.0 +7.0 +5.5 +5 40 70 +150

Unit V V V mA mA C C

output in HIGH-state VI < 0 V output in LOW-state in free air

[1]

0 65

The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.

8. Recommended operating conditions


Table 5. Symbol VCC VIH VIL IIK IOH IOL Recommended operating conditions Parameter supply voltage HIGH-level input voltage LOW-level input voltage input clamping current HIGH-level output current LOW-level output current Conditions Min 4.5 2.0 1 Typ 5.0 Max 5.5 0.8 18 20 Unit V V V mA mA mA

74F269

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74F269
8-bit bidirectional binary counter

9. Static characteristics
Table 6. Static characteristics Conditions Min VIK VOH input clamping voltage HIGH-level output voltage VCC = 4.5 V; IIK = 18 mA VCC = 4.5 V; VI = VIL or VIH VCC = 10 %; IOH = 1 mA VCC = 5 %; IOH = 1 mA VOL LOW-level output voltage VCC = 4.5 V; IOL = 20 mA; VI = VIL or VIH VCC = 10 % VCC = 5 % II IIH IIL IO ICC input leakage current LOW-level input current output current supply current VCC = 5.5 V; VI = 7.0 V VCC = 5.5 V; VI = 0.5 V VCC = 5.5 V PE = CET = CEP = U/D = GND; VCC = 5.5 V; CP = rising edge Dn: VI = 4.5 V Dn: VI = GND
[1] [2] All typical values are measured at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[2]

Symbol Parameter

25 C Typ[1] 0.73 3.4 Max 1.2 -

40 C to +85 C Unit Min 1.2 2.5 2.7 Max V V V

0.30 0.30 -

60

0.50 0.50 100 20 0.6 150

V V A A mA mA

HIGH-level input current VCC = 5.5 V; VI = 2.7 V

93 98

120 125

mA mA

10. Dynamic characteristics


Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 13. Symbol Parameter Conditions 25 C; VCC = 5.0 V Min tPLH LOW to HIGH CP to Qn; load; PE = LOW; see Figure 7 propagation delay CP to Qn; count; PE = HIGH; see Figure 7 CP to TC; see Figure 7 CET to TC; see Figure 8 U/D to TC; see Figure 9 tPHL HIGH to LOW CP to Qn; load; PE = LOW; see Figure 7 propagation delay CP to Qn; count; PE = HIGH; see Figure 7 CP to TC; see Figure 7 CET to TC; see Figure 8 U/D to TC; see Figure 9 3.0 3.0 4.5 3.5 4.5 4.0 4.5 5.0 3.0 4.5 Typ 6.0 6.0 6.5 6.0 7.0 6.5 7.0 6.5 6.5 7.0 Max 8.5 9.0 9.5 9.0 9.0 8.5 10.0 9.5 9.0 9.5 0 C to 70 C; Unit VCC = 5.0 V 0.5 V Min 3.0 3.0 4.0 3.0 4.0 4.0 4.0 5.0 3.0 4.0 Max 9.0 10.0 10.5 10.0 10.0 9.0 10.5 10.0 10.0 10.0 ns ns ns ns ns ns ns ns ns ns

74F269

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74F269
8-bit bidirectional binary counter

Table 7. Dynamic characteristics continued GND = 0 V; for test circuit, see Figure 13. Symbol Parameter Conditions 25 C; VCC = 5.0 V Min tsu(H) set-up time HIGH Dn to CP; see Figure 10 PE to CP; see Figure 10 CEP or CET to CP; see Figure 11 U/D to CP; see Figure 12 tsu(L) set-up time LOW Dn to CP; see Figure 10 PE to CP; see Figure 10 CEP or CET to CP; see Figure 11 U/D to CP; see Figure 12 th(H) hold time HIGH Dn to CP; see Figure 10 PE to CP; see Figure 10 CEP or CET to CP; see Figure 11 U/D to CP; see Figure 12 th(L) hold time LOW Dn to CP; see Figure 10 PE to CP; see Figure 10 CEP or CET to CP; see Figure 11 U/D to CP; see Figure 12 tWH tWL fmax pulse width HIGH pulse width LOW maximum frequency CP; see Figure 7 CP; see Figure 7 see Figure 7 3.5 5.5 6.0 8.0 3.5 6.5 8.0 6.5 1.0 0 0 0 1.0 0 0 0 4.0 4.5 100 Typ 115 Max 0 C to 70 C; Unit VCC = 5.0 V 0.5 V Min 2.5 5.5 5.0 6.5 2.5 6.5 6.5 6.5 0 0 0 0 1.0 0 0 0 4.0 5.0 85 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

11. Waveforms
1/fmax VI CP input GND tWH tPHL VOH Qn, TC output VOL VM
001aal292

VM

tWL tPLH

Measurement points are given in Table 8. VM = 1.5 V VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 7.

Clock (CP) to outputs (Qn, TC) propagation delay, the clock pulse width

74F269

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74F269
8-bit bidirectional binary counter

VI CET GND tPHL VOH TC VOL


001aaa652

VM

tPLH VI

VM

Measurement points are given in Table 8. VM = 1.5 V VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 8.

Input (CET) to output (TC) propagation delay

VI U/D GND tPHL VOH TC VOL


001aaa653

VM

tPLH VI

VM

Measurement points are given in Table 8. VM = 1.5 V VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 9.

The up/down control input (U/D) to output (TC) propagation delay

VI Dn GND VI PE GND tsu(L) VI CP GND VM VM


001aal301

VM tsu th VM VM

VM

VM tsu(H) th = 0 ns

VM th = 0 ns

The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VM = 1.5 V

Fig 10. Data input (Dn), parallel enable input (PE) and clock input (CP) set-up and hold times

74F269

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74F269
8-bit bidirectional binary counter

VI CET, CEP GND th(L) tsu(L) VI CP GND VOH Qn VOL COUNT NO CHANGE
001aal302

VM

VM

VM tsu(H)

VM th(H) VM

VM

The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VM = 1.5 V VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 11. Count enable inputs (CEP and CET) and clock input (CP) set-up and hold times

VI U/D GND tsu(L) VI CP GND VOH Qn VOL COUNT DOWN COUNT UP


001aal303

VM

VM th VM

VM

VM th VM

tsu(H)

The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VM = 1.5 V VOL and VOH are the typical output voltage levels that occur with the output load.

Fig 12. Up/down count control input (U/D) and clock input (CP) set-up and hold times

74F269

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74F269
8-bit bidirectional binary counter

VI negative pulse 0V

tW 90 % VM 10 % tf tr VM 10 % tr tf 90 % VM 10 % tW
001aai298

90 %
VEXT VCC VI VO DUT
RT CL RL RL

VI positive pulse 0V

90 % VM 10 %

mna616

a. Input pulse definition


Test data is given in Table 8. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RL = Load resistance.

b. Test circuit

RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times.

Fig 13. Test circuit for measuring switching times Table 8. Input VI 3.0 V fI 1 MHz tW 500 ns tr, tf 2.5 ns Test data Load CL 50 pF RL 500 VEXT tPHL, tPLH open tPZH, tPHZ open tPZL, tPLZ 7.0 V

74F269

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74F269
8-bit bidirectional binary counter

12. Package outline


SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

A X

c y HE v M A

Z 24 13

Q A2 A1 pin 1 index Lp L 1 e bp 12 w M detail X (A 3) A

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)

8o o 0

0.9 0.4

0.012 0.096 0.004 0.089

0.019 0.013 0.014 0.009

0.419 0.043 0.055 0.394 0.016

0.035 0.004 0.016

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 14. Package outline SOT137-1 (SO24)


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Product data sheet

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74F269
8-bit bidirectional binary counter

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm

SOT340-1

A X

c y HE v M A

Z
24 13

Q A2 pin 1 index A1 (A 3) Lp L
1 12

detail X w M

bp

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8o o 0

Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 15. Package outline SOT340-1 (SSOP24)


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74F269
8-bit bidirectional binary counter

13. Abbreviations
Table 9. Acronym BiCMOS DUT ESD HBM MM Abbreviations Description Bipolar Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model

14. Revision history


Table 10. 74F269 v.6 Modifications: 74F269 v.5 74F269 v.4 74F269 v.3 74F269 v.2 Revision history Release date 20111214 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Product specification Change notice Supersedes 74F269 v.5 74F269 v.4 74F269 v.3 74F269 v.2 74F269 v.1 Document ID

Legal pages updated.

20100325 20100308 20100126 19960105

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74F269
8-bit bidirectional binary counter

15. Legal information


15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualification Production

Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Definitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customers sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customers applications and products planned, as well as for the planned application and use of customers third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customers applications or products, or the application or use by customers third party customer(s). Customer is responsible for doing all necessary testing for the customers applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customers third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customers general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
NXP B.V. 2011. All rights reserved.

15.3 Disclaimers
Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
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8-bit bidirectional binary counter
NXP Semiconductors specifications such use shall be solely at customers own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications.

Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

16. Contact information


For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

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8-bit bidirectional binary counter

17. Contents
1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2011.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 14 December 2011 Document identifier: 74F269