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Department of

Electronics & Communication Engineering


Kalpataru Institute Of Technology
Tiptur-572202
HDL LAB

EXPERIMENT NO. 1
Aim: Simulation and realization of all logic
gates.

a_in not_op
and_op
ALL LOGIC nand_op
GATES or_op
nor_op
b_in xor_op
xnor_op

Block Diagram

Truth Table For logic gates: Logic Diagram

Inputs Outputs
not_op
a_in b_in and_op nand_op or_op nor_op xor_op xnor_op
(a_in)
0 0 1 0 1 0 1 0 1
0 1 1 0 1 1 0 1 0
1 0 0 0 1 1 0 1 0
1 1 0 1 0 1 0 0 1

VHDL CODE VERILOG CODE


LIBRARY IEEE; module gates(a_in, b_in, not_op, and_op, nand_op, or_op,
USE IEEE.STD_LOGIC_1164.ALL; nor_op, xor_op, xnor_op);
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input a_in;
input b_in;
ENTITY GATES IS output not_op;
PORT ( A_IN : IN STD_LOGIC; output and_op;
B_IN : IN STD_LOGIC;
output nand_op;
NOT_OP : OUT STD_LOGIC;
output or_op;
AND_OP: OUT STD_LOGIC;
NAND_OP: OUT STD_LOGIC; output nor_op;
OR_OP : OUT STD_LOGIC; output xor_op;
NOR_OP : OUT STD_LOGIC; output xnor_op;
XOR_OP : OUT STD_LOGIC;
XNOR_OP : OUT STD_LOGIC); assign not_op= ~a_in;
END GATES; assign and_op= a_in&b_in;
assign nand_op= ~(a_in&b_in);
ARCHITECTURE BEHAVIORAL OF GATES assign or_op= a_in|b_in;
IS assign nor_op=~(a_in|b_in);
BEGIN assign xor_op= a_in^b_in;
NOT_OP <= NOT A_IN; assign xnor_op= ~(a_in^b_in);
AND_OP <= A_IN AND B_IN ;
NAND_OP <= A_IN NAND B_IN ; endmodule
OR_OP <= A_IN OR B_IN ;
NOR_OP<= A_IN NOR B_IN ;
XOR_OP <= A_IN XOR B_IN ;
XNOR_OP <= A_IN XNOR B_IN ;
END BEHAVIORAL;

1 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for VHDL code:

Waveform for verilog code:

===============================================================
UCF file(User constraint file)
NET "A_IN " LOC = "p74";
NET "B_IN " LOC = "p76";
NET "NOT_OP" LOC = "p84";
NET "AND_OP " LOC = "p85";
NET "NAND_OP " LOC = "p86";
NET "OR_OP" LOC = "p87";
NET "NOR_OP " LOC = "p89";
NET "XOR_OP " LOC = "p90";
NET "XNOR_OP " LOC = "p92";
===============================================================

Result: The logic gates design has been realized, simulated and implemented using FPGA/CPLD using
HDL codes.

Date of Completion of Exp. Staff Signature Remarks

2 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO. 2
ENABLE
Aim: Write HDL codes for the following combinational circuits.
2. a) 2 to 4 Decoder.

D_OUT (0)
Sel (0)
2-4 D_OUT (1)
DECODER
D_OUT (2)
Sel (1)
D_OUT (3)

Truth Table For 2 to 4 Decoder:


Enable Select Outputs
Lines
E S1 S0 D_OUT(3) D_OUT(2) D_OUT(1) D_OUT(0)
0 X X Z Z Z Z
0 0 0 0 0 0 1
0 0 1 0 0 1 0
0 1 0 0 1 0 0
0 1 1 1 0 0 0
1 X X 0 0 0 0
VHDL CODE VERILOG CODE
LIBRARY IEEE; module DECODER (SEL,EN,D_OUT);
USE IEEE.STD_LOGIC_1164.ALL; input [1:0] SEL;
USE IEEE.STD_LOGIC_ARITH.ALL; input EN;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; output [3:0] D_OUT;
ENTITY DECODER2_4 IS reg [3:0] D_OUT;
PORT ( ENABLE: IN STD_LOGIC; always @(SEL , EN)
SEL: IN STD_LOGIC_VECTOR (1 DOWNTO 0); if (EN==1)
D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); D_OUT=4’b0000;
END DECODER2_4; else
ARCHITECTURE DECODER_ARC OF DECODER2_4 IS begin
BEGIN case (SEL)
PROCESS (ENABLE,SEL) 2'b00: D_OUT = 4'b0001;
BEGIN 2'b01: D_OUT = 4'b0010;
IF (ENABLE = '1') THEN 2'b10:D_OUT = 4'b0100;
D_OUT <= "0000"; 2'b11: D_OUT = 4'b1000;
ELSE default: D_OUT =4'bzzzz;
CASE SEL IS endcase
WHEN "00" => D_OUT <= "0001"; end
WHEN "01" => D_OUT <= "0010"; endmodule
WHEN "10" => D_OUT <= "0100";
WHEN "11" => D_OUT <= "1000";
WHEN OTHERS =>D_OUT <= "ZZZZ";
END CASE;
END IF;
END PROCESS;
END DECODER_ARC;
Waveform for VHDL code:

3 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for verilog code:

=============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "ENABLE" LOC = "P74";
NET "SEL<0>" LOC = "P76";
NET "SEL<1>" LOC = "P77";
NET "D_OUT<0>" LOC = "P84";
NET "D_OUT<1>" LOC = "P85";
NET "D_OUT<2>" LOC = "P86";
NET "D_OUT<3>" LOC = "P87";
=============================================================================

2. b) 8 to 3 Encoder Without Priority


ENABLE

SEL(0)
SEL(1)
D_OUT(0)
SEL(2)
8:3
SEL(3) Encoder D_OUT(1)
SEL(4) Without
D_OUT(2)
SEL(5) Priority
SEL(6)
SEL(7)

Truth Table for 8 to 3 Encoder without Priority:


INPUTS OUTPUTS
D_OUT D_OUT D_OUT
ENABLE SEL(7) SEL(6) SEL(5) SEL(4) SEL(3) SEL(2) SEL(1) SEL(0)
(2) (1) (0)
1 X X X X X X X X Z Z Z
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 0 1 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 1 0 1
0 0 1 0 0 0 0 0 0 1 1 0
0 1 0 0 0 0 0 0 0 1 1 1

4 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VHDL CODE VERILOG CODE


LIBRARY IEEE; module ENCODER8_3(EN, SEL,
USE IEEE.STD_LOGIC_1164.ALL; D_OUT);
USE IEEE.STD_LOGIC_ARITH.ALL; input EN;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input [7:0] SEL;
ENTITY ENCODER8_3 IS output [2:0] D_OUT;
PORT ( ENABLE: IN STD_LOGIC; reg [2:0] D_OUT;
SEL: IN STD_LOGIC_VECTOR(7 DOWNTO 0); always @ (SEL,EN)
D_OUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); begin
END ENCODER8_3; if(EN==1)
ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS D_OUT=3’bZZZ;
BEGIN else
PROCESS(ENABLE,SEL) begin
BEGIN case(SEL)
IF ( ENABLE = '1') THEN 8’b00000001: D_OUT=3'b000;
D_OUT <= "ZZZ"; 8’b00000010: D_OUT =3'b001;
ELSE 8’b 00000100: D_OUT =3'b010;
CASE SEL IS 8’b00001000: D_OUT =3'b011;
WHEN "00000001" => D_OUT <= "000"; 8’b00010000: D_OUT =3'b100;
WHEN "00000010" => D_OUT <= "001"; 8’b00100000: D_OUT =3'b101;
WHEN "00000100" => D_OUT <= "010"; 8’b01000000: D_OUT =3'b110;
WHEN "00001000" => D_OUT <= "011"; 8’b10000000:D_OUT =3'b111;
WHEN "00010000" => D_OUT <= "100"; default: D_OUT=3’bzzz;
WHEN "00100000" => D_OUT <= "101"; endcase
WHEN "01000000" => D_OUT <= "110"; end
WHEN "10000000" => D_OUT <= "111"; end
WHEN OTHERS =>D_OUT <= "ZZZ"; endmodule
END CASE;
END IF;
END PROCESS;
END ENCODER_ARCH;
Waveform for VHDL code:

Waveform for Verilog code:

============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "ENABLE" LOC = "P74"; NET "SEL<0>" LOC = "P100";
NET "SEL<1>" LOC = "P102"; NET "SEL<2>" LOC = "P124";
NET "SEL<3>" LOC = "P103"; NET "SEL<4>" LOC = "P105";
NET "SEL<5>" LOC = "P107"; NET "SEL<6>" LOC = "P108";
NET "SEL<7>" LOC = "P113"; NET "D_OUT<0>" LOC = "P84";
NET "D_OUT<1>" LOC = "P85"; NET "D_OUT<2>" LOC = "P86";

5 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB
ENABLE
2. c) 8 to 3 Encoder With Priority

SEL(0)
SEL(1)
D_OUT(0)
SEL(2)
8: 3
D_OUT(1)
SEL(3) Encoder
SEL(4) With Priority D_OUT(2)
SEL(5)
SEL(6)

Truth Table for 8 to 3 Encoder with Priority: SEL(7)


INPUTS OUTPUTS
D_OUT D_OUT D_OUT
ENABLE SEL(7) SEL(6) SEL(5) SEL(4) SEL(3) SEL(2) SEL(1) SEL(0)
(2) (1) (0)
1 X X X X X X X X 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 0 1 X X 0 1 0
0 0 0 0 0 1 X X X 0 1 1
0 0 0 0 1 X X X X 1 0 0
0 0 0 1 X X X X X 1 0 1
0 0 1 X X X X X X 1 1 0
0 1 X X X X X X X 1 1 1

VHDL CODE VERILOG CODE


LIBRARY IEEE; module ENCODER8_3P(EN, SEL,
USE IEEE.STD_LOGIC_1164.ALL; D_OUT);
USE IEEE.STD_LOGIC_ARITH.ALL; input EN;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input [7:0] SEL;
ENTITY ENCODER8_3P IS
output [2:0] D_OUT;
PORT ( ENABLE: IN STD_LOGIC;
SEL: IN STD_LOGIC_VECTOR(7 DOWNTO 0); reg [2:0] D_OUT;
D_OUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); always @ (SEL,EN)
END ENCODER8_3P; begin
ARCHITECTURE ENCODER_ARCH OF ENCODER8_3P IS if(EN==1)
BEGIN d_out=3’b000;
PROCESS(ENABLE,SEL) else
BEGIN begin
IF ( ENABLE = '1') THEN case(SEL)
D_OUT <= "000";
8’b00000001: D_OUT=3'b000;
ELSE
CASE SEL IS 8'b0000001x: D_OUT =3'b001;
WHEN "00000001" => D_OUT <= "000"; 8'b000001xx: D_OUT =3'b010;
WHEN "0000001X " => D_OUT <= "001"; 8'b00001xxx: D_OUT =3'b011;
WHEN "000001XX " => D_OUT <= "010"; 8'b0001xxxx: D_OUT =3'b100;
WHEN "00001XXX " => D_OUT <= "011"; 8'b001xxxxx: D_OUT =3'b101;
WHEN "0001XXXX " => D_OUT <= "100"; 8'b01xxxxxx: D_OUT =3'b110;
WHEN "001XXXXX " => D_OUT <= "101"; 8’b1xxxxxxx:D_OUT =3'b111;
WHEN "01XXXXXX" => D_OUT <= "110"; default: D_OUT=3’bzzz;
WHEN "1XXXXXXX" => D_OUT <= "111"; endcase
WHEN OTHERS =>D_OUT <= "ZZZ";
end
END CASE;END IF;END PROCESS;
end
END ENCODER_ARCH;
endmodule

6 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for VHDL code:

Waveform for Verilog code:

============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "ENABLE" LOC = "P74";
NET "SEL<0>" LOC = "P100";
NET "SEL<1>" LOC = "P102";
NET "SEL<2>" LOC = "P124";
NET "SEL<3>" LOC = "P103";
NET "SEL<4>" LOC = "P105";
NET "SEL<5>" LOC = "P107";
NET "SEL<6>" LOC = "P108";
NET "SEL<7>" LOC = "P113";
NET "D_OUT<0>" LOC = "P84";
NET "D_OUT<1>" LOC = "P85";
NET "D_OUT<2>" LOC = "P86";

2.d)8 to 1 Multiplexer

Truth Table for 8:1 Multiplexer


INPUTS OUTPUT A(0)
SEL[0] SEL[1] SEL[2] MUX_OUT A(1)
0 0 0 A(0) A(2)
8:1
0 0 1 A(1) A(3) MUX_OUT

0 1 0 A(2) A(4) MUX


0 1 1 A(3) A(5)
1 0 0 A(4) A(6)
1 0 1 A(5) A(7)
1 1 0 A(6)
1 1 1 A(7) SEL SELSEL
(0) (1) (2)

7 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

INPUTS SELECT LINES OUTPUT


A(7) A(6) A(5) A(4) A(3) A(2) A(1) A(0) SEL[2] SEL[1] SEL[0] MUX
_OUT
X X X X X X X 0 0 0 0 0
X X X X X X X 1 0 0 0 1
X X X X X X 0 X 0 0 1 0
X X X X X X 1 X 0 0 1 1
X X X X X 0 X X 0 1 0 0
X X X X X 1 X X 0 1 0 1
X X X X 0 X X X 0 1 1 0
X X X X 1 X X X 0 1 1 1
X X X 0 X X X X 1 0 0 0
X X X 1 X X X X 1 0 0 1
X X 0 X X X X X 1 0 1 0
X X 1 X X X X X 1 0 1 1
X 0 X X X X X X 1 1 0 0
X 1 X X X X X X 1 1 0 1
0 X X X X X X X 1 1 1 0
1 X X X X X X X 1 1 1 1

VHDL CODE VERILOG CODE


LIBRARY IEEE; module MUX8_1(A,, SEL,
USE IEEE.STD_LOGIC_1164.ALL; MUX_OUT);
USE IEEE.STD_LOGIC_ARITH.ALL; input[7:0]A;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input [2:0] SEL;
output MUX_OUT;
ENTITY MUX8_1 IS reg MUX_OUT;
PORT ( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); always @ (A , SEL )
A: IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- INPUTS OF THE MUX. case (SEL)
MUX_OUT: OUT STD_LOGIC ); -- OUTPUT OF THE MUX.
END MUX8_1; 3'b000: MUX_OUT =A[0];
ARCHITECTURE MUX4_1_ARCH OF MUX8_1 IS 3'b001: MUX_OUT =A[1];
BEGIN 3'b010: MUX_OUT = A[2];
PROCESS (SEL,A) 3'b011: MUX_OUT = A[3];
BEGIN 3'b100: MUX_OUT = A[4];
CASE SEL IS 3'b101: MUX_OUT = A[5];
WHEN "000" => MUX_OUT <= A(0); 3'b110: MUX_OUT = A[6];
WHEN "001" => MUX_OUT <= A(1); 3'b111: MUX_OUT = A[7];
WHEN "010" => MUX_OUT <= A(2); default: MUX_OUT =0;
WHEN "011" => MUX_OUT <= A(3);
WHEN "100" => MUX_OUT <= A(4); endcase
WHEN "101" => MUX_OUT <= A(5); endmodule
WHEN "110" => MUX_OUT <= A(6);
WHEN "111" => MUX_OUT <= A(7);
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END MUX4_1_ARCH;
Waveform for VHDL code:

8 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for verilog code:

======================================================================
UCF file(User constraint file)
NET "SEL<0>" LOC = "p100";
NET "SEL<1>" LOC = "p102";
NET "SEL<2>" LOC = "p124";
NET "A" LOC = "p74";
NET "B" LOC = "p76";
NET "C" LOC = "p77";
NET "D" LOC = "p79";
NET "E" LOC = "p78";
NET "F" LOC = "p82";
NET "G" LOC = "p80";
NET "H" LOC = "p83";
NET "MUX_OUT" LOC = "p84";
======================================================================

2.e)1 to 8 Demultiplexer

SEL SELSEL
(0) (1) (2)

D_OUT (0)
D_OUT (1)
D_OUT (2)
1:8
D_OUT (3)
D_IN Demultiplexer D_OUT (4)
D_OUT (5)
D_OUT (6)
D_OUT (7)

9 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Truth Table For 1:8 Demultiplexer


SELECT LINES INPUT OUTPUT
SEL[2] SEL[1] SEL[0] D_IN D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT D_OUT
(7) (6) (5) (4) (3) (2) (1) (0)
0 0 0 0 X X X X X X X 0
0 0 0 1 X X X X X X X 1
0 0 1 0 X X X X X X 0 X
0 0 1 1 X X X X X X 1 X
0 1 0 0 X X X X X 0 X X
0 1 0 1 X X X X X 1 X X
0 1 1 0 X X X X 0 X X X
0 1 1 1 X X X X 1 X X X
1 0 0 0 X X X 0 X X X X
1 0 0 1 X X X 1 X X X X
1 0 1 0 X X 0 X X X X X
1 0 1 1 X X 1 X X X X X
1 1 0 0 X 0 X X X X X X
1 1 0 1 X 1 X X X X X X
1 1 1 0 0 X X X X X X X
1 1 1 1 1 X X X X X X X

VHDL CODE VERILOG CODE


LIBRARY IEEE; module D_MUX1_8(SEL,
USE IEEE.STD_LOGIC_1164.ALL; D_OUT,D_IN);
USE IEEE.STD_LOGIC_ARITH.ALL; inputD_IN;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input [2:0] SEL;
output[7:0]D_OUT;
ENTITY D_MUX1_8 IS reg[7:0]D_OUT;
PORT ( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); always @ (D_IN, SEL )
D_OUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);. case (SEL)
D_IN: IN STD_LOGIC ); 3'b000: D_OUT[0] = D_IN;
END D_MUX1_8; 3'b001: D_OUT[1] = D_IN;
ARCHITECTURE D_MUX_1_ARCH OF D_MUX1_8 IS 3'b010: D_OUT [2]= D_IN;
BEGIN 3'b011: D_OUT [3]= D_IN;
PROCESS (SEL,D_IN) 3'b100: D_OUT [4]= D_IN;
BEGIN 3'b101: D_OUT [5]= D_IN;
CASE SEL IS 3'b110: D_OUT [6]= D_IN;
WHEN "000" =>D_OUT(0) <=D_IN; 3'b111: D_OUT [7]= D_IN;
WHEN "001" =>D_OUT(1)<= D_IN; default: D_OUT =0;
WHEN "010" =>D_OUT(2)<= D_IN; endcase
WHEN "011" =>D_OUT(3)<= D_IN; endmodule
WHEN "100" =>D_OUT(4)<= D_IN;
WHEN "101" =>D_OUT(5)<= D_IN;
WHEN "110" =>D_OUT(6)<= D_IN;
WHEN "111" =>D_OUT(7)<= D_IN;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END D_MUX_1_ARCH ;
Waveform for VHDL code:

10 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for Verilog code:

2. f) 1:4 De-multiplexer.
D_OUT[0]
1:4 D_OUT[1]
D_IN
D_OUT[2]
DEMUX
D_OUT[3]

SEL[0] SEL[1]
Truth TableFor1:4 De-multiplexer:
SELECT INPUT OUTPUT
SEL[1] SEL[0] D_IN D_OUT[3] D_OUT[2] D_OUT[1] D_OUT[0]
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0

VHDL CODE VERILOG CODE


LIBRARY IEEE; module DEMUX1_4(D_IN, SEL,
USE IEEE.STD_LOGIC_1164.ALL; D_OUT); input D_IN;
USE IEEE.STD_LOGIC_ARITH.ALL; input [1:0] SEL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; output [3:0] D_OUT;
reg[3:0] D_OUT;
ENTITY DEMUX1_4 IS
always @(D_IN ,SEL)
PORT ( D_IN: IN STD_LOGIC; case (SEL)
SEL: IN STD_LOGIC_VECTOR (1 DOWNTO 0); 2'b00:
D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); Begin
END DEMUX1_4; D_OUT [0]= D_IN;
D_OUT [1]=1’b0;
ARCHITECTURE DEMUX1_4_ARCH OF DEMUX1_4 IS D_OUT [2]=1’b0;
BEGIN D_OUT [3]=1’b0;
end
2'b01:
PROCESS(D_IN,SEL) Begin
BEGIN D_OUT [0]=1’b0;
D_OUT<="0000"; D_OUT [1]= D_IN;
CASE SEL IS D_OUT [2]=1’b0;
WHEN "00" => D_OUT(0)<=D_IN; D_OUT [3]=1’b0;
WHEN "01" => D_OUT(1)<=D_IN; end
WHEN "10" => D_OUT(2)<=D_IN; 2'b10: begin
WHEN OTHERS => D_OUT(3)<=D_IN; D_OUT [0]=1’b0;
END CASE; D_OUT [1]=1’b0;
D_OUT [2]= D_IN;
D_OUT [3]=1’b0;
END PROCESS; end
END DEMUX1_4_ARCH; 2'b11:
begin
D_OUT [0]=1’b0;

11 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

D_OUT [1]=1’b0;
D_OUT [2]=1’b0;
D_OUT [3]= D_IN;
end
default D_OUT =4'b0000;
endcase endmodule

Waveform for VDHL code:

Waveform for verilog code:

=============================================================================
UCF file(User constraint file)
NET "SEL<0>” LOC = "p76";
NET "SEL<1>” LOC = "p77";
NET "d_in" LOC = "p74";
NET "d_out<0>" LOC = "p84";
NET "d_out<1>" LOC = "p85";
NET "d_out<2>" LOC = "p86";
NET "d_out<3>" LOC = "p87";
=============================================================================

2.g)4 bit Binary to Gray converter

Truth TableFor4 bit Binary to Gray converter:


Binary inputs Gray Outputs
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1

12 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
B(3) G(3)
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1 B(2) G(2)
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
G(1)
B(1)

B(0) G(0)

G2 G1 G0
B1 B0 B1 B0 B1 B0
B3 B2 00 01 11 10 B3 B2 00 01 11 10 B3 B2 00 01 11 10
00 00 1 1 00 1 1
01 1 1 1 1 01 1 1 01 1 1
11 11 1 1 11 1 1
10 1 1 1 1 10 1 1 10 1 1

G3 = B3 G2 = B3 B2’ + B3 B2’ G1 = B2 B1’ + B1 B2’ G0 = B1’B0 + B1 B0’


G2 = B3 B2 G1 = B1  B2 G0 = B1  B0

VHDL CODE VERILOG CODE


LIBRARY IEEE; module BINARY_GRAY(G, B);
USE IEEE.STD_LOGIC_1164.ALL; input [3:0] B;
USE IEEE.STD_LOGIC_ARITH.ALL; output [3:0] G;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; reg[3:0] G;
ENTITY BINARY_GRAY IS always @ (B)
PORT( B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); begin
G: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); G[3] = B[3];
END BINARY_GRAY; G[2] = B[3] ^ B[2];
ARCHITECTURE BEHAVIORAL OF BINARY_GRAY IS G[1] = B[2] ^ B[1];
BEGIN G[0] = B[1] ^ B[0];
G(3)<= B(3); end
G(2)<= B(3) XOR B(2); endmodule
G(1)<= B(2) XOR B(1);
G(0)<= B(1) XOR B(0);
END BEHAVIORAL;

Waveform for VHDL code:

13 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for verilog code:

=============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "G<0>" LOC = "P74";
NET "G<1>" LOC = "P76";
NET "G<2>" LOC = "P77";
NET "G<3>" LOC = "P79";
NET "B<0>" LOC = "P84";
NET "B<1>" LOC = "P85";
NET "B<2>" LOC = "P86";
NET "B<3>" LOC = "P87";
=============================================================================

2.g)N bit comparator

Truth TableFor2 bit comparator: A<B


A 2-BIT
A B A=B A>B A<B
COMPARATER A>B
00 00 1 0 0
00 01 0 0 1 B
01 00 0 1 0 A=B

VHDL CODE VERILOG CODE


LIBRARY IEEE; module COMPARATER(A, B,
USE IEEE.STD_LOGIC_1164.ALL; ALB,AGB,AEB);
USE IEEE.STD_LOGIC_ARITH.ALL; parameter N = 1;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input [N:0] A;
ENTITY COMPARATOR IS input [N:0] B;
GENERIC (N: INTEGER := 1); output ALB;
PORT( A,B: IN STD_LOGIC_VECTOR(N DOWNTO 0); output AGB;
ALB,AGB,AEB: OUT STD_LOGIC); output AEB;
END COMPARATOR; reg ALB,AGB,AEB;
ARCHITECTURE COMPARATOR_ARC OF COMPARATOR IS always @ (A , B)
BEGIN begin
PROCESS(A,B) if (A<B)
BEGIN begin
IF ( A < B ) THEN ALB <= '1'; ALB=1'b1;
ELSE ALB <= '0'; END IF; AGB=1'b0;
IF ( A > B ) THEN AGB <= '1'; AEB=1'b0;
ELSE AGB <= '0'; END IF; end
IF ( A = B ) THEN AEB <= '1'; else if (A>B)
ELSE AEB <= '0'; END IF; begin
END PROCESS; AGB=1'b1;
END COMPARATOR_ARC; ALB=1'b0;
AEB=1'b0;
end
else if (A==B)

14 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

begin
AEB=1'b1;
ALB=1'b0;
AGB=1'b0;
end
end
endmodule

Waveform for VHDL code:

Waveform for verilog code:

=============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "A<0>" LOC = "P74";
NET "A<1>" LOC = "P76";
NET "B<0>" LOC = "P77";
NET "B<1>" LOC = "P79";
NET "ALB" LOC = "P84";
NET "AGB" LOC = "P85";
NET "AEB" LOC = "P86";
=============================================================================
Result: All combinational design has been realized ,simulated and implemented using FPGA/CPLD using
HDL code

Date of Completion of Exp. Staff Signature Remarks

15 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.3
Aim: Write a HDL code to describe the functions of a full adder using three modeling styles.

3. a)Half Adder.

Truth Table For Half Adder: Boolean expressions: Sum=A  B, Carry=A*B


Inputs Outputs
A B Sum(S) Carry(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

VHDL CODE VERILOG CODE


LIBRARY IEEE; module halfadder(a, b, sum, carry);
USE IEEE.STD_LOGIC_1164.ALL; input a;
USE IEEE.STD_LOGIC_ARITH.ALL; input b;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; output sum;
ENTITY HALFADDER IS output carry;
PORT ( A, B: IN STD_LOGIC; reg sum;
SUM, CARRY : OUT STD_LOGIC); reg carry;
END HALFADDER; always @ (a , b)
ARCHITECTURE BEHAVIORAL OF begin
HALFADDER IS sum = a^b;
BEGIN carry = a & b;
SUM <= A XOR B; end
CARRY<= A AND B; endmodule
END BEHAVIORAL;

Waveform for VHDL code:

Waveform for verilog code:

=============================================================================
UCF file(User constraint file)
NET "A” LOC = "p74";
NET "B” LOC = "p76";
NET "SUM” LOC = "p84";
NET "CARRY” LOC = "p85";

16 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

===========================================================================
3.b) FULL ADDER

Inputs Outputs
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Block Diagram For VHDL Code

Logic Diagram For VHDL Code Logic Diagram For Verilog Code

VHDL CODE FOR FULL ADDER USING COMPONENT VERILOG CODE FOR FULL ADDER
INSTANTIATION METHOD (STRUCTURAL STYLE) USING TWO HALF
ADDER.(STRUCTURAL STYLE)
LIBRARY IEEE; module FULL_2HA(A, B, C, SUM,
USE IEEE.STD_LOGIC_1164.ALL; CARRY);
USE IEEE.STD_LOGIC_ARITH.ALL; input A;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input B;
ENTITY FULLADDER IS input C;
PORT ( A,B,C : IN STD_LOGIC; output SUM;
CARRY : OUT STD_LOGIC; output CARRY;
SUM : OUT STD_LOGIC); wire S1,T1,T2;
END FULLADDER; xor
X1(S1,A,B),
ARCHITECTURE BEHAVIORAL OF FULLADDER IS X2(SUM,S1,C);
COMPONENT HALFADDER and
PORT ( A : IN STD_LOGIC; A1(T1,S1,C),
B : IN STD_LOGIC; A2(T2,A,B);
SUM : OUT STD_LOGIC; or
CARRY : OUT STD_LOGIC); O1(CARRY,T1,T2);
END COMPONENT; endmodule

SIGNAL TEMP1,TEMP2, TEMP3: STD_LOGIC;


BEGIN
L1: HALFADDER PORT MAP( A, B,TEMP1,TEMP2);
L2: HALFADDER PORT MAP( TEMP1,C,SUM,TEMP3);
CARRY <= TEMP2 OR TEMP3;
END BEHAVIORAL;

17 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for VHDL code:

Waveform for Verilog code:

VHDL CODE USING DATA FLOW VERILOG CODE USING DATA FLOW
LIBRARY IEEE; module FULLADDER(A, B, C, SUM,
USE IEEE.STD_LOGIC_1164.ALL; CARRY);
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input A;
input B;
ENTITY FA IS input C;
PORT (A,B,C:IN BIT; output SUM;
SUM,CARRY:OUT BIT); output CARRY;
END FA;
wire T1, T2, T3;
ARCHITECTURE FA_ARCH OF FA IS
BEGIN assign SUM=A^B^C;
assign T1=A&B;
SUM <= AXOR B XOR C; assign T2=B&C;
assign T3=C&A;
CARRY<=(A AND B )OR (B AND C) OR (C assign CARRY=(T1| T2) | T3;
AND A);
endmodule
END FA_ARCH;

Waveform for VHDL code:

18 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for verilog code:

VHDL CODE (BEHAVIORAL STYLE) VERILOG CODE (BEHAVIORAL


STYLE)

LIBRARY IEEE; module fulladd(cin,x,y,s,co);


USE IEEE.STD_LOGIC_1164.ALL; input cin,x,y;
USE IEEE.STD_LOGIC_ARITH.ALL; output s,co;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; reg s,co;

ENTITY FULLADDER IS always@(cin or x or y)


PORT ( A,B,C : IN STD_LOGIC; begin
SUM,CARRY : OUT STD_LOGIC);
END FULLADDER ; case ({cin,x,y})
3'b000:{co,s}=2'b00;
ARCHITECTURE BEHAVIORAL OF FULLADDER IS 3'b001:{co,s}=2'b01;
BEGIN 3'b010:{co,s}=2'b01;
PROCESS( A,B,C) 3'b011:{co,s}=2'b10;
BEGIN 3'b100:{co,s}=2'b01;
IF(A='0' AND B='0' AND C='0') THEN SUM<='0'; 3'b101:{co,s}=2'b10;
CARRY<='0'; 3'b110:{co,s}=2'b10;
ELSIF(A='0' AND B='0' AND C='1') THEN SUM<='1'; 3'b111:{co,s}=2'b11;
CARRY<='0'; endcase
ELSIF(A='0' AND B='1' AND C='0') THEN SUM<='1'; end
CARRY<='0'; endmodule
ELSIF(A='0' AND B='1' AND C='1') THEN SUM<='0';
CARRY<='1';
ELSIF(A='1' AND B='0' AND C='0') THEN SUM<='1';
CARRY<='0';
ELSIF(A='1' AND B='0' AND C='1') THEN SUM<='0';
CARRY<='1';
ELSIF(A='1' AND B='1' AND C='0') THEN SUM<='0';
CARRY<='1';
ELSE
SUM<='1'; CARRY<='1';
END IF;
END PROCESS;
END BEHAVIORAL;

Waveform for VHDL code:

19 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for Verilog code:

=======================================================================
UCF file (User constraint file)
NET "A” LOC = "p74";
NET "B” LOC = "p76";
NET "C” LOC = "p77";
NET "Sum” LOC = "p84";
NET "Carry” LOC = "p85";
========================================================================

Result: Three modeling styles of full adder have been realized simulated and implemented using
FPGA/CPLD using HDL Codes.

Date of Completion of Exp. Staff Signature Remarks

20 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO. 4
Aim: Write a model for 32 bit alu using the schematic diagram shown below

OPCODE OPCODE ALU OPERATION


1 A+B
2 A-B
3 A Complement
4 A*B
5 A or B
6 A and B
7 A nand B
8 A xor B

Truth table For 32bits ALU:

EN OPC A B Y OPM OPERATION


xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx zzzzzzzzzzzzzzzz
0 xxxx - -
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx zzzzzzzzzzzzzzzz
0000000000000000 0000000000000000 000000000000000
1 0001 - A+B
0000000000001111 0000000000000000 000000000001111
0000000000000000 0000000000000000 000000000000000
1 0010 - A-B
0000000000001110 0000000000000010 000000000001100
0000000000000000 000000000000000 111111111111111
1 0011 - not A
0000000000001111 000000000001111 111111111110000
0000000000000000 0000000000000000 00000000000000000000000000000000
1 0100 - A*B
0000000000001001 0000000000001000 00000000000000000000000001001000
0000000000000000 0000000000000000 000000000000000
1 0101 - A or B
0000000000001111 0000000000000000 000000000001111
0000000000000000 0000000000000000 000000000000000
1 0110 - A and B
0000000000001111 0000000000001011 000000000001011
0000000000000000 0000000000000000 000000000000000
1 0111 - A nand B
0000000000001111 0000000000000010 000000000001101
0000000000000000 0000000000000000 000000000000000
1 1000 - A xor B
0000000000000000 0000000000000100 000000000000100

21 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VHDL CODE FOR 4 BIT ALU MODEL VERILOG CODE FOR 4 BIT ALU
MODEL
LIBRARY IEEE; moduleALU(A, B, OPC,EN,Y,OPM);
USE IEEE.STD_LOGIC_1164.ALL; input [31:0] A, B;
USE IEEE.STD_LOGIC_ARITH.ALL; input EN;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input [3:0] OPC;
output [31:0] Y;
output [63:0] OPM;
ENTITY ALU IS
PORT ( A,B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); reg [31:0]Y; reg [63:0]OPM;
OPC : IN STD_LOGIC_VECTOR(3 DOWNTO 0); always @(A ,B , OPC,EN)
EN : IN STD_LOGIC; -- ENABLE SIGNAL begin
Y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OPM : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)); if (EN==1)
END ALU; begin
case (OPC)
4'b0001:Y=A+B;
ARCHITECTURE BEHAVIORAL OF ALU IS
4'b0010:Y=A-B;
BEGIN 4'b0011:Y=~A;
4'b0100: OPM=A*B;
PROCESS(A,B,OPC,EN) 4'b0101:Y=A|B;
BEGIN 4'b0110:Y=A&B;
4'b0111:Y=~(A|B);
IF EN = '1' THEN 4'b1000:Y=A^B;
CASE OPC IS endcase
WHEN "0001" =>Y<= A+B; end
WHEN "0010" =>Y<= A-B;
else
WHEN "0011" =>Y<= NOT A; begin
WHEN "0100" =>OPM<= A*B; Y = 32’bz;
WHEN "0101" =>Y<= A OR B; OPM = 32’bz;
WHEN "0110" =>Y<= A AND B;
WHEN "0111" =>Y<= A NAND B; end
WHEN "1000" => Y<= A XOR B;
WHEN OTHERS => Y<=(OTHERS =>'Z') ; end
END CASE;
ELSE endmodule
OPM<= (OTHERS =>'Z');
END IF;

END PROCESS;

END BEHAVIORAL;

Waveform for VHDL code:

22 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for Verilog code:

=============================================================================
UCF file(User constraint file for 4bit ALU )
NET "A<0>” LOC = "p74";
NET "A<1>” LOC = "p76";
NET "A<2>” LOC = "p77";
NET "A<3>” LOC = "p79";
NET "B<0>” LOC = "p78";
NET "B<1>” LOC = "p82";
NET "B<2>” LOC = "p80";
NET "B<3>” LOC = "p83";
NET "Opcode<0>” LOC = "p102";
NET "Opcode<1>” LOC = "p124";
NET "Opcode<2>” LOC = "p103";
NET "en” LOC = "p100";
NET "Y<0>” LOC = "p84";
NET "Y<1>” LOC = "p85";
NET "Y<2>” LOC = "p86";
NET "Y<3>” LOC = "p87";
NET "OPM<0>” LOC = "p112";
NET "OPM<1>” LOC = "p116";
NET "OPM<2>” LOC = "p119";
NET "OPM<3>” LOC = "p118";
NET "OPM<4>” LOC = "p123";
NET "OPM<5>” LOC = "p131";
NET "OPM<6>” LOC = "p130";
NET "OPM<7>” LOC = "p137";
===========================================================================
Result: 32 bit ALU operations have been realized, simulated and implemented on FPGA/CPLD using HDL
codes.

Date of Completion of Exp. Staff Signature Remarks

23 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.5
Aim: Develop the HDL code for the following flip-flop, SR, D, JK, T.

5.a). SR Flip-flop RST

Truth Table For SR Flip-flop:


INPUTS OUTPUTS
RST S R Q QBAR S Q
S-R
1 X X 0 1
0 0 0 0 1 CLK
0 0 1 0 1 FLIP-FLOP
0 1 0 1 0 R QBAR
0 1 1 ?

VHDL CODE VERILOG CODE


LIBRARY IEEE; module sr_ff(s ,r ,clk , rst , q , qbar);
USE IEEE.STD_LOGIC_1164.ALL; input s,r,clk,rst;
USE IEEE.STD_LOGIC_ARITH.ALL; output q,qbar;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; regq,qbar;
always@(posedge clk ,rst , s , r)
ENTITY SRFF IS begin
PORT ( if(rst==1)
S: IN BIT; -- S BIT INPUT begin
R: IN BIT; -- R BIT INPUT q=0;
RST: IN BIT; qbar=1;
CLK: IN BIT; -- GLOBAL CLOCK end
Q,QBAR : OUT STD_LOGIC ); else
END SRFF; begin
if(s==0&&r==0)
ARCHITECTURE S_R_FF_ARCH OF SRFF IS begin
SIGNAL TEMP:STD_LOGIC:='0'; q=q;
BEGIN qbar=qbar;
end
PROCESS(CLK) if(s==1&&r==0)
BEGIN begin
q=1;
IF CLK='1' AND CLK'EVENT THEN qbar=0;
IF (RST=’1’)THEN TEMP<='0'; end
ELSIF (S='0' AND R='0')THEN TEMP<= TEMP; if(s==0&&r==1)
ELSIF(S='0' AND R='1')THEN TEMP<='0'; begin
ELSIF(S='1' AND R='0')THEN TEMP<='1'; q=0;
ELSIF (S='1' AND R='1')THEN TEMP<='X'; qbar=1;
end
if (s==1&&r==1)
END IF;END IF;
begin
Q<=TEMP; QBAR<=NOT TEMP;
q=1'bx;
qbar=1'bx;
END PROCESS;
end end end endmodule
END S_R_FF_ARCH;
Waveform for VHDL code:

24 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for Verilog code:

=============================================================================
UCF file(User constraint file)
NET "s” LOC = "p74"; NET "r” LOC = "p76";
NET "clk” LOC = "p52"; NET "q” LOC = "p84";
NET "qbar” LOC = "p85";

5. b). D Flip-flop
D Q
Truth Table For D Flip-flop: D
RESET D Q QBAR CLK
0 0 1 FLIP-FLOP
1 0 0 1 RST QBAR
1 1 1 0

VHDL CODE VERILOG CODE


LIBRARY IEEE; module D_FF(D, RESET, CLK, Q, QBAR);
USE IEEE.STD_LOGIC_1164.ALL; input D;
USE IEEE.STD_LOGIC_ARITH.ALL; input RESET;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input CLK;
ENTITY DFF IS output Q,QBAR;
PORT (CLK, D, RST: IN STD_LOGIC; reg Q,QBAR;
Q,QBAR : OUT STD_LOGIC); always@(posedge CLK , posedge
END DFF; RESET)
begin
ARCHITECTURE D_FF_ARCH OF DFF IS if (RESET==0)
SIGNAL TEMP:STD_LOGIC:='0'; begin
BEGIN Q=0;
PROCESS(CLK) QBAR=1;
BEGIN end
IF(CLK'EVENT AND CLK='1')THEN else
IF (RST=’0’)THEN TEMP<='0'; begin
ELSE Q=D;
TEMP<=D; QBAR=~D;
END IF; END IF; end
Q<=TEMP; QBAR<=NOT TEMP; end
END PROCESS;END D_FF_ARCH; endmodule

Waveform for VHDL code:

25 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for Verilog code:


=============================================================================
UCF file(User constraint file)
NET "d” LOC = "p74";
NET "clk” LOC = "p52";
NET "q” LOC = "p84";
NET "qbar” LOC = "p85";

5.c). JK Flip-flop
RST
Truth TableForJK Flip-flop:
RESET J K Q QBAR
1 0 1
0 0 0 0 1 J Q
0 0 1 0 1
J-K
CLK
0 1 0 1 0
0 1 1 Toggle K FLIP-FLOP QBAR
VHDL CODE VERILOG CODE
LIBRARY IEEE; module JK_FF(J, K, CLK, RESET, Q,
USE IEEE.STD_LOGIC_1164.ALL; QBAR);
USE IEEE.STD_LOGIC_ARITH.ALL; input J;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; input K;
ENTITY JKFF IS input CLK;
PORT ( input RESET;
CLK : IN BIT; . output Q, QBAR;
J : IN BIT; . reg Q, QBAR;
K : IN BIT; always @ (posedge CLK , posedge RESET)
RESET :IN BIT; begin
Q,QBAR : OUT STD_LOGIC); if(RESET==1)
END JKFF; begin
Q=0;
ARCHITECTURE JKFF_ARCH OF JKFF IS QBAR=1;
SIGNAL TEMP:STD_LOGIC:='0'; end
BEGIN else if (J==0 && K==0)
PROCESS(CLK,RESET) begin
BEGIN Q=Q;
QBAR=QBAR;
IF(RESET='1')THEN end
TEMP<='0'; else if (J==0 && K==1)
ELSIF(CLK'EVENT AND CLK='1')THEN begin
IF(J='0' AND K='0') THEN Q=0;
TEMP<= TEMP; QBAR=1;
ELSIF(J='0' AND K='1') THEN end
TEMP<='0'; else if (J==1 && K==0)
ELSIF(J='1' AND K='0') THEN begin
TEMP<='1'; Q=1;
ELSIF(J='1' AND K='1') THEN QBAR=0;
TEMP<=NOT TEMP; end
else
END IF; begin
END IF; Q=~Q;
Q<=TEMP; QBAR<=NOT TEMP; QBAR=~QBAR;
END PROCESS; end end
END JKFF_ARCH; endmodule

26 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for VHDL code:

Waveform for Verilog code:

=============================================================================
UCF file(User constraint file)
NET "j” LOC= "p74";
NET "k” LOC = "p76";
NET "Reset” LOC = "p77";
NET "clk” LOC = "p52";
NET "q” LOC = "p100";
NET "qbar” LOC = "p102";

5. d).T Flip-flop

T Q
T
CLK
FLIP-FLOP
RST QBAR

Truth Table For T Flip-flop:


RESET T Q QBAR
1 X 0 1
0 0 0 1
0 1 Toggle

27 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VHDL CODE VERILOG CODE


LIBRARY IEEE; module T_FF(T, CLK, RESET, Q, QBAR);
USE IEEE.STD_LOGIC_1164.ALL; input T, CLK,RESET;
USE IEEE.STD_LOGIC_ARITH.ALL; output Q, QBAR;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; reg Q,QBAR;

ENTITY TFF IS always @ (posedge CLK or RESET)


PORT ( T,RST: IN STD_LOGIC; -- INPUT T begin
CLK: IN STD_LOGIC; -- GLOBAL CLOCK SIGNAL
Q,QBAR : OUT STD_LOGIC); -- Q OUTPUT if (RESET==1)
END TFF; begin
Q=0;
ARCHITECTURE T_FF_ARCH OF TFF IS QBAR=1;
SIGNAL TEMP:STD_LOGIC:='0'; end
BEGIN else if (T==0)
begin
PROCESS(CLK) Q=Q;
BEGIN QBAR=QBAR;
end
IF(CLK'EVENT AND CLK='1')THEN else
IF RST=’1’ THEN begin
TEMP<=’0’; Q=~Q;
ELSE QBAR=~QBAR;
IF (T=’0’) THEN
TEMP<= TEMP; end
ELSE end
TEMP<= NOT TEMP;
END IF; endmodule
END IF;
END IF;

Q<=TEMP; QBAR<=NOT TEMP;


END PROCESS;
END T_FF_ARCH;

Waveform for VHDL code:

Waveform for Verilog code:

28 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

=============================================================================
UCF file(User constraint file)
NET "T” LOC= "p76";
NET "clk” LOC = "p52";
NET "q” LOC = "p100";
NET "qbar” LOC = "p109";
NET "rst” LOC = "p74";
=============================================================================

Result: Flip-flop operations have been realized, simulated and implemented on FPGA /CPLD using HDL
codes.

Date of Completion of Exp. Staff Signature Remarks

29 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.6
Aim: Design 4 bit Binary, BCD counter ( Synchronous reset and Asynchronous reset and any sequence
counters.

6.a).4-Bit Synchronous Counter


Truth TableFor4-Bit Synchronous Counter:

Reset Clock Q3 Q2 Q1 Q0
1 1 0 0 0 0
0 1 0 0 0 0
0 1 0 0 0 1
0 1 0 0 1 0
0 1 0 0 1 1
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 0 0 1
0 1 1 0 1 0
0 1 1 0 1 1
0 1 1 1 0 0
0 1 1 1 0 1
0 1 1 1 1 0
0 1 1 1 1 1

VHDL CODE FOR 4-BIT SYNCHRONOUS COUNTER VERILOG CODE FOR 4 BIT
SYNCHRONOUS COUNTER
LIBRARY IEEE; module sync2(clk, reset, count);
USE IEEE.STD_LOGIC_1164.ALL; input clk;
USE IEEE.STD_LOGIC_ARITH.ALL; input reset;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; output [3:0] count;
ENTITY SYNC_COUNTER IS reg[3:0]count;
PORT ( CLK : IN STD_LOGIC; always@(posedge clk , posedge reset)
RESET : IN STD_LOGIC; begin
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); if(reset==1)
END SYNC_COUNTER; count=4'b0000;
else
ARCHITECTURE BEHAVIORAL OF SYNC_COUNTER IS count=count+1;
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0); end
BEGIN endmodule
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
IF (RESET='1' )THEN --SYNCRONOUS RESET
TEMP<="0000"; --RESET COUNT
ELSE
TEMP<=TEMP+1;
END IF;
END IF;
END PROCESS;
Q<=TEMP;
END BEHAVIORAL;

30 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Waveform for VHDL code:

Waveform for Verilog code:

VHDL CODE FOR 4-BIT SYNCHRONOUS COUNTER.(FOR VERILOG CODE FOR 4-BIT
HARDWARE IMPLEMENTATION) SYNCHRONOUS COUNTER.(FOR
HARDWARE IMPLEMENTATION)
LIBRARY IEEE; module counter(clk, reset, count);
USE IEEE.STD_LOGIC_1164.ALL; input clk, reset;output [3:0] count;
USE IEEE.STD_LOGIC_ARITH.ALL; reg[3:0] count;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; integer timer_count1 = 0,timer_count2 = 0;
regclk_msec,clk_sec;
ENTITY SYNC_COUNTER IS
PORT( CLK: IN STD_LOGIC; always@(posedgeclk)begin
RESET: IN STD_LOGIC; if(timer_count1==3999)
COUNT: OUT begin
STD_LOGIC_VECTOR( 3 DOWNTO 0)); timer_count1=0;
END SYNC_COUNTER; clk_msec=1'b1;
end
ARCHITECTURE COUNTER_ARCH OF SYNC_COUNTER IS elsebegin
SIGNAL TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0); timer_count1=timer_count1+1;
SIGNAL DCLK:STD_LOGIC_VECTOR(20DOWNTO 0); clk_msec=1'b0;
BEGIN
endend
PROCESS(CLK) always@(posedgeclk_msec)begin
BEGIN if(timer_count2==999)
IF RISING_EDGE(CLK) THEN begin
DCLK<=DCLK+’1’; timer_count2=0;
END IF; clk_sec=1'b1;
END PROCESS; end
else
PROCESS (DCLK(18)) begin
BEGIN timer_count2=timer_count2+1;
IF DCLK(18)='1' AND DCLK(18)'EVENT THEN
clk_sec=1'b0;
IF RESET='1' THEN –SYNCHRONOUS RESET
TEMP <= (OTHERS=>'0'); endend
ELSE always@(posedgeclk_sec)
TEMP <= TEMP + 1; begin
END IF;END IF; if(~reset)
count = 4'b0000;
COUNT<= TEMP; else

31 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

END PROCESS; count = count+1;


END COUNTER_ARCH; end endmodule

=============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "RESET" LOC= "P74";
NET "CLK" LOC = "P52";
NET "COUNT<0>" LOC = "P84";
NET "COUNT<1>" LOC = "P85";
NET "COUNT<2>" LOC = "P86";
NET "COUNT<3>" LOC = "P87";

6. b). 4-Bit Asynchronous Counter

VHDL Code FOR 4-bit Asynchronous Binary Counter VERILOG CODE FOR Asynchronous
Counter
LIBRARY IEEE; module synk(clk, reset, count);
USE IEEE.STD_LOGIC_1164.ALL; input clk;
USE IEEE.STD_LOGIC_ARITH.ALL; input reset;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; output [3:0] count;
reg [3:0]count;
ENTITY ASYNC_C IS
PORT ( CLK : IN STD_LOGIC; always@(posedge clk , posedge reset)
RESET : IN STD_LOGIC; begin
COUNT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); if(reset==1)
END ASYNC_C; count=4'b0000;
else
ARCHITECTURE BEHAVIORAL OF ASYNC_C IS count=count+1;
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0); end
BEGIN endmodule
PROCESS(CLK,RESET)
BEGIN
IF RESET='1' THEN --ASYNCHRONOUS RESET
TEMP<=(OTHERS=>'0');
ELSIF CLK='1' AND CLK'EVENT THEN
TEMP<=TEMP+1;
END IF;
END PROCESS;
COUNT<=TEMP;
END BEHAVIORAL;

Waveform for VHDL code:

Waveform for Verilog code:

32 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VHDL CODE for 4-bit Asynchronous binary counter.(for hardware implementation)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ASYNC_COUNTER IS
PORT( CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
COUNT: BUFFERSTD_LOGIC_VECTOR( 3 DOWNTO 0));
END ASYNC_COUNTER;

ARCHITECTURE COUNTER_ARCH OF ASYNC_COUNTER IS


SIGNAL DIV:STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL CLKDIV:STD_LOGIC;
BEGIN
PROCESS (CLK)--CLKDIVIDE
BEGIN
IF CLK='1' AND CLK'EVENT THEN
DIV<=DIV+1;
ENDIF;
END PROCESS;
CLKDIV<=DIV(22);
PROCESS(CLKDIV,RESET)
BEGIN
IF RESET='1' THEN
COUNT <= “0000”;
ELSIF (CLKDIV='1' AND CLKDIV' EVENT) THEN
COUNT <= COUNT + 1;
END IF;
END PROCESS;
END COUNTER_ARCH;
=============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "RESET" LOC= "P74"; NET "CLK" LOC = "P52";
NET "COUNT<0>" LOC = "P84"; NET "COUNT<1>" LOC = "P85";
NET "COUNT<2>" LOC = "P86"; NET "COUNT<3>" LOC = "P87";
=============================================================================
VERILOG CODE FOR 4-BIT ASYNCHRONOUS BINARY COUNTER.(FOR
HARDWARE IMPLEMENTATION)
------- ASSIGNMENT--------
=====================================================================
6.c). BCD Counter Truth Table For BCD Counter: Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 0 0 0 0

33 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VHDL CODE for 4-bit synchronous BCD counter VERILOG CODE for 4-bit
synchronous BCD counter.
LIBRARY IEEE; module bcd (clk, reset, count);
USE IEEE.STD_LOGIC_1164.ALL; input clk, reset;
USE IEEE.STD_LOGIC_ARITH.ALL; output [3:0] count;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
reg[3:0]count;
ENTITY SYNC_COUNTER IS
PORT ( CLK : IN STD_LOGIC; always@(posedge clk , posedge reset)
RESET : IN STD_LOGIC; begin
COUNT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END SYNC_COUNTER; if(reset==1 | count==4'b1001)
begin
ARCHITECTURE BEHAVIORAL OF SYNC_COUNTER IS count=4'b0000;
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0); end
BEGIN else
count=count+1;
PROCESS(CLK)
BEGIN end
endmodule
IF CLK='1' AND CLK'EVENT THEN
IF (RESET='1' OR TEMP =”1001” )THEN
TEMP<="0000";--RESET COUNT
ELSE
TEMP<=TEMP+1;
END IF;
END IF;
END PROCESS;

COUNT<=TEMP;
END BEHAVIORAL;

Waveform for VHDL code:

Waveform for Verilog code:

34 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VHDL CODE for 4-bit synchronous BCD counter.(For Hardware Implementation)


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SYNC_COUNTER IS
PORT( CLK: IN STD_LOGIC; -- GLOBAL CLOCK SIGNAL
RESET: IN STD_LOGIC; -- GLOBAL RESET SIGNAL
COUNT: BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0)); --COUNTER OUTPUT
END SYNC_COUNTER;

ARCHITECTURE COUNTER_ARCH OF SYNC_COUNTER IS


BEGIN

PROCESS (CLK)
BEGIN

IF CLK='1' AND CLK'EVENT THEN


IF (RESET='1' OR COUNT=”1010”) THEN --SYNCHRONOUS RESET
COUNT <= “0000”; --SET INTIAL VALUE OF COUNT FOR ANY SEQUENCE COUNTER
ELSE
COUNT <= COUNT + 1;

END IF;END IF;

END PROCESS;
END COUNTER_ARCH;

=============================================================================
UCF file(User constraint file)
NET "RESET" LOC= "p74";
NET "CLK" LOC = "p52";
NET "COUNT<0>" LOC = "p84";
NET "COUNT<1>" LOC = "p85";
NET "COUNT<2>" LOC = "p86";
NET "COUNT<3>" LOC = "p87";

Verilog CODE FOR 4-bit synchronous BCD counter (FOR HARDWARE


IMPLEMENTATION)

----- ASSIGNMENT------
=============================================================================

6.d). Binary Any Sequence up down 4bit Counter

4
d_in /
load
Binary Any 4
updown Sequence up / Bin_out
down 4bit
rst Counter

clk

35 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VHDL CODE for Binary Any Sequence up down 4bit VERILOG CODEfor Binary Any Sequence up
Counter down 4bit Counter
LIBRARY IEEE; module
USE IEEE.STD_LOGIC_1164.ALL; seq_counter(clk,rst,load,updown,d_in,bin_out);
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
input clk,rst,load,updown;
ENTITY SEQ_COUNTER IS input [3:0] d_in;
PORT ( CLK,RST,LOAD,UPDOWN : IN STD_LOGIC; output [3:0] bin_out;
D_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
BIN_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO reg[3:0] bin_out;
0));
END SEQ_COUNTER; always@ (posedgeclk)
ARCHITECTURE BEHAVIORAL OF SEQ_COUNTER IS
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO begin
0):=”0000”; if(rst)
BEGIN bin_out =4'b0000;
PROCESS(CLK, RST) else if (load)
BEGIN bin_out= d_in;
IF (RST = ‘1’) THEN else if (updown)
TEMP <=”0000”; bin_out = bin_out + 4'b0001;
ELSIF (LOAD = ‘1’) THEN else
TEMP <= D_IN; bin_out = bin_out - 4'b0001;
ELSIF (CLK='1' AND CLK'EVENT AND LOAD=’0’) THEN
IF ( UPDOWN =”1” )THEN
TEMP <= TEMP+’1’; end
ELSE endmodule
TEMP<=TEMP - ‘1’;
END IF;
END IF;
END PROCESS;
BIN_OUT <=TEMP;
END BEHAVIORAL;
Waveform for VHDL code:

Waveform for Verilog code:

Result: Asynchronous and synchronous counters have been realized, simulated and implemented
on FPGA/CPLD using HDL codes.
Date of Completion of Exp. Staff Signature Remarks

36 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

INTERFACING PROGRAMS
EXPERIMENT NO.7
Aim: Write HDL code to display messages on the given seven segment display and LCD and accepting Hex
key pad input data.

7.a).LCD Display

Procedure:
1. Make the connection between FRC5 of the FPGA board to the LCD display Connector of the VTU card1.
2. Make the connection between FRC 4 of the FPGA board to the keyboard Connector of the VTU card1.
3. Make the connection between FRC 6 of the FPGA board to the dipswitch Connector of the VTU card1.
4. Connect the downloading cable and power supply to the FPGA board
5. Then open the xilinx impact software (refer ISE flow) select the slave Serial mode and select the
respective bit file and click program.
6. Make the reset switch on (active low).
7. Press the hex keys and analyze the data.

VHDL Code for LCD Display Package


--Package for LCD Display (This Package must be added to display all the messages on LCD)
-- Package File Template
-- Purpose: This package defines supplemental types, subtypes, constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package LCD_GRAP is
-- THE NUMBERS
constant ONE : std_logic_vector(7 downto 0) := "00110001";
constant TWO : std_logic_vector(7 downto 0) := "00110010";
constant THREE : std_logic_vector(7 downto 0) := "00110011";
constant FOUR : std_logic_vector(7 downto 0) := "00110100";
constant FIVE : std_logic_vector(7 downto 0) := "00110101";
constant SIX : std_logic_vector(7 downto 0) := "00110110";
constant SEVEN : std_logic_vector(7 downto 0) := "00110111";
constant EIGHT : std_logic_vector(7 downto 0) := "00111000";
constant NINE : std_logic_vector(7 downto 0) := "00111001";
constant ZERO : std_logic_vector(7 downto 0) := "00110000";
-- THE CHARACTERS
constant A : std_logic_vector(7 downto 0) := "01000001";
constant B : std_logic_vector(7 downto 0) := "01000010";
constant C : std_logic_vector(7 downto 0) := "01000011";
constant D : std_logic_vector(7 downto 0) := "01000100";
constant E : std_logic_vector(7 downto 0) := "01000101";
constant F : std_logic_vector(7 downto 0) := "01000110";
constant G : std_logic_vector(7 downto 0) := "01000111";
constant H : std_logic_vector(7 downto 0) := "01001000";
constant I : std_logic_vector(7 downto 0) := "01001001";
constant J : std_logic_vector(7 downto 0) := "01001010";
constant K : std_logic_vector(7 downto 0) := "01001011";
constant L : std_logic_vector(7 downto 0) := "01001100";
constant M : std_logic_vector(7 downto 0) := "01001101";
constant N : std_logic_vector(7 downto 0) := "01001110";
constant O : std_logic_vector(7 downto 0) := "01001111";
constant P : std_logic_vector(7 downto 0) := "01010000";
constant Q: std_logic_vector(7 downto 0) := "01010001";
constant R : std_logic_vector(7 downto 0) := "01010010";
constant S : std_logic_vector(7 downto 0) := "01010011";
constant T : std_logic_vector(7 downto 0) := "01010100";
constant U : std_logic_vector(7 downto 0) := "01010101";
constant V : std_logic_vector(7 downto 0) := "01010110";

37 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

constant W : std_logic_vector(7 downto 0) := "01010111";


constant X : std_logic_vector(7 downto 0) := "01011000";
constant Y : std_logic_vector(7 downto 0) := "01011001";
constant Z : std_logic_vector(7 downto 0) := "01011010";

-- SMAL LETTERS
constant SA : std_logic_vector(7 downto 0) := "01100001";
constant SB : std_logic_vector(7 downto 0) := "01100010";
constant SC : std_logic_vector(7 downto 0) := "01100011";
constant SD : std_logic_vector(7 downto 0) := "01100100";
constant SE : std_logic_vector(7 downto 0) := "01100101";
constant SF : std_logic_vector(7 downto 0) := "01100110";
constant SG : std_logic_vector(7 downto 0) := "01100111";
constant SH : std_logic_vector(7 downto 0) := "01101000";
constant SI : std_logic_vector(7 downto 0) := "01101001";
constant SJ : std_logic_vector(7 downto 0) := "01101010";
constant SK : std_logic_vector(7 downto 0) := "01101011";
constant SL : std_logic_vector(7 downto 0) := "01101100";
constant SM : std_logic_vector(7 downto 0) := "01101101";
constant SN : std_logic_vector(7 downto 0) := "01101110";
constant SO : std_logic_vector(7 downto 0) := "01101111";
constant SP : std_logic_vector(7 downto 0) := "01110000";
constant SQ : std_logic_vector(7 downto 0) := "01110001";
constant SR : std_logic_vector(7 downto 0) := "01110010";
constant SS : std_logic_vector(7 downto 0) := "01110011";
constant ST : std_logic_vector(7 downto 0) := "01110100";
constant SU : std_logic_vector(7 downto 0) := "01110101";
constant SV : std_logic_vector(7 downto 0) := "01110110";
constant SW : std_logic_vector(7 downto 0) := "01110111";
constant SX : std_logic_vector(7 downto 0) := "01111000";
constant SY : std_logic_vector(7 downto 0) := "01111001";
constant SZ : std_logic_vector(7 downto 0) := "01111010";
---THE SYMBOLS
constant SPACE: std_logic_vector(7 downto 0) := "00100000";
constant SLASH: std_logic_vector(7 downto 0) := "00101111";
constant MINUS: std_logic_vector(7 downto 0) := "00101101";
constant EQUAL: std_logic_vector(7 downto 0) := "00111101";
constant PLUS : std_logic_vector(7 downto 0) := "00101011";
constant STAR : std_logic_vector(7 downto 0) := "00101010";
constant DOT : std_logic_vector(7 downto 0) := "00101110";
end LCD_GRAP;

VHDL CODE for LCD Display


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.LCD_GRAP.ALL;
ENTITY HEXKEY_LCD IS
PORT (
CLK: IN STD_LOGIC; -- 16 MHZ CLOCK
RESET: IN STD_LOGIC; -- MASTER RESET PIN
LCD_RW : OUT STD_LOGIC;
LCD_SELECT : OUT STD_LOGIC;
LCD_ENABLE : OUT STD_LOGIC;
ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT
COL: INOUT STD_LOGIC_VECTOR(0 TO 3));
END HEXKEY_LCD;
ARCHITECTURE HEXKEY_BEH OF HEXKEY_LCD IS

38 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1); --
STATE NAMES
TYPE STATE_TYPE IS (INITIAL,DISPLAY,CLEAR,LOCATION,PUTCHAR);
SIGNALSTATE,NEXT_STATE: STATE_TYPE;
-- CLEAR SCREEN.
CONSTANT CLR: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";
-- DISPLAY ON, WITHOUT CURSOR.
CONSTANT DON: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001100";
-- FUNCTION SET FOR 8-BIT DATA TRANSFER AND 2-LINE DISPLAY
CONSTANT SET: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00111000";
--FREQUENCY DIVIDER
CONSTANT BIG_DELAY: INTEGER :=16;
CONSTANT SMALL_DELAY: INTEGER :=2;
CONSTANT REG_SETUP: INTEGER :=1;
SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXTSTATES
SIGNAL DIV_REG: STD_LOGIC_VECTOR (16 DOWNTO 0); -- CLOCK DIVIDE REGISTER
SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);
SIGNAL R1: STD_LOGIC; -- ROW DETECTION SIGNAL
SIGNAL KEY_VALUE: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL DATA: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);
---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------
SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART
BEGIN
IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY
CS <= WAIT_R_0;
ELSIF (DCLK'EVENT AND DCLK = '1') THEN
CS <= NS;
END IF;
END PROCESS;
COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART
BEGIN
CASE CS IS
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED
COL<= "1111"; -- KEEP ALL COLUMNS ACTIVATED
IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?
NS <= C3; -- LET'S FIND OUT
ELSE
NS <= WAIT_R_0;
END IF;
---------------------------------------------------------------------------------------------------
WHEN C3 => --
COL<= "0001"; -- ACTIVATE COLUMN 3
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 3
NS <= C2; -- SO CHECK IF IT WAS IN COLUMN 2
ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN C2 => --
COL<= "0010"; -- ACTIVATE COLUMN 2
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 2
NS <= C1; -- SO CHECK IF IT WAS IN COLUMN 1
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 2
END IF;
---------------------------------------------------------------------------------------------------
WHEN C1 => --
COL<= "0100"; -- ACTIVATE COLUMN 1

39 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 1


NS <= C0; -- SO CHECK IF IT WAS IN COLUMN 0
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 1
END IF;
---------------------------------------------------------------------------------------------------
WHEN C0 => --
COL<= "1000"; -- ACTIVATE COLUMN 0
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??
NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN FOUND => --
COL<= COL_REG_VALUE;
IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIALSTATE
ELSE
NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER
END IF;
---------------------------------------------------------------------------------------------------
WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD FOR
SAMPLING
COL<= COL_REG_VALUE;
NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_1 => --
COL<= COL_REG_VALUE;
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIALSTATE
ELSE
NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED
END IF;
---------------------------------------------------------------------------------------------------
END CASE;
END PROCESS;
---------------------------------------------------------------------------------------------------
WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER
BEGIN
IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE
IF CS = FOUND THEN
DATA <= KEY_VALUE;
END IF;
END IF;
END PROCESS; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER
BEGIN
IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING EDGE
IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU
C0 ONLY
COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID
END IF;
END IF;
END PROCESS; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED KEY
FROM ROW AND
COLUMN
VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);

40 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

BEGIN
CODE := (ROW & COL_REG_VALUE);
CASE CODE IS
-- COL
-- ROW 0 0123
WHEN "00010001" => KEY_VALUE <= ZERO;--KEY 0
WHEN "00010010" => KEY_VALUE <= ONE;--KEY 1
WHEN "00010100" => KEY_VALUE <= TWO;--KEY 2
WHEN "00011000" => KEY_VALUE <= THREE;--KEY 3
-- ROW 1
WHEN "00100001" => KEY_VALUE <= FOUR;--KEY 4
WHEN "00100010" => KEY_VALUE <= FIVE;--KEY 5
WHEN "00100100" => KEY_VALUE <= SIX;--KEY 6
WHEN "00101000" => KEY_VALUE <= SEVEN;--KEY 7
-- ROW 2
WHEN "01000001" => KEY_VALUE <= EIGHT;--KEY 8
WHEN "01000010" => KEY_VALUE <= NINE;--KEY 9
WHEN "01000100" => KEY_VALUE <= A;--KEY A
WHEN "01001000" => KEY_VALUE <= B;--KEY B
-- ROW 3
WHEN "10000001" => KEY_VALUE <= C;--KEY C
WHEN "10000010" => KEY_VALUE <= D;--KEY D
WHEN "10000100" => KEY_VALUE <= E;--KEY E
WHEN "10001000" => KEY_VALUE <= F;--KEY F
WHEN OTHERS => KEY_VALUE <= SPACE; -- JUST IN CASE
END CASE;
END PROCESS; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------
-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY
CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
DIV_REG <= DIV_REG + 1;
END IF;
END PROCESS;
DCLK <= DIV_REG(8);
DDCLK<=DIV_REG(10);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
LCD_RW<='0';
PROCESS (DDCLK,RESET)
VARIABLE COUNT: INTEGERRANGE 0 TO BIG_DELAY;
VARIABLE C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF RESET = '0' THEN
STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF DDCLK'EVENT AND DDCLK = '1' THEN
CASESTATE IS
WHEN INITIAL => -- TO SET THE FUNCTION
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN
STATE<=DISPLAY;

41 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN DISPLAY => -- TO SET DISPLAY ON
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN
STATE<=CLEAR;COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN CLEAR => -- CLEAR THE SCREEN
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN LOCATION => -- CLEAR THE SCREEN
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="11000000";
ELSIF C1="11001111" THEN
C1:="10000000";
ELSE
C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1 ;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=PUTCHAR;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN PUTCHAR=> -- DISPLAY THE CHARACTER ON THE LCD
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
CASE C1 IS

42 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

WHEN "10000000" => LCD_DATA<= H ;--SIGLE LINE


WHEN "10000001" => LCD_DATA<= E ;--SIGLE LINE
WHEN "10000010" => LCD_DATA<= X ;--SIGLE LINE
WHEN "10000011" => LCD_DATA<= SPACE ;--SIGLE LINE
WHEN "10000100" => LCD_DATA<= SPACE ;--SIGLE LINE
WHEN "10000101" => LCD_DATA<= K ;--SIGLE LINE
WHEN "10000110" => LCD_DATA<= E ;--SIGLE LINE
WHEN "10000111" => LCD_DATA<= Y ;--SIGLE LINE
WHEN "10001000" => LCD_DATA<= B ;
WHEN "10001001" => LCD_DATA<= O ;
WHEN "10001010" => LCD_DATA<= A ;
WHEN "10001011" => LCD_DATA<= R ;
WHEN "10001100" => LCD_DATA<= D ;
WHEN "10001101" => LCD_DATA<= SPACE ;
WHEN "10001110" => LCD_DATA<= SPACE ;
WHEN "10001111" => LCD_DATA<= SPACE;
WHEN "11000000" => LCD_DATA<= K ;--SIGLE LINE
WHEN "11000001" => LCD_DATA<= E ;--SIGLE LINE
WHEN "11000010" => LCD_DATA<= Y ;--SIGLE LINE
WHEN "11000011" => LCD_DATA<= P ;--SIGLE LINE
WHEN "11000100" => LCD_DATA<= R ;--SIGLE LINE
WHEN "11000101" => LCD_DATA<= E ;--SIGLE LINE
WHEN "11000110" => LCD_DATA<= S ;--SIGLE LINE
WHEN "11000111" => LCD_DATA<= S ;--SIGLE LINE
WHEN "11001000" => LCD_DATA<= E ;
WHEN "11001001" => LCD_DATA<= D ;
WHEN "11001010" => LCD_DATA<= SPACE ;
-- WHEN "11001011" => LCD_DATA<= RIGHT_ARROW ;
WHEN "11001100" => LCD_DATA<= SPACE ;
WHEN "11001101" => LCD_DATA<= DATA ;
WHEN "11001110" => LCD_DATA<= SPACE ;
WHEN "11001111" => LCD_DATA<= SPACE;
WHEN OTHERS => NULL;
END CASE ;
LCD_SELECT<='1';
IF COUNT=SMALL_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
END CASE;
END IF;
END PROCESS;
END HEXKEY_BEH;

===============================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52" ;
NET "COL<0>" LOC = "P139" ;
NET "COL<1>" LOC = "P134" ;
NET "COL<2>" LOC = "P136" ;
NET "COL<3>" LOC = "P132" ;
NET "LCD_DATA<0>" LOC = "P21" ;
NET "LCD_DATA<1>" LOC = "P23" ;
NET "LCD_DATA<2>" LOC = "P22" ;
NET "LCD_DATA<3>" LOC = "P26" ;
NET "LCD_DATA<4>" LOC = "P27" ;
NET "LCD_DATA<5>" LOC = "P30" ;
NET "LCD_DATA<6>" LOC = "P29" ;
NET "LCD_DATA<7>" LOC = "P31" ;

43 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

NET "LCD_ENABLE" LOC = "P19" ;


NET "LCD_RW" LOC = "P20" ;
NET "LCD_SELECT" LOC = "P4" ;
NET "RESET" LOC = "P41" ;
NET "ROW<0>" LOC = "P126" ;
NET "ROW<1>" LOC = "P129" ;
NET "ROW<2>" LOC = "P124" ;
NET "ROW<3>" LOC = "P122" ;
===============================================================

7)b. SEVEN SEGMENT DISPLAY

Procedure:
1. Make the connection between FRC5 of the FPGA board to the seven-segment connector of the
VTUcard1.
2. Make the connection between FRC 1 of the FPGA board to the keyboard connector of the VTU card.
3. Make the connection between FRC 5 of the FPGA board to the 7segment connector of the VTU card.
4. Connect the downloading cable and power supply to the fpga board.
5. Then open the xilinx impact software (refer ISE flow) select the slave serial mode and select the
respective bit file and click program.
6. Make the reset switch on (active low).
7. Press the hex keys and analyze the data.

VHDL CODE FOR SEVEN DISPLAY


------------------------------------
--CODE FOR SIMULATING 16 KEYS USING
--KEYBOARD PROVIDED ON SPARTAN BOARD
------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY KEY IS
PORT ( COLUMN : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0):=”0001”;
ROW_READ : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK : IN STD_LOGIC;
DISP_SELECT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SEVEN_SEG : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END KEY;

44 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

ARCHITECTURE BEHAVIORAL OF KEY IS


BEGIN

PROCESS(CLK)
BEGIN

IF CLK='1' AND CLK'EVENT THEN


COLUMN <=COLUMN(2 DOWNTO 0)& COLUMN (3); --SHIFTING
END IF;
END PROCESS;

DISP_SELECT <=”1110”; ----TO SELECT DISPLAY

PROCESS(ROW_READ,COLUMN)
BEGIN

CASE COLUMN IS

WHEN "0001" => CASE ROW_READ IS


WHEN "0001" => SEVEN_SEG <= "1111110";
WHEN "0010" => SEVEN_SEG <= "0110011";
WHEN "0100" => SEVEN_SEG <= "1111111";
WHEN "1000" => SEVEN_SEG <= "1001110";
WHEN OTHERS=> SEVEN_SEG <= "0000000";
END CASE;

WHEN "0010" => CASE ROW_READ IS


WHEN "0001" => SEVEN_SEG <= "0110000";
WHEN "0010" => SEVEN_SEG <= "1011011";
WHEN "0100" => SEVEN_SEG <= "1111011";
WHEN "1000" => SEVEN_SEG <= "0111101";
WHEN OTHERS=> SEVEN_SEG <= "0000000";
END CASE;
WHEN "0100" => CASE ROW_READ IS
WHEN "0001" => SEVEN_SEG <= "1101101";
WHEN "0010" => SEVEN_SEG <= "1011111";
WHEN "0100" => SEVEN_SEG <= "1110111";
WHEN "1000" => SEVEN_SEG <= "1001111";
WHEN OTHERS=> SEVEN_SEG <= "0000000";
END CASE;
WHEN "1000" => CASE ROW_READ IS
WHEN "0001" => SEVEN_SEG <= "1111001";
WHEN "0010" => SEVEN_SEG <= "1110000";
WHEN "0100" => SEVEN_SEG <= "0011111";
WHEN "1000" => SEVEN_SEG <= "1000111";
WHEN OTHERS=> SEVEN_SEG <= "0000000";
END CASE;
WHEN OTHERS=> NULL;

END CASE;

END PROCESS;

END BEHAVIORAL;

45 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

===============================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52";
NET "COLUMN <0>" LOC = "P78";
NET "COLUMN <1>" LOC = "P82";
NET "COLUMN <2>" LOC = "P80";
NET "COLUMN <3>" LOC = "P83";
NET "DISP_SELECT<0>" LOC = "P23";
NET "DISP_SELECT <1>" LOC = "P24";
NET "DISP_SELECT <2>" LOC = "P26";
NET "DISP_SELECT <3>" LOC = "P27";
NET "ROW_READ <0>" LOC = "P74";
NET "ROW_READ <1>" LOC = "P76";
NET "ROW_READ <2>" LOC = "P77";
NET "ROW_READ <3>" LOC = "P79";
NET "SEVEN_SEG<0>" LOC = "P18";
NET "SEVEN_SEG <1>" LOC = "P17";
NET "SEVEN_SEG <2>" LOC = "P15";
NET "SEVEN_SEG <3>" LOC = "P14";
NET "SEVEN_SEG <4>" LOC = "P13";
NET "SEVEN_SEG <5>" LOC = "P12";
NET "SEVEN_SEG <6>" LOC = "P1";
===============================================================

Date of Completion of Exp. Staff Signature Remarks

46 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.8
Aim: To control speed and direction of DC motor and Stepper motor.

8.a). DC Motor

Procedure:
1. Make the connection between FRC9 of the fpga board to the dc motor connector of the vtu card2.
2. Make the connection between FRC7 of the fpga board to the keyboard connector of the vtucard2.
3. Make the connection between FRC1 of the fpga board to the dip switch connector of the vtu card2.
4. Connect the downloading cable and power supply to the fpga board.
5. Then open the xilinx impact software (refer ise flow) select the slave serial mode and select the
respective bit file and click program.
6. Make the reset switch on (active low).
7. Press the hex keys and analyze the speed changes.

VHDL CODE FOR DC MOTOR CONTROL


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DCMOTOR IS

PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK


RESET,DIR: IN STD_LOGIC; -- MASTER RESET PIN
PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
RLY: OUT STD_LOGIC;
ROW: IN STD_LOGIC_VECTOR(0 TO 3) ); -- THIS ARE THE ROW LINES
END DCMOTOR;

ARCHITECTURE DCMOTOR1 OF DCMOTOR IS


SIGNAL COUNTER : STD_LOGIC_VECTOR(7 DOWNTO 0):="11111110";
SIGNAL DIV_REG: STD_LOGIC_VECTOR (16 DOWNTO 0); -- CLOCK DIVIDE REGISTER
SIGNAL DDCLK,TICK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL DUTY_CYCLE: INTEGER RANGE 0 TO 255;
BEGIN

47 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY

CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER


BEGIN
IF (CLK'EVENT AND CLK='1') THEN
DIV_REG <= DIV_REG + 1;
END IF;
END PROCESS;
DDCLK<=DIV_REG(12);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
TICK <= ROW(0) AND ROW(1) AND ROW(2) AND ROW(3);

PROCESS(TICK)
BEGIN
IF FALLING_EDGE(TICK) THEN
CASE ROW IS
WHEN "1110" => DUTY_CYCLE <= 255 ; --MOTOR SPEED 1
WHEN "1101" => DUTY_CYCLE <= 200 ; --MOTOR SPEED 2
WHEN "1011" => DUTY_CYCLE <= 150 ; --MOTOR SPEED 3
WHEN "0111" => DUTY_CYCLE <= 100 ; --MOTOR SPEED 4
WHEN OTHERS => DUTY_CYCLE <= 100;
END CASE;
END IF;
END PROCESS;

PROCESS(DDCLK, RESET)
BEGIN
IF RESET = '0' THEN
COUNTER <= (OTHERS => '0');
PWM<="01";
ELSIF (DDCLK'EVENT AND DDCLK = '1') THEN
COUNTER <= COUNTER + 1;
IF COUNTER >= DUTY_CYCLE THEN
PWM(1) <= '0';
ELSE
PWM(1) <= '1';
END IF; END IF;
END PROCESS;
-- RLY<='1'; --MOTOR DIRECTION CONTROL- CLOCK WISE
RLY<=DIR;--MOTOR DIRECTION CONTROL- COUNTER CLOCK WISE
END DCMOTOR1;

==============================================================
UCF FILE (USER CONSTRAINT FILE)
NET "CLK" LOC = "P52" ;
NET "PWM<0>" LOC = "P141" ;
NET "PWM<1>" LOC = "P4" ;
NET "RESET" LOC = "P76" ;
NET "RLY" LOC = "P2" ;
NET "DIR" LOC = "P74" ;
NET "ROW<0>" LOC = "P69" ;
NET "ROW<1>" LOC = "P63" ;
NET "ROW<2>" LOC = "P59" ;
NET "ROW<3>" LOC = "P57" ;
===============================================================
8.b). Stepper Motor

48 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Procedure:
1. Make the connection between FRC9 of the FPGA board to the stepper motor connector of the VTUcard2.
2. Make the connection between FRC1 of the FPGA board to the dip switch connector of the VTUcard2.
3. Connect the downloading cable and power supply to the FPGA board.
4. Then open the xilinx impact software (refer ISE flow) select the slave serial mode and select the
respective bit file and click program.
5. Make the reset switch on (active low).
6. Press the hex keys and analyze the speed changes.

S(3) S(2) S(1) S(0)


1 0 0 1
1 1 0 0
0 1 1 0
0 0 1 1
1 0 0 1

VHDL CODE FOR STEPPER MOTOR CONTROL


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY STEPPER IS
PORT ( DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
ROW: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK,RESET : IN STD_LOGIC;
DIRE: IN STD_LOGIC);
END STEPPER;

ARCHITECTURE BEHAVIORAL OF STEPPER IS


SIGNAL CLK_DIV : STD_LOGIC_VECTOR(25 DOWNTO 0);
SIGNAL CLK_INT: STD_LOGIC;
SIGNAL SHIFT_REG : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN

PROCESS(CLK)
BEGIN

49 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

IF RISING_EDGE (CLK) THEN


CLK_DIV <= CLK_DIV + '1';

CASE ROW IS
WHEN ”00” =>CLK_INT <= CLK_DIV(19);
WHEN ”01”=> CLK_INT<= CLK_DIV(18);
WHEN”10”=> CLK_INT<= CLK_DIV(15);
WHEN OTHERS => CLK_INT<= CLK_DIV(13);
END CASE;
END IF;
END PROCESS;

PROCESS(RESET,CLK_INT)
BEGIN
IF RESET='0' THEN
SHIFT_REG <= "1001";
ELSIF RISING_EDGE(CLK_INT) THEN
CASE DIRE IS
WHEN ‘0’ =>SHIFT_REG <= SHIFT_REG(2 DOWNTO 0) & SHIFT_REG(3);
WHEN ‘1’ =>SHIFT_REG <= SHIFT_REG(0) & SHIFT_REG(3 DOWNTO 1);
WHEN OTHERS => NULL;
END CASE;END IF;
END PROCESS;
DOUT <= SHIFT_REG;
END BEHAVIORAL;

============================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52";
NET "DIRE " LOC = "P74";
NET "DOUT<0>" LOC = "P141";
NET "DOUT<1>" LOC = "P2";
NET "DOUT<2>" LOC = "P4";
NET "DOUT<3>" LOC = "P5";
NET "RESET" LOC = "P76";
NET "ROW<0>" LOC = "P77";
NET "ROW<1>" LOC = "P79";

Date of Completion of Exp. Staff Signature Remarks

50 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.9

Aim: To generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using DAC change the
frequency and amplitude.

Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2.
2. Make the connection between FRC1 of the FPGA board to the dip switch connector of the VTU card2.
3. Connect the downloading cable and power supply to the FPGA board.
4. Then open the xilinx impact software (refer ise flow) select the slave serial mode and select the respective
bit file and click program.
5. Make the reset switch on (active low) and analyze the data.

9.a) SINE WAVE

Max amplitude(5v)=127 sinθ +127


where θ =0,15,30,45………..345

Resolution of the DAC :8 Bit (2pow8=256 steps)

VHDL CODE FOR SINE WAVE


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY DIGITAL_SINE_WAVE IS
PORT ( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));
END DIGITAL_SINE_WAVE ;

ARCHITECTURE BEHAVIORAL OF DIGITAL_SINE_WAVE IS


SIGNAL I: INTEGER RANGE 0 TO 23;
TYPE LOOK_UP IS ARRAY(0 TO 23) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
CONSTANT SINE_LOOKUP:LOOK_UP:=(“01111111”,”10100000”,10111110”,”11011001”,
”11101101”,”11111001”,”11111110”, --0 TO 90
“11111001”,”11101101”,”11011001”,”10111110”,”10100000”,”01111111”, --TILL 180
“01011110”,”00111111”,”00100101”,”00010001”,”00000100”,”00000000”, --TILL 270
“00000100”,”00010001”,”00100101”,”00111111”,”01011110”);
SIGNAL TEMP : STD_LOGIC_VECTOR(2 DOWNTO 0):=”000”;
BEGIN

51 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

PROCESS(CLK)
BEGIN

IF RISING_EDGE(CLK) THEN
TEMP <= TEMP + '1' ;
END IF;

END PROCESS;

PROCESS(TEMP(2))
BEGIN

IF TEMP(2)= '1' AND TEMP(2)’EVENT THEN

IF RST='1' THEN

DAC_OUT<= "00000000";
ELSE
I <= I +1;
DAC_OUT<=SINE_LOOKUP(I);
IF I=23 THEN
I<=0;
END IF;

END IF;

END IF;

END PROCESS;

END BEHAVIORAL;

===========================================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52" ;
NET "DAC_OUT<0>" LOC = "P21" ;
NET "DAC_OUT<1>" LOC = "P18" ;
NET "DAC_OUT<2>" LOC = "P17" ;
NET "DAC_OUT<3>" LOC = "P15" ;
NET "DAC_OUT<4>" LOC = "P14" ;
NET "DAC_OUT<5>" LOC = "P13" ;
NET "DAC_OUT<6>" LOC = "P12" ;
NET "DAC_OUT<7>" LOC = "P1" ;
NET "RST" LOC = "P74" ;

52 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

9.b) SQUARE WAVE

VHDL CODE FOR SQUARE WAVE


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SQUARE_WAVE IS
PORT ( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));
END SQUARE_WAVE;

ARCHITECTURE BEHAVIORAL OF SQUARE_WAVE IS


SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 7);
SIGNAL EN :STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
TEMP <= TEMP + '1' ;
END IF;
END PROCESS;

PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "00000000";
ELSIF RISING_EDGE(TEMP(3)) THEN
IF COUNTER<255 AND EN='0' THEN
COUNTER <= COUNTER + 1 ;
EN<='0';
DAC_OUT <="00000000"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR WAVE)
ELSIF COUNTER=0 THEN
EN<='0';
ELSE
EN<='1';
COUNTER <= COUNTER-1;
DAC_OUT <="11111111"; --DAC_OUT<=COUNTER;(FOR TRIANGULAR WAVE)
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
===============================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52" ;
NET "DAC_OUT<0>" LOC = "P21" ;
NET "DAC_OUT<1>" LOC = "P18" ;
NET "DAC_OUT<2>" LOC = "P17" ;
NET "DAC_OUT<3>" LOC = "P15" ;
NET "DAC_OUT<4>" LOC = "P14" ;
NET "DAC_OUT<5>" LOC = "P13" ;
NET "DAC_OUT<6>" LOC = "P12" ;
NET "DAC_OUT<7>" LOC = "P1" ;
NET "RST" LOC = "P74" ;
===============================================================

53 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

9.c) TRIANGULAR WAVE

VHDL CODE FOR TRIANGULAR WAVE


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TRIANGULAR_WAVE IS
PORT ( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));
END TRIANGULAR_WAVE ;
ARCHITECTURE BEHAVIORAL OF TRIANGULAR_WAVE IS
SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 8);
SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL EN :STD_LOGIC;
BEGIN

PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
TEMP <= TEMP + '1' ;
END IF;
END PROCESS;

PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "000000000";
ELSIF RISING_EDGE(TEMP(3)) THEN
COUNTER <= COUNTER + 1 ;
IF COUNTER(0)='1' THEN
DAC_OUT <=COUNTER(1 TO 8);
ELSE
DAC_OUT <=NOT(COUNTER(1 TO 8));
END IF;END IF;
END PROCESS;

END BEHAVIORAL;

================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52" ;
NET "DAC_OUT<0>" LOC = "P21" ;
NET "DAC_OUT<1>" LOC = "P18" ;
NET "DAC_OUT<2>" LOC = "P17" ;
NET "DAC_OUT<3>" LOC = "P15" ;
NET "DAC_OUT<4>" LOC = "P14" ;
NET "DAC_OUT<5>" LOC = "P13" ;
NET "DAC_OUT<6>" LOC = "P12" ;
NET "DAC_OUT<7>" LOC = "P1" ;
NET "RST" LOC = "P74" ;
================================================

54 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

9.d). RAMP WAVE

VHDL CODE FOR RAMP WAVE


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RAMP_WAVE IS
PORT ( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));
END RAMP_WAVE;

ARCHITECTURE BEHAVIORAL OF RAMP_WAVE IS


SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 7);
SIGNAL EN :STD_LOGIC;
BEGIN

PROCESS(CLK)
BEGIN

IF RISING_EDGE(CLK) THEN
TEMP <= TEMP + '1' ;
END IF;
END PROCESS;

PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "00000000";
ELSIF RISING_EDGE(TEMP(3)) THEN
COUNTER <= COUNTER + 15 ;
END IF;

END PROCESS;

DAC_OUT <=COUNTER;

END BEHAVIORAL;

UCF FILE(USER CONSTRAINT FILE)


NET "CLK" LOC = "P52" ;
NET "DAC_OUT<0>" LOC = "P21" ;
NET "DAC_OUT<1>" LOC = "P18" ;
NET "DAC_OUT<2>" LOC = "P17" ;
NET "DAC_OUT<3>" LOC = "P15" ;
NET "DAC_OUT<4>" LOC = "P14" ;
NET "DAC_OUT<5>" LOC = "P13" ;
NET "DAC_OUT<6>" LOC = "P12" ;
NET "DAC_OUT<7>" LOC = "P1" ;
NET "RST" LOC = "P74" ;

55 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

9.e). SAWTOOTH WAVE

VHDL CODE FOR SAWTOOTH WAVE


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SWATOOTH_WAVE IS
PORT ( CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
DAC_OUT : OUT STD_LOGIC_VECTOR(0 TO 7));
END SWATOOTH_WAVE;

ARCHITECTURE BEHAVIORAL OF SWATOOTH_WAVE IS


SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 7);
SIGNAL EN :STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
TEMP <= TEMP + '1' ;
END IF;
END PROCESS;

PROCESS(TEMP(3))
BEGIN
IF RST='1' THEN
COUNTER <= "00000000";
ELSIF RISING_EDGE(TEMP(3)) THEN
COUNTER <= COUNTER + 1 ;
END IF;
END PROCESS;
DAC_OUT <=COUNTER;
END BEHAVIORAL;

===============================================================
UCF FILE(USER CONSTRAINT FILE)
NET "CLK" LOC = "P52" ;
NET "DAC_OUT<0>" LOC = "P21" ;
NET "DAC_OUT<1>" LOC = "P18" ;
NET "DAC_OUT<2>" LOC = "P17" ;
NET "DAC_OUT<3>" LOC = "P15" ;
NET "DAC_OUT<4>" LOC = "P14" ;
NET "DAC_OUT<5>" LOC = "P13" ;
NET "DAC_OUT<6>" LOC = "P12" ;
NET "DAC_OUT<7>" LOC = "P1" ;
NET "RST" LOC = "P74" ;
===============================================================

Date of Completion of Exp. Staff Signature Remarks

56 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.10

Aim: To control external lights using relays.

Procedure:
1. Make the connection between FRC9 of the FPGA board to the
external light connector of the VTU card2.
2. Make the connection between frc1 of the FPGA board to the dip
switch connector of the VTU card2.
3. Connect the downloading cable and power supply to the FPGA
board.
4. Then open the xilinx impact software (refer ISE flow) select the
slave serial mode and select the respective bit file and click program.
5. Make the reset switch on (active low) and analyze the data.

VHDL CODE FOR EXTERNAL LIGHTS


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY EXTLIGHT IS
PORT ( CNTRL1,CNTRL2 : IN STD_LOGIC;
LIGHT : OUT STD_LOGIC);
END EXTLIGHT;
ARCHITECTURE BEHAVIORAL OF EXTLIGHT IS
BEGIN
LIGHT<= CNTRL1 OR CNTRL2 ;
END BEHAVIORAL;

===============================================================
UCF FILE(USER CONSTRAINT
NET "CNTRL1" LOC = "P74";
NET "CNTRL2" LOC = "P76";
NET "LIGHT" LOC = "P5";

Date of Completion of Exp. Staff Signature Remarks

57 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.11

Aim: To accept 8 channel analog signal, and display the data on LCD panel or seven segment display.

PROCEDURE:
1. Make the connection between frc5 of the FPGA board to the LCD display connector of the VTU card1.
2. Make the connection between frc10 of the FPGA board to the ADC connector of the VTU card1.
3. Make the connection between frc6 of the FPGA board to the dip switch connector of the VTU card1.
4. Short the jumper j1 to the vin to get the analog signal.
5. Connect the downloading cable and power supply to the fpga board.
6. Then open the xilinx impact software (refer ISE flow) select the slave serial mode and select the
respective bit file and click program.
7. Make the reset switch on (active low).
8. Press the hex keys and analyze the data.

VHDL CODING
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.LCD_GRAP.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
ENTITY ADC_LCD IS
PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK
RESET: IN STD_LOGIC; -- MASTER RESET PIN
INTR: IN STD_LOGIC;
ADC_OUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CS,RD,WR:OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_SELECT : OUT STD_LOGIC;
LCD_ENABLE : OUT STD_LOGIC;
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); -- GIVES REGISTERED DATA OUTPUT
END ADC_LCD;
ARCHITECTURE ADC_BEH OF ADC_LCD IS
TYPE STATE_TYPE IS (INITIAL,DISPLAY,CLEAR,LOCATION,PUTCHAR);
SIGNAL STATE,NEXT_STATE: STATE_TYPE;
-- CLEAR SCREEN.
CONSTANT CLR: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";
-- DISPLAY ON, WITHOUT CURSOR.
CONSTANT DON: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001100";
-- FUNCTION SET FOR 8-BIT DATA TRANSFER AND 2-LINE DISPLAY
CONSTANT SET: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00111000";
--FREQUENCY DIVIDER
SIGNAL COUNTER : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL CLK_DIV :STD_LOGIC;
CONSTANT BIG_DELAY: INTEGER :=16;
CONSTANT SMALL_DELAY: INTEGER :=2;
CONSTANT REG_SETUP: INTEGER :=1;
SIGNAL DIGITAL_DATA1,DATA1,DATA2: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DIGITAL_DATA : INTEGER RANGE 0 TO 255;
SIGNAL NTR :STD_LOGIC;
BEGIN
IBUF_INST : IBUF
-- EDIT THE FOLLOWING GENERIC TO SPECIFY THE I/O STANDARD FOR THIS PORT.
GENERIC MAP (
IOSTANDARD => "LVCMOS25")
PORT MAP (
O => NTR, -- BUFFER OUTPUT
I => INTR -- BUFFER INPUT (CONNECT DIRECTLY TO TOP-LEVEL PORT));
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNTER<=COUNTER+'1';
END IF;
END PROCESS;
CLK_DIV<=COUNTER(7);

58 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

CS <='0';
WR <=NTR;
DIGITAL_DATA1 <= ADC_OUT ;
RD <='0';
DIGITAL_DATA<=CONV_INTEGER(DIGITAL_DATA1) ;
PROCESS(DIGITAL_DATA)
BEGIN
CASE (DIGITAL_DATA) IS
WHEN 0 TO 100 => DATA1 <= ONE ; DATA2 <= NINE ;
WHEN 101 TO 110 => DATA1 <= TWO ; DATA2 <= ZERO ;
WHEN 111 TO 120 => DATA1 <= TWO ; DATA2 <= ONE ;
WHEN 121 TO 130 => DATA1 <= TWO ; DATA2 <= TWO ;
WHEN 131 TO 140 => DATA1 <= TWO ; DATA2 <= THREE ;
WHEN 141 TO 150 => DATA1 <= TWO ; DATA2 <= FOUR ;
WHEN 151 TO 160 => DATA1 <= TWO ; DATA2 <= FIVE ;
WHEN 161 TO 170 => DATA1 <= TWO ; DATA2 <= SIX ;
WHEN 171 TO 180 => DATA1 <= TWO ; DATA2 <= SEVEN ;
WHEN 181 TO 190 => DATA1 <= TWO ; DATA2 <= EIGHT ;
WHEN 191 TO 200 => DATA1 <= TWO ; DATA2 <= NINE ;
WHEN 201 TO 205 => DATA1 <= THREE ; DATA2 <= ZERO ;
WHEN 206 TO 210 => DATA1 <= THREE ; DATA2 <= ONE ;
WHEN 211 TO 215 => DATA1 <= THREE ; DATA2 <= TWO ;
WHEN 216 TO 220 => DATA1 <= THREE ; DATA2 <= THREE ;
WHEN 221 TO 225 => DATA1 <= THREE ; DATA2 <= FOUR ;
WHEN 226 TO 230 => DATA1 <= THREE ; DATA2 <= FIVE ;
WHEN 231 TO 235 => DATA1 <= THREE ; DATA2 <= SIX ;
WHEN 236 TO 240 => DATA1 <= THREE ; DATA2 <= SEVEN ;
WHEN 241 TO 245 => DATA1 <= THREE ; DATA2 <= EIGHT ;
WHEN 246 TO 250 => DATA1 <= THREE ; DATA2 <= NINE ;
WHEN OTHERS => DATA1 <= FOUR ; DATA2 <= ZERO ;
END CASE;
END PROCESS;
LCD_RW<='0';
PROCESS (CLK_DIV,RESET)
VARIABLE COUNT: INTEGER RANGE 0 TO BIG_DELAY;
VARIABLE C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF RESET = '1' THEN
STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF CLK_DIV'EVENT AND CLK_DIV = '1' THEN
CASE STATE IS
WHEN INITIAL => -- TO SET THE FUNCTION
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN
STATE<=DISPLAY;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN DISPLAY => -- TO SET DISPLAY ON
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN

59 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

STATE<=CLEAR;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN CLEAR => -- CLEAR THE SCREEN
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN LOCATION => -- CLEAR THE SCREEN
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="10000000";
ELSE
C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1 ;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=PUTCHAR;
COUNT:=0; ELSE
COUNT:=COUNT+1;
END IF;
WHEN PUTCHAR=> -- DISPLAY THE CHARACTER ON THE LCD
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;
CASE C1 IS
WHEN "10000000" => LCD_DATA<= A ;
WHEN "10000001" => LCD_DATA<= D ;
WHEN "10000010" => LCD_DATA<= C ;
WHEN "10000011" => LCD_DATA<= SPACE ;
WHEN "10000100" => LCD_DATA<= V ;
WHEN "10000101" => LCD_DATA<= O ;
WHEN "10000110" => LCD_DATA<= L ;
WHEN "10000111" => LCD_DATA<= T ;
WHEN "10001000" => LCD_DATA<= A ;
WHEN "10001001" => LCD_DATA<= G ;
WHEN "10001010" => LCD_DATA<= E ;
WHEN "10001011" => LCD_DATA<= SPACE ;
WHEN "10001100" => LCD_DATA<= EQUAL ;
WHEN "10001101" => LCD_DATA<= DATA1 ;
WHEN "10001110" => LCD_DATA<= DOT ;
WHEN "10001111" => LCD_DATA<= DATA2;
WHEN "11000000" => LCD_DATA<= SPACE ;
WHEN "11000001" => LCD_DATA<= SPACE ;
WHEN "11000010" => LCD_DATA<= SPACE;
WHEN "11000011" => LCD_DATA<= SPACE ;
WHEN "11000100" => LCD_DATA<= SPACE ;
WHEN "11000101" => LCD_DATA<= SPACE ;
WHEN "11000110" => LCD_DATA<= SPACE ;

60 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

WHEN "11000111" => LCD_DATA<= SPACE ;


WHEN "11001000" => LCD_DATA<= SPACE;
WHEN "11001001" => LCD_DATA<= SPACE ;
WHEN "11001010" => LCD_DATA<= SPACE ;
WHEN "11001011" => LCD_DATA<= SPACE ;
WHEN "11001100" => LCD_DATA<= SPACE ;
WHEN "11001101" => LCD_DATA<= SPACE ;
WHEN "11001110" => LCD_DATA<= SPACE ;
WHEN "11001111" => LCD_DATA<= SPACE;
WHEN OTHERS => NULL;
END CASE ;
LCD_SELECT<='1';
IF COUNT=SMALL_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
END CASE;
END IF;
END PROCESS;
END ADC_BEH;
===============================================================
UCF FILE(USER CONSTRAINT FILE)
NET "RESET" LOC = "P40" ;
NET "CLK" LOC = "P18" ;
NET "CS" LOC = "P6" ;
NET "INTR" LOC = "P12" ;
NET "ADC_OUT<0>" LOC = "P13" ;
NET "ADC_OUT<1>" LOC = "P43" ;
NET "ADC_OUT<2>" LOC = "P44" ;
NET "ADC_OUT<3>" LOC = "P46" ;
NET "ADC_OUT<4>" LOC = "P47" ;
NET "ADC_OUT<5>" LOC = "P49" ;
NET "ADC_OUT<6>" LOC = "P59" ;
NET "ADC_OUT<7>" LOC = "P62" ;
NET "WR" LOC = "P11";
NET "RD" LOC = "P10";
NET "LCD_RW" LOC = "P20";
NET "LCD_SELECT" LOC = "P4";
NET "LCD_ENABLE" LOC = "P19" ;
NET "LCD_DATA<0>" LOC = "P21" ;
NET "LCD_DATA<1>" LOC = "P23" ;
NET "LCD_DATA<2>" LOC = "P22" ;
NET "LCD_DATA<3>" LOC = "P26" ;
NET "LCD_DATA<4>" LOC = "P27" ;
NET "LCD_DATA<5>" LOC = "P30" ;
NET "LCD_DATA<6>" LOC = "P29" ;
NET "LCD_DATA<7>" LOC = "P31" ;
===============================================================

Date of Completion of Exp. Staff Signature Remarks

61 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

EXPERIMENT NO.12

Aim: To operate elevator and observe the simulation results on LCD.

Procedure:
1. Make the connection between FRC5 of the FPGA board to the LCD display connector of the VTU card1.
2. Make the connection between FRC1 of the FPGA board to the keyboard connector of the VTUcard1.
3. make the connection between FRC6 of the FPGA board to the dip switch connector of the VTU card1.
4. Connect the downloading cable and power supply to the FPGA board.
5. Then open the xilinx impact software (refer ISE flow) select the slave serial mode and select the
respective bit file and click program.
6. Make the reset switch on (active low).
7. Press the hex keys and analyze the data.

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.LCD_GRAP.ALL;
ENTITY ELEVATOR IS
GENERIC(BITS : INTEGER := 8 ); -- NUMBER OF BITS USED FOR DUTY CYCLE.
-- ALSO DETERMINES PWM PERIOD.
PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK
RESET,EN: IN STD_LOGIC; -- MASTER RESET PIN
LCD_RW : OUT STD_LOGIC;
PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
LCD_SELECT : OUT STD_LOGIC;
LCD_ENABLE : OUT STD_LOGIC;
ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT
COL: INOUT STD_LOGIC_VECTOR(0 TO 3));
END ELEVATOR;
ARCHITECTURE RTL OF ELEVATOR IS
SIGNAL COUNTER : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0):="00000000";
TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1);
-- STATE NAMES
TYPE STATE_TYPE IS (INITIAL,DISPLAY,CLEAR,LOCATION,PUTCHAR);
SIGNAL STATE,NEXT_STATE: STATE_TYPE;
-- CLEAR SCREEN.
CONSTANT CLR: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";
-- DISPLAY ON, WITHOUT CURSOR.
CONSTANT DON: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001100";
-- FUNCTION SET FOR 8-BIT DATA TRANSFER AND 2-LINE DISPLAY
CONSTANT SET: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00111000";
--FREQUENCY DIVIDER
CONSTANT BIG_DELAY: INTEGER :=16;
CONSTANT SMALL_DELAY: INTEGER :=2;
CONSTANT REG_SETUP: INTEGER :=1;
SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXT STATES
SIGNAL DUTY_CYCLE,DUTY_CYCLE1 : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0);
SIGNAL DIV_REG: STD_LOGIC_VECTOR (22 DOWNTO 0); -- CLOCK DIVIDE REGISTER
SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);
SIGNAL R1,CLK_D,START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL
SIGNAL KEY_VALUE1,FLOOR,KEY_VALUE: INTEGER RANGE 0 TO 15;
SIGNAL DATA,DATA1,FLOOR_NUM: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL TEMP1,TEMP2,TEMP3,TEMP4: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL TEMP5,TEMP6,TEMP7,TEMP8: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
--CLK_OUT <= DCLK;
R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);
---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------
SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART
BEGIN
IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY
CS <= WAIT_R_0;

62 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

ELSIF (DCLK'EVENT AND DCLK = '1') THEN


CS <= NS;
END IF; END PROCESS;
COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART
BEGIN
CASE CS IS
WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED
COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED
IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?
NS <= C3; -- LET'S FIND OUT
ELSE
NS <= WAIT_R_0;
END IF;
---------------------------------------------------------------------------------------------------
WHEN C3 => --
COL <= "0001"; -- ACTIVATE COLUMN 3
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 3
NS <= C2; -- SO CHECK IF IT WAS IN COLUMN 2
ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN C2 => --
COL <= "0010"; -- ACTIVATE COLUMN 2
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 2
NS <= C1; -- SO CHECK IF IT WAS IN COLUMN 1
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 2
END IF;
---------------------------------------------------------------------------------------------------
WHEN C1 => --
COL <= "0100"; -- ACTIVATE COLUMN 1
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 1
NS <= C0; -- SO CHECK IF IT WAS IN COLUMN 0
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 1
END IF;
---------------------------------------------------------------------------------------------------
WHEN C0 => --
COL <= "1000"; -- ACTIVATE COLUMN 0
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??
NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN FOUND => --
COL <= COL_REG_VALUE;
IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIAL STATE
ELSE
NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER
END IF;
---------------------------------------------------------------------------------------------------
WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD FOR
SAMPLING
COL <= COL_REG_VALUE;
NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_1 => --
COL <= COL_REG_VALUE;
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIAL STATE
ELSE
NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED
END IF;
---------------------------------------------------------------------------------------------------
END CASE;
END PROCESS;

63 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

---------------------------------------------------------------------------------------------------
WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER
BEGIN
IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE
IF CS = FOUND THEN
KEY_VALUE <= KEY_VALUE1;
END IF;
END IF;
END PROCESS; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER
BEGIN
IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING EDGE
IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU C0 ONLY
COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID
END IF;
END IF;
END PROCESS; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED KEY FROM
ROW AND
COLUMN
VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);
BEGIN
CODE := (ROW & COL_REG_VALUE);
CASE CODE IS
-- COL
-- ROW 0 0123
WHEN "00010001" => KEY_VALUE1 <= 0;
WHEN "00010010" => KEY_VALUE1 <= 1;
WHEN "00010100" => KEY_VALUE1 <= 2;
WHEN "00011000" => KEY_VALUE1 <= 3;
-- ROW 1
WHEN "00100001" => KEY_VALUE1 <= 4;
WHEN "00100010" => KEY_VALUE1 <= 5;
WHEN "00100100" => KEY_VALUE1 <= 6;
WHEN "00101000" => KEY_VALUE1 <= 7;
-- ROW 2
WHEN "01000001" => KEY_VALUE1 <= 8;
WHEN "01000010" => KEY_VALUE1 <= 9;
WHEN "01000100" => KEY_VALUE1 <= 10;
WHEN "01001000" => KEY_VALUE1 <= 11;
-- ROW 3
WHEN "10000001" => KEY_VALUE1 <= 12;
WHEN "10000010" => KEY_VALUE1 <= 13;
WHEN "10000100" => KEY_VALUE1 <= 14;
WHEN "10001000" => KEY_VALUE1 <= 15;
WHEN OTHERS => KEY_VALUE1 <= 0;
END CASE;
END PROCESS; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------
-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY
CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
DIV_REG <= DIV_REG + 1;
END IF;
END PROCESS;
DCLK <= DIV_REG(8);
DDCLK<=DIV_REG(10);
CLK_D<=DIV_REG(22);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
LCD_RW<='0';
PROCESS (DDCLK,RESET)
VARIABLE COUNT: INTEGER RANGE 0 TO BIG_DELAY;
VARIABLE C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF RESET = '0' THEN

64 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF DDCLK'EVENT AND DDCLK = '1' THEN
CASE STATE IS
WHEN INITIAL => -- TO SET THE FUNCTION
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN
STATE<=DISPLAY;
COUNT:=0;
ELSE COUNT:=COUNT+1;
END IF;
WHEN DISPLAY => -- TO SET DISPLAY ON
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN
STATE<=CLEAR;
COUNT:=0;
ELSE COUNT:=COUNT+1;
END IF;
WHEN CLEAR => -- CLEAR THE SCREEN
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE COUNT:=COUNT+1;
END IF;
WHEN LOCATION => -- CLEAR THE SCREEN
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="11000000";
ELSIF C1="11001111" THEN
C1:="10000000";
ELSE C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=PUTCHAR;
COUNT:=0;
ELSE COUNT:=COUNT+1;
END IF;
WHEN PUTCHAR=> -- DISPLAY THE CHARACTER ON THE LCD
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;

65 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

CASE C1 IS
WHEN "10000000" => LCD_DATA<= F ;--SIGLE LINE
WHEN "10000001" => LCD_DATA<= L ;--SIGLE LINE
WHEN "10000010" => LCD_DATA<= O ;--SIGLE LINE
WHEN "10000011" => LCD_DATA<= O ;--SIGLE LINE
WHEN "10000100" => LCD_DATA<= R ;--SIGLE LINE
WHEN "10000101" => LCD_DATA<= SPACE ;--SIGLE LINE
WHEN "10000110" => LCD_DATA<= N ;--SIGLE LINE
WHEN "10000111" => LCD_DATA<= U ;--SIGLE LINE
WHEN "10001000" => LCD_DATA<= M ;
WHEN "10001001" => LCD_DATA<= B ;
WHEN "10001010" => LCD_DATA<= E ;
WHEN "10001011" => LCD_DATA<= R ;
WHEN "10001100" => LCD_DATA<= SPACE ;
WHEN "10001101" => LCD_DATA<= EQUAL ;
WHEN "10001110" => LCD_DATA<= FLOOR_NUM ;
WHEN "10001111" => LCD_DATA<= SPACE;
WHEN "11000000" => LCD_DATA<= S ;--SIGLE LINE
WHEN "11000001" => LCD_DATA<= T ;--SIGLE LINE
WHEN "11000010" => LCD_DATA<= A ;--SIGLE LINE
WHEN "11000011" => LCD_DATA<= T ;--SIGLE LINE
WHEN "11000100" => LCD_DATA<= U ;--SIGLE LINE
WHEN "11000101" => LCD_DATA<= S ;--SIGLE LINE
WHEN "11000110" => LCD_DATA<= SPACE ;--SIGLE LINE
WHEN "11000111" => LCD_DATA<= TEMP1 ;--SIGLE LINE
WHEN "11001000" => LCD_DATA<= TEMP2 ;
WHEN "11001001" => LCD_DATA<= TEMP3 ;
WHEN "11001010" => LCD_DATA<= TEMP4 ;
WHEN "11001011" => LCD_DATA<= SPACE ;
WHEN "11001100" => LCD_DATA<= TEMP5 ;
WHEN "11001101" => LCD_DATA<= TEMP6 ;
WHEN "11001110" => LCD_DATA<= TEMP7 ;
WHEN "11001111" => LCD_DATA<= TEMP8 ;
WHEN OTHERS => NULL;
END CASE ;
LCD_SELECT<='1';
IF COUNT=SMALL_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE COUNT:=COUNT+1;
END IF; END CASE; END IF; END PROCESS;
PROCESS(CLK_D,RESET)
VARIABLE COU : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL
BEGIN
IF RESET='0' THEN
COU:="00";
TEMP1 <= L ;
TEMP2 <= I ;
TEMP3 <= F ;
TEMP4 <= T ;
TEMP5 <= I ;
TEMP6 <= D ;
TEMP7 <= L ;
TEMP8 <= E ;
FLOOR_NUM <= ZERO ;
ELSIF RISING_EDGE(CLK_D) THEN
CASE KEY_VALUE IS
WHEN 0 => FLOOR_NUM <= ZERO ;
FLOOR <=0;
WHEN 1 => FLOOR_NUM <= ONE ;
FLOOR <=1;
WHEN 2 => FLOOR_NUM <= TWO ;
FLOOR <=2;
WHEN 3 => FLOOR_NUM <= THREE ;
FLOOR <=3;
WHEN 4 =>
TEMP1 <= D ;

66 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= O ;
TEMP6 <= P ;
TEMP7 <= E ;
TEMP8 <= N ;
WHEN 5 =>
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= C ;
TEMP6 <= L ;
TEMP7 <= O ;
TEMP8 <= S ;
WHEN 6 =>
START:='1';
STOP:='0';
WHEN 7 =>
STOP:='1';
START:='0';
==========================================================
WHEN OTHERS =>
UCF FILE(USER CONSTRAINT FILE)
TEMP1 <= I ;
NET "CLK" LOC = "P18" ;
TEMP2 <= D ;
NET "RESET" LOC = "P40" ;
TEMP3 <= L ;
NET "COL<0>" LOC = "P83" ;
TEMP4 <= E ;
NET "COL<1>" LOC = "P79" ;
TEMP5 <= K ;
NET "COL<2>" LOC = "P80" ;
TEMP6 <= E ;
NET "COL<3>" LOC = "P77" ;
TEMP7 <= Y ;
NET "ROW<0>" LOC = "P78" ;
TEMP8 <= SPACE ;
NET "ROW<1>" LOC = "P76" ;
END CASE;
NET "ROW<2>" LOC = "P75" ;
IF START='1' THEN
NET "ROW<3>" LOC = "P74" ;
IF COU=FLOOR THEN
NET "LCD_ENABLE" LOC = "P19" ;
START := '0';
NET "LCD_RW" LOC = "P20" ;
COU:=COU;
NET "LCD_SELECT" LOC = "P4" ;
TEMP7 <= "001100" & COU ;
NET "LCD_DATA<0>" LOC = "P21" ;
ELSIF COU<=FLOOR THEN
NET "LCD_DATA<1>" LOC = "P23" ;
COU:=COU + '1';
NET "LCD_DATA<2>" LOC = "P22" ;
TEMP1 <= U ;
NET "LCD_DATA<3>" LOC = "P26" ;
TEMP2 <= P ;
NET "LCD_DATA<4>" LOC = "P27" ;
TEMP3 <= SPACE ;
NET "LCD_DATA<5>" LOC = "P30" ;
TEMP4 <= SPACE ;
NET "LCD_DATA<6>" LOC = "P29" ;
TEMP5 <= SPACE ;
NET "LCD_DATA<7>" LOC = "P31" ;
TEMP6 <= "01111110" ;
========================================================
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
ELSIF COU>=FLOOR THEN
COU:=COU-'1';
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= W ;
TEMP4 <= N ;
TEMP5 <= SPACE ;
TEMP6 <= "01111111" ;
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
END IF; END IF; END IF;
END PROCESS;
END RTL;

Date of Completion of Exp. Staff Signature Remarks

67 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

Additional Code apart from syllabus

68 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

69 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

VIVA QUESTIONS
1) Differences between D-Latch and D flip-flop?
2) What is setup time and hold time?
3) What is racing condition?
4) What do you mean by comparator and write the truth table?
5) What is decoder and write the truth table?
6) What is encoder and write the truth table?
7) What is priority encoder, and what is the difference between encoder and priority
encoder?
8) What is the difference between decoder and encoder?
9) What is multiplexer and write the truth table?
10) Give the applications of mux?
11) What is the difference between decoder and multiplexer?
12) What do you mean by sequential circuits and combinational circuits?
13) Give the comparison between combinational and sequential circuits.
14) Give the comparison between synchronous and asynchronous circuits.
15) Draw and explain the working of basic bistable element.
16) Draw and explain the working of a) SR latch b) gated SR latch c) Gated D latch.
17) Draw and explain the working of all flip-flops.
18) Explain the working of 4-bit asynchronous counter.
19) What is the difference between synchronous and asynchronous counters?
20) Explain Synchronous and Asynchronous reset.
21) How can you convert a JK flip-flop to a D flip-flop?
22) Define Clock skew , Negative Clock Skew, Positive Clock Skew.
23) Define Metastability.
24) Give the characteristic tables of RS, JK, D and T flip-flops
25) Mention and explain fundamental VHDL units
26) Comparison between VHDL and Verilog
27) Explain compilation, Simulation and synthesis
28) Explain design flow or design process for implementation of hardware
29) Why is it called VHDL code rather than VHDL program
30) Explain all the library packages in VHDL
31) Mention the design units of VHDL
32) Explain VHDL and Verilog codes
33) Explain difference between signal and variable with an example
34) Classify and explain data types in HDL
35) Explain syntax of generic statement
36) Explain structure of data type description
37) Write the syntax of sequential stamens in HDL
38) Explain CASEX and CASEZ statement
39) Explain the highlight of structural description
40) Explain
(a) Binding between entity and architecture in VHDL
(b) Binding between library and module in VHDL
(c) Binding between library and component in VHDL
(d) Binding between two modules in Verilog
41) Explain procedure, task and function in HDL with an Example
42) Difference between task and function?

70 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


HDL LAB

43) Differences between Functions and Procedures in VHDL?


44) What is delta simulation time?
45) What is sensitivity list?
46) What is the difference between wire and reg data type?
47) What is the difference between = = = and = =?
48) What is the difference between unary and logical operators?
49) Difference between blocking and non-blocking?
50) Explain VHDL file processing
51) Explain highlight of mixed language description
52) How to invoke one language from the other
53) Mention the limitation of mixed language disruption
54) Expand the following: PLA, PAL, CPLD, and FPGA.
55) Mention difference between FPGA and CPLD
56) What is LUT?
57) What is the significance of FPGAs in modern day electronics?
58) Give True or False.
(a) CPLD consumes less power per gate when compared to FPGA.
(b) CPLD has more complexity than FPGA
(c) FPGA design is slower than corresponding ASIC design.
(d) FPGA can be used to verify the design before making an ASIC.
(e) PALs have programmable OR plane.
(f) FPGA designs are cheaper than corresponding ASIC, irrespective of design
complexity.
59) What are different types of FPGA? What are you currently using and what is its
clock frequency?
60) Can you draw general structure of FPGA?
61) Why cannot initial statement be synthesizable?
62) Explain the Various steps in Synthesis?
63) Give detail about pattern generator and logic analyzer?
64) Expand XST, ISE, IDE, RTL,xc3s400-5tq144.

71 Department of Electronics & Communication Engineering , K.I.T, Tiptur.


PIN DETAIL OF SPATRON3 XC3S400

FRC1 FRC2 FRC3 FRC4 FRC6 FRC7


FRC XF400 FRC XF400 FRC XF400 FRC XF400 FRC XF400 FRC XF400
1 74 1 84 1 100 1 112 1 28 1 57
2 76 2 85 2 102 2 116 2 31 2 59
3 77 3 86 3 124 3 119 3 33 3 63
4 79 4 87 4 103 4 118 4 44 4 69
5 78 5 89 5 105 5 123 5 46 5 68
6 82 6 90 6 107 6 131 6 47 6 73
7 80 7 92 7 108 7 130 7 50 7 70
8 83 8 96 8 113 8 137 8 51 8 20
9 VCC 9 VCC 9 VCC 9 VCC 9 VCC 9 VCC
10 GND 10 GND 10 GND 10 GND 10 GND 10 GND

FRC5 FRC8 FRC10 FRC9


FRC XF400 FRC XF400 FRC XF400 FRC XF400
1 1 1 93 1 60 1 5
2 12 2 95 2 56 2 4
3 13 3 97 3 41 3 2
4 14 4 98 4 40 4 141
5 15 5 99 5 36 5 VCC
6 17 6 104 6 35 6 GND
7 18 7 125 7 32
8 21 8 122 8 10
9 23 9 129 9 11
10 24 10 132 10 8
11 26 11 135 11 7
12 27 12 140 12 6
13 5V 13 5V 13 5V
14 -5 14 -5 14 -5
15 VCC 15 VCC 15 VCC CLK
16 GND 16 GND 16 GND 52

*USE FRC 9 FOR DC AND STEPPER MOTOR

*USE FRC 5 FOR DAC