Modeling of Spatially Distributed Microwave Circuits Michael Steer1 Andreas Cangellaris2

1
Department of Electrical and Computer Engineering North Carolina State University Raleigh, North Carolina USA, 27695 m.b.steer@ieee.org

Outline
Why is it so difficult to design and model circuits with spatially distributed elements
Revisit circuit and network theory Revisit the concept of ground Circuit Theory for Spatially Distributed Systems

2
Department of Electrical and Computer Engineering University of Illinois, Urbana Champaign Urbana Champaign, Illinois USA, 61801 cangella@uiuc.edu

Research tools that address spatially distributed circuits Examples (throughout)
Opto Electronic Modeling On-Chip Supply/Ground Modeling

IMS2005

Workshop WFG: REDISCOVERING CIRCUIT DESIGN TECHNIQUES FOR MICROWAVE COMPONENTS, CIRCUITS AND SUBSYSTEMS: THE EFFICIENCY AND POWER OF EM/CIRCUIT CODESIGN

Mixed Signal System
Only really have good EDA solutions for digital.
DIGITAL ANALOG (feedback) RF (no feedback) MICROWAVE (distributed)

Motivation
Many HARD modeling problems:
PACKAGE (distributed)

Reflector VCSEL Lens

Is there a common solution strategy?

VCSEL Modeling with Optical Feedback

YES! = Local Reference Terminals

RF design is difficult as EDA cannot be used EDA to determine the system performance measures.. To streamline design we must revolutionize our ability to predict system performance.

OPTICAL

MECHANICAL

S

G

D

Delay

Active Antennas

Courtesy Rockwell Science Center

Background Reading

Where is ground? A fundamental consideration in handling spatially distributed circuits. Circuits (conventionally) have a single ground.

Background Reading

Microstrip Model
In a Field Simulator Voltages Are Determined By Integrating The Electric Field Along a Path In Microstrip Problems the Field is Integrated Over The Paths Shown to Obtain V The Path of Integration Matters The Dashed Path Yields a Different Value of V2
V
1

V
2

Not the same point electrically.

Microstrip Model
V1
REF

Local reference terminal concept This avoids non-physical connections and therefore is fundamental for the analysis of spatially distributed circuits as well as for simultaneous thermal-electrical simulations.

V2
REF REF

V1

V2
REF

V1
REF Network Model:

V2
REF

LOCAL REFERENCE TERMINAL

⎡ S11 ⎢S ⎣ 21

S12 ⎤ But a (SPICE) Circuit does not have two ⎥ reference terminals. S 22 ⎦

How to extend this beyond two terminal ports?

Modeling a Transformer
IDEAL TRANSFORMER

Modeling Transformer Network
IDEAL TRANSFORMERS IN SPICE Or your Favorite simulator NO BETTER

TWO LOCAL REFERENCE NODES

1 MΩ IN SPICE Or your Favorite simulator

=

OR

= 1 MΩ

Modeling Transformer Network Local Reference Group Concept
Really need simulator support for multiple ‘grounds’ i.e. local reference terminals

Local reference node concept This avoids non-physical connections and therefore is fundamental for the analysis of spatially distributed circuits as well as for simultaneous thermal-electrical simulations.

V1
REF
LOCAL REFERENCE TERMINAL Our common view of a port is that it has two terminals

V2
REF

i1

i2

1
i1

2
i2

=

How to extend this beyond two terminal ports?
Local Reference Terminal

Spatially Distributed Modeling

KEY CONCEPT:
LOCAL REFERENCE TERMINAL

Quasi-Optical Amplifier

Kunisch and Wolff
(preliminary concept)

Khalil and Steer
(full concept)

KCL applies to this local reference group
This is a multi terminal port!

Nodal Admittance Matrix Determination
Nodal Admittance Description Required in Microwave Circuit Simulators Process: Guess a node voltage and calculate node current.

Locally Reference Group (Single Local Reference Terminal)

LOCAL REFERENCE NODE

Using MOM model to develop model of spatially distributed system.

Grid Amplifier (Spatial Power Combiner)
It is important to do circuit/field co-simulation More accurate. Uncover unexpected physics. Comparison of measured and simulated results.
BEAM CENTER

Things learnt when it is done right. Role of Symmetry

BEAM CENTER

Full linear + nonlinear simulation with integrated field solution

BEAM CENTER

Symmetry Broken

Things learnt when it is done right. Role of Symmetry

Symmetry Lessons Learnt

GRID SYMMETRY
BEAM CENTER

CIRCUIT SYMMETRY

HORIZONTAL AXIS OF LINEAR SYMMETRY

VERTICAL AXIS OF LINEAR SYMMETRY

NORMAL AXIS OF CIRCULAR SYMMETRY

The grid symmetry and circuit symmetry are fundamentally incompatible.

Symmetry Effects

Modeling Concept
NO PLANE OF SYMMETRY NO POINT OF SYMMETRY
SPATIALLY DISTRIBUTED CIRCUIT LINEAR CIRCUIT NONLINEAR NETWORK

LINEAR CIRCUIT

LINEAR NETWORK

THERMAL NETWORK

+ Optoelectronic + Any other physics Incorporate using locally referenced groups.

EM-PDK (Em-Aware Process Design Kit)
Layout Mixed Layout ElectricTM EM – Aware Technology file fREEDA® Parasitic Extractor

LAYOUT

ELECTRIC

EM-PDK
MESH GENERATION

G2M
Commercial MESHER

DC2LIGHT
MACROMODEL
NETLIST SIMULATION

UIUC2D

S2IBIS R,L,C,G PRIME
⎛ a ai ⎞ ⎟G i Y( s) = G 0 + sC 0 + ∑ ⎜ i + ⎜ s − pi ⎟ i ⎝ s − pi ⎠

Integrating Electric & EM-PDK

EM-PDK (Java) is both a stand alone program and integrated into Electric.
STAND ALONE MODE: PARSES A LAYOUT FILE AND EXTRACTS EM FEATURES, EM_Aware, CREATES CIF OUTPUT. (METALS, DIELECTRICS THICKNESSES AND PROPERTIES ONLY). PASS TO EM SIMULATOR. ELECTRIC MODE IDENTIFIES LOCAL REFERENCE GROUPS AND ASSIGNS LOCAL REFERENCE TERMINALS. ASSIGNS TERMINAL NUMBERS. CREATES SPICE FILE + EM-Aware LAYOUT FILE

SCHEMATIC
+ L L

f REEDA
CIRCUIT SIMULATION

Electric (Editor)
Handles MOS-Bipolar Handles MOS-Bipolar Schematics, HDLs Common Layout-Schematic Interface Supports CIF, GDS II, VHDL, Verilog etc.. Custom IC layout tool. NCSU MILESTONE Modifications made to include naming of nodes at points of connection between schematic and layout. Support for materials properties added. Modifications to be included in next release of Electric Editor.

EM-fREEDA-Spice Interface
Step 1. Foster’s model fit to simulated or measured frequency data. GO TO fREEDA directly Step 2. Synthesize R, L, C, K subcircuit (many elements) GO TO Spice
Why Foster’s model ? It is a convenient method that facilitates the direct synthesis of an equivalent circuit representation of the power distribution network. Further this method is guaranteed to be causal and circumvents the problem of implementing reduced order models with problems concerning stability (AWE method), aliasing (Convolution based on Impulse response) and series approximations problem (Numerical Inversion of Laplace Transform Technique).

Coupled Inductors

• Layer Thickness. • Loss Tangent. • Dielectric Constant.

Foster’s canonical representation :
m m
+

H(s) = ∑

kj j =1 s – pj


j =1

aj s – pj

+

aj* s – pj*

Indicates LRT

where kj /(s-pj) represents the real pole and aj/(s-pj) and aj*/(s-pj*) together represents the complex conjugate pair

EM-fREEDA Interface
N-Port Foster Model
PORT 1 LRG 1 o o PORT2 o LRG 2 o Foster N – Terminal Network

Multigrid-Enhanced EM Modeling of the Power Grid On Chip Maxwell equation’s-based modeling
Finite Volume model

Key Attributes
The transfer function is given as, I(s) = H(s)V(s) Model developed directly from physical structure Cumbersome and error-prone extraction of [L] and [C] avoided Rigorous modeling of electromagnetic effects In addition to power switching noise analysis it enables prediction of power grid-induced EMI between different blocks on the chip

PORT N LRG N

o o

FV-Based Modeling Methodology
Finite-volume discretization of Maxwell’s equations

Implementation of Variable-Size Grid
Ex Ez Hz

∫C

E ⋅ dl = −
F

d µ H ⋅ dS dt ∫∫ SF

d ∫ C A H ⋅ dl = dt ∫∫S A ε E ⋅ dS + ∫∫S A σ E ⋅ dS Micron-size cross-sectional dimensions and regular layout of the grid exploited to contain model complexity
Grid size of the order of grid feature size Assignment of unknown electric & magnetic fields in space dictated by the electromagnetic effects that must be captured for accurate simulation
Ohmic loss in the wires Inductive effects during switching Capacitive coupling and common impedance coupling for grid-induced interference calculation

Ey Hy (a) Coarse Grid

z

y

Fine Grid

The choice of grid coarseness is dependent on the simulation objective and the desired accuracy.
Switching noise simulation only: Coarse grid Power grid-induced interference: Finer grid

Compatibility with SPICE
The state-space form of the discrete model,
⎡G ⎢D ⎣ e Dh ⎤ ⎡ e ⎤ ⎡ C 0 ⎤ d ⎡ e ⎤ ⎡ i S ⎤ + = R ⎥ ⎢h ⎥ ⎢ 0 L ⎥ dt ⎢ h ⎥ ⎢ v S ⎥ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎣ ⎦ ⎦

“Cartoon” of the On-Chip Grid

is of the same form with the MNA formalism used in SPICE Hence, it facilitates direct incorporation of lumped circuits and behavioral models for drivers and receivers
e , h : the discrete unknown fields G, R, L, C, Dh, De : sparse matrices (dependent on material and geometric properties of the structure) iS, vS : voltage & current sources connected to the grid

Top view of Metal-1 Layer
Inverter Model

Additional Features of Solver
Convenient interface to models for the offchip power grid
Can be incorporated either in terms of SPICE net lists or in terms of a matrix rational function representation of their multi-port form

Si Substrate

Modeling of the semiconductor substrate
Effected through position- and frequencydependent surface impedance relationships cast in terms of rational functions

Impact of semiconductor substrate on power grid switching response
t3 t2 t1
SiO2 p- epitaxy ε3 , µ3=µ 0 , σ3= 0 ε2 , µ2=µ 0 , σ2≠ 0 ε1 , µ1=µ 0 , σ1≠ 0 z x y

Impact of semiconductor substrate…
1.6 1.4 1.2 1 Case0 Case1 Case2 Gate Input

Voltage (V)

0.8 0.6 0.4 0.2

p+ bulk

Suppressed overshoot and oscillation

Case 0: Semiconductor substrate modeled as PEC Case 1: t1 = 198 µm, σ1 = 104 S/m, t2 = 2 µm, and σ2 = 10 S/m Case 2: t1 = 200 µm, σ1 = 104 S/m, t2 = 0 (no epi)

0 -0.2 -0.4 0 50 100 150 200 250 300

Time (ps)

Transient EM Modeling of Power Switching
Visualization of on-chip supply voltage disturbance during simultaneous switching at all nodes

Transient EM Modeling of Power Switching
Visualization of on-chip supply voltage disturbance during switching of drivers in central region only

Modeling of Substrate Noise
Volts 0 Simulation 0 Buffer -0.5 Output -1 -1.8 Millivolts -20 -40 -60 1.4 1.8 2.2 Time (µs) 2.6 -1.5 -2 20 0 Sensor -20 Output -40 -60 -80 -100 1 3 Millivolts Volts Experiment

Summary
On-Chip Power Grid Transient Simulator
Electromagnetic rigor Comprehensive modeling
Includes impact of semiconductor substrate

SPICE Compatible
Direct implementation of SPICE models for non-linear drivers, decoupling caps, etc… Supports convenient interfacing with models for the off-chip power distribution network

1

1.4

1.8 2.2 Time (µs)

2.6

3

Long interconnect from buffer output to pad: Its coupling to substrate critical for accurate prediction of substrate-induced noise

Distributed Noise Injector Noise injector Noise sensor

Supports both simultaneous switching noise and power grid-induced interference prediction

Optoelectronic Modeling
Feedback Modeling:
Optical Component Feedback:
Optical systems have reflective surfaces Small feedback can effect laser dynamics Optical component reflection study is important fREEDA enables component reflection modeling

VCSEL
VCSEL
P-contact GaAs AlA s

VCSEL Feedback Results:
Power and Wavelength degradation due to two components
f1=12mm, R=0.04
GaAs

AlAs Oxide

In0.2Ga0.8As

f2=12mm, R=0.04

Al0.8Ga0.2As

Vcsel Lens1 Lens2

Detector

Modeling Approach:
Calculate resultant field at each component Back propagate the resultant field to laser
Laser output sensitive to feedback phase

N-contact

z=12mm

z=12mm Output power degradation due to single and double lens feedback

Optical Power
No feedback

Wavelength

No feedback

L1 feedback

L1 feedback

VCSEL

Detector

L1+L2 feedback

Output wavelength degradation due to single and double lens feedback

L1+L2 feedback

Nonlinear Electro-Thermal Element
i ELECTRICAL COMPONENT i = f(x1,x2) v= g(x1,x2) T= x2 v,i h THERMAL COMPONENT h(t)=h(v(t),i(t)) T v

Nonlinear Electro-Thermal Element
NONLINEAR ELECTRO-THERMAL ELEMENT
i ELECTRICAL COMPONENT i = f(x1,x2) v= g(x1,x2) T= x2 v,i h THERMAL COMPONENT h(t)=h(v(t),i(t)) T v

LINEAR ELECTRICAL NETWORK

LINEAR ELECTRICAL NETWORK

THERMAL NETWORK

THERMAL NETWORK

THERMAL GROUND (0 K) THERMAL GROUND (0 K)

Time Delays
Spice handles only short (< 3 time step) time delays.
10
4

fREEDA Multiphysics Simulator
Product: fREEDA
10 Observed delay (ns)
3

TWTA used to validated fREEDA’s ability to handle models with long time delays. Also implemented in many transistor models. Validation in Progress
Input Terminal Voltage (volts) 1 0.5 0 -0.5 -1 0 3 2 1 0 -1 -2 -3 0 2000 4000 6000 8000 Time (ps) 10000 12000 14000 2000 4000 6000 8000 Time (ps) 10000 12000 14000

10

2

REQUIREMENTS FOR FIRST PASS DESIGNS: A Rapid development of models B 140 dB dynamic range required C Integration of tools. (new concepts for mixed digital/analog simulation; transmission lines in transient simulators) D Achieve 1 or 2 fab cycles (need exact emulation)

10

1

10 0 10

0

10

1

10 Specified delay (ns)

2

10

3

10

4

Extracted amplitude and time-delay parameters for in-band linear and nonlinear (3,5,7th order) from 8510C measurements of an HP 495A TWTA. Created TWTA model using 4 instances of Vccsd with extracted parameters. Voltage gain ~10, transit time ~10.5 nsec reflect well in simulated results. (Sinusoidal input at 7.5 GHz.)

STATE-OF-THE-ART AT START OF PROGRAM: A Limited ability to model new devices B Inadequate dynamic range 40–60 dB C Many unconnected EDA tools D NRE for a mixed signal chip $50M + 2 years (Bluetooth/802.11 complexity, 8–20 fab cycles)

TECHNOLOGIES DEVELOPED A Rapid development of models (completed) (6 days versus 1 year in spice, e.g. BSIM3SOIv3 ) B 140 dB dynamic range required to determine actual performance (achieved 160 dB) C Proven distributed circuit concepts: True time delay for the first time; multiphysics/multiscale environment. D Experimental validation of precise simulations.

Output Terminal Voltage (volts)

Major features
Feature Dynamic Range Multi Physics Time Delay Initial State of The Art
40–60 dB SPICE > 120 dB ADS

Accessibility
Goal 140 dB Thermal / EM / Circuit Unlimited Achieved 160 dB Thermal / EM / Circuit Unlimited
fREEDA runs on all Linux and cygwin flavors Can be downloaded as a single executable on windows (16 MB) (Must first install cygwin) Improved Documentation (on line)

Limited 2 or 3 time steps

www.freeda.org

Transient Dynamic Range 0.05
(Defined as the detection of a small signal in the presence of a 0.04 large signal.)
Primarily achieved through • better error estimation • better time point selection
SPICE (UCB) Algorithm

Time Delays
Spice handles only short (< 4 time step) time delays. fREEDA has no limit X-band MMIC 160 dB TWTA used to validated fREEDA’s ability to handle models with long time delays. Also implemented in many transistor models.
Input Terminal Voltage (volts) 1 0.5 0 -0.5 -1 0 3 2 1 0 -1 -2 -3 0 2000 4000 6000 8000 Time (ps) 10000 12000 14000 2000 4000 6000 8000 Time (ps) 10000 12000 14000
10 0 10
0

10

4

10 Observed delay (ns)

3

0.03

10

2

Error
0.02

10

1

40 dB line CONVENTIONAL

10

1

10 Specified delay (ns)

2

10

3

10

4

Result from Error estimate Backward Euler

0.01
IDEAL RESULT

Output Terminal Voltage (volts)

Result from trapezoidal

NEW

1 ns

0
Tn-1 Tn Tn+1

0

0.002 0.004 0.006 0.008 0.01

Tolerance

Products
Delivery of best in class software tools: (beta release)
fREEDA
High dynamic range multi physics circuit simulator Easy development of advanced device models Now available as single binary for Windows (16 MB)

Conclusions New Circuit Concept

S2IBIS3
Digital macromodeling tool

EMPDK
Em-Aware physical design kit tool (JAVA) (Can also be run in conjunction with Electric Editor)

V1
REF
LOCAL REFERENCE TERMINAL Our common view of a port is that it has two terminals

V2
REF

UIUC2D EM modeling tool for 2D geometries ICWAVE
On chip, comprehensive, 3D EM modeling

PRIME
EM reduced Order Model macromodeler tool (Foster Model) Directly interfaces with fREEDA Synthesizes R, L, C, K models for Spice.

i1

i2

1
i1

2
i2

All packages can be accessed through http://www.freeda.org
PRIME and UIUC2D http://alpha1.ece.uiuc.edu/download For PRIME: username: prime pwd: fitting For UIUC2D: username: uiuc2d pwd: rlcgsyn For ICWAVE Contact Andreas Cangellaris

How to extend this beyond two terminal ports?

Acknowledgements
UIUC TEAM Integral Equation Solvers
V. Okhmatovski A. Rong J. Morsey V. Kourkoulos

NCSU TEAM Simulator
C. Christofferson S. Luniya S. Wang S. Skaggs F. Hart M. Basel C.-R. Chang P. Heron W. Kanj G. Rhyne

EM-Circuit Integration
M. Abdullah A. Khalil J. Patwardhan S. Nakazawa C. Hicks U. Mughal T. Nuteson M. Summers R. Mohan R. Bollapragada S. Uppathil B. Biswas

FEM Solvers
T. Yioultsis L. Proekt (Post-doc)

Model Order Reduction
T. Yioultsis J. Morsey

Sponsors: DARPA Army Research Office

Modeling
N. Kriplani S. Velu H. Guiterrez W. Jang

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