DSP Builder Handbook Volume 1: Introduction to DSP Builder

101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_INTRO-2.0

Document Version: Document Date:

2.0 December 2010

Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Contents

Chapter 1. Introducing DSP Design
DSP Systems in FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 FPGA Architecture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Software Design Flow with DSP Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 DSP Design Flow in FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Software Flow in FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Software with Hardware Acceleration Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Hardware Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5

Chapter 2. Introducing DSP Builder
Standard and Advanced Blocksets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Standard Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Tool Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Qsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

Chapter 3. Installing DSP Builder
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Obtaining and Installing DSP Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Downloading DSP Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Installing DSP Builder on Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Installing DSP Builder on Linux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Manual Configuration of the MATLAB Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 DSP Builder Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Using Previous Versions of DSP Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Previous Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 DSP Builder Start Up Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 MATLAB Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Directory Path Names in MATLAB Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Using Multiple Versions of MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Standard Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Using 32-bit MATLAB on 64-bit Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Licensing DSP Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Appending the License to Your license.dat File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Specifying the License File Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9

Chapter 4. Updating From Earlier Versions
Updating Models From the Previous Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Limitations of the Update Model Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Using a Simulink Library Forwarding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Updating the IP Cores in your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3

Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

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How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

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1. Introducing DSP Design

This chapter introduces using DSP Builder for digital signal processing (DSP) designs on Altera FPGAs. It introduces the DSP Builder standard and advanced blocksets, and the Altera-provided DSP IP libraries.

DSP Systems in FPGAs
The DSP market includes the following rapidly evolving applications, which cover a broad spectrum of performance and cost requirements:
■ ■ ■ ■ ■ ■ ■

3G wireless Voice over Internet protocol (VoIP) Multimedia systems Radar and satellite systems Medical systems Image-processing applications Consumer electronics.

Specialized DSP processors can implement many of these applications. Although these DSP processors are programmable through software, their hardware architecture is not flexible. Therefore, fixed hardware architecture such as bus performance bottlenecks, a fixed number of multiply accumulate (MAC) blocks, fixed memory, fixed hardware accelerator blocks, and fixed data widths limit DSP processors. The DSP processor’s fixed hardware architecture is not suitable for some applications that require customized DSP function implementations. FPGAs provide a reconfigurable solution for implementing DSP applications, higher DSP throughput, and more raw data processing power than DSP processors. You can reconfigure FPGAs in hardware, therefore they offer complete hardware customization while implementing various DSP applications. You can customize the architecture, bus structure, memory, hardware accelerator blocks, and the number of MAC blocks in an FPGA system.

FPGA Architecture Features
You can configure FPGAs to operate in different modes corresponding to a required functionality. This hardware flexibility allows you to use a suitable hardware description language (HDL) such as VHDL or Verilog HDL to implement any hardware design. Thus, the same FPGA can implement a DSL router, a DSL modem, a JPEG encoder, a digital broadcast system, or a backplane switch fabric interface.

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Chapter 1: Introducing DSP Design FPGA Architecture Features

High-density FPGAs incorporate embedded silicon features that can implement complete systems inside an FPGA, creating a system on a programmable chip (SOPC) implementation. Embedded silicon features such as embedded memory, DSP blocks, and embedded processors are ideally suited for implementing DSP functions such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), correlators, equalizers, encoders, and decoders. The embedded DSP blocks also provide other functionality such as accumulation, addition and subtraction, and summation, which are common arithmetic operations in DSP functions. Altera FPGAs offer much more multiplier bandwidth than DSP processors, which only offer a limited number of multipliers. One determining factor of the overall DSP bandwidth is the multiplier bandwidth, therefore the overall DSP bandwidth of FPGAs can be much higher using FPGAs than with a DSP processors. Many DSP applications use external memory devices to manage large amounts of data processing. The embedded memory in FPGAs meets these requirements and also eliminates the need for external memory devices in some cases. Embedded processors in FPGAs provide overall system integration and flexibility while partitioning the system between hardware and software. You can implement the system’s software components in the embedded processors and implement the hardware components in the FPGA's general logic resources. Altera devices provide a choice between embedded soft core processors and embedded hard core processors. You can implement soft core processors such as the Nios® II embedded processor in FPGAs and add multiple system peripherals. The Nios II processor supports a user-determinable multi-master bus architecture that optimizes the bus bandwidth and removes potential bottlenecks found in DSP processors. You can use multimaster buses to define as many buses and as much performance as needed for a particular application. Off-the-shelf DSP processors make compromises between size and performance when they choose the number of data buses on the chip, potentially limiting performance. Soft embedded processors in FPGAs provide access to custom instructions such as the MUL instruction in Nios II processors that can perform a multiplication operation in two clock cycles using hardware multipliers. FPGA devices provide a flexible platform to accelerate performance-critical functions in hardware because of the configurability of the device’s logic resources. DSP processors have predefined hardware accelerator blocks, but FPGAs can implement hardware accelerators for each application, allowing the best achievable performance from hardware acceleration. You can implement hardware accelerator blocks with parameterizable IP functions or from scratch using HDL. f Altera offers many IP cores for DSP design, for more information about these IP cores, refer to Chapter 2, Introducing DSP IP Cores. You can parameterize Altera DSP IP cores for the most efficient hardware implementation and to provide maximum flexibility. You can easily port the IP to new FPGA families, leading to higher performance and lower cost. The flexibility of programmable logic and soft IP cores allows you to quickly adapt your designs to new standards without waiting for long lead times usually associated with DSP processors.

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Chapter 1: Introducing DSP Design Software Design Flow with DSP Processors

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Software Design Flow with DSP Processors
Figure 1–1 shows the typical software design flow that DSP programmers follow.
Figure 1–1. Software-Based DSP Design Flow

Use MATLAB or Simulink to Design Algorithm

Write Assembly or C Code

Add DSP Libraries

Use DSP Processor Tools (Compiler, Assembler, Linker, and Debugger) to Implement Algorithm

You can use algorithm development tools such as MATLAB to optimize DSP algorithms and Simulink for system-level modeling. The algorithms and the system-level models are then implemented in C/C++ or assembly code with an integrated development environment that provides design, simulation, debug, and real-time verification tools. You can use standard C-based DSP libraries to shorten design cycles and derive the benefits of design re-use.

DSP Design Flow in FPGAs
Traditionally, DSP systems were implemented in FPGAs using the hardware flow based on a HDL language such as Verilog HDL and VHDL. Altera tools such as DSP Builder, Qsys, and the Nios II embedded design suite (EDS) enable you to follow a software-based design flow while targeting FPGAs. The DSP Builder tool simplifies hardware implementation of DSP functions, provides a system-level verification tool to the system engineer who is not necessarily familiar with HDL design flow, and allows the system engineer to implement DSP functions in FPGAs without learning HDL. Altera's DSP Builder tool provides an interface from Simulink directly to the FPGA hardware (Figure 1–2). Additionally, you can incorporate the designs created by DSP Builder into a Qsys system for a complete DSP system implementation

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Figure 1–2. DSP Builder General Design Flow for Altera FPGAs
Use MATLAB or Simulink to Design Algorithm

Add Functions in DSP Builder

DSP Libraries

Perform Synthesis, Place-and-Route (Quartus IISoftware)

Evaluate Hardware in a DSP Development Kit

Figure 1–3 shows the various design-flow options available for FPGAs.
Figure 1–3. FPGA-Based DSP Design Flow Options
Software Flow Software and Hardware Acceleration Flow Hardware Flow

Develop DSP Algorithm Model System

Develop DSP Algorithm Model System

Develop DSP Algorithm Model System

Build System

Use Software Library

Develop Software

Design DSP Hardware Accelerator Functions Use Software Library

Translate to HDL Develop Software

Build System

Configure FPGA

Configure FPGA

Configure FPGA

Software Flow in FPGAs
Altera FPGAs with embedded processors support a software-based design flow. Altera provides the Nios II EDS development tools for compiling, debugging, assembling, and linking software designs. You can then download these software designs to an FPGA using either on-chip RAM or an external memory device.

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Software with Hardware Acceleration Flow
Embedded processors and hardware acceleration offer the flexibility, performance, and cost effectiveness in a development flow that is familiar to software developers. You can combine a software design flow with hardware acceleration. In this flow, you first profile C code and identify the functions that are the most performance-intensive. Then, you can use Altera's DSP IP or develop your own custom instructions to accelerate those tasks in the FPGA. You can run the system control code with the other low-performance DSP algorithms on a Nios II embedded processor. Altera also provides system integration tools such as Qsys for system-level partitioning and interconnection. You can use Qsys to build entire hardware systems by combining the embedded processor, such as a Nios II embedded processor, with other system peripherals and IP cores.

Hardware Design Flow
You can use an HDL-based hardware design flow to develop a pure hardware implementation of a DSP system. Altera provides a complete set of FPGA development tools including the Quartus® II software and interfaces to other EDA tools such as Synopsys, Synplify, and Precision Synthesis. These tools enable hardware design, simulation, debug, and in-system verification of the DSP system. The suite of pre-optimized DSP IP cores can simplify this development process. You can also follow the DSP Builder design flow (Figure 1–2) and implement hardware-only DSP systems in FPGAs without learning HDL. f For information about the DSP Builder design flow, refer to Chapter 2, Introducing DSP Builder.

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Chapter 1: Introducing DSP Design DSP Design Flow in FPGAs

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2. Introducing DSP Builder

DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. DSP Builder integrates the algorithm development, simulation, and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with the Altera Quartus II software and third-party synthesis and simulation tools. You can combine Simulink blocks with DSP Builder blocks and IP blocks to verify system level specifications and perform simulation (Figure 2–1). DSP Builder supports all Altera DSP IP cores.
Figure 2–1. DSP Builder Design Flow
Design in MATLAB or Simulink

MATLAB/ Simulink

DSP Builder

IP

Convert to FPGA Design

VHDL or Verilog HDL and Tcl Files to run Synthesis

Simulation testbenches and Tcl files to run ModelSim

DSP block

System Verification and Construction

Quartus II synthesis and fitting

ModelSim

SOPC Builder

Standard and Advanced Blocksets
When you install DSP Builder two separate blocksets (standard and advanced ) are added to the Simulink library browser, which you can can use separately or together. The DSP Builder standard blockset includes libraries of design building and interface blocks and a library of blocks that represent each of the DSP MegaCore functions. The standard blockset has the following features:
■ ■ ■ ■ ■ ■

Cycle-accurate behavioral models Multiple clock domain management Control rich with backpressure support Access to specific hardware device features Hardware-in-the-loop (HIL) support enables FPGA hardware cosimulation Support for importing VHDL or Verilog HDL design entities

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Chapter 2: Introducing DSP Builder Standard and Advanced Blocksets

■ ■ ■ ■

Tabular and graphical state machine support Rapid prototyping using Altera DSP development boards SignalTap® II logic analyzer debugging support Direct instantiation of DSP IP cores

The DSP Builder advanced blockset does not interface directly with the DSP IP cores but instead includes its own timing-driven IP blocks that can generate high performance FIR, CIC, NCO, and FFT models. The advanced blockset has the following features:
■ ■ ■ ■ ■ ■ ■ ■ ■ ■

Specification driven design with automatic pipelining and folding High level synthesis technology High performance timing-driven IP models Multichannel designs with automatically vectorized inputs Automatic generation of memory-mapped interfaces Simulink fixed-point types Single system clock for the main datapath logic Feed-forward datapath with minimum control Portability across different device families High-level resource trade-offs such as hard versus soft multipliers

You can use both blocksets in subsystems of the same design when you want to combine features from each blockset. For example, when you want to combine an IP model from the advanced blockset with development board support or hardware-in-loop (HIL) from the standard blockset.

Standard Blockset
You can use blocks from the standard blockset to create a hardware implementation of a system modeled in Simulink in sampled time. DSP Builder contains bit- and cycle-accurate Simulink blocks—which cover basic operations such as arithmetic or storage functions—and takes advantage of key device features such as built-in PLLs, DSP blocks, and embedded memory. You can integrate complex functions by including IP cores in your DSP Builder model. You can also use the faster performance and richer instrumentation of hardware cosimulation by implementing parts of your design in an FPGA. The standard blockset supports imported HDL subsystems including HDL defined in a Quartus II project file. f For more information about the standard blockset, refer to Volume 2: DSP Builder Standard Blockset in the DSP Builder Handbook.

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Advanced Blockset
The DSP Builder advanced blockset consists of a number of Simulink libraries that allow you to implement DSP designs quickly and easily. The blockset is based on a high-level synthesis technology that optimizes the untimed netlist into low-level, pipelined hardware for the target FPGA device and clock rate. DSP Builder implements the hardware as VHDL with scripts that integrate with the Quartus II software and the ModelSim simulator. The combination of these features allows you to create a design without intimate device knowledge, which can run on a variety of FPGA families with different hardware architectures. After specifying the desired clock frequency, number of channels, and other top-level design constraints, the generated RTL is automatically pipelined to achieve timing closure. By analyzing the system-level constraints, DSP Builder also optimizes folding (time-division multiplexed (TDM) designs) to achieve optimum logic utilization, with no need for manual RTL editing. The synthesis technology also allows you to easily increase or decrease the number of channels. For example, in your FIR filter or digital up conversion signal chain, you can use a parameter file within the Simulink design. DSP Builder then adds the required TDM control logic and generates the updated RTL. The advanced blockset includes a library of basic control blocks and two component libraries—ModelIP and ModelPrim. These are useful in the following circumstances:

The ModelIP library consists of a set of multichannel, multirate cycle- accurate filters, mixers, and a numerically controlled oscillator (NCO) that allow you to quickly create designs for digital front end applications. Altera provides several implementation examples including up and down converters. The ModelPrim library allows you to create fast efficient designs captured in the behavioral domain rather than the implementation domain by combining zero latency primitive blocks. For example, you can use a delay block and DSP Builder decides how to implement that delay.

The advanced blockset is particularly suited for streaming algorithms characterized by continuous data streams and occasional control. For example, RF card designs that comprise long filter chains. f For more information about the advanced blockset, refer to Volume 3: DSP Builder Advanced Blockset in the DSP Builder Handbook.

Tool Integration
The DSP Builder standard and advanced blocksets are designed to operate with the Simulink, ModelSim software, Quartus II software, and Qsys.

Simulink
DSP Builder is interoperable with other Simulink blocksets. In particular, use the basic Simulink blockset to create interactive testbenches.

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The DSP Builder standard blockset uses signed integer, unsigned integer or signed fractional signal types and can be connected to other Simulink blocks using type casting Input and Output blocks. f For information about the internal signal types used by the standard blockset, refer to Volume 2: DSP Builder Standard Blockset in the DSP Builder Handbook. The VHDL model for standard blockset subsystems is generated when you compare the Simulink simulation results with the ModelSim simulator when you use the TestBench block. f For information about Simulink fixed point types, the signal processing blockset and the communications blockset, refer to the MATLAB Help. A VHDL model generates for subsystems with the advanced blockset when you run a Simulink simulation. There are many examples of using Simulink blocks in the tutorial and design examples. In particular, use Simulink scopes in the advanced blockset example to identify signals to add to the ModelSim Wave window for display as a digital or analog signal. f For information about the tutorials and design examples, refer to Design Examples in DSP Builder Standard Blockset Libraires section in volume 2 of the DSP Builder Handbook and the DSP Builder Advanced Blockset Libraires section in volume 3 of the DSP Builder Handbook.

ModelSim
You can run the ModelSim simulator from within a DSP Builder standard or advanced blockset design, if the ModelSim executable (vsim.exe) is in your path. Use the TestBench block to integrate between the DSP Builder standard blockset and the ModelSim simulator. When you click Compile against HDL, a VHDL testbench generates and a tb_<model name>.tcl script generates that you can use to load the testbench into the ModelSim simulator. You can optionally load the ModelSim GUI for interactive simulation. f For more information, refer to the description of the TestBench block in the DSP Builder Standard Blockset Libraires section in volume 2 of the DSP Builder Handbook.

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You can use any of the following generated scripts to integrate between the DSP Builder advanced blockset and the ModelSim simulator:

Control.do. This script, named after the control block (normally Control) compiles the entire design with RTL equivalents of the testbench structures, adds all relevant signals to the Wave window, and runs for the same period as the Simulink simulation. The script relies on some subordinate scripts that recursively compile library files, all the RTL files in the project, and adds the signals to the Wave window, before the simulation is started. Use these easy-to-follow scripts when building custom flows. To automatically load the design in the ModelSim simulator, click on the Run Modelsim block in the top-level model. f Only a subset of the Simulink blocks are translated into RTL that you can use for simulation in the ModelSim simulator. For a list of compatible blocks, refer to the Run ModelSim block descriptionin the DSP Builder Advanced Blockset Libraires section in volume 3 of the DSP Builder Handbook.

<block name>_atb.do. This script runs the automatic testbench flow for a block. It relies on reading some stimulus files at run time to verify a hardware block. The automatic testbench flow runs a rigorous test and returns a result whether or not the outputs match.

f

For more information, refer to the Comparison with RTL section in the DSP Builder Advanced Blockset Libraires section in volume 3 of the DSP Builder Handbook.

Quartus II Software
The standard blockset is tightly integrated with the Quartus II software using the Signal Compiler block. You can choose the device family and device, synthesize your design, run the Quartus II Fitter, and program your selected device. You can also enable the SignalTap II logic analyzer or export synthesizable model of your design. The advanced blockset allows you to build high-speed, high-performance DSP datapaths. In most production designs there is an RTL layer surrounding this datapath to perform interfacing to processors, high speed I/O, memories, and so on. To complete the design, use the DSP Builder standard blockset, Qsys, or RTL to assign board level components. The Quartus II software can then complete the synthesis and place and route process. You can automatically load a design into the Quartus II software by clicking on the Run Quartus II block in the top-level model.

Qsys
The DSP Builder standard blockset includes a library of Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interface blocks. A Tcl script <model name>_add.tcl is created by Signal Compiler, which can add your design to a Quartus II project. Any design that includes the Avalon interface blocks is automatically available for connection to other Avalon components in Qsys.

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DSP Builder Handbook Volume 1: Introduction to DSP Builder

DSP Builder creates a memory-mapped interface and class. refer to the Using the Interface Library chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.ptf file to the Qsys IP search path. DSP Builder Handbook Volume 1: Introduction to DSP Builder Preliminary © December 2010 Altera Corporation . A DSP Builder advanced blockset subsystem is available from the System Contents tab in Qsys after you add the path to the class.ptf file for each advanced blockset design. f For an example of the advanced blockset integration with Qsys.2–6 Chapter 2: Introducing DSP Builder Tool Integration f For an example of the standard blockset integration with Qsys. This file can expose the processor bus for connection in Qsys. refer to the DSP Builder Advanced Blockset User Guide section in volume 3 of the DSP Builder Handbook.

(3) The DSP Builder advanced blockset uses Simulink fixed-point types for all operations and requires licensed versions of Simulink Fixed Point.3. 2. (2).1 R2009a R2009b R2010a 10. You should use the same version of the Quartus II software and DSP Builder. Table 3–1. you can download DSP Builder from Altera’s web site at www. skip to “DSP Builder Directory Structure” on page 3–6. Point your web browser to www.0 R2008a R2008b R2009a 9. 1 Software Version 10. reinstall MATLAB with the READ ONLY option unchecked. Installing DSP Builder This chapter describes how to install DSP Builder. Altera also recommends the Simulink Signal Processing Blockset and Communications blocksets.altera. Downloading DSP Builder If you have Internet access. (2) DSP Builder does not work with MATLAB in read-only mode. To download DSP Builder from the Internet.com/support/software/download. follow these steps: 1. The following instructions describe downloading and installing DSP Builder.altera. If your PC issues error messages while creating board components during the DSP Builder installation. Fill out the registration form and click Submit Request. If you install DSP Builder from the DVD. ensure both tools are available on your workstation before you install DSP Builder. System Requirements As DSP Builder integrates with the The MathWorks MATLAB and Simulink tools and with the Altera Quartus® II software. which the design examples use. Table 3–1 lists the tool dependencies for DSP Builder.com. f For system requirements and installation instructions. 3. DSP Builder Tool Dependencies Tool DSP Builder The MathWorks (MATLAB and Simulink) (1). © December 2010 Altera Corporation DSP Builder Handbook Volume 1: Introduction to DSP Builder . (3) Notes to Table 3–1: (1) DSP Builder only supports 32-bit versions of The MathWorks release.1 R2008a R2008b R2009a Obtaining and Installing DSP Builder You can install DSP Builder from the Altera Complete Design Suite DVD or download from the Altera web site. refer to Altera Software Installation and Licensing. Click on DSP Builder and then the link to Download DSP Builder.

you must have an existing MATLAB or Simulink installation. 6.m files in the MATLAB installation directory. Click Run (Windows Start menu). The DSP Builder <version> . You can also choose whether to install the standard. you can setup DSP Builder to use a shared MATLAB installation using local configuration information in the matlab subdirectory below your home directory. the installer updates the pathdef. Follow the instructions on the download and installation page to download the executable and save it to your hard disk. In this case.m and classpath. 4. Close the following software. Installing DSP Builder on Linux To install DSP Builder on Linux. If you have write access privileges to this installation. where <path> is the location of the downloaded file. You are prompted for the locations of the Quartus II and MATLAB software you want to use with DSP Builder.3–2 Chapter 3: Installing DSP Builder Obtaining and Installing DSP Builder 4. which you can ignore and all components initialize correctly. use the following command to untar the file: tar xvf 90_dsp_builder_linux. To install DSP Builder on a computer running a supported version of the Linux operating system. 3. Installing DSP Builder on Windows To install DSP Builder on a computer running a supported version of the Windows operating system. 5.InstallShield Wizard dialog box appears. if it is running on your computer: ■ ■ ■ The Quartus II software The MATLAB and Simulink tools The ModelSim simulator 2. Turn on I have read the license agreement and click Proceed to Final Step. Click OK. If you download the Linux version of DSP Builder. If you do not have write access privileges to the MATLAB or Simulink installation. contact your local Altera representative to obtain the Altera Complete Design Suite DVD. 5.tar 1 If you do not have Internet access. Type <path>\DSPBuilder-<version>. or both blocksets. follow these steps: 1. you can setup DSP Builder for all users of MATLAB. Read the Altera license agreement. advanced. 1 MATLAB is runs in a minimized window during the installation. Follow the online instructions to install a new version. The transcript may include a number of entity creation error messages.exe. follow these steps: DSP Builder Handbook Volume 1: Introduction to DSP Builder Preliminary © December 2010 Altera Corporation .

m script in $HOME/matlab. 3. You can perform this operation manually by copying the archive file into the directory above the Quartus II installation directory and running the following command: gtar -xzf dsp_builder.Chapter 3: Installing DSP Builder Obtaining and Installing DSP Builder 3–3 1. set the following paths for the advanced blockset: <installation directory>/dspba/Blocksets <installation directory>/dspba/Blocksets/BaseBlocks <installation directory>/dspba/Blocksets/FFTBlocks <installation directory>/dspba/Blocksets/Filters © December 2010 Altera Corporation DSP Builder Handbook Volume 1: Introduction to DSP Builder .tgz 1 Altera provides the gtar and gzip executables with the archive file in case there are compatibility issues with the default executables. This script automatically sets the MATLAB path and classpath when you start MATLAB. The standard and advanced blocksets install by default when you use the Linux installation script. where <path> is the location of the downloaded files. 1 The MATLAB path. However. 1 2. You can also use the --auto option to install both blocksets using default locations without prompting for the location of the Quartus II software. Setting the MATLAB Path If you use the --setup_matlab option. Type <path>/install --setup_matlab. The installer prompts you for the location of the Quartus II software you want to use with DSP Builder. Alternatively you can set the MATLAB path by clicking Set Path on the File menu in MATLAB and adding the following paths for the standard blockset: <installation directory>/dsp_builder/bin <installation directory>/dsp_builder/bin/matlab <installation directory>/dsp_builder/bin/mdllibrary Similarly. you can specify the option --dspb_only to install only the standard blockset or --dspba_only to install only the advanced blockset. libraries and classpath are set up using scripts that write to your local matlab subdirectory. the installer creates a startup. Manual Configuration of the MATLAB Environment The installer unzips the dsp_builder. remove the existing dsp_builder and dspba directories before running the installation script. Close the following software.tgz archive into the specified Quartus II installation directory. Follow the on-line instructions. if it is running on your computer: ■ ■ ■ The Quartus II software The MATLAB and Simulink tools The ModelSim simulator If you have an existing version of DSP Builder.

glnx86) #------------------------------------------------------------------ If you add the required paths to LDPATH_SUFFIX. you can copy classpath. If it is not set correctly. The matlab7rc.matlab7rc. Therefore set it either in a script that you use to start MATLAB or create a .sh in your home directory.3–4 Chapter 3: Installing DSP Builder Obtaining and Installing DSP Builder <installation directory>/dspba/Blocksets/ModelBus <installation directory>/dspba/Blocksets/ModelPrim <installation directory>/dspba/Blocksets/WaveformSynthesis <installation directory>/dspba/Docs/Help You can optionally add paths to each of the directories that contain example design models if you want to open them from your current working directory. Setting the Classpath The startup. Alternatively. changing it to include <installation directory>/dsp_builder/bin/dspb_sblocks. 1 You can check the classpath by running javaclasspath in MATLAB to confirm that the dspb_sblocks.sh file has sections for each operating system.jar..jar file.mexglx If you set LD_LIBRARY_PATH globally it may affect other programs. the following MATLAB error messages appear: Invalid MEX-file . the relevant section is marked: #-----------------------------------------------------------------.m file that the installer creates also updates the static classpath to include the dspb_sblocks. and then invoking MATLAB from this local directory. Setting LD_LIBRARY_PATH Set the LD_LIBRARY_PATH environment variable for the C++ shared libraries to work properly. MATLAB adds them to the end of the LD_LIBRARY_PATH variable when it starts up. . 1 You can check that the library path has been set correctly by using the following command in MATLAB: getenv('LD_LIBRARY_PATH') DSP Builder Handbook Volume 1: Introduction to DSP Builder Preliminary © December 2010 Altera Corporation .. You must have the following paths: ■ ■ ■ <installation directory>/linux for the Quartus II software <installation directory>/dsp_builder/bin for the DSP Builder standard blockset <installation directory>/dspba/Blocksets/BaseBlocks/post2008a for the DSP Builder advanced blockset.txt from /toolbox/local/ in the MATLAB installation into a local directory.. For 32-bit Linux.jar file is on the static classpath.

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DSP Builder Directory Structure
Figure 3–1 shows the DSP Builder directory structure, where <path> is the installation directory that contains the Quartus II software. The default installation directory is c:\altera\<version>\quartus on Windows or /opt/altera<version>/quartus on Linux.
Figure 3–1. DSP Builder Directory Structure
<path> Installation directory containg the Quartus II software. dsp_builder Contains the DSP Builder standard blockset. bin Contains binary files, m-scripts and the Simulink Library for the standard blockset. DesignExamples Contains a wide variety of design examples that use the standard blockset. docs Contains the on-line help files for each standard block that displays in the MATLAB Help window. func_sim Contains files for fast functional simulation. legacy Contains files required for upgrading legacy designs. lib Contains library files. dspba Contains the DSP Builder advanced blockset. Blocksets Contains binary files, m-scripts and the Simulink Library for the advanced blockset. Docs Contains the on-line help files for each advanced block that displays in the MATLAB Help window. Examples Contains a wide variety of design examples that use the advanced blockset.

After installing DSP Builder, the Altera DSP Builder standard blockset and the Altera DSP Builder advanced blockset libraries, which you specified, are available in the Simulink library browser in the MATLAB software.

Using Previous Versions of DSP Builder
The DSP Builder installer searches for an existing installation of DSP Builder before it installs a new version. If it finds an existing installation, the installer prompts you to update the existing installation or install a new copy of the product. If you choose to update an existing product, you can modify, repair, or remove the old version. 1 Do not use the current installer to modify or repair a previous version of DSP Builder.

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Chapter 3: Installing DSP Builder MATLAB Procedures

Previous Versions
A previous version of DSP Builder cannot coexist with a current version in the same version of MATLAB. However, you can register each version of DSP Builder with different versions of MATLAB. Refer to “Using Multiple Versions of MATLAB” on page 3–7. 1 Use DSP Builder with a matching version of the Quartus II software.

DSP Builder Start Up Dependencies
DSP Builder uses the Quartus II libraries to share functionality that exists in the Quartus II software, which places explicit dependencies on the Quartus II versions. DSP Builder is Simulink dependent. After installing DSP Builder, you need to register it inside MATLAB to enable the DSP Builder features. You can then create DSP designs using DSP Builder blocks and run Simulink simulations without any requirements on the Quartus II software. However, when you want to generate VHDL for the DSP design and to fit the design into an FPGA, DSP Builder requires the Quartus II synthesis, and Fitter tools. You can only start the DSP Builder Signal Compiler tool with a matching version of the Quartus II software—it explicitly requires the correct version libraries and dynamic link library (.dll) files in the Quartus II software installation. The Signal Compiler dialog box does not display without a matching version of the Quartus II software.

MATLAB Procedures
Table 3–1 on page 3–1 shows the which versions of MATLAB you can use with DSP Builder .

Directory Path Names in MATLAB Scripts
Commands run from within an m-script cannot resolve a uniform naming convention (UNC) path to a remote file system. An error message appears when you attempt to run a MATLAB script that uses a UNC path. This error affects the HDL import, functional simulation, hardware-in-the-loop (HIL), and the State Machine Table block. Avoid this issue by mapping the network UNC path to a local drive.

Using Multiple Versions of MATLAB
You specify the MATLAB version that you want to use with DSP Builder during DSP Builder installation. If you have more than one MATLAB version (for example, release R2007b and R2008a) you can register DSP Builder with another version using the following procedure:

Standard Blockset
1. Open a command prompt and change directory to the standard blockset installation:

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cd <DSP Builder Installation Path>dsp_builder

2. Run the following command to register the DSP Builder blocksets with the required MATLAB version:
setupMatlabClassPath install <MATLAB Installation Path> <DSP Builder Installation Path>\dsp_builder

1

You must use quotation marks around the DSP Builder or MATLAB installation path, if the paths include spaces.

Advanced Blockset
1. Open MATLAB and change directory to the advanced blockset installation:
cd <DSP Builder Installation Path>dspba

2. Run the following command in the MATLAB command window to register the DSP Builder advanced blockset with the current MATLAB version:
alt_adv_dspb_install

Using 32-bit MATLAB on 64-bit Machines
DSP Builder currently only supports 32-bit versions of MATLAB. However, if you have 64-bit MATLAB on a 64-bit Linux machine, you can run MATLAB with the -glnx86 option to run in 32-bit mode compatible with DSP Builder. On a 64-bit Widows machine, you must install the 32-bit version of MATLAB to run DSP Builder. You can check the MATLAB version by running the MATLAB mexext utility. Table 3–2 shows the return values.
Table 3–2. Return Values for the MATLAB mexext Utility MATLAB Version 32-bit Linux 64-bit Linux 32-bit Windows 64-bit Windows Return Value mexglx mexa64 mexw32 mexw64

Licensing DSP Builder
Before using DSP Builder, you must request a license file from the Altera website at www.altera.com/licensing and install it on your computer. When you request a license file, Altera e-mails you a license.dat file that enables HDL file and Tcl script generation. If you do not have a DSP Builder license file, you can create models with DSP Builder blocks but you cannot generate HDL files or Tcl scripts. 1 Before you set up licensing for DSP Builder, you must already have the Quartus II software installed on your computer with licensing set up. To install your license, you can either append the license to your existing license.dat file or you can specify an additional license file location.

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Chapter 3: Installing DSP Builder Licensing DSP Builder

Appending the License to Your license.dat File
To install your license, perform the following steps: 1. Close the following software if it is running on your computer:
■ ■ ■ ■ ■ ■

The Quartus II software The LeonardoSpectrum software The Synplify software The MATLAB and Simulink tools The ModelSim simulator The Precision RTL synthesis software

2. Open the DSP Builder license file in a text editor. The file contains one FEATURE line, spanning two lines. 3. Open your Quartus II license.dat file in a text editor. 4. Copy the FEATURE line from the DSP Builder license file and paste it into the Quartus II license file. 1 Do not delete any FEATURE lines from the Quartus II license file.

5. Save the Quartus II license file. 1 When using editors such as Microsoft Word or Notepad, ensure that the file does not have any extra extensions appended to it after you save (for example, license.dat.txt or license.dat.doc). Verify the file name at the system command prompt.

Specifying the License File Location
DSP Builder always looks for a license in the LM_LICENSE_FILE environment variable, you can modify this variable to specify an additional location for the DSP Builder license file. To ensure the Quartus II software uses the LM_LICENSE_FILE variable follow these steps: 1. On the Tools menu click License Setup. The License Setup dialog box appears. 2. Turn on Use LM_LICENSE_FILE.

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4. Updating From Earlier Versions

Updating Models From the Previous Version
To update your designs from the previous version, open them with the latest version and save the model files. This procedure does not automatically update any MegaCore function blocks in your design but the previous versions are compatible if the previous version of the MegaCore IP library is still installed on your system. 1 If you have a pre-v7.1 design, update to v7.2 before you update the v7.2 design to v8.x or v9.0 or later.

Limitations of the Update Model Utility
The blocks in your model are updated to use the corresponding block in the new blockset. However some blocks may be obsolete or require manual intervention to complete the conversion process. Table 4–1 lists some of the issues that may require attention.
Table 4–1. Model Update Issues (Part 1 of 2) Issue PLL output clocks cannot be named Action In previous versions of DSP Builder, it was possible to have a PLL block and multiple ClockAltr blocks which represented PLL outputs. The PLL output clocks took the names of the clock blocks. This feature is no longer supported and cannot be automatically fixed. The PLL output clocks are now named <PLL name>_clk<output index>. All source blocks and rate change blocks referencing clock pins must be manually edited to reference these PLL clock output pins. In pre-7.1 versions, the multiply and divide values may have non-integer values and may be specified using MATLAB variables. You must now specify the clock period ratio directly as an integer period multiplier and an integer period divider. MATLAB variables cannot be used. Occasionally, the PLL parameters are updated incorrectly. Open the PLL parameter dialog and enter the correct values for the period multipliers and dividers. The extra Clock and Clock_Derived blocks should be removed, and any blocks referencing them manually corrected to reference the PLL-driven clocks. Note that the numbering of these clock pins does not in general match the numbering of the PLL clocks. Typically, you may want to create a new Clock block replicating this information, as the base clock pin generated by the update script is unlikely to be the correct driving clock domain. For example, if the PLL specified an input clock frequency of 50 MHz, add a Clock block and configure it to a clock period of 20ns and sample time 20e-9. In pre-7.1 versions, the ClockAltr blocks supported a rate change option (addition clock divider), which can generate a slower clock signal. This feature is no longer supported. If you want to generate different frequency clocks internally, you must add a PLL block driven from the required input clock.

PLL period multiply and divide values must be integers The PLL output clock period is incorrect after update When upgrading a design with a PLL, extra clock blocks are created for each distinct sample time The PLL input clock frequency information is lost during the update process Clock blocks do not support rate change divider

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Chapter 4: Updating From Earlier Versions Limitations of the Update Model Utility

Table 4–1. Model Update Issues (Part 2 of 2) Issue Error assigning clock for Dual-Clock FIFO block Error assigning PLL clock for Multi-Rate DFF block Unnecessary clock specification for source blocks Action Under some circumstances - noted by the message “No clock specified for {write/read} port, ...” you may have to manually select clocks after upgrading designs containing the Dual-Clock FIFO block. When upgrading a multirate DFF block connected to a PLL clock, an error is issued of the form: “Cannot update clock in block foo/Multi-Rate DFF. Original clock source: PLL CLOCK0.” The blocks must be manually corrected to reference the PLL clock. In general, source blocks do not need to specify a clock domain, if it can be inferred from the blocks they are driving. However, the update path always specifies a clock if it is not the base clock. Your multi-clock design may be easier to maintain if, after upgrading, you manually turn off Specify Clock for source blocks – especially constant, VCC and GND blocks – wherever possible. These errors can usually be fixed by turning off Specify Clock on the constant block. If the block is fed into several clock domains, you also need to add a Tsamp block before each one.

Errors issued if a constant, GND or VCC block is driving a block with a different sample time

The BP block does not A warning is issued if your design includes a bus probe (BP) block which was set to display support sample time mode the sample time because this option is no longer supported. Phase selection has been standardized across all blocks The Multi Channel Display and Extract blocks are not supported HIL designs must be recompiled Changes to rounding method used for the MATLAB arrays initialize the LUT and RAM blocks Results in behavioral change when upgrading blocks that use phase selection.

These blocks are no longer supported and should be removed before running the update script. You can use the Avalon-ST Packet Format Converter block directly in place of these blocks. To prevent HDL being generated, insert Output blocks followed by Non-synthesizable Input blocks on the inputs to the Avalon-ST packet format converter block. For designs with Hardware in the Loop, you must recreate the Quartus II project and recompile the HIL revision after upgrading. The rounding method used when the data values specified by an initializing MATLAB array are not exactly expressed if the data type changes. For example, if you specify the data type as Unsigned Integer and the value as 1.9 in a pre-v7.1 design, this value was rounded up to 2; it is now rounded down to 1. You should the check the outputs from LUT or RAM blocks if an error is issued stating that the values cannot be exactly represented in the selected data format and choose revised initialization values that can be represented exactly if the outputs are not as expected. Altbus blocks used as black box inputs or outputs must be manually changed to HDL Input and HDL Output blocks and a HDL Entity block added to specify the HDL file and clock/reset ports. Rename any block containing a ‘/’ character in its name.

Black box subsystem are not updated An error is issued for any block name which has a ‘/’ character AltBus blocks within subsystems which function as input pins not updated correctly Device Programmer block is not supported The External RAM block is not updated

Move the input pins to the top level or replace them by Input blocks. (It is better to replace these AltBus blocks before upgrading to ensure that the clock signals are set correctly.)

Remove the Device Programmer block before running the update program. Use Signal Compiler or a HIL block to program the DSP development board. This block is outside the DSP Builder system and is not automatically updated. You must manually replace any pre-7.1 External RAM blocks in your designs with the latest version.

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Chapter 4: Updating From Earlier Versions Updating the IP Cores in your Design

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Using a Simulink Library Forwarding Table
You can use a Simulink library forwarding table to update models with changes in the names or locations of the library blocks that they reference. Using this feature, all of the links in the updated version of the old file can be quickly and easily changed to point to a different library. f For more information, refer to Making Backward-Compatible Changes to Libraries in the MATLAB Simulink help.

Updating the IP Cores in your Design
After you have updated designs containing IP cores, regenerate the IP blocks to ensure they are up-to-date. Either individually double-click on each block, (changing the parameters, if required) and click the Generate option, or enter the following command at the MATLAB prompt:
alt_dspbuilder_refresh_megacore

This command automatically regenerates all the IP cores in the updated design, using the existing parameterizations.

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Chapter 4: Updating From Earlier Versions Updating the IP Cores in your Design

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Additional Information

Revision History
The following table shows the revision history for this document.
Date December 2010 July 2010 Version 10.1 10.0 Updated MATLAB version support. First release. Changes Made

How to Contact Altera
For the most up-to-date information about Altera® products, see the following table.
Contact Method Website Website Email Altera literature services Non-technical support (General) (Software Licensing)
Note:
(1) You can also contact your local Altera sales office or sales representative.

Contact (Note 1) Technical support Technical training

Address www.altera.com/support www.altera.com/training custrain@altera.com literature@altera.com nacomp@altera.com authorization@altera.com

Email Email Email

Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue Bold Type with Initial Capital Letters bold type Meaning Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example, Save As dialog box. For GUI elements, capitalization matches the GUI. Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, <file name> and <project name>.pof file. Initial Capital Letters Indicates keyboard keys and menu names. For example, Delete key and the Options menu.

Italic Type with Initial Capital Letters Italic type

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Additional Information Typographic Conventions

Visual Cue “Subheading Title”
Courier type

Meaning Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, “Typographic Conventions.” Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).

1., 2., 3., and a., b., c., and so on.
■ ■

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. The hand points to information that requires special attention. A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic.

1 c w r f

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DSP Builder Handbook Volume 2: DSP Builder Standard Blockset

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Document Version: Document Date:

1.0 June 2010

Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Contents

Section Revision Dates

Section I. DSP Builder Standard Blockset User Guide
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Chapter 1. About DSP Builder
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Memory Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 High-Speed DSP with Programmable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Interoperability with the Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3

Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Creating the Amplitude Modulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Create a New Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Add the Sine Wave Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Add the SinIn Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Add the Delay Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Add the SinDelay and SinIn2 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Add the Mux Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Add the Random Bitstream Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Add the Noise Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 Add the Bus Builder Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 Add the GND Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 Add the Product Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11 Add the StreamMod and StreamBit Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12 Add the Scope Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Add a Clock Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Simulating the Model in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Performing RTL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Adding the Design to a Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20 Creating a Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20 Add the DSP Builder Design to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Chapter 3. Design Rules and Procedures
DSP Builder Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Using a MATLAB Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Fixed-Point Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Binary Point Location in Signed Binary Fractional Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

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Bit Width Design Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Data Width Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Tapped Delay Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5 Arithmetic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Frequency Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Single Clock Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Multiple Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Using Clock and Clock_Derived Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 Clock Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 Using the PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14 Using Advanced PLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 Timing Semantics Between Simulink and HDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 Simulink Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 HDL Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 Startup & Initial Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17 DSP Builder Global Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17 Reference Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18 Signal Compiler and TestBench Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19 Design Flows for Synthesis, Compilation and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19 Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20 Goto and From Block Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21 Create Black Box and HDL Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22 Using a MATLAB Array or .hex File to Initialize a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22 Comparison Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22 Adding Comments to Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22 Adding Quartus II Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23 Displaying Port Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24 Displaying the Pipeline Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24 Updating HDL Import Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24 Analyzing the Hardware Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25 Loading Additional ModelSim Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27 Making Quartus II Assignments to Block Entity Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–27

Chapter 4. Using MegaCore Functions
Installing MegaCore Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Updating MegaCore Function Variation Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Design Flow Using MegaCore Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Adding the MegaCore Function in the Simulink Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Parameterizing the MegaCore Function Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Generating the MegaCore Function Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Connecting the MegaCore Function Variation Block to the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Simulating the MegaCore Function Variation in the Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 MegaCore Function Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Creating a New Simulink Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Adding the FIR Compiler Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Parameterizing the FIR Compiler Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Generating the FIR Compiler Function Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Adding Stimulus and Scope Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Simulating the Design in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Performing RTL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10

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MegaCore Functions Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 Simulink Files Associated with a MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 Simulating MegaCore Functions That Have a Reset Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 Setting the Device Family for MegaCore Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14

Chapter 5. Using HIL
HIL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 HIL Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 HIL Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 Burst and Frame Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 Using Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 Using Frame Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8 Troubleshooting HIL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 Fails to Load the Specified Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 No Inputs Found From the Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 No Outputs Found From the Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 HIL Design Stays in Reset During Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 HIL Compilation Appears to Hang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 Scan JTAG Fails to Find Correct Cable or Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10

Chapter 6. Performing SignalTap II Logic Analysis
SignalTap II Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 SignalTap II Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 SignalTap II Trigger Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 SignalTap II Example Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Opening the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3 Adding the Configuration and Connector Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3 Specifying the Nodes to Analyze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 Turning On the SignalTap II Option in Signal Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 Specifying the Trigger Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 Performing SignalTap II Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

Chapter 7. Using the Interfaces Library
Avalon-MM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Avalon-MM Interface Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 Avalon-MM Slave Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 Avalon-MM Master Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4 Wrapped Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5 Avalon-MM Write FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6 Avalon-MM Read FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7 Avalon-MM Interface Blocks Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Adding Avalon-MM Blocks to the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Verifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 Running Signal Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Instantiating the Design in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Compiling the Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Testing the DSP Builder Block from Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15 Avalon-MM FIFO Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Opening the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17 Instantiating the Design in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18

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Avalon-ST Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20 Avalon-ST Packet Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Avalon-ST Packet Format Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22

Chapter 8. Using Black Boxes for HDL Subsystems
Implicit Black Box Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 Explicit Black-Box Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 HDL Import Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 Importing Existing HDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 Simulating the HDL Import Model using Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4 Subsystem Builder Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6 Creating a Black Box System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6 Building the Black-Box SubSystem Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8 Simulating the Subsystem Builder Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–11 Adding VHDL Dependencies to the Quartus II Project and ModelSim . . . . . . . . . . . . . . . . . . . . . . 8–11 Simulate the Design in ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–12

Chapter 9. Using Custom Library Blocks
Creating a Custom Library Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1 Creating a Library Model File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 Building the HDL Subsystem Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 Defining Parameters Using the Mask Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 Linking the Mask Parameters to the Block Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 Making the Library Block Read Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 Adding the Library to the Simulink Library Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 Synchronizing a Custom Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6

Chapter 10. Adding a Board Library
Creating a New Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1 Predefined Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1 Component Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1 Component Description File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–2 Example Component Description File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3 Board Description File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4 Header Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4 Board Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–4 Building the Board Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–6

Chapter 11. Using the State Machine Library
Using the State Machine Table Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2 Using the State Machine Editor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–7 Integration with Source Control Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–1 HDL Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 MegaCore Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 Memory Initialization Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 Exporting HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 Using Exported HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Migration of DSP Builder (Standard Blockset) Files to a New Location . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Integration of Multiple Models in a Top-Level Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6

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Troubleshooting Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1 Signal Compiler Cannot Checkout a Valid License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–1 Verifying That Your DSP Builder Licensing Functions Properly . . . . . . . . . . . . . . . . . . . . . . . . . . 13–2 Verifying That the LM_LICENSE_FILE Variable Is Set Correctly . . . . . . . . . . . . . . . . . . . . . . . . . 13–3 Verifying the Quartus II Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3 If You Still Cannot Get a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 Loop Detected While Propagating Bit Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 The MegaCore Functions Library Does Not Appear in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 The Synthesis Flow Does Not Run Properly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 Check the Software Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 DSP Development Board Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 SignalTap II Analysis Appears to Hang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 Error if Output Block Connected to an Altera Synthesis Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 Warning if Input/Output Blocks Conflict with clock or aclr Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Wiring the Asynchronous Clear Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Error Issues when a Design Includes Pre-v7.1 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Creating an Input Terminator for Debugging a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 A Specified Path Cannot be Found or a File Name is Too Long . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 Incorrect Interpretation of Number Format in Output from MegaCore Functions . . . . . . . . . . . . . 13–7 Simulation Mismatch For FIR Compiler MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 Simulation Mismatch After Changing Signals or Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 Unexpected Exception Error when Generating Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 VHDL Entity Names Change if a Model is Modified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 Algebraic Loop Causes Simulation to Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 Parameter Entry Problems in the DSP Block Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 DSP Builder System Not Detected in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 MATLAB Runs Out of Java Virtual Machine Heap Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 ModelSim Fails to Invoke From DSP Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Unexpected End of File Error When Comparing Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 13–10

Section II. DSP Builder Standard Blockset Libraries
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Chapter 1. AltLab Library
BP (Bus Probe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Clock_Derived . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Display Pipeline Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 HDL Entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 HDL Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 HDL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7 HDL Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 HIL (Hardware in the Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Quartus II Global Project Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11 Quartus II Pinout Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11 Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12 Signal Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 SignalTap II Logic Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14 SignalTap II Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15 Subsystem Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15 TestBench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17

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VCD Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18

Chapter 2. Arithmetic Library
Barrel Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 Bit Level Sum of Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Increment Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19 Magnitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21 Multiply Accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23 Multiply Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25 Parallel Adder Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27 Pipelined Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29 Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31 SOP Tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33 Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35 Sum of Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

Chapter 3. Complex Type Library
Butterfly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Complex AddSub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Complex Conjugate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Complex Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Complex Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Complex Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 Complex Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 Complex to Real-Imag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13 Real-Imag to Complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14

Chapter 4. Gate & Control Library
Binary to Seven Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Bitwise Logical Bus Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Flipflop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 If Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 LFSR Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 Logical Bit Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16 Logical Bus Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Logical Reduce Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22 Single Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23

Chapter 5. Interfaces Library
Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3

DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary

© June 2010 Altera Corporation

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Avalon-MM Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 Avalon-MM Read FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9 Avalon-MM Write FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11 Avalon-ST Packet Format Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12 PFC Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15 Packet Format Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15 Packet Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17 Multi-Packet Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18 Avalon-ST Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18 Avalon-ST Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20

Chapter 6. IO & Bus Library
AltBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Binary Point Casting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 Bus Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 Bus Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7 Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Bus Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9 Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10 Extract Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12 Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14 Non-synthesizable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15 Non-synthesizable Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17 Round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18 Saturate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21

Chapter 7. Rate Change Library
Multi-Rate DFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Tsamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4

Chapter 8. Simulation Library
External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1 Multiple Port External RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3

Chapter 9. Storage Library
Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 Down Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 Dual-Clock FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7 FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 LUT (Look-Up Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–11 Memory Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13 Parallel To Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16 Serial To Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18 Shift Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20 Single-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21

© June 2010 Altera Corporation Preliminary

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True Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–24 Up Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28

Chapter 10. State Machine Functions Library
State Machine Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–1 State Machine Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–3 Design Rule Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–5

Chapter 11. Boards Library
Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1 PLL Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–1 ADC Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2 Cyclone II DE2 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–2 Cyclone II EP2C35 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–3 Cyclone II EP2C70 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–4 Cyclone III EP3C25 Starter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6 Cyclone III EP3C120 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–6 Setting Up the Mezzanine Card Test Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–9 Stratix EP1S25 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–11 Stratix EP1S80 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–13 Stratix II EP2S60 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–14 Stratix II EP2S180 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–15 Stratix II EP2S90GX PCI Express Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–17 Stratix III EP3SL150 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–18 Setting Up the Mezzanine Card Test Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11–20

Chapter 12. MegaCore Functions Library Chapter 13. Design Examples
Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3 HIL Frequency Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–3 Switch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 Avalon-MM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 Avalon-MM FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–4 HDL Import . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 Subsystem Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 Custom Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 State Machine Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 CIC Interpolation (3 Stages x75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 CIC Decimation (3 Stages x75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Convolution Interleaver Deinterleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 IIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 32 Tap Serial FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 MAC based 32 Tap FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 Color Space Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 Farrow Based Resampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–7 CORDIC, 20 bits Rotation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 Imaging Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 Quartus II Assignment Setting Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 SignalTap II Filtering Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 SignalTap II Filtering Lab with DAC to ADC Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Cyclone II DE2 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Cyclone II EP2C35 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9

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Cyclone II EP2C70 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Cyclone III EP3C25 Starter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Cyclone III EP3C120 DSP Board (LED/PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Cyclone III EP3C120 DSP Board (7-Seg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–10 Cyclone III EP3C120 DSP Board (HSMC A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–10 Cyclone III EP3C120 DSP Board (HSMC B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–10 Stratix EP1S25 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–10 Stratix EP1S80 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–10 Stratix II EP2S60 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11 Stratix II EP2S180 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11 Stratix II EP2S90GX PCI Express Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11 Stratix III EP3SL150 DSP Board (LED/PB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11 Stratix III EP3SL150 DSP Board (7-Seg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11 Stratix III EP3SL150 DSP Board (HSMC A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–11 Stratix III EP3SL150 DSP Board (HSMC B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–12 Combined Blockset Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–12

Chapter 14. Categorized Block List
AltLab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–1 Complex Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–2 Gate & Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–3 IO & Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–3 Rate Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 Simulation Blocks Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 State Machine Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–5

Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

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Section Revision Dates

The following table shows the revision dates for the sections in this volume.
Section DSP Builder Standard Blockset User Guide DSP Builder Standard Blockset Libraries Version 1.0 1.0 Date June 2010 June 2010 Part Number HB_DSPA_STD_UG-1.0 HB_DSPA_STD_LIB-1.0

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Section Revision Dates

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Section I. DSP Builder Standard Blockset User Guide

101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPA_STD_UG-1.0

Document Version: Document Date:

1.0 June 2010

Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Changes Made © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .0 First published.About This Section Revision History The following table shows the revision history for this section. Date June 2010 Version 1.

iv About This Section Revision History DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

In general. Stratix III. DSP Builder Release Information Item Version Release Date Ordering Code Description 10. Cyclone III. Supported Memory Block Types Memory Block Type M144K M9K MLAB Device Family Stratix IV. Arria II GX Stratix IV. Table 1–2 on page 1–1 shows the device families that support each memory block type. Arria II GX Stratix IV. DSP Builder lists all supported memory block types as options although some may not be available for all device families.0 June 2010 IPT-DSPBUILDER Device Family Support DSP Builder supports the following Altera® device families: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Arria™ GX Arria II GX Cyclone® Cyclone II Cyclone III. Stratix III. Stratix® Stratix GX Stratix II Stratix II GX Stratix III Stratix IV Memory Options A number of the blocks in the Storage library allow you to choose the required memory block type. Arria II GX © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Table 1–1.1. About DSP Builder Release Information Table 1–1 provides information about this release of DSP Builder. Stratix III. Table 1–2.

Stratix II. Stratix GX. Stratix II. Features DSP Builder standard blockset supports the following features: ■ Links The MathWorks MATLAB (Signal Processing ToolBox and Filter Design Toolbox) and Simulink software with the Altera® Quartus® II software. Supports hardware-in-the loop (HIL) to enable FPGA hardware accelerated cosimulation with Simulink. Supports tabular and graphical state machine editing. Enables rapid prototyping using Altera DSP development boards.1–2 Chapter 1: About DSP Builder Features Table 1–2. Cyclone II. Supports the SignalTap® II logic analyzer—an embedded signal analyzer that probes signals from the Altera device on the DSP board and imports the data into the MATLAB workspace to ease visual analysis. Stratix. Stratix GX. Supports Avalon® Memory-Mapped (Avalon-MM) interfaces including user configurable blocks. Arria GX f For more information about each memory block type. Stratix II. Allows HDL import of VHDL or Verilog HDL design entities and HDL defined in a Quartus II project file. Stratix. Generates VHDL testbench and controls Quartus II compilation. Allows you to instance Altera DSP MegaCore® functions in a DSP Builder design model. Supported Memory Block Types Memory Block Type M-RAM M4K M512 Device Family Stratix II GX. Stratix. Arria GX. Stratix GX. Provides a variety of fixed-point arithmetic and logical operators for use with the Simulink software. which you can use to build custom logic that works with the Nios® II processor and other SOPC Builder designs. Arria GX Stratix II GX. refer to the DSP Builder Release Notes and Errata. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ f For information about new features and errata in this release. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Cyclone Stratix II GX. Supports Avalon Streaming (Avalon-ST) interfaces including an Packet Format Converter block and configurable Avalon-ST sink and Avalon-ST source blocks. refer to the Quartus II Help.

For more information about the differences between the standard and advanced blocksets and about design flows that combine both blocksets. High-Speed DSP with Programmable Logic Programmable logic offers compelling performance advantages over dedicated DSP processors. they give many times better performance than standard DSP processors by executing hundreds of instructions at the same time. Interoperability with the Advanced Blockset DSP Builder includes an optional advanced blockset. and hardware designers to share a common development platform. f For more information about the advanced blockset. and simulation.Chapter 1: About DSP Builder General Description 1–3 General Description Digital signal processing (DSP) system design in Altera programmable logic devices (PLDs) requires both high-level algorithm and hardware description language (HDL) development tools. Think of programmable logic as an array of elements. and verification capabilities of The MathWorks MATLAB and Simulink system-level design tools with VHDL and Verilog HDL design flows. In this way. The DSP Builder Signal Compiler block reads Simulink Model Files (. Algorithms that benefit from this improved performance include forward-error correction (FEC). refer to Volume 1: Introduction to DSP Builder in the DSP Builder Handbook. When connected in parallel. Signal Compiler then generates the VHDL files and Tcl scripts for synthesis. The Altera DSP Builder integrates these tools by combining the algorithm development.mdl) that contain other DSP Builder blocks and MegaCore functions. refer to Volume 3: DSP Builder Advanced Blockset in the DSP Builder Handbook. each of which you can configure as a complex processor routine. hardware implementation. f © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . DSP Builder shortens DSP design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. simulation. or connect them in parallel. modulation and demodulation. including the Altera Quartus II software. algorithm. You can link these routines together in serial (the same way that a DSP processor executes them). DSP Builder allows system. You can combine existing MATLAB functions and Simulink blocks with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore functions to link system-level design and implementation with DSP algorithm development. and encryption.

1–4 Chapter 1: About DSP Builder General Description DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Design Flow When using DSP Builder. refer to the Quartus II help. output VHDL files for synthesis and Quartus II compilation. or generate files for VHDL simulation. DSP Builder generates VHDL and does not generate Verilog HDL. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .2. you can compile directly in the Quartus II software. f For information about this flow. However. Getting Started This chapter describes the design flow and a tutorial. after you have created a Quartus II project. After you have created your model. you can use the quartus_map command in the Quartus II software to run a simulation netlist flow that generates files for Verilog HDL simulation. you start by creating a Simulink design model in the MathWorks software.

System-Level Design Flow The design flow involves the following steps: 1. which must have a period greater than 1ps but less than 2. Figure 2–1. Use the MathWorks software to create a model with a combination of Simulink and DSP Builder blocks. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Include a Clock block from the DSP Builder AltLab library to specify the base clock for your design.1 ms. You can derive additional clocks from the base clock by adding Clock_Derived blocks. DSP Builder creates a default clock with a 20ns real-world period and a Simulink sample time of 1.2–2 Chapter 2: Getting Started Design Flow Figure 2–1 shows the system-level design flow using DSP Builder. 1 Separate The DSP Builder blocks in your design from the Simulink blocks by Input and Output blocks from the DSP Builder IO and Bus library. 2. 1 If no base clock exists in your design.

Alternatively. you can synthesize the VHDL files manually using other synthesis tools. Simulate your model in Simulink using a Scope block to monitor the results.Chapter 2: Getting Started Design Flow 2–3 3. Set a discrete (no continuous states) solver in Simulink. Figure 2–2. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Use the output files generated by the DSP Builder Signal Compiler block to perform RTL synthesis. the Testbench block generates a testbench and supporting files for VHDL simulation. 6. You can synthesize and simulate the output files in other software tools without the Tcl scripts. 4. In addition. refer to the description of the “Solver Pane” in the Simulink Help. For an automated design flow. Compile your design in the Quartus II software. Choose a Fixed-step solver type if you are using a single clock domain or a Variable-step type if you use multiple clock domains. 7. DSP Builder supports an automated flow for the ModelSim software (using the TestBench block). You can also use the generated VHDL for manual simulation in other simulation tools. 5. To set the solver options. The Tcl scripts let you perform synthesis and compilation automatically in the MATLAB and Simulink environment. 8. the Signal Compiler block generates VHDL and Tcl scripts for synthesis in the Quartus II software. click Configuration Parameters on the Simulation menu to open the Configuration Parameters dialog box and select the Solver page (Figure 2–2). Perform RTL simulation. 9. Run Signal Compiler to setup RTL simulation and synthesis. Configuration Parameters for Simulation f For detailed information about solver options. Download to a hardware development board and test.

This tutorial assumes the following points: ■ ■ You are using a PC running Windows XP. to demonstrate the DSP Builder design flow. and click Model to create a new model window. Start the MATLAB software. follow these steps: 1. f For information about using the Simulink software. f Creating the Amplitude Modulation Model This tutorial uses an amplitude modulation design example. To create the amplitude modulation model. and a delay element. singen. This tutorial uses the working directory <DSP Builder install path>\DesignExamples\Tutorials\GettingStartedSinMdl\my_SinMdl. In the new model window. 2. a dialog box displays where you can enter the parameters for the block. point to New. to save the file.mdl. refer to “Design Flows for Synthesis. and ModelSim® software and the software is installed on your PC in the default locations. 5. 6. your working directory. Compilation and Simulation” on page 3–19. You are familiar with the MATLAB. You have basic knowledge of the Simulink software. on the File menu click Save. Browse to a directory. ■ You can use the singen. For more information about the blocks in the DSP Builder blockset. follow these instructions. 3. Click the MATLAB Start button. 4. Click Save. Simulink. a quadrature multiplier.mdl model file in <DSP Builder install path>\DesignExamples\Tutorials\GettingStartedSinMdl or you can create your own amplitude modulation model. Click the Help button in these dialog boxes to view help for a specific block. Type the file name into the File name box. This tutorial uses the name singen. The amplitude modulation design example is a modulator that has a sine wave generator. Each block in the model is parameterizable. Create a New Model To create a new model. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .mdl. 7. refer to the Simulink Help. Point to Simulink and click Library Browser. Quartus II. When you double-click a block in the model. On the File menu.2–4 Chapter 2: Getting Started Creating the Amplitude Modulation Model f For information about controlling the DSP Builder design flow using Signal Compiler. refer to the DSP Builder Reference Manual.

16-Bit Sine Wave Specified in the Sine Wave Dialog Box 4. Drag and drop a Sine Wave block into your model. follow these steps: 1. Figure 2–3. In the Simulink Library Browser. 500-kHz. 2. Set the Sine Wave block parameters (Table 2–1). Parameters for the Sine Wave Block Parameter Sine type Time Amplitude Bias Samples per period Number of offset examples Sample time Interpret vector parameters a 1-D Value Sample based simulation time 2^15–1 0 80 0 25e-9 On © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Double-click the Sine Wave block in your model to display the Block Parameters dialog box (Figure 2–3).Chapter 2: Getting Started Creating the Amplitude Modulation Model 2–5 Add the Sine Wave Block To add the Sine Wave block. click Simulink and Sources to view the blocks in the Sources library. Table 2–1. 3.

Altera DSP Builder Folder in the Simulink Library Browser 2. 1 For information about how you can calculate the frequency.. follow these steps: 1. expand the Altera DSP Builder Blockset folder to display the DSP Builder libraries (Figure 2–4). refer to the equation in “Frequency Design Rules” on page 3–8. Figure 2–4. In the Simulink Library Browser. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Add the SinIn Block To add the SinIn block.2–6 Chapter 2: Getting Started Creating the Amplitude Modulation Model 5. Click OK. Select the IO & Bus library.

Delete the text Input and type the text SinIn to change the name of the block instance. Set the SinIn block parameters (Table 2–2). follow these steps: 1. Drag and drop the Input block from the Simulink Library Browser into your model. Parameters for the SinIn Block Parameter Bus Type [number of bits]. Down. 1 Alternatively. Double-click the Delay block in your model to display the Block Parameters dialog box (Figure 2–5). Drag and drop the Delay block into your model and position it to the right of the SinIn block. 6.Chapter 2: Getting Started Creating the Amplitude Modulation Model 2–7 3. 2. 8. hold down the Ctrl key and click the destination block to automatically make a connection between the two blocks. Right.[] Specify Clock Value Signed Integer 16 Off 7. Click the text under the block icon in your model. 1 You can use the Up. Table 2–2. Select the Storage library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. you can select a block. If you are unsure how to position the blocks or draw connection lines. Click OK. Draw a connection line from the right side of the Sine Wave block to the left side of the SinIn block by holding down the left mouse button and dragging the cursor between the blocks. Double-click the SinIn block in your model to display the Block Parameters dialog box. 4. Position the block to the right of the Sine Wave block. Add the Delay Block To add the Delay block. 4. 3. refer to the completed design (Figure 2–7 on page 2–14). Type 1 as the Number of Pipeline Stages for the Delay block. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 5. and Left arrow keys to adjust the position of a block.

Drag and drop two Output blocks into your model. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Table 2–3. 7. 4. positioning them to the right of the Delay block. Draw a connection line from the right side of the SinIn block to the left side of the Delay block. Click the Optional Ports tab and set the parameters (Table 2–3). Parameters for the Delay Block. 3. 5. follow these steps: 1. Parameter Clock Phase Selection Use Enable Port Use Synchronous Clear port Value 01 Off Off 6. Set the SinDelay block parameters (Table 2–4).2–8 Chapter 2: Getting Started Creating the Amplitude Modulation Model Figure 2–5. Click OK. Click the text under the block symbols in your model. Change the block instance names from Output and Output1 to SinDelay and SinIn2. Double-click the SinDelay block in your model to display the Block Parameters dialog box. Add the SinDelay and SinIn2 Blocks To add the SinDelay and SinIn2 blocks. Setting the Downsampling Delay 5. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Draw a connection line from the right side of the Delay block to the left side of the SinDelay block. 2. positioning it to the right of the SinDelay block. Parameters for the SinIn2 Block Parameter Bus Type [number of bits]. Set the Mux block parameters (Table 2–6). Table 2–5.[] External Type Value Signed Integer 16 Inferred 8. 3. Draw a connection line from the bottom left of the Mux block to the right side of the SinDelay block. 8. Parameters for the Mux Block Parameter Number of Inputs Display Options Value 2 bar 5. 7. Double-click the Mux block in your model to display the Block Parameters dialog box. Drag and drop a Mux block into your design. 7. 6. Draw a connection line from the top left of the Mux block to the line between the SinIn2 block. Add the Mux Block To add the Mux block. follow these steps: © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . follow these steps: 1. Draw a connection line from the SinIn2 block to the line between the SinIn and Delay blocks. Repeat steps 4 to 6 for the SinIn2 block setting the parameters (Table 2–5). Select the Simulink Signal Routing library in the Simulink Library Browser. Click OK.Chapter 2: Getting Started Creating the Amplitude Modulation Model 2–9 Table 2–4. Table 2–6. 4. Add the Random Bitstream Block To add the Random Bitstream block.[] External Type Value Signed Integer 16 Inferred 6. Click OK. Parameters for the SinDelay Block Parameter Bus Type [number of bits].

Click OK. 7. 6. Double-click the Random Number block in your model to display the Block Parameters dialog box. Select the Simulink Sources library in the Simulink Library Browser. Double-click the Noise block to display the Block Parameters dialog box. Drag and drop an Input block into your model. 4. Parameters for the Noise Block Parameter Bus Type Specify Clock Value Single Bit Off 1 The dialog box options change to display only the relevant options when you select a new bus type. positioning it to the right of the Random Bitstream block. Rename the block Noise. 3. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Click the text under the block icon in your model. Drag and drop a Random Number block into your model. Draw a connection line from the right side of the Random Bitstream block to the left side of the Noise block. 3. Set the Noise block parameters (Table 2–8). 5. Table 2–7. positioning it underneath the Sine Wave block. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. follow these steps: 1. Rename the Random Noise block Random Bitstream. Set the Random Number block parameters (Table 2–7). Table 2–8. 2. Parameters for the Random number Block Parameter Mean Variance Initial seed Sample time Interpret vector parameters as 1-D Value 0 1 0 25e–9 On 5. 6. Add the Noise Block To add the Noise block. Click OK. 2. 4.2–10 Chapter 2: Getting Started Creating the Amplitude Modulation Model 1.

Add the GND Block To add the GND block. 4. follow these steps: 1. Select the Arithmetic library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Click OK. Add the Product Block To add the Product block. To add the Bus Builder block. Set the Product block parameters (Table 2–10). Drag and drop a Bus Builder block into your model. Double-click the Product block to display the Block Parameters dialog box. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Draw a connection line from the right side of the GND block to the bottom left side of the Bus Builder block. Table 2–9. Drag and drop a Product block into your model. Drag and drop a GND block into your model. Set the Bus Builder block parameters (Table 2–9). follow these steps: 1. Leave enough space so that you can draw a connection line under the Product block. 3. 2. positioning it underneath the Noise block.[] Value Signer Integer 2 5. 3. follow these steps: 1. positioning it to the right of the Noise block. 6.Chapter 2: Getting Started Creating the Amplitude Modulation Model 2–11 Add the Bus Builder Block The Bus Builder block converts a bit to a signed bus. Parameters for the Bus Builder Block Parameter Bus Type [number of bits]. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 4. Draw a connection line from the right side of the Noise block to the top left side of the Bus Builder block. 2. positioning it to the right of the Bus Builder block and slightly above it. Double-click the Bus Builder block in your model to display the Block Parameters dialog box. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 3.

5. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. Parameters for the StreamMod Block Parameter Bus Type [number of bits]. Click OK. Add the StreamMod and StreamBit Blocks To add the StreamMod and StreamBit blocks. Click the text under the block symbols in your model. 3. Table 2–11. Click OK. Drag and drop two Output blocks into your model. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Double-click the StreamMod block to display the Block Parameters dialog box. follow these steps: 1. Draw a connection line from the top left of the Product block to the line between the Delay and SinDelay blocks. Change the block instance names from Output and Output1 to StreamMod and StreamBit. Parameters for the Product Block Parameter Bus Type Number of Pipeline Stages Value Inferred 0 1 The bit width parameters are set automatically when you select Inferred bus type. positioning them to the right of the Product block. Set the StreamMod block parameters (Table 2–11). 2.[] External Type Value Signed Integer 19 Inferred 6. 7. Double-click the StreamBit block to display the Block Parameters dialog box (Figure 2–6). The parameters in the Optional Ports and Settings tab of this dialog box can be left with their default values.2–12 Chapter 2: Getting Started Creating the Amplitude Modulation Model Table 2–10. 4. 6. 5.

Parameters for the StreamBit Block Parameter Bus Type External Type Value Single Bit Inferred 9. Double-click the Scope block and click the Parameters ‘Scope’ parameters dialog box. Parameters for the Scope Block Parameter Number of axes Time range Tick labels Sampling Value 3 auto bottom axis only Decimation 1 icon to display the © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Select the Simulink Sinks library in the Simulink Library Browser. Set the StreamBit block parameters (Table 2–12). Set a Single-Bit Output Bus 8. Table 2–12. and from the right side of the Bus Builder block to the left side of the StreamBit block. follow these steps: 1. 3. Table 2–13. Add the Scope Block To add the Scope block. Draw connection lines from the right side of the Product block to the left side of the StreamMod block. Set the Scope parameters (Table 2–13). 2. Drag and drop a Scope block into your model and position it to the right of the StreamMod block. 4.Chapter 2: Getting Started Creating the Amplitude Modulation Model 2–13 Figure 2–6.

Double-click on the Clock block to display the Block Parameters dialog box. Figure 2–7. From the right side of the Mux block to the top left side of the Scope block. Click OK. Table 2–14. 3. c. Parameters for the Clock Block Parameter Real-World Clock Period Period Unit: Simulink Sample Time Reset Name Reset Type Export As Output Pin Value 20 ns 2. 7. 6. Close the Scope. d.2–14 Chapter 2: Getting Started Creating the Amplitude Modulation Model 5. Set the Clock parameters (Table 2–14). Figure 2–7 shows the required connections. follow these steps: 1.5e–008 aclr Active Low Off DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . 2. Drag and drop a Clock block into your model. 4. From the right side of the StreamMod block to the middle left side of the Scope block. Amplitude Modulation Design Example Add a Clock Block To add a Clock block. b. Make connections to connect the complete your design as follows: a. Select the AltLab library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. From the right side of the StreamBit block to the bottom left of the Scope block. From the bottom left of the Product block to the line between the Bus Builder block and the StreamBit block.

If no base clock exists in your design.0 4e–6 Fixed-step discrete (no continuous states) f For detailed information about solver options. follow these steps: 1. Click Configuration Parameters on the Simulation menu to display the Configuration Parameters dialog box and select the Solver page (Figure 2–8 on page 2–15). Figure 2–8. Configuration Parameters 3. a default clock with a 20ns real-world period and a Simulink sample time of 1 is automatically created. 2. Save your model. Click OK. Table 2–15. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .Chapter 2: Getting Started Simulating the Model in Simulink 2–15 1 A clock block is required to set a Simulink sample time that matches the sample time specified on the Sine Wave and Random Bitstream blocks. Simulating the Model in Simulink To simulate your model in the Simulink software. refer to the description of the Solver Pane in the Simulink Help. Configuration Parameters for the singen Model Parameter Start time Stop time Type Solver Value 0. Set the parameters (Table 2–15). 5.

4. Select the AltLab library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. add a Signal Compiler block by following these steps: 1. Figure 2–9 shows the scaled waveforms. 2. 6. 3. Figure 2–9. Scope Simulation Results Compiling the Design To create and compile a Quartus II project for your DSP Builder design. Drag and drop a Signal Compiler block into your model. Click Compile. Click the Autoscale icon (binoculars) to auto-scale the waveforms. Double-click the Signal Compiler block in your model to display the Signal Compiler dialog box (Figure 2–10).2–16 Chapter 2: Getting Started Compiling the Design 4. Start simulation by clicking Start on the Simulation menu. Double-click the Scope block to view the simulation results. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . For this tutorial. 5. The dialog box allows you to set the target device family. you can use the default Stratix device family. and to program your design onto an Altera FPGA.

click OK. 2. The Testbench Generator dialog box appears (Figure 2–11). Performing RTL Simulation To perform RTL simulation with the ModelSim software. 3. Double-click on the new TestBench block. by following these steps: 1. When the compilation completes successfully. Select the AltLab library from the Altera DSP Builder BlockSet folder in the Simulink Library Browser. 6. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . add a TestBench block. Signal Compiler Block Dialog Box 5.Chapter 2: Getting Started Performing RTL Simulation 2–17 Figure 2–10. Drag and drop a TestBench block into your model. Click Save on the File menu to save your model.

2–18 Chapter 2: Getting Started Performing RTL Simulation Figure 2–11. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Testbench Generator Dialog Box 4. Ensure that Enable Test Bench generation is on.

Testbench Generator Dialog Box Advanced Tab 6. 8. Figure 2–12. 10. Turn on the Launch GUI option. 9. 7. All waveforms initially show using digital format in the ModelSim Wave window. The testbench initializes all your design registers with a pulse on the aclr input signal. The user interface commands may be different in other versions of ModelSim.4a. This option causes the ModelSim GUI to launch when you invoke the ModelSim simulation. Click Run Simulink to generate Simulink simulation results for the testbench. you can right-click to display the popup menu. Click Generate HDL to generate a VDHL-based testbench from your model.Chapter 2: Getting Started Performing RTL Simulation 2–19 5. Your design simulates with the output displaying in the ModelSim Wave window. Click the Advanced tab (Figure 2–12). 1 In ModelSim 6. Change the format of the sinin. Click Run ModelSim to load your design into ModelSim. point to Format and click on Analog (Automatic). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . sindelay and streammod signals to analog.

Start the Quartus II software. Before you follow these steps. Adding the Design to a Quartus II Project DSP Builder uses the Quartus II project created by the Signal Compiler block. Figure 2–13. This section describes how to add your design to a new or existing Quartus II project. Analog Display The introductory DSP Builder tutorial is complete. Creating a Quartus II Project To create a new Quartus II project: 1. ensure that your design is compiled with the Signal Compiler block (“Compiling the Design” on page 2–16). Click Zoom Full on the right button pop-up menu in the ModelSim Wave window. D:\MyQuartusProject. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . For example. Click New Project Wizard on the File menu in the Quartus II software and specify the working directory for your project. The simulation results display as an analog waveform (Figure 2–13). 2. The next section shows how you can add a DSP Builder design to a new or existing Quartus II project.2–20 Chapter 2: Getting Started Adding the Design to a Quartus II Project 11. Subsequent chapters in this user guide provide examples that illustrate some of the additional design features supported by DSP Builder.

Click Next to display the Family & Device Settings page and check that the required device family is selected. For example. 5.mdl and click Select Set as Top-Level Entity. 2. Click the Files tab in the Quartus II software. 6. You can use a relative path if you organize your design data with the DSP Builder and Quartus II designs in subdirectories of the same design hierarchy. 1 When you specify a directory that does not already exist. Compile the Quartus II design by clicking Start Compilation on the Processing menu. 4. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . On the View menu in the Quartus II software. Run the singen_add. 4. 1 You can copy the component declaration from the example file for your own code.Chapter 2: Getting Started Adding the Design to a Quartus II Project 2–21 3. 5. Click Next to display the Add Files page. a message asks if the specified directory should be created.tcl script that can be found in the <DSP Builder install path>\DesignExamples\Tutorials\GettingStartedSinMdl directory by typing the following command in the Tcl Console window: # source <install path>/DesignExamples/Tutorials/GettingStar tedSinMdl/singen_add.tcl 1 You must use / separators instead of \ separators in the command path name used in the Tcl console window. Add the DSP Builder Design to the Project To add your DSP Builder design to the project in the Quartus II software: 1. There are no files to add for this tutorial. NewProject and the name of the top-level design entity for the project. 1 The name of the top-level design entity typically has the same name as the project. This should normally be the same device family as specified for Signal Compiler in “Compiling the Design” on page 2–16. 3. point to Utility Windows and click Tcl Console to display the Tcl Console. Click Finish to close the wizard and create the new project. Right-click singen. Click Yes to create the directory. Specify the name of the project. An example instantiation is added to your Quartus II project.

2–22 Chapter 2: Getting Started Adding the Design to a Quartus II Project DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

For example. Do not use illegal characters. the input port MyInput and MYINPUT is the same VHDL entity. VHDL identifier names can contain only a . All DSP Builder port names must comply with the following naming conventions: ■ VHDL is not case sensitive. and an error issues if they do not have unique names.z.hex File to Initialize a Block” “Comparison Utility” “Adding Comments to Blocks” “Adding Quartus II Constraints” “Displaying Port Data Types” “Displaying the Pipeline Depth” “Updating HDL Import Blocks” “Analyzing the Hardware Resource Usage” “Loading Additional ModelSim Commands” “Making Quartus II Assignments to Block Entity Names” DSP Builder Naming Conventions DSP Builder generates VHDL files for simulation and synthesis. Design Rules and Procedures This chapter discusses the following topics: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ “DSP Builder Naming Conventions” “Using a MATLAB Variable” “Fixed-Point Notation” “Bit Width Design Rule” “Frequency Design Rules” “Timing Semantics Between Simulink and HDL Simulation” “Signal Compiler and TestBench Blocks” “Hierarchical Design” “Goto and From Block Support” “Create Black Box and HDL Import” “Using a MATLAB Array or . clock and reset ports are never renamed. and underscore (_) characters.3.9. Avoid using VHDL keywords for DSP Builder port names. When there are blocks or ports in your model that share the same VHDL name. Avoid name clashes on other ports. to avoid renaming of the top-level ports in the VHDL. they are given unique names in the VHDL to avoid name clashes. However. ■ ■ © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 0 .

z). DSP Builder evaluates the variable and passes its value to the simulation model files. VHDL does not allow identifiers to begin with non-alphabetic characters or end with an underscore. integer (INT) Unsigned binary.3–2 Chapter 3: Design Rules and Procedures Using a MATLAB Variable ■ Begin all port names with a letter (a . For information about which values are parameterizable. MATLAB evaluates parameter values to doubles. Do not use two underscores in succession (__) in port names because it is illegal in VHDL. Using a MATLAB Variable You can specify many block parameters (such as bit widths and pipeline depth) by entering a MATLAB base workspace or masked subsystem variable.1} DOWNTO 0) A Simulink unsigned binary signal A[L] maps to STD_LOGIC_VECTOR({L . f Fixed-Point Notation Figure 3–1 describes the fixed-point notation that I/O formats use in the DSP Builder block descriptions. You can then set these variables on the MATLAB command line or from a script. and signals are converted to an underscore when DSP Builder converts the Simulink model file (.[R] maps in VHDL to STD_LOGIC_VECTOR({L + R .[R] where: fractional (SBF) representation. integer (UINT) [L] where: Notation [L] is the number of bits to the left of the binary point and the MSB is the sign bit [R] is the number of bits to the right of the binary point [L] is the number of bits of the signed bus and the MSB is the sign bit [L] is the number of bits of the unsigned bus A Simulink signed binary signal A[L] maps to STD_LOGIC_VECTOR({L . which you can access with the Help command in the right button pop-up menu for each block. which restricts the possible values to 51-bit numbers expressible by a double. DSP Builder ensures that the parameters are in the required range. 1 Although DSP Builder no longer restricts parameters to 51 bits. a fractional number Signed binary. refer to the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook or to the block descriptions. components.mdl) into VHDL. Fixed-Point Notation Description Signed binary: [L]. (2) A Simulink SBF signal A[L]. Table 3–1.1} DOWNTO 0) [L] where: DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . ■ 1 White spaces in the names for the blocks.1} DOWNTO 0) Simulink-to-HDL Translation (1).

[]—represents the number of bits to the left of the binary point including the sign bit.all and ieee. The Input block casts floating-point Simulink signals of type double into fixed-point signals. DSP Builder represents the fixed-point signals in the following signed binary fractional (SBF) format: ■ [number of bits]. convert floating-point values to fixed-point values. DSP Builder translates the Simulink unsigned bus type with width w into a VHDL signed bus of width w + 1 where the MSB bit is set to 0. Number Format Comparison Binary Point Location in Signed Binary Fractional Format For hardware implementation.std_logic_1164. This conversion is a critical step for hardware implementation because the number of bits required to represent a fixed-point value plus the location of the binary point affects both the hardware resources and the system accuracy.all IEEE library packages). you must cast Simulink signals into the desired hardware bus format. signed binary.std_logic_signed. (2) For designs in which unsigned integer signals are used in Simulink. Therefore. (2) A Simulink single bit integer signal maps to STD_LOGIC Figure 3–1 graphically compares the signed binary fractional.Chapter 3: Design Rules and Procedures Fixed-Point Notation 3–3 Table 3–1. Notation [1] where: the single bit can have values 1 or 0 Simulink-to-HDL Translation (1). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Figure 3–1. DSP Builder speeds up your design cycle by enabling simulation with fixed-point and floating-point signals in the same environment. and unsigned binary number formats. You must design for the optimum size and accuracy trade-off. Choosing a large number of bits gives excellent accuracy—the fixed-point result is almost identical to the floating-point result—but consumes a large amount of hardware. Fixed-Point Notation Description Single bit integer (BIT) Notes to Table 3–1: (1) STD_LOGIC_VECTOR and STD_LOGIC are VHDL signal types defined in the (ieee.

in the amplitude modulation tutorial design (Chapter 2. However. the binary numbers are identical.3–4 Chapter 3: Design Rules and Procedures Bit Width Design Rule ■ []. For example. while others have specific bit width growth rules that the documentation for each block describes.[number of bits]—represents the number of bits to the right of the binary point. that is. Some intermediate DSP Builder blocks must have a bit width specified.01. In the first case. In both cases. you can adjust the binary point location to define the signal range and the area of interest. refer to AN 83: Binary Numbering Systems. the multiplier output bus grows on the least significant bit (LSB). allow use of a growth rule—the Inferred type setting. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Therefore. the multiplier output bus grows on the most significant bit (MSB). two bits on the left side of the binary point and two bits on the right side. f For more information about number systems.75 or –3 is very different. In VHDL. you do not need to specify the bit width for all blocks. However. DSP Builder propagates this bit width from the source to the destination through all intermediate blocks. Some blocks. Some blocks which allow bit widths to be specified optionally. If you do not specify explicitly the bit width.75 This signed STD_LOGIC_VECTOR is interpreted as –3 From a system-level analysis point of view. the location of the binary point affects how a simulator formats the representation of the signal. which allow bit widths to be specified optionally. while others have specific bit width growth rules which are described in the documentation for each block. especially when looking at the bit width growth. DSP Builder represents the 4-bit binary number 1101 as: Simulink VHDL This signed integer is interpreted as –3 This signed STD_LOGIC_VECTOR is interpreted as –3 If you change the location of the binary point to 11. Some intermediate DSP Builder blocks must have a specified bit width. DSP Builder types the signals as STD_LOGIC_VECTOR. For complex systems. have an Inferred type setting that allows a growth rule to be used. multiplying a number by –0. DSP Builder represents the numbers as: Simulink VHDL This signed fraction is interpreted as –0. Data Width Propagation You can specify the bit width of many Altera blocks in the Simulink design. Bit Width Design Rule You must specify the bit width at the source of the datapath. in the second case. a bit width of 16 is automatically assigned to the intermediate Delay block. For example. Getting Started) the SinIn and SinDelay blocks have a bit width of 16. DSP Builder assigns a bit width during the Simulink-to-VHDL conversion by propagating the bit width from the source of a datapath to its destination.

DSP Builder propagates the 8-bit bus in this register chain where each register is eight bits wide (Figure 3–4).mdl created by Signal Compiler.Chapter 3: Design Rules and Procedures Bit Width Design Rule 3–5 Figure 3–2 illustrates bit-width propagation. 3-Tap FIR Filter in Quartus II RTL View Tapped Delay Line The bit width propagation mechanism starts at the source of the datapath. which feeds U2. which feeds U1.0000. 3-Tap FIR Filter The fir3tapsub. Figure 3–3. 1.0000. a Gain block performs the coefficient multiplication Figure 3–3 shows the RTL representation of fir3tapsub.mdl design is a 3-tap finite impulse response (FIR) filter and has the following attributes: ■ ■ ■ ■ The input data signal is an 8-bit signed integer bus The output data signal is a 20-bit signed integer bus Three Delay blocks build the tapped delay line The coefficient values are {1. This bus feeds the register U0. which is an 8-bit input bus.0000}. in this case at the Input block. -5. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Figure 3–2.

and 14 bits.[rb] + [lc].3–6 Chapter 3: Design Rules and Procedures Bit Width Design Rule Figure 3–4.[ra] + [lb]. DSP Builder automatically sign extends the 14-bit busses to 16 bits. Tap Delay Line in Quartus II Version RTL Viewer Arithmetic Operation Figure 3–5 shows the arithmetic section of the filter. 16. that computes the output yout: 2 yout  k  =  x  k – i c  i  i=0 where c[i] are the coefficients and x[k .(max([ra].[ra]  [lb]. [rc])) The parallel adder has three input buses of 14. which covers the full resolution. [rb].[rc] The bus width of the resulting signal is: (max([la]. 3-Tap FIR Filter Arithmetic Operation in Quartus II Version RTL Viewer This design requires three multipliers and one parallel adder. The output bit width of the parallel adder is 18 bits.[rb] The bus width of the resulting signal is: ([la] + [lb]).i] are the data.([ra] + [rb]) ■ Adding a + b + c in SBF format (where l is left and r is right) is equal to: [la]. [lc]) + 2). To perform this addition in binary. The arithmetic operations increase the bus width in the following ways: ■ Multiplying a  b in SBF format (where l is left and r is right) is equal to: [la]. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . [lb]. Figure 3–5.

the output of the Gain block has 4 bits removed. 3-Tap Filter with BusConversion to Control Bit Widths In Figure 3–6. The VHDL synthesis tool removes any unused logic. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . or Saturate block.Chapter 3: Design Rules and Procedures Bit Width Design Rule 3–7 The following options can change the internal bit width resolution and therefore change the size of the hardware required to perform the function that Simulink describes: ■ ■ Change the bit width of the input data. ■ Figure 3–6 shows how you can use Bus Conversion blocks to control internal bit widths. Change the bit width of the output data. Insert a Bus Conversion block to change the internal signal bit width. Round. Figure 3–6. Port data type display is enabled in this example and shows that the inputs to the Delay blocks are of type INT_8 but the outputs from the Bus Conversion blocks are of type INT_6. The parallel adder required has a smaller bit width and the synthesis tool reduces the size of the multiplier to have a 9-bit output (Figure 3–7). 1 You can also achieve bus conversion by inserting an AltBus. The RTL view illustrates the effect of this truncation.

You can use the Clock block to change the Simulink sample period and the hardware clock period. You can access and drive these optional ports by checking the appropriate option in the Block Parameters dialog box. the DSP Builder blocks use a sampling frequency of 1. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . For Simulink simulation. Simulink does not graphically display the clock enable and reset input pins of the DSP Builder registered blocks. However. Frequency Design Rules This section describes the frequency design rules for single and multiple clock domains. By default. it automatically connects these pins. When DSP Builder converts a design to VHDL. 1 Simulink issues a warning if you are using an inappropriate solver for your model. You should set the solver options to fixed-step discrete when you are using a single clock domain.3–8 Chapter 3: Design Rules and Procedures Frequency Design Rules Figure 3–7. all DSP Builder blocks (including registered DSP Builder blocks) use the sampling period specified in the Clock block. when DSP Builder converts your design to VHDL it automatically connects the clock pin of the registered blocks (such as the Delay block) to the single clock domain of the system. refer to “Fixed-Point Notation” on page 3–2. The default clock pin is named clock and there is also a default active-low reset pin named aclr. 3-Tap Filter with BusConversion to Control Bit Widths in Quartus II RTL Viewer f For more information. Single Clock Domain If your design does not contain a PLL block or Clock_Derived block. The clock pin is not graphically displayed in Simulink unless you use the Clock block. which runs at the system sampling frequency. All DSP Builder registered blocks (such as the Delay block) operate on the positive edge of the single clock domain. If there is no Clock block in your design. DSP Builder uses synchronous design rules to convert a Simulink design into hardware.

© June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . f Refer to “Using the PLL Block” on page 3–14 for more information. However for most DSP Builder blocks. 1 You must set a variable-step discrete solver in Simulink when you are using multiple clock domains. the DSP Builder registered blocks operate on the positive edge of one of the block’s output clocks. consider the following points: ■ Do not use DSP Builder combinational blocks for rate transitions to ensure that the behavior of the DSP Builder Simulink model is identical to the generated RTL representation. Figure 3–8. When using multiple sampling periods. To ensure a proper hardware implementation of a DSP Builder design using multiple clock domains. If your design contains the PLL block. You can specify the clock domain in some DSP Builder block sources. Therefore. DSP Builder must associate each sampling period to a physical clock domain that can be available from an FPGA PLL or a clock input pin. Example of Incorrect Usage: Mixed Sampling Rate on a NOT Block ■ Two DSP Builder blocks can operate with two different sampling periods. You can also specify the clock domain in DSP Builder rate change blocks such as Tsamp. You can use a PLL block to synthesize additional clock signals from a reference clock signal. These internal clock signals are multiples of the system clock frequency. the sampling period of each input port and each output port must be identical. Clock or Clock_Derived blocks. Figure 3–8 illustrates an incorrect use of the DSP Builder Logical Bit Operator (NOT) block. the top-level DSP Builder model must contain DSP Builder rate change blocks such as PLL or Clock_Derived.Chapter 3: Design Rules and Procedures Frequency Design Rules 3–9 Multiple Clock Domains A DSP Builder model can operate using multiple Simulink sampling periods. there are some exceptions such as the Dual-Clock FIFO block where the sampling period of the read input port is expected to be different than the sampling period of the write input port. Although this rule applies most of the DSP Builder blocks. such as the Counter block.

This requirement is especially true when the source data rate is higher than the destination register. Figure 3–9. Stable Hardware Implementation Using Clock and Clock_Derived Blocks DSP Builder maps the Clock and Clock_Derived blocks to two hardware device input pins. If you use Clock_Derived blocks. and there is only one system clock.3–10 Chapter 3: Design Rules and Procedures Frequency Design Rules ■ For a datapath using mixed clock domains. you must generate an appropriate clock signal for connection to the hardware device input pins for the derived clocks. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Figure 3–10. A design may contain zero or one Clock block and zero or more Clock_Derived blocks. and one for the reset input for the clock domain. Data Toggling Faster than Clock Figure 3–10 shows a stable hardware implementation. one for the clock input. the design may require additional register decoupling around the register that is between the domains. in other words. when the data of a register is toggling at the higher rate than the register’s clock pin (Figure 3–9).

Registered blocks—the output changes after a variable number of sample time slots. The clock domains of the PLL block share the reset pin of the PLL block's input clock. DSP Builder also connects the reset pins of the registered blocks to the top-level reset port for the block's clock domain. When your design does not contain a Clock block. DSP Builder uses a default base clock. You can use it to define multiple clock domains with sample times specified in terms of the PLL input clock. The Clock block and each of the Clock_Derived blocks have their own reset pin. there is a default base clock with a Simulink sample time of 1. the Clock_Derived block and the PLL block. clock enable. and Clock_Derived blocks define other clock domains. If your design contains more Clock and Clock_Derived blocks than there are clock buffers available. The Clock block defines the base clock domain. When your design contains clock source blocks. Use the PLL input clock either as the base clock or a derived clock. DSP Builder blocks fall into the following clocking categories: ■ Combinational blocks—the output always changes at the same sample time slot as the input. Each clock domain has an associated reset pin. The PLL block maps to a hardware PLL. You can specify its Simulink sample time and hardware clock period directly. If there is no Clock block. with a Simulink sample time of 1. ■ © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . the name of which is in the block's parameter dialog box. DSP Builder implicitly connects the clock pins of all the registered blocks to the appropriate clock pin or PLL output. Clock_Derived block. the design uses a default clock pin named clock and a default active-low reset pin named aclr. DSP Builder specifies the sample time of a derived clock as a multiple and divisor of the base clock sample time. non dedicated routing resources route the clock signals. DSP Builder specifies sample times in terms of the base clock sample time. all the registered DSP Builder block clock pins connect to a single clock domain (signal clock in VHDL). If there is no Clock block. The Signal Compiler block assigns a clock buffer and a dedicated clock-tree to clock-signal input pin automatically to maintain minimum clock skew. and reset signals in the VHDL design for synthesis. and a hardware clock period of 20 s. You can use the Clock_Derived block to define clock domains in terms of the base clock.Chapter 3: Design Rules and Procedures Frequency Design Rules 3–11 The Clock block defines the base clock domain. This feature is available across all device families that DSP Builder supports. Define clock domains by the clock source blocks: the Clock block. If no Clock block is present. Clock Assignment DSP Builder identifies registered DSP Builder blocks such as the Delay block and implicitly connects the clock. or PLL block.

DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . In the VHDL netlist. Figure 3–12 illustrates the behavior of a registered DSP block. with the Clock Phase Selection parameter equal to 100.3–12 Chapter 3: Design Rules and Procedures Frequency Design Rules Figure 3–11 illustrates DSP Builder block combinational behavior. Otherwise. is converted into a VHDL shift register with a decimation of three and an initial value of zero. Figure 3–12. Magnitude Block: Combinational Behavior The Magnitude block translates as a combinational signal in VHDL. Figure 3–11. a registered block must be in the feedback loop. Delay Block: Registered Behavior For feedback circuitry (the output of a block fed back into the input of a block). DSP Builder creates an unresolved combinational loop (Figure 3–13). DSP Builder does not add clock pins to this function. The Delay block. DSP Builder adds clock pin inputs to this function.

The Delay block is enabled every other phase and every other data (sampled at the rate 1) passes through. ■ Table 3–2. The data on phases 1. The Delay block is enabled on the 2nd phase out of 4 and only the 2nd data out of 4 (sampled at the rate 1) passes through. Table 3–2 shows some examples of typical clock phase selections. The Clock Phase Selection box accepts a binary pattern string to describe the clock phase selection. DSP Builder disables the block. When a bit is equal to one. DSP Builder enables the block. and 4 does not pass through the Delay block. Alternatively. Clock Phase Selection Example Phase 1 10 0100 Description The Delay block is always enabled and captures all data passing through the block (sampled at the rate 1). The Clock Phase Selection field in the Block Parameters dialog box specifies the values for the Delay block. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . DSP Builder processes each digit or bit of this string sequentially on every cycle of the fastest clock. Feedback Loop Use the PLL block and assign different sampling periods on registered DSP Builder blocks to design multirate designs.Chapter 3: Design Rules and Procedures Frequency Design Rules 3–13 Figure 3–13. when a bit is equal to zero. use a single clock domain with clock enable and the following design rules to design multirate designs without the DSP Builder PLL block: ■ The fastest sample rate is an integer multiple of the slower sample rates. 3.

mdl DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Figure 3–14.3–14 Chapter 3: Design Rules and Procedures Frequency Design Rules Figure 3–14 compares the scopes for the Delay block operating at a one quarter rate on the 1000 and 0100 phases. Figure 3–15. respectively. refer to the device handbook for the device family you are targeting. Figure 3–15 shows an example of multiple-clock domain support using the PLL block. f For information about the built-in PLLs. The number of PLL internal clock outputs that each device family supports depends on the specific device packaging. 1000 as Opposed to 0100 Phase Delay Using the PLL Block DSP Builder maps the PLL block to the hardware device PLL. MultipleClockDelay.

the Sample time parameters for the Sine Wave a block and Sine Wave b block are set explicitly to 1e-006 and 1e-007.mdl file to the Quartus II project as a source file. and output clock PLL_clk1 is set to 100 ns. Create a top-level design that instantiates your ALTPLL variation and your DSP Builder design. use a separate Quartus II project with the following method: ■ Create a new Quartus II project and use the MegaWizard™ Plug-In to configure the ALTPLL block. so that DSP Builder provides data to the input blocks at the rate at which they sample. Output clock PLL_clk0 is set to 800 ns. Specify these clocks by setting the Specify Clock option and enter the clock name in the Block Parameter dialog box for each input block. In this design.Chapter 3: Design Rules and Procedures Frequency Design Rules 3–15 Figure 3–16 shows the clock setting configuration for the PLL block in the design example MultipleClockDelay. Add the DSP Builder . duty cycle). ■ ■ © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Figure 3–16. Using Advanced PLL Features The DSP Builder PLL block supports the fundamental multiplication and division factor for the PLL. PLL Setting Datapath A (green in Figure 3–15) operates on output clock PLL_clk0 and datapath B (red in Figure 3–15) operates on output clock PLL_clk1. If you want to use other PLL features (such as phase shift.mdl.

The outputs of your model are the results of all these computations. However. 1 Use a fixed-step solver for a single clock domain design or a variable-step solver for multiple-clock domain designs. the rounding calculation that aligns the clock signals may set ModelSim simulation to run for one additional clock cycle (on the fastest clock). To avoid any timing conflicts. At the beginning of each step. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . you must use a discrete fixed or variable-step solver in Simulink. Each step is a discrete unit of simulation. The TestBench block-generated inputs arrive on negative clock edges. Simulation models in the DSP Builder libraries evaluate their logic on positive clock edges. This section describes the timing semantics that DSP Builder uses for translating between the Simulink and HDL environments. occasionally when using multiple clocks. DSP Builder quantizes the clock in an idealized manner as a cycle counter. Configure the solver timing mode in the Configuration Parameters dialog box from the Simulation menu in Simulink. For all steps.3–16 Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation Timing Semantics Between Simulink and HDL Simulation DSP Builder uses Simulink to simulate the behavior of hardware components. DSP Builder updates registered outputs on positive clock edges. You may receive an unexpected end of file error message because there is no stimulus data for this extra cycle. Simulink Simulation Model To ensure correlation between the HDL and Simulink simulation. Outputs varying based on inputs received in the same step are referred to as direct feedthrough. The TestBench block’ s testbench script feeds input signals to the HDL simulator that maintain correlation between the HDL and Simulink simulation. Generally DSP Builder aligns the timing so that ModelSim simulation finishes at the end of the stimulus data. Simulink blocks produce output signals. Some DSP Builder blocks may include direct feedthrough outputs. However. external inputs transition on negative clock edges. Simulink provides each block with inputs that you know. HDL Simulation Models DSP Builder drives hardware simulation with a clock signal and the available input stimuli. 1 The HDL simulation in ModelSim should run over the same time as the Simulink simulation. depending on the parameterization of each block. there are some fundamental differences between the step-based simulation in Simulink and the event-driven simulation that VHDL and Verilog HDL designs use. DSP Builder evaluates functions and propagates the resultant outputs in the current step. causing an apparent half-cycle delay in the arrival of output (Figure 3–17 on page 3–18).

1 DSP blocks or MegaCore functions may have additional initial conditions or startup states that are not automatically reset by the global reset signal. In the HDL domain. the Global Reset block outputs only a constant zero and has no simulation behavior. as this behavioral VHDL code example shows: process(CLOCK. this reset is ORed with the global reset. it automatically connects the implied clock enable and reset pins. A Global Reset block (SCLR). the value of the reset signal in Simulink simulation is still 0 for inactive and 1 for active. when targeting a development board. The value of the reset signal in simulation is therefore the value as it exists across the internal design. DSP Builder Global Reset Circuitry By default. and thus reset at the start of a ModelSim testbench simulation. All blocks (except the HDL Import and MegaCore function blocks) automatically connect any reset on the hardware to the global asynchronous reset for the clock domain. When converting from the Simulink domain to the hardware domain. The reset logic polarity can be either active-high or active-low. the registered DSP Builder blocks uses an asynchronous reset. and uses an input of the logic element look-up table to instantiate the function. end if. When you select active-low. When a block explicitly declares an asynchronous reset. Therefore. the reset period is before the Simulink simulation begins. If you turn on the optional ports in the Block Parameters dialog box for each of the DSP Builder registered blocks. Connect the hardware to reset. the Block Parameters dialog box for the DSP Board configuration block typically includes a Global Reset Pin selection box where you can choose from a list of pins that correspond to the DIP and push-button switches. DSP Builder inserts a NOT gate on the input pin in the generated hardware. which corresponds to this hardware signal is in the Altera DSP Builder Blockset IO & Bus library. you can access and drive the clock enable and reset input pins graphically in the Simulink software.Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation 3–17 Startup & Initial Conditions The testbench includes a global reset for each clock domain. else if CLOCK'event and CLOCK = '1' then dout <= din. in Simulink simulation. RESET) begin if RESET = '1' then dout <= (others => '0'). Simulink does not graphically display the clock enable and reset input pins on DSP Builder registered blocks. However. end In addition. The HDL simulates correctly in this case because the testbench produces the reset input as required. Quartus® II synthesis interprets this reset as an asynchronous reset. When DSP Builder converts a design to HDL. The global reset signal is reset before meaningful simulation. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . rather then the value at the input pin.

The counter output begins at 10—the value is 10 during the first Simulink clock step. In general.3–18 Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation Reference Timing Diagram Figure 3–17 shows the timing relationships in a hypothetical case where a register is fed by the output of a counter. Figure 3–18. For example. DSP Builder is not cycle-accurate when crossing clock domains. Figure 3–17. Figure 3–18 shows the timing delays in a design with a derived clock that has half the base clock period. Single-Clock Timing Relationships This timing is not true when crossing clock domains. Multiple-Clock Timing Relationships DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

sets up certain blocks (such as the memory blocks. With this flow. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Design Flows for Synthesis. Simulation flow—if the ModelSim executable (vsim.Chapter 3: Design Rules and Procedures Signal Compiler and TestBench Blocks 3–19 Signal Compiler and TestBench Blocks The Signal Compiler block uses Quartus II synthesis to convert a Simulink design into synthesizable VHDL including generation of a VHDL testbench and other supporting files for simulation and synthesis. You can also use the automatic flow to download your design into supported development boards. refer to the IO & Bus Library chapter of the DSP Builder Reference Manual. f For information about the parameters for the Signal Compiler and TestBench blocks. you can use the TestBench block to compile your design for ModelSim simulation. You should always run a simulation in Simulink before running Signal Compiler. The simulation updates all variables in your design (including workspace variables and inherited parameters). Manual flow—you can also add the . DSP Builder supports the following flows: ■ Automatic flow—allows you to control the entire design process in the MATLAB or Simulink environment with the Signal Compiler block. If you connect more Altera blocks (that map to HDL). Compilation and Simulation You can use the Signal Compiler and Testbench blocks to control your design flow for synthesis.mdl file and any imported HDL to your project. empty ports are created and the HDL does not compile for synthesis. compilation. and inputs from and outputs to workspace blocks).tcl script. You can then instantiate your design in HDL. Typically. f For more information about the Input and Output blocks. This script is generated whenever the Signal Compiler or TestBench block is run. and also traps any design errors that do not comply with Simulink rules. you connect these blocks to the Simulink simulation blocks for your testbench. and simulation. your design compiles inside a temporary Quartus II project. You can use the script to add the . refer to the AltLab Library chapter of the DSP Builder Reference Manual. An Output block should not connect to another Altera block. The results of the synthesis and compilation display in the Signal Compiler Messages box. ■ ■ For an example that uses the Signal Compiler blocker. The Input and Output blocks map to input and output ports in VHDL and mark the edge of the generated system. You can then automatically compare the Simulink and ModelSim simulation results.exe) is on your path. Signal Compiler assumes that your design complies with the Simulink rules and that any variables and inherited variables propagate through the whole design.mdl file to an existing Quartus II project using the <model name>_add. refer to page 2–14 of the “Getting Started”.

3–20 Chapter 3: Design Rules and Procedures Hierarchical Design Hierarchical Design DSP Builder supports hierarchical design using the Simulink Subsystem block. For example. Figure 3–19 illustrates a hierarchy for a design fir3tap.mdl) translates into one VHDL file. Figure 3–19. Hierarchical Design Example f For information about naming the Subsystem block instances. DSP Builder preserves the hierarchy structure in a VHDL design and each hierarchical level in a Simulink model file (. which implements two FIR filters.mdl. refer to “DSP Builder Naming Conventions” on page 3–1. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

and [WriteEna] with the From blocks ([ReadAddr]. You can use these blocks for large fan-out signals and to enhance the diagram clarity.Chapter 3: Design Rules and Procedures Goto and From Block Support 3–21 Goto and From Block Support DSP Builder supports the Goto and From blocks from the Signal Routing folder in the generic Simulink library. Figure 3–20. Figure 3–20 shows an example of the Goto and From blocks. which connect to the dual-port RAM blocks. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Goto & From Block Example Use the Goto blocks ([ReadAddr]. [WriteAddr]. [WriteAddr]. and [WriteEna].

'logfile. if the input value is –0. or ROM blocks.txt')r A testbench GUI displays messages as DSP Builder performs the comparison. if you select unsigned integer data type and the value is 1. HDL Entity. DSP Builder rounds this value down to 1. f For more information about running a comparison between Simulink and ModelSim. If the MATLAB array data values or the values in the . The command returns true (1) or false (0) according to whether the simulation results match and the output is recorded in the specified log file. True Dual-Port RAM. DSP Builder rounds them and issues a warning. Similarly. DSP Builder truncates the value to 11 = –0. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .[1]. refer to the “HDL Import Design Example” in Chapter 8.3–22 Chapter 3: Design Rules and Procedures Create Black Box and HDL Import Create Black Box and HDL Import You can add your own VHDL or Verilog HDL code to your design and specify which subsystem block(s) DSP Builder should translate into VHDL. For information about using these blocks to create an explicit black box. For information about creating an implicit black box with your own HDL code. Comparison Utility DSP Builder provides a simple utility that runs simulation comparison between Simulink and ModelSim from the command line: alt_dspbuilder_verifymodel('modelname.9.mdl'. then truncates to the specified width. HDL Output. An implicit black box uses the HDL Import block to instantiate the black-box subsystem.hex file do not represent exactly in the selected data type. You can implement this process—creating a black box—implicitly or explicitly. and Subsystem Builder blocks. DSP Builder rounds the value towards minus infinity to the nearest representable number. refer to “Subsystem Builder Design Example” in Chapter 8. refer to “Performing RTL Simulation” in Chapter 2. DSP Builder rounds the values by expressing the number in binary format.25 (minimally expressed in signed binary fractional two’s compliment format as 111) and the selected target data format is signed fractional [1]. Adding Comments to Blocks You can add comments to any DSP Builder block by right-clicking on the block to display the Block Properties dialog box and entering text in the Description field of the dialog box (Figure 3–21 on page 3–23). For example. You can also use an Intel format hexadecimal format (. An explicit black box uses the HDL Input.hex File to Initialize a Block Use a MATLAB array to specify the values entered in the LUT block or to initialize the Dual-Port RAM.5. Using a MATLAB Array or .hex) file to initialize a RAM or ROM block. Single-Port RAM. which results in rounding towards minus infinity.

refer to the DSP Builder Reference Manual. f For a description of the Quartus II Global Project Assignment block. You can add additional Quartus II assignments or constraints that are not supported in DSP Builder by creating a Tcl script in your design directory. Adding Quartus II Constraints You can set Quartus II global project assignments in your Simulink model by adding Quartus II Global Project Assignment blocks from the AltLab library. refer to the Quartus II Settings File Reference Manual. Any file named <model name>_add_user.Chapter 3: Design Rules and Procedures Adding Quartus II Constraints 3–23 Figure 3–21. The Tcl file can include any number of Quartus II assignments with the syntax: set_global_assignment -name <assignment> <value> f For detailed information about Quartus II assignments. such as target device or timing requirements. Each block sets a single global assignment but you can use multiple blocks for multiple assignments.tcl is automatically sourced when you run Signal Compiler. Adding Comments to a Block DSP Builder includes the comment text next to the instantiation of the block in the generated HDL. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . You can use these assignments to set Quartus II compilation directives.

The selected mode shows on the Display Pipeline Depth block symbol. or BIT where L. refer to “Fixed-Point Notation” on page 3–2. INT_L. the current pipeline depth displays at the top right corner of each block that adds latency to your design (Figure 3–22). UINT_L. When set. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . or UINT_16 for a 16-bit unsigned integer. Displaying the Pipeline Depth You can optionally display the pipeline depth on the primitive blocks (such as the Arithmetic library blocks) in your Simulink model by adding a Display Pipeline Depth block from the AltLab library. You can change the display mode by double-clicking on the block. SBF_8_4 for a 12-bit signed binary fractional data type with 4 fractional bits. and R are the number of bit to the left and right of the binary point) displays. When you set this option. Tutorial Example Showing Port Data Types and Pipeline Depth f For more information about the DSP Builder internal signal types. the DSP Builder internal signal type (SBF_L_R. For example. Figure 3–22 shows the amplitude modulation example with port data type display enabled. Figure 3–22. Updating HDL Import Blocks The HDL Import blocks in your design may need updating if you upgrade from a previous software version or move a design to a different workstation.3–24 Chapter 3: Design Rules and Procedures Displaying Port Data Types Displaying Port Data Types You can optionally display the Simulink and DSP Builder port data types for each of the signals in your Simulink model by turning on Port Data Types in the Port/Signal Displays section of the Simulink Format menu.

the HDL Import dialog box opens and a compilation is automatically invokes to regenerate the Simulink model. If it finds the references. it uses this netlist for simulation. Resource Usage Block The Resource Usage dialog box updates to show a detailed report of the resources that each of the blocks require in your model that generate hardware. Run the command by typing the following at the MATLAB prompt: alt_dspbuilder_refresh_hdlimport r You can optionally select a HDL Import block to run the command on only the selected subsystem. 2. Double-click on the Signal Compiler block and click Compile to recompile your design in the Quartus II software. Drag and drop a Resource Usage block into your model and double-click on the block to open the Resource Usage dialog box. This command checks that the referenced HDL files (or Quartus II project) exists. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . RAM and DSP block usage (Figure 3–23). 2. but there is an existing simulation netlist. 3. Analyzing the Hardware Resource Usage To analyze the hardware resources required for your design with a Resource Usage block. Select the AltLab library from the Altera DSP Builder BlockSet folder in the Simulink Library Browser. Open a Simulink model that contains imported HDL. Figure 3–23. If it finds neither.Chapter 3: Design Rules and Procedures Analyzing the Hardware Resource Usage 3–25 You can use the alt_dspbuilder_refresh_hdlimport command to update these blocks. 3. To run the command. The Resource Usage block updates to show a summary of the estimated logic. follow these steps: 1. Start the MATLAB or Simulink software. follow these steps: 1.

You can also click the Timing tab and click Highlight path to highlight the critical paths on your design. For a more complex example.3–26 Chapter 3: Design Rules and Procedures Analyzing the Hardware Resource Usage For example. the entire critical path through your design may highlight. Refer to the device documentation for more information. the critical path is due to the internal function or a feedback loop. Figure 3–24. 1 When the source and destination in the dialog box are the same and a single block is highlights. Figure 3–24 shows the hardware resources that the Product block requires in the amplitude modulation example. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Resource Usage Dialog Box f The information depends on the selected device family.

if your model is my_model. you can use regular expressions in the assignments. DSP Builder creates a subdirectory DSPBuilder<model name>_import. you may want to make a Preserve Registers assignment to the Delay blocks in Figure 3–25 to prevent them from merging. and for the assignment to remain when the block parameters change. a Delay block entity name: alt_dspbuilder_delay_GNLVAGVO3B Changing the parameterization of the block causes the entity name to change. Figure 3–25. The entity names have the following format: <block type name>_GN<8 alphanumeric characters> For example.tcl. For example. Blocks of the same type and same parameterization share a common VHDL entity. If you want to make an assignment to a block in the Quartus II project. which contain additional ModelSim commands that you want to load into ModelSim. You should not modify the generated scripts. Entity Name Assignment Example Using the Quartus II Assignment Editor and Node Finder tools.Chapter 3: Design Rules and Procedures Loading Additional ModelSim Commands 3–27 Loading Additional ModelSim Commands When you import HDL as a black box. the names may be: my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay|alt_dsp builder_SDelay:Delay1i|DelayLine my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay1|alt_ds pbuilder_SDelay:Delay1i|DelayLine © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Any Tcl script *_add_msim. you can identify the names of the registers and make the assignments to them.tcl in this subdirectory automatically sources when you launch ModelSim. Making Quartus II Assignments to Block Entity Names The VHDL entity names of the blocks in a DSP Builder design are dependent on the block’s parameter values. For example. but you can create you own scripts such as <user name>_add_msim.

DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . you can edit the To field of the assignment and use a regular expression that is still valid if the entity name changes due to a parameter change: Replace the eight alphanumeric characters following the GN in the block entity name with . If you change the length of the delay. The targets of the assignments then become: my_model_GN:auto_inst|alt_dspbuilder_delay_GN. you can use the following code: my_model_GN:auto_inst|alt_dspbuilder_delay_GN.3–28 Chapter 3: Design Rules and Procedures Making Quartus II Assignments to Block Entity Names These assignments prevent merging of the registers. However.{8}. which is a regular expression that matches any eight characters. Figure 3–26. the assignments are no longer valid.{8}:Delay|alt_dspbuil der_SDelay:Delay1i|DelayLine my_model_GN:auto_inst|alt_dspbuilder_delay_GN.{8}:Delay1|alt_dspbui lder_SDelay:Delay1i|DelayLine If you want the assignment to apply to the whole block.{8}:Delay my_model_GN:auto_inst|alt_dspbuilder_delay_GN. Preserve Registers Assignment in the Quartus II Assignment Editor This type of assignment can be useful for a complicated block that contains many registers when you want the assignment to apply to all of the registers.{8}:Delay1 Figure 3–26 shows this example in the Quartus II Assignment Editor. not just the specific nodes.

2. You must run the DSP Builder MegaCore function setup command after installing new MegaCore functions to update DSP Builder. You must parameterize and generate these MegaCore functions after you add one of these blocks to your model. 1 The OpenCore Plus evaluation feature allows you to download and evaluate these MegaCore functions in hardware and simulation prior to licensing. If MATLAB is already running. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . In this folder.4. Start the MATLAB software. Installing MegaCore Functions Altera DSP MegaCore functions install with the Quartus® II software. To run this setup command. follow these steps: 1. Blocks represent these MegaCore functions in the MegaCore Functions library of the Altera DSP Builder Blockset in the Simulink Library Browser. Run the setup command by typing the following at the MATLAB prompt: alt_dspbuilder_setup_megacore r 1 The process of building the MegaCore function blocks may take several minutes. Running this command. Using MegaCore Functions Altera provides a number of parameterizable intellectual property (IP) MegaCore functions that you can integrate into the Simulink model of your DSP Builder designs. f Refer to “MegaCore Function Design Example” on page 4–3 for an example of the design flow using these MegaCore functions. f Refer to the MegaCore function user guides for information about each MegaCore function. there is a blue block with a version name for each of the installed MegaCore functions. 3. Use the cd command at the MATLAB prompt to change directory to the directory where DSP Builder is installed. creates a MegaCore Functions subfolder below the Altera DSP Builder Blockset in the Simulink Library Browser.“ when installing a new MegaCore library. Do not close MATLAB before the process completes. ensure you close the Simulink library browser. Expect and ignore any messages of the form “Cannot find the declaration of element 'entity'.

Generate the MegaCore function variation. This command recreates the simulation files based on the VHDL file for each MegaCore function block in the current Simulink model. Adding the MegaCore Function in the Simulink Model Add a MegaCore function to a Simulink model by dragging a copy of the block from the Simulink Library Browser to your design workspace like any other Simulink block. Design Flow Using MegaCore Functions Using MegaCore functions in the MATLAB or Simulink environment involves the following steps: 1. These blocks may revert to their unconfigured appearance if the VHDL file that describes the function variation is available but the simulation database (. Add the MegaCore function to the Simulink model and give the block a unique name. Using unique block names ensures that all the generated entities for the same MegaCore function in a hierarchical design also have unique names. In these cases. 1 A Quartus II license must be available on the machine for the command to execute without errors. Connect your MegaCore function variation to the other blocks in your model. save your model file. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . you can update the MegaCore function variation blocks in your design using the alt_dspbuilder_refresh_megacore command. f Refer to the appropriate MegaCore function user guide for information about the design flow used for each MegaCore function. a MegaCore function variation block always uses an intermediate VHDL file to record parameters. 3. Update a block if you change the version of the MegaCore function you are using. 5. this number is automatically incremented to make the name unique. Simulate the MegaCore function variation in your model. Parameterize the MegaCore function variation. Altera recommends that you rename all blocks representing MegaCore functions with a name describing their use in your design. 4. If you add more than one copy of a block in the same model. 2. After adding the block and before parameterization.4–2 Chapter 4: Using MegaCore Functions Updating MegaCore Function Variation Blocks Updating MegaCore Function Variation Blocks Although a DSP Builder design using MegaCore function blocks from the MegaCore Functions library can be translated by Signal Compiler into a VHDL or Verilog HDL model. The correct version number still shows on the body of the block.simdb) file is not. The default name of a MegaCore function block includes its version number.

Simulating the MegaCore Function Variation in the Model You can simulate the Simulink block representing the MegaCore function variation like any other block from the Simulink Library Browser. DSP Builder also performs an additional step of optimizing your model for use in Simulink. Click Generate in IP Toolbench (or Finish in the MegaWizard interface) to generate the necessary files for your MegaCore function variation. point to New and click Model to create a new model window. generate a MegaCore function variation after you have parameterized the MegaCore function. Connecting the MegaCore Function Variation Block to the Design The Simulink block now has the required input and output ports as parameterized in IP Toolbench or the MegaWizard interface. Creating a New Simulink Model To create a new Simulink workspace. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 2. follow these steps: 1. You can connect these ports to other Altera DSP Builder blocks in your Simulink design. Start the MATLAB or Simulink software. 1 You can also double-click on a block to re-open and modify a previously parameterized MegaCore function variation. 1 This tutorial assumes that your PC has the Altera MegaCore IP Library. On the File menu. 3.Chapter 4: Using MegaCore Functions MegaCore Function Design Example 4–3 Parameterizing the MegaCore Function Variation Double-click the MegaCore function block to open the IP Toolbench or MegaWizard interface. 1 Ensure that the Simulink simulation engine is set to use the discrete solver by selecting fixed-step type under Solver Options in the Configuration Parameters dialog box. MegaCore Function Design Example This tutorial shows how to create a custom low-pass FIR filter MegaCore function variation using the IP Toolbench interface. Generating the MegaCore Function Variation Before you can connect the block to your design. You should reset the MegaCore function at the start of the simulation to avoid any functional discrepancy between RTL simulation and Simulink simulation (“Startup & Initial Conditions” on page 3–17). Click Save on the File menu in the new model window.

2. Click Save. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . The Simulink Library Browser displays. This tutorial uses the name mc_example.0 block into your model (Figure 4–2). Type the file name into the File name box. This directory becomes your working directory.mdl.4–4 Chapter 4: Using MegaCore Functions MegaCore Function Design Example 4. On the View menu In your Simulink model window. MegaCore Functions Library 3. Drag and drop a blue versioned fir_compiler_v9. Select the MegaCore Functions library from the Altera DSP Builder Blockset folder in the Simulink Library Browser (Figure 4–1 on page 4–4). follow these steps: 1. Browse to the directory in which you want to save the file. This tutorial creates and uses the working directory <DSP Builder install path>\DesignExamples\Tutorials\MegaCore 5. 6. Figure 4–1. click Library Browser. Adding the FIR Compiler Function To place a FIR Compiler MegaCore function block in your design.

Chapter 4: Using MegaCore Functions MegaCore Function Design Example 4–5 Figure 4–2. to generate the files for inclusion in the Simulink model and simulation. Click Exit. refer to the FIR Compiler User Guide.FIR Compiler MegaCore function dialog box displays. follow these steps: 1. To rename the block. Figure 4–3. 3. Click Finish. Click Step 2: Generate in IP Toolbench. Parameterizing the FIR Compiler Function To use FIR Compiler to create a MegaCore function variation that fits the specific needs of your design. FIR Compiler Block Placed in Simulink Model 4. The FIR filter is ready for you to connect it to the rest of your Simulink design. 2. Rename the block to my_fir_compiler. click the default name (the text outside of the block itself) and edit the text. The Parameterize . Click Step 1: Parameterize to specify how the FIR filter should operate. f For more information about the FIR Compiler including a complete description of the generated files. Generating the FIR Compiler Function Variation After you parameterize the MegaCore function. 2. Use the default values. follow these steps: © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Double-click the my_fir_compiler block to start IP Toolbench. 3. The generation report lists the design files that IP Toolbench creates. Naming conventions are described in “DSP Builder Naming Conventions” on page 3–1. specifying a low-pass filter. follow these steps: 1. FIR Compiler Block in Simulink Model After Generation Adding Stimulus and Scope Blocks To create a sample design to test the low-pass filter by feeding the filter two sine waves (Figure 4–4 on page 4–8). The my_fir_compiler block in the Simulink model updates to show the input and output ports for your configuration (Figure 4–3).

Use the Block Parameters dialog box to set the parameters (Table 4–2). DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . 9. Parameters for the Sine Wave Blocks Value Parameter Sine type Time Amplitude Bias Samples per period Number of offset examples Sample time Interpret vector parameters as 1-D Sine Wave Sample based Use simulation time 64 0 200 0 1 On Sine Wave1 Sample based Use simulation time 64 0 7 0 1 On 3. Add another Constant block (from the IO & Bus library) and connect this block to the ast_sink_error pin on the my_fir_compiler block.4–6 Chapter 4: Using MegaCore Functions MegaCore Function Design Example 1. Add two Sine Wave blocks (from the Simulink Sources library). Table 4–1. 5. 1 DSP Builder automatically gives the second block a unique name. Repeat Step 2 for the Sine Wave1 block. Add an Input block (from the IO & Bus library in the Altera DSP Builder Blockset) and connect it between the Add block and the ast_sink_data pin on the my_fir_compiler block. Connect the outputs from the Sine Wave and Sine Wave1 blocks to an Add block (from the Simulink Math Operations library). Parameters for the Input Block Parameter Bus Type [number of bits]. 4. 8. 2. Use the Block Parameters dialog box to set the parameters for the Constant block (Table 4–3). 6.[] Specify Clock Value Signed Integer 8 Off 7. Add a Constant block (from the IO & Bus library) and connect this block to both the ast_sink_valid and ast_source_ready pins on the my_fir_compiler block. Use the Block Parameters dialog box to set the parameters for the Sine Wave block (Table 4–1). Table 4–2.

[] External Type Value Signed Integer 18 Inferred 15. 11.[] Rounding Mode Saturation Mode Specify Clock Constant 1 Single Bit – Truncate Wrap Off Constant1 0 Signed Integer 2 Truncate Wrap Off 10. 16. Use the ‘Scope’ Parameters dialog box to configure the Scope block as a 2-input scope. Table 4–4. Use the Block Parameters dialog box to set the parameters (Table 4–4). Add an Output block (from the IO & Bus library in the Altera DSP Builder Blockset) to your design and connect it to the ast_source_data pin on the my_fir_compiler block. Parameters for the Single Pulse Block Parameter Signal Generation Type Delay Specify Clock Value Step Up 50 Off 13. 12.Chapter 4: Using MegaCore Functions MegaCore Function Design Example 4–7 Table 4–3. Repeat Step 9 for the Constant1 block. Add a Scope block (from the Simulink Sinks library). 14. Parameters for the Constant Blocks Value Parameter Constant Value Bus Type [Number of Bits]. Parameters for the Output Block Parameter Bus Type [number of bits]. Connect the Scope block to the Input and Output blocks to monitor the source noise data and the filtered output. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Use the Block Parameters dialog box to set the parameters (Table 4–5 on page 4–7). Figure 4–4 shows how your model looks. Add a Single Pulse block (from the Gate & Control library in the Altera DSP Builder Blockset) and connect it to the reset_n pin on the my_fir_compiler block. Table 4–5.

click Configuration Parameters to display the Configuration Parameters dialog box (Figure 4–5 on page 4–8). Connecting Blocks to the Low-Pass Filter Simulating the Design in Simulink To simulate your design. On the Simulation menu in your model. Figure 4–5.4–8 Chapter 4: Using MegaCore Functions MegaCore Function Design Example Figure 4–4. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . follow these steps: 1. Select the Solver page and set the parameters (Table 4–6). Configuration Parameters: mc_example/Configuration Dialog Box 2.

2. Double-click the new Signal Compiler block in your model.0 5000 Fixed-step discrete (no continuous states) f For detailed information about solver options. and to program your design onto an Altera FPGA. click Start. Simulation Output Check that the FIR filter block behaves as you expect and filters high-frequency data as a low-pass filter. add a Signal Compiler block. The scope output shows the effect of the low-pass filter in the bottom window (Figure 4–6). Follow these steps: 1. The Signal Compiler dialog box appears (Figure 4–7). refer to the description of the Solver Pane in the Simulink Help.Chapter 4: Using MegaCore Functions MegaCore Function Design Example 4–9 Table 4–6. Drag and drop a Signal Compiler block into your model. 4. 3. On the Simulation menu in the simulink model. Figure 4–6. 1 You may need to use the Autoscale command in the Scope display to view the complete waveforms. 3. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Configuration Parameters for the singen Model Parameter Start time Stop time Type Solver Value 0. Click OK. Compiling the Design To create and compile a Quartus II project for your DSP Builder design. Select the AltLab library from the Altera DSP Builder Blockset folder in the Simulink Library Browser.

add a TestBench block. Double-click on the new TestBench block. The TestBench Generator dialog box appears (Figure 4–8). Drag and drop a TestBench block into your model. Follow these steps: 1. Performing RTL Simulation To perform RTL simulation with the ModelSim software.4–10 Chapter 4: Using MegaCore Functions MegaCore Function Design Example Figure 4–7. Select the AltLab library from the Altera DSP Builder BlockSet folder in the Simulink Library Browser. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . 2. 3. Click Compile. Signal Compiler Dialog Box 4. 5. click OK. When the compilation has completed successfully.

Ensure that Enable Test Bench generation is on. 5.Chapter 4: Using MegaCore Functions MegaCore Function Design Example 4–11 Figure 4–8. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Click the Advanced Tab (Figure 4–9). TestBench Generator Dialog Box 4.

Turn on the Launch GUI option to launch the ModelSim GUI if you invoke ModelSim simulation. 9.25. TestBench Generator Dialog Box Advanced Tab 6. Repeat Step 10 for the output signal in the ModelSim Wave window and use the Wave Properties dialog box to change the format to Analog with height 75 and scale 0. 7. Click Run ModelSim to simulate your design in ModelSim. 8. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Click the Format tab and change the format to Analog with height 75 and Scale 0. Click Run Simulink to generate Simulink simulation results for the testbench. 10. 11.001. Right-click the input signal in the ModelSim Wave window and click Properties in the pop-up menu to display the Wave Properties dialog box. 1 All waveforms initially show using digital format in the ModelSim Wave window. Click Generate HDL to generate a VDHL-based testbench from your model. Your design loads into ModelSim and simulates with the Wave window displaying the output.4–12 Chapter 4: Using MegaCore Functions MegaCore Function Design Example Figure 4–9.

Generated HDL for mc_example Simulated in ModelSim Simulator Note to Figure 4–10: (1) This waveform display format shows the input and output signals as analog waveforms. Figure 4–10. Click Compare Results in the Testbench Generator dialog box to compare the simulink results with the ModelSim-generated results. MegaCore Functions Design Issues This section describes some of the design issues to consider when using MegaCore functions in a DSP Builder design. The ModelSim simulator now displays the input and output waveforms in analog format (Figure 4–10). make sure that you also copy this subdirectory. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . The message Exact Match indicates that the results are identical. Click Zoom Full on the right button right button pop-up menu in the ModelSim Wave window. Simulink Files Associated with a MegaCore Function DSP Builder stores the files that support the configuration and simulation of a MegaCore function variation in a subdirectory of the directory containing your Simulink MDL file DSPBuilder_<design name>_import. When copying a design from one location to another. Click OK to close the Testbench Generator dialog box. 1.Chapter 4: Using MegaCore Functions MegaCore Functions Design Issues 4–13 12. 2.

■ Simulating MegaCore Functions That Have a Reset Port MegaCores functions that have a reset port must have a reset cycle at the start of Simulink simulation to produce correct simulation results. Setting the Device Family for MegaCore Functions Most of the MegaCore functions available in DSP Builder use the IP Toolbench interface. Additional adjustment of the reset cycles may be necessary when a MegaCore function receives data from other MegaCore functions. As in hardware. and depends on the particular MegaCore function and parameterization. in Figure 4–11. this reset cycle must be sufficiently long to propagate through the core. your design variation is in a my_function. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .simdb file.4–14 Chapter 4: Using MegaCore Functions MegaCore Functions Design Issues DSP Builder needs the following specific files to simulate a MegaCore function variation: ■ If your MegaCore function variation is my_function. For example.vo. MegaCore Function Design With a Reset Port You must simulate an initial reset cycle (with the step input) to replicate hardware behavior. If your design is my_design. to ensure that the blocks leave the reset state in the correct order and DSP Builder delays them by the appropriate number of cycles. Figure 4–11. which may be 50 clock cycles or more for some MegaCore functions such as the FIR Compiler.vhd file in your design directory. DSP Builder cannot tie the reset to a constant because the simulation does not match hardware. The length of this reset cycle must be of sufficient length. the simulation information is in a DSPBuilder_my_design_import/my_function. and generates in VHDL.

Reed Solomon Compiler. This interface always inherits the device family setting from the Signal Compiler block. MegaCore functions that use IP Toolbench allow you to modify the device family setting in the IP Toolbench interface. 1 The FFT. NCO.Chapter 4: Using MegaCore Functions MegaCore Functions Design Issues 4–15 The CIC MegaCore function uses a MegaWizard user interface. and Viterbi Compiler MegaCore functions use IP Toolbench. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . If there is no Signal Compiler block in your design. FIR Compiler. you must check that any IP Toolbench MegaCore functions have the correct device family set to ensure that the simulation models and generated hardware are consistent. DSP Builder uses the Stratix device family by default. If you change the device family in Signal Compiler.

4–16 Chapter 4: Using MegaCore Functions MegaCore Functions Design Issues DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Create a Quartus II project that defines the functions you want to co-simulate in hardware and use Signal Compiler block to compile the Quartus II project through the Quartus II Fitter. and discusses the optional burst and frame data transfer modes. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . including the following options: ■ ■ ■ ■ ■ The Quartus II project to define its functionality The clock and reset pins The reset active level The input and output pin characteristics The use of single-step versus burst and frame mode 4. The Quartus II project you embed in an FPGA runs faster than a software-only simulation. Compile the HIL block to create a programming object file (. The HIL block also makes available to the hardware a large Simulink library of sinks and sources. The main benefits of using the HIL block are faster simulation and richer instrumentation. walks through an example using the HIL block. To further increase simulation speed. Using HIL Adding the HIL block to your Simulink model allows you to cosimulate a Quartus II software design with a physical FPGA board implementing a portion of that design. 2. The HIL design flow comprises the following steps: 1. It represents the functions implemented on your FPGA. which can give you greater control and observability. 3. you must add a Clock block with the same values as the HIL block. HIL Design Flow The HIL block in AltLab library of the Altera DSP Builder Blockset enables the HIL functionality. You can also connect instrumentation to your HIL block by adding additional blocks from the Simulink Sinks and Sources libraries. the HIL block offers frame and burst modes of data transfer that are significantly faster than single-step mode when you use it with suitable designs. A simple JTAG interface between Simulink and the FPGA board links the two. You define the contents and function of the FPGA by creating and compiling a Quartus II project. Add the HIL block to your Simulink model and import the compiled Quartus II project into the HIL block. This chapter explains the HIL block design flow. Specify parameters for the HIL block.pof) for hardware cosimulation. such as channel models and spectrum analyzers. 1 If the original design contains a Clock block that defines a period and sample time that is different from the default values.5. and works smoothly with the normal DSP Builder/Simulink work flow.

A valid Quartus II project that contains a single clock domain from Simulink. Cyclone. set a fixed-step. System-Level Design Flow HIL Requirements The HIL block has the following requirements: ■ An FPGA board with a JTAG interface (Stratix. Figure 5–1 shows this system-level design flow using DSP Builder. ByteBlaster. DSP Builder creates an internal Quartus II project when you run Signal Compiler. Figure 5–1. Stratix III. Scan for JTAG cables and hardware devices connected to the local host or any remotely enabled hosts. or USB-Blaster™ cable). ByteBlaster™ II. Program the board that contains your target FPGA. A maximum of one HIL block for each JTAG download cable. single tasking solver. 6.5–2 Chapter 5: Using HIL HIL Requirements 5. 1 When using a HIL block in a Simulink model. Cyclone II. a ByteBlasterMV™. Simulate the combined software and hardware system in Simulink. 7. Stratix II. A JTAG download cable (for example. MasterBlaster™. ■ ■ ■ DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . or Cyclone III device).

follow these steps: 1. Figure 5–2. and runs the Quartus II Fitter. 1 This tutorial uses the Stratix II hardware device on an Altera Stratix II EP2S60 DSP Development Board.qpf. FreqSweep. and open the model FreqSweep. This action creates a Quartus II project. To create a frequency sweep design.mdl in the <DSP Builder install path>\DesignExamples\Tutorials\HIL\FreqSweep directory. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Double-click the Signal Compiler block. Progress is indicated by status messages and a scrolling bar at the bottom of the dialog box. However. compiles your model for synthesis.Chapter 5: Using HIL HIL Design Example 5–3 HIL Design Example DSP Builder includes the following design examples in the <DSP Builder install path>\DesignExamples\Tutorials\HIL directory that demonstrate the use and effectiveness of HIL: ■ ■ ■ ■ Imaging edge detection Export example Fast Fourier Transform (FFT) Frequency sweep This section shows the frequency sweep design. Figure 5–2 shows the model. click Compile. you can also use any other supported device and development board. In the dialog box that appears (Figure 5–3 on page 5–4). Run MATLAB. Frequency Sweep Model 2.

Signal Compiler Dialog Box. Review the Messages. Figure 5–4 shows this model.5–4 Chapter 5: Using HIL HIL Design Example Figure 5–3. Figure 5–4. Replace the internal functions of the frequency sweep model with an HIL block.mdl from the FreqSweep directory (step 1). Open the model FreqSweep_HIL. then click OK to close the Signal Compiler dialog box. with the HIL block in place. Simple Tab 3. 4. Frequency Sweep Design Model Using the HIL Block DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Select aclr from the list of available reset pins. 16. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 15. Select the reset level to be Active_High. Click Close. to display the second page of the Hardware in the loop dialog box. 1 HIL does not support multiple clock domains and only the specified signal is the HIL clock signal. 9. Click Scan Jtag to find available cables and hardware devices in the chain. Identify the signed ports: ■ ■ Select the Input port and click Unsigned. 7. Select Clock from the list of available clock pins. 1 The full path to this file is visible in the dialog box when you select this file. Select the Quartus II project by browsing into the FreqSweep_dspbuilder directory to locate the FreqSweep. The HIL treats any other clocks in your design as input signals. check that the original Quartus II project is up-to-date and compiles with he same version of the Quartus II software that compiles your Simulink model. 8. 10. 11. Select the mode of operation by turning off Burst Mode. 14. Click Next page. Double-click the frequency sweep HIL block to display the Hardware in the loop dialog box. 13.Chapter 5: Using HIL HIL Design Example 5–5 5. Specify a value for the FPGA device and click Compile with Quartus II to compile the HIL design. 12.qpf file. Select each output port (OutputCordic and OutputFilter) and click Signed. Select the JTAG download cable that references the required FPGA device and click Configure FPGA to program the FPGA on the board. 6. 1 If no output writes to the MATLAB command window.

A latency is introduced on the output signals of the HIL block making feedback loop difficult outside the FPGA device.5–6 Chapter 5: Using HIL Burst and Frame Modes 17. To maximize the throughput of this data transfer. the HIL block offers a burst mode that buffers the stimulus data and presents it in bursts to the hardware. Feedback is possible outside of the HIL block. No frame mode. Burst mode also allows a frame mode for certain types of designs. Scope Output from the FrequencySweep Model with HIL Block Burst and Frame Modes The Quartus II software infrastructure that communicates with the FPGA through JTAG—system-level debugging (SLD)—uses a serial data transfer protocol. Burst ■ ■ ■ ■ ■ Disadvantages High SLD overhead. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Simulate your design in Simulink. Fast HIL results. Low SLD overhead. Comparing Single-Step and Burst Modes Mode Single step Advantages Cycle accurate simulation. Figure 5–5. Table 5–1. Frame mode possible. Table 5–1 shows the advantages and disadvantages of using burst mode compared with the normal single-step mode. Figure 5–5 shows the scope display from the finished design.

Chapter 5: Using HIL Burst and Frame Modes 5–7 Using Burst Mode To activate burst mode turn on the Burst Mode option in the Hardware in the loop dialog box (Figure 5–6). you can specify the required number of data packets as the Burst length. DSP Builder resets the burst length to 1. The HIL block sends data to the hardware in bursts of the size you specify. DSP Builder sets the Burst length to 1. Setting Parameters for the HIL Block in Figure 5–8 When you set this option. In the HIL model (C++). 1 DSP Builder determines the size of the packet by the larger of the total input data width or the total output data width. DSP Builder defines an array for storing the input and output data to the HIL as 0x800000 byte in size. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Figure 5–6. When the data record size (max of total input bits and output bits) / 8 × burst length × 2 (for both input and output) exceeds this number. If the packet size multiplied by the Burst length exceeds the preset data array.

feedback-loops may not work properly unless you enclose them in the HIL block. Frame mode builds on the burst functionality and provides a way to partially compensate for the burst mode output delay. For example. if the burst length is 1024 and the latency 3. There is one input synchronization and one output synchronization signal available. ■ In frame mode. As a consequence. the delay is 1027 (1024 + 3) without frame mode or 2048 (aligned to the next frame) with frame mode on. For example. you can use a frame burst size of N × 100 clocks (N positive integer). and some intervention may be necessary when comparing or visualizing HIL simulation results. and twiddle precision of 16 bits. Using Frame Mode To activate frame mode turn on the Frame Mode option in the Hardware in the loop dialog box (Figure 5–6 on page 5–7). with a transform length of 64 points. DSP Builder provides the data frames at regular intervals. To use frame mode. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . the following conditions must be true: ■ ■ ■ The HIL block works with the concept of blocks of data (frames).5–8 Chapter 5: Using HIL Burst and Frame Modes Simulation using burst mode works the same as single clock mode. if packets arrive every 100 clocks. Figure 5–7 illustrates a DSP Builder design with a FFT MegaCore function configured for the Stratix II target device family. the HIL block monitors the input synchronization and output synchronization signals and increases the output delay to align the output data frames with the input data frames. The burst packet size in frame mode must be a multiple of the frame packet interval. The latency between the input synchronization and output synchronization signals is constant. data precision of 16 bits. The HIL block uses software buffers to send and receive from the hardware. but DSP Builder introduces a latency of the specific packet size on the output signals of the HIL blocks. so you can change these buffer sizes without recompiling the HIL function.

DSP Builder Design Using the FFT MegaCore Function Figure 5–8 on page 5–9 shows the FFT design with a HIL block (and the parameters from Figure 5–6 on page 5–7). Using the FFT Design With an HIL Block The FFT MegaCore function respectively uses the Avalon-ST interface signals sink_eop and source_valid in the HIL block as the input synchronization and output synchronization signals. Figure 5–8. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . f Refer to the FFT MegaCore Function User Guide for additional information about the input and output port signal timing.Chapter 5: Using HIL Burst and Frame Modes 5–9 Figure 5–7.

and input and output ports. no output writes to the MATLAB command window. it can fail to load your project if the project is not compiled with the Quartus II Fitter. Scan JTAG Fails to Find Correct Cable or Device This issue occurs if you connect the target DSP development board switch it on after you open the HIL dialog box. reset. However. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . This issue occurs if the original Quartus II project is out-of-date or compiled by a different version of the Quartus II software. HIL Design Stays in Reset During Simulation An asynchronous reset is permanently asserted for a HIL design. Recompile the HIL design after you have changed the reset level. 1 If the top-level of your design changes. HIL simulation works correctly. However. or the Quartus II project file is not up-to-date. such as from a counter. Action: Check that the reset active level matches the setting in the original design. compile and reload the Quartus II project into HIL to ensure that all information is up-to-date. from the specified Quartus II project. such as clock. there is a Quartus II version mismatch. HIL Compilation Appears to Hang After clicking Compile with Quartus II in the HIL Block Parameters dialog box. No Outputs Found From the Quartus II Project This issue occurs if your design does not have any outputs and makes the HIL simulation meaningless. No Inputs Found From the Quartus II Project This issue occurs if the DSP Builder model file contains only the internally induced signals. Fails to Load the Specified Quartus II Project HIL reads design information. and also does not produce any outputs.5–10 Chapter 5: Using HIL Troubleshooting HIL Designs Troubleshooting HIL Designs This section describes various issues that you may encounter when you are using HIL designs.

88% of the data is pre-trigger and 12% of the data is post-trigger 1 Alternatively. 2. Add a SignalTap II Logic Analyzer block to your design. SignalTap II Design Flow Working with the SignalTap II logic analyzer in DSP Builder involves the following flow: 1. which feeds an LED on the DSP development board. you can use the Quartus II software to instantiate of the SignalTap II logic analyzer in your design. an LED on the DSP development board turns on or off depending on the state of user-controlled switches and the value of the incrementer. refer to the Quartus II Help or to Volume 3 of the Quartus II Handbook. The comparator and AND gate outputs feed an OR gate. This design flow works for any of the Altera development boards that DSP Builder supports. In this design. f For more information about using the SignalTap II logic analyzer with the Quartus II software. The Quartus II software supports additional features. and four switches that feed into two AND gates. 3. In this chapter. f For detailed information about the supported development boards. Specify the signals (nodes) that you want to analyze by inserting SignalTap II Node blocks. The design consists of an incrementer function feeding a comparator. The SignalTap II logic analyzer captures the signal activity at the output of the two AND gates and the incrementer of the design loads into the Altera device on the development board. such as using multiple clock domains.mdl. easy-to-use interface Analyzes signals in the top-level design file Uses a single clock source Captures data around a trigger point. and adjusting the percentage of data captured around the trigger point. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . A SignalTap II Logic Analyzer block in DSP Builder includes the following characteristics: ■ ■ ■ ■ Has a simple. The logic analyzer retrieves the values and displays them in the MATLAB work space. refer to the Boards Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. you analyze three internal nodes in a simple switch controller design named switch_control.6. Turn on the Enable SignalTap option in the Signal Compiler dialog box. Performing SignalTap II Logic Analysis This chapter describes how to set up and run the SignalTap® II logic analyzer.

The trigger pattern comprises a logic condition for each input signal. refer to the descriptions of these blocks in the AltLab Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. all signal conditions for the trigger pattern are set to Don’t Care. Before capturing signals. SignalTap II Trigger Conditions The trigger pattern describes a logic event in terms of logic levels or edges. The SignalTap II logic analyzer can analyze up to 128 internal nodes or I/O elements. Using Signal Compiler. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . perform compilation in the Quartus II software. you must connect it to a SignalTap II Node block. 5. The SignalTap II logic analyzer uses a comparison register to recognize the moment when the input signals match the data specified in the trigger pattern. Specify the required trigger conditions in the SignalTap II Logic Analyzer block. including I/O pins. it uses more logic elements (LEs) or embedded system blocks (ESBs). You can select one of the following logic conditions for each input signal in the trigger pattern: ■ ■ ■ ■ ■ ■ Don’t care Low High Rising edge Falling edge Either edge The SignalTap II logic analyzer triggers when it detects the trigger pattern on the input signals. SignalTap II Nodes A node represents a wire carrying a signal that travels between different logical components of a design file. 6.6–2 Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs 4. The SignalTap II logic analyzer can capture signals from any internal device node in a design file. By default. masking them from trigger recognition. To assign a node to an input channel. synthesize your model. assign each node to analyze to a SignalTap II logic analyzer input channel. As more it capture more signals. f For details of the SignalTap II Logic Analyzer and SignalTap II Node blocks. Choose one of the JTAG cable ports in the Signal Compiler dialog box or the SignalTap II Logic Analyzer dialog box. and download your design into the DSP development board (starter or professional). SignalTap II Example Designs Altera provides several example designs (Figure 6–1).

(Figure 6–2). Opening the Design Example Open the template switch_control. you can use the design in the completed_walkthrough directory and go directly to “Turning On the SignalTap II Option in Signal Compiler” on page 6–6. This tutorial uses the Cyclone II EP2C35 development board. Starting Point for the SignalTap II Design Example Adding the Configuration and Connector Blocks You must add the board configuration block and connector blocks for the board that you want to use.mdl design in the <DSP Builder install path>\ DesignExamples\Tutorials\SignalTap\professional\original_design directory. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs 6–3 Figure 6–1. Figure 6–2. SignalTap II Design Example Directory Structure You can start from the design in the original_design directory. Alternatively.

Select the Boards library from the Altera DSP Builder Blockset folder in the Simulink library browser. Figure 6–3 shows your model. Drag and drop the SW2 and SW3 blocks close to the AND_Gate2 block in your model. Drag and drop another Pulse Generator block near the SW4 and SW5 blocks and connect it to these blocks. 7. 6. 4. Figure 6–3. 2. Connect these switch blocks to the AND_Gate2 inputs. 1 You can rotate the SW5 block to make the connection easier by right-clicking the block and clicking Rotate Block on the Format menu. Use the Block Parameters dialog box to set the parameters (Table 6–1) for both pulse generator blocks. Open the CycloneIIEP2C35 folder. Drag and drop a Pulse Generator block near to the SW2 and SW3 blocks and connect it to these blocks. Drag and drop the LED0 block close to the OR_Gate block in your model. 5. Switch Control Example with Board. Connect this block to the OR_Gate output. Connect these switch blocks to the AND_Gate1 inputs. Pulse Generator and Terminator Blocks 8. Drag and drop the Cyclone II EP2C35 DSP Development Board configuration block into your model.6–4 Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs 1. 3. Select the Simulink Sources library. Drag and drop the SW4 and SW5 blocks close to the AND_Gate1 block in your model. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Position the block so that it is on top of the connection line between the AND_Gate1 block and the OR_Gate block (Figure 6–4). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Drag a SignalTap II Node block into your design. 1 If you position the block with this method. Parameters for the Pulse Generator Blocks Parameter Pulse type Time Amplitude Period Pulse Width Phase delay Interpret vector parameters as 1-D Value Time based Use Simulation time 1 2 50 0 On 9. Select the Simulink Sinks library. the Simulink software inserts the block and joins connection lines on both sides. follow these steps: 1. Specifying the Nodes to Analyze To add SignalTap II Node blocks to the signals (also called nodes) that you want to analyze (in this tutorial they are the output of each AND gate and the output of the incrementer). Open the AltLab library in the Simulink Library Browser.Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs 6–5 Table 6–1. Drag and drop a Terminator block near to the OR_Gate block and connect it to this block.

Completed SignalTap II Design 2. Click the text under the block icon in your model and change the block instance name by deleting the text and typing the new text firstandout. Signal Compiler inserts an instance of the SignalTap II logic analyzer into your design. 3. Double-click the Signal Compiler block and click the SignalTap II tab in the Signal Compiler dialog box. 5. This connection is a functional change to your model and you must recompile your design before you can use the SignalTap II logic analyzer. When this option is on. each block implicitly connects to the SignalTap II logic analyzer. Add a SignalTap II Node block between the Eightbit Counter block and the Comparator block and name it cntout. To compile your design. 2. Verify that the Enable SignalTap II option is on. Add a SignalTap II Node block between the AND_Gate2 block and the OR_Gate block and name it secondandout. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Click Save on the File menu. Turning On the SignalTap II Option in Signal Compiler When you add node blocks to signals. follow these steps: 1. 4.6–6 Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs Figure 6–4.

Specify the following trigger condition settings for the firstandout block: a. 4. information messages in the dialog box display the memory allocated during processing. Select Falling Edge in the Set Trigger Level list. Repeat these steps to specify the trigger condition High for the secondandout block. For example. Click firstandout under Signal Tap II Nodes. 9. the SignalTap II logic analyzer only triggers when it detects a falling edge on firstandout and a logic level high on secondandout. Click Scan Jtag in the SignalTap II Logic Analyzer dialog box and select the appropriate download cable and device. 2. 6. because you specify Falling Edge for firstandout and High for secondandout. Click Program to download your design to the development board. b. Click OK. Click Scan Jtag and select the appropriate download cable and device (for example. To perform analysis. Specifying the Trigger Levels To specify the trigger levels. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Double-click the SignalTap II Logic Analyzer block. Performing SignalTap II Analysis You are now ready to run the analyzer and display the results in a MATLAB plot. Select a depth of 128 for the SignalTap II sample buffer (that is. Click the Compile button. 3. the SignalTap II logic analyzer begins analyzing the data and waits for the trigger conditions to occur. 7. After you click Acquire. Click the Simple tab and verify that the Use Board Block to Specify Device option is on. Click Change. the number of samples stored for each input signal) in the SignalTap II depth list. Click Acquire. follow these steps: 1. 8.Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs 6–7 3. 1 You must compile your design before you open the SignalTap II Analyzer block because the block relies on data files that create during compilation. When the conversion is complete. The dialog box displays all the nodes connected to SignalTap II Node blocks as signals to be analyzed. follow these steps: 1. The condition is updated. 5. The SignalTap II logic analyzer captures data for analysis when it detects all trigger patterns simultaneously on the input signals. 2. USB-Blaster cable and EP2C35 device). Verify that the Use Base Clock option is on. c.

mat files in the working directory. 4. It stores the values in MATLAB . Press switch SW4 on the DSP development board to trigger the SignalTap II logic analyzer. MATLAB Plot for SignalTap II Node firstandout Figure 6–6 shows the MATLAB plot for the SignalTap II node secondandout. 1 If you press and hold switch SW2 or SW3 while pressing switch SW4. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Figure 6–6. DSP Builder interprets the captured data as unsigned values and displays them in MATLAB plots. MATLAB Plot for SignalTap II Node secondandout Figure 6–7 shows the MATLAB plot for the SignalTap II node cntout. Figure 6–5.6–8 Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs 3. Click OK in the SignalTap II Logic Analyzer dialog box when you finish. the trigger condition is not met and acquisition does not occur. Figure 6–5 shows the MATLAB plot for the SignalTap II node firstandout.

Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs 6–9 Figure 6–7. MATLAB Plot for SignalTap II Node cntout f For more information about the SignalTap II Logic Analyzer block. refer to the SignalTap II Logic Analyzer block description in the AltLab Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .

6–10 Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

a memory. Avalon-MM Interface The Avalon Interface Specifications provide peripheral designers with a basis for describing the address-based read and write interfaces on master (for example. peripherals.7. refer to the Avalon Interface Specifications. The Interfaces library supports peripherals that use the Avalon-MM and Avalon-ST interface specifications. The Avalon-MM Master and Avalon-MM Slave blocks in DSP Builder provide a seamless flow for creating a DSP Builder block as a custom peripheral and integrating the block into your SOPC Builder system. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 1 The correct version of MATLAB with DSP Builder must be available on your system path to integrate DSP Builder . SOPC Builder automates the task of integrating hardware components into a larger system. Using the Interfaces Library This chapter describes how to use the Avalon-MM blocks in the Interfaces library to create a design that functions as a custom peripheral to SOPC Builder. refer to the Quartus II Handbook Volume 4: SOPC Builder. for more information about the Avalon-MM Interface. UART. your peripheral must meet the Avalon-MM interface or Avalon-ST interface specification and qualify as a SOPC Builder-ready component. a microprocessor or DMA controller) and slave peripherals (for example.mdl files in SOPC Builder. To integrate a DSP Builder design into your SOPC Builder system. SOPC Builder is a system development tool for creating systems that can contain processors. or timer). and memories. These blocks provide you the following benefits: ■ Automates the process of specifying Avalon-MM ports that are compatible with the Avalon-MM bus Supports multiple Avalon-MM master and Avalon-MM slave instantiations Saves time spent hand coding glue logic that connects Avalon-MM ports to DSP blocks ■ ■ f For more information about SOPC Builder.

refer to the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook.7–2 Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Avalon-MM Interface Blocks A SOPC Builder component is a design module that SOPC Builder recognizes and can automatically integrate into a system. With the Avalon-MM blocks in the Interfaces library. You can instantiate each Avalon-MM block multiple times in a design to implement an SOPC component with multiple master or slave ports. you can design the DSP function and add an Avalon-MM block that makes it a custom peripheral in the Simulink environment. SOPC Builder can recognize a DSP Builder design model if it is in the same working directory as the SOPC Builder project. Avalon-MM Slave Block The Avalon-MM Slave block supports the following signals: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ clock address read readdata write writedata byteenable readyfordata dataavailable endofpacket readdatavalid waitrequest beginbursttransfer burst count irq begintransfer chipselect f For more information about these signals. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks 7–3 Figure 7–1 shows a block that describes an Avalon-MM slave interface where all the Avalon-MM signals are enabled. Avalon-MM Slave Block Signals © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Figure 7–1.

refer to the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook.7–4 Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Each of the input and output ports of the block correspond to the input and output ports of the pin or bus that Figure 7–1 shows between the ports. outputs from the core display as left pointing pins or busses. Avalon-MM Master Block You may want to use an Avalon-MM Master block (for example. You can use the opposite end of any pins to provide pass-through test data from the Simulink domain. Inputs to the DSP Builder core display as right pointing bus or pins. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . The Avalon-MM Master block is similar to the Avalon-MM Slave block and supports the following signals: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ clock waitrequest address read readdata write writedata byteenable endofpacket readdatavalid flush burstcount irq irqnumber f For more information about these signals. to design a DMA controller) in a design that functions as an Avalon-MM Master in your SOPC Builder system. Figure 7–2 on page 7–5 shows a block that describes an Avalon-MM master interface where all the Avalon-MM signals are enabled.

Valid. To provide a high level view. You can implement a typical DSP core that handles data in a streaming manner. but they do little to mask the complexities of the interface.Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks 7–5 Figure 7–2. and Ready. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Avalon-MM Master Block Signals Wrapped Blocks The Avalon-MM Master and Avalon-MM Slave interface blocks allow you to generate a SOPC Builder component in DSP Builder. with the signals Data. The Avalon-MM read and write FIFO blocks in the Interfaces library provide a higher level of abstraction. DSP Builder provides you with configurable Avalon-MM Write FIFO and Avalon-MM Read FIFO blocks for you to map Avalon-MM interface signals to this protocol.

It simulates stall conditions of the Avalon-MM bus and hence underflow to the SOPC Builder component. Connect this port to a DSP Builder block and assert whenever DataOut corresponds to real data. DataValid (output). one sample per clock. Connect this port to a DSP Builder block that corresponds to the oldest unsent data sample received on the TestData port. Connect this port to a DSP Builder block. You can use this design as a template to design new functionality (for example. when stall is de-asserted.7–6 Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Figure 7–3 shows an example system with Avalon-MM Write FIFO and Avalon-MM Read FIFO blocks. Connect this port to a Simulink block. 1 To open the hierarchy below the Avalon-MM Write FIFO block. Stall (input). DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . right-click the block and click Look Under Mask on the pop-up menu. Figure 7–3. DataOut (output). It indicates that the downstream hardware is ready for data. Ready (input). the Avalon-MM Write Test Converter caches the test data and releases in order. Connect this port to a Simulink block that provides simulation data to the Avalon-MM Write FIFO. The data passes to the DataOut port one cycle after the Ready input port asserts. For any simulation cycle where Stall asserts. Example System with Avalon-MM Write FIFO and Avalon-MM Read FIFO Blocks Avalon-MM Write FIFO An Avalon-MM Write FIFO has the following ports: ■ TestData (input). ■ ■ ■ ■ Double-click on an Avalon-MM Write FIFO block to open the Block Parameters dialog box so that you can set parameters for the data type. data width and FIFO depth. when you use an Avalon-MM address input to split incoming streams).

Figure 7–4. data width and FIFO depth. You can use this block to test the functionality of your design. Connect this port to a DSP Builder block and assert whenever the signal on the Data port corresponds to real data. Data (input). When full. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . For any simulation cycle where Stall asserts. indicates that the block is ready to receive data. TestDataOut (output). DataValid (input). Ready (output). Connect this port to a DSP Builder block and to outgoing data from the user design. Connect this port to a Simulink block that corresponds to data received over the Avalon-MM bus. TestDataValid (output). When asserted. You can open the hierarchy below the Avalon-MM Read FIFO block by right-clicking on the block and choosing Look Under Mask from the pop-up menu. Connect this port to a Simulink block and assert whenever TestDataOut corresponds to real data. Figure 7–5 shows the internal content of an Avalon-MM Read FIFO. Avalon-MM Write FIFO Content The Avalon-MM Write Test Converter block handles caching and conversion of Simulink or MATLAB data into accesses over the Avalon-MM interface. The Avalon-MM Write Test Converter is simulation only and does not synthesize to HDL. Connect this port to a Simulink block. Avalon-MM Read FIFO Buffer An Avalon-MM read FIFO buffer has the following ports: ■ Stall (input). the Ready output is de-asserted so that you lose no data.Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks 7–7 Figure 7–4 shows the internal content of an Avalon-MM Write FIFO buffer. It simulates stall conditions of the Avalon-MM bus and hence backpressure to the SOPC Builder component. no Avalon-MM reads take place and the internal FIFO buffer fills. ■ ■ ■ ■ ■ Double-clicking on an Avalon-MM Write FIFO block opens the Block Parameters dialog box that you can use to set parameters for the data type.

You load the coefficients with the Nios II embedded processor while an off-chip source supplies the input data through an analog-to-digital converter. The design sends filtered output data off-chip through a digital-to-analog converter. The design consists of a 4-tap FIR filter with variable coefficients. You can use this block to test the functionality of your design.7–8 Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example Figure 7–5. Browse to the <DSP Builder install path>\DesignExamples\Tutorials\ SOPCBuilder\SOPCBlock directory. Click Open on the File menu in the MATLAB software. Avalon-MM Read FIFO Content The Avalon-MM Read Data Converter block handles caching and conversion of Simulink or MATLAB data into accesses over the Avalon-MM interface. 2. follow these steps: 1. The Avalon-MM Read Data Converter is simulation only and does not synthesize to HDL. Avalon-MM Interface Blocks Design Example This tutorial describes how to interface a design using the Avalon-MM Blocks as a custom peripheral to the Nios II embedded processor in SOPC Builder. Adding Avalon-MM Blocks to the Design Example To complete the design example. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

mdl in this folder. Write ibit. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 7. 8. Turn off the Allow Byte Enable option.mdl file and click Open. and specify 8 bits for the data width. Change the block name to Avalon_MM_Write_Slave. Figure 7–6.mdl. Click OK.Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example 7–9 3. Double-click on the Avalon_MM_Write_Slave block to bring up the Block Parameters dialog box. Rename the file by clicking Save As on the File menu. 6. Create a new folder MySystem and save your new MDL file as topavalon. Figure 7–6 shows new_topavalon. The Avalon_MM_Write_Slave block redraws with three ports: Address i1:0.mdl Design Example 4. Open the Simulink Library Browser. Expand the Altera DSP Builder Blockset and select Avalon Memory-Mapped in the Interfaces library. and Write Data i7:0. 5. Select the new_topavalon. Drag and drop an Avalon-MM Slave block into the top left of your model. Signed Integer for the data type. 9. new_topavalon. Select Write for the address type.

Double-click on the Avalon_MM_Read_Slave block to bring up the Block Parameters dialog box. 14. 15. Complete your design by connecting the Avalon_MM_Read_Slave ports (Figure 7–7). 1 You can re-size a block by dragging the resize handles at each corner. Click OK and notice that the Avalon_MM_Read_Slave block redraws with three ports: Address i1:0. and Read Data o7:0. you must replace the board block and analog-to-digital converter blocks by corresponding blocks for the appropriate board. Select Read for the address type. Signed Integer for the data type. 13. refer to the Boards Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. Figure 7–7. f The default design example uses the Stratix II EP2S60 DSP Development Board. For more information. If you have a different board (such as the Cyclone II EP2C35 Development Board). DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . 12. Connect the ports (Figure 7–7). and specify 8 bits for the data width.mdl Design Example 11.7–10 Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example 10. topavalon. Drag and drop another Avalon-MM Slave block into the top right of your model and change the name of this block instance to Avalon_MM_Read_Slave. Read ibit.

Coefficient values 1 0 0 0 load into the filter. use the TestBench block to verify your design. 17. Click Save on the File menu in your model window to save your model. Figure 7–8. Add oscilloscope probes to monitor the signals on the DSP development board. follow these steps: 1. This process generates HDL. and then compares the simulation results. Run a simulation and observe the results on the oscilloscope probes. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 18. Click Compare against HDL. To verify your design. runs Simulink and ModelSim. TestBench Dialog Box 2. Progress messages issue in the dialog box and completes with a message “Exact Match”.Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example 7–11 16. Verifying the Design Before using your design in SOPC Builder. Double-click the TestBench block to display the TestBench Generator dialog box (Figure 7–8).

mdl file and other required files into the Quartus II project. Specify a name for your project.7–12 Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example 3. b. click New Project Wizard. 1 The Quartus II software automatically specifies a top-level design entity that has the same name as the project.tcl in the Project folder. Click Next in the New Project Wizard. When the compilation has completed successfully. On the Tools menu. follow these steps: 1. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . 4. 3. 2. Specify SOPC as the system name. b. Click OK. until you get to the Family and Device Settings page. b. 2. This tutorial uses SOPC for the project name. Click Run to load your . c. Click OK. Verify that the selected device matches the FPGA on your DSP development board (if applicable). On the File menu in the Quartus II software. Instantiating the Design in SOPC Builder To instantiate your design as a custom peripheral to the Nios II embedded processor in SOPC Builder. c. On the Tools menu. click Tcl Scripts and follow these steps: a. follow these steps: 1. Verify that the Device is set to match your target development kit and click Compile. Click Finish to create the Quartus II project. Double-click on the Signal Compiler block to display the Signal Compiler dialog box. Specify the working directory for your project by browsing to <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\ MySystem. a. Select topavalon_add. click SOPC Builder and set the following parameters in the Create New System dialog box: a. d. 3. This tutorial assumes that the names are the same. Select VHDL for the target HDL. Running Signal Compiler To generate all the hardware and files required by the Quartus II software. Start the Quartus® II software. click OK.

h. f. Click the System Contents tab in SOPC Builder and set the following options: a. i. Set the reset and exception vectors to use onchip_mem and click Finish to add the processor to your system with all other parameters set to their default values. Double-click on JTAG UART and click Finish to accept the default settings. Expand Interface Protocols and Serial. Figure 7–9. e. Double-click Nios II Processor in the System Contents tab to display the MegaWizard interface. Double-click on System ID Peripheral and click Finish to accept the default settings.Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example 7–13 5. Expand DSPBuilder Systems and double-click the topavalon_interface module to include it in your Nios II system (Figure 7–9). Specify 30 KBytes for the Total Memory size. Including Your DSP Builder Design Module in SOPC Builder © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Expand Peripherals and Debug and Performance. d. c. Click Finish to add an on-chip RAM device to the system. Expand On-Chip and double-click On-Chip Memory (RAM or ROM). b. Expand Memories and Memory Controllers. g.

6. However. When the compilation completes. 1 If the Location column does not display. Close the Quartus II Programmer window. The system generation may take several minutes. Compiling the Quartus II Project To compile the Quartus II project. 5. c. In the Device and Pin Options dialog box. On the Assignments menu. Close the Pin Planner. click Pins to open the Pin Planner and make pin assignments for clk and reset_n (Table 7–1) (depending on which development board you are using). b. you can design the rest of your Nios II embedded processor system using the standard Nios II embedded processor design flow. 2. right-click in the pin assignments table and click Customize Columns to change the table display. You can ignore all other pin assignments for this tutorial. click Start Compilation to compile the Quartus II project. Table 7–1. Click OK to close the Settings dialog box. 6. Click Generate to generate the SOPC Builder system.7–14 Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example 1 If the memory device. Continue with this tutorial to exercise the system from software using the Nios II processor. you can click Auto-Assign Base Addresses on the System menu to automatically add a base address if necessary. 4. click Device and Pin Options. click the Unused Pins tab. interface protocol. select As input tri-stated and click OK. On the Assignments menu in the Quartus II software. Nios II processor. you should not need to set a base address. In the Settings dialog box. follow these steps: 1. and DSP Builder system add in this order. After the system generation in SOPC Builder completes. click Programmer on the Tools menu and click Start in the Quartus II Programmer to program the FPGA device on your development board. Pin Assignments for the Stratix II and Cyclone II Development Boards Node Name Direction Location Stratix II EP2S60 or EP2S60ES DSP Development Board clk reset_n Input Input PIN_AM17 PIN_AG19 Cyclone II EP2C35 DSP Development Board clk reset_n Input Input PIN_N2 PIN_A14 3. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . debug peripheral. On the Processing menu. click Device to display the Device page of the Settings dialog box and create the basic pin settings as follows: a.

h. Nios II C/C++ Application. Click Finish in the New Project wizard. Click on Make a New Folder and create a software subdirectory.c file into the project. In the Properties dialog box click System Library. On the Nios II menu in SOPC Builder. and click Properties.. c.c in your file system.ptf i. To use this program. select Nios II C/C++ Application and click Next. point to New and click Project. Add the test software to the new project as follows: a. (<DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\) b. The project compiles and the application code runs on the development board. Verify that the application project test_DSP_Block appears in the Nios II C/C++ Projects list. Observe the following results in the Nios II IDE Console: LOADING. Browse to the System PTF file <DSP Builder install path>\DesignExamples\ Tutorials\SOPCBuilder\SOPCBlock\MySystem\SOPC. 5.c file and click Copy.Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example 7–15 Testing the DSP Builder Block from Software Altera provides a C program that loads a set of four coefficient into the filter. g. follow these steps: 1. j. c. Create a new Nios II C/C++ application as follows: a.. Type test_DSP_Block for the Name of the project and select the Blank Project template. Turn off Support C++. Click OK. f. b. Select the test_DSP_Block project folder in the Nios II IDE and paste the test_DSP_Block. c. Turn on Reduced device drivers and Small C library. 4. Coefficient 1 = 1 © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Right-click on the test_DSP_Block. e. 2. and then repeats the process. Click OK. Run the test_DSP_Block software project in the Nios II IDE by right-clicking on test_DSP_Block and clicking Run As Nios II Hardware. 3. Right-click on the Nios II IDE application project. Locate the file test_DSP_Block. d. e. reads them back. Set some of the reduced code footprint options in the Nios II IDE as follows: a. d. In the New Project wizard. Turn on Specify Location and browse to the directory <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\MySystem. On the File menu in the Nios II IDE. test_DSP_Block. b. click Nios II IDE.

refer to AN364: Edge Detection Reference Design.. The design uses an additional slave port as a control port. follow these steps: 1. 3.7–16 Chapter 7: Using the Interfaces Library Avalon-MM FIFO Design Example Coefficient 2 = 0 Coefficient 3 = 0 Coefficient 4 = 0 RELOADING. Browse to the <DSP Builder install path>\DesignExamples\Tutorials\ SOPCBuilder\AvalonFIFO directory. Click Open on the File menu in the MATLAB software. Figure 7–10 shows sopc_edge_detector. Coefficient 1 = 0 Coefficient 2 = 0 Coefficient 3 = 1 Coefficient 4 = 0 f For information about using SOPC Builder to create a custom Nios II embedded processor. Select the sopc_edge_detector. 1 Avalon-MM FIFO Design Example This tutorial describes how to interface a design built using the Avalon-MM FIFO block as a custom peripheral to the Nios® II embedded processor in SOPC Builder.mdl design for the Cyclone II EP2C35 and Stratix II EP2S60 DSP development boards are available in the <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\Finished Examples directory. The DSP Builder model uses Simulink to read in the original image and to capture the edge detected result. Opening the Design Example To open the design example.. refer to AN 351: Simulating Nios II Embedded Processor Designs. Completed versions of the topavalon. 2. DSP Builder outputs the edge detected image through a VGA controller. f For a full description of the Prewitt edge detector design.mdl. The design consists of a Prewitt edge detector with one Avalon-MM write FIFO buffer and one Avalon-MM read FIFO buffer. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . DSP Builder stores the image in the compact flash and loads it in DMA with a Nios II embedded processor. For this hardware implementation.mdl file and click Open.

3.Chapter 7: Using the Interfaces Library Avalon-MM FIFO Design Example 7–17 Figure 7–10. Select the family and device for the DSP Development board you are using. Click Compile. sopc_edge_detector. 2.mdl Design Example Compiling the Design In this example. Double-click the Signal Compiler block. use the TestBench block (“Avalon-MM Interface Blocks Design Example” in “Verifying the Design” on page 7–11). The design example is configured for a Stratix 1S25 board (Figure 7–11). you use the Signal Compiler block to verify that your design generates valid HDL. follow these steps: 1. To verify your design. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 1 Alternatively.

Instantiating the Design in SOPC Builder To instantiate your design as a custom peripheral to the Nios II embedded processor in SOPC Builder. 1 The Avalon-MM read and write converter is simulation only and does not synthesize to HDL. click OK. Start the Quartus II software. When the compilation completes successfully. follow these steps: 1. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Signal Compiler Dialog Box 4.7–18 Chapter 7: Using the Interfaces Library Avalon-MM FIFO Design Example Figure 7–11.

b.Chapter 7: Using the Interfaces Library Avalon-MM FIFO Design Example 7–19 2. 1 The Quartus II software automatically specifies a top-level design entity that has the same name as the project. Double-click the Nios II Processor module in the System Contents tab to display the MegaWizard interface. Click Finish to add an on-chip RAM device with default parameters. b. refer to “Instantiating the Design in SOPC Builder” on page 7–12 in the “Avalon-MM Interface Blocks Design Example”. Click the System Contents tab in SOPC Builder and set the following options: a. Set the reset and exception vectors to use onchip_memory2_0 and click Finish to add the processor to your system with all other parameters set to their default values.tcl in the Project folder. On the File menu in the Quartus II software. a. 3. You can now design the rest of your NIOS embedded processor with the standard SOPC Builder design flow. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Specify the working directory for your project by browsing to <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\AvalonFIFO. 7. b. f For more detailed instructions. 4. c. Specify a name for your project. click SOPC Builder to display the Create New System dialog box. On the Tools menu. Specify AvalonFIFO as the system name. Click OK. Select VHDL for the target HDL. click Tcl Scripts and set the following options: a. b. Expand DSPBuilder Systems in the System Contents tab and double-click the sopc_edge_detector_interface module to include it in your Nios II system. Expand On-Chip and double-click On Chip Memory (RAM or ROM). 5. Expand Memories and Memory Controllers. Load your design by selecting sopc_edge_detector_add. 8. This tutorial uses FIFO for the project name. 6. Click Run. c. c. On the Tools menu. click New Project Wizard and set the following options: a. This tutorial assumes that the names are the same. Click Finish to create the Quartus II project.

Figure 7–12 shows the interaction that occurs between the source interface valid signal and the sink interface ready signal. The Avalon Interface Specifications define how to convey data between a source interface and a sink interface. On the fourth cycle. the source provides data and asserts valid even though the sink is not ready. Some modules have parallel input interfaces and other instances require serial input interfaces. The choice depends on the algorithm. You can configure the DSP Builder Avalon-ST Source and Avalon-ST Sink blocks with a ready latency of 0 or 1. This unit of data may consist of one or more symbols. and it holds that data until sink asserts ready. Avalon-ST Interface Timing for ready-latency=0 On cycle one. the source happens to provide data on the same cycle that the sink is ready to receive it and so the transfer occurs immediately. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . and throughput requirements. For the ready_latency = 0 mode. optimization technique. The specification also defines how the MegaCore functions may stall other blocks (backpressure) or regulate the rate at which you provide data with a feedback sideband signal. the data bus is not sampled. The interface indicates the integrity of the data by a feed forward signal. For example. The source waits until cycle two and the sink acknowledges that it samples the data by asserting ready. This section summarizes the features of the Avalon-ST interface. the sink is ready but because the source does not provide any valid data. Figure 7–12. The ready signal notifies the source interface that it has sampled the data on that clock cycle.7–20 Chapter 7: Using the Interfaces Library Avalon-ST Interface Avalon-ST Interface All DSP MegaCore functions in the DSP Builder MegaCore Functions library have interfaces that comply with the Avalon Interface Specifications. You can combine multiple MegaCore functions easily because they use a common interface. A beat is the transfer of one unit of data between a source and sink interface. when conveying an in-phase and quadrature component on the same clock cycle. The source interface provides valid data at the earliest time possible. ready. valid. On cycle three. so it can support modules that convey more than one piece of information on each valid cycle. The ready latency is the number of cycles that a source must wait after a sink asserts ready so that a data transfer is possible.

To describe the relationship between the input and the output interfaces of a MegaCore function. Two parameters describe the basic format of a packet: SymbolsPerBeat. Figure 7–13. each symbol is eight bits wide. The MegaCore functions have internal counters that count the samples in a packet so they know which channel a particular sample is associated with and synchronize appropriately with the start and end of packet signals. and PacketDescription. the in phase and quadrature components associated with three different channels convey between two MegaCore functions. Field names are case sensitive and white space is not permitted. The PacketDescription is a string description of the fields in the packet. Avalon-ST Packet Formats You can allocate the data associated with each channel a field in a packet. where a field name starts with a letter and may include the characters a-zA-Z0-9_. Channel2. Packetized Data Transfer The Avalon Interface Specifications also describe several mechanisms to support the transfer of data associated with multiple channels. Packet transfers require two additional signals that mark the start and the end of the packet. and Q. In Figure 7–13. Typical field names include Channel1.Chapter 7: Using the Interfaces Library Avalon-ST Interface 7–21 Figure 7–13 gives an example of a data transfer where two symbols are conveyed on each beat—an in phase symbol I and a quadrature symbol Q. Altera recommends that you achieve this mechanism with packet based transfers where each packet has a deterministic format and each channel is allocated a specific field (time slot in a packet). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . A basic PacketDescription is a comma-separated list of field names. you must define the packets associated with each interface. The SymbolsPerBeat parameter defines the number of symbols that DSP Builder presents in parallel on every valid cycle. In this example.

For an example of a design that uses Avalon-ST interfaces and the Packet Format Converter blocks. endofpacket. f For a complete description of the Avalon-ST interface. valid. DSP Builder aligns the packets on each output interface so that the startofpacket signal presents on the same clock cycle. refer to AN442: Tool Flow for Design of Digital IF for Wireless Systems. The appropriate control logic is automatically generated. refer to the Avalon Interface Specifications. The PFC performs data mapping on a packet by packet basis. which asserts to indicate a frame delineation error. and data signals. startofpacket. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . you can select the multipacket mapping option. empty. and the PFC can map fields from multiple input packets to multiple output packets. Generic Function Avalon-ST Packet Format Converter The packet format converter (PFC) is a flexible. The PFC takes packet data from one or more input interfaces. If each interface supports fixed-length packets.7–22 Chapter 7: Using the Interfaces Library Avalon-ST Interface Figure 7–14 shows an example of a generic function that has two input interfaces and performs a transformation on the two input streams. You can specify the input packet format and the desired output packet format. multipurpose component that transforms packets that are received from one function into a packet format that is supported by another function. so that there is exactly one input packet on each input interface for each output packet on each output interface. Each input interface has Avalon-ST ready. The interface limits the packet rate of the converter with the longest packet. Figure 7–14. When the PFC has multiple output interfaces. Each output interface has an additional error bit. and provides field reassignment in time and space to one or more output packet interfaces.

HDL Entity. The Signal Compiler block recognizes the HDL Import block as a black box and bypasses this block during the HDL translation. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Implicit Black Box Interface Use the HDL Import block to infer the implicit black-box interface. and Subsystem Builder blocks to specify the explicit black-box interface. Explicit Black-Box Interface Use the HDL Input. 1 To define imported VHDL use std_logic_1164 types. refer to the block description in the AltLab Library chapter of the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. write a wrapper that converts them to std_logic or std_logic_vector. There are two types of black-box interface in DSP Builder: implicit and explicit. You can also use a Subsystem Builder block to create a new subsystem and then automatically populate its ports using the specified HDL. The following sections show an example of importing an existing VHDL design into the DSP Builder environment with the HDL Import block. and Subsystem Builder blocks. Using Black Boxes for HDL Subsystems The Signal Compiler block converts subsystems with blocks from the DSP Builder block libraries into HDL code. HDL Import Design Example The HDL Import block provides an interface to import a HDL module into your DSP Builder design. Typically use the explicit black-box interface to encapsulate non-DSP Builder blocks from the main Simulink blocksets. and HDL Entity blocks prevents Signal Compiler from translating the subsystem into HDL. Using the HDL Input. require the Signal Compiler block to recognize them as black boxes so that the conversion process does not alter them. Non-DSP Builder blocks. HDL Entity. such as encapsulations of your own pre-existing HDL code. HDL Output.8. f For information about the HDL Import block. refer to the block descriptions in the AltLab Library chapter of the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. f For information about the HDL Input. If your design uses any other VHDL type definitions (such as arithmetic or numeric types). HDL Output. HDL Output.

Expand the Altera DSP Builder Blockset and select the AltLab library. On the File menu.vhd. In MATLAB. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . It is missing the main filter function. which implements an 8-tap low-pass FIR filter design. From the VHDL Black Box File dialog box. 5. Drag and drop a HDL Import block into your model.8–2 Chapter 8: Using Black Boxes for HDL Subsystems HDL Import Design Example Importing Existing HDL Files To import existing HDL files into a DSP Builder design. The fir_vhdl. 8. 7. 9. Double-click on the HDL Import block to bring up the DSP Builder HDL Import dialog box (Figure 8–1 on page 8–3). 6. then click on Open.vhd.mdl. and final_add.vhd. which you can import as HDL. follow these steps: 1. enable the Import HDL radio button and click on the Add button to select the HDL input files. Rename the file by clicking Save As on the File menu. click Open and select empty_MyFilter. select the files fir_vhdl. 3. change the current directory setting to: <DSP Builder install path>\DesignExamples\Tutorials\BlackBox\HDLImport 2. 4. Ensure that fir_vhdl is specified as the name of the top-level design entity. In the HDL Import dialog box. four_mult_add.mdl. Name your new MDL file MyFilter. This design file has some of the peripheral blocks instantiated including the input and output ports and source blocks that provide appropriate stimulus for simulation. Open the Simulink Library Browser.vhd file describes the top-level entity.

Figure 8–1. Turn on the option to Sort top-level ports by name. click Compile to generate a Simulink simulation model for the imported HDL design. HDL Import Dialog Box © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .Chapter 8: Using Black Boxes for HDL Subsystems HDL Import Design Example 8–3 10. Under Generate Simulink Model. 11.

8–4 Chapter 8: Using Black Boxes for HDL Subsystems HDL Import Design Example 12. Click Start on the Simulation menu in your model window. 4. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . The code generated for the HDL Import block automatically converts to a black box. Figure 8–2. The HDL Import block in the MyFilter. Figure 8–3 on page 8–5 shows the simulation results. Double-click on the Scope block to view the simulation results. Progress messages issue in the HDL Import dialog box ending with the message: Quartus II Analysis & Synthesis was successful.mdl file. Click the Zoom X-axis icon and drag the cursor to zoom in on the first 70 X-axis time units. which verifies the impulse response of the low-pass filter. 2. Simulating the HDL Import Model using Simulink Follow these steps to run simulation in Simulink: 1. Completed Design 16.mdl model updates to show the ports defined in the imported HDL. 13. 5. 3. 14. This toggles the switch and sets the impulse_in stimulus. Double-click on the manual switch connected to the Tsamp block which feeds into the fir_data_in input port. Click Save on the File menu to save the MyFilter. Click the Autoscale icon to resize the scope. This scales both axes to display all stored simulation data until the end of the simulation (which is set to 500*Tsamp for this model). Click OK to close the HDL Import dialog box. Connect the input and output ports to the symbol (Figure 8–2). 15.

Double-click on the Scope block to view the simulation results. Double-click on the manual switch connected to the Tsamp block to select the chirp_in stimulus—a sinusoidal signal the frequency of which increases at a linear rate with time. Figure 8–4 shows the simulation results. Click Start on the Simulation menu in your model window. 9. Simulink Simulation Results for the Impulse Stimulus 6. 8. 7. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .Chapter 8: Using Black Boxes for HDL Subsystems HDL Import Design Example 8–5 Figure 8–3. Press the Autoscale icon to resize the scope. Figure 8–4. Simulink Simulation Results for the Chirp Stimulus The HDL import tutorial is complete. You can optionally compile your model for synthesis or perform RTL simulation on your design by following similar procedures to those described in the “Getting Started”.

refer to the block description in the AltLab Library chapter in the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. f For more information about the Subsystem Builder block.8–6 Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example Subsystem Builder Design Example The Subsystem Builder block makes it easy for you to import the input and output signals for a VHDL or Verilog HDL design into a Simulink subsystem. follow these steps: 1. Select the filter8tap. change the current directory to: <DSP Builder install path> \DesignExamples\Tutorials\BlackBox\SubSystemBuilder 2. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Creating a Black Box System To create a black-box system. In addition to porting the HDL design to a Simulink subsystem. Click Open on the File menu. The Subsystem Builder block also allows you to create your own Simulink simulation model from non-DSP Builder blocks for faster simulation speed. The following section shows an example that uses an S-function to describe the simulation models of the HDL code. the Subsystem Builder block does not create a Simulink simulation model for the imported HDL design.mdl file and click OK. 3. Unlike the HDL Import block. In MATLAB. If your HDL design contains any LPM or megafunctions that the HDL Import block does not support. 4. you must create the Simulink simulation model for the block. The following options are available to create Simulink simulation models: ■ ■ ■ ■ ■ Simulink generic library Simulink blocksets (such as the DSP and Communications blocksets) DSP Builder blockset MATLAB functions S-functions 1 You must add a Non-synthesizable Input block and a Non-synthesizable Output block around any DSP Builder blocks in the subsystem. Open the Simulink Library Browser and expand the AltLab library under the Altera DSP Builder blockset. use the Subsystem Builder block. Drag a Subsystem Builder block into your model. The simulation models describes the functionality of the particular HDL subsystem.

browse for the fir_vhdl. 7. In the dialog box. The Subsystem Builder dialog box automatically closes. filter8tap Design © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .vhd file and click Build. Connect the ports (Figure 8–6). The Subsystem Builder dialog box displays (Figure 8–5). Figure 8–5. Double-click the Subsystem Builder block.Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example 8–7 5. Subsystem Builder Dialog Box 6. Figure 8–6.mdl model. This action builds the subsystem and adds the signals for the fir_vhdl subsystem to the symbol in your filter8tap.

Click the Edit button to view the code that describes the S-Function. In the Simulink Library Browser. you build the simulation model that represents the functionality of this block in your Simulink simulations. From the User-Defined Functions library. In the Block Parameters dialog box. Library: filter8tap/fir_vhdl Window The subsystem contains two HDL Input blocks (simulink_sclr and data_in) and a HDL Output block (data_out). The first parameter refers to the sampling rate (-1 indicates it inherits the sampling rate from the preceding block) and the rest of the parameters represent the eight filter coefficients. The Sfir8tap function is a C++ Simulink S-Function simulation model for the 8-tap Fir filter block. 9. Double-click on the fir_vhdl symbol. 1 Leave the S-function modules parameter with its default value. 2. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . drag and drop a S-Function block into your model window. Double-click the S-Function block to display the Function Block Parameters: S-Function dialog box. 3. DSP Builder also creates a HDL Entity block to store the name of the HDL file and the names of the clock and reset ports. Each of these blocks in turn connects to a subsystem input or output. Leave your model window open for use in the next section. The filter8tap/fir_vhdl subsystem opens (Figure 8–7). 4. follow these steps: 1. 1 The clock is handled implicitly and no port is explicitly created in the subsystem. 5. change the S-Function name to Sfir8tap and enter the parameters -1 3962 4817 5420 5733 5733 5420 4817 3962.8–8 Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example 8. you use a S-function C++ simulation model to represent the 8-tap FIR filter block. In the next section. expand the Simulink folder. Figure 8–7. Building the Black-Box SubSystem Simulation Model For this example. To create your model.

0). 6. etc. /* Number of expected parameters */ if (ssGetNumSFcnParams(S) != ssGetSFcnParamsCount(S)) { /* Return if number of expected != number of actual parameters */ return. states. SS_DOUBLE).p<iMaxssGetSFcnParamsCount. SS_DOUBLE). 1)) return. 1)) return. 0). 1). Scroll down in the Sfir8tap. 0). 0. ssSetInputPortWidth(S. ssSetNumSampleTimes(S. */ static void mdlInitializeSizes(SimStruct *S) { /* See sfuntmpl. // reserve element in the ssSetNumModes(S. 0). click Browse and select the Sfir8tap. 0. 9). ssSetNumDiscStates(S. } if (!ssSetNumInputPorts(S.CPP file. ssSetInputPortDataType(S. ssSetNumIWork(S. ssSetNumContStates(S. 1). } // Set DialogParameters not tunable const int iMaxssGetSFcnParamsCount = ssGetSFcnParamsCount(S).doc for more details on the macros below */ ssSetNumSFcnParams(S. ssSetOutputPortDataType(S. outputs. DYNAMICALLY_SIZED). // pointers vector to store a C++ object © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example 8–9 1 If the code does not appear automatically. ssSetNumRWork(S.p++) { ssSetSFcnParamTunable(S.). The following code shows the Simulink C++ S-Mex function code that designs a Simulink filter simulation model: /*====================* * S-function methods * *====================*/ /* Function: mdlInitializeSizes======================================= * Abstract: * The sizes information is used by Simulink to determine the S-function * block's characteristics (number of inputs. p. 1).CPP file to the S-function methods section. 0. if (!ssSetNumOutputPorts(S. 0). for (int p=0. 1). 0. ssSetNumDWork(S. ssSetOutputPortWidth(S.

type: mex Sfir8tap. Initialize the vectors of this S-function. Table 8–1 shows the design example callback methods.mdl file. Close the editor window and click on OK to close the Function Block Parameters dialog box. mdlInitializeSampleTimes Specify the sample rates at which this S-function operates. 2. Update the states of the block.8–10 Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example ssSetNumNonsampledZCs(S. 0). and calculate output. 0). The extension is specific to 32-bit version of MATLAB run in Windows. ssSetOptions(S.CPP r The mex command compiles and links the source file into a shared library executable in MATLAB. and connect the output port of the S-function block to the data_out block (Figure 8–8). Click Save on the File menu to save the filter8tap. } During simulation. Simulink invokes certain callback methods from the S-function. and any input ports named simulink_sclr to the global synchronous clear signal.mexw32. Table 8–1. The HDL Entity block automatically maps any input ports named simulink_clock in the VHDL entity to the global clock signal. update discrete states. In the filter8tap/fir_vhdl window. and other characteristics of the S-function. 4. parameters. mdlStart mdlOutputs mdlUpdate mdlTerminate 1. S-Function Block Connection 1 You do not need to connect the simulink_sclr block. Compute the signals that this block emits. outputs. Figure 8–8. Perform any actions required at termination of simulation. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . connect the input port of the S-function block to the data_in block. S-Function Callback Methods Callback Method mdlInitializeSizes Description Specify the number of inputs. At the MATLAB command prompt. 3. states. The callback methods are subfunctions that initialize. Sfir8tap.

2. Click Autoscale to resize the scope. This action creates a DSPBuilder_filter8tap_import directory in the directory containing your design. Ignore the result for now. Click Start on the Simulation menu in the filter8tap.tcl when it compiles your design testbench. which translates to the eight coefficient values. Simulink Simulation Results of 8-Tap FIR Filter. You can change the input stimulus to verify the step and random response of the filter. 2. Figure 8–9 shows the simulation results.tcl compiles them in ModelSim when your design is run using the TestBench block.vhd to the Quartus II project. Click the Zoom X-axis icon and use the cursor to zoom in on the first 22 x-axis time units. Double-click on the Signal Compiler block and click Compile. Copy the extra_add. Scope Window 1 Because the input is a pulse. and compilation either fails or gives unexpected results. The extra_add.Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example 8–11 Simulating the Subsystem Builder Model To run the Simulink simulation. Double-click the Scope block to view the simulation results. Figure 8–9. while extra_add_msim. 1 Alternatively.vhd and four_mult_add. 3. The Quartus II software executes any files ending with _add.tcl when it creates the project. follow these steps: 1.tcl file adds final_add. ModelSim executes files ending with _add_msim. the simulation results show the impulse response of the 8-tap FIR filter. Adding VHDL Dependencies to the Quartus II Project and ModelSim The VHDL file is dependent on two other VHDL files.tcl and extra_add_msim.mdl window to begin the simulation. To resolve this issue. The Quartus II software or ModelSim do not examine these two files. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .tcl files from the original design directory to the DSPBuilder_filter8tap_import directory. follow these steps: 1. you can create the directory DSPBuilder_filter8tap_import directly.

When the comparison completes successfully an Exact Match message issues in the TestBench Generator dialog box. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . You can optionally compile your model for synthesis (“Getting Started”). 2. This completes the Subsystem Builder tutorial. Double-click on the TestBench block and click Compare against HDL. Drag a TestBench block into your model. click on the Advanced tab.8–12 Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example Simulate the Design in ModelSim To test the simulation model against the HDL in ModelSim. follow these steps: 1. In the Simulink Library Browser. 3. expand AltLab library under Altera DSP Builder Blockset. and then click Run ModelSim. turn on the Launch GUI option. 1 If you want to use ModelSim directly.

(Figure 9–1). <DSP Builder install path>\ DesignExamples\Tutorials\BuildingCustomLibrary\top. Defining Parameters Using the Mask Editor 4.mdl defines it. Adding the Library to the Simulink Library Browser © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Creating a Library Model File 2. follow these steps: 1. This design flow also supports parameterizable hierarchical subsystem structures. The RamBasedDelay block has one parameter. top. Building the HDL Subsystem Functionality 3.9.mdl uses. Using Custom Library Blocks A parameterizable custom library block is a Simulink subsystem in which DSP Builder primitives describe the block functionality. Altera provides an example of a custom library block. Delay. Figure 9–1. is an example of a custom parameterizable Simulink block. Creating a Custom Library Block To create your own custom block. The library file MyLib. Linking the Mask Parameters to the Block Parameters 5.mdl Example The RamBasedDelay block that top.mdl. Making the Library Block Read Only 6.

Drag and drop a Shift Taps block from the Storage library in the Altera DSP Builder Blockset into your model window. Parameters for the Shift Taps Block Parameter Main Tab Number Of Taps Distance Between Taps Optional Ports and Settings Tab Use Shift Out Port Use Enable port: Use Dedicated Circuitry Memory Block Type Off On On Auto 1 10 Value DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Shift Taps Block 3. Double-click on the DelayFIFO block to open the NewLib/DelayFIFO subsystem window. change the current directory setting to: <DSP Builder install path>\DesignExamples\Tutorials\BuildingCustomLibrary. Double-click the Shift Taps block to open the Block Parameters dialog box.mdl. follow these steps: 1. follow these steps: 1. Insert the Shift Taps block between the input and output blocks (Figure 9–2). Click on the Subsystem text below the block and rename the block DelayFIFO. Building the HDL Subsystem Functionality To add functionality to the DelayFIFO block. Expand the Simulink Ports & Subsystems library in the Simulink Library Browser and drag a Subsystem block into your model. 1 You should always rename a block representing an HDL Subsystem to ensure that all the generated entities in a hierarchical design are unique. Figure 9–2. Open the Simulink Library Browser. In MATLAB. On the File menu in the Simulink Library Browser. 2. 4. Table 9–1 shows the parameters to set. Click Save on the File menu and save the library file as NewLib.9–2 Chapter 9: Using Custom Library Blocks Creating a Custom Library Block Creating a Library Model File To create a Library Model File for your custom block. 5. Table 9–1. 2. point to New and click Library to open a new library model window. 3.

Figure 9–3 shows the completed DelayFIFO subsystem. In the Mask Editor dialog box set the parameters (Table 9–3 on page 9–4). Table 9–2. 5. NewLib Model Defining Parameters Using the Mask Editor Use the Mask Editor to create parameters for the DelayFIFO block by following these steps: 1. Figure 9–4. Add an Input block (In2) from the Simulink Ports & Subsystems library and connect it to the ena port on the Shift Taps block. Rename the blocks (Table 9–2).Chapter 9: Using Custom Library Blocks Creating a Custom Library Block 9–3 4. Renaming the Blocks Old Name In1 In2 Shift Taps Out1 InDin InEna DRB OutDout New Name 7. Click OK to close the Block Parameters dialog box. Click Save on the File menu. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 2. DelayFIFO Subsystem Figure 9–4 shows the NewLib library model that now shows the input and output ports defined in the DelayFIFO subsystem. Figure 9–3. Right-click the DelayFIFO block in the NewLib model and click Mask Subsystem on the pop-up menu. 6.

'din').1. f For more information about the Mask Editor.1. Linking the Mask Parameters to the Block Parameters To pass parameters from the symbol’s mask into the block. 4. by following these steps: 1. port_label('input'. Making the Library Block Read Only Make a library block read only so that you do not accidentally edit it in a design model. follow these steps: DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .9–4 Chapter 9: Using Custom Library Blocks Creating a Custom Library Block Table 9–3. 5.d) Value Parameters Tab Prompt Variable Documentation Tab Mask type Mask description SubSystem AlteraBlockSet RAM-Based Delay Element Altera Corporation Delay d 3. 4. Click OK in the Block Parameters dialog box. use a model workspace variable.2. Copy the mask parameter variable name d from the Parameters tab of the Mask Editor into the Distance Between Taps field in the Block Parameters dialog box.'ena'). Close your model window. fprintf('Delay %d'. 3. port_label('output'. 7. Double-click the DRB block in the NewLib/DelayFIFO window to open the Block Parameters dialog box. 2. Click OK to close the Shift Taps Block Parameters dialog box. To set the read and write permissions.'dout'). Click Save on the File menu to save your library model. Parameters for the Mask Editor Parameter Icon Tab Frame Transparency Rotation Units Drawing Commands Visible Opaque Fixed Autoscale port_label('input'. refer to the MATLAB Help. Specify a Delay of 5. 6. Double-click on the DelayFIFO block in your NewLib model to display the Block Parameters dialog box. Click OK in the Mask Editor dialog box.

% End of slblocks 3. Click Save on the File menu to save your library model. 4.MaskDisplay = ''. Browser(1). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . 2.Name = 'Custom Library DSP Builder'. Click OK to close the Block Parameters dialog box.Browser = Browser.IsFlat = 0. follow these steps: 1.OpenFcn = 'NewLib'. 3. 1 The ReadWrite option allows edits from both the library and the design.m file. If you want to modify a library model. Enter the following text in the editor window: function blkStruct = slblocks blkStruct. the first % element contains the information for the Simulink % block library and the second for the Simulink % Extras block library. Remember to reset ReadOnly after changing the library model. blkStruct. % Define the Browser structure array.Library = 'NewLib'. To create this file. blkStruct. click Unlock Library on the File menu and change the read and write permissions in the Block Parameters dialog box. The NoReadOrWrite option does not allow Signal Compiler to generate HDL for the design.m in the same directory as NewLib. 2. In the Read/Write permissions list. open your model. select ReadOnly. Browser(1).mdl. Save the M-file with the file name slblocks. Your changes are automatically propagated to all instances in your design. blkStruct. Browser(1). The next time that you display the Simulink library browser the custom library is available (Figure 9–5). point to New and click M-File to open a new editor window. This file must be in the same location as your library file and both files must be in search path for MATLAB.Name = ['Custom Library DSP Builder']. Adding the Library to the Simulink Library Browser You can add a custom library to the Simulink library browser by creating a slblocks. Right-click the DelayFIFO block in the NewLib model and click SubSystem Parameters on the pop-up menu to display the Block Parameters dialog box. On the File menu in MATLAB.Chapter 9: Using Custom Library Blocks Creating a Custom Library Block 9–5 1.

You can create a custom library with multiple blocks by creating the required blocks in the same library file.m file with explanatory comments is at <MATLAB install path>\toolbox\ simulink\blocks\slblocks. If you move or copy your design. Custom Library in the Simulink Library Browser You can drag and drop a block from your custom library in the same way as from any other library in the Simulink library browser. A template slblocks. Synchronizing a Custom Library A custom library can contain MegaCore functions. f For more information about M-files. refer to the MATLAB Help.m. or state machine editor blocks.9–6 Chapter 9: Using Custom Library Blocks Synchronizing a Custom Library Figure 9–5. HDL import. synchronize your model containing these blocks by using the following command: alt_dspbuilder_refresh_user_library_blocks 1 This command calls automatically when you use either of the commands: alt_dspbuilder_refresh_hdlimport or alt_dspbuilder_refresh_megacore DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Adding a Board Library This chapter describes how to create and build a custom board library to use inside DSP Builder using built-in board components.10.component. This board description file contains all the board components and their FPGA pin assignments. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . <component_name>. This file defines its data type. You can use the existing components or create your own custom components. and selectable single bit. fixed size bus. that describes each separate board component. Each board library is defined by a XML board description file. direction. refer to the DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder Handbook. Component Types There are three main types of component: single bit. Predefined Components Predefined components are in the following folder: <install dir>\quartus\dsp_builder\lib\boardsupport\components There is a single XML file. Creating a New Board Description To add additional boards create new board description files. DSP Builder supports the following development boards: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Cyclone II DE2 Starter board Cyclone II EP2C35 board Cyclone II EP2C70 board Cyclone III EP3C25 Starter board Cyclone III EP3C120 board Stratix EP1S25 board Stratix EP1S80 board Stratix II EP2S60 board Stratix II EP2S180 board Stratix II EP2SGX90 PCI Express board Stratix III EP3SL150 board f For information about these boards. You only need to create a board description file for each new board and run a MATLAB command to build it into a DSP Builder Library. and appearance. The file also contains a brief description of the component. bus width.

The components are either inputs or outputs and you cannot change them. PROTO1 to PROTO3) Evaluation input pin (EvalIoIn) Evaluation output pin (EvalIoOut) Component Description File To define a new component create a corresponding component file.10–2 Chapter 10: Adding a Board Library Creating a New Board Description Single Bit Type These components have a single bit with one FPGA pin assigned to each component. DSP Builder offers the following fixed-size bus type predefined components: ■ ■ ■ ■ ■ 12-bit analog-to-digital converter (A2D1Bit12 and A2D2Bit12) 14-bit analog-to-digital converter (A2D1Bit14 and A2D2Bit14) 14-bit digital-to-analog converter (D2A1 and D2A2) 8-bit dual in-line package switch (DipSwitch) 7-Segment display with a decimal point (SevenSegmentDisplay0 to SevenSegmentDisplay1) Simple 7-Segment display without a decimal point (Simple7SegmentDisplay0 to Simple7SegmentDisplay7) ■ Selectable Single Bit Type These components have a single bit. in the same folder as the predefined components. the pin can be set as either input or output. <component_name>. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Furthermore. The component has the following attributes: ■ displayname= Specifies the name of the component. you can select the pin from a group of predefined FPGA pins. DSP Builder offers the following single-bit predefined components: ■ ■ ■ ■ ■ Red and Green LEDs (LED0 to LED17 and LEDG0 to LEDG8) Software switches (SW0 to SW17) User push buttons (PB0 to PB3) Reset push buttons (IO_DEV_CLRn and USER_RESETN) RS232 receive output and RS232 transmit input pins (RS232Rout and RS232Tin) Fixed-Size Bus Type These components have a fixed-sized group of same type (either input or output) pins with one FPGA pin assigned to each bit of the bus. DSP Builder offers the following selectable single-bit predefined components: ■ ■ ■ ■ Debug pins (DebugA and DebugB) Prototyping pins (PROTO. which the board description file references. The component description file contains a root element component that contains several attributes and subelements that define the component.component.

[0 0 1 0 0 0 -1 0]).0]" is a 12-bit unsigned integer. You can omit this attribute for the Selectable Single Bit Type. </display> Example Component Description File The following code shows an example of a component description file: <component displayname="EVAL IO OUT" direction="Output" type="BIT[1. It can have the value of Input or Output.[0 0 1 0 0 0 -1 0]).0]" defines a single bit while "UINT[12.Chapter 10: Adding a Board Library Creating a New Board Description 10–3 ■ direction= Specifies the direction of the signal. ■ The component subelements have the following definitions: ■ <documentation> text </documentation> This subelement contains text describing the component and one of the following variable that define how the pin name. or UINT. you can omit the icon display attribute and define a visual representation using the plot and fprintf commands. INT. </display> </component> © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . "BIT[1. fprintf('EVAL IO OUT \n%pinname% '). or list of pin-names appears in the new board library: ■ ■ ■ %pinname% for single bit type %pinlist% for selectable single bit type %indexedpinliat% for fixed size bus type ■ <display [attributes]> This subelement has the following attributes: ■ ■ ■ icon= specifies the image file name for the component width= specifies the display width for the image file height= specifies the display height for the image file 1 For components without an image. For example: <display width="90" height="26"> plot([0 19 20 21 22 21 20 19]. fprintf('EVAL IO OUT \n%pinname% '). type= Specifies the data type of the signal. followed by the size in square brackets. The type can be BIT.0]"> <documentation> Prototyping Area Pin Single Bit Output %pinlist% </documentation> <display width="90" height="26"> plot([0 19 20 21 22 21 20 19]. For example. because it is set later.

. Header Section This section contains the following line that defines the XML version and character encoding: <?xml version="1...board. the document conforms to the 1... family= Device family of the FPGA on board (assuming only one device is on the board)..10–4 Chapter 10: Adding a Board Library Creating a New Board Description Board Description File Create the board description file. in the following folder: <install dir>\quartus\dsp_builder\lib\boardsupport\boards The board description file has header and board description sections... The board must contain a displayname subelement containing text that describes the board. The board attributes have the following definitions: ■ ■ uniquename= A unique name to reference the board. For example: <displayname>Cyclone II XYZ Board</displayname> The following component subelements declare the components: ■ Single bit type examples: <component name="LED0" pin="Pin_E5"/> DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . <board_name>.. Board Description Section The main body of the document is a root element board that has several attributes and subelements that define the details of the board.0" encoding="UTF-8"?> In this case. You should not modify this line.0 specification of XML and uses the ISO-8859-1 (Latin-1/West European) character set.. <component Attributes /> <configuration Attributes> <devices> Attributes> </devices> <option Attributes> </option> </configuration> </board> 1 The last line in the file must be a closing tag for the root element board </board>. <board Attributes> <displayname> Text </displayname> <component Attributes /> .

Chapter 10: Adding a Board Library Creating a New Board Description 10–5 <component name="LED1" pin="Pin_B3"/> where attribute name defines the name of the component on the board and pin defines the FPGA pin to which the component is connected. The configuration element defines the board configuration block.MSB--> </component> where attribute name defines the name of the component on the board and label defines the name of the component as it appears in Simulink.LSB --> <pin location="Pin_A19"/> <pin location="Pin_C21"/> <pin location="Pin_C23"/> <pin location="Pin_AE18"/> <pin location="Pin_AE19"/> <!-. For example: <configuration icon="dspboard2c35. The pin location must be a valid FPGA pin name. with LSB on top of the list. ■ Selectable single bit type example: <component name="PROTO1"> <pin location="Pin_C3"/> <pin location="Pin_D2"/> <pin location="Pin_L3"/> <pin location="Pin_J7"/> <pin location="Pin_J6"/> <pin location="Pin_K6"/> </component> This element has the same format as the fixed-size bus type. For a component with width n. but you can choose each pin element from a specified list of available FPGA pin locations.Input clock selection list --> <option name="ClockPinIn" label="Clock Pin In"> <pin location="Pin_N2"/> <pin location="Pin_N25"/> <pin location="Pin_AE14"/> <pin location="Pin_AF14"/> <pin location="None"/> © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . The pin ordering is listed from LSB to MSB. ■ Fixed-size bus type example: <component name="DipSwitch" label="S1"> <pin location="Pin_AC13"/> <!-. there must be n pin subelements.bmp" width="166" height="144"> <devices jtag-code="0x020B40DD"> <device name="EP2C35F672C6" /> </devices> <!-. The name must match one of the predefined components and you can use it only once per board.

10–6 Chapter 10: Adding a Board Library Building the Board Library </option> <!-. Building the Board Library Restart MATLAB without opening the Simulink library and run the following command in the MATLAB command window to create the new board library: alt_dspbuilder_createComponentLibrary DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .Global Reset Pin --> <option name="GlobalResetPin" label="Global Reset Pin"> <pin location="Pin_A14"/> <pin location="Pin_AC18"/> <pin location="Pin_AE16"/> <pin location="Pin_AE22"/> <pin location="None"/> </option> </configuration> The configuration attributes have the following definitions: ■ ■ ■ icon = the image file to be used for the board configuration block width = the width of the image height = the height of the image The devices subelement has the following attributes: ■ ■ jtag-code = the JTAG code of the FPGA device device name = the device name of the FPGA used on the board Each option subelement has the following attributes: ■ ■ ■ name = the name of the option (clock or reset pin) label = labels that identifies the pins on the blocks pin location = a list of selectable clock or reset pins f For more examples. refer to any of the existing board description files.

Figure 11–1 shows the top-level schematic for the FIFO design example.mdl. When the address counter is equal to 0. FIFO Design Example Top-Level Schematic The state machine in this design example feeds the control inputs of a Dual-Port RAM block and the inputs of an address counter. Using the State Machine Library This chapter describes how to implement a state machine in DSP Builder. The state machine has the following operation: ■ When you assert the push input and the address counter is less than 250. 1 The State Machine Table block is not available on Linux and is deprecated on Windows. the empty flag asserts When the address counter is equal to 250. the address counter increments and a byte of data writes to memory. When you assert the pop input and the address counter is greater than 0. the full flag asserts. the address counter decrements and a byte of data reads from memory. The design example. Use the State Machine Editor block in new designs. The design files for this example are in the <DSP Builder install path>\ DesignExamples\Tutorials\StateMachine\StateMachineTable directory.11. Figure 11–1. ■ ■ ■ © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . fifo_control_logic. contains a simple state machine to implement the control logic for a first-in first-out (FIFO) memory structure.

In3. and delete state names. You cannot delete or change the reset input. follow these steps: 1. Double-click the fifo_controller block to define the state machine properties. You cannot delete or change the name of a state while it is selected as the reset state. Delete the default input names In2. and delete input names. the block is named fifo_controller. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . change. The States tab also allows you to select the reset state for your state machine. The States tab displays the state names defined for your state machine and provides an interface to allow you to add. Add a State Machine Table block to your Simulink design and assign it a new name. Click the States tab. fifo_controller State Machine Table Block 1 You must save you model and change the default name of the State Machine Table block before you define the state machine properties.11–2 Chapter 11: Using the State Machine Library Using the State Machine Table Block Using the State Machine Table Block To use the State Machine Table block. 2. The Inputs tab displays the input names defined for your state machine and provides an interface to allow you to add. 3. and In5 and enter the following new input names: ■ ■ ■ count_in pop push You can add or delete inputs but you cannot change an existing input name directly. to create the FIFO controller in the design example. The State Machine Builder dialog box appears with the Inputs tab selected. In4. The reset state is the state to which the state machine transitions when you assert the reset input. 1 4. In this example. Figure 11–2 shows the default State Machine Table block. Figure 11–2. 1 You must define at least two states for the state machine.

click the Conditional Statements tab and use it to describe the behavior of your state machine by adding the statements (Table 11–1). After specifying the input and state names. S3. Change. and the next state to which the state machine transitions. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . FIFO Controller Conditional Statements Current State empty empty full full idle idle idle idle pop_not_empty pop_not_empty pop_not_empty pop_not_empty pop_not_empty push_not_full push_not_full push_not_full push_not_full push_not_full Condition (push=1)&(count_in!=250) (push=0)&(pop=0) (push=0)&(pop=0) (pop=1) (pop=1)&(count_in=0) (push=1) (pop=1)&(count_in!=0) (push=1)&(count_in=250) (push=0)&(pop=0) (pop=1)&(count_in=0) (push=1)&(count_in!=250) (pop=1)&(count_in!=0) (push=1)&(count_in=250) (push=0)&(pop=0) (pop=1)&(count_in=0) (push=1)&(count_in!=250) (push=1)&(count_in=250) (pop=1)&(count_in!=0) idle idle pop_not_empty empty push_not_full pop_not_empty full idle empty push_not_full pop_not_empty full idle empty push_not_full full pop_not_empty Next State push_not_full The Conditional Statements tab displays the state transition table. Table 11–1. S4. which you can select from a list in the dialog box. Use the Add. a condition that causes a transition to take place.Chapter 11: Using the State Machine Library Using the State Machine Table Block 11–3 5. and S5 with the following states: ■ ■ ■ ■ ■ empty (reset state) full idle pop_not_empty push_not_full 6. 1 There must be at least one conditional statement defined in the Conditional Statements tab. The current state and next state values must be state names defined in the States tab. which contains the conditional statements that define your state machine. A conditional statement consists of a current state. and Delete buttons to replace the default states S1. S2.

specify the conditional expression to be one. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . The priority of the conditional operator determines the priority if the condition contain only one operator. Table 11–2 shows the conditional operators you can use to define a conditional expression. it may need to evaluate more than one condition to determine the next state to which it transitions. Figure 11–3. Figure 11–3 shows the Conditional Statements tab. State Machine Builder Conditional Statements Tab When a state machine is in a particular state.11–4 Chapter 11: Using the State Machine Library Using the State Machine Table Block 1 To indicate in a conditional statement that a state machine always transitions from the current state to the next state. after defining the conditional statements for the FIFO controller.

Use the Move Up and Move Down buttons to change the order of the conditional statements (Table 11–4).. Table 11–3.Chapter 11: Using the State Machine Library Using the State Machine Table Block 11–5 Table 11–2. Table 11–3 shows the conditional statements when the current state is idle. therefore it has higher priority. The condition (pop=1)&(count_in!=0) has the next highest priority and the condition (push=1)&(count_in=250) has the lowest priority. Idle State Condition Priority Current State idle idle idle idle push=1 (pop=1)&(count_in!=0) (push=1)&(count_in=250) Condition (pop=1)&(count_in=0) empty push_not_full pop_not_empty full Next State 1. Table 11–4. Idle State Condition Priority (Reordered) Current State idle idle idle idle Condition (pop=1)&(count_in=0) (push=1)&(count_in=250) (pop=1)&(count_in!=0) push=1 empty full pop_not_empty push_not_full Next State © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Comparison Operators Supported in Conditional Expressions Operator .) = != > >= < <= & | Description Negative Brackets Numeric equality Not equal to Greater than Greater than or equal to Less than Less than or equal to AND OR 1 1 2 2 2 2 2 2 2 2 Priority -1 (1) in1=5 in1!=5 in1>in2 in1>=in2 in1<in2 in1<=in2 (in1=in2)&(in3>=4) (in1=in2)|(in1>in2) Example If the conditions contain multiple operators.. they are evaluated in the order that you list them in the conditional statements table.(unary) (. The condition (pop=1)&(count_in=0) is higher in the table than the condition (push=1)&(count_in=250).

To save the changes made to your state machine. an error message. fifo_controller Block After Closing the State Machine Table DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Click the Design Rule Check tab. Click Analyze to evaluate the design rules for your state machine. highlighted in red.11–6 Chapter 11: Using the State Machine Library Using the State Machine Table Block 2. Figure 11–5. If a design rule is violated. Figure 11–5 shows the updated fifo_controller block. You can use this tab to verify that the state machine you defined in the previous steps does not violate any of the design rules. The design file automatically updates with the input and output names defined in the previous steps. Figure 11–4 shows the Design Rule Check tab after clicking Analyze. is listed in the Analysis Results box. State Machine Builder Design Rule Check Tab 3. 1 You may need to resize the block to ensure that the input and state names do not overlap and display correctly. fix the errors and rerun the analysis until no error messages appear before simulating and generating VHDL for your design. Figure 11–4. If error messages appear in the analysis results. The State Machine Builder dialog box closes and returns you to your Simulink design file. click OK.

follow these steps: 1. On the Tools menu in the Quartus II State Machine Editor. Figure 11–7. Figure 11–6. Add a State Machine Editor block to your Simulink design and assign it a new name. 2. In this example. Double-click the fifo_controller block to open the State Machine Editor in the Quartus II software (Figure 11–7).Chapter 11: Using the State Machine Library Using the State Machine Editor Block 11–7 Using the State Machine Editor Block To use the State Machine Editor block to create the FIFO controller in the design example. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . the block is named fifo_controller. Quartus II State Machine Editor Window 3. point to State Machine Wizard and click Create a new state machine design. Figure 11–6 shows the default State Machine Editor block. fifo_controller State Machine Editor Block 1 You should save you model and change the default name of the State Machine Editor block before you define the state machine properties.

Edit the state transitions by entering the statements (Table 11–1).11–8 Chapter 11: Using the State Machine Library Using the State Machine Editor Block 4. Delete the default state names (state1. 1 7. The count_in port must be defined as an 8-bit vector to allow count values up to 250. The first page of the wizard allows you to choose the reset mode. FIFO Controller Transitions Source State empty empty full full idle idle idle idle pop_not_empty pop_not_empty pop_not_empty pop_not_empty pop_not_empty push_not_full push_not_full push_not_full push_not_full push_not_full idle idle pop_not_empty empty push_not_full pop_not_empty full idle empty push_not_full pop_not_empty full idle empty push_not_full full pop_not_empty Destination State push_not_full Condition (push==1)&(count_in!=250) (push==0)&(pop==0) (push==0)&(pop==0) (pop==1) (pop==1)&(count_in==0) (push==1) (pop==1)&(count_in!=0) (push==1)&(count_in==250) (push==0)&(pop==0) (pop==1)&(count_in==0) (push==1)&(count_in!=250) (pop==1)&(count_in!=0) (push==1)&(count_in==250) (push==0)&(pop==0) (pop==1)&(count_in==0) (push==1)&(count_in!=250) (push==1)&(count_in==250) (pop==1)&(count_in!=0) DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . 5. active-high. Accept the default values (synchronous. whether the reset is active-high or active-low. Table 11–5. Delete the default input port names (input1. and whether the outputs are registered. input2) and type the following new input port names: ■ ■ ■ count_in[7:0] pop push Do not change the clock and reset port names. state2. registered outputs) and click Next to display the Transitions page of the wizard. state3) and type the following new state names: ■ ■ ■ ■ ■ empty full idle pop_not_empty push_not_full 6.

Click Next to display the Actions page. State Machine Editor Wizard Transitions Page 8. Delete the default output port name (output1) and enter the following new output port names: ■ ■ ■ ■ ■ out_empty out_full out_idle out_pop_not_empty out_push_not_full © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Figure 11–8. Figure 11–8 shows the Transitions page after you define the states.Chapter 11: Using the State Machine Library Using the State Machine Editor Block 11–9 1 The transitions are validated on entry and must conform with Verilog HDL syntax. and transitions. inputs.

FIFO Controller Output Actions Output Port out_empty out_full out_idle out_pop_not_empty out_push_not_full out_empty out_empty out_empty out_empty out_full out_full out_full out_full out_idle out_idle out_idle out_idle out_pop_not_empty out_pop_not_empty out_pop_not_empty out_pop_not_empty out_push_not_full out_push_not_full out_push_not_full out_push_not_full 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Output Value empty full idle pop_not_empty push_not_full full idle pop_not_empty push_not_full empty idle pop_not_empty push_not_full empty full pop_not_empty push_not_full empty full idle push_not_full empty full idle pop_not_empty In State DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Specify the output logic for each output port by specifying the action conditions to set each output port to 1 when the state is true and 0 for all other states (Table 11–6).11–10 Chapter 11: Using the State Machine Library Using the State Machine Editor Block 9. Table 11–6.

count_in[7:0]. Click Next to display the Summary page. 11. State Machine Editor Wizard Actions Page 10. and action. and the five output ports (out_empty. The state machine displays graphically in the State Editor window (Figure 11–10 on page 11–12). push. and push_not_full). pop_not_empty. the five input ports (clock. Figure 11–9. pop. out_full. full. Check that the summary lists the five states (empty.Chapter 11: Using the State Machine Library Using the State Machine Editor Block 11–11 Figure 11–9 shows the Actions page after you define the output ports. out_pop_not_full. Click Finish to complete the state machine definition. out_idle. and reset). and out_push_not_full). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . idle.

you can edit the state machine using the Properties dialog boxes that you can display from the right button pop-up menu when you select a state or transition. You can ignore these messages. click Exit. This state is the empty state and is the state to which the state machine transitions when you assert the reset input. If there are any errors. click Generate HDL File to display the Generate HDL File dialog box. Click Yes to save the fifo_controller. 12. refer to the About the State Machine Editor topic in the Quartus II Help. You can also edit the state machine in table format by clicking the tabs at the bottom of the State Machine Editor window. f For information about editing state machine properties and drawing a graphical state machine. 1 There are five warning messages stating that FSM verification skips in each state. Select VHDL and click OK to confirm your choice. The fifo_controller block on your model updates with the input and output ports defined in the state machine. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .smf file and check that there are no FSM verification errors. Graphical fifo_controller State Machine Diagram 1 DSP Builder marks the first state that you enter in the wizard as the default state. On the File menu in the Quartus II State Machine Editor.11–12 Chapter 11: Using the State Machine Library Using the State Machine Editor Block Figure 11–10. 13. On the Tools menu in the Quartus II State Machine Editor.

Chapter 11: Using the State Machine Library Using the State Machine Editor Block 11–13 1 You may need to resize the block to ensure that the input and state names do not overlap and are displayed correctly. Figure 11–11. fifo_controller Block After Closing the State Machine Editor © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Figure 11–11 shows the updated fifo_controller block for the FIFO design example.

11–14 Chapter 11: Using the State Machine Library Using the State Machine Editor Block DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

qip file. follow these steps in the Quartus II software: 1. Managing Projects and Files DSP Builder design requires the following files to store all the components: ■ ■ ■ ■ ■ ■ The top-level Simulink model <top_level_name>. 2. 1 When you include the .qar file. Any Intel format hexadecimal memory initialization (. or are passing the design a user without access to MATLAB. Export HDL and specify the exported HDL as the source with no references to the . follow one of these steps: ■ ■ Include both the .mdlxml file in a Quartus II project. Integration with Source Control Systems Altera recommends that you store Quartus II archive (. Perform analysis and elaboration to ensure the design incorporates any black-box system files. 3.mdlxml file. which are referenced in the "# Imported IP files" section of the top-level .hex) files.mdl The import directory DSPBuilder_<top_level_name>_import and its contents.12. but you must call MATLAB as part of the generation flow. The analyzed Simulink model file <top_level_name>. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . Archive the project by clicking Archive Project on the project menu in the Quartus II software) to generate the . 1 Any design that includes HDL Import. You can still synthesize a project without the .mdlxml. If you do not want Quartus II synthesis to call MATLAB. To create a .mdl or .qar file.mdlxml files in the project.mdl and corresponding .qip) file that the DSP Builder Export HDL flow generates (“Exporting HDL” on page 12–2).qar) files rather than individual HDL files for source control purposes. you do not need to call MATLAB to synthesize the design. list the required files. Create a Quartus II project that sources the top-level Quartus II IP (. State Machine Editor or MegaCore functions requires the import directory. Any referenced custom library files. 1 Any HDL elements that you introduce into DSP Builder with custom library blocks may require their own source control. Additional .mdlxml files in the project. Any source files for imported HDL.qip files.

Successful migration of designs with MegaCore Functions assumes that the new environment has all the required IP installed.qip) files that you must modify when you move projects to a different location.0.qip file contains all the assignments and other information that the design requires to process the exported HDL in the Quartus II compiler and generate hardware. The expected directory structure is: <install_path><QUARTUS_ROOTDIR>\.\ip This feature allows the Export HDL flow to use relative paths. This fact is generally not the case if you generate the files with HDL Import. source files that you import with HDL Import are not part of a DSP Builder project. with absolute paths. Exporting HDL You can export the DSP Builder-generated synthesizable HDL to a Quartus II project and then use the Export tab in the Signal Compiler block to export them (Figure 12–1). When migrating to a new computer. If you use an old version of the MegaCore IP Library in your design. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . and improves portability. ensure that they are in the import directory. MegaCore Functions The MegaCore IP Library always installs in the same parent directory as the Quartus II installation. run the alt_dspbuilder_refresh_HDLimport script to ensure the HDL Import blocks are up-to-date. The . run the alt_dspbuilder_refresh_megacore script to ensure that the MegaCore function blocks are up-to-date.hex) files are required for memory initialization in simulation and hardware generation. When moving a design to a new version of the tools or a different location.12–2 Chapter : HDL Import HDL Import In general. When you move a design to a new version of the tools or to a location on a different computer. DSP Builder references them in projects that generate with the Export HDL flow as external files. If they are generated by HDL Import or MegaCore function blocks. 1 Before the Quartus II software version 8. It may be necessary to install the MegaCore IP Library and run the alt_dspbuilder_setup_megacore script.. there may still be absolute paths in the generated Quartus II IP (. Memory Initialization Files Intel-format hexadecimal (. it was possible to install previous versions of the MegaCore IP Library in any specified location. re-import the HDL to enable hardware generation (although simulation in Simulink may be possible without this step). This directory is not a subdirectory of the quartus directory but a relative path to an install directory at the same level as the quartus directory.

mdl file to export.qip file corresponding to the top-level of your design. exportedDir_value is the return string indicating the output directory containing the newly generated files. DSP Builder uses the default or previous export directory.Chapter : Exporting HDL 12–3 Figure 12–1. exportDir is the directory that contains the exported files. ■ ■ Running this flow creates a set of source files in the export directory. If you omit this optional argument. <exportDir>) where: ■ model is the name of the . © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . This file is always the top-level name in the exported Quartus II project. Export Tab in Signal Compiler You can also export HDL by executing the alt_dspbuilder_exportHDL command in the MATLAB command window. The syntax for the export HDL command is: <exportDir_value> alt_dspbuilder_exportHDL(<model>. including a .

Use the Archive Project command in the Quartus II software to archive this project.qip. You should enter the top-level name of the exported project and add the corresponding . recreate the auxiliary files to achieve a successful compilation. you can create a project using the New Project Wizard.mdl) HDL source files associated with HDL import blocks (if any)—maintain same relative path to MDL HDL wrapper files associated with IP MegaCore function blocks (if any)— maintain same relative path to the . .qip files if they include absolute paths to library components.vhd file is in the <QUARTUS_ROOTDIR>\libraries\vhdl\altera directory on a Windows computer. in some cases. This additional alt_dspbuilder_package. regenerate the auxiliary files (.mdl file (they should be in the DSPBuilder_<mdl name>_import subdirectory) Memory initialization . You require the following minimum set of design files to recreate a project: ■ ■ DSP Builder model (. The top-level files sources these files automatically.qip files as the single source file for the project. If the model contains IP MegaCore function or HDL import blocks. However.simdb) associated with the IP MegaCore function or HDL import block by following these steps: a. you can recreate the project by transferring a minimum set of design files. You do not need to copy the entire project directory. follow these steps: 1.entityimport. this act requires adding an additional file to the project.qip files describing the requirements for black-box components. Successful migration of design with IP MegaCore functions assumes that you install the required MegaCore IP library on the new environment. IP MegaCore functions—run the alt_dspbuilder_refresh_megacore script to automatically update all the IP MegaCore function blocks in the new location. However. HDL import—run the alt_dspbuilder_refresh_HDLimport script to automatically update all the HDL import blocks in the new location. Migration of DSP Builder (Standard Blockset) Files to a New Location When moving DSP Builder (standard blockset) projects to a new directory or machine. Use the Export HDL flow on a Windows computer to a Linux-based computer to migrate the files generated. edit their corresponding .hex files (if any) Custom library files (if any) ■ ■ ■ To recreate the project in the new location. which is available on the File menu in the Quartus II software. b. when the relative paths for the design files change in the new location. There may be additional .12–4 Chapter : Migration of DSP Builder (Standard Blockset) Files to a New Location Using Exported HDL After the Export HDL flow completes. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . . 1 When migrating designs that include MegaCore function blocks to a different location.

.qip file updates automatically with the new path settings. 2. the Quartus II software needs the .qip file is a single file that contains paths for all the files for an IP design.qip may reference embedded . create an additional directory <project directory>/ip/<module name> and create a file <module name>. you need the . SOPC Builder uses the same IP librarian to search for SOPC Builder components. Use the Quartus II IP (.qip file(s).. The ./<module name>/**/*'/> </library> © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .ipx file for the HDL import and IP MegaCore function blocks that your model uses. The . rather than adding all the necessary files individually. If you migrate the files from a different location. the top-level project also requires an IP Index (. it may be necessary to manually edit their corresponding . the DSP Builder system is an entity composed of DSP Builder blocks. which does not use it for generation.ipx file and need no special action—you just need to add the extra HDL import and MegaCore function entities. You only need the .ipx in that subdirectory.qip source files. skip this step.qip file for Quartus II archiving for DSP Builder.qip.ipx file has the following contents: <library> <path path='. By running the Analyze process from the Signal Compiler block in the new location. some older versions of IP MegaCore functions (before v8. 1 The DSP Builder specifies the main entities in the main Quartus II . The . . ././. and non-native entities like HDL import and MegaCore functions.qip file allows you to add an IP design to the project by adding only one file.Chapter : Integration of Multiple Models in a Top-Level Quartus II Project 12–5 1 If the .ipx) associated with the model.ipx files.qip files. Essentially.mdlxml.ipx) file that specifies additional paths for the IP Librarian to find components..ipx files to find all entities. Use the IP Librarian with .qip) file as the single source file for each DSP Builder model. Also.qip file(s) contain the information concerning the projects. To update the IP librarian search path for the top-level Quartus II project. These embedded .mdl and . Integration of Multiple Models in a Top-Level Quartus II Project To integrate multiple DSP Builder (standard blockset) designs in a top-level Quartus II project. Specifically for DSP Builder designs.. the . libraries and source HDL required by the Quartus II software for successful integration of these external entities into DSP Builder. (which themselves are entities but are easily discoverable). In addition to the . the top-level .\DSPBuilder_<mdl name>_import subdirectory copies and the design files. Re-analyze the model by clicking Analyze in the Advanced tab of the Signal Compiler block to regenerate the auxiliary files (.0) and HDL import blocks may have absolute paths in the generated . If the DSP Builder design includes HDL import or IP MegaCore functions.qip files to reflect the new environment.

/..ipx'/> Design Example The following example shows how you can integrate multiple DSP Builder designs into a top-level Quartus II project. create additional directories <project directory>/ip/<module name> and create an . Suppose your top-level design consists of the following three DSP Builder models: ■ ■ ■ fir1.mdl file and where to search for directories containing further ./<project directory>/ip/fir1 .. there are the following four design files: ■ ■ ■ ■ top. You can combine all the search paths into a single ..ipx files. Thus in this design example. create a text file <module name>..mdl—containing multiple HDL import blocks fir3.qip—Quartus IP file for fir3.ipx file using: <index file='.. fir2./<project directory>/ip/fir2 .. </library> You can also specify a path to a specific .mdl—containing one IP MegaCore function block with two Avalon-ST interfaces In the top-level Quartus II project...ipx file./../. The ** means search recursively.qip—Quartus IP file for fir2. To update the IP Librarian search path. For example: <library> <path path='.mdl Figure 12–2 on page 12–7 shows the design example in the Quartus II Project Navigator window..12–6 Chapter : Integration of Multiple Models in a Top-Level Quartus II Project These statements specify the relative path to the directory where to locate the .qip has an embedded ./<module name>/**/*'/> DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .../blockdemo. create the following directories: ■ ■ ■ .ipx with the following contents: <library> <path path='. 1 In this example../..qip associated with the HDL import block and fir3.qip associated with the IP MegaCore function block.mdl—containing two Avalon-MM slave interfaces fir2../.ipx file in each subdirectory.mdl fir3.vhd—Top-level wrapper that instantiates the three separate models fir1././<module name1>/**/*'/> <path path='././<module name2>/**/*'/> . and the final * locates all identifiable elements there..qip—Quartus IP file for fir1..mdl fir2.qip has an embedded ././<project directory>/ip/fir3 and in each subdirectory.

Figure 12–2.mdl file is located and tell the IP Librarian where to look for the components. where the .Chapter : Integration of Multiple Models in a Top-Level Quartus II Project 12–7 </library> These . Project Navigator Window in the Quartus II Software © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .ipx files specify the relative path to the directory.

12–8 Chapter : Integration of Multiple Models in a Top-Level Quartus II Project DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .

Troubleshooting Troubleshooting Issues This chapter contains information about resolving the following DSP Builder issues and error conditions: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Signal Compiler Cannot Checkout a Valid License Loop Detected While Propagating Bit Widths The MegaCore Functions Library Does Not Appear in Simulink The Synthesis Flow Does Not Run Properly DSP Development Board Troubleshooting SignalTap II Analysis Appears to Hang Error if Output Block Connected to an Altera Synthesis Block Warning if Input/Output Blocks Conflict with clock or aclr Ports Wiring the Asynchronous Clear Signal Error Issues when a Design Includes Pre-v7.13. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .1 Blocks Creating an Input Terminator for Debugging a Design A Specified Path Cannot be Found or a File Name is Too Long Incorrect Interpretation of Number Format in Output from MegaCore Functions Simulation Mismatch For FIR Compiler MegaCore Function Simulation Mismatch After Changing Signals or Parameters Unexpected Exception Error when Generating Blocks VHDL Entity Names Change if a Model is Modified Algebraic Loop Causes Simulation to Fail Parameter Entry Problems in the DSP Block Dialog Box DSP Builder System Not Detected in SOPC Builder MATLAB Runs Out of Java Virtual Machine Heap Memory ModelSim Fails to Invoke From DSP Builder Unexpected End of File Error When Comparing Simulation Results Signal Compiler Cannot Checkout a Valid License You may receive this error message if you try to generate VHDL files and Tcl scripts (or try to generate VHDL stimuli) and you have not installed a license for DSP Builder.

12. For example. All Rights Reserved.dat ----------------------------------------------------"C4D5_512A" v0000. and/or Macrovision Corporation. Verifying That Your DSP Builder Licensing Functions Properly Type the following command in the MATLAB Command Window: dos('lmutil lmdiag C4D5_512A') r where C4D5_512 is the DSP Builder feature ID. vendor: alterad uncounted nodelocked license. if you are using a node locked license: lmutil . FLEXnet diagnostics on Mon 8/11/2008 10:49 ----------------------------------------------------License file: node@lic_server ----------------------------------------------------"C4D5_512A" v2030. locked to Vendor-defined "GUARD_ID=T000001297" no expiration date 1 You receive a message about the hostid if you are using an Altera software guard for licensing. and/or Macrovision Corporation. your license file may not be set up correctly. if you are using a floating license: >> dos('lmutil lmdiag C4D5_512A') lmutil . refer to Volume 1: Introduction to DSP Builder in the DSP Builder Handbook. vendor: alterad License server: lic_server floating license expires: 31-dec-2030 This license can be checked out ----------------------------------------------------- If the command does not work. If your license file has a SERVER line.00. type the following command in the MATLAB Command Window: dos('lmutil lmstat -a') r This command outputs the status of the DSP Builder license in the following format: DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .Copyright (C) 1989-2006 Macrovision Europe Ltd.Copyright (c) 1989-2006 Macrovision Europe Ltd. For information about how to check your system path and registry settings. FLEXnet diagnostics on Mon 8/11/2008 14:36 ----------------------------------------------------License file: c:\qdesigns\license.13–2 Chapter : Troubleshooting Issues f For information about how to obtain a license. All Rights Reserved. This command outputs the status of the DSP Builder license. Alternatively. refer to “The Synthesis Flow Does Not Run Properly” on page 13–5.

7.2 Feature usage info: Users of C4D5_512A: (Total of 100 licenses issued. such as Mentor Graphics LeonardoSpectrum. type <path to license file>\license. Click OK. Click the System Variable list to highlight it. Verifying the Quartus II Path Verify that the QUARTUS_ROOTDIR environment variable points at the correct version of the Quartus II software by typing the following command in the MATLAB Command Window: !echo %QUARTUS_ROOTDIR% r © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . type LM_LICENSE_FILE. In the Variable Value box.dat files in the steps below. make sure that LM_LICENSE_FILE points to the version of software that you want to use with DSP Builder.dat files into one or you can specify multiple license. Double-click the System icon in the Control Panel window. 1 If you have multiple versions of software that uses a license. also use the LM_LICENSE_FILE variable to point to a license file. On the Windows Start menu point to Settings and click Control Panel.8 Vendor daemon status (on lic_server): alterad: UP v9. your license file may not be set up correctly. click the Advanced tab. Total of 0 licenses in use) If the command does not work. Flexible License Manager status on Mon 8/11/2008 15:36 License server status: [Detecting lmgrd processes.dat file that includes the DSP Builder FEATURE line for the DSP Builder to operate properly.dat file (for example.. Follow these steps to set the LM_LICENSE_FILE variable: 1. 8. and/or Macrovision Corporation.Copyright (c) 1989-2006 Macrovision Europe Ltd. Click on Environment Variables. Verifying That the LM_LICENSE_FILE Variable Is Set Correctly The LM_LICENSE_FILE system variable must point to your license. 6.Chapter : Troubleshooting Issues 13–3 lmutil . and then click New. 5. Quartus II Limited Edition and a full version of the Quartus II software). In the System Properties dialog box. All Rights Reserved. Other software products. 4. You can combine several license.dat.dat: lic_server: license server UP (MASTER) v10.. 2. In the Variable Name box.] License server status: node@lic_server License file(s) on shama: /usr/licenses/quartus/license. 3.

Figure 13–1 shows this error.13–4 Chapter : Troubleshooting Issues This command returns the path that the QUARTUS_ROOTDIR environment variable specifies. For example: C:\altera\81\quartus If You Still Cannot Get a License ■ Try adding the following paths to your system path: ■ ■ quartus/bin matlab/bin ■ Remove and reinstall DSP Builder. Figure 13–2. Feedback Loop With AltBus Block as an Internal Node The MegaCore Functions Library Does Not Appear in Simulink The Simulink Library Browser may not display MegaCore functions library if you install DSP Builder before you install the Altera MegaCore IP Library. Loop Detected While Propagating Bit Widths You may get an error if you have a feedback loop in your design and you have not explicitly defined the feedback loop’s bit width. Feedback Loop With Unresolved Width Error To avoid this error. include an AltBus block configured as an internal node to specify the bit width in the feedback loop explicitly (Figure 13–2). Figure 13–1. After removing DSP Builder. type the following command after you instal the Altera MegaCore IP Library: alt_dspbuilder_setup_megacore r DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . To fix this problem. delete any DSP Builder files or directories that remain in the file system to ensure that you re-install a clean file set.

ByteBlaster. You can configure the DSP board manually with an SRAM Object File (.sof) file in your working directory. Check the Software Paths If you have multiple versions of the same software product on your PC (for example. Signal Compiler generates the SRAM object file (. With the automated flow. check the following points: ■ Ensure that you set up and connect the board to your PC and you install any necessary drivers. if it does not meet one or more of the trigger conditions. ■ ■ SignalTap II Analysis Appears to Hang The SignalTap II logic analyzer should terminate successfully after it meets all trigger conditions. check the software paths and if necessary. or switch off the board and switch it on again. However. the Signal Compiler block outputs VHDL files and Tcl scripts and then automatically begins synthesis and compilation in the Quartus II software. a ByteBlasterMV. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .Chapter : Troubleshooting Issues 13–5 The Synthesis Flow Does Not Run Properly The DSP Builder automated flows allow you to control your entire synthesis and compilation flow in the MATLAB or Simulink environment using the Signal Compiler block. the CONF_DONE LED illuminates. the SignalTap II analyzer does not terminate and the JTAG node remains locked. Error if Output Block Connected to an Altera Synthesis Block An Output block maps to output ports in VHDL and marks the edge of the generated system. If the Quartus II software does not run automatically. ByteBlaster II. You should normally use these blocks to connect simulation blocks (Simulink blocks) for your testbench. configuration is unsuccessful. You can either disconnect and reconnect the USB cable. your registry DSP Development Board Troubleshooting If Signal Compiler does not configure the device on the DSP development board. or USB-Blaster download cable. When the board powers up. You must program the board again if you power it off. change the system path settings. Quartus II Web Edition and a full version of the Quartus II software). and the Quartus II Programmer in JTAG mode. If you want to use DSP Builder blocks outside your synthesizable system (such as for test bench generation or verification) put Non-synthesizable Input and Non-synthesizable Output blocks around them. The CONF_DONE LED turns off and then on when configuration completes successfully.sof). If you do not observe the LED operating in this way.

This procedure may cause bit width propagation and inheritance problems. this name is the same name as the default system reset and the following warning issues during analysis: Warning: aclrInputPortTest/aclr has been renamed to avoid conflict: aclr has been renamed to aclr_1: The input port renames during HDL conversion. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation .1 blocks: Data type mismatch. Figure 13–3. disconnect some subsystems so that you can analyze a small portion of your design. However. it is driven by a signal of data type 'DSPB_Type'. Creating an Input Terminator for Debugging a Design If there is a problem somewhere in a design.13–6 Chapter : Troubleshooting Issues Warning if Input/Output Blocks Conflict with clock or aclr Ports A warning issues if an input or output port has the same name as a clock or reset signal that your model uses. This combination functions as a temporary input terminator and you can remove them after you debug your design. f For information about upgrading your designs. Wiring the Asynchronous Clear Signal 1 A design may not match the hardware if an asynchronous clear performs during simulation because the aclr cycle may last several clocks . If you want to keep the port aclr. refer to Volume 1: Introduction to DSP Builder in the DSP Builder Handbook. You can avoid these problems by inserting a Non-synthesizable Output block followed immediately by a Non-synthesizable Input block. Input port 1 of '<old block>' expects a signal of data type 'double'. add a Clock block and use it to rename the reset port.1 Blocks An error of the following form issues if you attempt to simulate a design that includes unupgraded pre-v7. Wiring the Asynchronous Clear Signal Wire the asynchronous clear signal with a register to make sure that the end of the aclr cycle synchronizes with the clock (Figure 13–3). For example if your design has an input port aclr.depending on clock speed and the device. Error Issues when a Design Includes Pre-v7.

Unexpected Exception Error when Generating Blocks DSP Builder issues errors of the following form when you generate a DSP Builder system: Info: IP Generator Info: stderr: No clock info for my_alt_dspbuilder_clock Info: IP Generator Info: stderr: Failed to find clock my_alt_dspbuilder_clock Info: IP Generator Info: stderr: Failed to find clock my_alt_dspbuilder_clock Error: IP Generator Error: Unexpected exception thrown by MDLFactory: java. by directly attaching scopes. unsigned. signed fractional. This issue can cause problems when visualizing the output.vhd Line: 30 © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide .Chapter : Troubleshooting Issues 13–7 A Specified Path Cannot be Found or a File Name is Too Long The maximum length for a path is limited to 256 characters in the Windows operating system. For example. Incorrect Interpretation of Number Format in Output from MegaCore Functions For some MegaCore functions. Correct this issue by connecting to the output with an AltBus block or a Non-synthesizable Output block (as appropriate) with the correct bus type assignment. refer to the Simulate the Design section in the FIR Compiler User Guide. If this problem occurs. DSP Builder may attempt to create a file path exceeding this limit. when the signal waveform may obscur because of the incorrectly inferred number formats. Simulation Mismatch For FIR Compiler MegaCore Function FIR Compiler MegaCore function-generated functional simulation models generally do not output valid data until the data storage of these models is clear. DSP Builder may be unable to infer whether it should interpret output signals as signed. delete the previous testbench directory (tb_<model name>) and run the simulation again.NullPointerException Error: Node instance "dut" instantiates undefined entity "TestBarrelShifter" File: <path>/mytoplevel. Simulation Mismatch After Changing Signals or Parameters The simulation results may not match after changing any signal names or parameters.lang. When the file path to a model or the name of the model is very long. If this problem occurs. reduce the length of the file path to the model or the length of its name. f For more information including a formula that estimates the number of cycles before relevant samples are available.

that is. 'use_dynamic_feedthrough_data'. and a 1 indicating that all paths to outputs from this input are registered. 'inDelayed'. Solve this problem with a regular expression in the project assignments (“Making Quartus II Assignments to Block Entity Names” on page 3–27). inputs that have a purely combinational path to at least one output of the block. refer to the MATLAB Help. when it is in fact direct feedthrough. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . Algebraic Loop Causes Simulation to Fail HDL import and IP Toolbench-based MegaCore function blocks provide an interface for changing the direct feedthrough settings of their inputs. if you change the pipeline delay on a Delay block. f For more information about algebraic loops. Enable it by typing the following command in the MATLAB command window: set_param(<HDL Import block name>. <feedthrough setting>) For example. with the following command: set_param(<block name>. A more direct method of changing the direct feedthrough settings is to modify the InDelayed parameter on HDL Import or MegaCore function blocks. 1 Specifying a value of 1 for an input. For example.quartus\ip_cache VHDL Entity Names Change if a Model is Modified The Signal Compiler VHDL files have a random number suffix appended to the file if you modify the model. 'inDelayed'. '1 0 0 1') A valid value of this parameter is a series of digits. one for each of the inputs on the block (from top to bottom). causes Simulink to treat combinational paths as registered. 'on') The direct feedthrough settings for the HDL Import block update after a successful compile of the HDL when this parameter is on. Algebraic loops are loops entirely consisting of blocks having some inputs that are direct feedthrough. with a 0 indicating direct feedthrough.altera. while the VHDL file name for the rest of the blocks in the model remain the same. if the block is named My_HDL: set_param(<My_HDL>. the corresponding VHDL file: alt_dspbuilder_delay_<randomnumber> changes.13–8 Chapter : Troubleshooting Issues This problem is caused by corrupted Librarian IP cache and can be resolved by deleting the IP cache directory which is normally located at: C:\Documents and Settings\<user>\. The feature to automatically infer the correct direct feedthrough values is disabled by default for HDL Import (and DSP Builder treats all inputs as direct feedthrough). and results in incorrect simulation results. 1 This feature may not generate correct settings when importing low-level LPM-based HDL.

Your PC should automaticall include ModelSim in your path if you install ModelSim-Altera but you may need to be add it manually if you use a different ModelSim installation. MATLAB Runs Out of Java Virtual Machine Heap Memory For a very large design (containing many thousand blocks). Altera does not guarantee backwards compatibility of these modules when you use them in SOPC Builder. This procedure is useful if you know which block is providing the correct initial values.Chapter : Troubleshooting Issues 13–9 Adjust the order in which Simulink exercises all the blocks in a feedback loop.mathworks. A lower value of priority causes DSP Builder to execute a block before a block with a higher value. Parameter Entry Problems in the DSP Block Dialog Box There are issues with the Block Properties dialog box for the DSP block. To workaround this issue. Reopen the dialog box and you can select now select Symmetric saturation. 3. Re-run compilation from the Signal Compiler block with the current DSP Builder version. set the saturation type to None (wrap) and close the dialog box.com/support/solutions/data/1-18I2C. check that the currently supported ModelSim executable (vsim. The priority of a block can be set with the General tab in the block properties for a block. follow these steps: 1. Refresh the SOPC Builder system. Some interdependencies require that you close and re-open the dialog box to edit further parameters.exe) is in the path.html ModelSim Fails to Invoke From DSP Builder If ModelSim fails to invoke from within DSP Builder. MATLAB may have insufficient heap memory available for the Java virtual machine and issues an error message of the form: “OutofMemoryError: Java heap space” f For information about how to increase the heap space available to the Java virtual machine. if you change the Output Rounding Operation Type you may get an error when Symmetric is selected for the Output Saturation Operation Type. refer to: http://www. by giving blocks a priority value. 2. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset User Guide . This issue may be occur after a warning message issues or when a required option is not available. For example. If this occurs. Remove the <dspbuilder system name>_dspbuilder directory that the older DSP Builder version generated. DSP Builder System Not Detected in SOPC Builder SOPC Builder may not detect DSP Builder systems whose hardware has been generated using previous versions of the DSP Builder software.

Unexpected End of File Error When Comparing Simulation Results Occasionally an “Unexpected End of File” error issues when you are comparing the Simulink and ModelSim simulation results for a design with multiple clocks. DSP Builder Standard Blockset User Guide Preliminary © June 2010 Altera Corporation . f For information about the supported version of ModelSim. refer to the DSP Builder Installation and Licensing manual.13–10 Chapter : Troubleshooting Issues You can verify the ModelSim installation by typing the following command at the MATLAB prompt: !vsim This command returns the ModelSim version and the path to the ModelSim preferences Tcl file. If an error message issues or the returned path is incorrect. You can ignore the error message. This error occurs because the rounding calculation that aligns the clock signals sets ModelSim simulation to run for one additional clock cycle (on the fastest clock) and there is no stimulus data for this extra cycle. you may need to move ModelSim to be ahead of any other similar tool in the path.

0 Document Version: Document Date: 1.0 June 2010 .altera. DSP Builder Standard Blockset Libraries 101 Innovation Drive San Jose.com HB_DSPA_STD_LIB-1.Section II. CA 95134 www.

Altera products are protected under numerous U. and foreign patents and pending applications. . Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. The Programmable Solutions Company. All rights reserved. or service described herein except as expressly agreed to in writing by Altera Corporation. and other countries. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty. product. maskwork rights.Copyright © 2010 Altera Corporation. Altera assumes no responsibility or liability arising out of the application or use of any information. unless noted otherwise. and all other words and logos that are identified as trademarks and/or service marks are. the trademarks and service marks of Altera Corporation in the U. All other product or service names are the property of their respective holders. but reserves the right to make changes to any products and services at any time without notice. specific device designations. the stylized Altera logo.S. and copyrights.S.

0 First published. Date June 2010 Version 1. Changes Made © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .About This Section Revision History The following table shows the revision history for this section.

iv About This Section Revision History DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

1. AltLab Library The blocks in the AltLab library manage design hierarchy and generate RTL VHDL for synthesis and simulation. The AltLab library contains the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ BP (Bus Probe) Clock Clock_Derived Display Pipeline Depth HDL Entity HDL Import HDL Input HDL Output HIL (Hardware in the Loop) Quartus II Global Project Assignment Quartus II Pinout Assignments Resource Usage Signal Compiler SignalTap II Logic Analyzer SignalTap II Node Subsystem Builder TestBench VCD Sink © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .

the clock period must be greater than 1ps but less than 2. When you specify these reset types. DSP Builder adds two extra registers to avoid metastability issues during reset removal. Each clock must have a unique reset name. The Bus Probe block does not have any hardware representation and therefore does not appear in the VHDL RTL representation generated by the Signal Compiler block. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . which you can place on any node of a model. a default clock (clock) with a 20-ns real-world period and a Simulink sample time of 1 is automatically created with a default Active Low reset (aclr). The Display in Symbol parameter selects the graphical shape of the symbol in your model and the information that is reported there (Table 1–1).1–2 Chapter 1: AltLab Library BP (Bus Probe) BP (Bus Probe) The Bus Probe (BP) block is a sink. You can add reset synchronizer circuitry for this clock domain by specifying the reset type to be either synchronized active low or synchronized active high. 1 To avoid sample time conflicts in the Simulink simulation. the Bus Probe block back-annotates the following information in the parameters dialog box for the Bus Probe block: ■ ■ ■ Maximum value reached during simulation Minimum value reached during simulation Maximum number of integer bits required during simulation Clock Use the Clock block in the top level of a design to set the base hardware clock domain. Table 1–1. The block name is the name of the clock signal and must be a valid VHDL identifier. If no base clock exists in your design. After simulating your model.1ms. ensure that the sample time specified in the Simulink source block matches the sample time specified in the Input block (driven by the Clock block or a derived clock). Bus Probe Block “Display in Symbol” Parameter Shape of Symbol Circle Rectangle Data Reported in Symbol Maximum number of integer bits required during simulation. As all clock blocks have the same default reset name (aclr) ensure you specify a valid unique name with multiple clocks. Place additional clocks in the system by adding Clock_Derived blocks. You can specify the required units and enter any positive value with the specified units. Maximum or minimum value reached during simulation. However. A design can have zero or one base clock in a design and an error issues if you try to use more than one base clock.

Export As Output Pin Turn on to export this clock as an output pin. ms. However. You can add reset synchronizer circuitry for this clock domain by specifying the reset type to be synchronized active low or synchronized active high.1 ms. Specify these clocks as a rational multiple of the base clock for simulation purposes. You can specify the numerator and denominator multiplicands calculates the derived clock. Each clock must have a unique reset name. Specify the Simulink sample time. Specify the units for the clock period (picoseconds. milliseconds.Chapter 1: AltLab Library Clock_Derived 1–3 Table 1–2 lists the parameters for the Clock block. ensure that the sample time specified in the Simulink source block matches the sample time specified in the Input block (driven by the Clock block or a derived clock). 1 To avoid sample time conflicts in the Simulink simulation. Specify a unique reset name. Table 1–3 lists the parameters for the Clock_Derived block: © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . DSP Builder uses the block name as the name of the clock signal. or seconds). nanoseconds. Table 1–2. Specify whether the reset signal is active high or active low. Synchronized Active Low. ns. Active High. As all clock blocks have the same default reset name (aclr) ensure you specify a valid unique name with multiple clocks. It must be a valid VHDL identifier. Synchronized Active High On or Off Description Specify the clock period. When you specify these reset types. the resulting clock period should be greater than 1ps but less than 2. Clock_Derived Use the Clock_Derived block in the top level of a design to add additional clock pins to your design. microseconds. DSP Builder creates a 20ns base clock and determines the derived clock period. us. The default reset is aclr. If no base clock is set in your design. Clock Block Parameters Name Real-World Clock Period Period Unit Simulink Sample Time Reset Name Reset Type Value user specified ps. DSP Builder adds two extra registers to avoid metastability issues during reset removal.1ms. s >0 User defined Active Low. You must use a Clock block to set the base clock if you want the sample time to be anything other than 1. which should be greater than 1ps but less than 2.

Active High. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Export As Output Pin Turn on to export this clock as an output pin. Changing modes causes a Simulink display update. The Subsystem Builder block usually creates this block. Specify whether the reset signal is active high or active low. On or Off Turn on to use the subsystem port names as the entity port names instead of the names of the HDL Input and HDL Output blocks.1ms. Specify a unique reset name. The default reset is aclr. HDL Entity Use the HDL Entity block for black-box simulation subsystems that you include in your design with a Subsystem Builder block. HDL Entity Block Parameters Name HDL File Name Clock Name Reset Name HDL takes port names from Subsystem Value Description User defined Specifies the name of the HDL file that DSP Builder substitutes for the subsystem represented by a Subsystem Builder block. The currently selected mode shows on the Display Pipeline Depth block symbol. The resulting clock period should be greater than 1ps but less than 2. Synchronized Active High On or Off Value Description Multiply the base clock period by this value. the current pipeline depth displays at the top right corner of each block that adds latency to your design. The HDL Entity block specifies the name of the HDL file that DSP Builder substitutes for the subsystem and the names of the clock and reset ports for the subsystem. You can change the display mode by double-clicking on the block. The resulting clock period should be greater than 1ps but less than 2. Display Pipeline Depth The Display Pipeline Depth block controls whether the pipeline depth displays on primitive blocks. Divide the base clock period by this value. which may be slow for very large designs. User defined Specifies the name of the clock signal that the black-box subsystem uses. Synchronized Active Low.1ms. User defined Specifies the name of the reset signal that the black-box subsystem uses. When set.1–4 Chapter 1: AltLab Library Display Pipeline Depth Table 1–3. Table 1–4. The Display Pipeline Depth block has no parameters. Table 1–4 shows the parameters for the HDL Entity block. Clock_Derived Block Parameters Name Base Clock Multiplicand Numerator Base Clock Multiplicand Denominator Reset Name Reset Type >= 1 >= 1 User defined Active Low.

Chapter 1: AltLab Library HDL Import 1–5 HDL Import Use the HDL Import block to import existing blocks implemented in HDL into DSP Builder. there may be Xs in the simulation results. The source files that the Quartus II project uses must be in the same directory as your model file or be explicitly referenced in the Quartus II settings file (. it issues an error message after you click Compile and it cannot import the HDL. Click to remove the selected file from the list.qpf). However. Click to change the compilation order by moving the selected HDL file up or down the list. which includes FIFO buffers. . Down Value On or Off — — Description You can import individual HDL files when this option is on.qpf file © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . and gates. Individually specify the VHDL or Verilog HDL files or define in a Quartus® II project file (. you may be able to rewrite the HDL so that the Quartus II software infers a different megafunction or LPM function. The netlist then compiles into a binary simulation netlist for use by the HDL simulation engine in DSP Builder.qsf). Table 1–5. 1 You must save your model file before you can import HDL with the HDL Import block.vhd file Click to browse for one or more VHDL files or Verilog HDL files. Table 1–5 shows the parameters for the HDL Import block. If DSP Builder encounters an unsupported function. To import a different revision. When simulating imported VHDL in ModelSim. You should use the FIFO buffer carefully to avoid any overflows or underflows. a simulation file generates and the block in your model configures with the required input and output ports. specify the required revision in the Quartus II software. Specifies the name of the top level entity in the imported HDL files. The Quartus II software synthesizes the imported HDL or project as a netlist of megafunctions. DSP Builder imports the current HDL configuration. Error messages issue for any entities that DSP Builder cannot find. When this option is on. Refer to the Quartus II documentation for information about setting the current revision of a project and how to explicitly reference the source files in your design. DSP Builder may explicitly instantiate the megafunctions and LPM functions in the imported files. which may give a mismatch with the Simulink simulation. LPM functions. Click to browse for a Quartus II project file.v or . When you click Compile. Examine and eliminate any warnings of Xs that ModelSim reports during simulation before you compare to the Simulink results. or the Quartus II software may infer them. The file order is not important when you use the Quartus II software but may be significant when you use other downstream tools (such as ModelSim). The simulator supports many of the common megafunctions and LPM functions although it does not support some.qpf). Enter name of top level design entity Import Quartus II Project Entity name On or Off Browse . HDL Import Block Parameters (Part 1 of 2) Name Import HDL Add Remove Up. you can specify the HDL to import with a Quartus II project file (.

1–6 Chapter 1: AltLab Library HDL Import Table 1–5. Figure 1–1. Typical HDL Import Block Use std_logic_1164 types to define the input and output interfaces to the imported VHDL. LPM Functions lpm_abs lpm_add_sub lpm_compare lpm_counter lpm_mult (Note 1) lpm_mux lpm_ram_dp altsyncram parallel_add scfifo Table 1–7 on page 1–7 lists the megafunctions and LPM functions that are not supported. If you import a design with multiple clocks. and two output ports (Output. Output1). HDL import only supports single clock designs. you should write a wrapper that converts them to std_logic or std_logic_vector. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . If your design uses any other VHDL type definitions (such as arithmetic or numeric types). sclrp). Supported Megafunctions and LPM Functions Megafunctions a_graycounter altaccumulate altmult_add altshift_taps Note to Table 1–6: (1) The lpm_mult LPM function is not supported when configured to perform a squaring operation. Input1. HDL Import Block Parameters (Part 2 of 2) Sort top-level ports by name Compile On or Off — Turn on to sort the ports that the top-level HDL file alphabetically defines instead of the order specified in the HDL. DSP Builder uses one clock as the implicit clock and shows any others as input ports on the Simulink block. Input2. 1 Store HDL source files in any directory or hierarchy of directories. Table 1–6 lists the supported megafunctions and LPM functions. Figure 1–1 shows an example of an imported HDL design implementing a simple adder with four input ports (Input. Compiles a simulation model from the imported HDL and displays the ports defined in the imported HDL on the block. Table 1–6.

HDL Input Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2).Optional © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Signed Fractional.Chapter 1: AltLab Library HDL Input 1–7 Table 1–7. Single Bit >= 0 (Parameterizable) []. [number of bits]. This parameter does not apply to single-bit buses. Unsupported Megafunctions and LPM Functions Megafunctions alt3pram altcam altcdr altclklock altddio altdpram altera_mf_common altfp_mult altlvds altmemmult altmult_accum altpll altqpram altsqrt alt_exc_dpram alt_exc_upcore dcfifo lpm_and lpm_bustri lpm_clshift lpm_constant lpm_decode lpm_divide lpm_ff lpm_fifo lpm_fifo_dc LPM Functions lpm_inv lpm_latch lpm_or lpm_pad lpm_ram_dq lpm_ram_io lpm_rom lpm_shiftreg lpm_xor HDL Input Connect the HDL Input block directly to an input node in a subsystem. (3) I1[L1]. is connected to or explicitly set to either Simulink Fixed Point or Double Double type. The type and bit width must match the type and bit width on the corresponding input port in the HDL file referenced by the HDL Entity block.[R1] VHDL I1: out STD_LOGIC_VECTOR({L1 + R1 .[number of bits] External Type >= 0 (Parameterizable) Description The number format of the bus. Use with the Subsystem Builder and HDL Entity blocks for black-box simulation. the width may be truncated if the bit width is greater than 52. including the sign bit. This parameter applies only to signed fractional buses. You can optionally specify the external Simulink type. Specify the number of bits to the right of the binary point.1} DOWNTO 0) Type (4) Implicit . The default is Inferred. Inferred. HDL Input Block Parameters Name Bus Type Value Signed Integer. Table 1–9. Table 1–8 shows the HDL Input block parameters. . the bit width is the same as the input. If set to Simulink Fixed Point Type. Table 1–9 on page 1–7 shows the HDL Input block I/O formats. Unsigned Integer.[] Specify the number of bits to the left of the binary point. HDL Input blocks are automatically generated by the Subsystem Builder block. If set to Double. Table 1–8. Specifies whether the external type is inferred from the Simulink block it Simulink Fixed Point Type.

[R1] O1[LP]. [1] is a single bit. To specify the bus format of an implicit input port.[] []. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . [L]. (2) [L] is the number of bits on the left side of the binary point. [R] is the number of bits on the right side of the binary point.[RP] (Note 1) VHDL I1: out STD_LOGIC_VECTOR({L1 + R1 . that is.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP . [R] is the number of bits on the right side of the binary point.[R] is an input port. that is. (4) Explicit means that the port bit width information is a block parameter. HDL Output blocks are automatically generated by the Subsystem Builder block. use a Bus Conversion block to set the width. that is. For single bits.1} DOWNTO 0) Type (4) Implicit . For single bits.[RP] VHDL O1: out STD_LOGIC_VECTOR({LP + RP . O1[L]. The number format of the bus. R = 0. For signed or unsigned integers R = 0. HDL Output Block Parameters Name Bus Type Value Signed Integer. that is. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. For signed or unsigned integers R = 0. HDL Input Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2).[number of bits] Table 1–11 shows the HDL Output block I/O formats. [1] is a single bit. (2) [L] is the number of bits on the left side of the binary point. O1[L]. (3) I1[L].[R] is an output port.[R] is an output port. Use with the Subsystem Builder and HDL Entity blocks for black-box simulation.[0]. the MSB is the sign bit.[R] is an input port. Description [number of bits]. use a Bus Conversion block to set the width. (Parameterizable) This parameter does not apply to single-bit buses. The type and bit width must match the type and bit width on the corresponding output port in the HDL file referenced by the HDL Entity block. To specify the bus format of an implicit input port. Table 1–10 shows the HDL Output block parameters. >= 0 Specify the number of bits to the right of the binary point.Optional Explicit Notes to Table 1–11: (1) For signed integers and signed binary fractional numbers.1} DOWNTO 0) Type (4) Explicit Notes to Table 1–9: (1) For signed integers and signed binary fractional numbers. Signed Fractional. Unsigned Integer. Table 1–10. Single Bit >= 0 Specify the number of bits to the left of the binary point. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. (3) I1[L1]. (4) Explicit means that the port bit width information is a block parameter. including the sign bit. (3) I1[L]. This parameter applies (Parameterizable) only to signed fractional buses.[0]. [L]. (3) O1[LP]. HDL Output The HDL Output block should be connected directly to an output node in a subsystem. HDL Output Block I/O Formats I/O I O Simulink (2). R = 0. Table 1–11. the MSB is the sign bit.1–8 Chapter 1: AltLab Library HDL Output Table 1–9.

ByteBlaster™. HIL Block Parameters.which describes the hardware design that the HIL block uses. When off (the default).) Burst Mode Burst Length (Note 1) Frame Mode Input Sync Output Sync Sampling Period On or Off Port name Port name Integer © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . The reset pin name for the hardware design in the Quartus II software. the reset level is specified in the Clock or Clock_Derived block. and also allows access to real hardware in a simulation. The clock pin name for the hardware design in the Quartus II software. Use higher values to produce faster simulations (although the extra gain becomes negligible with bigger burst sizes). The reset level that matches the setting in the original design. you need an FPGA development board with a JTAG interface. When Off. The simulation results may be unreliable for combinational paths. it uses a default clock with reset level active high. allows sending data to the FPGA in bursts. Active_High. When on. On or Off When on. the port is exported to the Simulink model. HIL supports advanced features. For designs originated from the advanced blockset. Use in burst mode when data is sent or received in frames. This configuration accelerates the simulation time. Use any JTAG download cable. it defaults to single-step mode. or USB-Blaster™ cable. Page 1 (Part 1 of 2) Name Select the Quartus II project Select the clock pin Select the reset pin Identify the signed ports Export Select the reset level Value . The input port for the synchronization signal in frame mode. For designs originated Active_Low from the standard blockset. including: ■ ■ Exported ports (allows the use of hardware components connected to the FPGA) Burst and frame modes (improves HIL simulation speed) 1 This block supports only single clock designs with registered paths in a design. Specify the length of a burst ("1" is equivalent to disabling burst mode).qpf file Port name Port name Signed or Unsigned On or Off Description Browse for a Quartus II project file . To use an HIL block. If your design uses no clock block. such as a ByteBlasterMV™. the reset level is specified in the Signals block. Table 1–12. which improves the simulation speed.Chapter 1: AltLab Library HIL (Hardware in the Loop) 1–9 HIL (Hardware in the Loop) The HIL (Hardware in the Loop) block allows you to use an FPGA as a simulation device inside a Simulink design. allows synchronizing of the output data frames to the input data frames. The output port for the synchronization signal in frame mode. When on. Table 1–12 shows the parameters specified in page 1 of the HIL dialog box. Set the number of bits and select the type (signed or unsigned) of each input and output port in the hardware design. Specify the sample time period in seconds. but delays the outputs by the burst length. (A value of -1 means that the sampling period is inherited from the block connected to the inputs. the selected port is exported on an FPGA pin (or on multiple pins for buses).

the optimal record size is between 1 to 2 MBPS (depending on the host computer. Configure FPGA Transcript window — — Figure 1–2 shows an example with the HIL block. Description device location The required entry for the location of the device. set the burst length to 32×1024. Table 1–13. Page 2 Name FPGA device Compile with Quartus II JTAG Cable Device in chain Scan JTAG Value device name — cable name — The FPGA device. Page 1 (Part 2 of 2) Name Value Description When on. HIL Block Parameters. Example With the HIL Block 1 Refer to the “Using Hardware in the Loop” chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. clock pin. The available cable names and device names are loaded into the JTAG Cable and Device in chain list boxes. The JTAG cable. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Displays the progress of the compilation. or any of the exported ports. asserts the synchronous clear signal before the simulation starts. USB driver and cables). Click to compile the HIL block with the Quartus II software. for a packet size of 1024 bits. Assert “Sclr” before On or Off starting the simulation Note to Table 1–12: (1) The record size is 32×1024×1024. Table 1–13 shows the parameters specified in page 2 of the HIL dialog box. Click to scan the JTAG interface for all JTAG cables attached to the system (including any remote computers) and the devices on each JTAG cable. due to the limitations of the JTAG interface. Hence.1–10 Chapter 1: AltLab Library HIL (Hardware in the Loop) Table 1–12. Click to configure the FPGA. Figure 1–2. HIL Block Parameters. For example. setting a bigger burst size might not give significant speed up. which is the product of (packet size) × (burst length) while the packet size is the larger of the total input data width and the total output data width. 1 The HIL block needs recompilation if you change the Quartus II project. However.

Quartus II Global Project Assignment Block Parameters Name Assignment Name Assignment Value Value String String Specify the assignment name. Any values or arguments that contain spaces or other special characters must be enclosed in quotes. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . family. use a comma to separate the bit pin assignment location from LSB to MSB. 1 You cannot assign the device. Assignments With Quartus II Global Project Assignment Blocks Quartus II Pinout Assignments The Quartus II Pinout Assignments block passes Quartus® II project pinout assignments to the Quartus II project generated by the Signal Compiler block. refer to the Quartus II Settings File Reference Manual or use the following Quartus II shell command: quartus_sh --tcl_eval get_all_assignment_names f Table 1–14 shows the Quartus II Global Project Assignment block parameters.Chapter 1: AltLab Library Quartus II Global Project Assignment 1–11 Quartus II Global Project Assignment This block passes Quartus® II global project assignments to the Quartus II project. Figure 1–3. This block sets the pinout location of the Input or Output blocks in your model. Use the Signal Compiler block to make device and family settings. Each block sets a single assignment. Description Figure 1–3 shows an example defining multiple assignments with Quartus II Global Project Assignment blocks. If you need to make multiple assignments. Only use this block at the top level of your model. which have the specified pin names. or fMAX requirement with this block. use multiple blocks (Figure 1–3). Specify the assignment value with any optional arguments. These assignments could set Quartus II compilation directives such as target device or timing requirements. For buses. or the Clock and Clock_Derived blocks to make explicit clock settings. For a full list of Quartus II global assignments and their syntax. Table 1–14.

the default is clock) for the pin name. block RAM and DSP blocks resources required by your design. Pin_AB. use the name of the Clock block (for example. Table 1–15. Figure 1–4 shows an example with the Quartus II Pinout Assignments block. display timing information. Refer to the Quartus II Help for the pinout values of a device. Quartus II Pinout Assignments Block Parameters Name Pin Name Pin Location Value String String Description The pin name must be the exact instance name of the Input or Output block from the IO & Bus library. For example: Pin Name: aclr Pin Location: Pin_B4 Table 1–15 shows the Quartus II Pinout Assignments block parameters. Pin_AC assigns abc[0] to Pin_AA. The Resource Usage block displays an estimate of the logic. For example: Pin Name: clock Pin Location: Pin_AM17 To set the pin assignment for a reset. 1 You must save your model file and run Signal Compiler before you can use the Resource Usage block. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Pin location value of the FPGA IO. and abc[2] to Pin_AC To set the pin assignment for a clock. abc[1] to Pin_AB. Assignments With Quartus II Pinout Assignments Blocks Resource Usage Use the Resource Usage block to check the hardware resources. use the name of the reset signal specified in the Clock block (for example the default global reset is aclr) for the pin name. and highlight the critical paths in your design.1–12 Chapter 1: AltLab Library Resource Usage For example: Pin Name: abc Pin Location: Pin_AA. Figure 1–4.

Chapter 1: AltLab Library Signal Compiler 1–13 You can double-click on the Resource Usage block to display more information about the blocks in your design that generate hardware. Click to analyze the DSP Builder system. Arria II GX. Specifies the clock to use for capturing data with the SignalTap II feature from a list of available signals. f The information that displays depends on the selected device family. Enable SignalTap II On or Off SignalTap II depth SignalTap II clock Use Base Clock Export 2. Stratix II. Signal Compiler Use the Signal Compiler block to create and compile a Quartus II project for your DSP Builder design. Click to download your design to the connected development board. 256. The required JTAG cable port. 64. 1 You must save your model file before you can use the Signal Compiler block. Turn on this setting to add extra logic and memory to capture signals in hardware in real time. Turn on if you want to use the base clock for the SignalTap II Logic Analyzer. 8. Stratix GX. Select the Timing tab and click Highlight path to highlight the critical paths on your design. Click to run the Quartus II Fitter tool. 8K User defined On or Off © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Stratix III. Table 1–16. 128. Stratix IV. Table 1–16 shows the controls and parameters for the Signal Compiler block. and to program your design onto an Altera® FPGA. — Exports synthesizable HDL to a user-specified directory. 512. 16. — — — — Description The Altera device family you want to target. 1 When the source and destination in the dialog box are the same and you highlight a single block. 1k. Cyclone II. Turn on to enable use of a SignalTap II Logic Analyzer block in your design. Arria® GX. The required depth for the SignalTap II Logic Analyzer. 2K. Click to run Quartus II synthesis. Signal Compiler Block Parameters Settings Page Name Family ® Value Stratix . Cyclone III On or Off — List of ports connected to the JTAG cable. Refer to the device documentation for more information. the critical path is because of the internal function or a feedback loop. Use Board Block to Specify Device Compile Scan JTAG Program Analyze Synthesis Fitter Turn on to get the device information from the development board block. Cyclone®. Click to compile your design. 32. If you use the automated design flow. Stratix II GX. 4. the Quartus II software automatically uses the smallest device in which your design fits. 4K.

DSP Builder supports the SignalTap® II embedded logic analyzer. Table 1–17 shows the SignalTap II Logic Analyzer block parameters. Rising Edge. displayed as a waveform in a MATLAB plot. and are subsequently streamed off chip via the JTAG port with an Altera download cable. SignalTap II Logic Analyzer As programmable logic design complexity increases. Either Edge f For detailed instructions on with the SignalTap II Logic Analyzer and SignalTap II Node blocks. High. Falling Edge. which lets you capture signal activity from internal Altera device nodes while the system under test runs at speed.1–14 Chapter 1: AltLab Library SignalTap II Logic Analyzer 1 Use a Clock or Clock_Derived block to specify the clock and reset signals. Change Don’t Care. Click to select a node and use the Change button to set a trigger condition. refer to the Performing SignalTap II Logic Analysis chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. To alleviate these problems. Description SignalTap Nodes List of SignalTap II node blocks. Samples are saved to internal embedded system blocks (ESBs) when the logic analyzer is triggered. — The JTAG cable port. The captured data is then stored in a text file. Low. You use the SignalTap II Node block to select signals to monitor. and display captured waveforms. and transferred to the MATLAB workspace as a global variable. SignalTap II Logic Analyzer Block Parameters Page Name Scan JTAG Acquire Value List of ports connected to the JTAG cable. you can supplement traditional system verification with efficient board-level verification. configure memory. Click the Change button to set the specified logic condition as the trigger condition for the selected node. Use the SignalTap II Logic Analyzer block to set up event triggers. Table 1–17. Click to acquire data from the development board. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . system verification in software becomes time consuming and replicating real-world stimulus is increasingly difficult.

This alternative to HDL import gives better simulation speed. Figure 1–5.Chapter 1: AltLab Library SignalTap II Node 1–15 Figure 1–5 shows an example with the SignalTap II Node block and the SignalTap II Logic Analyzer block. The subsystem connects the inputs and outputs in the specified VHDL to HDL Input and HDL Output blocks and creates an HDL Entity block. You can also use this block if you cannot use HDL import because of unsupported megafunctions or LPMs. The SignalTap II Node block has no parameters. Subsystem Builder The Subsystem Builder block allows you to build black-box subsystems that synthesize user-supplied VHDL and simulate non-DSP Builder Simulink blocks. refer to the description of the SignalTap II Logic Analyzer block. Example SignalTap II Analysis Model SignalTap II Node Use the SignalTap II Node block with the SignalTap II Logic Analyzer block to capture signal activity from internal Altera device nodes while the system under test runs at speed. The SignalTap II Node block specifies the signals (also called nodes) for which you want to capture activity. f Refer to the Performing SignalTap II Logic Analysis chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . which you can modify if the clock and reset signals are not correctly identified. For an example of a design with the SignalTap II Logic Node block.

DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . specify the file to import. is not supported To use the Subsystem Builder block. drag and drop it into your model. is not supported input [0:7] a.c:STD_LOGIC. is not supported The Verilog HDL module should be formatted according to the following guidelines: ■ ■ ■ The Verilog HDL file should contain a single module Port direction: input or output Bus size: ■ ■ ■ input [7:0] a. The VHDL entity should be formatted according to the following guidelines: ■ ■ ■ ■ The VHDL file should contain a single entity Port direction: in or out Port type: STD_LOGIC or STD_LOGIC_VECTOR Bus size: ■ ■ ■ a(7 DOWNTO 0) is supported (0 is the LSB. is supported a. is not supported ■ Single port declaration per line: ■ ■ input [7:0] a. and maps any input ports named simulink_sclr in the VHDL entity section to the global VHDL synchronous clear signal.b. Table 1–18. and must be 0) input [8:1] a. Subsystem Builder Block Parameters Name Select HDL File Build SubSystem Value — Description Click to build a subsystem for the selected HDL file. and must be 0) a(8 DOWNTO 1) is not supported a(0 TO 7) is not supported ■ Single port declaration per line: ■ ■ a:STD_LOGIC. click Select HDL File. Table 1–18 shows the Subsystem Builder block parameters.b. User defined Browse for the VHDL or Verilog HDL file to import. and click Build.c.1–16 Chapter 1: AltLab Library Subsystem Builder The Subsystem Builder block automatically maps any input ports named simulink_clock in the VHDL entity section to the global VHDL clock signal. is correct (0 is the LSB. is correct input [7:0] a.

Info >=0 Default = 10 Description Turn on to enable automatic testbench generation. Example With the Subsystem Builder Block TestBench The TestBench block controls the generation of a testbench. Turn on to launch the ModelSim graphical user interface. Load the testbench into the ModelSim simulator. Re-run the Simulink simulation.Chapter 1: AltLab Library TestBench 1–17 Figure 1–6 shows an example with the Subsystem Builder block. Specify the maximum number of mismatches to display. Compare the Simulink and ModelSim results. Table 1–19. Enable Testbench generation On or Off © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Display ModelSim unknown values as error. TestBench Block Parameters Name Compare against HDL Generate HDL Run Simulink Run ModelSim Launch GUI Compare Results Mark ModelSim Unknowns (X’s) as Maximum number of mismatches to display Value — — — — On or Off — Error. Warning.exe) is available on your path. warnings in blue. info in green. warning. Input and output vectors are generated when you use the Compare against HDL option in the Simple tab or Run Simulink in the Advanced tab. Click to generate HDL. Table 1–19 shows the TestBench block parameters. If the ModelSim executable (vsim. Errors display in red. you can load the testbench into ModelSim and compare the results with Simulink. 1 Enabling testbench generation may slow simulation as all input and output values are stored to a file. You can optionally launch the ModelSim GUI to visually view the ModelSim simulation. run Simulink and compare the Simulink simulation results with ModelSim. or info messages. Figure 1–6. Click to generate a VHDL testbench from the Simulink model.

tcl where the path is the hierarchical path of the block in the Simulink model.vcd file. Table 1–20. That is: <model name>_<subsystem names>_<block name> each separated by underscore character. load the VCD file directly into the viewer. Run the Simulink simulation. VCD Sink Block Parameters Name Number of Inputs Value Description An integer greater than 0 Specify the number of input ports on the VCD Sink block. and displays the signals. Add a VCD Sink block to your Simulink model. Table 1–20 shows the parameters for the VCD Sink block. starts the waveform viewer. If you use any other third-party viewer. The VCD Sink block does not have any hardware representation and therefore does not appear in the VHDL RTL representation created by the Signal Compiler block.1–18 Chapter 1: AltLab Library VCD Sink VCD Sink The VCD Sink block exports Simulink signals to a third-party waveform viewer. the VCD Sink block generates a value change dump (.vcd) <VCD Sink block name>. Read the VCD file in the third-party waveform viewer. run the script <VCD Sink block path>_vcd. Simulink Model With the VCD Sink Block DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Connect the simulink signals you want to display in a third-party waveform viewer to the VCD Sink block. To use the VCD Sink block in your Simulink model. 2.wlf). If you use the ModelSim software to view waveforms. perform the following steps: 1. When you run the simulation of your model. This Tcl script converts VCD files to ModelSim waveform format (. which a third-party waveform viewer can read. 4. 3. Figure 1–7 shows an example of the VCD Sink block Figure 1–7.

Arithmetic Library The Arithmetic library contains two’s complement signed arithmetic blocks such as multipliers and adders. Some blocks have a Use Dedicated Circuitry option. The Arithmetic library contains the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Barrel Shifter Bit Level Sum of Products Comparator Counter Differentiator Divider DSP Gain Increment Decrement Integrator Magnitude Multiplier Multiply Accumulate Multiply Add Parallel Adder Subtractor Pipelined Adder Product SOP Tap Square Root Sum of Products © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . which implements functionality into dedicated hardware in the Altera FPGA devices (that is. in the dedicated DSP blocks of these devices).2.

Unsigned Integer Description The bus number format that you want to use. The Barrel Shifter block shift data to the left only. Turn off to specify the bit width of the distance port. Barrel Shifter Block Inputs and Outputs Signal a distance direction ena aclr r Direction Input Input Input Input Input Output Data input. On or Off On or Off Turn on to pipeline the barrel shifter with a latency of 3. Shift Right. Table 2–2. 1 = shift right). the design uses the full input bus width. Optional asynchronous clear. Result after shift. or in the direction specified by the optional direction input. Barrel Shifter Parameters Name Bus Type Value Signed Integer. Description Direction to shift (0 = shift left. the shifting operation preserves the input data sign for a right shift although the input sign is lost for a left shift. [number of bits]. On or Off On or Off Turn on to use the clock enable input (ena). This option is available only when the pipeline option is enabled. Table 2–2 shows the Barrel Shifter block parameters.[number of bits] Enable Pipeline Infer size of distance port from input port Bit width of distance port Shift Direction Use Enable Port Use asynchronous Clear Port >= 0 (Parameterizable) Specify the number of bits to the left of the binary point. This field is zero (0) unless Signed Fractional is selected. Enabling pipeline. that is. If you target devices that support DSP blocks. Use Dedicated Circuitry On or Off DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .2–2 Chapter 2: Arithmetic Library Barrel Shifter Barrel Shifter The Barrel Shifter block shifts the input data a by the amount set by the distance bus. increases latency and may increase the fMAX of your design. Turn on to enable the asynchronous clear input. Table 2–1. Distance to shift. The shifting operation is an arithmetic shift and not a logical shift.[] []. Optional clock enable. The Barrel Shifter block can shift data to the left (toward the MSB) or to the right (toward the LSB). Signed Fractional. The direction you want to shift the bits or specify the direction with the Use direction input pin direction input. Table 2–1 shows the Barrel Shifter block inputs and outputs. >= 0 (Parameterizable) Specify the width in bits of the distance port. >= 0 (Parameterizable) Specify the number of bits to the right of the binary point. Defaults to the size of the input port. or to the right only. turn on to implement the functionality in DSP blocks instead of logic elements. When on. Shift Left.

O1[L]. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. [1] is a single bit. Figure 2–1 shows an example with the Barrel Shifter block. For single bits.[R] is an input port. [L]. Barrel Shifter Block Example Bit Level Sum of Products The Bit Level Sum of Products block performs a sum of the multiplication of one-bit inputs by signed integer fixed coefficients. (3) I1[L]. R = 0.1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 + R2 . (3) I1[L1]. use a Bus Conversion block to set the width. (4) Explicit means that the port bit width information is a block parameter.. For signed or unsigned integers R = 0.Chapter 2: Arithmetic Library Bit Level Sum of Products 2–3 Table 2–3 shows the Barrel Shifter block I/O formats. Figure 2–1. that is..1} DOWNTO 0 Type (4) Explicit Explicit Explicit O O1[L1]. + a(n–1)Cn-1 where: ■ ■ ■ ■ q is the output result a(i) is the one-bit input data Ci are the signed integer fixed coefficients n is the number of coefficients in the range one to eight Table 2–4 on page 2–4 shows the Bit Level Sum of Products block inputs and outputs..[R1] Notes to Table 2–3: (1) For signed integers and signed binary fractional numbers. Table 2–3. To specify the bus format of an implicit input port.[R1] I2[L2].[R2] I3[1] VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 .1} DOWNTO 0) I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 . (2) [L] is the number of bits on the left side of the binary point.[0].. The Bit Level Sum of Products block uses the equation: q = a(0)C0 + . Barrel Shifter Block I/O Formats (Note 1) I/O I Simulink (2). the MSB is the sign bit. + a(i)Ci + . that is.[R] is an output port. [R] is the number of bits on the right side of the binary point.

[0] I(n+1)[1] I(n+2)[1] O O1[L0]. O1[L]. Description Table 2–6 shows the Bit Level Sum of Products block I/O formats.. Specify the coefficient values for each port as a sequence of signed integers. (2) [L] is the number of bits on the left side of the binary point. Bit Level Sum of Products Block Inputs and Outputs Signal Direction Description 1 to 8 ports corresponding to the signed integer fixed coefficient values specified in the block parameters.1} DOWNTO 0 Explicit DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . [1] is a single bit.. Result.[0] .2–4 Chapter 2: Arithmetic Library Bit Level Sum of Products Table 2–4. the coefficient values must be capable of being expressed as a double in MATLAB. that is. (4) Explicit means that the port bit width information is a block parameter. [R] is the number of bits on the right side of the binary point. Ii[1]. Bit Level Sum of Products Block I/O Formats I/O I . [L]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. In[1].[0] Notes to Table 2–6: (1) For signed integers and signed binary fractional numbers. For signed or unsigned integers R = 0.[R] is an output port. R = 0. Table 2–5. a register is added on the input signal. use a Bus Conversion block to set the width. To specify the bus format of an implicit input port. the MSB is the sign bit.[R] is an input port. that is. Optional synchronous clear. (Note 1) VHDL Type (4) Explicit Simulink (2). Ii: in STD_LOGIC . (3) I1[L].. Optional clock enable. For single bits..[0] I1: in STD_LOGIC .. Specify the bit width as a signed integer. In: in STD_LOGIC I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC O1: out STD_LOGIC_VECTOR({L0 . Bit Level Sum of Products Block Parameters Name Number of Coefficients 1–8 Coefficient Number of Bits Signed Integer Fixed-Coefficient Values Register Inputs Use Enable Port Use Synchronous Clear Port >= 1–51 (Parameterizable) User Defined (Parameterizable) On or Off On or Off On or Off Value The number of coefficients. (3) I1[1]. The bit width must be capable of being expressed as a double in MATLAB. Table 2–6... Turn on to use the synchronous clear input (sclr). a(0) to a(n–1) Input ena sclr q Input Input Output Table 2–5 shows the Bit Level Sum of Products block parameters..[0]. For example: [-21 2 13 5] When on. Turn on to use the clock enable input (ena).

signed binary or unsigned integer) and produces a single-bit output. Description Table 2–8 shows the Comparator block parameters. > b Description The operation you want to perform on the two buses. Comparator Block Inputs and Outputs Signal a b <unnamed> Direction Input Input Output Operand a. ~= b. Figure 2–2. Comparator Block Parameters Name Operator a a a a a a Value == b. Table 2–7 shows the Comparator block inputs and outputs.1} DOWNTO 0) I1: in STD_LOGIC_VECTOR({L2 + R2 . Bit Level Sum of Products Block Example Comparator The Comparator block compares two Simulink signals and returns a single bit. Table 2–9 shows the Comparator block I/O formats. <= b. Table 2–7.[R1] I2[L2]. >= b. Table 2–9. (3) I1[L1].Chapter 2: Arithmetic Library Comparator 2–5 Figure 2–2 shows an example with the Bit Level Sum of Products block. Result. Table 2–8. < b.[R2] VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . The Comparator block implicitly understands the input data type (for example.1} DOWNTO 0) Type (4) Implicit Implicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Operand b. Comparator Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2).

[R] is the number of bits on the right side of the binary point. (Disables counting and sload. For each cycle.[R] is an output port. For single bits.[R] is an input port. sclr signals. Table 2–10 shows the Counter block inputs and outputs. O1[L].) Optional counter enable. Signed Fractional >= 0 (Parameterizable) Description The bus number format that you want to use for the counter.[] Value Signed Integer. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Specify the number of bits to the left of the binary point. sset. For signed or unsigned integers R = 0. (2) [L] is the number of bits on the left side of the binary point.) Optional synchronous clear. the counter increments or decrements its output by the smallest amount that DSP Builder can represent with the selected bus type. use a Bus Conversion block to set the width. (4) Explicit means that the port bit width information is a block parameter. that is. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. that is. Table 2–11. R = 0.2–6 Chapter 2: Arithmetic Library Counter Table 2–9. (Loads zero into the counter. Optional synchronous set port. Counter Block Parameters (Part 1 of 2) Name Bus Type [number of bits].[0]. Unsigned Integer. Figure 2–3. [1] is a single bit. Optional clock enable. and sclr signals. the MSB is the sign bit. Comparator Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2). 0 = down). Optional synchronous load signal. Table 2–10.) Result. (3) I1[L]. Comparator Block Example Counter The Counter block is an up/down counter. To specify the bus format of an implicit input port. (3) O1[1] O1: out STD_LOGIC VHDL Type (4) Implicit Notes to Table 2–9: (1) For signed integers and signed binary fractional numbers. Counter Block Inputs and Outputs Signal data sload sset updown clk_ena ena sclr q Direction Input Input Input Input Input Input Input Output Optional parallel data input. [L]. sset. (Disables counting but not sload.) Optional direction (1 = up. (Loads the specified constant value into the counter. Description Table 2–11 shows the Counter block parameters. Figure 2–3 shows an example with the Comparator block.

Specify the maximum count plus 1. For single bits.Chapter 2: Arithmetic Library Counter 2–7 Table 2–11. This option is not available for bit widths greater than 31. This field is ignored unless Signed Fractional selected. (2) [L] is the number of bits on the left side of the binary point. Use Direction Port (updown) On or Off On or Off User defined On or Off On or Off On or Off Description Specify the number of bits to the right of the binary point. [R] is the number of bits on the right side of the binary point.[number of bits] Use Modulo Count Modulo Specify Clock Clock Counter Direction Use Synchronous Load Ports Use Synchronous Set Port Set Value Use Clock Enable Port Use Counter Enable Port Use Synchronous Clear Port Value >= 0 (Parameterizable) On or Off User defined (Parameterizable) On or Off User defined Increment. Turn on to use the synchronous clear input (sclr). For signed or unsigned integers R = 0. [1] is a single bit. Turn on to use the counter enable input (ena). Decrement. Specify the clock signal name. This value must be less than the Count Modulo value (if used). that is. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Turn on to explicitly specify the clock name. Table 2–12 shows the Counter block I/O formats.[R] is an input port. Turn on to enable the Count Modulo parameter. Turn on to use the synchronous load inputs (data.[R]] I2[1] I3[1] I4[1] I5[1] I6[1] O O1[L]. Counter Block I/O Formats I/O I Simulink (2).[R] is an output port. Turn on to use the clock enable input (clk_ena). the MSB is the sign bit.[0]. use a Bus Conversion block to set the width. This option is not available for bit widths greater than 31. Counter Block Parameters (Part 2 of 2) Name []. that is. Specify the constant value loaded when the design uses the sset input. (4) Explicit means that the port bit width information is a block parameter.1} DOWNTO 0) Explicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . R = 0. (3) I1[L]. sload). This represents the number of unique states in the counter’s cycle. (Note 1) VHDL Type (4) Explicit I1: in STD_LOGIC_VECTOR({L + R . Turn on to use the synchronous set input (sset). The direction you want to count or specify the direction with the direction input. (3) I1[L]. O1[L].1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC I6: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R .[R] Notes to Table 2–12: (1) For signed integers and signed binary fractional numbers. [L]. Table 2–12. To specify the bus format of an implicit input port.

Value Specify the number of bits. the MSB is the sign bit. Use this block for DSP functions such as CIC filters. use a Bus Conversion block to set the width. Description Table 2–14 shows the Differentiator block parameters. Table 2–13 shows the Differentiator block inputs and outputs.1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 . [L]. Optional clock enable. [R] is the number of bits on the right side of the binary point.1} DOWNTO 0) Explicit DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Table 2–14. Table 2–15. Turn on to use the synchronous clear input (sclr). that is. Optional synchronous clear. Differentiator Block I/O Formats I/O I Simulink (2). Differentiator Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Data input. Description Use Synchronous Clear Port On or Off Table 2–15 shows the Differentiator block I/O formats.[R] is an output port. O1[L]. For single bits. R = 0.[0] Notes to Table 2–15: (1) For signed integers and signed binary fractional numbers. Table 2–13.[0]. Result. For signed or unsigned integers R = 0.d(n-D) where D is the delay parameter. (4) Explicit means that the port bit width information is a block parameter. (3) I1[L]. (Note 1) VHDL Type (4) Explicit I1: in STD_LOGIC_VECTOR({L1 . that is.[0] I2[1] I3[1] O O1[L1]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port. Differentiator Block Parameters Name Number of Bits Depth Use Enable Port >= 1 (Parameterizable) Any positive number (Parameterizable) On or Off Specify the depth of the differentiator register. The equation 1-z-D describes the transfer function that the Differentiator block implements. Turn on to use the clock enable input (ena).2–8 Chapter 2: Arithmetic Library Differentiator Differentiator The Differentiator block is a signed integer differentiator with the equation: q(n) = d(n) . (2) [L] is the number of bits on the left side of the binary point.[R] is an input port. (3) I1[L1]. [1] is a single bit.

Table 2–16. Denominator. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Table 2–17. Optional asynchronous clear.[] Specify the number of bits to the left of the binary point. Table 2–16 shows the Divider block inputs and outputs. 1 Dividing a maximally negative number by a minimally negative one (-1 if using signed integers). Divider Block Inputs and Outputs Signal a b ena aclr q r Direction Input Input Input Input Output Output Numerator. Figure 2–4. The numerator and denominator inputs can have different widths but convert to the specified bit width. Optional clock enable. Signed Fractional. Differentiator Block Example Divider The Divider block takes a numerator and a denominator and returns the quotient and a remainder with the equation: a = b × q + r. outputs a truncated answer. Description Table 2–17 shows the Divider block parameters. Quotient. Remainder. [number of bits].Chapter 2: Arithmetic Library Divider 2–9 Figure 2–4 shows an example with the Differentiator block. q and r are undefined if b is zero. Divider Block Parameters (Part 1 of 2) Name Bus Type Value Signed Integer. Unsigned Integer >= 0 (Parameterizable) Description The bus number format that you want to use for the divider.

This option applies only to signed fractional formats. [1] is a single bit.[number of bits] Number of Pipeline Stages Use Enable Port Use Asynchronous Clear Port Value >= 0 (Parameterizable) 0 to number of bits (Parameterizable) On or Off On or Off Description Specify the number of bits to the right of the binary point. It is equivalent to the Multiply Add block but exposes extra features (including chaining) that are available only on Stratix IV and Stratix III DSP blocks. For single bits.[R] Explicit Explicit Notes to Table 2–18: (1) For signed integers and signed binary fractional numbers. R = 0. The clock enable and asynchronous clear ports are available only if the block is registered (that is.1} DOWNTO 0) O2: out STD_LOGIC_VECTOR({L + R .1} DOWNTO 0) Type (4) Explicit Explicit O O1[L]. The second and fourth multiplier outputs can optionally be added or subtracted from the total.[R] I2[L].2–10 Chapter 2: Arithmetic Library DSP Table 2–17. Divider Block Parameters (Part 2 of 2) Name []. if the number of pipeline stages is greater than or equal to 1).[R] is an input port.1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. The operands in each pair are multiplied together.1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R . use a Bus Conversion block to set the width. To specify the bus format of an implicit input port. Turn on to use the asynchronous clear input (aclr).[0]. that is. Figure 2–5. Divider Block Example DSP The DSP block consists of one to four multipliers feeding a parallel adder. Divider Block I/O Formats (Note 1) I/O I Simulink (2). Table 2–18. (3) I1[L]. (4) Explicit means that the port bit width information is a block parameter.[R] O2[L].[R] I3[1] I4[1] VHDL I1: in STD_LOGIC_VECTOR({L + R . [L]. O1[L]. For signed or unsigned integers R = 0. The DSP block accepts one to four pairs of multiplier inputs a and b. adds pipeline stages to increase the data throughput. Table 2–18 shows the Divider block I/O formats. (2) [L] is the number of bits on the left side of the binary point. (3) I1[L].[R] is an output port. Figure 2–5 shows an example with the Divider block. Turn on to use the clock enable input (ena). the MSB is the sign bit. When non-zero. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . [R] is the number of bits on the right side of the binary point. that is.

Optional clock enable. (1) Optional reset to zero for the chainout value. Do not use for any other signal. you can optionally enable a chainout adder output (chainout) instead of the normal output (res). (Replaces the res output when enabled. Optional accumulator synchronous load input. refer to the altmult_add Megafunction User Guide. Optional shift out from A input of last multiplier. Direction Input Input Input Input Input Input Output Output Output Output Operand a. Optional asynchronous clear. Only drive this chainin port from the chainout output of a DSP block at the preceding stage.Chapter 2: Arithmetic Library DSP 2–11 The following equation expresses the block function: res = a0×b0 ± a1×b1 [+ a2×b2 [± a3×b3]] [+ chainin] If there are four multipliers and the input bit widths are both less than or equal to 18. Optional chainout output.) zero_chainout Input © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Optional saturation overflow output. Other features include: ■ ■ ■ ■ ■ ■ ■ ■ Parameterizable input and output data widths Optional asynchronous clear and clock enable inputs Optional accumulator synchronous load input Optional shiftin instead of an a input Optional shift out from the a input of the last multiplier Optional saturation overflow outputs Optional registers to pipeline the adder and chainout adder Optional accumulator mode f For more information about multiplier or adder operations. DSP Block Inputs and Outputs Signal a0—a3 b0—b3 ena chainin aclr accum_sload res shiftouta overflow chainout Note to Table 2–19: (1) Use the chainin port to feed the adder result (chainout) from a previous stage. Table 2–19 shows the DSP block inputs and outputs. Result. Table 2–19. If there are four multipliers and the input bit widths are both equal to 18. Operand b. Description Optional input bus from the preceding stage. you can enable a chainout adder input (chainin).

Figure 2–7. rounding and saturation enabled. a chainout adder and saturation overflow outputs. Basic 2-Input Multiplier or Adder Figure 2–7 shows a 4-input multiplier or adder with shiftin inputs. registered outputs. 4-Input Multiplier or Adder with Chainout Adder DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Figure 2–6.2–12 Chapter 2: Arithmetic Library DSP Figure 2–6 shows a basic multiplier or adder with two inputs where the product is subtracted.

Add or subtract the product of the second multiplier pair. Unsigned Integer. Nearest Even You can disable rounding (truncate). round to the nearest integer or round to the nearest even. (Parameterizable) This option applies only to signed fractional formats. The number format you want to use for the bus.[number of bits] >= 0 Specify the number of data a input bits to the right of the binary point. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . b Inputs []. you can select the accumulator direction and use the optional accum_sload input. This option is available only if the input bit widths are less than or equal to 18 and the number of multipliers is 4. SUB On or Off On or Off On or Off On or Off On or Off Specify the number of data output bits to the left of the binary point.[number of bits] >= 0 Specify the number of data b input bits to the right of the binary point. SUB On or Off Turn on to connect the multiplier input a to shiftin from the previous multiplier. (Parameterizable) including the sign bit. Add or subtract the product of the first multiplier pair. you can specify a different output width. Add or subtract values in the accumulator. DSP Block Parameters (Part 1 of 2) Name Number of Multipliers Bus Type Value 1. Accumulator Direction Use Accumulator Synchronous Load Input Use Chainout Adder Input (chainin) Use Chainout Adder Output (chainout) Use Zero Chainout Input Full Resolution for Output Result Output [number of bits]. When on. a Inputs []. 2. a Inputs [number of bits]. Turn on to enable accumulator mode. 4 Signed Integer. Nearest Integer.[] >= 0 Specify the number of data a input bits to the left of the binary point. the multiplier output bit width is full resolution. Turn on to use the chainin input for the chainout adder to add the result from a previous stage. (Parameterizable) This option applies only to signed fractional formats. Rounding and saturation are available for certain input/output type combinations. >= 0 (Parameterizable) including the sign bit. (Parameterizable) including the sign bit. Connect Multiplier Input a to shiftin Use Shiftout from a Input of Last Multiplier Output Operation on First Multiplier Pair Output Operation on Second Multiplier Pair Enable Accumulator Mode On or Off On or Off ADD. 3.[] Output []. Turn on to use the zero_chainout input. SUB ADD.) Turn on to create a shiftouta output from the a input of the last multiplier. Table 2–20. which dynamically sets the chainout value to zero. >= 0 Specify the number of data output bits to the right of the binary point. Signed Fractional Description The number of multipliers you want to feed the adder. (Parameterizable) This option applies only to signed fractional formats.[number of bits] Output Rounding Operation Type ADD. b Inputs [number of bits]. This option is available only if the input bit widths are less than or equal to 18 and the number of multipliers is 4. When this option is on. When off. The design uses separate inputs for each multiplier. Turn on to use the chainout output from the chainout adder output instead of the res output. None (truncate). Turn on to use the optional accum_sload input.[] >= 0 Specify the number of data b input bits to the left of the binary point.Chapter 2: Arithmetic Library DSP 2–13 Table 2–20 shows the DSP block parameters.

) Turn on to create a register at the output of the chainout adder (if it is used). output rounding with an output LSB in the range 6 to 21. Symmetric. I1: in STD_LOGIC_VECTOR({L1 + R1 .. use a Bus Conversion block to set the width. DSP Block Parameters (Part 2 of 2) Name Output Saturation Operation Type Value None (wrap). that is.1} DOWNTO 0) In: in STD_LOGIC_VECTOR({L1 + R1 . (3) I1[L]. Asymmetric Description You can disable (wrap). For signed or unsigned integers R = 0. Explicit Simulink (2).1} DOWNTO 0) Implicit Notes to Table 2–21: (1) For signed integers and signed binary fractional numbers.) Turn on to create a register at the data output from the multiplier. or enable saturation. O1[L]. Turn on to create registers at the data inputs to the multiplier. [R] is the number of bits on the right side of the binary point. For single bits. Table 2–21.1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC where 3 < n < 9 O1: out STD_LOGIC_VECTOR({(2 x L1) + ceil(log2(n)) + (2 x R1) .2 x [R1] (Note 1) VHDL Type (4) Explicit ..[R1] I(n+1)[1] I(n+2)[1] where 3 < n < 9 O O12 x [L1]+ ceil(log2(n)). R = 0. Table 2–21 shows the DSP block I/O formats. Asymmetric saturation specifies that the absolute value of the maximum negative number is 1 greater than the maximum positive number. Use Output Overflow Port Register Data Inputs to the Multiplier(s) Register Output of the Multiplier Register Output of the Adder Register Chainout Adder Register Shiftout Use Enable Port Use User Asynchronous Clear Port On or Off On or Off On or Off On or Off On or Off On or Off On or Off On or Off 1 Compilation in the Quartus II software requires that the input bit widths are 18 bits when you use the chainout adder input. Turn on to use the clock enable input (ena) if using registers. In[L1]. [1] is a single bit. Turn on to create a register at the output of the adder. To specify the bus format of an implicit input port. the MSB is the sign bit. Do not enable rounding unless you have enabled saturation. (3) I1[L1]. Registers the shiftouta output (if it is used). DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .[0].[R] is an input port. (Always on if accumulator mode is enabled. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.2–14 Chapter 2: Arithmetic Library DSP Table 2–20. that is. (Always on if in shiftin mode. Turn on to use the asynchronous clear input (aclr) if using registers. or output saturation with an output MSB in the range 28 to 43. Turn on to use the overflow output for the saturation unit.[R1] …. Symmetric saturation specifies that the absolute value of the maximum negative number is equal to the maximum positive number. (2) [L] is the number of bits on the left side of the binary point. (4) Explicit means that the port bit width information is a block parameter.[R] is an output port. [L]. DSP Block I/O Formats I/O I ….

you can use it only for simulation. The gain factor must be a scalar. You must enter the gain as a numeric value in the Gain block parameter field. Table 2–22 shows the Gain block inputs and outputs. Gain Block Inputs and Outputs Signal d ena aclr <unnamed> Direction Input Input Input Output Data input.Chapter 2: Arithmetic Library Gain 2–15 Figure 2–8 shows an example of a basic low-pass filter with two DSP blocks. Signal Compiler cannot convert it to HDL. If you use the Simulink Gain block in your model. Table 2–22. Figure 2–8. Optional clock enable. Optional asynchronous clear. Description © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . DSP Block Example Gain The Gain block generates its output by multiplying the signal input by a specified gain factor. Result. 1 The Simulink software also provides a Gain block.

if the number of pipeline stages is greater than or equal to 1).[] >= 0 Specify the number of bits to the left of the binary point. including the (Parameterizable) sign bit. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). (3) I1[L1]. This option (Parameterizable) applies only to signed fractional formats. Gain Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2). Table 2–24. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. Signed Fractional. When on.[R1] I2[1] I3[1] I2: in STD_LOGIC I3: in STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . Unsigned Integer [Gain value number of bits]. The Clock Phase Selection and (Parameterizable) Optional Ports options are available only if the block is registered (that is. 3.1} DOWNTO 0) Type Implicit (4) DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . []. Gain Block Parameters Name Gain Value Value User Defined Description Specify the gain value you want to use as a decimal number (or an expression that evaluates to a decimal number). The gain is masked to the number format (bus type) you select. Turn on to use the asynchronous clear input (aclr). The bus number format you want to use for the gain value. Number of Pipeline Stages >= 0 The number of pipeline delay stages.2–16 Chapter 2: Arithmetic Library Gain Table 2–23 shows the Gain block parameters. and 4 do not pass through the block. Map Gain Value to Bus Type Signed Integer. Table 2–23. Use Asynchronous Clear Port On or Off Clock Phase Selection Table 2–24 shows the Gain block I/O formats. This parameter is for synthesis. User Defined Specify the phase selection with a binary string. Use Enable Port Use LPM On or Off On or Off Turn on to use the clock enable input (ena). where a 1 indicates the phase in which the block is enabled. That is. the Gain block is mapped to the LPM_MULT library of parameterized modules (LPM) function and the VHDL synthesis tool uses the Altera LPM_MULT implementation. the data on phases 1.[Gain value number of bits] >= 0 Specify the number of bits to the right of the binary point.

unsigned integer. (Parameterizable) []. Increment Decrement Block Parameters (Part 1 of 2) Name Bus Type Value Description Signed Integer.<number of bits> >= 0 Select the number of bits to the right of the binary point. Increment Decrement Block Inputs and Outputs Signal ena sclr c Direction Input Input Output Optional clock enable. Result.[R] is an output port. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . For single bits. [1] is a single bit. [L]. the value always changes by 1. The output is a signed integer. Optional synchronous clear. (3) O1[L1 + LK]. Table 2–25. The number format you want to use for the bus. that is. Unsigned Integer <number of bits>.RK)-1} DOWNTO 0) Type Implicit Notes to Table 2–24: (1) For signed integers and signed binary fractional numbers. (5) K is the gain constant with the format K[LK].RK)] (5) VHDL O1: out STD_LOGIC_VECTOR({L1+LK+2*max(R1. including the sign bit. Gain Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2). Gain Block Example Increment Decrement The Increment Decrement block increments or decrements a value in time.[0].2*max(R1. that is. Table 2–25 shows the Increment Decrement block inputs and outputs. This option applies only (Parameterizable) to signed fractional formats. O1[L].[RK] Figure 2–9 shows an example with the Gain block. For signed or unsigned integers R = 0. To specify the bus format of an implicit input port.[R] is an input port. the MSB is the sign bit. Table 2–26. Signed Fractional. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. for integer types. For all number formats.Chapter 2: Arithmetic Library Increment Decrement 2–17 Table 2–24. the counting sequence increases or decreases by the smallest representable value. use a Bus Conversion block to set the width. R = 0. [R] is the number of bits on the right side of the binary point. or signed binary fractional number. Figure 2–9.[] >= 0 Select the number of bits to the left of the binary point. Description Table 2–26 shows the Increment Decrement block parameters. (3) I1[L]. (2) [L] is the number of bits on the left side of the binary point.

2–18

Chapter 2: Arithmetic Library Increment Decrement

Table 2–26. Increment Decrement Block Parameters (Part 2 of 2) Name Direction Starting Value Clock Phase Selection Value Increment, Decrement Count up or down. Description

User Defined Enter the value with which to begin counting. This value is the initial output value (Parameterizable) of the block after a reset. User Defined Specify the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block.

Specify Clock Clock Use Enable Port Use Synchronous Clear Port

On or Off User defined On or Off On or Off

Turn on to explicitly specify the clock name. Specify the clock signal name. Turn on if you want to use the clock enable input (ena). Turn on if you want to use the synchronous clear input (sclr).

Table 2–27 shows the Increment Decrement block I/O formats.
Table 2–27. Increment Decrement Block I/O Formats (Note 1) I/O I O Simulink (2), (3) I1[1] I2[1] O1[LP].[RP]
Notes to Table 2–27:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

VHDL I1: in STD_LOGIC I2: in STD_LOGIC O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)

Type (4)

Explicit

Figure 2–10 shows an example with the Increment Decrement block.
Figure 2–10. Increment Decrement Block Example

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Chapter 2: Arithmetic Library Integrator

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Integrator
The Integrator block is a signed integer integrator with the equation: q(n+D) = q(n) + d(n) where D is the delay parameter. Use this block for DSP functions such as CIC filters. The equation z-D/(1-z-D) describes the transfer function that the Integrator block implements. This behavior of this transfer function is slightly different from the more typical 1/(1-z-D). Figure 2–11 shows the block diagrams for these functions.
Figure 2–11. Integrator Transfer Functions

The magnitude response of these two functions is the same although their phase response is different. For the typical integrator function, 1/(1-z-D), there is an impulse on the output at time = 0, whereas the output delays by a factor of D for the z-D/(1-z-D) function that the DSP Builder integrator uses. This behavior effectively registers the output and gives a better Fmax performance compared to the typical function where if you chained a row of n integrators together, it is equivalent to n unregistered adder blocks in a row, and is slow in hardware. Table 2–28 shows the Integrator block inputs and outputs.
Table 2–28. Integrator Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Data input. Optional clock enable. Optional synchronous clear. Result. Description

Table 2–29 shows the Integrator block parameters.
Table 2–29. Integrator Block Parameters Name Number of Bits Depth Value >= 1 (Parameterizable) A positive number (Parameterizable) Specify the number of bits. Specify the depth of the integrator register. Description

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Chapter 2: Arithmetic Library Magnitude

Table 2–29. Integrator Block Parameters Name Use Enable Port Value On or Off Description Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr).

Use Synchronous Clear Port On or Off

Table 2–30 shows the Integrator block I/O formats.
Table 2–30. Integrator Block I/O Formats I/O I Simulink (2), (3) I1[L1].[0] I2[1] I3[1] O O1[L1].[0]
Notes to Table 2–30:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

(Note 1) VHDL Type (4) Explicit

I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0) I2: STD_LOGIC I3: STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)

Explicit

Figure 2–12 shows an example of the Integrator Block.
Figure 2–12. Integrator Block Design Example

Magnitude
The scalar Magnitude block returns the absolute value of the incoming signed binary fractional bus. The Magnitude block has no parameters. Table 2–31 shows the Magnitude block I/O formats.
Table 2–31. Magnitude Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2), (3) I1[L1].[R1] VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Implicit

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Chapter 2: Arithmetic Library Multiplier

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Table 2–31. Magnitude Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[L1].[R1] VHDL O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Implicit

Notes to Table 2–31:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

Figure 2–13 shows an example with the Magnitude block.
Figure 2–13. Magnitude Block Example

Multiplier
The Multiplier block supports two scalar inputs (no multidimensional Simulink signals). Operand a is multiplied by operand b and the result r output as the following equation shows: r=a×b The differences between the Multiplier block and the Product block are:

The Product block supports clock phase selection while the Multiplier block does not. The Product block uses implicit input port data widths that it inherits from the signals’ sources, whereas the Multiplier block uses explicit input port data widths that you must specify as parameters. The Product block allows you to use the LPM multiplier megafunction, whereas the Multiplier block always uses the LPM.

Table 2–32 shows the Multiplier block inputs and outputs.
Table 2–32. Multiplier Block Inputs and Outputs Signal a b ena aclr r Direction Input Input Input Input Output Operand a. Operand b. Optional clock enable. Optional asynchronous clear. Result r. Description

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Chapter 2: Arithmetic Library Multiplier

Table 2–33 lists the parameters for the Multiplier block.
Table 2–33. Multiplier Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) On or Off Description The bus number format to use for the Multiplier block.

Input [number of bits].[] Input [].[number of bits]

Specify the number of bits to the left of the binary point for input a (or both input signals if set to have the same width). Specify the number of bits to the right of the binary point for input a (or both input signals if set to have the same width). This option applies only to signed fractional formats. The number of pipeline stages. The ena and aclr ports are available only if the block is registered (that is, if the number of pipeline stages is greater than or equal to 1). Turn on if you want input a and input b to have the same bit width. When off, additional fields are available to specify the number of bits to the left and right of the binary point for input b. Specify the number of bits to the left of the binary point for input b. Specify the number of bits to the right of the binary point for input b. This option applies only to signed fractional formats. When on, the multiplier output bit width is full resolution. When off, you can specify the number of bits for the output. Specify the number of MSBs in the output for an integer bus. Specify the number of LSBs in the output for an integer bus. Specify the number of bits to the left of the binary point for the output r. This option applies only to signed fractional formats. Specify the number of bits to the left of the binary point for the output r. This option applies only to signed fractional formats. Use dedicated multiplier circuitry (if supported by your target device). A value of AUTO means that the Quartus II software uses the dedicated multiplier circuitry based on the width of the multiplier. Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (aclr).

Number of Pipeline Stages

Both Inputs Have Same Bit Width Input b [number of bits].[] Input b [].[number of bits] Full Resolution for Output Result Output MSB Output LSB Output [number of bits].[] Output [].[number of bits] Use Dedicated Circuitry

>= 0 (Parameterizable) >= 0 (Parameterizable) On or Off >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) AUTO, YES, NO

Use Enable Port Use Asynchronous Clear Port

On or Off On or Off

Table 2–34 shows the Multiplier block I/O formats.

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Table 2–34. Multiplier Block Input/Output Ports (Note 1) I/O I Simulink (2), (3) I1[L].[R] I2[L].[R] I3[1] I4[1] O O1[Lo].[Ro] O2[Lo].[Ro]
Notes to Table 2–34:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

VHDL I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0) I3: STD_LOGIC I4: STD_LOGIC O1: out STD_LOGIC_VECTOR({Lo + Ro - 1} DOWNTO 0) O2: out STD_LOGIC_VECTOR({Lo + Ro - 1} DOWNTO 0)

Type (4) Explicit Explicit

Explicit Explicit

Figure 2–14 shows an example with the Multiplier block.
Figure 2–14. Multiplier Block Example

f

For more information about multiplier operations, refer to the Multiplier Megafunction User Guide.

Multiply Accumulate
The Multiply Accumulate block consists of a single multiplier feeding an accumulator, which performs the calculation y += a × b. The input is signed integer, unsigned integer, or signed binary fractional formats. Table 2–35 shows the Multiply Accumulate block inputs and outputs.
Table 2–35. Multiply Accumulate Block Inputs and Outputs (Part 1 of 2) Signal a b sload addsub Direction Input Input Input Input Operand A. Operand B. Synchronous load signal. Optional accumulator direction (1= add, 0 = subtract). Description

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Chapter 2: Arithmetic Library Multiply Accumulate

Table 2–35. Multiply Accumulate Block Inputs and Outputs (Part 2 of 2) Signal ena aclr y Direction Input Input Output Optional clock enable. Optional asynchronous clear. Result. Description

Table 2–36 shows the Multiply Accumulate block parameters.
Table 2–36. Multiply Accumulate Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer Description The number format you want to use for the bus.

Input A [number of bits].[] >= 0 (Parameterizable) Input A [].[number of bits] >= 0 (Parameterizable) Input B [number of bits].[] >= 0 (Parameterizable) Input B [].[number of bits] >= 0 (Parameterizable) Output Result number of bits Pipeline Register >= 0 (Parameterizable) None, Data Inputs, Multiplier Output, Data Inputs and Multiplier AUTO, YES, NO

Specify the number of data input bits to the left of the binary point for operand A, including the sign bit. Specify the number of data input bits to the right of the binary point for operand A. This option applies only to signed fractional formats. Specify the number of data input bits to the left of the binary point for operand B, including the sign bit. Specify the number of data input bits to the right of the binary point for operand B. This option applies only to signed fractional formats. Specify the number of output bits. Add pipelining to the data inputs, multiplier output, both, or neither.

Use Dedicated Multiplier Circuitry

Select AUTO to automatically implement the functionality in DSP blocks. Select YES or NO to explicitly enable or disable this option. If your target device does not support DSP blocks or you select NO, the functionality implements in logic elements. Add or subtract the result of the multiplier. Turn on to use the direction input (addsub). Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).

Accumulator Direction Use Add/Subtract Port Use Enable Port Use Asynchronous Clear Port

Add, Subtract On or Off On or Off On or Off

Table 2–37 shows the Multiply Accumulate block I/O formats.

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Chapter 2: Arithmetic Library Multiply Add

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Table 2–37. Multiply Accumulate Block I/O Formats (Note 1) I/O I Simulink (2), (3) I1[L1].[R1] I2[L2].[R2] I3[1] I4[1] I5[1] I6[1] O O1[LO].[RO]
Notes to Table 2–37:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC I6: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L0 + R0 - 1} DOWNTO 0)

Type (4) Explicit Explicit

Explicit

The sload input controls the accumulator feedback path. If the accumulator is adding and sload is high, the multiplier output is loaded into the accumulator. If the accumulator is subtracting, the opposite (negative value) of the multiplier output is loaded into the accumulator. Figure 2–15 shows an example with the Multiply Accumulate block.
Figure 2–15. Multiply Accumulate Block Example

Multiply Add
The Multiply Add block consists of two, three, or four multiplier pairs feeding a parallel adder. The operands in each pair are multiplied together and the second and fourth multiplier outputs can optionally be added to or subtracted from the total. The following equation expresses the block function: y = a0×b0 ± a1×b1 [+ a2×b2 [± a3×b3]]] The operand b inputs can optionally be hidden and instead have constant values assigned in the Block Parameters dialog box. The input is a signed integer, unsigned integer, or signed binary fractional formats. Table 2–38 shows the Multiply Add block inputs and outputs.

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Chapter 2: Arithmetic Library Multiply Add

Table 2–38. Multiply Add Block Inputs and Outputs Signal a0—a3 b0—b3 ena aclr y Direction Input Input Input Input Output Operand a. Operand b. Optional clock enable. Optional asynchronous clear Result. Description

Table 2–39 shows the Multiply Add block parameters.
Table 2–39. Multiply Add Block Parameters Name Number of Multipliers Bus Type 2, 3, 4 Signed Integer, Signed Fractional, Unsigned Integer (Parameterizable) Input [].[number of bits] >= 0 (Parameterizable) Adder Mode Add Add, Add Sub, Sub Add, Sub Sub Value Description The number multipliers you want to feed the adder. The number format you want to use for the bus.

Input [number of bits].[] >= 0

Specify the number of data input bits to the left of the binary point, including the sign bit. Specify the number of data input bits to the right of the binary point. This option applies only to signed fractional formats. The operation mode of the adder.
■ ■ ■ ■

Add Add: Adds the products of each multiplier. Add Sub: Adds the second product and subtracts the fourth. Sub Add: Subtracts the second product and adds the fourth. Sub Sub: Subtracts the second and fourth products.

Pipeline Register

No Register, Inputs Only, The elements to pipeline. The clock enable and asynchronous clear Multiplier Only, Adder Only, ports are available only if the block is registered. Inputs and Multiplier, Inputs and Adder, Multiplier and Adder, Inputs Multiplier and Adder On or Off If you target devices that support DSP blocks, turn on to implement the functionality in DSP blocks instead of with logic elements. This option is not available if you select the Unsigned Integer bus type. Turn on to assign the operand b inputs to constant values. Use this option with the Constant Values parameter but is not available when you enable Use Dedicated Circuitry. Type the constant values in this box as a MATLAB array. This option is available only if One Input is Constant is on. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).

Use Dedicated Circuitry

One Input is Constant

On or Off

Constant Values Use Enable Port Use Asynchronous Clear Port

User Defined On or Off On or Off

Table 2–40 shows the Multiply Add block I/O formats.

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Table 2–40. Multiply Add Block I/O Formats I/O I …. Ii[L1].[R1] … In[L1].[R1] I(n+1)[1] I(n+2)[1] where 3 < n < 9 O O12 x [L1]+ ceil(log2(n)).2 x
[R1]

(Note 1) VHDL Type (4) Explicit ... Explicit ... Explicit

Simulink (2), (3) I1[L1].[R1] …

I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Ii: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) …. In: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC where 3 < n < 9

O1: out STD_LOGIC_VECTOR({(2 x L1) + ceil(log2(n)) + (2 x R1) - 1} DOWNTO 0) Implicit

Notes to Table 2–40:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

Figure 2–16 shows an example with the Multiply Add block.
Figure 2–16. Multiply Add Block Example

Parallel Adder Subtractor
The Parallel Adder Subtractor block takes any input data type. If the input widths are not the same, Signal Compiler sign extends the buses so that they match the largest input width. The generated VHDL has an optimized, balanced adder tree. Table 2–41 shows the Parallel Adder Subtractor block inputs and outputs.

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Chapter 2: Arithmetic Library Parallel Adder Subtractor

Table 2–41. Parallel Adder Subtractor Block Inputs and Outputs Signal data0–dataN ena aclr r Direction Input Input Input Output Operands. Optional clock enable. Optional asynchronous clear Result. Description

Table 2–42 shows the Parallel Adder Subtractor block parameters.
Table 2–42. Parallel Adder Subtractor Block Parameters Name Number of Inputs Add (+) Sub (–) Value >= 2 User Defined Description The number of inputs you want to use. Specify addition or subtraction operation for each port with the operators + and –. For example + – + implements a – b + c for 3 ports. However, two consecutive subtractions, (– –) are not legal. Missing operators are assumed to be +. When on, DSP Bu idler registers the output from each stage in the adder tree, resulting in a pipeline length that is equal to ceil(log2(number of inputs)). When you enable a pipeline, you can indicate the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block. Use Enable Port Use Asynchronous Clear Port On or Off On or Off Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr).

Enable Pipeline

On or Off

Clock Phase Selection User Defined

Table 2–43 shows the Parallel Adder Subtractor block I/O formats.
Table 2–43. Parallel Adder Subtractor Block I/O Formats (Part 1 of 2) (Note 1) I/O I …. Ii[Li].[LiI] … In[Ln].[Rn] I(n+1)[1] I(n+2)[1] Simulink (2), (3) I1[L1].[R1] … Ii: in STD_LOGIC_VECTOR({Li + Ri - 1} DOWNTO 0) …. In: in STD_LOGIC_VECTOR({Ln + Rn - 1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) Type (4) Implicit ... Implicit ... Implicit

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Table 2–43. Parallel Adder Subtractor Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2), (3) O1[max(Li) +
ceil(log2(n))].[max(Ri)]

VHDL

Type (4)

O1: out STD_LOGIC_VECTOR({max(Li) + ceil(log2(n)) + max(Ri) - 1} DOWNTO 0) Implicit

Notes to Table 2–43:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

Figure 2–17 shows an example with the Parallel Adder Subtractor block.
Figure 2–17. Parallel Adder Subtractor Block Example

Pipelined Adder
The Pipelined Adder block is a pipelined adder and subtractor that performs the following calculation: r = a + b + cin (when addsub = 1) r = a - b + cin -1 (when addsub = 0) Use the optional ovl port an overflow with signed arithmetic or as a carry out with unsigned arithmetic. For unsigned subtraction, the output is 1 when no overflow occurs. Table 2–44 shows the Pipelined Adder block inputs and outputs.
Table 2–44. Pipelined Adder Block Inputs and Outputs Signal a b cin addsub ena aclr r ovl Direction Input Input Input Input Input Input Output Output Operand a. Operand b. Optional carry in. Optional control (1= add, 0 = subtract). Optional clock enable. Optional asynchronous clear. Result r. Optional overflow (signed) or carry out (unsigned). Description

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Chapter 2: Arithmetic Library Pipelined Adder

Table 2–45 shows the Pipelined Adder block parameters.
Table 2–45. Pipelined Adder Block Parameters Name Bus Type Value Signed Integer, Signed Fractional, Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) ADD, SUB On or Off On or Off On or Off On or Off On or Off Description The bus number format that you want to use.

[number of bits].[] [].[number of bits] Number of Pipeline Stages Direction Use Enable Port Use Asynchronous Clear Port Use Carry In Port Use Overflow / Carry Out Port Use Direction Port

Specify the number of bits to the left of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats. The number of pipeline stages. Use the block as an adder or subtractor. Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr). Turn on to use the carry in input (cin). Turn on to use the overflow or carry out output (ovl). Turn on to use the direction input (addsub). 1= add, 0 = subtract.

Table 2–46 shows the Pipelined Adder block I/O formats.
Table 2–46. Pipelined Adder Block I/O Formats (Note 1) I/O I Simulink (2), (3) I1[L].[R] I2[L].[R] I3[1] I4[1] I5[1] I6[1] O O1[L].[R] O2[1]
Notes to Table 2–46:
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit. (3) I1[L].[R] is an input port. O1[L].[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.

VHDL I1: in STD_LOGIC_VECTOR({L + R} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC I6: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R} DOWNTO 0) O2: out STD_LOGIC

Type (4) Explicit Explicit

Explicit

Figure 2–18 shows an example with the Pipelined Adder block.

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Figure 2–18. Pipelined Adder Block Example

Product
The Product block supports two scalar inputs (no multidimensional Simulink signals). Operand a is multiplied by operand b and the result output on r as the following equation shows: r=a×b The differences between the Product block and the Multiplier block are:

The Product block supports clock phase selection while the Multiplier block does not. The Product block uses implicit input port data widths that are inherited from the signals’ sources, whereas the Multiplier block uses explicit input port data widths that you must specify as parameters. The Product block allows you to use the LPM multiplier megafunction, whereas the Multiplier block always uses the LPM.

1

The Simulink software also provides a Product block. If you use the Simulink Product block in your model, you can use it only for simulation. Signal Compiler issues an error and cannot convert the Simulink Product block to HDL. Table 2–47 shows the Product block inputs and outputs.
Table 2–47. Product Block Inputs and Outputs Signal a b ena aclr r Direction Input Input Input Input Output Operand a. Operand b. Optional clock enable. Optional asynchronous clear. Result. Description

Table 2–48 shows the Product block parameters.

© June 2010 Altera Corporation Preliminary

DSP Builder Standard Blockset Libraries

2–32

Chapter 2: Arithmetic Library Product

Table 2–48. Product Block Parameters Name Bus Type Value Description

Inferred, The bus number format that you want to use. Inferred means that the format is Signed Integer, automatically set by the format of the connected signal. Signed Fractional, Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) User Defined Specify the number of bits to the left of the binary point. Specify the number of bits to the right of the binary point. This option applies only to signed fractional formats. The Pipeline represents the delay. The clock enable and asynchronous clear ports are available only if the block is registered (that is, if the number of pipeline stages is greater than or equal to 1). This option is available only when the Pipeline value is greater than 0. Specifies the phase selection with a binary string, where a 1 indicates the phase in which the block is enabled. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and 4 do not pass through the block.

[number of bits].[] [].[number of bits] Number of Pipeline Stages Clock Phase Selection

Use Enable Port Use Asynchronous Clear Port Use LPM

On or Off On or Off On or Off

Turn on to use the clock enable input (ena). Turn on to use the asynchronous clear input (aclr). When on, the Product block is mapped to the LPM_MULT library of parameterized modules (LPM) function and the VHDL synthesis tool uses the Altera LPM_MULT implementation. When off, the VHDL synthesis tool uses the native * operator to synthesize the product. If your design does not need arithmetic boundary optimization—such as connecting a multiplier to constant combinational logic or register balancing optimization—the LPM_MULT implementation generally yields a better result for both speed and area.

Use Dedicated Circuitry

On or Off

Turn on to use the dedicated multiplier circuitry (if supported by your target device). This option is ignored if not supported by your target device.

Table 2–49 shows the Product block I/O formats.
Table 2–49. Product Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2), (3) I1[L1].[R1] I2[L2].[R2] I3[1] I4[1] VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC Type (4) Explicit Explicit

DSP Builder Standard Blockset Libraries Preliminary

© June 2010 Altera Corporation

that is. O1[L]. Figure 2–19 shows an example with the Product block. (3) I1[L]. To specify the bus format of an implicit input port.[R] is an output port. [L].L2) + 2×max(R1. Figure 2–19. The SOP Tap block implements with a multiplier-adder. [1] is a single bit. Product Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2).[R] is an input port. the MSB is the sign bit. Use this block to build two or four tap FIR filters.[2×max(R1.R2) . use a Bus Conversion block to set the width. the result always lags the input by 3 cycles.L2]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.1} DOWNTO 0) Implicit Notes to Table 2–49: (1) For signed integers and signed binary fractional numbers. For signed or unsigned integers R = 0. which has registers on the inputs. The block has the following equations: For 2 taps: q(n+3) = c0(n)×din(n) + c1(n)×din(n-1) dout(n+2) = din(n) For 4 taps: q(n+3) = c0(n)×din(n) + c1(n)×din(n-1) + c2(n)×din(n-2) + c3(n)×din(n-3) dout(n+4) = din(n) Table 2–50 shows the SOP Tap block inputs and outputs. (3) O1[2×max(L1. (4) Explicit means that the port bit width information is a block parameter. multipliers and adders.[0].Chapter 2: Arithmetic Library SOP Tap 2–33 Table 2–49. R2)] VHDL Type (4) O1: out STD_LOGIC_VECTOR({2×max(L1. R = 0. or cascade blocks to create filters with more taps. refer to the lpm_mult Megafunction User Guide. For single bits. Thus. that is. (2) [L] is the number of bits on the left side of the binary point. [R] is the number of bits on the right side of the binary point. Product Block Example f For more information about multiplier operations. The dout port is assigned the value of din(n-t) where t is the number of taps. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . SOP Tap The SOP Tap block performs a sum of products for two or four taps.

For signed or unsigned integers R = 0. c3 ena aclr q dout Direction Input Input Input Input Output Output Data input. SOP Tap Block I/O Formats I/O I Simulink (2).. Description Table 2–51 shows the SOP Tap block parameters. R = 0. Turn on to use the asynchronous clear input (aclr). (2) [L] is the number of bits on the left side of the binary point. the MSB is the sign bit. [L]. 2 or 4 tap coefficients. Optional asynchronous clear. use a Bus Conversion block to set the width. Unsigned Integer Description The bus number format that you want to use for the counter. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .2–34 Chapter 2: Arithmetic Library SOP Tap Table 2–50.[R] is an output port. In: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) I(n+1): STD_LOGIC I(n+2): STD_LOGIC O1: out STD_LOGIC_VECTOR({2L + cell(log2(N + 1)) + 2R . SOP Tap Block Inputs and Outputs Signal din c0. Table 2–52. (3) I1[L]. that is. c1.[R] . [1] is a single bit.[2R] (Note 1) VHDL Type (4) Explicit Explicit ... Figure 2–20 shows an example with the SOP Tap block.1} DOWNTO 0) Explicit O2: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) Explicit O2 Notes to Table 2–52: (1) For signed integers and signed binary fractional numbers. >= 0 Specify the number of bits. In[L]. Turn on to use the clock enable input (ena). To specify the bus format of an implicit input port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Optional clock enable. (4) Explicit means that the port bit width information is a block parameter. SOP Tap Block Parameters Name Bus Type Input Number of Bits Number of Taps Use Enable Port Value Signed Integer.[R] is an input port. Use Asynchronous Clear Port On or Off Table 2–52 shows the SOP Tap block I/O formats.[0]. Shifted input data. Table 2–51. [R] is the number of bits on the right side of the binary point. (Parameterizable) 2 or 4 On or Off The number of taps. that is. For single bits.. (3) I1[L].[R] I(n+1) I(n+2) O O1[2L + cell(log2(N + 1))]. c2... Explicit I1: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L + R -1} DOWNTO 0) .[R] I2[L]. O1[L]. Result.

Chapter 2: Arithmetic Library Square Root 2–35 Figure 2–20. On or Off Turn on to use the clock enable input (ena). SOP Tap Block Example Square Root The Square Root block returns the square root and optional remainder of unsigned integer input data with the equation: q2 + remainder = d where remainder <= 2 × q The Square Root block supports sequential mode (when the number of pipeline stages> 0) or combinational mode (when the number of pipeline stages = 0). Square Root Block Inputs and Outputs Signal d en aclr q remainder Direction Input Input Input Output Output Data input. Optional clock enable. Table 2–53. (Parameterizable) >= 0 Specify the number of pipeline stages. Use Enable Port © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . The computation is sequential (Parameterizable) when the pipeline is greater than 1 or combinational when the number of pipeline stages is zero. Result. Table 2–53 shows the Square Root block inputs and outputs. Optional remainder. Assume the radical d is an unsigned integer. Optional asynchronous clear. and that q and the remainder are always unsigned integers. Table 2–54. Square Root Block Parameters (Part 1 of 2) Name Input Number of Bits Number of Pipeline Stages Value Description >= 0 Specify the number of bits of the unsigned input signal. The clock enable and asynchronous clear ports are available only if the number of pipeline stages is greater than or equal to 1. Description Table 2–54 lists the parameters for the Square Root block.

[R] is an input port. [L]. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. (3) I1[L]. Square Root Block Parameters (Part 2 of 2) Name Use Remainder Port Value On or Off Description Turn on to use the asynchronous clear input (aclr). [R] is the number of bits on the right side of the binary point. Use Asynchronous Clear Port On or Off Table 2–55 shows the Square Root block I/O formats. Turn on to use the remainder input (remainder). For single bits. that is. For signed or unsigned integers R = 0.. + a(n-1)Cn-1 where: ■ ■ ■ ■ q is the output result a(i) is the signed integer input data Ci are the signed integer fixed coefficients n is the number of coefficients in the range one to eight Table 2–56 shows the Sum of Products block inputs and outputs. that is.2–36 Chapter 2: Arithmetic Library Sum of Products Table 2–54.[0].[R] O2[L].[R] I2[1] I3[1] O O1[L]. use a Bus Conversion block to set the width. Table 2–55. [1] is a single bit. O1[L]. VHDL I1: in STD_LOGIC_VECTOR({L + R} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R} DOWNTO 0) O2: out STD_LOGIC_VECTOR({L + R} DOWNTO 0) Type (4) Explicit Explicit Figure 2–21 shows an example of the Square Root block. the MSB is the sign bit. Square Root Block Design Example Sum of Products The Sum of Products block implements the following expression: q = a(0)C0 + . Square Root Block I/O Formats (Note 1) I/O I Simulink (2). + a(i)Ci + . (3) I1[L].[R] is an output port. Figure 2–21. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . R = 0.[R] Notes to Table 2–55: (1) For signed integers and signed binary fractional numbers. To specify the bus format of an implicit input port. (2) [L] is the number of bits on the left side of the binary point....

Specify the number of bits to the left of the binary point of all non-variable coefficients represented as a signed integer. Table 2–57. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . you can specify the number of bits in the output signal and the number of least significant bits (LSBs) truncated from the output signal. Optional clock enable. For example: [-587 -844 -678 -100 367 362 71 -244] Specify the number of pipeline stages. Output Number of Bits >= 0 (Parameterizable) Output Truncated LSB FPGA Implementation >= 0 (Parameterizable) Distributed Arithmetic. Sum of Products Block Parameters Name Input Data Number of Bits Number of Coefficients Coefficients Number of Bits Signed Integer Fixed-Coefficient Values Number of Pipeline Stages Full Resolution for Output Result >= 0 (Parameterizable) 1–8 >= 1 (Parameterizable) Vector (Parameterizable) >= 0 (Parameterizable) On or Off When on. Value Description Specify the number of bits to the left of the binary point of all input signals. Specify the number of bits in the output signal. Specify the number of LSBs to be truncated from the output signal. Auto On or Off On or Off Turn on to use the clock enable input (ena). Optional asynchronous clear. When off. Specify the coefficient values for each port as a sequence of signed integers. dedicated multiplier or automatically Dedicated Multiplier determined implementation. Circuitry. Result.Chapter 2: Arithmetic Library Sum of Products 2–37 Table 2–56. The number of coefficients. Turn on to use the asynchronous clear input (aclr). Sum of Products Block Inputs and Outputs Signal Direction Description 1 to 8 ports corresponding to the signed integer fixed coefficient values specified in the block parameters. a(0) to a(n–1) Input ena aclr q Input Input Output Table 2–57 lists the parameters for the Sum of Products block. the multiplier output bit width is full resolution. Use Enable Port Use Asynchronous Clear Port Table 2–58 shows the Sum of Product block I/O formats. Use a distributed arithmetic.

[1] is a single bit. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.. [L].[0] . Figure 2–22.[R] is an input port. For signed or unsigned integers R = 0.1} DOWNTO 0) . O1[L].1} DOWNTO 0) I(n+1): STD_LOGIC I(n+2): STD_LOGIC O1: out STD_LOGIC_VECTOR({2L + cell(log2(n + 1)) + 2R ..1} DOWNTO 0) Explicit Notes to Table 2–58: (1) For signed integers and signed binary fractional numbers. Figure 2–22 shows an example with the Sum of Product block. For single bits. Explicit I1: in STD_LOGIC_VECTOR({L . (3) I1[L]. use a Bus Conversion block to set the width. that is.[R] is an output port..[2R] (Note 1) VHDL Type (4) Explicit . In[L].[0] I(n+1) I(n+2) O O1[2L + cell(log2(n + 1))]... To specify the bus format of an implicit input port.2–38 Chapter 2: Arithmetic Library Sum of Products Table 2–58. Sum of Product Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . (2) [L] is the number of bits on the left side of the binary point.[0]. In: in STD_LOGIC_VECTOR({L . that is. (4) Explicit means that the port bit width information is a block parameter.. Sum of Products Block I/O Formats I/O I Simulink (2). the MSB is the sign bit. (3) I1[L]. [R] is the number of bits on the right side of the binary point. R = 0.

DSP Builder supports native complex signal types.3. and complex filters. Use complex number notation to simplify the design of applications such as FFT. For an example. Complex Type Library Like Simulink. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . refer to Figure 3–2 on page 3–5. I-Q modulation. connecting AltBus to Complex AddSub). you must use Real-Imag to Complex or Complex to Real-Imag blocks between the blocks. The Complex Type library contains the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ Butterfly Complex AddSub Complex Conjugate Complex Constant Complex Delay Complex Multiplexer Complex Product Complex to Real-Imag Real-Imag to Complex 1 When connecting DSP Builder blocks to blocks from the Complex Type library (for example.

The full bit width precision of A and B is: 2 × [input bit width] + 2. you can specify the real and imaginary values for W instead of the W port. W) Number of Pipeline Stages Full Resolution for Output Type Output Bit Width (A. This option is available when Full Resolution for Output Type is off. then the full precision is 34 bits and the output ports A[15:0] and B[15:0] each contain the bit slice 19:4.Yv . Optional clock enable. full output bit width resolution is enabled. B) Output Truncated LSB W is constant Value >= 1 >= 3 On or Off >= 1 >= 0 On or Off Description Specify the bit width of the complex signed integer inputs a. For example. A. Optional asynchronous clear. b. Specify the required number of pipeline stages. Table 3–1. Specify the bit width of the complex signed integer outputs A and B. b. When off. Description Table 3–2 shows the Butterfly block parameters. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . This option is available when Full Resolution for Output Type is off. Data input b.YV + j(X + Yv + yV) B = (x . Butterfly Block Parameters (Part 1 of 2) Name Input Bit Width (a. Data Output B. and B are complex numbers (type signed integer) such as: a = x + jX b = y + jY W = v + jV A = (x + yv) . b. Butterfly Block Inputs and Outputs Signal a b W ena aclr A B Direction Input Input Input Input Input Output Output Data input a.3–2 Chapter 3: Complex Type Library Butterfly Butterfly The Butterfly block performs the following arithmetic operation on complex signed integer numbers: A = a + b×W B = a . Optional input W. you can separately specify the output bit width and LSB of the output. Data Output A.b×W where a. When this option is on.yV) This function operates with full bit width precision. Specify the LSB of the output bus slice of the full resolution computation. W. the output bit width is 16. When this option is on. and W.yv) + YV + j(X . and the output LSB is 4. Table 3–1 shows the Butterfly block inputs and outputs. The Output Bit Width and Output Truncated LSB parameters specify the bit slice for the output ports A and B. if the input bit width is 16. Table 3–2.

No On or Off On or Off Description Specify the value of the real part of the constant W Specify the value of the imaginary part of the constant W.[0])Imag([Li].[0])Imag([Li]. R = 0. For signed or unsigned integers R = 0.1} DOWNTO 0) I2Imag: in STD_LOGIC_VECTOR({Li .1} DOWNTO 0) I3Real: in STD_LOGIC_VECTOR({Li .[0])Imag([Li]. (2) [L] is the number of bits on the left side of the binary point.[R] is an input port. VHDL I1Real: in STD_LOGIC_VECTOR({Li . To specify the bus format of an implicit input port.[R] is an output port. Butterfly Block I/O Formats (Note 1) I/O I Simulink (2).[0])Imag([Li].[0]) I3Real([Li].[0]) I2Real([Li].1} DOWNTO 0) Type (4) Explicit Explicit Explicit Explicit Explicit Explicit Explicit Explicit Explicit Explicit Figure 3–1 shows an example with the Butterfly block. [L]. Butterfly Block Parameters (Part 2 of 2) Name W (real) W (imaginary) Dedicated Multiplier Circuitry Use Enable Port Use Asynchronous Clear Port Value User defined User defined Auto.[0]) Notes to Table 3–3: (1) For signed integers and signed binary fractional numbers. use a Bus Conversion block to set the width. [1] is a single bit.1} DOWNTO 0) I2Real: in STD_LOGIC_VECTOR({Li . O1[L]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. (4) Explicit means that the port bit width information is a block parameter. Table 3–3. For devices that support multipliers.1} DOWNTO 0) I4: in STD_LOGIC I5: in STD_LOGIC O1Real: out STD_LOGIC_VECTOR({Lo . Table 3–3 shows the Butterfly block I/O formats. (3) I1Real([Li]. For single bits.1} DOWNTO 0) I3Imag: in STD_LOGIC_VECTOR({Li . [R] is the number of bits on the right side of the binary point. Yes.1} DOWNTO 0) O2Imag: out STD_LOGIC_VECTOR({Lo . Butterfly Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Turn on to use the asynchronous clear input (aclr). Figure 3–1.Chapter 3: Complex Type Library Butterfly 3–3 Table 3–2. (3) I1[L].[0])Imag([Li].1} DOWNTO 0) O2Real: out STD_LOGIC_VECTOR({Lo .[0]) O2Real([Lo]. Turn on to use the clock enable input (ena).[0]) I4[1] I5[1] O O1Real([Lo].1} DOWNTO 0) O1Imag: out STD_LOGIC_VECTOR({Lo . that is.1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({Li . that is. the MSB is the sign bit.[0]. a value of Auto specifies that the choice is based on the width of the multiplier.

Missing operators are assumed to be +. However. Turn on to use the asynchronous clear input (aclr). Use Enable Port Use Asynchronous Clear Port On or Off On or Off Turn on to use the clock enable input (ena). Optional asynchronous clear. User defined Specify addition or subtraction operation for each port with the characters + and –. Table 3–4. Result. the data on phases 1. Description Table 3–5 shows the Complex AddSub block parameters. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). resulting in a pipeline length that is equal to ceil(log2(number of inputs)). Thus. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. Each consecutive pair of inputs are + +. For example + – + implements +a – b + c for three ports. Table 3–4 shows the Complex AddSub block inputs and outputs. + – – + + is also valid but + + – – + is not valid. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. Complex AddSub Block Inputs and Outputs Signal + or – ena aclr R Direction Input Input Input Output Complex inputs. you can specify the phase selection as a binary string. where a 1 indicates the phase in which the block is enabled. DSP Builder implements the block as a tree of 2-input adders. Clock Phase Selection User Defined When you enable pipeline.3–4 Chapter 3: Complex Type Library Complex AddSub Complex AddSub The Complex AddSub block performs addition or subtraction on a specified number of scalar complex inputs. + – – + is valid (as the two input adders are parameterized + – and – +). That is. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . DSP Builder registers the output from each stage in the adder tree. Enable Pipeline On or Off When this option is on. 3. none of the input adders can have two consecutive subtractions. Optional clock enable. Table 3–5. + – or – +. Complex AddSub Block Parameters Name Number of Inputs Add (+) Sub (–) Value >= 2 Description Specifies the number of input wires to combine. and 4 do not pass through the block.

[R1]) . For single bits.Rn) + 1)Imag(max(L1.1} DOWNTO 0) InImag: in STD_LOGIC_VECTOR({LPn + RPn .[0]. InReal: in STD_LOGIC_VECTOR({LPn + RPn . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. that is. Figure 3–2 shows an example with the Complex AddSub block. the MSB is the sign bit. that is.[Rn]) I(n+1)[1] I(n+2)[1] O O1Real(max(L1.Rn)} DOWNTO 0) Implicit O1Imag: out STD_LOGIC_VECTOR({max(LI.[Rn])Imag([Ln]. [1] is a single bit.Ln) + max(RI.. Complex AddSub Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .Rn) + 1) (Note 1) VHDL Type (4) Implicit Implicit Implicit Implicit I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 .. O1[L]. InReal([Ln]. (3) I1Real([L1].1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 .[R] is an output port.Rn)} DOWNTO 0) Implicit Notes to Table 3–6: (1) For signed integers and signed binary fractional numbers.[R1])Imag([L1]. use a Bus Conversion block to set the width. [R] is the number of bits on the right side of the binary point. (4) Explicit means that the port bit width information is a block parameter.(max(RI. (2) [L] is the number of bits on the left side of the binary point.1} DOWNTO 0) I(n+1): in STD_LOGIC I(n+2): in STD_LOGIC O1Real: out STD_LOGIC_VECTOR({max(LI. R = 0. For signed or unsigned integers R = 0. Complex AddSub Block I/O Formats I/O I Simulink (2). To specify the bus format of an implicit input port. (3) I1[L].Ln) + max(RI. Figure 3–2.(max(RI.[R] is an input port. Table 3–6..Chapter 3: Complex Type Library Complex AddSub 3–5 Table 3–6 shows the Complex AddSub block I/O formats..Ln) + 1).Ln) + 1).1} DOWNTO 0) . [L].

To specify the bus format of an implicit input port.[R] is an output port. Table 3–9 shows the Complex Conjugate block I/O formats. Negative. Complex Conjugate Block Parameters Name Operation Register Inputs Use Enable Port Use Asynchronous Clear Port Value Description Conjugate. the MSB is the sign bit. Negative Conjugate On or Off On or Off On or Off Turn on to register the inputs and to enable the optional clock enable and asynchronous clear options. O1[L].[0]. Optional asynchronous clear. (3) I1Real([L1]. Complex Conjugate Block I/O Formats (Note 1) I/O I Simulink (2). Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. [L]. Table 3–7.[R1]) VHDL I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 . Turn on to use the asynchronous clear input (aclr). Specify the operation to perform. the block returns: ■ ■ ■ Conjugate: x – iy Negative: –x – iy Negative Conjugate: –x + iy Table 3–7 shows the Complex Conjugate block inputs and outputs. For single bits. Turn on to use the clock enable input (ena). Fixed point complex conjugate output. negative. (2) [L] is the number of bits on the left side of the binary point. [R] is the number of bits on the right side of the binary point. that is.3–6 Chapter 3: Complex Type Library Complex Conjugate Complex Conjugate The Complex Conjugate block outputs a fixed-point complex conjugate value by performing simple arithmetic operations on the complex inputs. Optional clock enable.[R1])Imag([L1]. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Table 3–8. (3) I1[L]. Table 3–9. The operation can optionally be conjugate. R = 0. or negative conjugate. Description Table 3–8 shows the Complex Conjugate block parameters. For an input w = x + iy. Complex Conjugate Block Inputs and Outputs Signal w ena aclr c Direction Input Input Input Output Complex inputs.[R] is an input port.1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 .1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1Real: in STD_LOGIC_VECTOR({LP1 + RP1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1} DOWNTO 0) Type (4) Implicit Implicit Implicit Implicit Notes to Table 3–9: (1) For signed integers and signed binary fractional numbers. use a Bus Conversion block to set the width. (4) Explicit means that the port bit width information is a block parameter. For signed or unsigned integers R = 0.[R1])Imag([L1] + 1.[R1]) I2[1] I3[1] O O1Real([L1] + 1. [1] is a single bit. that is.

Complex Conjugate Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Figure 3–3. negative and negative conjugate values.Chapter 3: Complex Type Library Complex Conjugate 3–7 Figure 3–3 shows an example with Complex Conjugate blocks to output conjugate.

Signed Fractional. For single bits. the MSB is the sign bit.[R] is an input port. including the sign bit.1} DOWNTO 0) Notes to Table 3–11: (1) For signed integers and signed binary fractional numbers. Complex Constant Block I/O Formats I/O O Simulink (2). Complex Constant Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . [number of bits]. (3) O1Real([L1]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. R = 0. [1] is a single bit. (4) Explicit means that the port bit width information is a block parameter. Table 3–10. that is. Complex Constant Block Parameters Name Real Part Imaginary Part Bus Type Value User Defined User Defined Signed Integer. Specify the clock signal name. Figure 3–4. (2) [L] is the number of bits on the left side of the binary point. Turn on to explicitly specify the clock name.[] >= 0 (Parameterizable) []. Specify the number format of the bus.[number of bits] >= 0 (Parameterizable) Specify Clock Clock On or Off User defined Specify the number of bits to the left of the binary point. O1[L].[0]. This parameter does not apply to single-bit buses. Unsigned Integer Description Specify the value of the real part of the constant.[R] is an output port. Specify the value of the imaginary part of the constant. use a Bus Conversion block to set the width. that is. Table 3–10 shows the Complex Constant block parameters.3–8 Chapter 3: Complex Type Library Complex Constant Complex Constant The Complex Constant block outputs a fixed-point complex constant value. Table 3–11 shows the Complex Constant block I/O formats. For signed or unsigned integers R = 0. [R] is the number of bits on the right side of the binary point.[R1])Imag([L1]. (3) I1[L]. This parameter applies only to signed fractional buses. Specify the number of bits to the right of the binary point. Table 3–11. Type (4) Explicit Figure 3–4 shows an example with Complex Constant blocks as inputs to a Complex AddSub block.1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . [L].[R1]) (Note 1) VHDL O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 . To specify the bus format of an implicit input port.

Optional synchronous clear. (3) I1Real([L1].1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC Type (4) Implicit Implicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Table 3–12. The input must be a complex number. where a 1 indicates the phase in which the block is enabled. When you enable pipeline. Complex Delay Block Parameters Name Number of Pipeline Stages Clock Phase Selection Value >= 1 User Defined Description Specify the delay length of the block. Table 3–14. Description Table 3–13 shows the Complex Delay block parameters. Use Enable Port Use Synchronous Clear Port On or Off On or Off Turn on to use the clock enable input (ena). 3. Delayed output data. Table 3–12 shows the Complex Delay block inputs and outputs. and 4 do not pass through the block.Chapter 3: Complex Type Library Complex Delay 3–9 Complex Delay The Complex Delay block delays the incoming data by an amount specified by the Number of Pipeline Stages parameter. Table 3–14 shows the Complex Delay block I/O formats. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. Table 3–13.[R1]) I2[1] I3[1] VHDL I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 . Turn on to use the synchronous clear input (sclr). Complex Delay Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Input data. you can indicate the phase selection with a binary string. the data on phases 1.[R1])Imag([L1]. Optional clock enable. That is. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1).1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. Complex Delay Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2).

3–10 Chapter 3: Complex Type Library Complex Multiplexer Table 3–14. Table 3–15 shows the Complex Multiplexer block inputs and outputs. (3) O1Real([L1]. [L]. the MSB is the sign bit. Table 3–16. Type (4) Implicit Figure 3–5 shows an example with the Complex Delay block. Complex Multiplexer Block Parameters Name Number of Input Data Lines Number of Pipeline Stages Use Enable Port Use Asynchronous Clear Port One Hot Select Bus Value >= 2 >= 0 On or Off On or Off On or Off Description Number of complex input data lines.1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . (4) Explicit means that the port bit width information is a block parameter.[R] is an input port. For signed or unsigned integers R = 0. (3) I1[L]. Complex Multiplexer Block Inputs and Outputs Signal sel 0 to N—1 ena aclr unnamed Direction Input Input Input Input Output Non-complex select line. Optional asynchronous clear.[0]. For single bits. [R] is the number of bits on the right side of the binary point. Complex Delay Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2). The select port sel is a non-complex scalar. Optional clock enable. To specify the bus format of an implicit input port. use a Bus Conversion block to set the width. [1] is a single bit.[R] is an output port. Specify the delay length of the block.[R1]) VHDL O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 . Table 3–15. Complex Delay Block Example Complex Multiplexer The Complex Multiplexer block multiplexes N complex inputs to one complex output. (2) [L] is the number of bits on the left side of the binary point. that is. Result. R = 0. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Turn on to use one-hot selection for the select signal instead of full binary. Turn on to use the clock enable input (ena).[R1])Imag([L1]. Turn on to use the asynchronous clear input (aclr). O1[L]. Description Table 3–16 shows the Complex Multiplexer block parameters. that is. Figure 3–5. Complex inputs.1} DOWNTO 0) Notes to Table 3–14: (1) For signed integers and signed binary fractional numbers. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.

[L]. For signed or unsigned integers R = 0. (4) Explicit means that the port bit width information is a block parameter.1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({max(LI. Operand a is multiplied by operand b and the result output on r as the following equation shows: r=a×b © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .L2) + max(RI.Chapter 3: Complex Type Library Complex Product 3–11 Table 3–17 shows the Complex Multiplexer block I/O formats.[0].[R1])Imag([L1]. (3) I1Real([L1]. that is. (2) [L] is the number of bits on the left side of the binary point. Figure 3–6.R2)) (Note 1) VHDL Type (4) Implicit Implicit I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 . (3) I1[L]. [1] is a single bit. Figure 3–6 shows an example with the Complex Multiplexer block.R2) ) O1Real: in STD_LOGIC_VECTOR({max(LI.1} DOWNTO 0) I2Imag: in STD_LOGIC_VECTOR({LP2 + RP2 . the MSB is the sign bit. Table 3–17.[R] is an output port. use a Bus Conversion block to set the width. Complex Multiplexer Block Example Complex Product The Complex Product block performs output multiplication of two scalar complex inputs.[R2]) I3[1] I4[1] I5[1] O Imag(max(L1. For single bits.L2)).1} DOWNTO 0) Implicit Notes to Table 3–17: (1) For signed integers and signed binary fractional numbers.[R2])Imag([L2].[R1]) I2Real([L2].1} DOWNTO 0) I2Real: in STD_LOGIC_VECTOR({LP2 + RP2 . [R] is the number of bits on the right side of the binary point.L2) + max(RI. O1[L].R2) . R = 0.[R] is an input port.1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . that is.(max(RI. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC I5: in STD_LOGIC O1Real(max(L1.R2) .L2)). Complex Multiplexer Block I/O Formats I/O I Simulink (2). To specify the bus format of an implicit input port.(max(RI.

Multiplier and Adder. Description Table 3–19 shows the Complex Product block parameters. Specify the number of bits to the left of the binary point. Signed Fractional. This option applies only to signed fractional formats. Complex operand b.1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) Description Specify the bus number format that you want to use. Inferred means that the format is automatically set by the format of the connected signal. Complex Product Block Inputs and Outputs Signal a b ena aclr r Direction Input Input Input Input Output Complex operand a. Table 3–18.[R1]) I2Real([L2]. Signed Integer. Table 3–19. Use Enable Port Use Asynchronous Clear Port Use Dedicated Circuitry Table 3–20 shows the Complex Product block I/O formats.[] []. Optional clock enable. If you target devices that support DSP blocks. asynchronous clear ports are available only if the block is registered. (3) I1Real([L1]. Inputs Only. Complex Product Block Parameters Name Bus Type Value Inferred. Optional asynchronous clear.3–12 Chapter 3: Complex Type Library Complex Product Table 3–18 shows the Complex Product block inputs and outputs.1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC Type (4) Implicit DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . turn on to implement the functionality in DSP blocks instead of logic elements. Specify the number of bits to the right of the binary point. The clock enable and No Register. Multiplier Only.[R2])Imag([L2]. [number of bits]. Turn on to use the asynchronous clear input (aclr).[R1])Imag([L1]. Inputs and Adder.[R2]) I3[1] I4[1] VHDL I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 .1} DOWNTO 0) I2Real: in STD_LOGIC_VECTOR({LP2 + RP2 . Result.[number of bits] Pipeline Register Specify the elements that you want pipelined. Inputs and Multiplier.1} DOWNTO 0) I2Imag: in STD_LOGIC_VECTOR({LP2 + RP2 . Table 3–20. Adder Only. Inputs Multiplier and Adder On or Off On or Off On or Off Turn on to use the clock enable input (ena). Complex Product Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2).

R = 0. (4) Explicit means that the port bit width information is a block parameter.R 2)) VHDL O1Real: in STD_LOGIC_VECTOR({(2 x max(LI. [L]. that is.L2)). Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Figure 3–7 shows an example with the Complex Product block. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .[R] is an output port. Table 3–21 shows the Complex to Real-Imag block inputs and outputs. [R] is the number of bits on the right side of the binary point.[number of bits] Select the number of data input bits to the left of the binary point.L2)) + (2 x max(RI. Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) Description Specify the number format you want to use for the bus.R2)) -1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({(2 x max(LI. For signed or unsigned integers R = 0. Real part output. Complex to Real-Imag Block Parameters Name Bus Type Value Signed Integer.R2)) Imag(2 x max(LI.R2)) -1} DOWNTO 0) Type (4) Implicit Notes to Table 3–20: (1) For signed integers and signed binary fractional numbers.(2 x max(RI. (2) [L] is the number of bits on the left side of the binary point. This option applies only to signed fractional formats. Complex Product Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2). To specify the bus format of an implicit input port.[] []. (3) I1[L]. Complex to Real-Imag Block Inputs and Outputs Signal c r i Direction Input Output Output Complex input. including the sign bit.L2)). Description Table 3–22 shows the Complex to Real-Imag block parameters.Chapter 3: Complex Type Library Complex to Real-Imag 3–13 Table 3–20.L2)) + (2 x max(RI. Figure 3–7. Select the number of data input bits to the right of the binary point. use a Bus Conversion block to set the width. For single bits. Table 3–21. (3) O1Real(2 x max(LI. Imaginary part output. Table 3–22. O1[L].[0]. Complex Product Block Example Complex to Real-Imag The Complex to Real-Imag block constructs a fixed-point real and fixed-point imaginary output from a complex input.[R] is an input port. that is.(2 x max( RI. [number of bits]. the MSB is the sign bit. Signed Fractional. [1] is a single bit.

Table 3–24 shows the Real-Imag to Complex block has the inputs and outputs. (4) Explicit means that the port bit width information is a block parameter.[R1]) Notes to Table 3–23: (1) For signed integers and signed binary fractional numbers. (3) I1Real([L1]. Table 3–23.1} DOWNTO 0) Figure 3–8 shows an example with the Complex to Real-Imag block.[0]. Real-Imag to Complex Block Inputs and Outputs Signal r i c Direction Input Input Output Real part input. R = 0. [R] is the number of bits on the right side of the binary point.3–14 Chapter 3: Complex Type Library Real-Imag to Complex Table 3–23 shows the Complex to Real-Imag block I/O formats. that is.1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . For single bits. (3) I1[L]. Complex output.1} DOWNTO 0) O2Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . O1[L].[R] is an input port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. For signed or unsigned integers R = 0.[R1])Imag([L1]. Imaginary part input.1} DOWNTO 0) O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 .[R1]) O1Real([L1]. use a Bus Conversion block to set the width. Table 3–24. (2) [L] is the number of bits on the left side of the binary point. To specify the bus format of an implicit input port.[R] is an output port. that is. (Note 1) VHDL Type (4) Implicit Explicit I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 .[R1]) O2Imag([L1]. [L]. Description DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . the MSB is the sign bit. [1] is a single bit. Complex to Real-Imag Block Example Real-Imag to Complex The Real-Imag to Complex block constructs a fixed-point complex output from real and imaginary inputs. Figure 3–8. Complex to Real-Imag Block I/O Formats I/O I O Simulink (2).

[R1]) O1Real([L1]. (3) I1Real([L1].[0].1} DOWNTO 0) O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 . To specify the bus format of an implicit input port.Chapter 3: Complex Type Library Real-Imag to Complex 3–15 Table 3–25 shows the Real-Imag to Complex block parameters. [number of bits].[R] is an output port. use a Bus Conversion block to set the width.[number of bits] Select the number of data input bits to the left of the binary point. R = 0. Type (4) Implicit Explicit Figure 3–9 shows an example with the Real-Imag to Complex block. Figure 3–9. that is. Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) Description Specify the number format you want to use for the bus. [L]. [R] is the number of bits on the right side of the binary point. (4) Explicit means that the port bit width information is a block parameter. This option applies only to signed fractional formats. including the sign bit.[R1])Imag([L1]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. For signed or unsigned integers R = 0. [1] is a single bit.1} DOWNTO 0) Notes to Table 3–26: (1) For signed integers and signed binary fractional numbers. Real-Imag to Complex Block Parameters Name Bus Type Value Signed Integer. Real-Imag to Complex Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . (2) [L] is the number of bits on the left side of the binary point. Table 3–25.[] [].1} DOWNTO 0) I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . For single bits. that is. the MSB is the sign bit. Table 3–26 shows the Real-Imag to Complex block I/O formats.1} DOWNTO 0) O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 . O1[L]. Signed Fractional. Table 3–26.[R1]) I2Imag([L1]. (3) I1[L].[R1]) (Note 1) VHDL I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 . Select the number of data input bits to the right of the binary point. Real-Imag to Complex Block I/O Formats I/O I O Simulink (2).[R] is an input port.

3–16 Chapter 3: Complex Type Library Real-Imag to Complex DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

The Gate & Control library contains the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Binary to Seven Segments Bitwise Logical Bus Operator Case Statement Decoder Demultiplexer Flipflop If Statement LFSR Sequence Logical Bit Operator Logical Bus Operator Logical Reduce Operator Multiplexer Pattern Single Pulse © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Gate & Control Library The blocks in the Gate &Control library support gate and other related control functions.4.

7-bit data output. Table 4–1. (3) I1[4]. Description Table 4–2 shows the 4-bit to 7-bit conversion performed by the Binary to Seven Segments block. Table 4–3. Table 4–1 shows the Binary to Seven Segments block inputs and outputs.[0] VHDL I1: in STD_LOGIC_VECTOR(3 DOWNTO 0) Type (4) Explicit DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .4–2 Chapter 4: Gate & Control Library Binary to Seven Segments Binary to Seven Segments The Binary to Seven Segments block converts a 4-bit unsigned input bus to a 7-bit output for connection to a seven-segment displays. Table 4–2. Binary to Seven Segments Display Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2). Binary to Seven Segments Block Inputs and Outputs Signal (3:0) (6:0) Direction Input Output 4-bit data input. The seven-segment display is set to display the hexadecimal representation of the input number. Binary to Seven Segments Input Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 0 1 2 3 4 5 6 7 8 9 A b C d E F Binary 1000000 1111001 0100100 0110000 0011001 0010010 0000010 1111000 0000000 0010000 0001000 0000011 1000110 1000001 0000110 0001110 Output Decimal 64 121 36 48 25 18 2 120 0 16 8 3 70 33 6 14 Table 4–3 shows the Binary to Seven Segments block I/O formats.

O1[L]. Binary to Seven Segments Display Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2).[0].[R] is an output port. To specify the bus format of an implicit input port. Bitwise Logical Bus Operator Block Inputs and Outputs Signal a b q Direction Input Input Output Data input a. [R] is the number of bits on the right side of the binary point. Table 4–4. use a Bus Conversion block to set the width. Figure 4–1 shows an example with the Binary to Seven Segments block. R = 0. For signed or unsigned integers R = 0. OR. Data output. that is. Binary to Seven Segments Block Example Bitwise Logical Bus Operator The Bitwise Logical Bus Operator block performs bitwise AND. Description © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Figure 4–1. Table 4–4 shows the Bitwise Logical Bus Operator block inputs and outputs.[R] is an input port. (4) Explicit means that the port bit width information is a block parameter.Chapter 4: Gate & Control Library Bitwise Logical Bus Operator 4–3 Table 4–3. (2) [L] is the number of bits on the left side of the binary point. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Data input b. [L]. [1] is a single bit.[0] VHDL O1: in STD_LOGIC_VECTOR(6 DOWNTO 0) Type (4) Explicit Notes to Table 4–3: (1) For signed integers and signed binary fractional numbers. (3) I1[L]. the MSB is the sign bit. or XOR logical operations on two input buses. For single bits. that is. (3) O1[7].

Table 4–6.[] >= 0 (Parameterizable) []. Table 4–5. Signed Fractional. O1[L]. that is.[R] is an input port. [1] is a single bit. (3) I1[L]. Unsigned Integer Description Specify the bus number format that you want to use.[R1] O1[L1]. [L]. (3) I1[L1]. [number of bits]. that is.[R] is an output port. (Note 1) VHDL Type (4) Explicit Explicit Explicit I1: in STD_LOGIC_VECTOR({L1 + R1 . (2) [L] is the number of bits on the left side of the binary point. (4) Explicit means that the port bit width information is a block parameter. XOR Specify the number of bits to the left of the binary point. the MSB is the sign bit. For single bits.1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L1 + R1 . For signed or unsigned integers R = 0.[R1] I2[L1].1} DOWNTO 0) O1: in STD_LOGIC_VECTOR({L1 + R1 . OR. Bitwise Logical Bus Operator Block I/O Formats I/O I O Simulink (2). Bitwise Logical Bus Operator Block Parameters Name Bus Type Value Signed Integer.[0]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.[R1] Notes to Table 4–6: (1) For signed integers and signed binary fractional numbers. including the sign bit.[number of bits] >= 0 (Parameterizable) Logic Operation AND.4–4 Chapter 4: Gate & Control Library Bitwise Logical Bus Operator Table 4–5 shows the Bitwise Logical Bus Operator block parameters. use a Bus Conversion block to set the width. Figure 4–2. Table 4–6 shows the Bitwise Logical Bus Operator block I/O formats. Specify the logical operation to perform. Bitwise Logical Bus Operator Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . R = 0.1} DOWNTO 0) Figure 4–2 shows an example with the Bitwise Logical Bus Operator block. [R] is the number of bits on the right side of the binary point. To specify the bus format of an implicit input port. Specify the number of bits to the right of the binary point.

Table 4–9.1} DOWNTO 0) Type (4) Explicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . A separate output is provided for each case.4. You can implement multiple cases with a comma (. Data Bus Type [number of bits].5 in the Case Values box. for four cases if the first has two conditions. including the sign bit. which you can use for combinational functions. Table 4–7 shows the Case Statement block inputs and outputs. You can have multiple conditions for each case with a pipe (|) to separate the conditions.5|-1.[] [].[number of bits] Enable Pipeline >= 0 Specify the number of bits to the left of the binary point.[R1] VHDL I1: in STD_LOGIC_VECTOR({LP1 + RP1 . enter 1|2. For example. A comma at the end of the case values is ignored. Provide Default Case On or Off Table 4–9 shows the Case Statement block I/O formats. Case Statement Block Inputs and Outputs Signal unnamed 0 to n Direction Input Output Data input.4. Case Statement Block Parameters Name Case Statement Value Description User defined Specify the values with which you want to compare the input. Description Table 4–8 shows the Case Statement block parameters. Unsigned Integer Specify the bus number format that you want to use. (3) I1[L1]. (Parameterizable) >= 0 Specify the number of bits to the right of the binary point. Table 4–8. Table 4–7.Chapter 4: Gate & Control Library Case Statement 4–5 Case Statement This Case Statement block contains boolean operators. (Parameterizable) On or Off Turn on if you want pipeline the output result. Use a comma (Parameterizable) between each case and separate conditions by a pipe (|). Case Statement Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2).3. Turn on if you want the others output signal to go high when all the other outputs are false. The Case Statement block compares the input signal (which must be a signed or unsigned integer) with a set of values (or cases).7 Signed Integer. A single-bit output generates for each case. For example: 1|2|3.) to separate each case.

that is. Case Statement Block I/O Formats (Part 2 of 2) (Note 1) I/O O … Oi[1] …. r3 <= '0'.[0]. [R] is the number of bits on the right side of the binary point.[R] is an output port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. For single bits. (2) [L] is the number of bits on the left side of the binary point. On: out STD_LOGIC VHDL Type (4) Explicit Figure 4–3 shows an example model with the Case Statement block. On[1] Notes to Table 4–9: (1) For signed integers and signed binary fractional numbers. r3 <= '0'. when "00000100" | "00000110" => r0 <= '0'. Case Statement Block Example The following VHDL code generates from the model in Figure 4–3: caseproc:process( input ) begin case input is when "00000001" | "00000010" | "00000011" => r0 <= '1'. use a Bus Conversion block to set the width.4–6 Chapter 4: Gate & Control Library Case Statement Table 4–9. when "00000100" => r0 <= '0'. r2 <= '0'. (3) O1[1] O1: out STD_LOGIC … Oi: out STD_LOGIC …. R = 0. r1 <= '1'. (3) I1[L]. Simulink (2).[R] is an input port. that is. [1] is a single bit. r4 <= '0'. O1[L]. [L]. the MSB is the sign bit. To specify the bus format of an implicit input port. r4 <= '0'. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . (4) Explicit means that the port bit width information is a block parameter. r1 <= '0'. For signed or unsigned integers R = 0. r2 <= '0'. Figure 4–3.

Data output (1 = match. If the specified value is not representable in the data type of the input bus. if they do not match it outputs a 0.[number of bits] >= 0 (Parameterizable) Register Output Decoded Value On or Off User defined (Parameterizable) Specify the number of bits to the left of the binary point. Decoder Block Parameters Name Input Bus Type Value Signed Integer. r1 <= '0'. Signed Fractional. Decoder Block Inputs and Outputs Signal in match Direction Input Output Data input. Table 4–11. end case. r4 <= '0'. 1 The Case Statement block output ports in the VHDL are named r<number> where <number> is auto-generated. r1 <= '0'. Specify the decoded value for matching. This option is zero (0) unless Signed Fractional is selected. For example: 5 (binary 101) as a 2 bit unsigned integer results in 1 (binary 01). end process. Unsigned Integer Description Specify the bus number format that you want to use. [number of bits]. r3 <= '1'. when others => r0 <= '0'.Chapter 4: Gate & Control Library Decoder 4–7 r1 <= '0'. the block outputs a 1. Decoder The Decoder block is a bus decoder that compares the input value against the specified decoded value. Table 4–10 shows the Decoder block inputs and outputs. Description Table 4–11 shows the Decoder block parameters. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Turn this option on if you want to register the output result. r3 <= '0'. Table 4–10. Specify the number of bits to the right of the binary point for the gain. If the values match. 0 = mismatch). r4 <= '0'. r2 <= '0'.[] >= 0 (Parameterizable) []. it is truncated to the data type of the input bus. r2 <= '0'. when "00000111" => r0 <= '0'. r3 <= '0'. r2 <= '1'. r4 <= '1'.

Optional clock enable port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Output ports. For signed or unsigned integers R = 0. the MSB is the sign bit. Figure 4–4. For single bits. Table 4–13. Optional synchronous clear port. (3) I1[L]. R = 0. Select control port. [1] is a single bit. (2) [L] is the number of bits on the left side of the binary point. Description DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . O1[L]. The sel input is an unsigned integer bus. Table 4–12. [L].[R] is an output port.4–8 Chapter 4: Gate & Control Library Demultiplexer Table 4–12 shows the Decoder block I/O formats.[0].[R] is an input port. that is.[R1] O1[1]. [R] is the number of bits on the right side of the binary point. The value of the input d is output to the selected output. Figure 4–4 shows an example with the Decoder block. Demultiplexer Block Inputs and Outputs Signal d sel ena sclr 0–(n-1) Direction Input Input Input Input Output Data input port. (4) Explicit means that the port bit width information is a block parameter. Table 4–13 shows the Demultiplexer block inputs and outputs. (3) I1[L1]. use a Bus Conversion block to set the width. All other outputs remain constant. Decoder Block I/O Formats I/O I O Simulink (2). Decoder Block Example Demultiplexer The Demultiplexer block is a 1-to-n demultiplexer that uses full encoded binary values. To specify the bus format of an implicit input port. that is.[0] O1: in STD_LOGIC (Note 1) VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 .1} DOWNTO 0) Type (4) Explicit Explicit Notes to Table 4–12: (1) For signed integers and signed binary fractional numbers.

(Note 2) VHDL Type (5) Implicit Implicit I1: in STD_LOGIC_VECTOR({L + R1 . [L].[0]..[R] I3[1] I4[1] O O1[L]. [1] is a single bit.. use a Bus Conversion block to set the width. the MSB is the sign bit.. For single bits.1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L + R .. Demultiplexer Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Table 4–15. Turn on to use the clock enable input (ena). On: out STD_LOGIC_VECTOR({L + R . For signed or unsigned integers R = 0. On[L].[R] . (2) For signed integers and signed binary fractional numbers.[R] is an input port.Chapter 4: Gate & Control Library Demultiplexer 4–9 Table 4–14 describes the parameters for the Demultiplexer block. Number of Output Data Lines An integer greater than 1 (Parameterizable) Use Enable Port Use Synchronous Clear Port On or Off On or Off Table 4–15 shows the Demultiplexer block I/O formats. O1[L]. Figure 4–5.1} DOWNTO 0) Implicit Implicit Figure 4–5 shows an example with the Demultiplexer block.1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. (3) [L] is the number of bits on the left side of the binary point. [R] is the number of bits on the right side of the binary point. Demultiplexer Block Parameters Name Value Description Specify how many outputs you want the demultiplexer to have.[R] I2[L]. that is. (5) Explicit means that the port bit width information is a block parameter. To specify the bus format of an implicit input port.[R] (1) Notes to Table 4–15: (1) Where I is the number of outputs to the demultiplexer. R = 0. (4) I1[L].[R] is an output port. Turn on to use the synchronous clear input (sclr). that is. Table 4–14. Demultiplexer Block I/O Formats I/O I Simulink (3).1} DOWNTO 0) . (4) I1[L].

Enable port. When active this sets the output and internal state to 1 for the remainder/duration of the clock cycle. else if (0 == aprn) Q = 1. else if (0 == aprn) Q = 1. Single Bit Description Specify the type of flipflop to implement. Specify the bus number format that you want to use. [number of bits]. the signal is processed with n 1-bit TFFE flipflops. Asynchronous clear port. Specify the number of bits to the right of the binary point for the gain. Unsigned Integer. The aclrn port is an active-low asynchronous clear port. Table 4–17. Table 4–17 shows the Flipflop block parameters. Asynchronous reset port. For example. The aprn port is an active-low asynchronous preset port. Output port. for a TFFE flipflop with an n-bit signal. Flipflop Block Inputs and Outputs Signal input ena aprn aclrn Q Direction Input Input Input Input Output Data or togggle port.4–10 Chapter 4: Gate & Control Library Flipflop Flipflop Set the Flipflop block as a D-type flipflop with enable (DFFE) or T-type flipflop with enable (TFFE).[number of bits] >= 0 (Parameterizable) Specify the number of bits to the left of the binary point. Table 4–16 shows the Flipflop block inputs and outputs. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Signed Fractional. else if (1 == ena) Q = D TFFE mode: if (0 == aclrn) Q = 0. else if (1 == ena) and (1 == T) Q = toggle 1 DSP Builder does not support (aclrn == 0) and (aprn == 0). Flipflop Block Parameters Name Mode Bus Type Value DFFE or TFFE Signed Integer.[] >= 0 (Parameterizable) []. If the number of bits is set to more than 1. This option is zero (0) unless you select Signed Fractional. Description DFFE mode: if (0 == aclrn) Q = 0. the block behaves as single-bit flipflops for each bit. Table 4–16. When active this sets the output and internal state to 0 for the remainder/duration of the clock cycle.

(2) [L] is the number of bits on the left side of the binary point. For single bits.[0] I2[1]. (4) Explicit means that the port bit width information is a block parameter. Description © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Optional ELSE output port (high when false). Output port (high when true). Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. For signed or unsigned integers R = 0. use a Bus Conversion block to set the width.1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC O1: in STD_LOGIC_VECTOR({L1 . [1] is a single bit. that is. Table 4–18. O1[L].[0]. Flipflop Block I/O Formats I/O I Simulink (2). If Statement Block Inputs and Outputs Signal a–j n true false Direction Input Input Output Output Input ports. Flipflop Block Example If Statement The If Statement block outputs a 0 or 1 result based on the IF condition expression. that is.[0] I3[1]. [L]. R = 0. (Note 1) VHDL Type (4) Explicit I1: in STD_LOGIC_VECTOR({L1 . (3) I1[L1].Chapter 4: Gate & Control Library If Statement 4–11 Table 4–18 shows the Flipflop block I/O formats.[0] O O1[L1]. [R] is the number of bits on the right side of the binary point.[0] I4[1]. the MSB is the sign bit.1} DOWNTO 0) Explicit Figure 4–6 shows an example with the Flipflop block.[R] is an output port. Figure 4–6.[R] is an input port. Table 4–19 shows the If Statement block inputs and outputs. Table 4–19. Optional ELSE IF input port. (3) I1[L]. To specify the bus format of an implicit input port.[0] Notes to Table 4–18: (1) For signed integers and signed binary fractional numbers.

0 is treated as a signal not a boolean. In other words.found 0 possible definitions" where /= is the hardware translation of the 'not equal to' operator. carefully check the expressions specified in the If Statement blocks. The correct syntax for this expression is just (a>b). otherwise you receive an error at HDL generation of the following form: Can't determine definition of operator "<mixed operator>" -. and booleans (the 'true' or 'false' result of such operations) only compare with and operate with booleans. so the hardware generation fails with an error: Can't determine definition of operator ""/="" -. where a. That is. The following examples of bad syntax give errors: ■ (a>b)&c. the types must be the same on either side of an operator. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . ensure that the operators are always operating on the same types. Here (a>b) returns a boolean ('true' or 'false') and is ANDed with signal c.4–12 Chapter 4: Gate & Control Library If Statement You can build an IF condition expression with the signal values 0 or 1 and any of the permitted operators given in Table 4–20.found 0 possible definitions If you receive this error. 0 and 1. as signals rather than as booleans.b and c are all input values to the If Statement. Table 4–20. Supported If Statement Block Operators Operator & | $ = ~ > < () AND OR XOR Equal To Not Equal To Greater Than Less Than Parentheses Operation When writing expressions in an If Statement block. This operation is ill defined and results in the following error: Can't determine definition of operator ""&"" -.found 0 possible definitions ■ ((a>b)~0) Again (a>b) returns a boolean ('true' or 'false'). and is unnecessary. bus signals compare with and operate with bus signals. Here the ~0 incorrectly means 'not false'. Treat an If statement expression.

This option turns on the else input.[R] is an input port. 1. Use ELSE Output Port On or Off Use ELSE IF Input Port On or Off Table 4–22 shows the If Statement block I/O formats. the MSB is the sign bit. <. This option is zero (0) unless Signed Fractional is selected.[R1] … I1: in STD_LOGIC_VECTOR({L1 + R1 . or j. O1[L].Chapter 4: Gate & Control Library If Statement 4–13 Table 4–21 shows the If Statement block parameters. (3) I1[L]. Data Bus Type Signed Integer. (Note 1) VHDL Type (4) Implicit Simulink (2). Ii[LI].[] []. The selected type must be capable of expressing 0 and 1 exactly. Specify the if condition with any of the following operators: &. (3) I1[L1]. If Statement Block Parameters Name Number of Inputs IF Expression 2–10 User Defined Value Description Specify the number of inputs to the If Statement. |. If Statement Block I/O Formats I/O I …. Table 4–22.1} DOWNTO 0) …. when you want to cascade multiple IF Statement blocks together or as an enable for the block. For single bits. Specify the number of bits to the right of the binary point for the gain. the variables a. and the single digit numerals 0. i. that is. Specify the bus number format that you want to use. [1] is a single bit. c. f. $. e.[0]. (4) Explicit means that the port bit width information is a block parameter. >. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. In: in STD_LOGIC_VECTOR({LN + RN . Table 4–21.[RI] … In[LN]. Unsigned Integer Single Bit.[number of bits] Specify the number of bits to the left of the binary point. Signed Fractional. h.[RN] O O1[1] O2[1] Notes to Table 4–22: (1) For signed integers and signed binary fractional numbers. which implements an ELSE condition and goes high if the condition evaluated by the If Statement block is false. [R] is the number of bits on the right side of the binary point. use a Bus Conversion block to set the width.[R] is an output port. =. (2) [L] is the number of bits on the left side of the binary point. [L]. that is. d. which implements an ELSE IF input. g. R = 0.1} DOWNTO 0) O1: out STD_LOGIC O2: out STD_LOGIC Explicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . To specify the bus format of an implicit input port.1} DOWNTO 0) Ii: in STD_LOGIC_VECTOR({LI + RI . or (). ~. This option turns on the false output. b. For signed or unsigned integers R = 0. Inferred >= 0 (Parameterizable) >= 0 (Parameterizable) [number of bits].

The register output bits can optionally be XORed or XNORed together. The register output bits shift from LSB to most significant bit (MSB) with the output sout connected to the MSB of the shift register. Default LFSR Sequence Block with Length 8 Circuitry In this default structure: ■ ■ ■ ■ The polynomial is a primitive or maximal-length polynomial All registers are initialized to one The feedback gate type is XOR The feedback structure is an external n-input gate or many to one You can modify the implemented LFSR sequence by changing the parameter values. Figure 4–8.4–14 Chapter 4: Gate & Control Library LFSR Sequence Figure 4–7 shows an example of the If Statement block. For example. when choosing an LFSR sequence of length eight. which implements the conditional statement: Quantizer: if (Input<-4) Output = -100 else if ((Input>=-4) & (Input<10)) Output = 0 else Output = 100 Figure 4–7. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . the default polynomial is x8 + x4 + x3 + x2 + 1 with the circuitry that Figure 4–8 shows. If Statement Block Example LFSR Sequence The LFSR Sequence block implements a linear feedback shift register that shifts one bit across L registers.

Specify the name of the clock signal. Description Optional clock enable port. Turn on to use the parallel output (pout). If this value is larger than is represented in the shift register (set by LFSR Length) the unrepresentable bits are truncated. Specify the type of feedback gate to implement. Turn on to explicitly specify the clock name.Chapter 4: Gate & Control Library LFSR Sequence 4–15 For example. The numbers should be enclosed in square brackets. Figure 4–9. LFSR Sequence Block Parameters (Part 1 of 2) Name LFSR Length Feedback Structure Feedback Gate Type Initial Register Value (Hex) Value User Defined (Parameterizable) External n-inputs gate. For example. Table 4–24 shows the LFSR Sequence block parameters. Specify the initial values in the register. Internal two-inputs gate XOR or XNOR Any Hexadecimal Number (Parameterizable) Description Specify the LFSR length as an integer. [0 3 10]. Specify where the taps occur in the shift register. Table 4–23. Serial output port for MSB of the LFSR. 1 denotes the LSB and the LFSR length denotes the MSB. Primitive Polynomial User-Defined Array of Tap Sequence Polynomial Coefficients (Parameterizable) Specify Clock Clock Use Parallel Output On or Off User defined (Parameterizable) On or Off © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . DSP Builder implements the circuitry (Figure 4–9). after changing the feedback structure to an internal two-inputs gate. Table 4–24. Internal 2-Input Gate Circuitry This circuitry changes the sequence from: 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 to: 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 Table 4–23 shows the LFSR Sequence block inputs and outputs. There must be a minimum of 2 taps. LFSR Sequence Block Inputs and Outputs Signal ena rst sout pout Direction Input Input Output Output Optional reset port. Specify whether you want an external n-inputs gate (many-to-one) or internal two-inputs gate (one-to-many) structure. Optional parallel output port for LFSR unsigned value.

[R] is an input port. Specify the operator you want to use. If the integer is positive.[0] I2[1]. (2) [L] is the number of bits on the left side of the binary point. [R] is the number of bits on the right side of the binary point. OR. NAND. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . that is. XOR. the MSB is the sign bit. VHDL I1: in STD_LOGIC I2: in STD_LOGIC O1: out STD_LOGIC O2: out STD_LOGIC_VECTOR(L-1 DOWNTO 0) Type — — — — Figure 4–10 shows an example with the LFSR Sequence block. Table 4–25. (3) I1[1]. NOR.[0]. (3) I1[L]. For signed or unsigned integers R = 0. The number of inputs is variable. LFSR Sequence Block I/O Formats (Note 1) I/O I O Simulink (2). otherwise it is interpreted as 0. Table 4–26.[0] Notes to Table 4–25: (1) For signed integers and signed binary fractional numbers.[0] O2[L]. Turn on to use the synchronous clear input (sclr). O1[L]. [L]. [1] is a single bit. Logical Bit Operator Block Parameters Name Logical Operator Number of Inputs Value Description AND. Table 4–25 shows the LFSR Sequence block I/O formats.4–16 Chapter 4: Gate & Control Library Logical Bit Operator Table 4–24.[0] O1[1]. This parameter defaults to 1 if the NOT logical (Parameterizable) operator is selected. Table 4–26 shows the Logical Bit Operator block parameters. that is.[R] is an output port. Figure 4–10. it is interpreted as a boolean 1. LFSR Sequence Block Parameters (Part 2 of 2) Name Use Enable Port Use Synchronous Clear Port On or Off On or Off Value Description Turn on to use the clock enable input (ena). R = 0. LFSR Sequence Block Example Logical Bit Operator The Logical Bit Operator block performs logical operations on single-bit inputs. For single bits. You can specify a variable number of inputs. NOT 1–16 Specify the number of inputs.

a right shift operation preserves the input data sign (for signed inputs).[R] is an output port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. (2) [L] is the number of bits on the left side of the binary point. XOR. O1[L]. [R] is the number of bits on the right side of the binary point. Figure 4–11. [L]. the MSB is the sign bit. or a shift (rotate) operation by entering the number of bits. To specify the bus format of an implicit input port. that is. (3) I1: in STD_LOGIC … Ii: in STD_LOGIC ….Chapter 4: Gate & Control Library Logical Bus Operator 4–17 Table 4–27 shows the Logical Bit Operator block I/O formats. use a Bus Conversion block to set the width. You can perform masking by entering a mask value in decimal notation. For single bits. Table 4–27. OR.[0]. By default. (3) I1[L]. Logical Bit Operator Block Example Logical Bus Operator The Logical Bus Operator block performs logical operations on a bus such as AND. Logical Bit Operator Block I/O Formats I/O I I1[1] … Ii[1] ….[R] is an input port. (4) Explicit means that the port bit width information is a block parameter. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . that is. [1] is a single bit. R = 0. (Note 1) VHDL Type (4) Explicit Simulink (2). and invert. In: in STD_LOGIC O1: out STD_LOGIC Explicit Figure 4–11 shows an example with the Logical Bit Operator block. In[1] O O1[1] Notes to Table 4–27: (1) For signed integers and signed binary fractional numbers. For signed or unsigned integers R = 0.

Shift Left. [R] is the number of bits on the right side of the binary point. Signed Fractional. Specify the number of bits to the right of the binary point. Logical Bus Operator Block I/O Formats I/O I O Simulink (2). XOR.[0].[number of bits] Logical Operation Specify the number of bits to the left of the binary point. For signed or unsigned integers R = 0. Table 4–29. Specify the logical operation to perform. Mask Value Specify the mask value for an AND. or XOR operation as an unsigned integer representing the required mask. To specify the bus format of an implicit input port. [1] is a single bit. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. [number of bits]. (3) I1[L]. O1[L].4–18 Chapter 4: Gate & Control Library Logical Bus Operator Table 4–28 shows the Logical Bus Operator block inputs and outputs. Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) AND. including the sign bit. (2) [L] is the number of bits on the left side of the binary point. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Turn on to preserve the input data sign when right shifting signed data. use a Bus Conversion block to set the width. (3) I1[L1]. Specify how many bits you want to shift when you chose a shift or rotate operation.[R] is an output port.[] []. For single bits. Description Table 4–29 shows the Logical Bus Operator block parameters. R = 0. that is. Rotate Left. Logical Bus Operator Block Parameters Name Bus Type Value Signed Integer. OR. the MSB is the sign bit. Shift Right.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({L1 + R1 .1} DOWNTO 0) Type (4) Explicit Explicit Notes to Table 4–30: (1) For signed integers and signed binary fractional numbers. (4) Explicit means that the port bit width information is a block parameter.[R1] (Note 1) VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . Table 4–30. Logical Bus Operator Block Inputs and Outputs Signal d q Direction Input Output Input data. Number of Bits to Shift User Defined (Parameterizable) Sign Extend On or Off Table 4–30 shows the Logical Bus Operator block I/O formats. OR. Invert. [L]. Rotate Right Integer (Parameterizable) Description Specify the bus number format that you want to use.[R1] O1[L1].[R] is an input port. Output data. that is. which must have the same number of bits as the input. Table 4–28.

© June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Description Table 4–32 shows the Logical Reduce Operator block parameters. Figure 4–12.[] >= 0 (Parameterizable) Specify the number of bits to the left of the binary point. Signed Fractional.Chapter 4: Gate & Control Library Logical Reduce Operator 4–19 Figure 4–12 shows an example with the Logical Bus Operator block. Signed Integer. Table 4–31. Logical Reduce Operator Block Inputs and Outputs Signal d q Direction Input Output Input data. Table 4–31 shows the Logical Reduce Operator block inputs and outputs. The logical operation is applied bit-wise to the input bus to give a single bit result. [number of bits]. Logical Bus Operator Block Example Logical Reduce Operator The Logical Reduce Operator block performs logical reduction operations on a bus such as AND. Output result. Unsigned Integer Description Specify the bus number format that you want to use. XOR. including the sign bit. Table 4–32. Logical Reduce Operator Block Parameters (Part 1 of 2) Name Bus Type Value Inferred. OR.

the MSB is the sign bit.[R] is an output port. (2) [L] is the number of bits on the left side of the binary point. OR. The output width of the multiplexer is equal to the maximum width of the input data lines. use a Bus Conversion block to set the width. Table 4–33. Specify the logical operation to perform.4–20 Chapter 4: Gate & Control Library Multiplexer Table 4–32. [R] is the number of bits on the right side of the binary point. [L]. The block works on any data type and sign extends the inputs if there is a bit width mismatch. Logical Reduce Operator Block I/O Formats (Note 1) I/O I O Simulink (2). For single bits. Figure 4–13 shows an example with the Logical Reduce Operator block. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Figure 4–13. For signed or unsigned integers R = 0. NAND. (3) I1[L].[R] is an input port.[0].1} DOWNTO 0) Type (4) Explicit Explicit Notes to Table 4–30: (1) For signed integers and signed binary fractional numbers.[R1] O1[1] O1: out STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . O1[L].[number of bits] >= 0 (Parameterizable) Logical Reduction Operation AND. (4) Explicit means that the port bit width information is a block parameter. Logical Reduce Operator Block Parameters (Part 2 of 2) Name Value Description Specify the number of bits to the right of the binary point. Table 4–34 shows the Multiplexer block inputs and outputs. [1] is a single bit. that is. R = 0. XOR. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. []. To specify the bus format of an implicit input port. (3) I1[L1]. NOR Table 4–33 shows the Logical Reduce Operator block I/O formats. that is. Logical Reduce Operator Block Example Multiplexer The Multiplexer block operates as either a n-to-1 one-hot or full-binary bus multiplexer with one select control.

that is. [R] is the number of bits on the right side of the binary point. In: in STD_LOGIC_VECTOR({Ln + Rn . Multiplexer Block Inputs and Outputs Signal sel 0–(n-1) ena aclr <unnamed> Direction Input Input Input Input Output Select control port.Chapter 4: Gate & Control Library Multiplexer 4–21 Table 4–34. Optional asynchronous clear port. Output port. (4) Explicit means that the port bit width information is a block parameter. Table 4–35. [L]. O1[L].[max(Ri)] with (0 < I < i + 1) Notes to Table 4–36: (1) For signed integers and signed binary fractional numbers. Turn on to use the clock enable input (ena). use a Bus Conversion block to set the width.[Rn] In+1[1] In+2[1] O O1[max(Li)].1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 + R2 . Multiplexer Block I/O Formats (Note 1) I/O I Simulink (2).[0]. For signed or unsigned integers R = 0. R = 0. Turn on to use one-hot selection for the bus select signal instead of full binary. Number of Input Data Lines An integer greater than 1 (Parameterizable) Number of Pipeline Stages One Hot Select Bus Use Enable Port Use Asynchronous Clear Port On or Off On or Off On or Off >= 0 (Parameterizable) Specify the number of pipeline stages. Optional enable port.1} DOWNTO 0) …. Multiplexer Block Parameters Name Value Description Specify how many inputs the multiplexer has. To specify the bus format of an implicit input port.1} DOWNTO 0) … Ii: in STD_LOGIC_VECTOR({Li + Ri . This option is available only when the number of pipeline stages is greater than 0.[R2] ….1} DOWNTO 0) Type (4) Implicit Implicit Figure 4–14 shows an example with the Multiplexer block.[R] is an input port. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . [1] is a single bit. Table 4–36.[Ri] … In[Ln]. (2) [L] is the number of bits on the left side of the binary point.1} DOWNTO 0) In+1: STD_LOGIC In+2: STD_LOGIC O1: out STD_LOGIC_VECTOR({max(Li)) + max(Ri) . that is. Turn on to use the asynchronous clear input (aclr).[0] (select input) I2[L2]. Ii[Li]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. For single bits. (3) I1[LS]. Description Table 4–35 shows the Multiplexer block parameters.[R] is an output port. (3) I1[L]. This option is available only when the number of pipeline stages is greater than 0. Data input ports. Table 4–36 shows the Multiplexer block I/O formats. VHDL I1: in STD_LOGIC_VECTOR({L1 . the MSB is the sign bit.

You can enter the required pattern as a binary sequence. For example. Table 4–38. Multiplexer Block Example Pattern The Pattern block generates a repeating periodic bit sequence in time. the pattern 01100 outputs the repeating pattern: 0110001100011000110001100011000110001100 You can change the output data rate for a registered block by feeding the clock enable input with the output of the Pattern block. User defined Specify the name of the required clock signal.4–22 Chapter 4: Gate & Control Library Pattern Figure 4–14. (Parameterizable) DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . the Pattern block acts as a constant. Optional synchronous clear port. holding its output to the specified value at all times. Output data port. Pattern Block Inputs and Outputs Signal ena sclr <unnamed> Direction Input Input Output Description Optional clock enable port. 1 With a sequence of length 1. Table 4–37. There is no artificial limit to the pattern length. Turn on to explicitly specify the clock name. Table 4–38 shows the Pattern block parameters. Pattern Block Parameters (Part 1 of 2) Name Binary Sequence Specify Clock Clock Value User Defined On or Off Description Specify the sequence that you want to use. Table 4–37 shows the Pattern block inputs and outputs.

Pattern Block I/O Formats I/O I O Simulink (2). Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Pattern Block Example Single Pulse The Single Pulse block generates a single pulse output signal. (4) Explicit means that the port bit width information is a block parameter. R = 0. [R] is the number of bits on the right side of the binary point. Table 4–40 shows the Single Pulse block inputs and outputs. The output signal is a single bit that takes only the values 1 or 0. a step up (0 to 1). or a step down (1 to 0). (Note 1) VHDL Type (4) Explicit . Pattern Block Parameters (Part 2 of 2) Name Use Enable Port Value On or Off Description Turn on to use the clock enable input (ena).optional Explicit I1: in STD_LOGIC I2: in STD_LOGIC O1: out STD_LOGIC Figure 4–15 shows an example with the Pattern block. For single bits. that is. [1] is a single bit. (3) I1[L]. The signal generation type can be an impulse. (3) I1[1] I2[1] O1[1] Notes to Table 4–39: (1) For signed integers and signed binary fractional numbers. (2) [L] is the number of bits on the left side of the binary point. For signed or unsigned integers R = 0. Table 4–39.[R] is an output port. Use Synchronous Clear Port On or Off Table 4–39 shows the Pattern block I/O formats. use a Bus Conversion block to set the width. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . The output of a step down starts at 1 changing to 0 after a specified delay. that is.Chapter 4: Gate & Control Library Single Pulse 4–23 Table 4–38. The output of a step up starts at 0 changing to 1 after a specified delay.optional Explicit . Turn on to use the synchronous clear input (sclr). the MSB is the sign bit. [L]. Figure 4–15. The output of a impulse starts at 0 changing to 1 after a specified delay and changing to 0 again after a specified length.[0]. O1[L]. To specify the bus format of an implicit input port.[R] is an input port.

Single Pulse Block Parameters Name Signal Generation Type Value Step Up. Figure 4–16. Specify the number of clock cycles that occur before the pulse transition.4–24 Chapter 4: Gate & Control Library Single Pulse Table 4–40. Step Down. Table 4–41 shows the Single Pulse block parameters. Table 4–41. Impulse Length Delay Specify Clock Clock Use Enable Port Specify the number of clock cycles for which the output signal is transitional from 0 to 1 for an Impulse type output. Table 4–42. Output port. shows an example of a Single Pulse block. Use Synchronous Clear Port On or Off Table 4–42 shows the Single Pulse block I/O formats. Specify the name of the required clock signal. Optional synchronous clear port. Turn on to explicitly specify the clock name. Single Pulse Block I/O Formats I/O I O I1[1] I2[1] O1[1] Notes to Table 4–42: (1) I1[1] is an input port. O1[1] is an output port. Turn on to use the clock enable input (ena). Turn on to use the synchronous clear input (sclr). Single Pulse Block Inputs and Outputs Signal ena sclr <unnamed> Direction Input Input output Description Optional clock enable port. Simulink (1) I1: in STD_LOGIC I2: in STD_LOGIC O1: out STD_LOGIC VHDL Type Optional trigger Optional reset — Figure 4–16. Impulse Integer (Parameterizable) Integer (Parameterizable) On or Off User defined (Parameterizable) On or Off Description Specify the type of single pulse. Single Pulse Output Signal Types DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

the working directory for your SOPC Builder project must be the same as your DSP Builder working directory. ■ f For more information about the Avalon-MM interface. Interfaces Library Use the blocks in the Interfaces library to build custom logic blocks that support the Avalon® Memory-Mapped (Avalon-MM) and Avalon Streaming (Avalon-ST) interfaces. Wrapped versions of the Avalon-MM slave that implement an Avalon-MM read FIFO buffer and Avalon-MM write FIFO. For information about using SOPC Builder to create Nios II designs. After you synthesize your model and compile it in the Quartus II software. A file mydesign. f © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .mdl creates a component mydesign_interface in SOPC Builder. Your design automatically appears under the DSP Builder category in the SOPC Builder component browser peripherals listing if the MDL file is in the same directory as the SOPC file. use SOPC Builder to add it to your Nios II system. The Interfaces library contains the following blocks: ■ ■ ■ ■ ■ ■ ■ Avalon-MM Master Avalon-MM Slave Avalon-MM Read FIFO Avalon-MM Write FIFO Avalon-ST Packet Format Converter Avalon-ST Sink Avalon-ST Source Avalon Memory-Mapped Blocks The Avalon-MM blocks automate the process of specifying master and slave ports that are compatible with the Avalon-MM bus. refer to the Nios II Hardware Development Tutorial. you can add the following blocks to control the peripheral’s inputs and outputs: ■ Configurable master and slave blocks that contain the ports required to connect peripherals that use the Avalon-MM bus. After you build a model of your DSP Builder peripheral. refer to the Avalon Interface Specifications. 1 For the peripheral to appear in SOPC Builder.5.

Nios II processor.5–2 Chapter 5: Interfaces Library Figure 5–1 shows SOPC Builder with an on-chip RAM memory. Figure 5–1. and a DSP Builder created peripheral topavalon. DSP Builder & SOPC Builder Design Flow DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . SOPC Builder with DSP Builder Peripheral Figure 5–2 shows the design flow with DSP Builder and SOPC Builder. Figure 5–2.

Available when Write or Read/Write address type is chosen and the bit width is greater than 8. The address signal represents a byte address but is asserted on word boundaries only. Not required if there are no read transfers. Avalon-MM Blocks Example Avalon-MM Master The Avalon-MM Master block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-MM master interface. Write request signal. endofpacket Input © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .Chapter 5: Interfaces Library Avalon-MM Master 5–3 Figure 5–3 shows an example model with Avalon-MM blocks. Indicates an end-of-packet condition. If used. Available when Write or Read/Write address type is chosen. Not required if there are no read transfers. Not required if there are no write transfers. Signals Supported by the Avalon-MM Master Block (Part 1 of 2) Signal waitrequest address read readdata write writedata byteenable Direction Input Output Output Input Output Output Output Description This signal forces the master port to wait until you are ready to proceed with the transfer. Data lines for read transfers. Data lines for write transfers. Enables specific byte lane(s) during write transfers to memories of width greater than 8 bits. Figure 5–3. also use write. If used. Read request signal. Not required if there are no write transfers. also use readdata. also use writedata. Available with Read or Read/Write address type. Table 5–1. Available when Write or Read/Write address type is chosen. Table 5–1 lists the signals supported by the Avalon-MM Master block. Available when Allow Flow Control is on. also use read. All byteenable lines must be enabled during read transfers. Available when Read or Read/Write address type is chosen. If used. If used.

Flow control allows a slave port to regulate incoming transfers from a master port. This option is available when Allow Burst Transfers is on. Turn on to clear any pending transfers in the pipeline. including the sign bit. The number format of the bus. Indicates when one or more ports have requested an interrupt. Available when Receive IRQ is on and IRQ mode is set to Prioritized. Read and write buses must have the same number of bits. Use for pipelined read transfers with latency. so that a transfer only begins when the slave port indicates that it has valid data or is ready to receive data. Available when Allow Burst Transfers is on. The address type for the bus. Specifies the maximum width of a burst transfer. Figure 5–2 shows the Avalon-MM Master block parameters. This option is available when Allow Pipeline Transfers is on. Read/Write Signed Integer. Specifies the number of address bits. Signals Supported by the Avalon-MM Master Block (Part 2 of 2) Signal Direction Description Available when Allow Pipeline Transfers is on. but can return data every cycle thereafter. and maximize the throughput for slave ports that achieves the greatest efficiency when handling multiple units of data from one master port at a time. [number of bits]. This option is available when the address type is set to Write or Read/Write and the bit width is greater than 8. readdatavalid Input flush burstcount irq irqnumber Output Output Input Input 1 The direction in Table 5–1 refers to the direction in respect of the DSP Builder block interface. Allow Pipeline Transfers On or Off Use Flush Signal On or Off Allow Burst Transfers On or Off Maximum Burst Size 2–32 DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Signed Fractional. Available when Allow Pipeline Transfers and Use Flush Signal are on. Turn on to allow burst transfers. Indicates the interrupt priority. Table 5–2. Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) On or Off On or Off Specifies the clock signal name. Indicates the number of transfers in a burst.[] []. Pipeline transfers increase the bandwidth for synchronous slave peripherals that require several cycles to return data for the first access. Turn on to enable flow control. This parameter applies only to signed fractional buses. Can be asserted to clear any pending transfers in the pipeline. Avalon-MM Master Block Parameters (Part 1 of 2) Name Specify Clock Clock Address Width Address Type Data Type Value On or Off User defined 1–32 Read. Specifies the number of bits to the right of the binary point. Available when Receive IRQ is on. Turn on to use the Byte Enable signal. Write. Turn on to allow pipeline transfers. Lower value means higher priority.[number of bits] Allow Byte Enable Allow Flow Control Specifies the number of bits to the left of the binary point.5–4 Chapter 5: Interfaces Library Avalon-MM Master Table 5–1. Indicates that valid data is present on the readdata lines. This option is available when the address type is Read or Read/Write. Description Turn on to explicitly specify the clock name. A burst executes multiple transfers as a unit.

Figure 5–4. Individual Signals Description Turn on to enable interrupt requests from the slave port. refer to “Avalon Memory-Mapped Blocks” on page 5–1. Avalon-MM Master Block with All Signals Enabled f For general information about Avalon-MM blocks. This option is available when Receive IRQ is on. Figure 5–4 shows an Avalon-MM Master block with all signals enabled. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .Chapter 5: Interfaces Library Avalon-MM Master 5–5 Table 5–2. The interrupt request mode. Avalon-MM Master Block Parameters (Part 2 of 2) Name Receive IRQ IRQ Mode Value On or Off Prioritized.

The slave port ignores all other Avalon-MM signal inputs unless chipselect is asserted. Table 5–3. Data lines for write transfers. Available when Allow Pipeline Transfers is on and variable read latency is chosen. also use writedata. Asserted when a port needs to be serviced. also use writedata.5–6 Chapter 5: Interfaces Library Avalon-MM Slave Avalon-MM Slave The Avalon-MM Slave block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-MM slave interface. also use readdata. Available when Read or Read/Write address type is chosen. Available when Output IRQ is on. Indicates that the peripheral is ready for a write transfer. If used. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Not required if there are no write transfers. Indicates that the peripheral is ready for a read transfer. Asserted during the first cycle of every transfer. If used. Available when Allow Flow Control is on. Write-request signal. Interrupt request. Data lines for read transfers. Not required if there are no read transfers. Available when Allow Burst Transfers is on. also use waitrequest. Available when Write or Read/Write address type is chosen. Available when Use Chip Select is on. If used. Available when variable wait-state format is chosen. Use to stall the interface when the slave port cannot respond immediately. Marks the rising clock edge when readdata asserts. Available when Read or Read/Write access is chosen and Allow Flow Control is on. Read-request signal. Available when Allow Burst Transfers is on. writedata byteenable Output Output readyfordata dataavailable endofpacket readdatavalid waitrequest Input Input Input Input Input beginbursttransfer Output burstcount irq begintransfer chipselect Output Input Output Output 1 The direction in Table 5–3 refers to the direction in respect of the DSP Builder block interface. Not required if there are no read transfers. Indicates the number of transfers in a burst. Byte-enable signals to enable specific byte lane(s) during write transfers to memories of width greater than 8 bits. also use write. Asserted for the first cycle of a burst to indicate when a burst transfer is starting. Not required if there are no write transfers. Available when Allow Byte Enable is on and the bit width is greater than 8. If used. If used. Signals Supported by the Avalon-MM Slave Block Signal address read readdata write Direction Output Output Input Output Description Address lines to the slave port. Available when Write or Read/Write address type is chosen. Available when Read or Read/Write address type is chosen. Indicates an end-of-packet condition. Available when Write or Read/Write access is chosen and Allow Flow Control is on. Table 5–3 lists the signals supported by the Avalon-MM Slave block. Table 5–4 shows the Avalon-MM Slave block parameters. Specifies a word offset into the slave address space. also use read. If used. Available when Receive Begin Transfer is on.

Description Turn on to explicitly specify the clock name. Allow Pipeline Transfers On or Off Wait-State Format Fixed. Pipeline transfers increase the bandwidth for synchronous slave peripherals that require several cycles to return data for the first access. This option is available only when Allow Burst Transfer is on. Avalon-MM Slave Block Parameters Name Specify Clock Clock Address Width Address Alignment Address Type Data Type Value On or Off User defined 1–32 Native. Specifies the number of write wait state cycles. Turn on to enable flow control. Variable Read Wait-State Cycles 0–255 Write Wait-State Cycles 0–255 Read Latency Format Read Latency Cycles Fixed. so that a transfer only begins when the slave port indicates that it has valid data or is ready to receive data. even though it may require several cycles of latency to return the first unit of data. and maximize the throughput for slave ports that achieves the greatest efficiency when handling multiple units of data from one master port at a time. but can return data every cycle thereafter. Turn on to enable the chipselect signal. Latency determines the length of the data phase. This option is available only when the address type is set to Read or Read/Write. Turn on to receive begintransfer signals. A burst executes multiple transfers as a unit. Specifies the maximum width of a burst transfer. Specifies the number of read wait-state cycles. Flow control allows a slave port to regulate incoming transfers from a master port. Read/Write Signed Integer. Dynamic Read. For example. This option is available only when Allow Pipeline Transfers is on. [number of bits]. This option is available only when Allow Pipeline Transfers is on and Fixed read latency format is set. Signed Fractional. Turn on to use the Byte Enable signal. Use native address alignment or dynamic bus sizing. Write. Specifies the number of bits to the right of the binary point. This option is available only when the address type is set to Write or Read/Write. Turn on to allow pipeline transfers. Turn on to enable interrupt requests from the slave port. The address type for the bus. The required read latency format. The required wait-state format. Read and write buses must have the same number of bits. This option is available only when the wait-state format is set to Fixed. This parameter applies only to signed fractional buses. Specifies the pipeline read latency.[] [].Chapter 5: Interfaces Library Avalon-MM Slave 5–7 Table 5–4. This option is available only when the wait-state format is set to Fixed. Variable 0–8 Allow Burst Transfers On or Off Maximum Burst Size Output IRQ Receive BeginTransfer Use Chip Select 4–232 On or Off On or Off On or Off © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . a pipelined slave port (with no wait-states) can sustain one transfer per cycle. Specifies the number of address bits. independently of the address phase. Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) On or Off On or Off Specifies the clock signal name. including the sign bit.[number of bits] Allow Byte Enable Allow Flow Control Specifies the number of bits to the left of the binary point. The number format of the bus. Turn on to allow burst transfers.

Avalon-MM Slave Block with All Signals Enabled f For general information about Avalon-MM blocks refer to “Avalon Memory-Mapped Blocks” on page 5–1. Figure 5–5. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .5–8 Chapter 5: Interfaces Library Avalon-MM Slave Figure 5–5 shows an Avalon-MM Slave block with all signals enabled.

This port should be connected to Simulink blocks and is asserted whenever TestDataOut corresponds to real data. This port should be connected to DSP Builder blocks and should be connected to outgoing data from the user design. including the sign bit. Specifies the depth of the FIFO. For any simulation cycle where the Stall signal is asserted. For information about the Avalon-MM Slave block. This parameter does not apply to single-bit buses. indicates that the block is ready to receive data. It simulates stall conditions of the Avalon-MM bus and hence back pressure to the SOPC component. When asserted. the Ready output is de-asserted so that no data is lost. no Avalon-MM reads take place and the internal FIFO buffer fills. Signed Fractional. When full. This parameter applies only to signed fractional buses. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .[number of bits] >= 0 (Parameterizable) FIFO Depth >2 Specifies the number of bits to the left of the binary point. Table 5–5 lists the signals supported by the Avalon-MM Read FIFO block. Table 5–6.[] >= 0 (Parameterizable) []. Unsigned Integer The number format of the bus.Chapter 5: Interfaces Library Avalon-MM Read FIFO 5–9 Avalon-MM Read FIFO The Avalon-MM Read FIFO block is essentially an Avalon-MM Slave block configured to implement a read FIFO. Data DataValid TestDataOut Input Input Output TestDataValid Output Ready Output Table 5–6 shows the Avalon-MM Read FIFO block parameters. Signals Supported by the Avalon-MM Read FIFO Block Signal Stall Direction Input Description This port must be connected to Simulink blocks. Specifies the number of bits to the right of the binary point. Table 5–5. Avalon-MM Read FIFO Block Parameters Name Data Type Value Signed Integer. It is accessed by other Avalon-MM peripherals to obtain data when connected in SOPC Builder. This port should be connected to Simulink blocks and corresponds to the data received over the Avalon-MM bus. refer to “Avalon-MM Slave” on page 5–6. This port should be connected to DSP Builder blocks and should be asserted whenever the signal on the Data port corresponds to real data. Description [number of bits].

Figure 5–7. Avalon-MM Read FIFO Content DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Avalon-MM Read FIFO Figure 5–7 shows the content of the Avalon-MM Read FIFO block. Figure 5–6.5–10 Chapter 5: Interfaces Library Avalon-MM Read FIFO Figure 5–6 shows an Avalon-MM Read FIFO block.

the test data is cached by the Avalon-MM write converter and released in order. refer to “Avalon-MM Slave” on page 5–6. Unsigned Integer Description [number of bits]. Avalon-MM Write FIFO Block Parameters Name Data Type Value Signed Integer. For any simulation cycle where Stall is asserted.[] >= 0 Specifies the number of bits to the left of the binary point. (Parameterizable) This parameter does not apply to single-bit buses. Figure 5–8. when stall is de-asserted. This port must be connected to Simulink blocks. The data is passed to the DataOut port one cycle after the Ready input port is asserted. This parameter applies (Parameterizable) only to signed fractional buses. This port should be connected to DSP Builder blocks and is asserted whenever DataOut corresponds to real data. Avalon-MM Write FIFO © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . The number format of the bus. Signed Fractional. Table 5–7 lists the signals supported by the Avalon-MM Write FIFO block. Table 5–8. []. It indicates that the downstream hardware is ready for data. FIFO Depth >2 Specifies the depth of the FIFO buffer. This port must be connected to DSP Builder blocks. Signals Supported by the Avalon-MM Write FIFO Block Signal TestData Direction Input Description This port must be connected to Simulink blocks. This port should be connected to DSP Builder blocks and corresponds to the oldest unsent data sample received on the TestData port. one sample per clock. Stall Input Ready DataOut Input Output DataValid Output Table 5–8 shows the Avalon-MM Write FIFO block parameters. It simulates stall conditions of the Avalon-MM bus and hence underflow to the SOPC component. Table 5–7. f For information about the Avalon-MM Slave block. including the sign bit. It provides simulation data to the Avalon-MM write FIFO.[number of bits] >= 0 Specifies the number of bits to the right of the binary point. Figure 5–8 shows an Avalon-MM Write FIFO block.Chapter 5: Interfaces Library Avalon-MM Write FIFO 5–11 Avalon-MM Write FIFO The Avalon-MM Write FIFO block is essentially an Avalon-MM Slave block configured to implement a write FIFO.

The PFC operates on a single clock domain. refer to the Avalon Interface Specifications. Avalon-ST Packet Format Converter The Avalon-ST Packet Format Converter (PFC) block transforms packets received from one block to a different packet format required by another block. Figure 5–9. Avalon-ST Sink and Avalon-ST Source. The ready latency of the PFC block is zero and it can only connect to other Avalon-ST interfaces with a ready latency of zero. You specify the input packet format and the desired output packet format. then the appropriate control logic automatically generates. and supports multicast data. 1 Verilog HDL generates for the PFC block and you must therefore have a license that supports Verilog HDL when simulating in ModelSim. The blocks include an Avalon-ST Packet Format Converter. f For information about the Avalon-ST interface. Avalon-MM Write FIFO Content Avalon Streaming Blocks The Avalon Streaming blocks automate the process of specifying ports that are compatible with an Avalon-ST interface.5–12 Chapter 5: Interfaces Library Avalon-ST Packet Format Converter Figure 5–9 shows the content of the Avalon-MM Write FIFO block. where an input field is broadcast copied to multiple output fields. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . and provides field reassignment in time and space to one or more output packet interfaces. The PFC takes packet data from one or more input interfaces.

Each output interface has an additional error signal that asserts to indicate a frame delineation error. endofpacket. Data input bus for sink interface X. Table 5–9 lists the signals supported by the Avalon-ST Packet Format Converter block. If each interface supports fixed-length packets. f For more information about these signal types. valid. Description 1 © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Basic Packet Format Converter The PFC performs data mapping on a packet by packet basis. empty. Table 5–9. When the PFC has multiple output interfaces. and data signals. The interface with the longest packet limits the packet rate of the converter. The PFC block does not support Avalon-ST bursts or blocks on its output interfaces. the packets on each output interface are aligned so that the startofpacket signal is presented on the same clock cycle. Use the Split Data option to split the input or output data signals across additional ports named data0 through dataN. Figure 5–10. The PFC does not support bursts or blocks on its output interfaces. The PFC can then map fields from multiple input packets to multiple output packets. refer to the Avalon Interface Specifications. startofpacket. so that there is exactly one input packet on each input interface for one output packet on each output interface.Chapter 5: Interfaces Library Avalon-ST Packet Format Converter 5–13 Figure 5–10 shows the basic operation of the PFC. you can select a Multi-Packet Mapping option. Indicates the number of empty symbols for sink interface X during cycles that mark the end of a packet. Each input interface consists of the ready. Signals Supported by the Avalon-ST Packet Format Converter Block (Part 1 of 2) Signal reset_n inX_dataN inX_empty Direction Input Input Input Active-low reset signal.

Indicates that sink interface X is ready to output data. Avalon-ST Packet Format Converter Block Parameters Name Number of Sinks Number of Sources Split Data Value 1–16 1–16 On or Off Description Specifies the number of sink interfaces X. Signals Supported by the Avalon-ST Packet Format Converter Block (Part 2 of 2) Signal inX_endofpacket inX_startofpacket inX_valid outY_ready aclr inX_ready outY_dataN outY_empty outY_endofpacket Direction Input Input Input Input Input Output Output Output Output Description This signal marks the active cycle containing the end of the packet for sink interface X. Table 5–10. Specifies number of symbols per beat for source interface Y. Specifies the number of symbols per beat for sink interface X. When off. A quoted string or MATLAB variable that describes the packet format for source interface Y. Optional asynchronous clear port. outY_startofpacket Output outY_valid outYerror Output Output Table 5–10 shows the Avalon-ST Packet Format Converter block parameters. When on. the data signals on the sink and source interface are split into signals named data0 through dataN with widths corresponding to the specified symbol width. This signal marks the active cycle containing the start of the packet for source interface Y.5–14 Chapter 5: Interfaces Library Avalon-ST Packet Format Converter Table 5–9. This signal marks the active cycle containing the start of the packet for sink interface X. Multi-Packet Mapping On or Off Symbol Width Use Asynchronous Clear Port Sink Format X Sink X Symbols Per Beat Source Format Y >= 1 On or Off string 1–32 string Source Y Symbols Per Beat 1–32 DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Specifies the number of source interfaces Y. Indicates DSP Builder can accept data for sink interface X. Specifies the number of bits per symbol that all the PFC sink and source interfaces use. Turn on to use the asynchronous clear input (aclr). A quoted string or MATLAB variable that describes the packet format for sink interface X. When on. Indicates that valid data is available on source interface Y. Indicates the number of empty symbols for source interface Y during cycles that mark the end of a packet. one input packet is matched to one output packet and the input and output packets must have the name number of instances in each field. the PFC maps the input packets to output packets such that all instances of every data field are accounted for. This signal marks the active cycle containing the end of the packet for source interface Y. Indicates that the sink driven by the source interface Y is ready to accept data. Data output bus for source interface Y. Indicates an error condition when asserted high.

F2. (Red. The following examples describe the parenthesis further: ■ Dest.F2. back pressuring an output interface or starving an input interface affects all other interfaces. If fields repeat in a packet. The number of symbols per beat defines. and a positive integer follows the group to indicate the number of repeats. DSP Builder can provide the data at the output of each interface as soon as it writes it into the memory and all previous output data is transferred. Therefore. Packet Format Description For each input and output interface. so that (F1. for each interface. For multiple interface PFC blocks.Green.F4 is equivalent to (F1.F4 or F1.F2. _.F2. the number of symbols per beat and the packet description describe the basic format of the packet. the startofpacket signal for all the interfaces is asserted at the same time. and DestinationAddress. Red. followed by a symbol of Blue. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .F4.Blue)100 refers to a frame with 100 repetitions of a symbol of Red. the number of symbols that present in parallel on every active cycle.F2. the output interfaces eventually stop. or 0-9 but must start with a letter. the PFC deasserts the ready signals on its own input interface.(B. ■ ■ Use a + instead of a positive integer. and spools it out in a different order as it leaves. such a group must compose the entire packet. such as (Red.F2. However. (A. At this point. the input interfaces are back pressured.C)+. causing the other outputs to be starved of data.Chapter 5: Interfaces Library Avalon-ST Packet Format Converter 5–15 PFC Data Flow The PFC spools data into a FIFO-like memory as it arrives. Blue.(F2)3. Do not use whitespace in a packet description. the PFC accepts data until it risk overwriting unsent data. A basic packet description is a comma-separated list of field names. For example: Field1.F3)2. if an input interface is starved of data.(Data)128.F2. or((A)+)2. The PFC stops data input on input interfaces by deasserting the ready signal whenever there is a risk of overwriting data that it has not yet output.F2.Blue)+. The packet description is a string that describes the fields in the packet. A-Z. if the upstream block starves the PFC of data by deasserting the valid signals to the PFC. Field names are case sensitive. When an output interface is back pressured. none of the following examples are valid: A.(CRC)4 indicates a packet that has destination and source address symbols followed by 128 data symbols and 4 CRC symbols. Nest repeats.F1. When the PFC has multiple output interfaces.F3)2.F3. where a field name includes any of the characters a-z. Likewise.F2.Green. followed by a symbol of Green. Green. causing the other input interfaces to be back pressured. to repeat a group an unspecified number of times in a packet.Source. It then stops sending data by deasserting the output valid signals. causing the upstream block to stop sending data. then the PFC output interface continues to send data until the memory drains.F3. If a downstream block pauses output data by deasserting the ready signal to the PFC.B)+. parentheses delineate the repeated group (of one or more fields). In a similar way.C.

B/2 refers to an interface where the packet description is R.B.(A)2.G.C)2. Packet Description Examples Packet Description / Symbols Per Beat (R. so that R.D)2 DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . All these examples use the convention <packet description> / <symbols per beat>.G. Table 5–11. Packet Description Syntax Packet Descriptor: Group | (Group)+ where + indicates that the preceding Group is repeated an unknown number of times Group repeatedGroup repeatedGroup | simpleGroup (Group)N where N is a positive integer indicating the number of times the preceding group is repeated simpleGroup FieldName[.B)4/3 Example Packets (Y.C. Table 5–12.Cb)/2 ((A)2.D)3/4 ((((A)2.Y.Group] Table 5–12 shows some example packets.B)2.B.G.5–16 Chapter 5: Interfaces Library Avalon-ST Packet Format Converter Table 5–11 summarizes the packet description syntax for the PFC.G.Cr.B)4 (R.B and the number of symbols per beat is 2.

however. position} pair). compare the field name strings. Multi-Packet Mapping Set the Multi-Packet Mapping option. Each output interface may or may not use a given input field.Green.Red. To achieve packet mapping.Red. For example. It is not valid for any field name to exist on multiple-input interfaces. For example. the source of data for the Red field in a given output interface is the field on an input interface with the name Red. the data for the first Red field is taken from the first Red field in the input packet. Figure 5–11.Blue)3 by using three input packets for every two output packets. Green and Red. For example. If an output interface has Blue. but unless you set the Multi-Packet Mapping option (and if the input field is used) there must be the same number of instances of the field in each output as there is in the input. It is valid. Example of a Packet Format Converter with Two Input and Two Output Interfaces Packet Mapping Packet mapping is the process of determining where the data for each field in each output interface is coming from (as an {input interface. For example.Green. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . (Red.Chapter 5: Interfaces Library Avalon-ST Packet Format Converter 5–17 Figure 5–11 shows an example of the packet formats for a PFC with two input and two output interfaces. no two input interfaces may have a Red field.Red.Blue)2 maps to (Red.Blue represents a packet with two red symbols per packet. Red. It can map multiple input packets to multiple output packets. The PFC matches the nth instance of a field on an input interface to the nth instance of the same field on an output interface. for multiple-output interfaces to have the same field.Green are both valid. A single input or output interface can have multiple instances of the same field. so that the PFC is not limited to mapping a single input packet on each port to a single output packet on each port.Red.Green.Green. but Red. you may copy the Red data to two or more output interfaces.Green is not.

and are not missed. the PFC presents no more data to that output interface. The PFC only has a single output error bit to report frame delineation errors. When all output interfaces stop. but two input packets for Green and Blue. connect the reset port to a pulse generator (such as the Single Pulse block in the DSP Builder Gate & Control library) that is configured to output an initial 0.5–18 Chapter 5: Interfaces Library Avalon-ST Sink The ratio of input fields to output fields must be constant. the PFC also checks that the startofpacket and endofpacket signals assert when they should do. Avalon-ST Sink The Avalon-ST Sink block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-ST sink. For PFC variants where the packet size is known.Green)2 and Blue map to output interface (Red)6. two input interfaces with the formats (Red. Error Handling The PFC contains internal counters that keep track of the current position in the packet for each input and uses these counters to detect frame delineation errors. output interface} pairs. the PFC uses its knowledge of the frame structure to ensure that the assertion is on a valid cycle. It is not possible to guarantee synchronization of output interfaces when frame delineation errors are present. The PFC stops independently on the endofpacket signal for each output. three of the first input's packets and six of the second input's packets are required.Blue(3). DSP Builder supports multiple interfaces but the packet ratio must be constant across all {input interface.Blue does not map to (Red. While errors assert to the output interfaces and the core is reset. and it asserts for each output interface independently until an endofpacket asserts for that output interface. Red. Every time a startofpacket or endofpacket signal asserts on an input interface. the input interfaces are not back pressured. it waits until it sees a startofpacket signal for each input interface before accepting data for that interface. then a 1 for the remainder of the simulation. The output error bit asserts on all outputs as soon as DSP Builder detects an error. When the PFC starts again. and components downstream of the PFC should never see partial frames. the PFC resets and resumes normal operation. The same inputs do not map to (Red)3.Blue)2 because each output packet requires one input packet for Red. The PFC does not support relaying errors from an upstream component to a downstream component. For example. This action prevents loss of any synchronization between input interfaces by uneven back pressuring during error conditions. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .Green(6) because three input packets are required for two output packets for all input and output pairs.Red.Green. 1 DSP Builder does not support packets of unknown length. because to make two output packets.Green(3).Blue(3). After the endofpacket asserts. For example.Green. When simulating the PFC block.

[] >= 0 Specifies the number of bits to the left of the binary point. Data input ready signal. When this option is on. Signed Fractional. Data valid signal that indicates the validity of the input data signals. Table 5–13 lists the signals supported by the Avalon-ST Sink block. This signal is available when Use endofpacket is on and marks the active cycle containing the end of the packet. This parameter applies (Parameterizable) only to signed fractional buses. When this option is on. Indicates that the sink can accept data. The number format of the bus. the empty port is available on the Avalon-ST Sink block. []. Defines the relationship between assertion or deassertion of the Ready signal and cycles the ones ready for data transfer separately for each interface. Table 5–14. Signed Integer. a 32-bit wide bus with 8-bit symbols can have an empty value from 0 to 3. When this option is on and the bit width is greater than the symbol width. Unsigned Integer [number of bits]. Description Turn on to explicitly specify the clock name. the endofpacket port is available on the Avalon-ST Sink block. Signals Supported by the Avalon-ST Sink Block Signal DataIn Valid Ready startofpacket endofpacket empty Direction Input Input Output Input Input Input Data input bus. Description Table 5–14 shows the Avalon-ST Sink block parameters. refer to the Avalon Interface Specifications. Table 5–13.[number of bits] >= 0 Specifies the number of bits to the right of the binary point.Chapter 5: Interfaces Library Avalon-ST Sink 5–19 f For information about the Avalon-ST interface. This signal is available when Use empty is turned on and the bit width is greater than the symbol width. Symbol Width Use endofpacket Use startofpacket Use empty Ready Latency >= 1 On or Off On or Off On or Off 0 or 1 Specifies the symbol width in bits. the startofpacket port is available on the Avalon-ST Sink block. This signal is available when Use startofpacket is on and marks the active cycle containing the start of the packet. It specifies how many of the symbols in a packet are empty. (Parameterizable) Read and write buses must have the same number of bits. Avalon-ST Sink Block Parameters Name Specify Clock Clock Data Type Value On or Off User defined Specifies the clock signal name. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . including the sign bit. For example.

Avalon-ST Sink Block with All Signals Enabled Avalon-ST Source The Avalon-ST Source block defines a collection of ports for connection to an SOPC Builder system when your design functions as an Avalon-ST source. Data output ready signal. Figure 5–12. For example. Description Table 5–16 on page 5–21 shows the Avalon-ST Source block parameters. refer to the Avalon Interface Specifications. Data valid signal that indicates the validity of the output data signals.5–20 Chapter 5: Interfaces Library Avalon-ST Source Figure 5–12 shows an Avalon-ST Sink block with all signals enabled. This signal is available when the Use startofpacket parameter is on and marks the active cycle containing the start of the packet. Table 5–15 lists the signals supported by the Avalon-ST Source block. It specifies how many of the symbols in a packet are empty. Signals Supported by the Avalon-ST Source Block Signal DataOut Valid Ready startofpacket endofpacket empty Direction Output Output Input Output Output Output Data input bus. Indicates that the source can accept data. Table 5–15. This signal is available when the Use endofpacket parameter is on and marks the active cycle containing the end of the packet. This signal is available when Use empty is turned on and the bit width is greater than the symbol width. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . a 32-bit wide bus with 8-bit symbols can have an empty value from 0 to 3. f For information about the Avalon-ST interface.

Unsigned Integer [number of bits]. When this option is on. []. (Parameterizable) Read and write buses must have the same number of bits. Figure 5–13. Description Turn on to explicitly specify the clock name. Avalon-ST Source Block with All Signals Enabled © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . When this option is on. When this option is on and the bit width is greater than the symbol width. the empty port is available on the Avalon-ST Sink block. Signed Fractional. the endofpacket port is available on the Avalon-ST Source block. including the sign bit. The number format of the bus. Symbol Width Use endofpacket Use startofpacket Use empty Ready Latency 1–512 On or Off On or Off On or Off 0 or 1 Specifies the symbol width in bits. Defines the relationship between assertion/deassertion of the Ready signal and cycles the ones ready for data transfer separately for each interface.Chapter 5: Interfaces Library Avalon-ST Source 5–21 Table 5–16. Figure 5–13 shows an Avalon-ST Source block with all signals enabled.[number of bits] >= 0 Specifies the number of bits to the right of the binary point. This parameter applies (Parameterizable) only to signed fractional buses. Avalon-ST Source Block Parameters Name Specify Clock Clock Data Type Value On or Off User defined Specifies the clock signal name. the startofpacket port is available on the Avalon-ST Source block. Signed Integer.[] >= 0 Specifies the number of bits to the left of the binary point.

5–22 Chapter 5: Interfaces Library Avalon-ST Source DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

IO & Bus Library The blocks in the IO & Bus library manipulate signals and buses to perform operations such as truncation. The IO & Bus library contains the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ AltBus Binary Point Casting Bus Builder Bus Concatenation Bus Conversion Bus Splitter Constant Extract Bit Global Reset GND Input Non-synthesizable Input Non-synthesizable Output Output Round Saturate VCC © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . bit extraction.6. saturation. or bus format conversion.

if the output is greater than the maximum positive or negative value to be represented. use a Bus Conversion block to set the width. When off. R = 0. more bits are needed to represent the integer part of the number.6–2 Chapter 6: IO & Bus Library AltBus AltBus The AltBus block modifies the bus format of a DSP Builder signal. Table 6–3. When this option is on. you can specify to either truncate or saturate the excess bits.3333) is cast into signed binary fractional format with three different binary point locations. Floating-Point Numbers Cast to Signed Binary Fractional Bus Notation [4]. Single Bit The number format of the bus. the MSB is the sign bit.[4] Note to Table 6–3: (1) In this case. Table 6–1. the output is forced (or saturated) to the maximum positive or negative value. For single bits. the MSB is truncated. not as an input to or output from the system. Unsigned Integer. This parameter does not apply to single-bit buses. This parameter applies only to signed fractional buses. respectively.1} DOWNTO 0) Type (4) Implicit .[0]. Only use this block as an internal node in a system.[RP] VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . AltBus Block Parameters Name Bus Type Value Signed Integer.[1] [2]. To specify the bus format of an implicit input port.[] >= 0 (Parameterizable) []. If it is smaller than the input bit width. Table 6–3 and Figure 6–1 on page 6–3 illustrate how a floating-point number (4/3 = 1.[R1] O1[LP].00 1. Signed Fractional.[R] is an output port. (4) Explicit means that the port bit width information is a block parameter. (2) [L] is the number of bits on the left side of the binary point. AltBus Block I/O Formats (Note 1) I/O I O Simulink (2). (3) I1[L1].Optional Explicit Notes to Table 6–2: (1) For signed integers and signed binary fractional numbers.6875 (1) VHDL 2 10 -11 DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . [1] is a single bit. For signed or unsigned integers R = 0. Table 6–2 shows the AltBus block I/O formats.25 -0. that is. [R] is the number of bits on the right side of the binary point. the bus is sign extended to fit. that is. Table 6–1 shows the AltBus block parameters.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP . Input 4/3 4/3 4/3 Simulink 1. Table 6–2.[3] [1]. If the specified bit width is wider than the input bit width. Description [number of bits]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. O1[L].[number of bits] >= 0 (Parameterizable) Saturate Output On or Off Specifies the number of bits to the left of the binary point.[R] is an input port. Specifies the number of bits to the right of the binary point. (3) I1[L]. including the sign bit. [L].

this results in extracting a 4-bit bus (AltBus(3 DOWNTO 0)) from a 20-bit bus (AltBus(19 DOWNTO 0)) with the assignment: AltBus3(3 DOWNTO 0)) AltBus(11 DOWNTO 8)) Figure 6–2. Internal Format Conversion © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .[2] signed binary fractional format.Chapter 6: IO & Bus Library AltBus 6–3 Figure 6–1. Floating-Point Conversion Figure 6–2 illustrates the usage of AltBus to convert a 20-bit bus with a ([10].[10]) signed binary fractional format to a 4-bit bus with a [2]. In VHDL.

6–4 Chapter 6: IO & Bus Library Binary Point Casting Figure 6–3 shows AltBus blocks for sign extension. Figure 6–3. Table 6–5. Table 6–4 shows the Binary Point Casting block parameters. Table 6–4. including the sign bit.1} DOWNTO 0) Type (4) Explicit DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . (Parameterizable) []. Sign Extension 1 You can also perform additional internal bus manipulation with the Altera Bus Conversion. Binary Point Casting The Binary Point Casting block changes the binary point position for a signed fractional bus type. or Bus Builder blocks. Extract Bit.[number of bits] >= 0 Specifies the number of bits to the right of the binary point. The output bit width remains equal to the input bit width. (Parameterizable) Table 6–5 shows the Binary Point Casting block I/O formats. Signed Fractional. Binary Point Casting Block Parameters Name Bus Type Value Signed Integer. (3) I1[Li].[Ri] VHDL I1: in STD_LOGIC_VECTOR({Li + Ri . This parameter (Parameterizable) applies only to signed fractional buses. Binary Point Casting Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2). or converts an integer to a fractional bus type. Output Binary Point Position >= 0 Specifies the binary point location of the output. Unsigned Integer Description [number of bits].[] >= 0 Specifies the number of bits to the left of the binary point. The number format of the bus.

The input MSB is at the bottom left of the symbol and the input LSB displays at the top left of the symbol. Figure 6–4. [1] is a single bit. [R] is the number of bits on the right side of the binary point. (4) Explicit means that the port bit width information is a block parameter. For signed or unsigned integers R = 0. use a Bus Conversion block to set the width.1} DOWNTO 0) Type (4) Explicit Notes to Table 6–5: (1) For signed integers and signed binary fractional numbers. O1[L]. (3) I1[L].[0]. that is. including the sign bit. R = 0. Instead use a an AltBus block (Figure 6–3 on page 6–4). The output bus is signed integer. Unsigned Integer The number format of the bus. Binary Point Casting Block Example Bus Builder The Bus Builder block constructs an output bus from single-bit inputs.[RO] VHDL O1: out STD_LOGIC_VECTOR({LO + RO . Bus Builder Block Parameters (Part 1 of 2) Name Bus Type Value Signed Integer. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . or signed binary fractional format. Table 6–6 shows the Bus Builder block parameters. Description [number of bits]. Figure 6–4 shows a design example with the Binary Point Casting block. 1 The Bus Builder block does not support sign extension.[] >= 0 (Parameterizable) Specifies the number of bits to the left of the binary point.Chapter 6: IO & Bus Library Bus Builder 6–5 Table 6–5. Table 6–6. To specify the bus format of an implicit input port. Binary Point Casting Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2).[R] is an output port. Signed Fractional. For single bits. [L]. The HDL mapping of the Bus Builder block is a simple wire. You can specify the number of bits in each case. the MSB is the sign bit. unsigned integer. (2) [L] is the number of bits on the left side of the binary point.[R] is an input port. that is. (3) O1[LO].

6–6 Chapter 6: IO & Bus Library Bus Builder Table 6–6. [R] is the number of bits on the right side of the binary point. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. This parameter applies only to signed binary fractional buses. (3) I1: in STD_LOGIC … Ii: in STD_LOGIC …...[RP] with LP + RP = n where n is the number of inputs Notes to Table 6–7: (1) For signed integers and signed binary fractional numbers. R = 0. Bus Builder Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Bus Builder Block Parameters (Part 2 of 2) Name Value Description Specifies the number of bits to the right of the binary point. []. (3) I1[L]. In[1] O O1[LP]. that is. (2) [L] is the number of bits on the left side of the binary point.[0]. [L]. [1] is a single bit. Table 6–7. To specify the bus format of an implicit input port. For single bits.[R] is an input port. (4) Explicit means that the port bit width information is a block parameter. Figure 6–5. For signed or unsigned integers R = 0. Explicit Explicit Simulink (2). that is. O1[L]..[number of bits] >= 0 (Parameterizable) Table 6–7 shows the Bus Builder block I/O formats. use a Bus Conversion block to set the width..1} DOWNTO 0) Figure 6–5 shows a design example with the Bus Builder block. (Note 1) VHDL Type (4) Explicit . Explicit . In: in STD_LOGIC O1: out STD_LOGIC_VECTOR({LP + RP . Bus Builder Block I/O Formats I/O I I1[1] … Ii[1] …. the MSB is the sign bit.[R] is an output port.

Bus Concatenation Block Parameters Name Output Is Signed Width of Input a Width of Input b Value On or Off >= 1 (Parameterizable) >= 1 (Parameterizable) Description Turn on if the output bus is signed. Table 6–9. Table 6–8. input b becomes the LSB part.Chapter 6: IO & Bus Library Bus Concatenation 6–7 Bus Concatenation The Bus Concatenation block concatenates two buses. (4) Explicit means that the port bit width information is a block parameter. Bus Concatenation Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . The block has two inputs. (3) I1[N] is an input port.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({N1 + N2 . The output width is width(a) + width(b). Specifies the width of the second bus to concatenate. Table 6–9 shows the Bus Concatenation block I/O formats. Bus Concatenation Block I/O Formats I/O I O Simulink (2). a and b. (2) [N] is the number of bits. These may be signed integer or unsigned integer. O1[N] is an output port. Input a becomes the MSB part of the output. Specifies the width of the first bus to concatenate. (Note 1) VHDL Type (4) Explicit Explicit I1: in STD_LOGIC_VECTOR({N1 . Table 6–8 shows the Bus Concatenation block parameters.1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({N2 . (3) I1[N1] I2[N2] O1[N1 + N2] Notes to Table 6–9: (1) For signed integers.1} DOWNTO 0) Figure 6–6 shows an example with the Bus Concatenation block. the MSB is the sign bit. Figure 6–6.

Unsigned Integer >= 0 Specifies the number of bits to the left of the binary point including the (Parameterizable) sign bit. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. The input bus type for the simulator. If the input is in signed binary fractional format. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LPO + LPO . (3) I1[L]. [1] is a single bit.6–8 Chapter 6: IO & Bus Library Bus Conversion Bus Conversion The Bus Conversion block extracts a subsection of a bus including bus type and width conversion. Do not use this option with signed fractional type or with rounding. This (Parameterizable) parameter applies only to signed binary fractional buses. Table 6–10. If the input is an integer. if the output is greater than the maximum positive or negative value to be represented.[] >= 0 Specifies the number of bits to the left of the binary point.[R] is an output port. For single bits. >= 0 Specifies the number of bits to the right of the binary point. When this option is off. the output is forced (or saturated) to the maximum positive or negative value. specify the input bit to connect to the output LSB. [R] is the number of bits on the right side of the binary point.[number of bits] >= 0 Specifies the number of bit on the right side of the binary point. (3) I1[LPi].[] Input []. R = 0. Table 6–11. For signed or unsigned integers R = 0. that is. On or Off On or Off Turn on to round the output away from zero. (2) [L] is the number of bits on the left side of the binary point. Table 6–11 shows the Bus Conversion block I/O formats.[RPO] VHDL I1: in STD_LOGIC_VECTOR({LPi + RPi . the MSB is the sign bit. To specify the bus format of an implicit input port. When this option is on. Input Bit Connected to Output LSB Round Saturate >= 0 Specifies the slice of the input bus to use. Input [number of bits]. [L]. the LSM is truncated: <int>(input +0. use a Bus Conversion block to set the width. VHDL or both. (Parameterizable) Output []. Table 6–10 shows the Bus Conversion block parameters. Bus Conversion Block Parameters Name Bus Type Value Description Signed Integer.[number of bits] Output [number of bits]. that is. 1 If Input Bit Connected To Output LSB is on. This parameter designates the (Parameterizable) start point of the slice that is transferred to the output LSB and applies to signed or unsigned integer buses only. Bus Conversion Block I/O Formats (Note 1) I/O I O Simulink (2). This parameter (Parameterizable) applies only to signed binary fractional buses. O1[L].1} DOWNTO 0) Type (4) Explicit Explicit Notes to Table 6–11: (1) For signed integers and signed binary fractional numbers. you should specify a left bit width (number of integer bits) and a right bit width (number of fractional bits) for the output bus.5).[R] is an input port.[0]. the MSB is truncated.[RPi] O1[LPO]. respectively. the input bit indexing starts from 0. Signed Fractional. If off.

(3) I1[LP]. Table 6–12 shows the Bus Splitter block parameters. Signed Fractional. Bus Splitter Block I/O Formats (Part 1 of 2) (Note 1) I/O I Simulink (2).Chapter 6: IO & Bus Library Bus Splitter 6–9 Figure 6–7 shows a design example with the Bus Conversion block. Figure 6–7.[RP] with LP + RP = n where n is the number of inputs VHDL I1: in STD_LOGIC_VECTOR({LP + RP . Table 6–13 shows the Bus Splitter block I/O formats. Unsigned Integer The number format of the bus. Specifies the number of bits to the right of the binary point. Description [number of bits].1} DOWNTO 0) Type (4) Explicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Table 6–12. Bus Splitter Block Parameters Name Bus Type Value Signed Integer. You can specify the bus type that you want to use. This parameter applies only to signed binary fractional buses. including the sign bit. Bus Conversion Block Example Bus Splitter The Bus Splitter block splits a bus into single-bit outputs.[number of bits] >= 0 (Parameterizable) Specifies the number of bits to the left of the binary point.[] >= 0 (Parameterizable) []. Table 6–13. The output ports are numbered from LSB to MSB. and specify the number of bits on either side of the binary point.

. Specifies the number of bits to the right of the binary point. [L]. The number format of the bus. For signed or unsigned integers R = 0. [R] is the number of bits on the right side of the binary point. Bus Splitter Block I/O Formats (Part 2 of 2) (Note 1) I/O O O1[1] … On[1] Notes to Table 6–7: (1) For signed integers and signed binary fractional numbers. including the sign bit. [1] is a single bit. use a Bus Conversion block to set the width. Bus Splitter Block Example Constant The Constant block specifies a constant bus. Constant Block Parameters (Part 1 of 2) Name Constant Value Bus Type Value Double (Parameterizable) Signed Integer. (2) [L] is the number of bits on the left side of the binary point. This parameter does not apply to single-bit buses. Single Bit Description Specifies the constant value that is formatted with the specified bus type. that is.[R] is an input port.. Signed Fractional. Figure 6–8. the MSB is the sign bit.[] >= 0 (Parameterizable) []. Table 6–14 shows the Constant block parameters. (3) I1[L].6–10 Chapter 6: IO & Bus Library Constant Table 6–13. Table 6–14. that is. For single bits. [number of bits]. Explicit Figure 6–8 shows a design example with the Bus Splitter block. O1[L]. R = 0.[number of bits] >= 0 (Parameterizable) Specifies the number of bits to the left of the binary point. Unsigned Integer. Simulink (2). This parameter applies only to signed fractional buses. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . The options available depend on the selected bus type.[0]. (4) Explicit means that the port bit width information is a block parameter. To specify the bus format of an implicit input port. (3) O1: in STD_LOGIC … On: in STD_LOGIC VHDL Type (4) Explicit . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.[R] is an output port.

the MSB is the sign bit.[R] is an output port. Constant Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . O1[L]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. information about the rounding modes. The rounding mode. Figure 6–9 shows an example with the Constant block.Chapter 6: IO & Bus Library Constant 6–11 Table 6–14. Saturation Mode Specify Clock Clock Table 6–15 shows the Constant block I/O formats. R = 0. To specify the bus format of an implicit input port. Refer to the description of the Round block for more Round Towards Zero. Constant Block Parameters (Part 2 of 2) Name Rounding Mode Value Description Truncate. Turn on to explicitly specify the clock name. (3) O1[LP]. (4) Explicit means that the port bit width information is a block parameter. For signed or unsigned integers R = 0. [1] is a single bit.1} DOWNTO 0) Type (4) Explicit Notes to Table 6–15: (1) For signed integers and signed binary fractional numbers. Specifies the name of the required clock signal. use a Bus Conversion block to set the width. Table 6–15. Constant Block I/O Formats I/O O Simulink (2). Convergent Rounding Wrap. [R] is the number of bits on the right side of the binary point.[R] is an input port. that is. Round Away From Zero. Round To Plus Infinity. For single bits. Saturate On or Off User defined (Parameterizable) The saturation mode.[RP] (Note 1) VHDL O1: out STD_LOGIC_VECTOR({LP + RP .[0]. Figure 6–9. that is. (2) [L] is the number of bits on the left side of the binary point. (3) I1[L]. [L].

Signed Fractional. The selected bit is indexed starting from zero for the LSB and increasing to (total bit width .6–12 Chapter 6: IO & Bus Library Extract Bit Extract Bit The Extract Bit block reads a Simulink bus in the specified format and outputs the single bit specified. that is. For signed or unsigned integers R = 0. For single bits. Unsigned Integer Description Specifies the number format of the bus. Table 6–16 shows the Extract Bit block parameters. [1] is a single bit. (2) [L] is the number of bits on the left side of the binary point.[R] is an output port. Table 6–17. (3) I1[L1]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.[0]. Extract Bit Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . R = 0. Select the Bit to be >= 0 (Parameterizable) Specifies the input bit to extract. (4) Explicit means that the port bit width information is a block parameter. [number of bits]. Figure 6–10. Table 6–16. the MSB is the sign bit. (3) I1[L]. Extracted From the Bus Table 6–17 shows the Extract Bit block I/O formats. that is.1} DOWNTO 0) Type (4) Explicit Explicit Notes to Table 6–17: (1) For signed integers and signed binary fractional numbers. [R] is the number of bits on the right side of the binary point. O1[L]. Extract Bit Block I/O Formats I/O I O Simulink (2). including the sign bit. use a Bus Conversion block to set the width.[number of bits] >= 0 (Parameterizable) Specifies the number of bits to the left of the binary point.[R] is an input port.[] [].[R1] O1[1] O1: out STD_LOGIC (Note 1) VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . [L]. Extract Bit Block Parameters Name Bus Type Value Signed Integer. >= 0 (Parameterizable) Specifies the number of bits to the right of the binary point. Figure 6–10 shows a design example with the Extract Bit block.1) for the MSB. To specify the bus format of an implicit input port.

[R] is an input port. Table 6–20 shows the GND block parameters. Table 6–18 shows the Global Reset block parameters. GND Block I/O Formats I/O O Simulink (2).[R] is an output port. the MSB is the sign bit. In simulation. [1] is a single bit. that is. GND The GND block is a single bit that outputs a constant 0.[R] is an output port. To specify the bus format of an implicit input port. this block outputs a constant 0. that is. use a Bus Conversion block to set the width. that is. R = 0. Global Reset Block Parameters Name Specify Clock Clock On or Off User defined (Parameterizable) Value Description Turn on to explicitly specify the clock name. use a Bus Conversion block to set the width. [R] is the number of bits on the right side of the binary point. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. O1[L]. For signed or unsigned integers R = 0. (3) O1[1]. For signed or unsigned integers R = 0.[0]. To specify the bus format of an implicit input port. GND Block Parameters Name Specify Clock Clock On or Off User defined (Parameterizable) Value Description Turn on to explicitly specify the clock name. (4) Explicit means that the port bit width information is a block parameter. For single bits. Table 6–20. Specifies the name of the required clock signal. R = 0. Specifies the name of the required clock signal. (2) [L] is the number of bits on the left side of the binary point.[0].[R] is an input port. Figure 6–11 shows a design example with the GND block. Table 6–19. All signals driven by the block are connected to the global reset for that clock domain. that is. Table 6–21.[0] O1: out STD_LOGIC (Note 1) VHDL Type (4) Explicit Notes to Table 6–19: (1) For signed integers and signed binary fractional numbers. (3) O1[1]. [1] is a single bit. [L]. (4) Explicit means that the port bit width information is a block parameter.[0] O1: out STD_LOGIC (Note 1) VHDL Type (4) Explicit Notes to Table 6–21: (1) For signed integers and signed binary fractional numbers. [R] is the number of bits on the right side of the binary point. Table 6–18. [L]. Table 6–19 shows the Global Reset block I/O formats. the MSB is the sign bit. For single bits. (3) I1[L]. Table 6–21 shows the GND block I/O formats. O1[L]. (2) [L] is the number of bits on the left side of the binary point. Global Reset Block I/O Formats I/O O Simulink (2).Chapter 6: IO & Bus Library Global Reset 6–13 Global Reset The Global Reset (or SCLR) block provides a single bit reset signal. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . (3) I1[L]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.

6–14 Chapter 6: IO & Bus Library Input Figure 6–11.[] >= 0 (Parameterizable) []. Table 6–23 on page 6–15 shows the Input block I/O formats.[number of bits] >= 0 (Parameterizable) Specify Clock Clock On or Off User defined (Parameterizable) Specifies the number of bits to the left of the binary point. Specifies the number of bits to the right of the binary point. GND Block Example Input The Input block defines the input boundary of a hardware system and casts floating-point Simulink signals (from generic Simulink blocks) to signed binary fractional format (feeding DSP Builder blocks). Single Bit Description Specifies the number format of the bus. This parameter does not apply to single-bit buses. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Unsigned Integer. Input Block Parameters Name Bus Type Value Signed Integer. Signed Fractional. Specifies the name of the required clock signal. [number of bits]. This parameter applies only to signed fractional buses. including the sign bit. Table 6–22. Table 6–22 shows the Input block parameters. Turn on to explicitly specify the clock name.

(4) Explicit means that the port bit width information is a block parameter.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP . (2) [L] is the number of bits on the left side of the binary point. (3) I1[L1]. This parameter applies only to signed fractional buses.Optional Explicit Notes to Table 6–23: (1) For signed integers and signed binary fractional numbers.[R1] O1[LP]. [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0. Non-synthesizable Input Block Parameters Name Bus Type Value Signed Integer. [L].1} DOWNTO 0) Type (4) Implicit . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. (3) I1[L1].[R] is an input port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Turn on to explicitly specify the clock name. this block is required when the DSP Builder blocks are not intended to be synthesized. For single bits.[0]. [1] is a single bit. Table 6–25 shows the Non-synthesizable Input block I/O formats. Specifies the name of the required clock signal.[0].1} DOWNTO 0) Notes to Table 6–23: (1) For signed integers and signed binary fractional numbers.Chapter 6: IO & Bus Library Non-synthesizable Input 6–15 Table 6–23. that is. that is.[R] is an input port. To specify the bus format of an implicit input port. Input Block I/O Formats I/O I O Simulink (2). [R] is the number of bits on the right side of the binary point. (3) I1[L]. the MSB is the sign bit. O1[L]. Table 6–24 shows the Non-synthesizable Input block parameters. Table 6–25.[R1] O1[LP].[R] is an output port. O1[L]. Because DSP Builder registers its own type with Simulink. that is. [1] is a single bit. Non-synthesizable Input Block I/O Formats I/O I O Simulink (2). Signed Fractional.[RP] (Note 1) VHDL I1: out STD_LOGIC_VECTOR({L1 + R1 . including the sign bit. To specify the bus format of an implicit input port. (3) I1[L]. (2) [L] is the number of bits on the left side of the binary point. R = 0. use a Bus Conversion block to set the width.[RP] (Note 1) VHDL Type (4) Implicit . that is.Optional Explicit I1: out STD_LOGIC_VECTOR({L1 + R1 . [number of bits]. Table 6–24.[] >= 0 (Parameterizable) []. Unsigned Integer.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP .[R] is an output port. Single Bit Description Specifies the number format of the bus. (4) Explicit means that the port bit width information is a block parameter. For single bits. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Specifies the number of bits to the right of the binary point. Non-synthesizable Input The Non-synthesizable Input block marks an entry point to a non-synthesizable DSP Builder system.[number of bits] >= 0 (Parameterizable) Specify Clock Clock On or Off User defined (Parameterizable) Specifies the number of bits to the left of the binary point. R = 0. the MSB is the sign bit. [L]. This parameter does not apply to single-bit buses. Use a corresponding Non-synthesizable Output block to mark the exit point. For signed or unsigned integers R = 0. use a Bus Conversion block to set the width.

1} DOWNTO 0) Type (4) Implicit .[0]. (3) I1[L]. You can also use this block to create an non-synthesizable output from a synthesizable system. Non-synthesizable Output Block I/O Formats I/O I O Simulink (2). Table 6–27 shows the Non-synthesizable Output block I/O formats. If set to Double. Signed Fractional. If set to Simulink Fixed Point Type. The default is Inferred. is connected to or explicitly set to either Simulink Fixed Point or Double Double type. Inferred. [1] is a single bit. [R] is the number of bits on the right side of the binary point.6–16 Chapter 6: IO & Bus Library Non-synthesizable Output Non-synthesizable Output The Non-synthesizable Output block marks an exit point from a non-synthesizable DSP Builder system. (3) I1[L1].Optional Explicit Notes to Table 6–29: (1) For signed integers and signed binary fractional numbers.[R] is an input port. [number of bits].[RP] (Note 1) VHDL I1: out STD_LOGIC_VECTOR({L1 + R1 . This parameter does not apply to single-bit buses. use a Bus Conversion block to set the width. including the sign bit. Signed Integer. You can optionally specify the external Simulink type. [L]. Table 6–26. This parameter applies only to signed fractional buses. the MSB is the sign bit. (4) Explicit means that the port bit width information is a block parameter. For signed or unsigned integers R = 0. For single bits. that is.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP . Table 6–26 shows the Non-synthesizable Output block parameters. that is. To specify the bus format of an implicit input port. R = 0.[] >= 0 (Parameterizable) []. the width may be truncated if the bit width is greater than 52.[number of bits] >= 0 (Parameterizable) External Type Specifies the number of bits to the left of the binary point. Because DSP Builder registers its own type with Simulink. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . O1[L]. Table 6–27.[R] is an output port. Use a corresponding Non-synthesizable Input block to mark the entry point. the bit width is the same as the DSP Builder input type. Unsigned Integer. this block is required when the DSP Builder blocks are not intended to be synthesized. (2) [L] is the number of bits on the left side of the binary point. Specifies the number of bits to the right of the binary point. Non-synthesizable Output Block Parameters Name Bus Type Value Inferred. Specifies whether the external type is inferred from the Simulink block it Simulink Fixed Point Type. Single Bit Description Specifies the number format of the bus.[R1] O1[LP].

Unsigned Integer. that is. You normally connect these blocks to Simulink simulation blocks in your testbench.Chapter 6: IO & Bus Library Output 6–17 Output The Output block defines the output boundary of a hardware system and casts signed binary fractional format (from DSP Builder blocks) to floating-point Simulink signals (feeding generic Simulink blocks).[] >= 0 (Parameterizable) []. The default is Inferred. (3) I1[L]. Output Block Parameters Name Bus Type Value Inferred. (2) [L] is the number of bits on the left side of the binary point. Specifies whether the external type is inferred from the Simulink block it Simulink Fixed Point Type.[R1] O1[LP].[RP] (Note 1) VHDL I1: out STD_LOGIC_VECTOR({L1 + R1 . If set to Simulink Fixed Point Type. Table 6–28 shows the Output block parameters. Their outputs should not be connected to other Altera blocks. (4) Explicit means that the port bit width information is a block parameter.[R] is an output port. Signed Fractional. the bit width is the same as the input. [L]. Table 6–28. Table 6–29. R = 0. This parameter does not apply to single-bit buses.[0]. Description [number of bits]. is connected to or explicitly set to either Simulink Fixed Point or Double Double type. (3) I1[L1]. Specifies the number of bits to the right of the binary point. You can optionally specify the external Simulink type.[number of bits] >= 0 (Parameterizable) External Type Specifies the number of bits to the left of the binary point. To specify the bus format of an implicit input port.[R] is an input port. Single Bit The number format of the bus.1} DOWNTO 0) Type (4) Implicit . the MSB is the sign bit. that is. This parameter applies only to signed fractional buses. Output blocks map to output ports in VHDL and mark the edge of the generated system. For signed or unsigned integers R = 0.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP . [1] is a single bit. Output Block I/O Formats I/O I O Simulink (2). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . If set to Double. O1[L]. including the sign bit.Optional Explicit Notes to Table 6–29: (1) For signed integers and signed binary fractional numbers. [R] is the number of bits on the right side of the binary point. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. the width may be truncated if the bit width is greater than 52. Table 6–29 shows the Output block I/O formats. Signed Integer. use a Bus Conversion block to set the width. Inferred. For single bits.

it is best to use saturation logic to prevent this from happening. 0. Convergent Rounding: Specify the even value. Floor (equivalent to Truncate). Table 6–30 shows the Round block parameters.1 rounds to 0 but the MATLAB Ceiling mode rounds 0. specify the lower value. upwards for positive values). Ceiling.1 to 1. Unsigned Integer >= 2 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) The number format of the bus.6–18 Chapter 6: IO & Bus Library Round Round The Round block rounds the input to the closest possible representation in the specified output bus format. ■ ■ ■ ■ 1 When using Simulink fixed-point types. Round Block Parameters (Part 1 of 2) Name Bus Type Value Signed Integer.9 rounds to 1 (for all modes except Truncate) but the MATLAB Zero mode rounds 0.[] []. The MATLAB Zero and Ceiling modes round all intermediate values up or down and have no DSP Builder equivalent. Round Towards Zero: Specify the value closer to zero. Description [number of bits]. when rounding from an 8-bit signed input to a 6-bit signed output. Specifies how many bits to remove. Nearest (equivalent to Round Away From Zero). Signed Fractional.0 and before. Round To Plus Infinity: Specify the higher value. This is the simplest and fastest mode to implement in hardware.[number of bits] Number of LSB Bits to Remove Specifies the number of bits to the left of the binary point. effectively. This was the rounding behavior in DSP Builder version 7. This parameter applies only to signed fractional buses. If the nearest two possibilities are equidistant. For example. 01111111 (127) becomes 100000 (-32). including the sign bit.9 to 0. This is because the DSP Builder modes (except Truncate) always specify the nearest representable value and the rounding mode applies only to values that are equidistant from two representable values. Specifies the number of bits to the right of the binary point. For example. This parameter does not apply to single-bit buses. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . and Simplest. you can specify from the available rounding modes: ■ Truncate: Remove discarded bits without changing the other bits. Similarly 0. If you use this mode. For a large sample of random input values there is no bias —on average the same number of values round upwards as downwards. Table 6–30. Round Away From Zero: Specify the value further from zero (round downwards for negative values. MATLAB supports the following rounding options: Zero. When using this mode —the maximum positive value overflows the available representation.

Turn on to use the asynchronous clear input (aclr). Round Away From Zero.[R] is an output port. Round To Plus Infinity. Round Block Parameters (Part 2 of 2) Name Rounding Mode Value Truncate. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.[R] is an input port. For signed or unsigned integers R = 0. (3) I1[L1]. (Note 1) VHDL Type (4) Explicit Simulink (2).Chapter 6: IO & Bus Library Round 6–19 Table 6–30. that is. (4) Explicit means that the port bit width information is a block parameter. Figure 6–12. Description Enable Pipeline Use Asynchronous Clear Port (1) Note to Table 6–30: Turn on if you want to pipeline the function. (3) I1[L].1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP . R = 0. Round Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . For single bits. To specify the bus format of an implicit input port. Turn on to use the clock enable input (ena). [L]. that is. Round Block I/O Formats I/O I I2[1] I3[1] O O1[LP]. [1] is a single bit. O1[L]. use a Bus Conversion block to set the width. Table 6–31. Use Enable Port (1) On or Off (1) These ports are available only when you enable pipeline.[R1] I2: in STD_LOGIC I3: in STD_LOGIC I1: out STD_LOGIC_VECTOR({L1 + R1 . the MSB is the sign bit. Round Towards Zero. [R] is the number of bits on the right side of the binary point.1} DOWNTO 0) Explicit Figure 6–12 shows a design example with the Round block.[0].[RP] Notes to Table 6–31: (1) For signed integers and signed binary fractional numbers. Table 6–31 shows the Round block I/O formats. (2) [L] is the number of bits on the left side of the binary point. Convergent Rounding On or Off On or Off The rounding mode.

[] []. including the sign bit. or specify the saturation limits for the output. respectively. Unsigned Integer >= 2 (Parameterizable) >= 0 (Parameterizable) >= 0 (Parameterizable) Saturate. Lower Saturation Limit Integer (Parameterizable) Enable Pipeline Use Saturation Occurred Port Use Enable Port (1) Use Asynchronous Clear Port (1) Note to Table 6–30: On or Off On or Off On or Off On or Off (1) These ports are available only when you enable pipeline. Table 6–32 shows the Saturate block parameters. Upper Saturation Limit Specifies the upper saturation limit when Saturation Type is set to Enter Saturation Limits. Turn on if you want to pipeline the function. [number of bits]. Saturate Block Parameters Name Input Bus Type Value Signed Integer. you can truncate the MSB.[number of bits] Number of MSB Bits to Remove Saturation Type Specifies the number of bits to the left of the binary point. Alternatively. Enter Saturation Limits Integer (Parameterizable) Description The number format of the bus. Table 6–32. truncate. Turn on to use the clock enable input (ena).6–20 Chapter 6: IO & Bus Library Saturate Saturate The Saturate block limits output to a maximum value. Truncate MSB. Specifies the number of bits to the right of the binary point. Specifies the lower saturation limit when Saturation Type is set to Enter Saturation Limits. Specifies how many bits to remove. Turn on to use the asynchronous clear input (aclr). This parameter does not apply to single-bit buses. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Signed Fractional. Turn on to use the saturation occurred input (sat_flag). the output is forced (or saturated) to the maximum positive or negative value. Saturate. If the output is greater than the maximum positive or negative value to be represented. This parameter applies only to signed fractional buses.

Figure 6–13. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LP + RP . Table 6–34. that is. R = 0. [R] is the number of bits on the right side of the binary point. Saturate Block I/O Formats I/O I I2[1] I3[1] I4[1] O O1[LP]. (3) I1[L]. O1[L]. (4) Explicit means that the port bit width information is a block parameter. VCC Block Parameters Name Specify Clock Clock Value On or Off User defined (Parameterizable) Description Turn on to explicitly specify the clock name. (2) [L] is the number of bits on the left side of the binary point.[R] is an input port. the MSB is the sign bit.[R] is an output port. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . that is. Specifies the name of the required clock signal.1} DOWNTO 0) Explicit Figure 6–13 shows a design example with the Saturate block.[RP] Notes to Table 6–33: (1) For signed integers and signed binary fractional numbers. use a Bus Conversion block to set the width.Chapter 6: IO & Bus Library VCC 6–21 Table 6–33 shows the Saturate block I/O formats. For single bits. [L]. [1] is a single bit.[R1] I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC I1: out STD_LOGIC_VECTOR({L1 + R1 . (3) I1[L1]. Saturate Block Example VCC The VCC block outputs a single-bit constant 1. To specify the bus format of an implicit input port. For signed or unsigned integers R = 0. Table 6–34 shows the VCC block parameters. Table 6–33. (Note 1) VHDL Type (4) Explicit Simulink (2).[0].

[R] is an input port. For signed or unsigned integers R = 0. (3) O1[1] O1: out STD_LOGIC (Note 1) VHDL Type (4) Explicit Notes to Table 6–35: (1) For signed integers and signed binary fractional numbers. Figure 6–14. O1[L]. [L]. (4) Explicit means that the port bit width information is a block parameter. (3) I1[L]. use a Bus Conversion block to set the width.[0]. [R] is the number of bits on the right side of the binary point. that is. (2) [L] is the number of bits on the left side of the binary point. To specify the bus format of an implicit input port. Table 6–35. For single bits. Figure 6–14 shows a design example with the VCC block. [1] is a single bit.6–22 Chapter 6: IO & Bus Library VCC Table 6–35 shows the VCC block I/O formats. VCC Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . that is.[R] is an output port. the MSB is the sign bit. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. R = 0. VCC Block I/O Formats I/O O Simulink (2).

Table 7–1 shows the Multi-Rate DFF block inputs and outputs. Use a Dual-Clock FIFO block instead to guarantee correct data transfer. increasing the latency of the Multi-Rate DFF block to at least one slow clock period should result in correct simulation results. Description © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Typically.7. such as Delay or Increment Decrement blocks: ■ ■ ■ ■ ■ ■ Clock Clock_Derived Dual-Clock FIFO Multi-Rate DFF PLL Tsamp f For information about the Clock and Clock_Derived blocks. Table 7–1. an error message of the following form issues in the MATLAB command window: Warning: simulation will not match hardware If your design allows. Output data port. Multirate DFF Block Inputs and Outputs Signal d q ena sclr Direction Input Output Input Input Input data port. Storage Library. In such cases. otherwise data is corrupted or lost. refer to Chapter 9. Rate Change Library The Rate Change library contains the following blocks that allow you to control the clock assignment to registered DSP Builder blocks. Do not use a Multi-Rate DFF block to cross asynchronous clock domains. differences may occur when moving from a slow to a fast clock domain. If the clocks are asynchronous. simulations do not match hardware. For information about the Dual-Clock FIFO block. AltLab Library. Multi-Rate DFF The Multi-Rate DFF block implements a D-type flipflop and typically specifies sample rate transitions. 1 Simulation of the Multi-Rate DFF block may not match hardware because of limitations in the way DSP Builder simulates multiclock designs. Optional synchronous clear port. refer to Chapter 1. Optional clock enable port.

(2) [L] is the number of bits on the left side of the binary point. For signed or unsigned integers R = 0. Multi-Rate DFF Block Parameters Name Number of Pipeline Stages Use Base Clock Clock Name Use Enable Port Use Synchronous Clear Port Value Description >= 1 Adds more pipeline stages to the block.[R] is an output port. Table 7–3. the MSB is the sign bit. R = 0. [R] is the number of bits on the right side of the binary point. Figure 7–1. Specify the name of the clock signal. that is. Table 7–2. Turn on to use the synchronous clear input (sclr). use a Bus Conversion block to set the width. (3) I1[L].[R] Notes to Table 7–3: (1) For signed integers and signed binary fractional numbers.[0].1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({L + R . [L]. (4) Explicit means that the port bit width information is a block parameter. On or Off User specified On or Off On or Off Turn on to use the base clock. Increased delay reduces the likelihood of (Parameterizable) metastability. that is. (3) I1[L]. Multi-Rate DFF Block I/O Formats I/O I I2[1] I3[1] O O1[L]. Table 7–3 shows the Multi-Rate DFF block I/O formats. Turn on to use the clock enable input (ena). [1] is a single bit.[R] is an input port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port. For single bits.1} DOWNTO 0) Implicit Figure 7–1 shows an design example with the Multi-Rate DFF block. O1[L].7–2 Chapter 7: Rate Change Library Multi-Rate DFF Table 7–2 shows the Multi-Rate DFF block parameters. Multirate DFF Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . (Note 1) VHDL Type (4) Implicit Simulink (2).[R] I2: in STD_LOGIC I3: in STD_LOGIC I1: in STD_LOGIC_VECTOR({L + R .

Their use ranges from improving timing as zero delay lines to full-system clock synthesis. Divide the reference clock period by this value. Cyclone. The following restrictions apply when you use a PLL block: ■ Your design may contain more than one PLL block but they must be at the top level. spread spectrum. The PLL block generates internal clocks with frequencies that are multiples of the frequency of the system clock. PLL Block Parameters (Part 1 of 2) Name Input Clock: Use Base Clock Output Clocks Period Multiplier Period Divider On or Off <PLL block name>_clk0 to <PLL block name>_clk8 (1) (1) Value User specified Description Specify the name of the input clock signal. The PLLs offer full frequency synthesis capability (the ability to multiply up or divide down the clock period) and phase shifting for optimizing I/O timing. The number of PLL internal clock outputs supported by each device family depends on the specific device packaging. The number of PLL clock outputs. The PLL block checks the validity of the parameters. refer to the device handbook for the device family you target. Additionally. Turn on to use the base clock. Select the PLL clock that you want to set frequency multiplier and divider factors for. Each output clock of the PLL has a zero degree phase shift and 50% duty cycle. Each PLL has multiple outputs that can source any of the 40 system clocks in the devices to give you complete control over your clocking needs. 1 If you use a PLL block to define clock signals when there is no Clock block in your design. and clock switchover. Table 7–4. f For information about the built-in PLLs. ■ Table 7–4 shows the PLL block parameters. the PLL-derived clocks might not pass the derived period correctly to the blocks referencing the PLL-derived clock. The Arria. Multiply the reference clock period by this value. and Stratix series device families offer advanced on-chip PLL features that were previously offered only by the most complex discrete devices.Chapter 7: Rate Change Library PLL 7–3 PLL The PLL block generates a clock signal that is based on a reference clock. the PLLs have high-end features such as programmable bandwidth. Number of Output Clocks 1–9 © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Always explicitly include a Clock block with a PLL block. PLLs on the FPGA can simultaneously multiply and divide the reference clock. Phase-locked loops (PLL) have become an important building block of most high-speed digital systems today.

DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . slower multiple of the upstream clock.1} DOWNTO 0) Type (4) Implicit Implicit Notes to Table 7–7: (1) For signed integers and signed binary fractional numbers. Output data port. For signed or unsigned integers R = 0. Description Table 7–6 shows the Tsamp block parameters. Table 7–5. the MSB is the sign bit. the simulation results may not match ModelSim. (3) I1[L].[R] is an input port.[R] (Note 1) VHDL I1: in STD_LOGIC_VECTOR({L + R . Tsamp Block Inputs and Outputs Signal <unnamed> <unnamed> Direction Input Output Input data port. Specify the name of the Clock block that specifies the clock signal. (2) [L] is the number of bits on the left side of the binary point. R = 0. O1[L]. that is.[0]. For single bits. Tsamp Block I/O Formats I/O I O Simulink (2). Table 7–5 shows the Tsamp block inputs and outputs. Tsamp Block Parameters Name Specify Clock Clock Name Value On or Off User specified Description Turn on to explicitly specify the clock name. Figure 7–2 on page 7–5 shows an design example with the Tsamp block. Value On or Off Description Turn on to export this clock as an output pin.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({L + R . To specify the bus format of an implicit input port. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Table 7–6. in this case it is better to use a Multi-Rate DFF block. PLL Block Parameters (Part 2 of 2) Name Export As Output Pin Note to Table 7–4: (1) Refer to the device documentation for the device family you target. [L]. (4) Explicit means that the port bit width information is a block parameter. Table 7–7 shows the Tsamp block I/O formats. [R] is the number of bits on the right side of the binary point. 1 When you use the Tsamp block. Table 7–7.[R] O1[L]. you must select a variable step solver in the Simulink configuration parameters. (3) I1[L]. that is. Unless the downstream clock is an exact. Tsamp The Tsamp block sets the clock domain inherited by all downstream blocks.[R] is an output port. use a Bus Conversion block to set the width. [1] is a single bit.7–4 Chapter 7: Rate Change Library Tsamp Table 7–4.

Tsamp Block Example This design example is available in the <DSP Builder install path>\DesignExamples \Demos\Filters\Filters\CicFilter directory. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .Chapter 7: Rate Change Library Tsamp 7–5 Figure 7–2.

7–6 Chapter 7: Rate Change Library Tsamp DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

refer to Avalon Interface Specifications. also use Read. This block is not cycle-accurate and a warning issues if you use it in a gate level (cycle-accurate) simulation. Not required if there are no write transfers. Write request signal. Address lines for read transfers. also use ReadData. the block attempts to use a Simulink fixed-point license. refer to the Simulink Help. Not required if there are no read transfers. If you do not have a Simulink fixed-point license. f For information about the Avalon-MM interface. Read request signal. you can only use 8. If used. The External RAM block stores and retrieves data from a range of addresses and is compatible with the Avalon-MM interface. Data lines for read transfers. 16 or 32 bit data widths. Stalls the interface when the Avalon-MM interface cannot respond immediately to a write request. f WriteWaitRequest Output © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Not required if there are no write transfers. This is a simulation only block.8. also use WriteData. 1 If 64 or 128 bit data width is specified. For information about fixed-point licenses. Table 8–1. Simulation Library The Simulation library contains the following simulation-only blocks that do not synthesize to HDL when Signal Compiler runs: ■ ■ External RAM Multiple Port External RAM External RAM The External RAM block is a simulation model of an external RAM. Not required if there are no read transfers. also use Write. and does not generate any HDL when Signal Compiler is run. If used. Address lines for write transfers. If used. Table 8–1 shows the External RAM block inputs and outputs. External RAM Block Inputs and Outputs (Part 1 of 2) Signal WriteData WriteAddress ReadAddress Read Write ReadData Direction Input Input Input Input Input Output Description Data lines for write transfers. If used..

Specifies the number of bits n for the address. Table 8–2 shows the External RAM block parameters. 64 and 128 bit data widths require a Simulink fixed-point license. (Note 1) Specifies the total size of the RAM in bytes (the number of addresses when you use a range of addresses). or 128 1–32 0–10 1–255 1–2n Description Specifies the number of bits for the data. 32. Marks the rising clock edge when ReadData is asserted. Specifies the latency for pipelined read transfers. 64. External RAM Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . 16. Figure 8–1. 1–2n (Note 1) Specifies an offset for the RAM start address (the start address when you use a range of addresses. Figure 8–1 shows an design example with the External RAM block. Value 8. Indicates that valid data is present on the ReadData lines. Table 8–2. No other values are supported. External RAM Block Parameters Name Data Width Address Width Wait States Per Write Maximum Latency Size Offset Notes to Table 8–2 (1) The size added to the offset must be less than 2n where n is the address width. External RAM Block Inputs and Outputs (Part 2 of 2) Signal ReadWaitRequest ReadDataValid Direction Output Output Description Stalls the interface when the Avalon-MM interface cannot respond immediately to a read request.8–2 Chapter 8: Simulation Library External RAM Table 8–1. Specifies a fixed number of wait states for each write transfer.

For information about fixed-point licenses. perform the following steps: 1. WriteWaitRequestN Output ReadDataN ReadDataValidN ReadWaitRequestN Output Output Output © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Click on the block. Stalls the interface when the Avalon-MM interface cannot respond immediately to a read request on port N. Address lines for write transfers on port N. However. f For information about the Avalon-MM interface. Data lines for read transfers on port N. Write burst count for transfers on port N. you can only use 8. To display the updated block symbol correctly. Indicates that valid data is present on the ReadDataN lines. It stores and retrieves data from a range of addresses and is compatible with the Avalon-MM interface. Marks the rising clock edge when ReadDataN is asserted. Write enable for transfers on port N. If you do not have a Simulink fixed-point license. The ports on the block symbol update when you change the number of write or read interfaces. This is a simulation only block. 1 If 64 or 128 bit data width is specified. refer to the Simulink Help. run the following command in MATLAB: alt_dspbuilder_update_external_RAM f Table 8–3 shows the Multiple Port External RAM block inputs and outputs. Read enable for transfers on port N. Table 8–3. 16 or 32 bit data widths. and does not generate any HDL when you run Signal Compiler. 2.Chapter 8: Simulation Library Multiple Port External RAM 8–3 Multiple Port External RAM The Multiple Port External RAM block is a simulation model of a multiple port external RAM block. the block attempts to use a Simulink fixed-point license. This block is not cycle-accurate and a warning issues if you use it in a gate level (cycle-accurate) simulation. the port names do not automatically show on the block symbol. Address lines for read transfers on port N. Multiple Port External RAM Block Inputs and Outputs Signal WriteDataN WriteAddressN WriteEnableN WriteBurstCountN ReadAddressN ReadEnableN ReadBurstCountN Direction Input Input Input Input Input Input Input Description Data lines for write transfers on port N.. Read burst count for transfers on port N. refer to Avalon Interface Specifications. Stalls the interface when the Avalon-MM interface cannot respond immediately to a write request on port N. point to Link Options in the popup menu and click Break Link. While the block is still selected.

Value Description Specifies the number of write ports. Specifies the latency for pipelined read transfers. Multiple Port External RAM Block Parameters Name Number of Write Interfaces 0–5 Number of Read Interfaces 0–5 Data Width Address Width Wait States Per Write Maximum Latency Size Offset Notes to Table 8–4 (1) The size added to the offset must be less than 2n where n is the address width. Specifies the number of bits n for the address. 64. Specifies a fixed number of wait states for each write transfer. Specifies the number of read ports. or 128 1–32 0–10 1–255 1–2n (Note 1) Specifies the total size of the RAM in bytes (the number of addresses when you use a range of addresses). 32. 64 and 128 bit data widths require a Simulink fixed-point license. No other values are supported. Specifies the number of bits for the data.8–4 Chapter 8: Simulation Library Multiple Port External RAM Table 8–4 shows the Multiple Port External RAM block parameters. 16. 1–2n (Note 1) Specifies an offset for the RAM start address (the start address when you use a range of addresses. 8. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Table 8–4.

9. Storage Library The Storage library contains the following blocks. which support storage and associated control functions: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Delay Down Sampling Dual-Clock FIFO Dual-Port RAM FIFO Buffer LUT (Look-Up Table) Memory Delay Parallel To Serial ROM Serial To Parallel Shift Taps Single-Port RAM True Dual-Port RAM Up Sampling © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .

the data on phases 1. Use Enable Port Use Synchronous Clear Port Reset To Constant (Non-Zero) Value Reset Value On or Off On or Off On or Off Turn on to use the clock enable input (ena). The block accepts any data type as inputs. Description Table 9–2 shows the Delay block parameters. and 4 do not pass through the delay block. Turn on to use the synchronous clear input (sclr). Optional synchronous clear port. That is. Table 9–1 shows the Delay block inputs and outputs. The delay must be greater than or equal to Stages (Parameterizable) 1. Clock Phase Selection User Defined Specify the phase selection with a binary string.1} DOWNTO 0) Type (4) Implicit DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . (Parameterizable) Table 9–3 shows the Delay block I/O formats. where a 1 indicates the phase in which the Delay block is enabled. Delay Block I/O Formats (Part 1 of 2) (Note 1) I/O I I2[1] I3[1] Simulink (2). Table 9–2. Output data port. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). User Defined Specify the reset value. Table 9–3. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. Delay Block Inputs and Outputs Signal <unnamed> ena sclr <unnamed> Direction Input Input Input Output Input data port. 3. Table 9–1. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. Optional clock enable port.[R1] I2: in STD_LOGIC I3: in STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . Delay Block Parameters Name Value Description Number of Pipeline User Defined Specify the pipeline length of the block. (3) I1[L1]. Turn on to specify a non-zero reset value. Specifying a reset value increases the hardware resources.9–2 Chapter 9: Storage Library Delay Delay The Delay block delays the incoming data by an amount specified by the number of pipeline stages.

[R] is the number of bits on the right side of the binary point. (3) O1[L1].[0].Chapter 9: Storage Library Down Sampling 9–3 Table 9–3. The output data is sampled at every Nth cycle where N is the down sampling rate. that is. use a Bus Conversion block to set the width. the MSB is the sign bit.[R1] VHDL O1: in STD_LOGIC_VECTOR({L1 + R1 . Table 9–4 shows the Down Sampling block inputs and outputs. O1[L]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. (3) I1[L]. (4) Explicit means that the port bit width information is a block parameter. that is. R = 0. Table 9–4. Figure 9–1. Delay Block Example Down Sampling The Down Sampling block decreases the output sample rate from the input sample rate. [L]. For single bits. [1] is a single bit. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Output data port. Figure 9–1 shows an example with the Delay block.[R] is an output port. Down Sampling Block Inputs and Outputs Signal d q Direction Input Output Input data port. To specify the bus format of an implicit input port. The output data is then held constant for the next N input cycles. Delay Block I/O Formats (Part 2 of 2) (Note 1) I/O O Simulink (2). Table 9–5. For signed or unsigned integers R = 0. Down Sampling Block Parameters Name Down Sampling Rate Value An integer greater than 1 (Parameterizable) Description Specify the down sampling rate.1} DOWNTO 0) Type (4) Implicit Notes to Table 9–3: (1) For signed integers and signed binary fractional numbers. Description Table 9–5 shows the Down Sampling block parameters. (2) [L] is the number of bits on the left side of the binary point.[R] is an input port.

the MSB is the sign bit. Optional asynchronous clear input. [L]. [1] is a single bit. Indicates that the FIFO buffer is full and disables the wrreq port.1} DOWNTO 0) Type (4) Implicit Implicit Notes to Table 9–6: (1) For signed integers and signed binary fractional numbers. that is. (3) I1[L1]. O1[L]. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Figure 9–2.1} DOWNTO 0) O1: in STD_LOGIC_VECTOR({L1 + R1 . Write request control. Down Sampling Block Example Dual-Clock FIFO The Dual-Clock FIFO block implements a parameterized. but not cycle-accurate. The oldest data in the FIFO buffer goes to the q[] port. To specify the bus format of an implicit input port. Optional output synchronized to the read clock. Description DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . The d[] port is written to the FIFO buffer. Indicates the number of words that are in the FIFO buffer. (3) I1[L]. dual-clock FIFO buffer controlled by separate read-side and write-side clocks. Dual-Clock FIFO Block Inputs and Outputs (Part 1 of 2) Signal d wrreq rdreq aclr q rdfull rdempty rdusedw Direction Input Input Input Input Output Output Output Output Data input to the FIFO buffer. Optional output synchronized to the read clock. Indicates that the FIFO buffer is empty and disables the rdreq port. Table 9–7 shows the Dual-Clock FIFO block inputs and outputs. Optional output synchronized to the read clock. For single bits. 1 The Dual-Clock FIFO block simulation in Simulink is functionally equivalent to hardware. that is.[R] is an input port.[R] is an output port. which flushes the FIFO. use a Bus Conversion block to set the width. Figure 9–2 shows an example with the Down Sampling block.[R1] O1[L1]. R = 0.[R1] VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 .[0]. Table 9–6. Down Sampling Block I/O Formats (Note 1) I/O I O Simulink (2). Read request control. (4) Explicit means that the port bit width information is a block parameter. [R] is the number of bits on the right side of the binary point. For signed or unsigned integers R = 0. (2) [L] is the number of bits on the left side of the binary point. Data output from the FIFO buffer.9–4 Chapter 9: Storage Library Dual-Clock FIFO Table 9–6 shows the Down Sampling block I/O formats. Table 9–7.

Turn on to register the output ports. Table 9–8 shows the Dual-Clock FIFO block parameters. AUTO. M512. Unsigned Integer. Turn on to use the write-side empty port (wrfull). Specify the read-side clock signal when not using the base clock. M144K device types. Some memory types are not available for all M9K. Specify the write-side clock signal when not using the base clock.Chapter 9: Storage Library Dual-Clock FIFO 9–5 Table 9–7. Turn on to use the base clock signal for the read-side clock. Indicates that the FIFO buffer is empty and disables the rdreq port. Turn on to use the show-ahead mode of read-request. Indicates the number of words that are in the FIFO buffer.[] []. Optional output synchronized to the write clock. Turn on to use the write-side empty port (wrempty). Description Number of Words in the FIFO Integer (Parameterizable) Input Bus Type Signed Integer. Turn on to use the read-side full port (rdfull). Specify the number of bits to the right of the binary point. Indicates that the FIFO buffer is full and disables the wrreq port. M4K. Turn on to use the asynchronous clear port (aclr). This mode is faster but larger. MLAB. Turn on to use the base clock signal for the write-side clock. User defined On or Off User defined On or Off On or Off On or Off On or Off On or Off On or Off Use Base Clock for Read Side On or Off Read-Side Clock Use Base Clock for Write Side Write-Side Clock Use Read-Side Synchronized EMPTY Port Use Read-Side Synchronized FULL Port Use Read-Side Synchronized USEDW Port Use Write-Side Synchronized EMPTY Port Use Write-Side Synchronized EMPTY Port Use Write-Side Synchronized USEDW Port Register Output Implement FIFO with logic Cells Only Use Show-Ahead Mode of Read Request Use Asynchronous Clear Port On or Off On or Off On or Off On or Off © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Table 9–8. Signed Fractional >= 0 (Parameterizable) >= 0 (Parameterizable) [number of bits]. Turn on to use the read-side empty port (rdempty). Dual-Clock FIFO Block Inputs and Outputs (Part 2 of 2) Signal wrfull wrempty wrusedw Direction Output Output Output Description Optional output synchronized to the write clock. Turn on to implement the FIFO buffer with logic cells only. This option applies only to signed fractional formats. Optional output synchronized to the write clock. Dual-Clock FIFO Block Parameters Name Value Specify the FIFO depth The bus type format. Turn on to use the read-side words port (rdusedw). Turn on to use the write-side words port (wrusedw).[number of bits] Memory Block Type Specify the number of bits stored on the left side of the binary point. The FPGA RAM type.

1} DOWNTO 0) Figure 9–3 shows an example with the Dual-Clock FIFO block.9–6 Chapter 9: Storage Library Dual-Clock FIFO Table 9–9 shows the Dual-Clock FIFO block I/O formats. the MSB is the sign bit. [R] is the number of bits on the right side of the binary point. Table 9–9. Dual-Clock FIFO Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .[R1] I2[1] I3[1] O O1[L1]. Figure 9–3. [L].[R] is an input port. [1] is a single bit. (3) I1[L]. that is. (3) I1[L1]. O1[L]. (4) Explicit means that the port bit width information is a block parameter. For signed or unsigned integers R = 0.[R1] O2[1] O3[1] O4[1] O5[1] O6[L2]. (Note 1) VHDL Type (4) Explicit Explicit Explicit Explicit Explicit Explicit Explicit Explicit Explicit-optional Explicit-optional I1: in STD_LOGIC_VECTOR({L1 + R1 . R = 0. For single bits.1} DOWNTO 0) O7: out STD_LOGIC_VECTOR({L2 .[0] Notes to Table 9–9: (1) For signed integers and signed binary fractional numbers. (2) [L] is the number of bits on the left side of the binary point. that is. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.1} DOWNTO 0) I2: in STD_LOGIC I3: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 . use a Bus Conversion block to set the width.[0] O7[L2]. To specify the bus format of an implicit input port.[R] is an output port.[0]. Dual-Clock FIFO Block I/O Formats I/O I Simulink (2).1} DOWNTO 0) O2: out STD_LOGIC O3: out STD_LOGIC O4: out STD_LOGIC O5: out STD_LOGIC O6: out STD_LOGIC_VECTOR({L2 .

The Quartus II software does allow you to create non-standard . Optional clock enable port Output data port. Write address bus. The MATLAB array parameter must be a one dimensional MATLAB array with a length less than or equal to the number of words.hex file is formatted in multiples of eight and the output bit width should also be in multiples of eight. Dual-Port RAM Block Inputs and Outputs Signal d rd_add wr_add wren ena q_a Direction Input Input Input Input Input Output Input data port. especially if the memory implements as a MLAB. Turning on DONT_CARE may give a higher fMAX for your design. When this option is on. The contents of the RAM are pre-initialized to zero by default. you should set the output bit width to the same as that in the . in the case of MLAB implementation. and you gain an extra half-cycle on the output. which outputs old data for read-during-write. f For instructions on creating this file. or embedded system block. The Dual-Port RAM block accepts any data type as input.hex file. large numbers with less bits may be treated as negative numbers.hex files but pads 1's to the front for negative numbers to make them multiples of eight. EAB. Description © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Table 9–10 shows the Dual-Port RAM block inputs and outputs.hex file. Specify the array from the MATLAB workspace or directly in the MATLAB Array box. f For more information about this option. Write enable. DSP Builder supports 32-bit addressing with extended linear address records in the .Chapter 9: Storage Library Dual-Port RAM 9–7 Dual-Port RAM The Dual-Port RAM block maps data to an embedded RAM (embedded array block. Thus. uses fewer external registers). The clock enable signal (ena) bypasses any output register. 1 The input address bus must be unsigned. If you require a different bit width. A warning issues if you specify a non-standard .hex file but use an AltBus block to convert to the required bit width. The default is off. Read address bus. refer to the Read-During-Write Output Behavior section in the RAM Megafunction User Guide. Use an Intel Hexadecimal (.hex file that must be in your DSP Builder working directory. Use the Quartus II software to generate a. ESB) in Altera devices. the output is not double-registered (and therefore. The input port always registers and the output port can optionally be registered. The read and write ports are separate. refer to Creating a Memory Initialization File or Hexadecimal (Intel-Format) File in the Quartus II Help.hex) file or MATLAB array to specify them. The data in a standard . Table 9–10.

Specify the initialization. Specify the number of bits to the right of the binary point. MLAB. From HEX file. When this option is set. [number of bits]. the contents of the RAM are pre-initialized to zero. M144K Description Specify the address width in words.hex file. ensure that the same address is not read from and written to at the same time or that your design does not depend on the read output in these circumstances.hex file. you see mismatches associated with any read/write to the same address events. For example: [0:1:15] Turn on to register the output port. Use DONT_CARE when reading from and writing to the same address On or Off Initialization Input HEX File Blank. The input data type format. If the implementation is set to MLAB. Dual-Port RAM Block Parameters (Part 1 of 2) Name Number of words Data Type Value >= 1 (Parameterizable) Inferred. but a warning message issues on every simultaneous read/write to the same address. setting DONT_CARE gives more flexibility in RAM block placement. The Simulink simulation is unchanged whether or not you use this option. Table 9–11. Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. and comparisons with ModelSim shows differences.[] []. By default this option is off. M4K. The FPGA RAM memory block type. Unsigned Integer. Specify the name of a . M9K. From MATLAB array User defined MATLAB Array Register output Port Use Enable Port User defined (Parameterizable) On or Off On or Off DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . M512. and data is always read before write. because the output is not double registered. and the resulting memory block can often be run at a higher fMax. Signed Fractional >= 0 (Parameterizable) >= 0 (Parameterizable) AUTO. Simulink does not modify the unknowns . In ModelSim simulation.[number of bits] Memory Block Type Specify the number of bits stored on the left side of the binary point. Some RAM memory types are not available for all device types. If the memory block type is set to AUTO.hex. Signed Integer. However. unknowns (X) are output when reading from and writing to the same address. the RAM is always initialized to unknown in the hardware and simultaneous read/writes to the same address also give unknown in hardware. This option applies only to signed fractional formats. DSP Builder supports 32-bit addressing with extended linear address records in the . If you specify M-RAM. For example: input. Turn on to use the optional clock enable input (ena). If Blank is selected. If you compare the simulation results to ModelSim. M-RAM.9–8 Chapter 9: Storage Library Dual-Port RAM Table 9–11 shows the Dual-Port RAM block parameters. which must be in your DSP Builder working directory. the design uses fewer external registers. the output in hardware when reading from and writing to the same address is unpredictable.

(4) Explicit means that the port bit width information is a block parameter. that is. the data on phases 1. O1[L]. [1] is a single bit.[R] is an input port. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Table 9–12 shows the Dual-Port RAM block I/O formats. (2) [L] is the number of bits on the left side of the binary point. To specify the bus format of an implicit input port. Table 9–12. For single bits. R = 0. Dual-Port RAM Block I/O Formats I/O I Simulink (2). Figure 9–4. That is. (3) I1[L1].1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 . [L]. and 4 do not pass through the block. Dual-Port RAM Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .1} DOWNTO 0) I3: in STD_LOGIC_VECTOR({L3 .[0]. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). where a 1 indicates the phase in which the block enables.Chapter 9: Storage Library Dual-Port RAM 9–9 Table 9–11.1} DOWNTO 0) Explicit Figure 9–4 shows an example with the Dual-Port RAM block.[R1] Notes to Table 9–12: (1) For signed integers and signed binary fractional numbers.[R1] I2[L2]. (Note 1) VHDL Type (4) Explicit I1: in STD_LOGIC_VECTOR({L1 + R1 . use a Bus Conversion block to set the width. that is. 3.1} DOWNTO 0) I4: in STD_LOGIC I5: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 .[0] I3[L2].[0] I4[1] I5[1] O O1[L1]. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. (3) I1[L]. Dual-Port RAM Block Parameters (Part 2 of 2) Name Clock Phase Selection Value User Defined Description Specify the phase selection with a binary string. [R] is the number of bits on the right side of the binary point. the MSB is the sign bit.[R] is an output port. For signed or unsigned integers R = 0.

Indicates that the FIFO buffer is empty and disables the rreq port. [number of bits]. Some memory types are not available for all device M9K. Turn on to implement the FIFO buffer with logic cells only. Indicates the number of words that are in the FIFO buffer. FIFO Block Parameters Name Number of Words in the FIFO Data Type Value User Defined (Parameterizable) Inferred. The d[] port is written to the FIFO buffer. Read request control. Turn on to use the show-ahead mode of read-request. Signed Fractional. Use Show-Ahead On or Off Mode of Read Request DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . M4K.[number of bits] Memory Block Type Use Synchronous Clear Port Implement FIFO with logic Cells Only Specify the number of bits stored on the left side of the binary point including the sign bit.[] []. Indicates that the FIFO buffer is full and disables the wrreq port. The data input type format. The oldest data in the FIFO buffer goes to the q[] port. The RAM block type. M144K types. single-clock FIFO buffer. This option applies only to signed fractional. Signed Integer.9–10 Chapter 9: Storage Library FIFO Buffer FIFO Buffer The FIFO block implements a parameterized. Write request control. Specify the number of bits stored on the right side of the binary point. Table 9–14. Table 9–13. AUTO. Data output from the FIFO buffer. M512. On or Off On or Off Turn on to use the synchronous clear port (sclr). FIFO Block Inputs and Outputs Signal d rreq sclr q full usdw Direction Input Input Input Output Output Output Data input to the FIFO buffer. Optional synchronous clear port that flushes the FIFO. The default is 64. Table 9–13 shows the FIFO block inputs and outputs. Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) Description Specify how many words you want in the FIFO buffer. Description wrreq Input empty Output Table 9–14 shows the FIFO block parameters. 1 Reading an empty FIFO buffer may give unknown (X) in hardware. MLAB.

[R1] I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC I1: in STD_LOGIC_VECTOR({L1 + R1 . R = 0. O1[L]. The values of the words are specified in the data vector field as a MATLAB array.[0] Notes to Table 9–15: (1) For signed integers and signed binary fractional numbers. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.hex to store data. the synthesis tool may use logic cells or embedded array blocks (EABs). Figure 9–5.[0].1} DOWNTO 0) Explicit Figure 9–5 shows an example with the FIFO block. (3) I1[L1]. [L]. that is. FIFO Block I/O Formats I/O I I2[1] I3[1] I4[1] O O1[L1]. 1 If you want to use a . To specify the bus format of an implicit input port. For single bits. (3) I1[L]. or TriMatrix™ memory.[R] is an output port. Depending on the look-up table size. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .[R1] O2[1] O3[1] O4[L2]. embedded system blocks (ESBs). For signed or unsigned integers R = 0. (2) [L] is the number of bits on the left side of the binary point. the MSB is the sign bit. [R] is the number of bits on the right side of the binary point. [1] is a single bit.[R] is an input port. FIFO Block Example LUT (Look-Up Table) The LUT (Look-Up Table) block stores data as 2(address width) words of data in a look-up table. Table 9–15. use a Bus Conversion block to set the width. use the ROM block not the LUT block.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({L1 + R1 . (4) Explicit means that the port bit width information is a block parameter.1} DOWNTO 0) O2: out STD_LOGIC O3: out STD_LOGIC O4: out STD_LOGIC_VECTOR({L2 . that is. (Note 1) VHDL Type (4) Explicit Simulink (2).Chapter 9: Storage Library LUT (Look-Up Table) 9–11 Table 9–15 shows the FIFO block I/O formats.

[1] is a single bit. Some memory types are not available for all device types. [L]. (Note 1) VHDL Type (4) Explicit Simulink (2). You should turn on this option for large look-up tables. Specify the number of data bits stored on the right side of the binary point.[R] is an input port.[R] is an output port. Signed Fractional.9–12 Chapter 9: Storage Library LUT (Look-Up Table) Table 9–16 shows the LUT block parameters. use a Bus Conversion block to set the width. (3) I1[L1].1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LPO + LPO . (4) Explicit means that the port bit width information is a block parameter. Turn on to use the optional clock enable input (ena). the look-up table implements as case conditions with the lpm_rom library of parameterized modules (LPM) function. the input address is always registered. Table 9–16. the input address bus generates.[] []. When on.[0] I2: in STD_LOGIC I1: in STD_LOGIC_VECTOR({L1 . O1[L]. To specify the bus format of an implicit input port. A warning is given if the values in the MATLAB array cannot be exactly represented in the chosen data format.[number of bits] MATLAB Array Specify the number of data bits stored on the left side of the binary point including the sign bit. Table 9–17. If you use LPM. MLAB. greater than 8 bits. M144K Table 9–17 shows the LUT block I/O formats.1} DOWNTO 0) DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . R = 0. For single bits. that is. that is. The input address always registers when this option is on. LUT Block Parameters Name Address Width Data Type 2–16 Signed Integer. The data type format that you want to use. M4K. The RAM block type. LUT Block I/O Formats I/O I O I2[1] O1[LPO].[RPO] Notes to Table 9–17: (1) For signed integers and signed binary fractional numbers. M9K. for example. Unsigned Integer. (3) I1[L]. [R] is the number of bits on the right side of the binary point. M512. Use Enable Port Register Data Use LPM Register Address On of Off Memory Block Type AUTO.[0]. When register address is on. Turn on to register the output result. For signed or unsigned integers R = 0. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. [number of bits]. Single Bit >= 0 (Parameterizable) >= 0 (Parameterizable) User Defined (Parameterizable) On or Off On or Off On or Off Value Description The address width as an unsigned integer. This field must be a one-dimensional MATLAB array with a length smaller than 2 to the power of the address width. the MSB is the sign bit. (2) [L] is the number of bits on the left side of the binary point.

M144K device types.[number of bits] Number of Pipeline Stages Specify the number of data bits stored on the left side of the binary point including the sign bit. Some memory types are not available for all M9K.Chapter 9: Storage Library Memory Delay 9–13 Figure 9–6 shows an example with the LUT block. Table 9–21 shows the Memory Delay block inputs and outputs. Table 9–19. Output data port. Memory Delay Block Parameters Name Data Type Value Inferred. When non-zero. if the number of pipeline stages is greater than or equal to 1). The RAM block type. M4K. Unsigned Integer >= 0 (Parameterizable) >= 0 (Parameterizable) 0 to number of bits (Parameterizable) Description The data type format that you want to use. Table 9–18.[] []. Specify the number of data bits stored on the right side of the binary point. Signed Fractional. M512. On or Off Turn on to use the clock enable input. Signed Integer. [number of bits]. adds pipeline stages to increase the data throughput. Use Synchronous Clear Port On or Off © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Figure 9–6. MLAB. Description Table 9–19 shows the Memory Delay block parameters. Memory Delay Block Inputs and Outputs Signal d ena sclr q Direction Input Input Input Output Input data port. Optional clock enable port. You should typically use this block for delays greater than 3. when possible. Optional synchronous clear port. Turn on to use the synchronous clear port (sclr). Memory Block Type Use Enable Port AUTO. LUT Block Example Memory Delay The Memory Delay block implements a shift register that uses the Altera device’s embedded memory blocks. The clock enable and synchronous clear ports are available only if the block is registered (that is.

Table 9–20. if this option is off. 1 . use a Bus Conversion block to set the width.. <--------------... <--------------.. if input is an 8-bit unsigned integer value 1 the output is: 0 .. Memory Delay Block Example Parallel To Serial The Parallel To Serial block takes a bus input on load and outputs the individual bits one cycle at a time with either the MSB or LSB first...[0].. 1 .. Figure 9–7. 0 .. (4) Explicit means that the port bit width information is a block parameter.... 0 .9–14 Chapter 9: Storage Library Parallel To Serial Table 9–20 shows the Memory Delay block I/O formats.. 0 . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.. 0 . that is.. [R] is the number of bits on the right side of the binary point.1} DOWNTO 0) Implicit Figure 9–7 shows an example with the Memory Delay block..data values ---------------->|<----. the MSB is the sign bit. 0 . R = 0. [1] is a single bit..[R] is an input port.... 0 . You can specify to continually output the last bit until the last load... that is.. (3) I1[L1]...last bit repeated until next load -> Alternatively.. For signed or unsigned integers R = 0. 0 .. Simulink (2)..1} DOWNTO 0) Type (4) Implicit O1: in STD_LOGIC_VECTOR({L1 + R1 ..data values ---------------->|<.... 0 . you can output 0 after the data has finished. [L].[R1] Notes to Table 9–20: (1) For signed integers and signed binary fractional numbers..... 0 .. 0 ... (3) I1[L]..[R1] I2: in STD_LOGIC I3: in STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . Memory Delay Block I/O Formats (Note 1) I/O I I2[1] I3[1] O O1[L1].... 0 .. 1 . 0 ... 0 .. for the same example: 0 . O1[L].. (2) [L] is the number of bits on the left side of the binary point. For example... 0 ..... For single bits..[R] is an output port.... 0 . 1 . To specify the bus format of an implicit input port.. that is. 1 ..zeros until next load ----> DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation ..

(4) Explicit means that the port bit width information is a block parameter. Table 9–21. [L]. Table 9–23. Description [number of bits]. Optional synchronous clear port. Turn on to use the synchronous clear port (sclr). use a Bus Conversion block to set the width. [1] is a single bit. (3) I1[L1]. Table 9–23 shows the Parallel To Serial block I/O formats. Optional clock enable port. Transmit the MSB or LSB first. Serial output port. Load port. that is. (Note 1) VHDL Type (4) Explicit Simulink (2). Parallel To Serial Block Inputs and Outputs Signal d load ena sclr sd Direction Input Input Input Input Output Parallel input port. R = 0. that is.[R] is an output port. Parallel To Serial Block Parameters Name Data Bus Type Value Signed Integer. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. O1[L]. To specify the bus format of an implicit input port. (3) I1[L]. Table 9–22.[R] is an input port. Parallel To Serial Block I/O Formats I/O I I2[1] I3[1] I4[1] O O1[1] Notes to Table 9–23: (1) For signed integers and signed binary fractional numbers. LSB First On or Off On or Off On or Off Specify the number of bits stored on the left side of the binary point. Unsigned Integer The bus type format. Turn on to use the clock enable input. For signed or unsigned integers R = 0.[] >= 0 (Parameterizable) []. [R] is the number of bits on the right side of the binary point. Description Table 9–22 shows the Parallel To Serial block parameters. Turn on to repeat the last bit until the next load.Chapter 9: Storage Library Parallel To Serial 9–15 Table 9–21 shows the Parallel To Serial block inputs and outputs. (2) [L] is the number of bits on the left side of the binary point.[number of bits] >= 0 (Parameterizable) Serial Bit Order Repeat Last Bit Until Next Load Use Enable Port Use Synchronous Clear Port MSB First.[R1] I2: in STD_LOGIC I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC I1: in STD_LOGIC_VECTOR({L1 + R1 .1} DOWNTO 0) Explicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . This option applies only to signed fractional formats. Signed Fractional. For single bits. the MSB is the sign bit.[0]. Specify the number of bits stored on the right side of the binary point.

or embedded system block. 1 The input address bus must be Unsigned.hex file. and you can optionally register the data output port. you should set the output bit width to the same as that in the .hex file but use an AltBus block to convert to the required bit width. If you require a different bit width.hex file is formatted in multiples of eight and the output bit width should also be in multiples of eight. f For instructions on creating a .hex) format file. refer to Creating a Memory Initialization File or Hexadecimal (Intel-Format) File in the Quartus II Help. The MATLAB array parameter must be a one dimensional MATLAB array with a length less than or equal to the number of words. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file. large numbers with less bits may be treated as negative numbers. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .hex file. The address port is registered. Figure 9–8. ESB) in Altera devices. Specify the array from the MATLAB workspace or directly in the MATLAB Array box. with read-only access.9–16 Chapter 9: Storage Library ROM Figure 9–8 shows an example with the Parallel To Serial block. Thus. The contents of the ROM are pre-initialized from an Intel Hexadecimal (.hex file that you must save in your DSP Builder working directory.hex files but pads 1's to the front for negative numbers to make them multiples of eight. The clock enable signal (ena) bypasses any output register. The Quartus II software does allow you to create non-standard . A warning issues if you specify a non-standard . EAB. The data in a standard . Parallel To Serial Block Example ROM The ROM block maps data to an embedded RAM (embedded array block. Use the Quartus II software to generate a . The ROM block can store any data type. or from a MATLAB array.

Turn on to use the optional clock enable input (ena). Description Table 9–25 shows the ROM block parameters. Specify the phase selection with a binary string. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . ROM Block Inputs and Outputs Signal addr ena q Direction Input Input Output Input data port.[] >= 0 (Parameterizable) []. This option applies only to signed fractional formats. From MATLAB array User defined Specify whether the ROM is initialized from a . the data on phases 1. Table 9–25. That is. Specify the number of bits stored on the right side of the binary point.hex file. Some memory types are not available for all device types. The data type format. M9K.Chapter 9: Storage Library ROM 9–17 Table 9–24 shows the ROM block inputs and outputs. [number of bits]. For example: input. where a 1 indicates the phase in which the block is enabled. Table 9–24.hex file that must be in your DSP Builder working directory. For example: [0:1:15] Turn on to register the output port. Unsigned Integer Description Specify the depth of the ROM in words. and 4 do not pass through the delay block. AUTO. M144K From HEX file. ROM Block Parameters Name Number of Words Data Type Value User Defined (Parameterizable) Signed Integer. DSP Builder supports 32-bit addressing with extended linear address records in the . 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through.hex. For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1).[number of bits] >= 0 (Parameterizable) Memory Block Type Initialization Input HEX File Specify the number of bits stored on the left side of the binary point including the sign bit. M512. M4K. The RAM block type. Output data port. 3. Optional clock enable port. Signed Fractional. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through.hex file or from a MATLAB array. Specify the name of a. MATLAB Array Register output Port Use Enable Port Clock Phase Selection User defined (Parameterizable) On or Off On or Off User Defined Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. MLAB.

[R] is the number of bits on the right side of the binary point. R = 0. ROM Block I/O Formats (Note 1) I/O I O I2[1] O1[LPO]. that is.[0].1} DOWNTO 0) Type (4) Explicit Explicit Figure 9–9 shows an example with the ROM block that reads a 256×8 ramp waveform . Parallel output port. For signed or unsigned integers R = 0. Figure 9–9. Description DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . (2) [L] is the number of bits on the left side of the binary point. Table 9–26. O1[L]. (4) Explicit means that the port bit width information is a block parameter. Optional clock enable port.9–18 Chapter 9: Storage Library Serial To Parallel Table 9–26 shows the ROM block I/O formats. Table 9–27.[RPO] Notes to Table 9–26: (1) For signed integers and signed binary fractional numbers. the MSB is the sign bit. (3) I1[L1].[R] is an input port.[0] I2: in STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 . Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port. Treat the input bit stream as either MSB first. Optional synchronous clear port. [L]. or LSB first. Serial To Parallel Block Inputs and Outputs Signal sd ena sclr d Direction Input Input Input Output Serial input port. Simulink (2).[R] is an output port. For single bits. (3) I1[L]. ROM Block Example Serial To Parallel The Serial To Parallel block implements a serial (input sd) to parallel bus conversion (output d). that is.1} DOWNTO 0) O1: out STD_LOGIC_VECTOR({LPO + RPO . use a Bus Conversion block to set the width. [1] is a single bit. Table 9–27 shows the Serial To Parallel block inputs and outputs.hex file.

[R1] Notes to Table 9–29: (1) For signed integers and signed binary fractional numbers. O1[L]. Table 9–29. Figure 9–10. (3) I1: in STD_LOGIC I2: in STD_LOGIC I3: in STD_LOGIC O1: in STD_LOGIC_VECTOR({L1 + R1 . MSB First. Unsigned Integer The bus type format.[R] is an input port.[0].[] >= 0 (Parameterizable) []. Signed Fractional. Turn on to use the clock enable input. (4) Explicit means that the port bit width information is a block parameter. (2) [L] is the number of bits on the left side of the binary point. For single bits. This option applies only to signed fractional formats. LSB First Transmit the MSB or LSB first. Description [number of bits]. For signed or unsigned integers R = 0. (3) I1[L]. [1] is a single bit.[number of bits] >= 0 (Parameterizable) Serial Bit Order Use Enable Port Use Synchronous Clear Port On or Off On or Off Specify the number of bits stored on the left side of the binary point including the sign bit.1} DOWNTO 0) Explicit Figure 9–10 shows an example with the Serial To Parallel block. (Note 1) VHDL Type (4) Explicit Simulink (2). [L]. that is.Chapter 9: Storage Library Serial To Parallel 9–19 Table 9–28 shows the Serial To Parallel block parameters. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. To specify the bus format of an implicit input port. R = 0. that is. the MSB is the sign bit.[R] is an output port. Table 9–29 shows the Serial To Parallel block I/O formats. Serial To Parallel Block Parameters Name Data Bus Type Value Signed Integer. Turn on to use the synchronous clear port (sclr). Table 9–28. Specify the number of bits stored on the right side of the binary point. Serial To Parallel Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . [R] is the number of bits on the right side of the binary point. Serial To Parallel Block I/O Formats I/O I I1[1] I2[1] I3[1] O O1[L1]. use a Bus Conversion block to set the width.

which translates to the number of RAM words that DSP Builder uses. this block implements in the small memory. Table 9–31. Output ports for taps 0–n. Table 9–30 shows the Shift Taps block inputs and outputs. Some memory types are not available for all device types.1} DOWNTO 0) Type (4) Implicit Explicit DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Arria II GX. Turn on to enable selection of the memory block type.9–20 Chapter 9: Storage Library Shift Taps Shift Taps The Shift Taps block implements a shift register that you can use for filters or convolution. (3) I1[L1]. M9K. Optional shift out port. Stratix III. In Stratix IV. Table 9–30. M4K. Optional clock enable port. Arria GX. Stratix GX. and Cyclone devices. Cyclone III. In Stratix devices. Shift Taps Block I/O Formats (Part 1 of 2) (Note 1) I/O I I2[1] Simulink (2). Stratix II. The block outputs occur at regularly spaced points along the shift register (that is. taps). Specifies the distance between the regularly spaced taps in clock cycles. the block implements a RAM-based shift register that is useful for creating very large shift registers efficiently. MLAB. M512.[R1] I2: in STD_LOGIC VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . M144K Table 9–32 shows the Shift Taps block I/O formats. Stratix II GX. Table 9–32. Cyclone II. Use Shift Out Port On or Off AUTO. Shift Taps Block Inputs and Outputs Signal d ena t0–tn sout Direction Input Input Output Output Data input port. This option is only valid when the Distance Between Taps is greater than 2. Description Table 9–31 shows the Shift Taps block parameters. Shift Taps Block Parameters Name Number of Taps Distance Between Taps Use Enable port Use Dedicated Circuitry Memory Block Type Value User Defined (Parameterizable) User Defined (Parameterizable) On or Off On or Off Description Specifies the number of regularly spaced taps along the shift register. The RAM block type. Turn on to create an output from the end of the shift register for cascading. Turn on to use an additional clock enable control input.

Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.1} DOWNTO 0) On+1: out STD_LOGIC Type (4) Implicit Explicit Figure 9–11 shows an example with the Shift Taps block. Oi[L1].[R] is an output port. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . that is. For single bits. (3) I1[L]. A single read/write port allow simple access. the MSB is the sign bit.[R] is an input port. Figure 9–11. [R] is the number of bits on the right side of the binary point. (4) Explicit means that the port bit width information is a block parameter. Shift Taps Block Example Single-Port RAM The Single-Port RAM block maps data to an embedded RAM (embedded array block.[0].[R1] … On[L1]. Simulink (2). The input port is registered. To specify the bus format of an implicit input port. The Single-Port RAM block accepts any type as data input. use a Bus Conversion block to set the width. [1] is a single bit. [L]. (3) O1[L1].1} DOWNTO 0) …. For signed or unsigned integers R = 0. EAB. Shift Taps Block I/O Formats (Part 2 of 2) (Note 1) I/O O …. The contents of the RAM are pre-initialized to zero by default. O1[L]. or embedded system block. and the output port can optionally be registered.[R1] …. (2) [L] is the number of bits on the left side of the binary point. ESB) in Altera devices.hex) file or a MATLAB array to specify them. that is.Chapter 9: Storage Library Single-Port RAM 9–21 Table 9–32. VHDL O1: in STD_LOGIC_VECTOR({L1 + R1 . The clock enable signal (ena) bypasses any output register. R = 0. The input address bus must be Unsigned. On: in STD_LOGIC_VECTOR({L1 + R1 .1} DOWNTO 0) Oi: in STD_LOGIC_VECTOR({L1 + R1 . Use an Intel Hexadecimal (.[R1] On+1[1] Notes to Table 9–32: (1) For signed integers and signed binary fractional numbers.

If you specify M-RAM. Table 9–33 shows the Single-Port RAM block inputs and outputs. Optional clock enable port Output data port. Unsigned Integer.hex files but pads 1's to the front for negative numbers to make them multiples of eight. M9K.[number of bits] >= 0 (Parameterizable) Memory Block Type AUTO. large numbers with less bits may be treated as negative numbers. If you require a different bit width. Table 9–34. Specify the initialization. M-RAM. [number of bits]. Specify the number of bits to the right of the binary point. From MATLAB array DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . and comparisons with ModelSim shows differences. The data in a standard . The FPGA RAM memory block type.hex file but use an AltBus block to convert to the required bit width.hex file is formatted in multiples of eight and the output bit width should also be in multiples of eight. M512.hex file.[] >= 0 (Parameterizable) []. Signed Integer. The MATLAB array parameter must be a one dimensional MATLAB array with a length less than or equal to the number of words. M4K. From HEX file. M144K Specify the number of bits stored on the left side of the binary point. MLAB.9–22 Chapter 9: Storage Library Single-Port RAM Use the Quartus II software to generate a . Address bus. Specify the array from the MATLAB work-space or directly in the MATLAB Array box. the RAM is always initialized to unknown in the hardware and simultaneous read/writes to the same address also give unknown in hardware. Table 9–33. f For instructions on creating this file. The input data type format. Write enable. you should set the output bit width to the same as that in the . Some memory types are not available for all device types. A warning issues if you specify a non-standard . Single-Port RAM Block Parameters (Part 1 of 2) Name Number of words Data Type Value >= 1 (Parameterizable) Inferred. The Quartus II software does allow you to create non-standard . Initialization Blank. Single-Port RAM Block Inputs and Outputs Signal d addr wren ena q_a Direction Input Input Input Input Output Input data port. Signed Fractional Description Specify the address width in words. This option applies only to signed fractional formats. If Blank is selected. refer to Creating a Memory Initialization File or Hexadecimal (Intel-Format) File in the Quartus II Help. The unknowns are not modeled in Simulink. the contents of the RAM are pre-initialized to zero. Description Table 9–34 shows the Single-Port RAM block parameters.hex file that must be in your DSP Builder working directory. Thus. DSP Builder supports 32-bit addressing with extended linear address records in the .hex file.

hex file that must be in your DSP Builder working directory. that is. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism. Single-Port RAM Block I/O Formats (Note 1) I/O I Simulink (2). Single-Port RAM Block Parameters (Part 2 of 2) Name Input HEX File Value User defined Description Specify the name of a . the MSB is the sign bit. To specify the bus format of an implicit input port. where a 1 indicates the phase in which the block is enabled. and 4 do not pass through the delay block. That is.[0] I3[1] I4[1] O O1[L1].[R] is an output port.[0]. For example: input.1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 .hex.1} DOWNTO 0) Type (4) Explicit Explicit © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . O1[L].[R] is an input port. (3) I1[L]. [1] is a single bit. For example: [0:1:15] Turn on to register the output port. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. (3) I1[L1]. that is. the data on phases 1.hex file. VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). For signed or unsigned integers R = 0. Table 9–35 shows the Single-Port RAM block I/O formats.Chapter 9: Storage Library Single-Port RAM 9–23 Table 9–34. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. [L]. (4) Explicit means that the port bit width information is a block parameter. MATLAB Array Register output Port Use Enable Port Clock Phase Selection User defined (Parameterizable) On or Off On or Off User Defined Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. [R] is the number of bits on the right side of the binary point.[R1] Notes to Table 9–12: (1) For signed integers and signed binary fractional numbers. Turn on to use the optional clock enable input (ena).[R1] I2[L2]. R = 0. For single bits. 3. Table 9–35. Specify the phase selection with a binary string. DSP Builder supports 32-bit addressing with extended linear address records in the . (2) [L] is the number of bits on the left side of the binary point.1} DOWNTO 0) I3: in STD_LOGIC I4: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 . use a Bus Conversion block to set the width.

Two read and two write ports allow true dual access. DSP Builder supports 32-bit addressing with extended linear address records in the . If you require a different bit width. refer to the Read-During-Write Output Behavior section in the RAM Megafunction User Guide. The contents of the RAM are pre-initialized to zero by default. in the case of MLAB implementation. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Thus. Single-Port RAM Block Example True Dual-Port RAM The True Dual-Port RAM block maps data to an embedded RAM (embedded array block. Use the Quartus II software to generate a .hex) file or from a MATLAB array to specify them. especially if the memory implements as a MLAB. the output is not double-registered (and therefore.hex file but use an AltBus block to convert to the required bit width.hex files but pads 1's to the front for negative numbers to make them multiples of eight. large numbers with less bits may be treated as negative numbers. ESB) in Altera devices. The input port is always registered and the output port can optionally be registered. The MATLAB array parameter must be a one dimensional MATLAB array with a length less than or equal to the number of words. refer to Creating a Memory Initialization File or Hexadecimal (Intel-Format) File in the Quartus II Help. and you gain an extra half-cycle on the output. Figure 9–12.hex file is formatted in multiples of eight and the output bit width should also be in multiples of eight.hex file. f For instructions on creating this file.hex file that must be in your DSP Builder working directory. Use an Intel Hexadecimal (. you should set the output bit width to the same as that in the .hex file. or embedded system block. EAB. The True Dual-Port RAM block accepts any data type as input. A warning issues if you specify a non-standard . The Quartus II software does allow you to create non-standard . Specify the array from the MATLAB workspace or directly in the MATLAB Array box.9–24 Chapter 9: Storage Library True Dual-Port RAM Figure 9–12 shows an example with the Single-Port RAM block. which outputs old data for read-during-write. f For more information about this option. The default is off. uses fewer external registers). When this option is on. Turning on the DONT_CARE option may give a higher fMAX for your design. The data in a standard .

" If this data is read. Table 9–36. Specify the number of bits to the right of the binary point. True Dual-Port RAM Block Parameters (Part 1 of 2) Name Number of words Data Type Value >= 1 (Parameterizable) Inferred.[] []. the data at this address is set to zero. True Dual-Port RAM Block Inputs and Outputs Signal data_a addr_a wren_a data_b addr_b wren_b ena q_a q_b Direction Input Input Input Input Input Input Input Output Output Input data port a Address bus a. In DSP Builder simulation. In ModelSim simulations. Unsigned Integer. Memory contents at this address will be Unknown (X) in hardware. Signed Fractional >= 0 (Parameterizable) >= 0 (Parameterizable) Description Specify the address width in words. The clock enable signal (ena) bypasses any output register. Table 9–37.Chapter 9: Storage Library True Dual-Port RAM 9–25 The input address bus must be Unsigned. the data written to the RAM is indeterminate (corrupt). Signed Integer. Table 9–36 shows the True Dual-Port RAM block inputs and outputs. This option applies only to signed fractional formats. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Memory contents at this address will be Unknown (X) in hardware. Write enable a Input data port b Address bus b Write enable b Optional clock enable port Output data port a Output data port b Description Table 9–37 shows the True Dual-Port RAM block parameters.[number of bits] Specify the number of bits stored on the left side of the binary point. you may get simulation mismatches if you are making use of corrupt data in your design or outputting the read memory contents to a pin. and a warning is given: "Warning: True Dual-Port RAM: simultaneous a and b side writing to address <addr>." If you execute a testbench comparison to hardware. [number of bits]. c If you write to the same address simultaneously with the a and b inputs. The input data type format. DSP Builder warns that you are reading corrupt data: "Warning: True Dual-Port RAM: <a|b>-side reading corrupt RAM data at address <addr>. the data at this address is set to Unknown (all bits X).

but a warning message issues on every simultaneous read/write to the same address. For example: input. From MATLAB array User defined DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . the output in hardware when reading from and writing to the same address is unpredictable. If you compare the simulation results to ModelSim. M4K. From HEX file. where a 1 indicates the phase in which the block is enabled. the data on phases 1. setting DONT_CARE gives more flexibility in RAM block placement. ensure that the same address is not read from and written to at the same time or that your design does not depend on the read output in these circumstances. M512. and the resulting memory block can often be run at a higher fMax. unknowns (X) are output when reading from and writing to the same address. you see mismatches associated with any read/write to the same address events. Specify the name of an . For example: 1—The block is always enabled and captures all data passing through the block (sampled at the rate 1). Specify the initialization. If the implementation is set to MLAB. 10—The block is enabled every other phase and every other data (sampled at the rate 1) passes through. In ModelSim simulation. However. MLAB.hex. the contents of the RAM are pre-initialized to zero. and comparisons with ModelSim shows differences. The Simulink simulation is unchanged whether or not you use this option. True Dual-Port RAM Block Parameters (Part 2 of 2) Name Memory Block Type Value AUTO. Use DONT_CARE when reading from and writing to the same address On or Off Initialization Input HEX File Blank. When this option is set. For example: [0:1:15] Turn on to register the output ports. the RAM is always initialized to unknown in the hardware and simultaneous read/writes to the same address give unknown in hardware. If you specify M-RAM. the design uses fewer external registers. If Blank is selected.hex file. Some memory types are not available for all device types. M-RAM. By default this option is off. Turn on to use the optional clock enable input (ena). M144K Description The FPGA RAM memory block type. The unknowns are not modeled in Simulink. and data is always read before write. because the output is not double registered.9–26 Chapter 9: Storage Library True Dual-Port RAM Table 9–37. If the memory block type is set to AUTO. M9K. That is. DSP Builder supports 32-bit addressing with extended linear address records in the . 3. MATLAB Array Register output Ports Use Enable Port Clock Phase Selection User defined (Parameterizable) On or Off On or Off User Defined Specify a one-dimensional MATLAB array with a length less than or equal to the number of words. Specify the phase selection with a binary string. and 4 do not pass through the block. 0100—The block is enabled on the second phase of and only the second data of (sampled at the rate 1) passes through. which must be in your DSP Builder working directory.hex file.

1} DOWNTO 0) Explicit Figure 9–13 shows an example with the True Dual-Port RAM block. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.[R] is an output port. For single bits. Figure 9–13.[0] I3[L2]. use a Bus Conversion block to set the width. R = 0. For signed or unsigned integers R = 0. [L]. True Dual-Port RAM Block I/O Formats I/O I Simulink (2).[R1] Notes to Table 9–12: (1) For signed integers and signed binary fractional numbers. Table 9–38.[0] I7[1] I8[1] O O1[L1].1} DOWNTO 0) I3: in STD_LOGIC_VECTOR({L3 . that is. (Note 1) VHDL Type (4) Explicit I1: in STD_LOGIC_VECTOR({L1 + R1 .[0] I4[L1].Chapter 9: Storage Library True Dual-Port RAM 9–27 Table 9–38 shows the True Dual-Port RAM block I/O formats.[R1] I5[L2]. (3) I1[L]. [R] is the number of bits on the right side of the binary point.[0]. (3) I1[L1]. (2) [L] is the number of bits on the left side of the binary point.1} DOWNTO 0) I4: in STD_LOGIC_VECTOR({L4 + R4 . that is. the MSB is the sign bit.1} DOWNTO 0) I2: in STD_LOGIC_VECTOR({L2 .1} DOWNTO 0) I6: in STD_LOGIC_VECTOR({L6 .[0] I6[L2]. O1[L].[R] is an input port.[R1] I2[L2]. (4) Explicit means that the port bit width information is a block parameter.1} DOWNTO 0) I7: in STD_LOGIC I8: in STD_LOGIC O1: out STD_LOGIC_VECTOR({L1 + R1 . [1] is a single bit.1} DOWNTO 0) I5: in STD_LOGIC_VECTOR({L5 . To specify the bus format of an implicit input port. True Dual-Port RAM Block Example © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .

Table 9–41.9–28 Chapter 9: Storage Library Up Sampling Up Sampling The Up Sampling block increases the output sample rate from the input sample rate. (2) [L] is the number of bits on the left side of the binary point. Up Sampling Rate An integer greater than 1 (Parameterizable) Table 9–41 shows the Up Sampling block I/O formats. then for the next N-1 cycles the output is zero. [R] is the number of bits on the right side of the binary point. Up Sampling Block Parameter Name Value Description Specify the up sampling rate. (4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath bit width propagation mechanism.[R1] O1[L1]. (3) I1[L1].[R1] (Note 1) VHDL I1: in STD_LOGIC_VECTOR({L1 + R1 . R = 0. the MSB is the sign bit. Output data port.[0]. For single bits. Figure 9–14.1} DOWNTO 0) O1: in STD_LOGIC_VECTOR({L1 + R1 . The output data is sampled every N cycles where N is equal to the up sampling rate. Table 9–39 shows the Up Sampling block inputs and outputs. O1[L]. that is. [L]. Table 9–40.1} DOWNTO 0) Type (4) Implicit Implicit Notes to Table 9–41: (1) For signed integers and signed binary fractional numbers. To specify the bus format of an implicit input port.[R] is an input port. For signed or unsigned integers R = 0. Description Table 9–40 shows the Up Sampling block parameter. [1] is a single bit. (3) I1[L]. The output holds this value for 1 cycle. Up Sampling Block Inputs and Outputs Signal d q Direction Input Output Input data port. Up Sampling Block Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Up Sampling Block I/O Formats I/O I O Simulink (2). use a Bus Conversion block to set the width.[R] is an output port. that is. Table 9–39. Figure 9–14 shows an example with the Up Sampling block.

10. Off On. A state machine is a very efficient means to specify complex control logic that you can then use to generate a HDL description and Simulink interface to the simulation model. Turn on to uses an active-high reset or off if you want an active-low reset. You can define a state machine graphically by adding states and transitions directly on the diagram. State Machine Wizard Parameters Name Which reset mode do you want to use Reset is active-high Register the output ports Value Synchronous. Asynchronous On. a graphical state diagram view is created with the states and transitions automatically placed for optimum readability. Figure 10–1. State Machine Functions Library The State Machine Functions library contains the following blocks: ■ ■ State Machine Editor State Machine Table State Machine Editor The State Machine Editor block provides access to the Quartus® II state machine editor. Off Description Specifies whether the state machine has a synchronous or asynchronous reset. Default State Machine Diagram View Table 10–1 shows the parameters that you can e set in the State Machine wizard. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . When you use the wizard interface. Table 10–1. which allows you to create graphic representations of state machines for use in your design. Turn on to register the state machine output ports. or by using a wizard interface to enter all the properties for the state machine. Figure 10–1 shows the state machine that is created when you use the default options in the wizard.

the generated HDL is compiled in the Quartus II software and the ports updated on the block in your Simulink model. Transition to source On. The syntax of each conditional statement is automatically checked on entry and the completed state machine is validated when you generate HDL to ensure that the state machine is functionally correct. State Machine Wizard Parameters Name States Input ports State transitions Value user specified user specified user specified Description You can specify any number of state names that must be valid HDL identifiers.. Off state if not specified Output ports Action conditions user specified user specified Use Verilog HDL syntax to specify the conditional statements that you specify for state transitions and output actions. which you can select from a drop down list in the wizard. Table 10–2 shows the operators you can use to define a conditional expression. f For more information including procedures for drawing a graphical state machine. a condition that causes a transition to take place. You can specify actions assigned to each output port. The state machine description is saved in a <block name>. Table 10–2.) == != > >= < <= & | Negative Brackets Numeric equality Not equal to Greater than Greater than or equal to Less than Less than or equal to AND OR Description 1 1 2 2 2 2 2 2 2 2 Priority ~in1 (1) in1==5 in1!=5 in1>in2 in1>=in2 in1<in2 in1<=in2 (in1==in2)&(in3>=4) (in1==in2)|(in1>in2) Example A conditional statement consists of a source state. State Machine Editor Operators Operator ~ (unary) (.smf file when you close the state machine wizard. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Turn on to always transition to the source state if not all transition conditions are specified. You can specify any number of conditional statements for the transitions between source and destination states. The source state and destination state values must be valid state names. When you exit from the State Machine Editor. and the destination state to which the state machine transitions..10–2 Chapter 10: State Machine Functions Library State Machine Editor Table 10–1. You can specify any number of output port names that must be valid HDL identifiers. You can specify any number of input port names that must be valid HDL identifiers. refer to the About the State Machine Editor topic in the Quartus II Help. Figure 10–2 shows an example of the default state machine that the State Machine Editor wizard creates and includes in a simple Simulink model.

Each state is represented by an output. Example With the State Machine Editor Block f For more information. In VHDL. an output is assigned a logic level 1 if its respective state is equal to the current state. refer to the Using the State Machine Editor Block chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. The inputs and outputs are represented as integers in Simulink. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . While the state machine is operating. Figure 10–3. 1 The State Machine Table block is not available on Linux and is deprecated on Windows. Moore Style State Machine The default state machine has five inputs and five states. the input and output are represented as standard logic vectors. All other outputs are assigned a logic level 0.Chapter 10: State Machine Functions Library State Machine Table 10–3 Figure 10–2. State Machine Table The State Machine Table block represents a one-hot Moore-style state machine where the output is equal to the current state (Figure 10–3). Use the State Machine Editor block in new designs.

Table 10–4.10–4 Chapter 10: State Machine Functions Library State Machine Table Figure 10–4 shows the default State Machine Table symbol . You cannot delete an input or state that the design uses in a conditional statement.. Deletes the selected input name. and conditional statements. state name or conditional statement. state name.(unary) (. or conditional statement to the table. You can change the reset state but you cannot delete or change the name of the reset state. Table 10–3 shows the controls available in the State Machine Builder dialog box. Table 10–3. states. This option is available in the States tab and allows you to specify the reset state from a list of specified state names. You cannot change an input name or state name that the design uses in a conditional statement. Available in the Conditional Statements tab and allows you to change the transition priority when there is more than one condition leaving a state by moving the conditional statement up or down the list. State Machine Table Operators Operator . Delete Reset State — state name Move Up Move Down Analyze — — Table 10–4 shows the operators that you can use to define a conditional expression. which control the transitions between the states. Figure 10–4. State Transition Table Block Controls Name Add Change Value — — Description Adds the specified input name. Do not use this option in the Inputs tab.. Allows you to change the selected state name or conditional statement. Available in the Design Rule Check tab to validate your state machine table.) = != > >= < <= & | Negative Brackets Numeric equality Not equal to Greater than Greater than or equal to Less than Less than or equal to AND OR Description 1 1 2 2 2 2 2 2 2 2 Priority -1 (1) in1=5 in1!=5 in1>in2 in1>=in2 in1<in2 in1<=in2 (in1=in2)&(in3>=4) (in1=in2)|(in1>in2) Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Default State Machine Table Block The State Machine Builder dialog box allows you to specify the inputs.

You may experience problems when using very large input signals (greater than 225). Design Rule Checks The Analyze button in the Design Rule Checks tab of the State Machine Builder dialog box performs the following checks: ■ ■ ■ ■ At least two states must be defined At least two conditional statements must be defined All input port names must be unique All state names must be unique © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . specify the conditional expression to be one. a condition that causes a transition to take place. Specify at least one transition for each state. The current state and next state values must be state names defined in the States tab. 1 To indicate in a conditional statement that a state machine always transitions from the current state to the next state. which you can select from drop down list in the dialog box. the expression strings for the port names are replaced by signals named <port name>_sig.Chapter 10: State Machine Functions Library State Machine Table 10–5 A conditional statement consists of a current state. the block does not generate legal VHDL. Figure 10–5. Simple State Transition Table 1 When VHDL generates. Figure 10–5 shows the dialog box that specifies a simple state transition table with the default inputs and states. and the next state to which the state machine transitions. Otherwise.

Figure 10–6.10–6 Chapter 10: State Machine Functions Library State Machine Table ■ ■ ■ ■ A single reset state must exist A reset input port must exist All current state and next state values must be valid All conditional statements must be syntactically correct Figure 10–6 shows an example with the State Machine Table block as a FIFO controller. refer to the Using the State Machine Table Block chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Example With the State Machine Table Block f For more information.

you do not need to make pin assignments to connect the board components.11. PLL Output Clocks You can manually add PLL blocks to your design and configure them to provide the required output clocks with the Quartus II Pinout Assignments block to assign pin locations to the PLL outputs. you can solve design problems that formerly required custom hardware and software solutions. It also displays details of the hardware device on the board. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . your design must contain the corresponding board configuration block at the top hierarchical level. connectors. 7-segment displays. analog-to-digital converters (ADC). When combined with DSP intellectual property (IP) from Altera or from the Altera Megafunction Partners Program (AMPPSM). push buttons. Board Configuration When targeting a development board. Boards Library The Boards library supports DSP development platforms for the following prototyping boards: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Cyclone II DE2 Board Cyclone II EP2C35 DSP Board Cyclone II EP2C70 DSP Board Cyclone III EP3C25 Starter Board Cyclone III EP3C120 DSP Board Stratix EP1S25 DSP Board Stratix EP1S80 DSP Board Stratix II EP2S60 DSP Board Stratix II EP2S180 DSP Board Stratix II EP2S90GX PCI Express Board Stratix III EP3SL150 DSP Board These development boards provide an economical solution for hardware and software verification that enables you to debug and verify both functionality and design timing. The other blocks available for each board provide connections to the controls on each board such as LEDs. The configuration block properties allow you to specify from a list of available pins to use for the clock and global reset connections. and digital-to-analog converters (DAC). switches. By using these blocks.

You can optionally specify the clock signal. Controls eighteen user-definable active-low toggle switches. Figure 11–2 shows the design example for the Cyclone II DE2 board. Control eight simple user-definable seven-segment LED displays. refer to Altera’s Development and Education Board on the Altera website. You can optionally specify the clock signal. You can optionally specify Input or Output node type. Table 11–1 lists the blocks available to support the Cyclone II DE2 board. and specify the pin location for each connector.11–2 Chapter 11: Boards Library Cyclone II DE2 Board ADC Control Signals The ADC control signals are not automatically assigned on the Cyclone II EP2C35 DSP Board or the Cyclone II EP2C70 DSP Board. Figure 11–1 shows how to use VCC and GND blocks to set the signal levels for the Cyclone II EP2C35 DSP Board. Two Santa Cruz connectors. ADC Reset Pin Assignments Cyclone II DE2 Board The Cyclone II DE2 development and education board provides a complete. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . you must make manual assignments with Quartus II Pinout Assignments blocks. ready-to-teach platform based on the Altera Cyclone II 2C35 device for use in courses on logic design and computer organization. Table 11–1. Cyclone II DE2 Board Blocks Block LED0–LED17 LEDG0–LEDG8 PB0–PB3 Description Controls eighteen red user-definable LEDs. For these boards. which control the prototyping area I/O. Controls nine green user-definable LEDs. Figure 11–1. PROTO and PROTO1 Display0-Display7 SW0–SW17 f For detailed information about the Cyclone II DE2 board. Controls four user-definable active-low push buttons. specify the input clock signal.

Controls eight user-definable LEDs (D2–D9). Controls the user-definable dual in-line package switch (S1). Table 11–2. You can optionally specify Input or Output node type. You can optionally specify the clock signal. J23). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Controls the 14-bit unsigned digital-to-analog converter (U25). Table 11–2 lists the blocks available to support the Cyclone II EP2C35 DSP board. You can optionally specify the clock signal. which control the prototyping area I/O. J22. specify the input clock signal. Santa Cruz connectors.Chapter 11: Boards Library Cyclone II EP2C35 DSP Board 11–3 Figure 11–2. and specify the pin location for each connector (J15. Cyclone II EP2C35 DSP Board Blocks (Part 1 of 2) Block A2D_1 D2A_1 Dip Switch LED0–LED7 PROTO and PROTO1 Description Controls the 12-bit signed analog-to-digital converter (U26). Design Example for the Cyclone II DE2 Board Cyclone II EP2C35 DSP Board The Cyclone II EP2C35 DSP board provides a low-cost hardware platform for developing high performance DSP designs based on Altera Cyclone II FPGA devices.

DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . refer to the Cyclone II DSP Development Board Reference Manual. SW2–SW5. f For information about setting up the board. and user reset USER_RESETN push-button SW6). You can optionally specify the clock signal. Controls four user-definable push-button switches (SW2–SW5. which has two 14-bit analog-to-digital converters and two 14-bit digital-to-analog converters. Figure 11–3. Cyclone II EP2C35 DSP Board Blocks (Part 2 of 2) Block Display0 and Display1 Description Controls two simple user-definable seven-segment LED displays (U32.11–4 Chapter 11: Boards Library Cyclone II EP2C70 DSP Board Table 11–2. For information about supported hardware features. refer to the DSP Development Kit. U33). Cyclone II Getting Started User Guide. Design Example for the Cyclone II EP2C35 DSP Board Cyclone II EP2C70 DSP Board The Cyclone II EP2C70 DSP board is an enhanced version of the EP2C35 board. Table 11–3 lists the blocks available to support the Cyclone II EP2C70 DSP board. Figure 11–3 shows the design example for the Cyclone II EP2C35 DSP board.

Controls four user-definable push-button switches (SW2–SW5. refer to the DSP Development Kit. USER_RESETN Description Controls the 14-bit signed analog-to-digital converters. Controls eight user-definable LEDs (D2–D9). which control the prototyping area I/O. f For information about setting up the board. Design Example for the Cyclone II EP2C70 DSP Board © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . J22. You can optionally specify the clock signal. Controls the user-definable dual in-line package switch (S1). J23). Figure 11–4 shows the design example for the Cyclone II EP2C70 DSP board. U33). Santa Cruz connectors. You can optionally specify Input or Output node type. Controls two simple user-definable seven-segment LED displays (U32. Figure 11–4. You can optionally specify the clock signal. For information about supported hardware features. specify the input clock signal.Chapter 11: Boards Library Cyclone II EP2C70 DSP Board 11–5 Table 11–3. Cyclone II EP2C70 DSP Board Blocks Block A2D_1 and A2D_2 D2A_1 and D2A_2 Dip Switch LED0–LED7 PROTO and PROTO1 Display0 and Display1 SW2–SW5. Cyclone II Getting Started User Guide. and specify the pin location for each connector (J15. refer to the Cyclone II DSP Development Board Reference Manual. You can optionally specify the clock signal. and the user reset push-button SW6). Controls the 14-bit unsigned digital-to-analog converters.

Controls four user-definable push-button switches and the user reset push button. low-power Altera Cyclone III device. Table 11–5 lists the blocks available to support the Cyclone III EP3C120 DSP board.11–6 Chapter 11: Boards Library Cyclone III EP3C25 Starter Board Cyclone III EP3C25 Starter Board The Cyclone III EP3C25 starter board is a hardware platform that you can customize with optional expansion connectors and daughtercards to evaluate the feature rich. USER_RESETN Controls four user-definable LEDs. Cyclone III EP3C25 Starter Board Blocks Block LED1–LED4 SW1–SW4. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Table 11–4. Figure 11–5. refer to the Cyclone III FPGA Starter Board Reference Manual. Figure 11–5 shows the design example for the Cyclone III EP3C25 starter board. refer to the Cyclone III FPGA Starter Kit User Guide. high-volume. feature-rich designs that demonstrate the Cyclone III device’s on-chip memory. For information about supported hardware features. Design Example for the Cyclone III EP3C25 Starter Board Cyclone III EP3C120 DSP Board The Cyclone III EP3C120 DSP board provides a hardware platform for developing and prototyping low-power. You can optionally specify the clock signal. Description f For information about setting up the board. and the Nios® II embedded soft processor. embedded multipliers. Table 11–4 lists the blocks available to support the Cyclone III EP3C25 starter board.

You can optionally specify the clock signal. CPU_RESETN Controls the 14-bit unsigned digital-to-analog converters on the optional high speed mezzanine cards (HSMC). A2D_1_HSMC_B. refer to the Cyclone III Development Board. You can optionally specify the clock signal. Cyclone III EP3C120 DSP Board Blocks Block Display0 A2D_1_HSMC_A.mdl: This design tests the 7-segment display on the main development board. Controls the user-definable dual in-line package switch (SW6). Test3C120Board_HSMA. A2D_2_HSMC_B D2A_1_HSMC_A.mdl: This design tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port B. Test3C120Board_HSMB. Test3C120Board_QuadDisplay. D2A_2_HSMC_A.Chapter 11: Boards Library Cyclone III EP3C120 DSP Board 11–7 Table 11–5. Controls four user-definable push-button switches (S1–S4) and the CPU reset push-button (S5). Description User defined 4-digit seven-segment LED display (U30). Controls eight user-definable LEDs (D26–D33). ■ ■ ■ Figure 11–6 shows the test design for the LEDs and push buttons. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .mdl: This design tests the LEDs and push-button switches on the main development board. f For information about setting up the board. D2A_2_HSMC_B Dip Switch LED0–LED7 PB0–PB3. Reference Manual. There are four design examples for the Cyclone III EP3C120 DSP board: ■ Test3C120Board_Leds. You can optionally specify the clock signal.mdl: This design tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port A. and supported hardware features. A2D_2_HSMC_A. Controls 14-bit signed analog-to-digital converters on the optional high speed mezzanine cards (HSMC). D2A_1_HSMC_B.

Figure 11–7. 7-Segment Display Design Example for the Cyclone III EP3C120 DSP Board Blocks Figure 11–8 shows the test design for a high speed mezzanine card. LED and Push-button Design Example for the Cyclone III EP3C120 DSP Board Blocks Figure 11–7 shows the test design for the 7-segment display. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .11–8 Chapter 11: Boards Library Cyclone III EP3C120 DSP Board Figure 11–6.

Assign signals to the SPI bus interface signals for the chip in static mode (ADA_SPI_CSB and ADA_SPI_CSB) and tie them to VCC. Setting Up the Mezzanine Card Test Designs The required pin and clock assignments are already set up in the design examples. If necessary.Chapter 11: Boards Library Cyclone III EP3C120 DSP Board 11–9 Figure 11–8. HSMC Design Example for the Cyclone III EP3C120 DSP Board Blocks 1 Figure 11–8 shows the test design for the daughtercard connected to HSMC port A. When these signal are pulled high. Assign signals to the output enable pins for both channels of the analog-to-digital converters (A2D1_OEB and A2D2_OEB) and tie them to GND. 2. you can set up your own test design as follows: 1. 3. The test design for the daughtercard connected to HSMC port B is very similar. set the following signals: AD_SCLK: ■ ■ High: Two’s complement output (for FIR or similar) Low: Straight binary from near midrange AD_SDIO: ■ ■ High: Duty cycle stabilizer (DCS) enabled to lower jitter Low: DSC disabled © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . The following Quartus II Global project assignments must be set with the value “Use AS REGULAR I/O”: ■ ■ ■ RESERVE_DATA1_AFTER_CONFIGURATION CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION RESERVE_DCLK_AFTER_CONFIGURATION These assignments enable you to use the programmer pins as I/O.

11–10 Chapter 11: Boards Library Cyclone III EP3C120 DSP Board 4.) Turn on Create ‘locked’ output. Add a Subsystem Builder block to your model.) Figure 11–10. Add two additional output clocks with 180 and 270 degrees phase shift from the input clock (c1 and c2) and clock multiplication factor of 2. Create a new block design file (for example. Assign appropriate pin assignments for the four output clocks on the test design model (Figure 11–10. (Turn off areset. pclk1p. pll_clkout. Figure 11–9 shows the completed block design file. c. pclk0n. b. b.bdf) and use the MegaWizard™ Plug-in Manager to add an ALTPLL megafunction. Open the subsystem (pll_clkout) and remove the default input port. 5.bdf file. PLL Subsystem DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Click Create HDL File for Current File on the File menu. Configured PLL in the Quartus II Block Design Editor c. 1 Each output clock is negated in the block editor to produce a the signals pclk0p. Specify the clock name (such as clkin_50) in the block parameters for the HDL Entity block. Double-click on the block and browse for the HDL file created in step 4c then click Build to create the subsystem. Figure 11–9. Import the PLL into the test design model: a. Open a Quartus II project and configure a PLL to produce the required output clocks: a. This name should match the clock name in the . and pclk1n. Configure the PLL with a 50MHz input clock (inclk0) and no other optional inputs.

You can optionally specify the clock signal for RS232 TIN. J21. Controls a dual user-definable seven-segment LED display (D4). © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . and features the Stratix EP1S25 device in the speed grade (-5) 780-pin package. Stratix & Stratix Professional Edition Getting Started User Guide. JP19. U23) Mictor connectors. Table 11–6. which control debugging ports A and B. refer to the DSP Development Kit.Chapter 11: Boards Library Stratix EP1S25 DSP Board 11–11 Stratix EP1S25 DSP Board The Stratix EP1S25 DSP board is a powerful development platform for digital signal processing (DSP) designs. Figure 11–11 shows the design example for the Stratix EP1S25 DSP board. For information about the supported hardware features. Controls the evaluation inputs and outputs. and specify the pin locations (J20. U30). Expansion connector. Controls the user-definable dual in-line package switch (SW3). RS232 ROUT and RS232 TIN Display0 and Display1 SW0–SW2 f For information about setting up the board. J24). JP20. Table 11–6 lists the blocks available to support the Stratix EP1S25 DSP board. You can optionally specify Input or Output node type. Controls two user-definable LEDs (D6. JP21. You can optionally specify Input or Output node type. JP24. Controls the RS232 serial receive output and transmit input (J8). J10). Controls the 14-bit unsigned digital-to-analog converters (U21. JP8). which controls the prototyping area I/O. specify the input clock signal. D7). and specify the pin location for each port (J9. JP22. You can optionally specify the clock signal. refer to the Stratix EP1S25 DSP Development Board Data Sheet. You can optionally specify the input clock signal for EVAL IO IN and specify the pin location for each input or output (JP7. specify the input clock signal. You can optionally specify the clock signal. Controls three user-definable push-button switches (SW0–SW2). Stratix EP1S25 DSP Board Blocks Block A2D_1 and A2D_2 D2A_1 and D2A_2 DEBUGA and DEBUGB Dip Switch EVAL IO IN and EVAL IO OUT LED0 and LED1 PROTO Description Controls the 12-bit signed analog-to-digital converters (U10. You can optionally specify the clock signal.

Design Example for the Stratix EP1S25 DSP Board DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .11–12 Chapter 11: Boards Library Stratix EP1S25 DSP Board Figure 11–11.

You can optionally specify the clock signal. Controls three user-definable push-button switches (SW0–SW2). Table 11–7 lists the blocks available to support the Stratix EP1S80 DSP board. Controls the RS232 serial receive output and transmit input (J8). You can optionally specify the clock signal for EVAL IO IN and specify the pin location for each input or output (JP7. You can optionally specify the clock signal. U23) Mictor connectors. Stratix & Stratix Professional Edition Getting Started User Guide.Chapter 11: Boards Library Stratix EP1S80 DSP Board 11–13 Stratix EP1S80 DSP Board The Stratix EP1S80 DSP board is a powerful development platform for digital signal processing (DSP) designs. which control debugging ports A and B. which controls the prototyping area I/O. JP19. Figure 11–12 shows the design example for the Stratix EP1S80 DSP board. Expansion connector. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . U30). Controls the user-definable dual in-line package switch (SW3). Stratix EP1S80 DSP Board Blocks Block A2D_1 and A2D_2 D2A_1 and D2A_2 DEBUGA and DEBUGB Dip Switch EVAL IO IN and EVAL IO OUT LED0 and LED1 PROTO Description Controls the 12-bit signed analog-to-digital converters (U10. D7). For information about the supported hardware features. refer to the Stratix EP1S80 DSP Development Board Data Sheet. Controls two user-definable LEDs (D6. JP21. J21. and specify the pin locations (J20. JP20. JP22. specify the input clock signal. Controls a dual user-definable seven-segment LED display (D4). Table 11–7. JP24. You can optionally specify the clock signal. You can optionally specify Input or Output node type. and specify the pin location for each port (J9. You can optionally specify the clock signal for RS232 TIN. J10). J24). RS232 ROUT and RS232 TIN Display0 and Display1 SW0–SW2 f For information about setting up the board. Controls the 14-bit unsigned digital-to-analog converters (U21. specify the input clock signal. JP8). refer to the DSP Development Kit. Controls the evaluation input and outputs. You can optionally specify Input or Output node type. and features the Stratix EP1S80 device in the speed grade (-6) 956-pin package.

You can optionally specify the clock signal. You can optionally specify Input or Output node type. Santa Cruz connectors. Table 11–8 lists the blocks available to support the Stratix EP2S60 DSP board. U15) Controls the board reset push-button switch (SW8). 1 The Stratix II EP2S60 DSP board supports alternative EP2S60F1020C4 and EP2S60F1020C4ES devices. You can optionally specify the clock signal. Design Example for the Stratix EP1S80 DSP Board Stratix II EP2S60 DSP Board The Stratix II EP2S60 DSP board is a development platform for high-performance digital signal processing (DSP) designs. which controls the prototyping area I/O. and features the Stratix II EP2S60 device in a 1020-pin package. which you can select in the configuration block properties. LED0–LED7 PROTO and PROTO1 DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . J26–J28). Stratix EP2S60 DSP Board Blocks (Part 1 of 2) Block A2D_1 and A2D_2 D2A_1 and D2A_2 IO_DEV_CLRn Description Controls the 12-bit signed analog-to-digital converters (U1. Controls the 14-bit unsigned digital-to-analog converters (U14. U2). Table 11–8. specify the input clock signal. and specify the pin locations (J23– J25.11–14 Chapter 11: Boards Library Stratix II EP2S60 DSP Board Figure 11–12. Controls eight user-definable LEDs (D1–D8).

Chapter 11: Boards Library Stratix II EP2S180 DSP Board 11–15 Table 11–8. refer to the Stratix II DSP Development Board Reference Manual. PROTO3 Display0 and Display1 SW4–SW7 f For information about setting up the board. You can optionally specify the clock signal. Stratix EP2S60 DSP Board Blocks (Part 2 of 2) Block PROTO2 Description Mictor connector. specify the input clock signal. specify the input clock signal. Figure 11–13. J6). Controls four user-definable push-button switches (SW4–SW7). You can optionally specify Input or Output node type. Controls a dual user-definable seven-segment LED display (U12. which controls the debugging port. refer to the DSP Development Kit Getting Started User Guide. Table 11–9 lists the blocks available to support the Stratix EP2S180 DSP board. and specify the pin location for each port (J20). External analog-to-digital converter interface connector. Design Example for the Stratix II EP2S60 DSP Board Stratix II EP2S180 DSP Board The Stratix II EP2S180 DSP board is a development platform for high-performance digital signal processing (DSP) designs. and specify the pin location for each port (J5. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . You can optionally specify Input or Output node type. For information about the supported hardware features. and features the Stratix II EP2S180 device in a 1020-pin package. Figure 11–13 shows a test design with the SignalTap II and EP2S60 DSP board blocks. The 7-segment display and LEDs on the board respond to user-controlled switches and the value of the incrementer. U13).

LED0–LED7 PROTO and PROTO1 PROTO2 PROTO3 Display0 and Display1 SW4–SW7 f For information about setting up the board. Santa Cruz connectors. which controls the prototyping area I/O. For information about the supported hardware features. External analog-to-digital converter interface connector. You can optionally specify Input or Output node type. You can optionally specify Input or Output node type. Controls four user-definable push-button switches (SW4–SW7). You can optionally specify the clock signal. You can optionally specify Input or Output node type. Controls eight user-definable LEDs (D1–D8). U15) Controls the board reset push-button switch (SW8). J6). J26–J28). Controls a dual user-definable seven-segment LED display (U12. and specify the pin location for each port (J5. and specify the pin location for each port (J20). Stratix EP2S180 DSP Board Blocks Block A2D_1 and A2D_2 D2A_1 and D2A_2 IO_DEV_CLRn Description Controls the 12-bit signed analog-to-digital converters (U1.11–16 Chapter 11: Boards Library Stratix II EP2S180 DSP Board Table 11–9. U13). refer to the Stratix II EP2S180 DSP Development Board Reference Manual. specify the input clock signal. You can optionally specify the clock signal. which controls the debugging port. specify the input clock signal. Controls the 14-bit unsigned digital-to-analog converters (U14. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . specify the input clock signal. refer to the DSP Development Kit Getting Started User Guide. Figure 11–14 shows the design example for the Stratix II EP2S180 DSP board. and specify the pin locations (J23– J25. Mictor connector. The 7-segment display and LEDs on the board respond to user-controlled switches and the value of the incrementer. U2). You can optionally specify the clock signal.

Getting Started User Guide. Figure 11–15 shows the design example for the Stratix II EP2S90GX PCI Express board. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . You can optionally specify the clock signal. Controls three user-definable push-button switches (S2–S4). Reference Manual. Stratix II GX Edition. For information about the supported hardware features. f For information about setting up the board. You can optionally specify the clock signal. refer to the Stratix II GX PCI Express Development Board. Design Example for the Stratix II EP2S180 DSP Board Stratix II EP2S90GX PCI Express Board The Stratix II EP2S90GX PCI Express board is a hardware platform for developing and prototyping high-performance PCI Express (PCIe)-based designs and also to demonstrate the Stratix II GX device’s embedded transceiver and memory circuitry. Controls eight user-definable LEDs D9–D16).Chapter 11: Boards Library Stratix II EP2S90GX PCI Express Board 11–17 Figure 11–14. Table 11–10 on page 11–17 lists the blocks available to support the Stratix II EP2S90GX PCI Express board. Table 11–10. refer to the PCI Express Development Kit. Stratix EP2S90GX PCI Express Board Blocks Block Dip Switch LED0–LED7 SW2–SW4 Description Controls the user-definable dual in-line package switch (S5).

A2D_2_HSMC_B D2A_1_HSMC_A. Controls 14-bit signed analog-to-digital converters on the optional high speed mezzanine cards (HSMC). embedded multipliers. You can optionally specify the clock signal. A2D_1_HSMC_B. Controls the user-definable dual in-line package switch (SW5). and the Nios® II embedded soft processor. high-volume. D2A_2_HSMC_A. You can optionally specify the clock signal. Stratix III EP3SL150 DSP Board Blocks (Part 1 of 2) Block Display0 A2D_1_HSMC_A. feature-rich designs that demonstrate the Stratix III device’s on-chip memory. D2A_2_HSMC_B Dip Switch Controls the 14-bit unsigned digital-to-analog converters on the optional high speed mezzanine cards (HSMC). Table 11–11 lists the blocks available to support the Stratix III EP3SL150 DSP board. Description User defined 4-digit seven-segment LED display (U27). A2D_2_HSMC_A. Design Example for the Stratix II EP2S90GX PCI Express Board Stratix III EP3SL150 DSP Board The Stratix III EP3SL150 DSP board provides a hardware platform for developing and prototyping low-power. Table 11–11.11–18 Chapter 11: Boards Library Stratix III EP3SL150 DSP Board Figure 11–15. D2A_1_HSMC_B. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

Figure 11–16. f For information about setting up the board and the supported hardware features.Chapter 11: Boards Library Stratix III EP3SL150 DSP Board 11–19 Table 11–11. CPU_RESETN Description Controls eight user-definable LEDs (D20–D27). refer to the Stratix III Development Board. Controls four user-definable push-button switches (S2–S5) and the CPU reset push-button (S6). Test3S150Board_QuadDisplay.mdl: tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port B. Stratix III EP3SL150 DSP Board Blocks (Part 2 of 2) Block LED0–LED7 PB0–PB3.mdl: tests the LEDs and push-button switches on the main development board. Test3S150Board_HSMA. You can optionally specify the clock signal.mdl: tests the analog-to-digital and digital-to-analog converters on the daughtercard connected to HSMC port A. Reference Manual.mdl: tests the 7-segment display on the main development board. ■ ■ ■ Figure 11–16 shows the test design for the LEDs and push-button switches. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Altera provides the following design examples for the Stratix III EP3SL150 DSP board: ■ Test3S150Board_Leds. Test3S150Board_HSMB. LED and Push-button Design Example for the Stratix III EP3SL150 DSP Board Blocks Figure 11–17 shows the test design for the 7-segment display.

The test design for the daughtercard connected to HSMC port B is very similar. HSMC Design Example for the Stratix III EP3SL150 DSP Board Blocks 1 Figure 11–18 shows the test design for the daughtercard connected to HSMC port A.11–20 Chapter 11: Boards Library Stratix III EP3SL150 DSP Board Figure 11–17. If necessary. 7-Segment Display Design Example for the Stratix III EP3SL150 DSP Board Blocks Figure 11–18 shows the test design for a high speed mezzanine card. Setting Up the Mezzanine Card Test Designs The required pin and clock assignments are already set up in the design examples. Figure 11–18. you can set up your own test design with similar procedures to the procedures that Cyclone III EP3C120 DSP Board on page 11–9 describes. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

■ FIR—implements a finite impulse response filter. refer to the NCO MegaCore Function User Guide. MegaCore Functions Library The MegaCore Functions library contains blocks that represent parameterizable IP that installs with the Quartus II software. ■ FFT—implements a high performance fast Fourier transform or inverse FFT processor. refer to the Viterbi Compiler User Guide. DSP Builder supports the following Altera DSP IP: ■ CIC—implements a cascaded integrator-comb) filter. f For more information. refer to the CIC MegaCore Function User Guide. f For more information. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .12. ■ NCO—implements a customized numerically controlled oscillator. ■ Reed-Solomon—implements a forward error correction encoder or decoder. refer to the FFT MegaCore Function User Guide. the MegaWizard Plug-In starts. ■ Viterbi—Implements a high performance Viterbi decoder. f For more information. When you double-click on a MegaCore function block. refer to the FIR Compiler User Guide. f For more information. f For more information. The MegaWizard interface allows you to generate all the files required to integrate a parameterized MegaCore function variation into your DSP Builder model. refer to the Reed-Solomon Compiler User Guide. f For more information.

12–2 Chapter 12: MegaCore Functions Library DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

20 bits Rotation Mode Imaging Edge Detection Quartus II Assignment Setting Example SignalTap II Filtering Lab SignalTap II Filtering Lab with DAC to ADC Loopback Cyclone II DE2 Board Cyclone II EP2C35 DSP Board Cyclone II EP2C70 DSP Board Cyclone III EP3C25 Starter Board Cyclone III EP3C120 DSP Board (LED/PB) Cyclone III EP3C120 DSP Board (7-Seg) © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Design Examples DSP Builder provides a variety of tutorials and design examples. Altera supplies the following tutorials: ■ ■ ■ ■ ■ ■ ■ ■ ■ Amplitude Modulation HIL Frequency Sweep Switch Control Avalon-MM Interface Avalon-MM FIFO HDL Import Subsystem Builder Custom Library State Machine Table Altera supplies the following design examples: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ CIC Interpolation (3 Stages x75) CIC Decimation (3 Stages x75) Convolution Interleaver Deinterleaver IIR Filter 32 Tap Serial FIR Filter MAC based 32 Tap FIR Filter Color Space Converter Farrow Based Resampler CORDIC. which you can learn from or use as a starting point for your own design.13.

Figure 13–1. DSP Builder Design Example Demos DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . type demo at the MATLAB command prompt.13–2 Chapter 13: Design Examples ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Cyclone III EP3C120 DSP Board (HSMC A) Cyclone III EP3C120 DSP Board (HSMC B) Stratix EP1S25 DSP Board Stratix EP1S80 DSP Board Stratix II EP2S60 DSP Board Stratix II EP2S180 DSP Board Stratix II EP2S90GX PCI Express Board Stratix III EP3SL150 DSP Board (LED/PB) Stratix III EP3SL150 DSP Board (7-Seg) Stratix III EP3SL150 DSP Board (HSMC A) Stratix III EP3SL150 DSP Board (HSMC B) The following additional design examples demonstrate how you can combine blocks from the advanced and standard blocksets in a single design: ■ Combined Blockset Example To view the design examples. Select DSP Builder Blockset in the Help window to expand the list (Figure 13–1) and click on an entry to display an overview of each design. The Demos tab opens in the Help window displaying a list of design examples.

mdl. The example model is singen. Access these examples in the directory <DSP Builder install path>\DesignExamples\Tutorials\UnitBlocks 1 Amplitude Modulation The Getting Started Tutorial uses the amplitude modulation design example to demonstrate the DSP Builder design flow. the model design window opens displaying the HIL frequency sweep model (Figure 13–2). refer to the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook.Chapter 13: Design Examples Amplitude Modulation 13–3 You can display the model corresponding to each design example by clicking Run this demo in the Help window. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . f For more information about this design. Figure 13–2. Many of these example blocks include Simulink Scope blocks that display the output waveforms when you simulate the models. The design example is a modulator that has a sine wave generator. f For more information. For example. Hardware in the Loop Example Model The <DSP Builder install path>\DesignExamples\Tutorials\ directory contains the getting started tutorials and design examples. refer to the Getting Started Tutorial chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. and a delay element. The example model is FreqSweep_HIL. HIL Frequency Sweep This HIL design shows a low-pass filter on the output of a modulated sine wave generation that the CORDIC algorithm creates.mdl. f For more information about this design. if you click Run this demo for the HIL example. refer to the HIL Example Designs in the Using Hardware in the Loop (HIL) chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. You can also access simple example models for most of the blocks in the DSP Builder blockset that correspond to the examples in the block descriptions. a quadrature multiplier.

The example model is topavalon. The design example sends filtered output data off-chip through a digital-to-analog converter.mdl.13–4 Chapter 13: Design Examples Switch Control Switch Control This design example shows how you can use blocks to control the switches on a DSP Development board and how to perform the SignalTap II analysis in DSP Builder. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Altera provide alternative design examples in the CII and SII subdirectories under the <DSP Builder install path>\DesignExamples\Tutorials\SOPCBuilder\SOPCBlock\Finished Examples directory. You can include the design as an SOPC Builder peripheral to the Avalon-MM bus.mdl. refer to the SignalTap II Design Example in the Performing SignalTap II Logic Analysis chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. f For more information about this design. Avalon-MM Interface This example consists of a 4-tap FIR filter with variable coefficients. The example model is sopc_edge_detector. You can include the design as an SOPC Builder peripheral to the Avalon-MM bus. The design example uses a Stratix II EP2S60 DSP development board but you can configure the design for other boards (for example. refer to the Avalon-MM Interface Blocks in the Using the Interfaces Library chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. 1 Avalon-MM FIFO This design example consists of a Prewitt edge detector with one Avalon-MM Write FIFO buffer and one Avalon-MM Read FIFO buffer.mdl. f For more information about this design. refer to Avalon-MM FIFO Buffer in the Using the Interfaces Library chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. the Cyclone II EP2C35 development board). The example model is switch_control. f For more information about this design. The coefficients load with an Avalon-MM write slave while an off-chip source supplies the input data through an analog-to-digital converter. DSP Bu idler uses an additional slave port as a control port.

f For more information and procedures to create your own library block. The example model is top. explicit. Subsystem Builder This design example allows you to create a simple. The example model is filter8tap. f For more information about this design. Demonstration Designs The <DSP Builder install path>\DesignExamples\Demos\ directory contains additional design examples. f For more information about this design. The example model is fifo_control_logic.mdl.mdl. refer to Subsystem Builder in the Using Black-Box Designs for HDL Subsystems chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. refer to HDL Import in the Using Black-Box Designs for HDL Subsystems chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. State Machine Table This example shows how you can use a State Machine Table block to implement a FIFO controller in DSP Builder. Custom Library This design example shows how you can use a custom library block to implement a parameterizable Simulink block.mdl. black-box model with the HDL Import block. refer to the Using Custom Library Blocks chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. The example model is empty_MyFilter. black-box model with the Subsystem Builder block. refer to the State Machine Example Designs in the Using the State Machine Library chapter in the DSP Builder Standard Blockset User Guide section in volume 2 of the DSP Builder Handbook. f For more information about this design. implicit.Chapter 13: Design Examples HDL Import 13–5 HDL Import This design example is a template design that you can use to create a simple. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .mdl.

FpCoef = fix(ScalingFactor * FlCoef). which are scaled in the design with the Gain block. This function creates floating-point coefficients. This example implements a 3-stage interpolating CIC filter with a rate change factor of 75. The design uses Stratix or Cyclone device PLLs. The example model is CiCInterpolator75.9 0. which implements a Butterworth filter.13–6 Chapter 13: Design Examples CIC Interpolation (3 Stages x75) CIC Interpolation (3 Stages x75) CIC (cascaded integrator and comb) structures are an economical way to implement high sample rate conversion filters.mdl.4. The example model is topiir. The coefficients compute with the MATLAB function butter. The example model is CicDecimator75. therefore. This design requires the Mathworks Signal Processing ToolBox to calculate the coefficient with the FIR1 function: FilterOrder = 32 InputBitWidth = 8 LowPassFreqBand = [0 0.mdl. Use this design in digital down-conversion applications.LowPassFreqBand. Convolution Interleaver Deinterleaver Use convolution interleaver deinterleavers on the transmission side for forward error correction. The input frequency is 2 MHz and the output is 150 MHz.2 1]. 32 Tap Serial FIR Filter This design example illustrates how to implement a low pass 32 tap FIR (finite impulse response) filter with a 4-8 look-up table (LUT) for partial product pre-computation.0001]. CoefBitWidth = InputBitWidth + ceil(log2((max(abs(FlCoef))/min(abs(FlCoef))))) ScalingFactor = (2^(CoefBitWidth-1))-1. the output is 75 times faster than the input. The input frequency is 150 MHz and the output is 2 MHz. with an order of two and a cutoff frequency of 0. This example implements a 3-stage decimating CIC filter with a rate change factor of 75. FlCoef = firls(FilterOrder.1 0.LowPassMagnBand). the output is 75 times slower than the input.mdl. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . LowPassMagnBand = [1 0. CIC Decimation (3 Stages x75) CIC (cascaded integrator and comb) structures are an economical way to implement high sample rate conversion filters. The example uses a Memory Delay block for the interleaver FIFO buffers. therefore.0001 0. The design uses Stratix or Cyclone device PLLs. It provides an example of how the interleaver and deinterleaver work together.mdl. IIR Filter This design example illustrates how to implement an order 2 IIR filter with a direct form two structure. The example model is top12x17.

The example model is TopCsc. where one clock rate is a simple integer multiple of another clock rate. Many integrated systems. low pass FIR (finite impulse response) filter with a single Multiply Accumulate block and a single memory element for the tap delay line. Color Space Converter This design example illustrates how to implement a color space converter. However.mdl. This design requires the MathWorks Signal Processing ToolBox to calculate the coefficient with the fir1 function: coef = fix(fir1(32. h = conv(coef. require you to resample data so that a unit can comply with communication standards where the sample rates are different. which converts R'G'B to Y'C'bCr. MAC based 32 Tap FIR Filter This design example illustrates how to implement a MAC-based. such as software defined radios (SDR).1000). ImpulseData = zeros(1.FpCoef).1000).mdl. The example model is FIR_MAC32. Impulse = zeros(1. FirSamplingPeriod=1. The example model is AltrFir32.Chapter 13: Design Examples MAC based 32 Tap FIR Filter 13–7 plot(FpCoef. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . fixed-coefficient. This phase difference then combines the phases of a polyphase filter in such a way that a sample for the output phase. In some cases. generates. use interpolating and decimating FIR filters to accomplish resampling. plot(coef. ImpulseData(1) = 100. Farrow Based Resampler This design example illustrates how to implement a Farrow based decimating sample rate converter. 32-tap.3/8)*2^16-1). fftplot(h). Impulse(1) = 1. Farrow resamplers provide an efficient way to resample a data stream at a different sample rate. title('Fixed-point scaled coefficient value').'o').Impulse).'o'). in most cases the interpolation and decimation factors are so high that this approach is impractical.mdl. title('FIR Frequency response'). h = conv(ImpulseData. which you want. title('Fixed-point scaled coefficient value'). title('Impulse Frequency response'). The underlying principle is that the phase difference between the current input and wanted output is determined on a sample by sample basis. fftplot(h).

f For more information about this design. Imaging Edge Detection This design example illustrates an edge detection design. 20 bits Rotation Mode This design example illustrates a Farrow resampler. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . Quartus II Assignment Setting Example This design example illustrates Quartus II assignment setting from DSP Builder. For applications where the input rate is much lower than the system clock. which computes sine and cosine angles and implements with the coordinate rotation digital computer (CORDIC) algorithm. You can launch the Signal Compiler block to compile the design and program the Stratix EP2S60 DSP development board. click on the Doc symbol in the design model window.mdl. generate VHDL and synthesize the model to Altera devices. The design example has an input clock rate identical to the system clock. SignalTap II Filtering Lab Two numerically-controlled oscillators generate a 833.mdl.33-kHz sinusoidal signal through to the fir_result output. The low-pass filter removes the 833. f Refer to AN364: Edge Detection Reference Design for a full description of the edge detector design. The example model is FilteringLab.33kHz sinusoidal signal and a 83. CORDIC. The design example adds the signals together. change it as required for your application. The example model is DemoCordic. The resulting signal loops back to a low-pass 34-tap filter with 14-bit fixed-point coefficients. 20 bits Rotation Mode This design example illustrates an iterative 20 bit rotation mode.33-kHz sinusoidal signal and allows the 83. The example model is Edge_detector. You can simulate its performance in MATLAB.mdl.mdl.33kHz sinusoidal signal. time sharing should be implemented to achieve a cost effective solution.mdl. The example model is Top_2s60Board. The example model is FarrowResamp.13–8 Chapter 13: Design Examples CORDIC.

refer to “Cyclone II EP2C70 DSP Board” on page 11–4.33kHz sinusoidal signal through to the fir_result output. The example model is Test2c35Board. For a description of this board. The low-pass filter removes the 833.mdl. The example model is StFilteringLab.mdl. refer to “Cyclone II DE2 Board” on page 11–2.mdl. refer to “Cyclone II EP2C35 DSP Board” on page 11–3. The example model is Test2C70Board. The design example adds the signals together on chip before they pass through a digital-to-analog converter on the Stratix EP1S25 DSP board. Cyclone III EP3C120 DSP Board (LED/PB) This design example illustrates how you can connect blocks representing the LED and push-button components on a Cyclone III EP3C120 DSP board. The example model is Test3C120Board_Leds. Cyclone III EP3C25 Starter Board This design example illustrates how you can connect blocks representing the components on a Cyclone III EP3C25 starter board.33kHz sinusoidal signal and allows the 83. For a description of this board.mdl. The example model is TestDE2Board. Cyclone II EP2C35 DSP Board This design example illustrates how you can connect blocks representing the components on a Cyclone II EP2C35 DSP development board. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries . Cyclone II EP2C70 DSP Board This design example illustrates how you can connect blocks representing the components on a Cyclone II EP2C70 DSP development board. The example model is Test3C25Board.33kHz sinusoidal signal.mdl. The resulting analog signal loops back to an analog-to-digital converter on the board and then passes to an on-chip. For a description of this board.mdl. refer to “Cyclone III EP3C25 Starter Board” on page 11–6. low-pass filter.33kHz sinusoidal signal and a 83. For a description of this board. Cyclone II DE2 Board This design example illustrates how you can connect blocks representing the components on a Cyclone II DE2 board.Chapter 13: Design Examples SignalTap II Filtering Lab with DAC to ADC Loopback 13–9 SignalTap II Filtering Lab with DAC to ADC Loopback Two numerically-controlled oscillators generate a 833.

mdl. For a description of this board. Cyclone III EP3C120 DSP Board (7-Seg) This design example illustrates how you can connect blocks representing the 7-segment display component on a Cyclone III EP3C120 DSP board. The example model is Test1S80Board. Cyclone III EP3C120 DSP Board (HSMC A) This design example illustrates how you can connect blocks representing the components on a high speed mezzanine card (HSMC) connected to HSMC port A of a Cyclone III EP3C120 DSP board. The example model is Test3C120Board_HSMA. refer to “Cyclone III EP3C120 DSP Board” on page 11–6. Stratix EP1S25 DSP Board This design example illustrates how you can connect blocks from the Boards library that represent components on a Stratix EP1S25 DSP development board. refer to “Stratix EP1S80 DSP Board” on page 11–13.mdl.mdl.13–10 Chapter 13: Design Examples Cyclone III EP3C120 DSP Board (7-Seg) For a description of this board. The example model is Test3C120Board_HSMB. Stratix EP1S80 DSP Board This design example illustrates how you can connect blocks from the Boards library that represent components on a Stratix EP1S80 DSP development board. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . refer to “Cyclone III EP3C120 DSP Board” on page 11–6. The example model is Test3C120Board_QuadDisplay. refer to “Stratix EP1S25 DSP Board” on page 11–11. For a description of this board.mdl. The example model is Test1S25Board. refer to “Cyclone III EP3C120 DSP Board” on page 11–6. refer to “Cyclone III EP3C120 DSP Board” on page 11–6.mdl. Cyclone III EP3C120 DSP Board (HSMC B) This design example illustrates how you can connect blocks representing the components on a high speed mezzanine card (HSMC) connected to HSMC port B of a Cyclone III EP3C120 DSP board. For a description of this board. For a description of this board. For a description of this board.

For a description of this board. Stratix II EP2S180 DSP Board This design example illustrates how you can connect blocks from the Boards library that represent components on a Stratix II EP2S180 DSP development board.mdl. Stratix III EP3SL150 DSP Board (HSMC A) This design example illustrates how you can connect blocks representing the components on a high speed mezzanine card (HSMC) connected to HSMC port A of a Stratix III EP3SL150 DSP board. For a description of this board. The example model is Test3S150Board_QuadDisplay. Stratix II EP2S90GX PCI Express Board This design example illustrates how you can connect blocks from the Boards library that represent components on a Stratix II EP2S90GX PCI Express board. For a description of this board. The example model is Test2S180Board.mdl. refer to “Stratix III EP3SL150 DSP Board” on page 11–18.mdl. The example model is Test3S150Board_HSMA. Stratix III EP3SL150 DSP Board (7-Seg) This design example illustrates how you can connect blocks representing the 7-segment display component on a Stratix III EP3SL150 DSP board.Chapter 13: Design Examples Stratix II EP2S60 DSP Board 13–11 Stratix II EP2S60 DSP Board This design example illustrates how you can connect blocks from the Boards library that represent components on a Stratix II EP2S60 DSP development board. For a description of this board. refer to “Stratix III EP3SL150 DSP Board” on page 11–18. For a description of this board.mdl.mdl. The example model is Test2S60Board. refer to “Stratix II EP2S60 DSP Board” on page 11–14. The example model is Test2S90GXBoard. Stratix III EP3SL150 DSP Board (LED/PB) This design example illustrates how you can connect blocks representing the LED and push-button components on a Stratix III EP3SL150 DSP board. refer to “Stratix II EP2S180 DSP Board” on page 11–15. The example model is Test3S150Board_Leds. © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .mdl. refer to “Stratix II EP2S90GX PCI Express Board” on page 11–17.

The resulting system comprises blocks from both blocksets.mdl. For a description of this board. simulates cycle-accurately and you can us the standard blockset TestBench block to test it.13–12 Chapter 13: Design Examples Stratix III EP3SL150 DSP Board (HSMC B) For a description of this board. The example model is demo_adapted_ad9856. refer to the DSP Builder chapter in the DSP Design Flow User Guide.mdl. refer to “Stratix III EP3SL150 DSP Board” on page 11–18. refer to “Stratix III EP3SL150 DSP Board” on page 11–18. Combined Blockset Example This design example illustrates how to embed a DSP Builder Advanced Blockset design inside a top-level standard blockset design. DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation . The example model is Test3S150Board_HSMB. f For more information about this design example. Stratix III EP3SL150 DSP Board (HSMC B) This design example illustrates how you can connect blocks representing the components on a high speed mezzanine card (HSMC) connected to HSMC port B of a Stratix III EP3SL150 DSP board.

AltLab The AltLab library includes the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ BP (Bus Probe) Clock Clock_Derived Display Pipeline Depth HDL Entity HDL Import HDL Input HDL Output HIL (Hardware in the Loop) Quartus II Global Project Assignment Quartus II Pinout Assignments Resource Usage Signal Compiler SignalTap II Logic Analyzer SignalTap II Node Subsystem Builder TestBench VCD Sink Arithmetic The Arithmetic library includes the following blocks: ■ ■ ■ ■ ■ ■ ■ Barrel Shifter Bit Level Sum of Products Comparator Counter Differentiator Divider DSP © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .14. Categorized Block List This appendix lists the blocks in each of the libraries in the Altera DSP Builder blockset.

14–2 Chapter 14: Categorized Block List ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Gain Increment Decrement Integrator Magnitude Multiplier Multiply Accumulate Multiply Add Parallel Adder Subtractor Pipelined Adder Product SOP Tap Square Root Sum of Products Complex Type The Complex Type library includes the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ Butterfly Complex AddSub Complex Conjugate Complex Constant Complex Delay Complex Multiplexer Complex Product Complex to Real-Imag Real-Imag to Complex Gate & Control The Gate & Control library includes the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ Binary to Seven Segments Bitwise Logical Bus Operator Case Statement Decoder Demultiplexer Flipflop If Statement LFSR Sequence DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

Chapter 14: Categorized Block List 14–3 ■ ■ ■ ■ ■ ■ Logical Bit Operator Logical Bus Operator Logical Reduce Operator Multiplexer Pattern Single Pulse Interfaces The Interfaces library includes the following blocks: ■ ■ ■ ■ ■ ■ ■ Avalon-MM Master Avalon-MM Slave Avalon-MM Read FIFO Avalon-MM Write FIFO Avalon-ST Packet Format Converter Avalon-ST Sink Avalon-ST Source IO & Bus The IO & Bus library includes the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ AltBus Binary Point Casting Bus Builder Bus Concatenation Bus Conversion Bus Splitter Constant Extract Bit Global Reset GND Input Non-synthesizable Input Non-synthesizable Output Output Round Saturate VCC © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .

14–4 Chapter 14: Categorized Block List Rate Change The Rate Change library includes the following blocks: ■ ■ ■ ■ ■ ■ Clock Clock_Derived Dual-Clock FIFO Multi-Rate DFF PLL Tsamp Simulation Blocks Library The Simulation Blocks library includes the following blocks: ■ ■ External RAM Multiple Port External RAM State Machine Functions The State Machine Functions library includes the following blocks: ■ ■ State Machine Editor State Machine Table Storage The Storage library includes the following blocks: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Delay Down Sampling Dual-Clock FIFO Dual-Port RAM FIFO Buffer LUT (Look-Up Table) Memory Delay Parallel To Serial ROM Serial To Parallel Shift Taps Single-Port RAM True Dual-Port RAM Up Sampling DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

Chapter 14: Categorized Block List 14–5 Boards The Boards library includes blocks that support the following development boards: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Cyclone II DE2 Board Cyclone II EP2C35 DSP Board Cyclone II EP2C70 DSP Board Cyclone III EP3C25 Starter Board Cyclone III EP3C120 DSP Board Stratix EP1S25 DSP Board Stratix EP1S80 DSP Board Stratix II EP2S60 DSP Board Stratix II EP2S180 DSP Board Stratix II EP2S90GX PCI Express Board Stratix III EP3SL150 DSP Board © June 2010 Altera Corporation Preliminary DSP Builder Standard Blockset Libraries .

14–6 Chapter 14: Categorized Block List DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation .

mdl file 1–3 .qar file 12–1 .Index Symbols .mdlxml file 12–1 .qip file 12–2 Avalon-ST Packet Format Converter block 5–12 Avalon-ST Sink block 5–18 Avalon-ST Source block 5–20 B Barrel Shifter block 2–2 Binary Point Casting block 6–4 Binary to Seven Segments block 4–2 Bit Level Sum of Products block 2–3 Bit width design rule 3–4 Bitwise Logical Bus Operator block 4–3 Black box 3–22 Explicit 8–1 HDL import Walkthrough 8–1 Implicit 8–1 Subsystem Builder Walkthrough 8–6 Using HDL import 8–1 Using SubSystem Builder 8–1 Boards library 11–1 Bus Builder block 6–5 Bus Concatenation block 6–7 Bus Conversion block 6–8 Bus Probe (BP) block 1–2 Bus Splitter block 6–9 Butterfly block 3–2 A Advanced blockset interoperability 1–3 alt_dspbuilder_createComponentLibrary Create component library command 10–6 alt_dspbuilder_exportHDL command 12–3 alt_dspbuilder_refresh_hdlimport Update HDL command 3–25 alt_dspbuilder_refresh_megacore Update MegaCore command 4–2 alt_dspbuilder_refresh_user_library_blocks Update user libraries command 9–6 alt_dspbuilder_setup_megacore Setup MegaCore command 4–1 alt_dspbuilder_verifymodel Comparision command 3–22 AltBus block 6–2 Altera Quartus II software 1–2 Integration with MATLAB 1–3 AltLab library 1–1 Arithmetic library 2–1 asynchronous clear signal wiring 13–6 Automatic flow 3–19 Avalon-MM interface Features 1–2 FIFO walkthrough 7–16 Interface blocks walkthrough 7–8 Master block 7–4 Read FIFO 7–7 Slave block 7–2 SOPC Builder integration 7–1 Write FIFO 7–6 Avalon-MM Master block 5–3 Avalon-MM Read FIFO block 5–9 Avalon-MM Slave block 5–6 Avalon-MM Write FIFO block 5–11 Avalon-ST interface Features 1–2 Packet Format Converter 7–22 Packet formats 7–21 SOPC Builder integration 7–20 C Case Statement block 4–5 Clock Setting a derived clock 2–2 Setting the base clock 2–2 Clock block 1–2 Clock_Derived block 1–3 Clocking 3–8 Assignment 3–11 Categories 3–11 Clock enable signal 3–8 Configuration parameters 2–3 Global reset 3–17 HDL simulation models 3–16 Multiple clock domains 3–9 Sampling period 3–8 Simulink simulation model 3–16 Single clock domain 3–8 Timing relationships 3–18 Using a PLL block 3–14 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation .hex file 12–2 .

1 blocks 13–6 Loop while propagating bit widths 13–4 Output connected to Altera block 13–5 Unexpected end of file 13–10 When generating blocks 13–7 Example designs 32 tap FIR filter 13–6 Amplitude modulation 13–3 Avalon-MM Blocks 13–4 Avalon-MM FIFO 13–4 CIC decimation 13–6 CIC interpolation 13–6 Color space converter 13–7 Combined blocksets 13–12 Convolution interleaver deinterleaver 13–6 CORDIC. 20 bits rotation mode 13–8 Custom Library 13–5 Custom library block 9–1 Cyclone II DE2 board 13–9 Cyclone II EP2C35 board 13–9 Cyclone II EP2C70 board 13–9 Cyclone III EP3C120 board (7-seg display) 13–10 D Data width propagation 3–4 Decoder block 4–7 Delay block 9–2 Demultiplexer block 4–8 Design flow 2–1 Control using Signal Compiler 3–19 Overview 2–1 Using a State Machine Editor block 11–7 Using a State Machine Table Block 11–2 Using Hardware in the loop 5–1 Using MegaCore functions 4–2 Design rules 3–1 Bit width 3–4 Frequency 3–8 Signal Compiler 3–19 Device family support Standard blockset 1–1 Differentiator block 2–8 Digital signal processing (DSP) 1–3 Display Pipeline Depth block 1–4 Divider block 2–9 Down Sampling block 9–3 DSP block 2–10 DSP development board Board description file 10–4 Component description file 10–2 Creating a board library 10–6 Cyclone III EP3C120 board (HSMC A) 13–10 Cyclone III EP3C120 board (HSMC B) 13–10 Cyclone III EP3C120 board (LED/PB) 13–9 Cyclone III EP3C25 starter board 13–9 Farrow based resampler 13–7 Getting started tutorial 2–4 Hardware in the loop 5–3 HDL Import 13–5 HDL import 8–1 HIL frequency sweep 13–3 IIR filter 13–6 Imaging edge detection 13–8 MAC based 32 tap FIR filter 13–7 Quartus II assignment setting 13–8 SignalTap II 6–2 SignalTap II filtering lab 13–8 SignalTap II filtering lab with loopback 13–9 SOPC Builder peripheral 7–8 State machine example 11–1 State Machine Table 13–5 Stratix EP1S25 board 13–10 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation .Index–2 Using advanced PLL features 3–15 Using Clock and Clock_Derived blocks 3–10 Comments Adding to a block 3–22 Comparator block 2–5 Complex AddSub block 3–4 Complex Conjugate block 3–6 Complex Constant block 3–8 Complex Delay block 3–9 Complex Multiplexer block 3–10 Complex Product block 3–11 Complex to Real-Imag block 3–13 Complex Type library 3–1 Constant block 6–10 Controlling synthesis and compilation 3–19 Counter block 2–6 Custom library Adding to the library browser 9–5 Creating a library model file 9–1 Walkthrough 9–1 Cyclone II DE2 DSP board 11–2 Cyclone II EP2C35 DSP board 11–3 Cyclone II EP2C70 DSP board 11–4 Cyclone III EP3C120 DSP board 11–6 Cyclone III EP3C25 DSP board 11–6 Creating a new board description 10–1 predefined components 10–1 Supported boards 10–1 Troubleshooting 13–5 Dual-Clock FIFO block 9–4 Dual-Port RAM block 9–7 E Error message Data type mismatch 13–6 Design includes pre-v7.

Index–3 Stratix EP1S80 board 13–10 Stratix II EP2S180 board 13–11 Stratix II EP2S60 board 13–11 Stratix II EP2S90GX PCI Express board 13–11 Stratix III EP3SL150 board (7-seg display) 13–11 Stratix III EP3SL150 board (HSMC A) 13–11 Stratix III EP3SL150 board (HSMC B) 13–12 Stratix III EP3SL150 board (LED/PB) 13–11 Subsystem Builder 13–5 Switch Control 13–4 External RAM block 8–1 Extract Bit block 6–12 Input block 6–14 Integrator block 2–19 Interfaces library 5–1 IO & Bus library 6–1 L LFSR Sequence block 4–14 Library AltLab 1–1 Arithmetic 2–1 Boards 11–1 Complex Type 3–1 Gate & Control 4–1 Interfaces 5–1 IO & Bus 6–1 MegaCore Functions 12–1 Rate Change 7–1 Simulation 8–1 State Machine Functions 10–1 Storage 9–1 Logical Bit Operator block 4–16 Logical Bus Operator block 4–17 Logical Reduce Operator block 4–19 LUT (Look-Up Table) block 9–11 F FIFO block 9–10 Flipflop block 4–10 Frequency Design Rules 3–8 G Gain block 2–15 Gate & Control library 4–1 Generating a Testbench 2–17 Global Reset (or SCLR) block 6–13 GND block 6–13 M H Hardware in the loop (HIL) 1–2 Burst & frame modes 5–6 Design flow 5–1 Overview 5–1 Requirements 5–2 Troubleshooting 5–10 Walkthrough 5–3 HDL Simulation model 3–16 HDL Entity block 1–4 HDL export 12–2 HDL import Black box 8–1 Features 1–2 Updating 3–24 Walkthrough 8–1 HDL Import block 1–5 HDL Input block 1–7 HDL Output block 1–8 Hierarchical design 3–20 HIL (Hardware in the Loop) block 1–9 How to Contact Altera Info–1 Magnitude block 2–20 Manual flow 3–19 MATLAB 1–2 Integration with 1–3 Opening the Simulink library browser 2–4 Using a base or masked subsystem variable 3–2 Using a MATLAB array to initilize a block 3–22 MegaCore function 1–3 Design flow 4–2 Design issues 4–13 Device family 4–14 Generating a variation 4–3 Installing 4–1 Instantiating 4–2 OpenCore Plus evaluation 4–1 Optimizing 4–3 Parameterizing 4–3 Signal Compiler 4–14 Simulating 4–3 Simulating in the tutorial design 4–8 Updating variations 4–2 Version numbers 4–1 Walkthrough 4–3 MegaCore Functions library 12–1 Memory block types 1–1 Memory Delay block 9–13 Model I If Statement block 4–11 Increment Decrement block 2–17 © June 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 2: DSP Builder Standard Blockset .

Index–4 Creating 2–4 Performing RTL simulation 2–17 Simulating in Simulink 2–15 ModelSim Comparison with Simulink 3–22 Simulation fllow 3–19 Using a Tcl file to add commands 3–27 Multiple Port External RAM block 8–3 Multiplexer block 4–20 Multiplier block 2–21 Multiply Accumulate block 2–23 Multiply Add block 2–25 Multi-Rate DFF block 7–1 Quartus II Project Pinout Assignments block 1–11 R Rate Change library 7–1 Real-Imag to Complex block 3–14 Release information 1–1 Reset Asynchronous 3–17 global 3–17 Resource usage Analyzing 3–25 Resource Usage block 1–12 ROM block 9–16 Round block 6–18 N Naming conventions 3–1 Nios II Support 1–2 Using the Nios II IDE 7–15 Non-synthesizable Input block 6–15 Non-synthesizable Output block 6–16 Notation Binary point location 3–3 Fixed-point 3–2 S Saturate block 6–20 Serial To Parallel block 9–18 Shift Taps block 9–20 Signal Compiler 3–19 Adding to a model 2–16 Enabling SignalTap II options 6–6 License 13–1 Synthesis and compilation flows 3–19 Signal Compiler block 1–13 Signal data type display format 3–24 SignalTap II Design flow 6–1 Walkthrough 6–2 SignalTap II logic analyzer 6–1 Features 1–2 Performing logic analysis 6–1 Signal Compiler options 6–6 Trigger conditions 6–7 SignalTap II Logic Analyzer block 1–14 SignalTap II Node block 1–15 Simulation Setting the Simulink solver 2–3 Using ModelSim 2–17 Using Simulink 2–15 Simulation flow 3–19 Simulation library 8–1 Simulation model HDL 3–16 Simulink Comparison with ModelSim 3–22 Integration with 1–3 Solver 3–16 Single Pulse block 4–23 Single-Port RAM block 9–21 Solver Setting simulation parameters 2–3 O Output block 6–17 P Packet Format Converter Avalon-ST 7–22 Parallel Adder Subtractor 2–27 Parallel To Serial block 9–14 Pattern block 4–22 Pipeline depth display 3–24 Pipelined Adder block 2–29 PLL block 7–3 PLL clocks device support 3–14 Port data type display format 3–24 Product block 2–31 Q Quartus II assignments Adding to block entity names 3–27 Quartus II constraints Adding to a model 3–23 Quartus II project Adding a DSP Builder design 2–20 Integration of multiple models 12–5 Quartus II Project Global Assignment block 1–11 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation .

Index–5 SOP Tap block 2–33 SOPC Builder Interfaces library 7–1 Support 1–2 SOPC builder Instantiating your design 7–12 Square Root block 2–35 State machine Implementing 11–1 State Machine Editor Walkthrough 11–7 State Machine Editor block 10–1 State Machine Functions library 10–1 State Machine table Walkthrough 11–2 State Machine Table block 10–3 Storage library 9–1 Stratix EP1S25 DSP board 11–11 Stratix EP1S80 DSP board 11–13 Stratix II EP2S180 DSP board 11–15 Stratix II EP2S60 DSP board 11–14 Stratix II EP2S90GX PCI Express board 11–17 Stratix III EP3SL150 DSP board 11–18 Subsystem Builder Walkthrough 8–6 Subsystem Builder block 1–15 Sum of Products block 2–36 Sum of Products Tap block 2–33 Adding to a model 2–17 TestBench block 1–17 True Dual-Port RAM block 9–24 Tsamp block 7–4 Tutorial Getting started 2–4 Typographic Conventions Info–1 U Up Sampling block 9–28 V VCC block 6–21 VCD Sink block 1–18 W Walkthrough Avalon-MM FIFO 7–16 Avalon-MM interface blocks 7–8 Black box HDL import 8–1 Subsystem Builder 8–6 Custom library 9–1 Hardware in the loop 5–3 MegaCore function 4–3 SignalTap II 6–2 State Machine Editor 11–7 State Machine Table 11–2 Warning message I/O blocks conflict with clock or aclr ports 13–6 T TestBench © June 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 2: DSP Builder Standard Blockset .

Index–6 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation .

resetn. Indicates variables. references to parts of files (for example. Active-low signals are denoted by suffix n. For example.com Email Email Email Typographic Conventions The following table shows the typographic conventions that this document uses.gdf file. Indicates directory names. AN 519: Stratix IV Design Guidelines.com/training custrain@altera.gdf. Indicates document titles. Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. and primitive names. \qdesigns directory.altera. such as a Report File. dialog box titles.com authorization@altera. and logic function names (for example. d: drive.altera. and chiptrip. and other GUI labels. software utility names. For example. Also indicates sections of an actual file. bit. For example. For example. Contact Method Website Website Email Altera literature services Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. project names.pof file.com/support www. Indicates command line commands and anything that must be typed exactly as it appears. TRI). Contact (Note 1) Technical support Technical training Address www. the AHDL keyword SUBDESIGN). tdi. file names. “Typographic Conventions. Variable names are enclosed in angle brackets (< >). capitalization matches the GUI. and input. For GUI elements. c:\qdesigns\tutorial\chiptrip. For example. Initial Capital Letters “Subheading Title” Courier type Italic Type with Initial Capital Letters Italic type Indicates keyboard keys and menu names. Delete key and the Options menu.” Indicates signal. file name extensions. For example. register. disk drive names. <file name> and <project name>. block.com literature@altera. Visual Cue Bold Type with Initial Capital Letters bold type Meaning Indicates command names. data1. For example. dialog box options.com nacomp@altera. For example. Save As dialog box. dialog box options. For example.Additional Information How to Contact Altera For the most up-to-date information about Altera® products. For example. see the following table. port. © June 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 2: DSP Builder Standard Blockset . and other GUI labels. n + 1.

■ ■ Meaning Numbered steps indicate a list of items when the sequence of the items is important. 2. 3.. Bullets indicate a list of items when the sequence of the items is not important. and a. A warning calls attention to a condition or possible situation that can cause you injury. 1 c w r f DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation . such as the steps listed in a procedure.. b.. The feet direct you to more information about a particular topic. c... A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.Info–2 Additional Information Typographic Conventions Visual Cue 1. The hand points to information that requires special attention. The angled arrow instructs you to press Enter. and so on..

altera.com HB_DSPB_ADV-2.0 December 2010 .0 Document Version: Document Date: 2.DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset 101 Innovation Drive San Jose. CA 95134 www.

product. and all other words and logos that are identified as trademarks and/or service marks are. or service described herein except as expressly agreed to in writing by Altera Corporation. the trademarks and service marks of Altera Corporation in the U. Altera assumes no responsibility or liability arising out of the application or use of any information. maskwork rights. and copyrights. All rights reserved. and foreign patents and pending applications. Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.S. and other countries. but reserves the right to make changes to any products and services at any time without notice. the stylized Altera logo.Copyright © 2010 Altera Corporation. . All other product or service names are the property of their respective holders. Altera products are protected under numerous U. specific device designations. The Programmable Solutions Company.S. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty. unless noted otherwise.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10 Time-Division Multiplexing . . . . . 1–19 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–22 Adding a DSP Builder Advanced Blockset Design to an Existing Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–28 Chapter 2. . . . . . . . . . . . . . . . . . . iii Chapter 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–28 Learning to Use the Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Signals Block . . . . . 1–19 Fixed-point Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents Section Revision Dates Section I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23 Comparison with RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 Vectorized Inputs . . . . . . . . . . . . . . . . . 1–5 ModelPrim Blocks . . 1–8 Cycle Accuracy and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12 Multichannel Operation . . . . 1–1 Base Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Specifying the Output Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–24 Run ModelSim Flow . . . . . . . . . . . . 1–22 Adding Advanced Blockset Components to SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Hardware Interfaces . . . . . . . . . . . . . . . . 1–7 ModelBus Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23 Loading in ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26 Design Space Exploration . . . . . . . . . . . . 1–14 Memory-Mapped Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23 Running from a Command . . . . . . . . . . . . . . . . . . Design Examples and Reference Designs Opening a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 FFT Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26 Interoperability with the Standard Blockset . . . . . . . . . . . . . . . . . . . . . 1–20 Generated Files . . . . . . . . . . . DSP Builder Advanced Blockset User Guide About This Section Revision History . . . . . . . 2–1 © December 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 SynthesisInfo Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–19 Sample Rate and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8 ModelIP Blocks . . . . . . 1–23 Running All the Automatic Testbenches in a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Protocol for Connecting IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Device Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Design Semantics . . . . . . . . . . . . . . . . . . . . . . About the DSP Builder Advanced Blockset Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 Channelization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23 Automatic Testbench Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21 Creating a Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 Chapter 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset Preliminary © December 2010 Altera Corporation . . . . . . . . . . 3–3 Simulating the Design Example in Simulink . . . . . . . . . . . . . . 4–9 Compiling with the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Configuring the NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 Compiling with the Quartus II Software . . . . ModelIP Tutorial Opening the NCO Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Complete the Top-Level Model . . . . . . . . . . . . . . 4–1 Creating the Fibonacci Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12 Instantiating the Design in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1–iv Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Running a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 Changing the Number of Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Simulating the Design in Simulink . . . . . . . . . . 4–6 Exploring the Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13 Customizing the NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 Increasing the Spurious Free Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Setting the Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Copying a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17 Chapter 4. . . . . . . . . . 4–5 Using Complex Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Simulating the RTL . . . . 4–1 Add Blocks from the ModelPrim Library . . . . . 3–10 Exploring the Generated Files . . . . . . . . . . . . . . . . . . . 4–1 Create a New Model . . . . . . . . . . . . . . . . . . . . . . . 4–4 Using Vector Types . . . . . . . 2–10 ModelIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1 Create a Synthesizable Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . Primitive Library Tutorial The Fibonacci Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19 Common Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19 ModelPrim Blocks Outside Primitive Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 Other Vector Blocks—Simulink Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15 Building System Components with Avalon-ST Interface Blocks . . . . . . . . . . . . . . . . . 4–13 Flow Control Using FIFO Buffers . . 4–17 Interfaces as Scheduling Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Verification Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23 Floating Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 Primitive Subsystem Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 Converting Blocks and Specifying Output Types . . . . . . . . . . . . . . . . System Tutorial System Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 Flow Control Using Latches . . . . . . 4–30 Generated Testbenches . . . . . . . . . . . . . . . . . . . . . 4–16 Adding More Ports to the Avalon-ST Blocks . . . . . . . . . . . . . . . . . . . . . .v General Primitive Library Guidelines . . . . . . . . . . . . . . . . 4–23 Interacting with Other Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Adding Custom Text . . . . . . . . . 4–14 Safe Operation of FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 Implementing Flow Control . . 4–10 Top-Level Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18 ModelPrim Subsystem Designs to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15 Flow Control Using the ForLoop Block . . . . . . . . . . . . . . . 5–1 © December 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–29 Floating Point Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Design Recommendations . . . . . . . . 4–14 Flow Control using Simple Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Essential Recommendations . . 4–32 Chapter 5. . . . . . . . . . . . 4–11 Using Vectors . . . . . . . . . . . 4–13 Forward Flow Control Using Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 Flow Control and Back Pressure Using FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21 Converting Between Floating. . . . . . . . . . . . . . . . . . . . . . . 4–20 Floating-Point Data Types . . . . . . . . . . . . . . . . . . 4–17 Interfaces as Subsystem Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–24 Floating-Point Type Propagation . . . . . . . . . . . . . . . 4–12 Vector Utils Library . . . . . . . . . . . . . . . . . . . 4–15 Using Loop or ForLoop Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–28 Special Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16 Extending the Interface Definition . . . . 4–10 Testbench Recommendations . . . . . . . 4–17 Using ModelPrim Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . .and Fixed-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 5–14 Compiling with the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 ModelBus Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Filter Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Builder Advanced Blockset Libraries About This Section Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 Mixer Scale Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 Control Block . . . . . . . . . . . . . 6–1 Non-Explicit Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 Signals Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency Management Zero Latency Example . . . . . 7–5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8 Decimating FIR Blocks . . . . . . . . . . . . . 5–13 Exploring the Generated Files . . . . . . . Folding Using Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16 Chapter 6. . . . . . . . . . 5–7 DecimatingCIC and Scale Blocks . . . . . 5–4 DDCChip Subsystem . . . 6–4 Latency and fMAX Constraint Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 Sink Blocks . . . . . . . . 1–1 FFT Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Using Latency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 Tool Interface Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Distributed Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6 NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2 Effects of Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 Primary Inputs . . . . . . . . 5–6 Mixer . . . . . . . . . . . . . . . . . . . iii Chapter 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Effects on Manual Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Waveform Synthesis Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3 Combined Blockset Example 2 . . . . . . . . 5–10 Simulating the Design in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6 Chapter 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6 Archiving Combined Blockset Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1–vi The DDC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4 Effects on Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 Source Blocks . . . . . . . . . . . . . . . . . . . . . . . 6–5 Chapter 7. . . . . 5–6 Merge Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Folded Subsystem with TDM . . . . . . . . . . . . . . . . . . . DSP Builder Standard and Advanced Blockset Interoperability Combined Blockset Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . 8–12 Section II. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 Using Latency Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 Folded Subsystem without Time Division Demultiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction Base Library . . . . . . . . . . . . . 8–12 Advanced Blockset Example . . . . . . . . . . . . 1–2 DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset Preliminary © December 2010 Altera Corporation . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Design Example . . . . . . 2–16 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 LocalThreshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vii ModelPrim Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 Zero-Latency Latch (latch_0L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Chapter 2. . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Design Example . . . . 2–9 Edit Params . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Run Quartus II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Set-Priority Latch (SRlatch) . . . . . . . . . . . . . . . . . . . . . 2–7 Control . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 Parameters . . . . . . . 2–15 Port Interface . . . . . . 2–16 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Vector Multiplexer (VectorMux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Avalon-ST Input (AStInput) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13 Run ModelSim . . . . . . . . . . . . . . . . . . . . . 2–6 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Usage . . . . . . . . . . . . . . . 2–4 Expand Scalar (ExpandScalar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 Reset-Priority Latch (SRlatch_PS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 © December 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset . . . . . Additional and Base Library Avalon-ST Output (AStOutput) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Tapped Delay Line (TappedDelayLine) . . . . 2–17 Signals . . 2–3 Avalon-ST Input FIFO Buffer (AStInputFIFO) . 2–6 Updated Help . . . . . . . . . . . . . 2–5 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 Channel Viewer (ChanView) . . . . . . . . . . . . . . . . . . . . . 2–3 Single-Cycle Latency Latch (latch_1L) . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Decimating CIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Operation . . . . . . . . . . 3–3 Parameterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Coefficient Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 High Speed Operation . . 3–5 Port Interface . . . . . . . . . . . 3–13 Typical Resource Utilization . . . . 3–14 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Updated Help . . . . 3–15 Interpolating CIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 Typical Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . 3–4 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 Design Example . . . . . . . . . . . . . . . . . . . . 3–7 Decimating FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Parameters . . . . . . . . . . . . . . . 3–12 Port Interface . . . . . . . . . . . . . . . . . 3–3 Channelization . . . . . . . . . . . . . . . . . . . . 3–5 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 Features . . 3–7 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Basic FIR Filter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 Updated Help . . . . . . . . . . . . . . . . . . . . . 3–1 Common Features . . . . . . . . . . . 3–11 Operation . . . . . . . . . . .1–viii Chapter 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8 Port Interface . . . . . . . . . . . . 3–8 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 Typical Resource Utilization . . . . . . . . . . . . . . 3–5 Typical Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 Fractional Rate FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 Scalability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . 3–2 Automatic Pipelining . . . . 3–4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Half-Band and L-Band Nyquist FIR Filters . . . . . . . . . . . . Filter Library FIR and CIC Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 Operation . . 3–18 DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset Preliminary © December 2010 Altera Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. 4–11 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Parameters . . . . . . . . . . . . . . . . . . . . . . 3–20 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23 Filter Coefficients . . . . . . . 4–12 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Negate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6 Parameters . . . . . . . . . . . . . . . . . . . . . 4–5 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Design Example . . . . . . . . . . . . . . . . . . . . . . . . 3–23 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Port Interface . . . . . . . . . . . . . . . . . . . . . 4–6 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24 Typical Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 Bit Reverse Core (BitReverseCore) . . . . 4–12 © December 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–26 Chapter 4. . . . . . . . . 4–11 Port Interface . . . . . . . . . . . . . . . . . . . . 4–8 Butterfly II (BFII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Parameters . . 4–11 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–25 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4 Dual Twiddle Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Twiddle Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22 Single-Rate FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19 Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20 Typical Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FFT Library Complex Multiplier (ComplexMult) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24 Port Interface . . . . 4–9 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Butterfly I (BFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Complex Sample Delay (ComplexSampleDelay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ix Interpolating FIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6 Negate Parameterizable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 Parameters . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveform Synthesis Library Complex Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9 DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset Preliminary © December 2010 Altera Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ModelBus Library Bus Slave (BusSlave) . . . . . . . . . . . . . . . . . . 6–3 Bus Stimulus File Reader (Bus StimulusFileReader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Shared Memory (SharedMem) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 Typical Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . 6–3 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 Updated Help . . . . . . . . . . . . . . . . . . 5–11 Chapter 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8 Design Example . . . . . 5–11 Design Example . . . . . . . . . . . . . . . . . . . . 6–7 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 Design Example . . . . . . . . . . . . 6–7 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 Port Interface . . . . . . . . . . . . . . . . . . . . . 5–3 Real Mixer . . . . . . . . . . . . . . . . . . . . . . . 6–2 Port Interface . . . . . . 6–7 Parameters . . . . . . 6–2 Bus Stimulus (BusStimulus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6 Register Field (RegField) . . . . . . . . . . . . . . . . 6–7 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9 Results Tab . . . . . . . . . . . . . . . . 5–8 Frequency Hopping . . . . . . . . . 5–2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 NCO . . . . . . . . . . . . . . . . . . . . . 6–5 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 Design Example . 5–6 Phase Increment and Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1–x Chapter 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7 Phase Increment Memory Registers . . . 5–6 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 Updated Help . . . . . . . . . 6–1 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4 Register Bit (RegBit) . . . . . . . 6–7 Register Out (RegOut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . 7–5 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Bit Combine (BitCombine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Parameters . . . . . . . . . . . . . . . . . . . . 7–13 Port Interface . . . . . . . . . . . 7–14 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Port Interface . . . . . . . . . . . . . . . . . . 7–3 Mathematical Vector Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4 Absolute Value (Abs) . . . . . 7–5 Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Design Example . . . . . . . . . . . 7–9 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4 Restrictions . . 7–6 Parameters . . . . . . . . . . . . 7–11 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Design Example . . . . . . . . . . . . 7–6 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13 Parameters . 7–16 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10 Bit Extract (BitExtract) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15 Compare Equality (CmpEQ) . . . . . . . . . . . . . 7–6 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Complex Conjugate (ComplexConjugate) . . . . . . . . . . . 7–5 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Port Interface . . . . . . . . . 7–4 Complex Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4 Interactions with Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7 Add SLoad (AddSLoad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 AND Gate (And) . . . . . . . . . . 7–10 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Port Interface . . . . . . . . . . 7–10 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Interactions with Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ModelPrim Library Vector and Complex Type Support . 7–12 Channel In (ChannelIn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Port Interface . . . . . . . . . . . 7–13 Channel Out (ChannelOut) . . . . . . . . . . . . . . . . . . . .xi Chapter 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 © December 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5 Design Example . . 7–3 Element by Element Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 Bit Reverse (BitReverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Vector Type Support . . . . .

. . . . . . . . . . . . . . . . . . . . . . . 7–17 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–33 ForLoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–28 Dual Memory (DualMem) . . . . . . . . . . . . . . . . . . . . . 7–28 Port Interface . . . . . . . . . . . . . . . . . . . . . 7–17 Compare Less Than (CmpLT) . . . . . . . 7–18 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37 Left Shift (LShift) . . . . . . . . . . . . . . . . . . 7–19 Port Interface . . . . . . . . . 7–21 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–32 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–35 General Purpose Input (GPIn) . . . . . . . . . . . . . . . . . . . . . . . . . 7–18 Compare Not Equal (CmpNE) . . . . . . . . . . . . . . . . . . . . . . 7–31 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–30 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–23 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–30 Demultiplexer (Demux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22 Design Example . . . . . . . . . . . . . . . . . . . . . . 7–20 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36 General Purpose Output (GPOut) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–22 CORDIC . . . . 7–29 Port Interface . . . . . . . . . . . . . . . . . . 7–18 Port Interface . . . . . . . . . . . . . . 7–20 Convert . . . . . . . . . . . . . . . . . . . . 7–28 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17 Design Example . . . . . . . . . . . . . . . . . . . . . . . . 7–36 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17 Parameters . . . . . . . . . . . . 7–29 Parameters . . . . . . . . . . . . . . . . 7–31 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19 Constant (Const) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–24 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–32 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–32 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–37 Design Example . . . . . . . . . . . . . . . . . 7–27 Count Leading Zeros (CLZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–34 Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 7–26 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1–xii Compare Greater Than (CmpGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38 Parameters . 7–26 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–38 DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset Preliminary © December 2010 Altera Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–36 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–50 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7–53 © December 2010 Altera Corporation Preliminary DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset . . . . . . . . . . . 7–43 Multiply (Mult) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–40 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48 OR Gate (Or) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–42 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44 Multiplexer (Mux) . . . . . . . . . . . . . . . . . . . . . . . . 7–44 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–45 NAND Gate (Nand) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–45 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–47 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46 NOR Gate (Nor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–43 Parameters . . . . . . . . . . . . . 7–53 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–44 Parameters . . . . . . . . . . . . . . . . . . 7–42 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–51 Sequence . . . 7–39 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–47 Port Interface . . . . . . . . . . . . . . . . . . . . . . . 7–50 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–50 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–42 Minimum Value (Min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52 Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–39 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii Look-Up Table (Lut) . . . . . . . . . . . . . . . . . . . . . 7–45 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–51 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–47 NOT Gate (Not) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49 Sample Delay (SampleDelay) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–45 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48 Design Example . 7–51 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–46 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–51 Port Interface . . . . . . . . . . . . . . 7–44 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–52 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–48 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41 Design Examples . . . . . . 7–53 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–43 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–49 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–50 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–41 Maximum Value (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–40 Loop . . . . . . . 7–53 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 ModelVectorPrim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–54 Synthesis Information (SynthesisInfo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–55 Updated Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 7–56 XNOR Gate (Xnor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–54 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–58 Chapter 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset Preliminary © December 2010 Altera Corporation . . . . . . 9–4 Additional Information How to Contact Altera . . . . . . . . . 8–2 Chapter 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Categorized Block List Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1 Filter . . . . . . . . . . . . . . . . . . . . . 8–2 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . 7–54 Design Example . . . . . . . . . . . . . . . . . . . . . . . 7–57 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–55 Parameters . . . . . . . . . . . . . . . . . 7–56 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 ModelBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–55 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–57 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–54 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–58 Parameters . . . . . . . . . . . . . . . . . . . . 9–2 ModelPrim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4 Waveform Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1 FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–57 XOR Gate (Xor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–58 Port Interface . . . . . . . . . . . . . . . . . . . . . . . . ModelVectorPrim Library Sum of Elements (SumOfElements) . . . . . . .1–xiv Subtract (Sub) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0 Date December 2010 December 2010 Part Number HB_DSPA_ADV_UG-2.0 2.0 © December 2010 Preliminary Altera Corporation DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset .Section Revision Dates The following table shows the revision dates for the sections in this volume.0 HB_DSPA_ADV_LIB-2. Section DSP Builder Advanced Blockset User Guide DSP Builder Advanced Blockset Libraries Version 2.

xvi Section Revision Dates DSP Builder Handbook Volume 3: DSP Builder Advanced Blockset Preliminary © December 2010 Altera Corporation .

com HB_DSPA_ADV_UG-2. DSP Builder Advanced Blockset User Guide 101 Innovation Drive San Jose.0 Document Version: Document Date: 2.altera.Section I.0 December 2010 . CA 95134 www.

unless noted otherwise. and foreign patents and pending applications. . specific device designations. Altera assumes no responsibility or liability arising out of the application or use of any information. the trademarks and service marks of Altera Corporation in the U.S. and all other words and logos that are identified as trademarks and/or service marks are. All rights reserved. and copyrights. product. The Programmable Solutions Company. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty. but reserves the right to make changes to any products and services at any time without notice.S. maskwork rights. or service described herein except as expressly agreed to in writing by Altera Corporation. All other product or service names are the property of their respective holders.Copyright © 2010 Altera Corporation. the stylized Altera logo. and other countries. Altera products are protected under numerous U. Altera.

0 ■ Changes Made Added the following design example descriptions: Rectangular nested loop Triangular nested loop Sequential loops Partial loops Folded color space converter Folded single-stage IIR filter Folded 3-stage IIR filter Folded primitive FIR filter Hybrid direct form and transpose form FIR filter Digital predistortion forward path Run-time configurable decimating and interpolating half-rate FIR filter Matrix initialization of vector memories Matrix initialization of LUT Vector initialization of sample delay ■ Added General Primitive Library Guidelines June 2010 1. Replaces DSP Builder Advanced Blockset User Guide © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide .0 First published.About This Section Revision History The following table shows the revision history for this section. Date December 2010 Version 2.

iv About This Section Revision History DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation .

You can use the advanced blockset entirely independently of the DSP Builder standard blockset. and reduce hardware size. Filters in the blockset automatically use a high-clock rate to increase folding. pipelined hardware for your target Altera® FPGA device and clock rate. DSP Builder Standard and Advanced Blockset Interoperability. 1 The DSP Builder advanced blockset uses Simulink fixed-point types for all operations. f For information about interoperability with the DSP Builder standard blockset. refer to the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook. The advanced blockset is based on a high-level synthesis technology that optimizes the high-level. DSP Builder writes out the hardware as plain text VHDL. Libraries The advanced blockset comprises the following Simulink libraries: ■ ■ ■ ■ ■ ■ ■ Base blocks FFT blockset Filters (ModelIP) ModelBus ModelPrim ModelVectorPrim Waveform synthesis (ModelIP) f For more information about the advanced blockset libraries. refer to Chapter 8. By specifying your desired clock frequency. About the DSP Builder Advanced Blockset The DSP Builder advanced blockset adds specialized Simulink libraries to the MATLAB design environment that allow you to implement DSP designs quickly and easily. untimed netlist into low level. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . The combination of these features allows you to create a design without needing detailed device knowledge.1. and generate a high quality implementation that runs on a variety of FPGA families with different hardware architectures. you can solve timing closure issues by generating register transfer level (RTL) code that pipelines to meet your goal. with scripts that integrate with the Quartus® II software and the ModelSim simulator. or you can embed its blocks in top-level DSP Builder designs that use the standard blockset.

and maintains an internal data flow representation of your design. whether explicitly from primitive delays. A design may include any number of subsystems that can combine blocks from the DSP Builder advanced blockset with blocks from the MATLAB Simulink libraries. the design implements delay that requires more than 20 LEs (two LABs) as a block of RAM. or M144K). 1 DSP Builder applies globally the options in the Control block to your design.1–2 Chapter 1: About the DSP Builder Advanced Blockset Libraries Base Blocks The top-level design of a DSP Builder advanced blockset design is a testbench and must include Control and Signals blocks. DSP Builder tries to balance the implementation between logic elements (LEs) and block memories (M512. M9K. or the high-order byte at the highest address and the low-order byte at the lowest address (little endian). You can also create automatic RTL testbenches for each subsystem in your design example and specify the depth of signals that DSP Builder includes when your design example simulates in ModelSim. synthesizes the individual primitive or ModelIP blocks into RTL. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . Control Block The Control block traverses your design. A single Control block must be present in your top-level model. The trade-off depends on the target FPGA family. Memory-Mapped Bus Interface You can specify the address and data bus widths that the memory-mapped bus interface use and specify whether DSP Builder stores the high-order byte of the address in memory at the lowest address and the low-order byte at the highest address (big endian). or in the ModelIP blocks. Memory and Multiplier Trade-Off Options When your design synthesizes to logic. DSP Builder creates delay blocks. and to automatically load your design into the ModelSim simulator or the Quartus II software. For example. The functional subsystem containing a Device block marks the top-level of the FPGA device and specifies the target device that the generated hardware uses. Hardware Generation Options in the Control block specify whether hardware generates for your design example and the location of the generated RTL. if a block of RAM occupies the silicon area of two logic array blocks (LABs). but as a guideline the trade-off is set to minimize the absolute silicon area the design uses. There may be cases when you want to influence this trade-off. Simulink simulation uses the internal representation of your design example and to write out the RTL and scripts for other tools. Altera provides other blocks to control and view the signals in your design. M4K.

but for some device families there may be different sizes of block memory available. use these resources instead of a soft multiplier made from LEs. To never use block memory for simple delays. If the hard multiplier threshold value is 100. CDualMem Dist RAM Threshold Description Trade-off between small and medium RAM blocks. enter a larger number. To make more delays use block RAM. enter a lower number. implement memory in medium block RAM (M4K. M-RAM blocks are never used. Default (–1) Usage 1.000. For families with only one type of memory block (for example Cyclone® II with only M4K. Implement any dual-port memory in a block memory. This threshold only applies to implementing simple delays in memory blocks or LEs. For example a value in the range 20 to 30. This threshold is similar to the CDelay RAM Block Threshold except that it applies only to the dual-port memories in the ModelPrim library. The hard multiplier threshold value corresponds to the number of LEs that save a multiplier. If you change this threshold to a lower value such as 200. M144K). Use Stratix III devices with the default threshold value (-1). DSP Builder uses M-RAM for the implementation. However. set to a very large number. If you set a large value such as the default of 1. For example. a 2-bit × 10-bit multiplier consumes very few LEs. Notes Notes M-RAM Threshold Description Default (–1) Usage Trade-off between medium and large RAM blocks. You cannot push back dual memories into LEs.000. If any delay's size is such that the number of LEs is greater than this parameter. 20 bits. these blocks always use some memory blocks. M9K) or use larger M-RAM blocks (M512K.280 bits as MLABs. For example 100. or Cyclone III with only M9K) this threshold has no effect. the threshold that determines whether to use M9K blocks rather than MLAB blocks on Stratix III and Stratix IV devices.280 bits. 1. you are allowing 100 LEs. Table 1–1. Memory and Multiplier Trade-Offs CDelay RAM Block Threshold Description Default (–1) Usage Trade-off between simple delay LEs and small ROM blocks. an 18×18 multiplier (that requires approximately 182 = 350 LEs) does not transfer to LEs because it requires more LEs than the threshold value. For larger delays. Implement delays of length less than 3 cycles in LEs because of the block RAM behavior.280 bits as M9Ks and implement dual memories less than or equal to 1.000 bits. If the number of bits in a memory or delay is greater than this threshold. For example. implement dual memories greater than 200 bits as M9Ks and implement dual memories less than or equal to 200 bits as MLABs. Hard Multiplier Threshold Description Trade-off between hard and soft multipliers. To use fewer block memories. DSP Builder builds some ModelIP blocks with dual memories.000. the design implements the delay as a block RAM.000 bits. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . The threshold value determines which medium size RAM memory blocks to use instead of small memory RAM blocks. Therefore. regardless of the value of this threshold.Chapter 1: About the DSP Builder Advanced Blockset Libraries 1–3 Table 1–1describes the memory and multiplier threshold trade-offs and provides some usage examples. rather than LEs. such as 10. to implement dual memories greater than 1. For devices that support hard multipliers or DSP blocks. DSP Builder implements a 16×4 multiplier that requires approximately 64 LEs as a soft multiplier with this setting. for example dual and multirate filters.

when interfacing to external logic. Set a values of approximately 10 to implement a 24×16 multiplier as a 36×36 multiplier. The Signals block provides a mechanism to name the clock. you are not even allowing the adder to combine the two multipliers. With this value. and memory bus signals that the RTL uses. the design modifies the amount of pipelining that hard multipliers uses. With this value. you must de-activate the separate bus clock option for the Signals block when using Cyclone device families. If the depth is greater than 2. and also provides information about the clock rate. The DSP Builder advanced blockset uses a single system clock to drive the main datapath logic. and. and pipelines long adders into smaller adders based on the absolute clock speed in relation to the FPGA family and speed-grade you specify in the device block. Set a value of approximately 300 to keep 18×18 multipliers hard. To determine the pipelining required at each stage of logic. which you should place at the top level of your model. optionally. For this reason. reset. Signals Block Each design example must have a Signals block. Notes DSP Builder converts multipliers with a single constant input into balanced adder trees. a second bus clock to provide an external processor interface. so this setting builds the hybrid multipliers that are required. Essentially you are allowing a high number (1000) of LEs to save an 18×18 multiplier. DSP Builder implements A 24×18 multiplier as 6×18 + 18×18. which is generally much lower than the size of a full soft multiplier. This information is important for the following reasons: ■ To calculate the ratio of sample rate to clock rate determine the amount of folding (or time-division multiplexing) in the ModelIP filters.1–4 Chapter 1: About the DSP Builder Advanced Blockset Libraries Table 1–1. If DSP Builder combines two non-constant multipliers followed by an adder into a single DSP block. The rationale for this is that it is most efficient to drive the logic at as high a clock rate as possible. The standard DSP Builder blockset is better for managing multiple clock domains for example. Set a value of approximately 1000 to implement the multipliers entirely as LEs. therefore the system has to burn a 36×36 multiplier in a single DSP block. but transform smaller multipliers to LEs. The Signals block specifies the details for the clocks and resets that drive the generated logic. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . DSP Builder compares the hard multiplier threshold with the estimated size of the adder tree. Memory and Multiplier Trade-Offs Default (–1) Usage The default (–1) means always use hard multipliers. This occurs automatically where the depth of the tree is not greater than 2. For example. DSP Builder implements 24×18 as two 18×18 multipliers. even if there is a large threshold. ■ 1 Cyclone device families do not support a separate bus clock due to the limited multiple clock support in block RAMs on those devices. DSP Builder does not convert the multiplier into LEs.

Sweden. without tracking block latencies around your design. f For information about the Radix-22 algorithm. at the expense of a little more logic by sharing them when the sample rate is below the clock rate. Stratix IV. A design that uses a vector input of width N is the same as connecting N copies of the block with a single scalar connection to each. such as multipliers. DSP Builder does not specify the timing relationship between different sets of inputs and outputs. Stratix GX. You should use the protocol described in “Protocol for Connecting IP” on page 1–10 to decode outputs. The DSP Builder advanced blockset supports the following target Altera device families: Stratix. Parameters on the ChannelIn and ChannelOut blocks allow the control of automated folding for the primitive subsystems. refer to A New Approach to Pipeline FFT Processor – Shousheng He & Mats Torkleson. However. or GPOut block line up correctly in time at their boundaries. Stratix II. You do not need to understand the details of the underlying FPGA architecture. as the primitive blocks automatically map into efficient FPGA constructs. Signals that pass through a single ChannelIn. Stratix II GX.Chapter 1: About the DSP Builder Advanced Blockset Libraries 1–5 Device Block The Device block marks a particular Simulink subsystem as the top-level of an FPGA device and allows you to specify the target device and speed grade for the device. GPIn. Lund University. and does not guarantee any fixed relationship if you change clock frequencies or devices. ChannelOut. f For more information on folding. All blocks above this level of hierarchy become part of the testbench. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . you can use a Delay block and let DSP Builder decide how to implement that delay. become part of the RTL design. refer to “Folding” on page 7–1. Cyclone III. You can design and debug quickly with zero-latency blocks. Most arithmetic and memory ModelPrim blocks allow you to use Simulink 1-D vector (array) and complex types. FFT Blockset The FFT Blockset library contains common blocks that support fast Fourier transform (FFT) design. Stratix III. DSP Builder displays and calculates the additional latency that your design requires to meet timing constraints as a parameter on the ChannelOut block. For example. Department of Applied Electronics. Folding allows DSP Builder to implement the design with fewer expensive resources. ModelPrim Blocks The ModelPrim library allows you to create fast efficient designs captured in the behavioral domain rather than the implementation domain by combining primitive functions. and Arria® II GX. rather than exact clock counting where possible. All blocks in subsystems below this level of hierarchy. It also includes several blocks that support the Radix-22 algorithm. Cyclone II.

If you want to change the data type format in a way that preserves the numerical value. Specify via dialog: additional fields that allow you to set the output type of the block explicitly. If you specify the output data type as sfix32_En28. Using the Specify via Dialog Option Specifying the output type with the dialog box is a casting operation. which exceeds the maximum positive number that DSP Builder can store in the number of bits of the input. which adds the corresponding hardware. just the underlying bits and never adds hardware to a block—just changes the interpretation of the output bits.5. and a 1*1 input gives an output value of 4. Adding a Convert block directly after a primitive block allows you to specify the data type in a way that preserves the numerical value. Inherit via internal rule with word growth: the number of fractional bits is equal to the maximum of the number of fractional bits in the input data types. with blocks potentially growing the word length where necessary. f For information about the options that DSP Builder supports by each block. refer to the ModelPrim Library chapter in the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook. For example.1–6 Chapter 1: About the DSP Builder Advanced Blockset Libraries Specifying the Output Data Type Many of the primitive blocks provide the following options in their Block Parameters dialog box to inherit or specify the output data type: ■ Inherit via internal rule: the number of integer and fractional bits is equal to the maximum of the number of bits in the input data types. For example. use a Convert block. the output numerical value is effectively divided by two and a 1*1 input gives an output value of 0. or Inherit via internal rule with word growth. If there are loops in your design. This operation does not preserve the numerical value. the output numerical value is effectively multiplied by four. a Mult block followed by a Convert block. ■ ■ ■ In general. a Mult block with both input data types specified as sfix16_En15 naturally has an output type of sfix32_En30. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . you can set the output type of a primitive block to Inherit via internal rule. The number of integer bits is the maximum of the number of integer bits in the input data types plus one. This additional word growth allows for subtracting the most negative number from 0. The type propagates through your design naturally. use the dialog box to specify the output type for at least one block in the loop. Boolean: the output type is Boolean. If you specify output data type of sfix32_En31. with input values 1*1 always gives output value 1. Word growth occurs if the input data types are not identical.

Consider the following two main cases: © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . and all those below as a unit. After you run a Simulink simulation. Use when you want full control over the pipelining in a system. The inputs and outputs to this subsystem become the primary inputs and outputs of the RTL entity that creates. This style takes full advantage of the automatic pipelining capability. the online Help page for the SynthesisInfo block updates to show the latency. port interface. Reads in and flattens your design example for any subsystem that contains a SynthesisInfo block. Xor) and the Simulink Mux and Demux blocks do not require a register. adds enough pipeline stages to meet that clock frequency. 1 The SynthesisInfo block can be at the same level as the Device block (if the synthesizable subsystem is the same as the generated hardware subsystem). For example. Or. However. If no SynthesisInfo block is present. The algorithm performs the following operations: 1. WYSIWYG Style WYSIWYG is the default style of operation. DSP Builder flattens and synthesizes the subsystem. Based on the absolute clock frequency requested. Not. 2.Chapter 1: About the DSP Builder Advanced Blockset Libraries 1–7 SynthesisInfo Block The ModelPrim library includes a SynthesisInfo block that sets the synthesis mode and labels a subsystem described by primitive blocks as the top-level of a synthesizable subsystem tree. Scheduled Style The Scheduled style of operation uses a pipelining and delay distribution algorithm that creates fast hardware implementations from an easily described untimed block diagram. Nor. 1 The primitive logic blocks (And. The preceding block absorbs the delay primitive to satisfy its delay requirements. the style defaults to WYSIWYG and DSP Builder issues error messages if there is insufficient delay. 1 Altera recommends the Scheduled style of operation. it is often convenient to create a separate subsystem level that contains the Device block. DSP Builder issues error messages if there is insufficient delay. Two styles of operation exist during synthesis: WYSIWYG and Scheduled. you may pipeline long adders into several shorter adders. and estimated resource utilization for the current primitive subsystem. Builds an internal graph to represent the logic. Refer to the design examples for some examples of design hierarchy. Xnor. Nand. This additional pipelining helps reach high clock frequencies. A Delay primitive must follow every primitive that requires registering (such as an adder or multiplier). 3.

but potentially more at higher clock rates Two input multiplexers: 1 delay with potentially more for large number of inputs and at high clock rates Multipliers: 3 cycles or 4 at higher clock rates ■ When you select the Scheduled style. feed-forward datapaths are balanced to ensure that all the input data reaches each functional unit in the same cycle.1–8 Chapter 1: About the DSP Builder Advanced Blockset Libraries ■ The simpler case is feed-forward. one or more lumped delays exist. distributes delay around the functional units as required. and leaves any residual delay as lumped delay elements. ModelBus Blocks The ModelBus library provides memories and registers that you can access in your DSP datapath with an external interface. observe a set of simultaneous constraints. ModelIP Blocks The ModelIP libraries include parameterizable multichannel filters and waveform synthesis blocks that allow you to quickly create designs for digital front-end applications. you can optionally specify a latency constraint limit that can be a workspace variable or expression but must evaluate to a positive integer. complex mixers. This library also includes blocks that you can use to simulate the bus interface in the Simulink environment. When there is insufficient delay to distribute. Typically. and fractional-rate FIR filters. When no loops exist. The following list gives the delay requirements for some typical blocks: ■ ■ ■ ■ Boolean logic operations: 0 delay Adders: 1 delay. After analysis. an error generates. and finite impulse response (FIR) filters including single-rate. The Waveform Synthesis library contains a numerically controlled oscillator (NCO). and real mixers. DSP Builder inserts delays on all the non-critical paths to balance out the delays on the critical path. You can use these blocks to configure coefficients or run-time parameters and to read calculated values. Altera provides the ModelIP blocks in the following libraries: ■ The Filters library contains several decimating and interpolating cascaded integrator-comb (CIC). multi-rate. DSP Builder creates all loops with a delay to avoid combinational loops that Simulink cannot analyze. ■ DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . Because loops can intersect or be nested with each other. Preserve the delay around the loop for correct operation. The synthesis engine solves these constraints. therefore the functional units borrow delays from the lumped delay that need them. The case with loops is more complex.

To display the latency that a ModelIP block adds. 1 You cannot use latency constraints with folding. 'latency') You can also use this command in an M-script. These blocks are 100% cycle accurate at their boundaries. For the blocks in the Filters library. add the %<latency> parameter as annotation on the block. and memory interface. by the time it updates and sets on the ModelIP block. your must run once with end time 0. In fact. and resource utilization. After you run a simulation. to create glue logic around other subsystems. so are not cycle accurate.Chapter 1: About the DSP Builder Advanced Blockset Cycle Accuracy and Latency 1–9 After you run a Simulink simulation. there is not even a one-to-one mapping between the blocks in the Simulink model and the blocks implement your design in RTL. If you are scripting the whole flow. These blocks are 100% cycle accurate and the Simulink behavior represents exactly the RTL behavior. The Boolean logic and delay blocks are cycle accurate. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . the added latency shows as a text annotation below the block. The latency of the block displays on the ChannelOut mask. ■ ■ You can also use primitive blocks outside of synthesizable subsystems. such as the FIR and CIC filters. You can turn on display of the latency added by each block. This information typically includes the latency. Synthesized primitive block designs from the ModelPrim library. the updated Help page also includes details of the parameterization. The boundary between the untimed block and the outsized. it is too late to initialize the delays elsewhere. For example when you want to use the returned latency value to balance delays with external circuitry. but other primitive blocks are not. You must run your design twice after any changes to make sure that you have the correct latency. 1 If you use an M-script to get this parameter and set latency elsewhere in your design. This block models the additional delay that the RTL introduces. port interface. The primitive blocks are untimed circuits. select the block and type the following command: get_param(gcb. input and output data formats. Cycle Accuracy and Latency The DSP Builder advanced blockset supports the following design styles: ■ ModelIP blocks designs. To read the added latency value for a ModelIP block (or for the ChannelOut ModelIP block). DSP Builder updates the online Help page for each ModelIP block to show specific design documentation describing its implementation in your design. so that data going in to the ChannelOut block delays internally. therefore interfacing to other blocks is straightforward. cycle accurate block is the ChannelOut block. and then run again immediately with the desired simulation end time. before DSP Builder presents it externally. It is this decoupling of design intent from design implementation that gives the productivity benefits.

Figure 1–1 shows the Interpolating FIR filter design example. During this clock cycle. For example.1–10 Chapter 1: About the DSP Builder Advanced Blockset Protocol for Connecting IP f For more information about latency. valid. because you can simply decode the valid and channel signals to determine when to capture the data in any downstream blocks. the channel carries an 8-bit integer channel identifier. These three signals connect most of the blocks in a DSP Builder advanced blockset design. DSP Builder preserves this channel identifier through the datapath so that you can easily track and decode data. refer to “Latency Management” on page 6–1. DSP Builder distributes the control structures in each block of your design. and counting cycles. valid. Interpolating FIR Filter Connections The design example uses just the three data. Protocol for Connecting IP Use the three signals data. Figure 1–1. and channel signals to connect the FilterSystem and ChanView block. Data on the data wire is only valid when DSP Builder asserts the valid wire high. This simple protocol is easy to interface with external circuitry when you require and avoids balancing delays. and channel to connect the ModelIP or synthesized subsystems. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation .

For an example that connects NCO. Figure 1–2 shows how a splitter extracts the real and imaginary channels when connecting a CIC or FIR filter to the ComplexMixer. Therefore if the sample rate is less than or equal to the value you specify in the dialog box. the valid signal is an enable. Similarly. Use a primitive subsystem to implement this logic. That is. If a FIR filter needs to use flow control. DSP Builder guarantees all signals that connect to ChannelOut blocks line up in the same clock cycle. The design may require some splitting or combining logic when using the mixer blocks. and ComplexSampleDelay blocks. valid. The ModelIP filters all use the same protocol with an additional simplification—DSP Builder produces all the channels for a frame in a multichannel filter in adjacent cycles. refer to “16-Channel DUC” on page 2–8.Chapter 1: About the DSP Builder Advanced Blockset Protocol for Connecting IP 1–11 In the FIR filters. refer to “16-Channel DUC” on page 2–8. pull down the valid signal between frames of data—just before you present channel 0 data. channel> protocol connects all CIC and FIR filter blocks and all subsystems with primitive blocks. and CIC Filter blocks. Figure 1–2. However. Use this feature when the sample rates of the filters are not all divisible by the clock rate. In primitive subsystems. The same <data. you must ensure all the signals arrive at a ChannelIn block in the same clock cycle. data can pass more slowly to the filter. NCO. The blocks in the Waveform Synthesis library support separate real and complex (or sine and cosine) signals. The ModelIP blocks follow the same rules. take care to generate the first valid signal when there is some real data and to connect this signal throughout the design. The valid signal is a stream synchronization signal. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . 1 Always. the delays on all paths from and to these blocks balance. use a combiner when connecting the output from a mixer to a downstream filter. Thus it is easy to connect ModelIP and primitive subsystems. which is also a requirement on the filter inputs. Real Mixer. Connecting a Filter to a ComplexSampleDelay For an example that connects a CIC Filter.

Table 1–2 shows the estimated resources for a 49-tap symmetric FIR filter. The ratio of system clock frequency to sample rate determines the amount of resource saving except for a small amount of additional logic for the serializer and deserializer. TDM to Save Hardware Resource To achieve the TDM factor. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . Table 1–2. the design requires a serializer and deserializer before and after the reused hardware block to control the timing.1–12 Chapter 1: About the DSP Builder Advanced Blockset Time-Division Multiplexing Time-Division Multiplexing Use time-division multiplexing to optimize hardware utilization. Figure 1–3. you can re-use the same hardware. the resource consumption is the same as for the 2 × sample rate case. For example. When the clock rate is set to 4 × sample rate. Example Resource Saving for a 49-Tap Single rate FIR Filter Clock Rate (MHz) 72 144 288 72 Sample Rate (MSPS) 72 72 72 36 Logic 2230 1701 1145 1701 Multipliers 25 13 7 13 Memory Bits 0 468 504 468 TDM Factor 1 2 4 2 When the sample rate equals the clock rate. The time-division multiplexed (TDM) factor (or folding factor) is the ratio of the clock rate to the sample rate. you can halve the required hardware (Figure 1–3). By clocking a ModelIP block faster than the sample rate. because the filter is symmetric you just need 25 multipliers. the number of multipliers the design requires drops by half to 13. by implementing a filter with a TDM factor of 2 and an internal clock multiplied by 2. If the clock rate stays the same while the new data sample rate is only 36 MSPS (million samples per second). the number of multipliers the design requires drops to 7. When you increase the clock rate to 2 × sample rate.

If a decimating filter requires a smaller vector on the output.Chapter 1: About the DSP Builder Advanced Blockset Multichannel Operation 1–13 1 You can implement the TDM factor automatically in primitive subsystems where the sample rate is less than the clock rate by enabling folding (refer to “Folding” on page 7–1). DSP Builder uses the same paradigm on outputs. 10 channels at 20 MSPS require 10×20 = 200 MSPS aggregate data rate. Use a mask variable to create a parameterizable component. Sequence and counter blocks regenerate valid and channel signals. data from individual filters use the TDM factor onto the output vector automatically. refer to the “Multi-Channel IIR Filter” on page 2–19. Multichannel Operation To build multichannel systems directly use the required channel count. and you can uses the channel indicator at any point to filter out some channels. 1 Each channel is an independent data source. To merge two streams. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . If the system clock rate is set to 100 MHz. two wires carry this data. Each ModelIP block determines the input and output wire counts. sample rate. for example a FIR filter. and number of channels. if data going into a block is a vector requiring multiple instances of. The block diagrams use vectors of wires to scale without cutting and pasting multiple blocks. where it represents high data rates on multiple wires as vectors. Primitive Subsystems. DSP Builder numbers the channels 0 to (N-1). draw out the logic required for your design to create a single channel version. to avoid using glue filters for custom logic. This approach is unlike traditional methods because you do not need to manually instantiate two ModelIP blocks and pass a single wire to each in parallel. ■ Vectorized Inputs The data inputs and outputs for the ModelIP blocks can be vectors. increase all the delays by the channel count required. For an example. The primitive subsystems contain ChannelIn and ChannelOut blocks. To create multichannel logic. based on the clock rate. which is useful when the clock rate is insufficiently high to carry the total aggregate data. An IF Modem design requires two channels for the complex pair from each antenna. rather than create a single channel system and scale it up. but do not have explicit support for multiple channels. DSP Builder creates some logic to multiplex the data. This is simple to conceptualize. and so the Simulink model uses a vector of width 2. To transform to a multichannel system. Each ModelIP block internally vectorizes. Consider the following two cases: ■ ModelIP blocks typically take a channel count as a parameter. DSP Builder creates multiple FIR blocks in parallel behind a single ModelIP block. For example. The ModelIP blocks are vectorizable.

■ The Period (or TDM factor) is the ratio of the clock rate to the sample rate and determines the number of available time slots: Period = max(1. Resolve vector width errors by carefully changing the sample rates. an interpolate by two FIR filter may have two wires at the input. If there is a rate change. ChanWireCount = 1. Channelization Use the following variables to determine the number of wires and the number of channels each wire carries by parameterization: ■ ■ ■ ClockRate is the system clock frequency. ChanCount is the number of channels. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . floor(ClockRate/SampleRate)) ■ The number of channel wires the design requires to carry all the channels is the number of channels divided by the TDM factor (except for supersampled filters): ChanWireCount = WiresPerChannel × WireGroups ■ The number of channels carried per wire is the number of channels divided by the number of channels per wire: ChanCycleCount = ceil(ChanCount/WireGroups) 1 The channel signal counts through 0 to ChanCycleCount – 1. Each ModelIP block in your design is internally vectorized to build multiple blocks in parallel.1–14 Chapter 1: About the DSP Builder Advanced Blockset Multichannel Operation Any rate changes in the ModelIP block affect the output wire count. The ModelIP block performs any necessary multiplexing and packing. multiple wires are required. SampleRate is the data sample rate per channel (MSPS). DSP Builder packs the output channels into the fewest number of wires (vector width) that supports that rate. Figure 1–4 on page 1–15 shows how a TDM factor of 3 combines two input channels into a single output wire (ChanCount = 2. The blocks connected to the inputs and outputs must have the same vector widths. If the number of channels is greater than the period. 1 Channels are enumerated from 0 to ChanCount – 1. 1 Most ModelPrim blocks also accept vector inputs. the output aggregate sample rate doubles. which Simulink enforces. ChanCycleCount = 2). but three wires at the output. For example. such as interpolating by two. ■ The WiresPerChannel is the number of wires per channel: WiresPerChannel = ceil(SampleRate/ClockRate) ■ The WireGroups is the number of wire groups to carry all the channels regardless of channel rate: WireGroups = ceil(ChanCount / Period).

Figure 1–5. Channelization for Two Channels with a TDM Factor of 3 Note to Figure 1–4: (1) In this example. Figure 1–4. ChanWireCount = 2.Chapter 1: About the DSP Builder Advanced Blockset Multichannel Operation 1–15 Figure 1–5 on page 1–15 shows how a TDM factor of 3 combines four input channels into two wires (ChanCount = 4. Channelization for Four Channels with a TDM Factor of 3 Note to Figure 1–5: (1) In this example. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . DSP Builder distributes the channels evenly on each wire leaving the third time slot as do not care on each wire. The value of the channel signal while the valid signal is low does not matter. three available time slots exist in the output channel and every third time slot has a “don’t care” value when the valid signal is low. two wires are required to carry the four channels and the cycle count is two on each wire. ChanCycleCount = 2).

For more than a single data wire. Figure 1–8 shows four channels simultaneously on four wires. DSP Builder uses the channel signal for synchronization and scheduling of data. Figure 1–6 shows the case for four channels of data on one data wire with no invalid cycles. enumerated 0 to ChanCount – 1. but specifies the synchronous channel data alignment across all the data wires. for ChanWireCount > 1. not a wire for each data wire.1–16 Chapter 1: About the DSP Builder Advanced Blockset Multichannel Operation 1 The generated Help page for the block shows the input and output data channel format that the FIR or CIC filter use after you have run a Simulink simulation. the channel signal is the same as a channel count. Figure 1–7. rather than the actual channel number: it counts from 0 to ChanCycleCount –1 rather than 0 to ChanCount –1. Figure 1–7 shows four channels on two wires with no invalid cycles. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . for ChanCycleCount = 1. Four Channels on Two Wires The channel signal remains a single wire. For example. It counts over 0 to ChanCycleCount –1. Figure 1–6. the channel signal specifies the channel data separation per wire. However. it is not equal to the channel count on data wires. Four Channels on One Wire For a single wire. It specifies the channel data separation per wire. The channel signal counts from 0 to ChanCycleCount – 1 in synchronization with the data. Thus. the channel signal is the same as the channel count.

f Memory-Mapped Interfaces DSP Builder includes a pipelined memory-mapped interface for all the programming registers in a design. Four Channels on Four Wires Simulink shows the ModelIP block as a single block. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . but the data input and output wires from the ModelIP blocks show as a vector with multiple dimension. refer to AN 544: Digital Modem Design with the DSP Builder Advanced Blockset. control registers for NCO frequencies. these registers include coefficient registers for filters. and individual control registers that you can use for any purpose such as providing programmable scaling. Multiple wires accommodate all the channels and the Simulink model uses a vector of width 2 (Figure 1–9). Figure 1–9.Chapter 1: About the DSP Builder Advanced Blockset Memory-Mapped Interfaces 1–17 Figure 1–8. Simulink and Hardware Representations of a Single Rate FIR Filter 1 To display the ChanWireCount in Simulink. point to Port/Signal Displays in the Format menu and click Signal Dimensions. For example. For more information about channelization in a real design. DSP Builder gathers the register map for your design into an XML file that it processes to produce design documentation to display in updated online Help for the Control block. in the demo_ddc design.

and write enable. Memory-mapped interface: allows access to the internal data coefficients and consists of inputs address. data. Figure 1–11 shows a write cycle (time-steps 2 to 6) and a read cycle (time-steps 10 to 14). Figure 1–10 shows typical output data. valid. with a single gap of non-valid data until the next sample time. and channel.1–18 Chapter 1: About the DSP Builder Advanced Blockset Hardware Interfaces Hardware Interfaces A typical ModelIP block has the following main interfaces: ■ Control signals: a synchronous clock and two asynchronous reset signals. DSP Builder writes contiguously the data for each channel for each sample. You must provide the data for multiple channels on consecutive cycles. and a_0 for a 4-channel FIR filter with 10 cycles. The reset returns internal state machines to initialized states. write data.t2 is the time between successive data samples for channel 0). twice as many valid cycles exist as on the input. and providing the channel input all during the same clock cycle. To process the channels (t12 . valid and channel signals as the input. Input port: consists of three input signals. ■ Figure 1–10. Figure 1–10 shows typical inputs data a_v. and outputs read data and read valid. The interpolation rate determines the output data timing. DSP Builder writes the data to the core by asserting the valid signal. Timing diagram for a Typical FIR Filter Interface ■ Output port: uses the same data. ■ DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . You may use a separate bus clock for this interface. a_c. For interpolation of two.

Sample Rate and Clocks The sample rate is the rate at which real data is clocked through the system at any point. When you start to tune the performance of your model. Using fixed-point types allows you to preserve the extra information of binary point position through hardware blocks. It builds the necessary bus decode logic to access all registers in the datapath. Fixed-point Representation DSP Builder uses the built-in Simulink fixed-point types to specify all the signals in a DSP Builder advanced blockset design. a fixed-point type change propagates through your design. Although. because you can display the signals as familiar floating-point types. Design Semantics Simulink uses the time-step representation of the system clock rate to represent a design. Memory-Mapped Registers Timing Diagram The DSP Builder advanced blockset uses these interfaces to build up chains of filters without additional glue logic. In a multi-rate environment. even with sample rate changes. Thus it is easy to debug your design.Chapter 1: About the DSP Builder Advanced Blockset Design Semantics 1–19 Figure 1–11. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . the sample rate may vary along the datapath. Other Simulink-based design systems disable the hardware based on the sample time (wasting hardware that is inactive for much of the time). so that it is easy to perform rounding and shifting operations without manually tracking the interpretation of an integer value. with all downstream calculations automatically adjusted. the Simulink multiple sample-time features does not represent them. the multi-rate system has multiple sample rates.

1 The memory-mapped input and output registers clear when the system is reset but DSP Builder retains the contents of the dual memory that the FIR Filter. the bus clock can have any frequency. NCO. refer to the Avalon Interface Specifications. The internal representation makes simulation fast. Running the clock as an integer fraction of the system clock rate ensures that no timing issues exist and that both clocks have co-incident edges. The bus clock is usually not performance critical and can run at a lower clock rate. and then run the simulation.1–20 Chapter 1: About the DSP Builder Advanced Blockset Simulation The datapath components in the DSP Builder advanced blockset use a single clock rate. and ensures bit and cycle accuracy. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . and ModelBus blocks use. Simulink performs this process very quickly. For information about the Avalon-MM Interface. each ModelIP block resynthesizes into an internal representation of the hardware components and Simulink writes it out as VHDL RTL. which allows easier timing closure in many cases. In many cases. An external processor uses a separate bus clock to read and write any primitive registers or shared memories and ModelIP block parameters through an Avalon® Memory-Mapped (Avalon-MM) interface. and gives greatly increased productivity over traditional flows where you must configure your design in an external tool. Set the clock rates in the Signals block (“Signals Block” on page 1–4). f Simulation At the start of each Simulink simulation run. import it into the simulator.

This file contains information about all the files DSP Builder requires to process your design in the Quartus II software.qip file in a lower level subdirectory that references a .qip and . the RAM is part of ModelIP blocks (such as the CIC. This directory structure uses the same hierarchy as the subsystems in your design with the files in lower level directories referenced from a corresponding file in its parent directory. For example.add. and . and may also contain empty black boxes for Simulink blocks that are not fully supported. A . This is the top-level testbench file. which translates into HTML on demand for display in the MATLAB Help viewer.tcl <model name>.qip file. Also additional .vhd An XML file containing information about each block in the advanced blockset.qip) file in the <model name> subdirectory that references a . The file includes a reference to any .xml rtl\<model name> subdirectory <block name>. Helper function that ensures a pathname reads correctly in ModelSim.stm safe_path.xml *. Any RAM in your design may generate Intel format hexadecimal (. there is a Quartus II IP (. An XML file that describes the attributes of your model.hex) files to initialize the RAM. Usually.xml <subsystem>.qip file in the next level of the subsystem hierarchy.vhd <model name>_<subsystem>_entity. DSP Builder generates a VHDL file for each component in your model.tcl files reference to ensure that pathnames read correctly in the Quartus II software.qip file for a subsystem containing such blocks has the initializing . which defaults to .do. .tcl files exist that DSP Builder automatically calls from the corresponding files in the top-level of your model.xml <model name>_entity. Stimulus files.\rtl (relative to the working directory that contains the .xml.mdl file).vhd safe_path_msim.add.qip file in the next lower level and so on throughout your design hierarchy.vhd rtl\<model name>\<subsystem> subdirectories Separate subdirectories exist for each hierarchical level in your design. Generated Files for the DDC Design Example File rtl directory <model name>.xml <model name>. Table 1–3. An XML file that describes the boundaries of the system (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). which include additional .qip <model name>_<block name>. Helper function that the . Description <model name>..vhd. An XML file that describes the boundaries of a subsystem as a block-box design (for Signal Compiler in designs that combine blocks from the standard and advanced blocksets). It may contain non-synthesizable blocks. or FIR Compiler) which are expandable to lower-level functions such as RAM or ADDSub. qip.add.hex files referenced from the . NCO. and .stm files describing the blocks in each level. DSP Builder generates the files in a directory structure at the location you specify in the Control block. This script loads the VHDL files in this subdirectory and in the subsystem hierarchy below it into the Quartus II project.Chapter 1: About the DSP Builder Advanced Blockset Generated Files 1–21 Generated Files Table 1–3 lists the files that DSP Builder generates for an advanced blockset design. .tcl. An XML file that describes the attributes of a subsystem. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide .

you can add a reference to the . A TCl script that loads the generated hardware into SOPC Builder. source the . The Quartus II project file (. Quartus II settings file (. The project compiles with the . You can use this script to setup the Quartus II project.qpf. refer to “Exploring the Generated Files” on page 5–14 in the System Tutorial.qpf). These files contain all references to the files in the hardware destination directory that the Control block specifies and generate when you run a Simulink simulation.add.qip and other generated files.hex <subsystem>. This Tcl script exists only in the subsystem that contains a Device block. DDCChip. click Start Compilation on the Processing menu. and . f For information about the .wav.tcl Description Script that loads the subsystem automatic testbench into ModelSim. For example. For an example of the files that DSP Builder generates for a typical design.qsf. refer to the Quartus II Help.add.do <subsystem>/<block>/*. The .sdc <subsystem>. Alternatively. f DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . The project automatically loads into the Quartus II software.tcl file in the subsystem that contains the Device block.tcl <subsystem>_hw. Script that loads signals for the subsystem automatic testbench into ModelSim.qip file references all the files that the project requires.mdl file when you click on the Run Quartus II block. Use the Archive Project command in the Quartus II software to use this file to archive the project.tcl. DSP Builder creates the files DDCChip. . f For information about archiving projects.1–22 Chapter 1: About the DSP Builder Advanced Blockset Creating a Quartus II Project Table 1–3.qip for the demo_ddc design. and DDCChip.qip files have the same name as the subsystem in your design that contains the Device block.tcl scripts in the hardware destination directory. Generated Files for the DDC Design Example File <subsystem>_atb. refer to Table 1–3 on page 1–21.qip file for the top-level Quartus II project.do <subsystem>_atb. Creating a Quartus II Project DSP Builder create a Quartus II project in the design directory that contains the . Adding a DSP Builder Advanced Blockset Design to an Existing Quartus II Project To add an advanced blockset design to an existing Quartus II project. For information about using Tcl files in the Quartus II software. To compile your design. Design constraint file for TimeQuest support.qsf).qip file in this subsystem from the . refer to the Quartus II Help. These are Intel format Hex files that initialize the RAM in your design for either simulation or synthesis.

DSP Builder creates an RTL testbench for each separate entity in your design (that is. Loading in ModelSim To load an automatic testbench. then the testbench for each entity uses this data as a stimulus and compares the ModelSim output to the Simulink captured output. you can easily verify the correct behavior of the synthesis engine. If there is a mismatch at any cycle. By using these automatic testbenches. you must turn on Generate hardware and Create automatic testbenches in the Control block parameters and the ModelSim executable (vsim. to run the automatic testbench for the NCOSubsystem subsystem in the NCO design example. in single quotes) © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . select the demo_nco_NCOSubsystem_NCO_atb. and each synthesized primitive block writes out test vectors to a stimulus file (*. use an automatic testbench that DSP Builder creates for each ModelIP and primitive block. 1 To use either of these flows. This command has the syntax: run_modelsim_atb('model'. the simulation stops and an error issues. Automatic Testbench Flow Each ModelIP block. The automatic testbench flow uses a stimulus and capture method and is therefore not restricted to a limited set of source blocks. Comparison with RTL To compare the Simulink results with the generated RTL.Chapter 1: About the DSP Builder Advanced Blockset Comparison with RTL 1–23 Adding Advanced Blockset Components to SOPC Builder To add a DSP Builder component to SOPC Builder.do file you require. 'entity'. click Execute Macro on the Tools menu in ModelSim and select the . Running from a Command To run an automatic testbench from the MATLAB command line. and compare the output from the RTL to the output from the Simulink model. or simulate your design in an interactive ModelSim session.do file.exe) must be available on your path.stm) during a Simulink simulation run. These testbenches replay the test vectors through the generated RTL. The Simulink simulation stores data at the inputs and outputs of each entity during simulation. ['rtl_path']). add a directory that contains generated hardware to the IP Search Path in the SOPC Builder Options dialog box. f For an example of this procedure. for each ModelIP block and primitive subsystem). For example. where model = design name (without extension. use the command run_modelsim_atb. refer to “Instantiating the Design in SOPC Builder” on page 3–13. in single quotes) entity = entity to test (the name of a primitive subsystem or a ModelIP block. A result returns that indicates whether or not the outputs match when the valid signal is high.

.std_logic_1164 has changed. [runSimulation]. [runFit]). . Typical error messages have the following form: # ** Error (vcom-13) Recompile <path>altera_mf. .vhd(30): (vcom-1195) Cannot find expanded name: 'altera_mf.altera_mf_components because <path>iee. # ** Error: <path>mdl_name_system_subsystem_component. DSP Builder creates a new file with an automatically incremented suffix each time the testbench is run.out This output file includes the ModelSim transcript and is useful for debugging if you encounter any errors. These errors may occur when a ModelSim precompiled model is out of date..altera_mf_components'.mdl file. not starting simulation.. where model = design name (without extension. result] where: pass = 1 or 0 status = should be 0 result = should be a string such as: "# ** Note: arrived at end of stimulus data on clk <clock name>" An output file with the full path to the component under test writes in the working directory. Running All the Automatic Testbenches in a Design To automatically run all the individual automatic testbenches in a design use the command run_all_atbs. The return values are in the format [pass.. # At least one module failed to compile.1–24 Chapter 1: About the DSP Builder Advanced Blockset Comparison with RTL rtl_path = optional path to the generated RTL (in single quotes. but not automatically recompiled.. A similar problem may occur after making design changes when ModelSim caches a previously compiled model for a component and does not detect when it changes. For example: demo_fft_radix2_DUT_FFTChip_atb. delete the rtl directory. in single quotes) runSimulation = optional flag that runs a simulation when specified (if not specified. # ** Error: <path>vcom failed. . if not specified the path is read from the Control block in your model) For example: run_modelsim_atb('demo_fft16_radix2'.. status. Run this command from the same directory that contains the .6. This command has the syntax: run_all_atbs('model'. a simulation must run previously to generate the required files) runFit = optional flag which runs the Quartus II Fitter when specified DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . In either of these cases. 'FFTChip'). resimulate your design and run the run_modelsim_atb command again.

true. The output is written to the MATLAB command window. If it cannot delete the directory. run_all_atbs('demo_agc'. For example: Starting demo_agc Tests at 2009-01-23 14:58:48 demo_agc: demo_agc/AGC_Chip/AGC hardware matches simulation (atb#1): PASSED demo_agc: Quartus II compilation was successful. true). (Directory=. run_all_atbs('demo_agc'. If you run the Quartus II Fitter. run the following command: getBlocksWithATBs(‘model’) 1 You must have run a simulation of the design before running this command (or set the runSimulation argument to true). true).txt in the current working directory.04) >= Required(200)) A summary also writes to a file results.Chapter 1: About the DSP Builder Advanced Blockset Comparison with RTL 1–25 For example: run_all_atbs('demo_agc'). run_all_atbs('demo_agc'. 0 Failed (fmax). true). The return value is 1 if all tests are successful or 0 if any tests fail.. the script fails with an appropriate error message. 3 Passes. For example: Met FMax Requirement (FMax(291. The script deletes any existing RTL directory before simulation occurs.04) >= Required(200)): PASSED Finished demo_agc Tests at 2009-01-23 15:01:59 (3 Tests. the command also reports whether the design achieves the target fMAX. 0 Failed (non-fmax)) To get a list of the blocks in a design that have automatic testbenches. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . 0 Skipped. false./quartus_demo_agc_AGC_Chip_2): PASSED demo_agc: Met FMax Requirement (FMax(291. for example if the files are in use.

on the Signals block you can set the target clock frequency: fmax_freq = 300. For example. if (isempty(control)) error('The design must contain a Control Block.'destination'.1–26 Chapter 1: About the DSP Builder Advanced Blockset Comparison with RTL Run ModelSim Flow To use the ModelSim simulator to compare the complete Simulink model with hardware. fmax_freq).0. end. set_param(control{1}. 'type'. Design Space Exploration You can write scripts that directly change parameters (such as the hardware destination directory) on the Control and Signals blocks. reports any mismatches.dest_dir). set_param(signals{1}. It creates a ModelSim testbench that contains the HDL generated for the device that the captured inputs feed. in a script that passes the design name (without . Similarly you can get and set other parameters. This comparison uses the same stimulus capture and comparison method as the automatic testbenches.'freq'. 'block'. It compares the Simulink outputs to the ModelSim simulation outputs in an HDL testbench process. 'type'. if (isempty(signals)) error('The design must contain a Signals Block. 'MaskType'. 'DSP Builder Advanced Blockset Control Block'). 'MaskType'. '). %% Example: set the RTL destination directory dest_dir = ['. 'block'. %% Get the Controls block control = find_system(model. and stops the ModelSim simulation./rtl' num2str(freq)].. %% Get the Signals block signals = find_system(model. DSP Builder captures stimulus files on the device level inputs and records Simulink output data on the device level outputs. 'DSP Builder Advanced Blockset Signals Block'). end. For example.mdl extension) as model you can use: %% Load the model load_system(model). DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . '). double-click on the Run ModelSim block.

DSP_18bit. and perform design space exploration. '.Regs. %% Then run the Quartus II compilation flow. details. details. details.command./') %% where details is a struct containing resource and timing information details. details. which also does the RTL generation.ALM.Logic.Chapter 1: About the DSP Builder Advanced Blockset Comparison with RTL 1–27 You can also change the following threshold values that are parameters on the Control block: ■ ■ ■ ■ distRamThresholdBits hardMultiplierThresholdLuts mlabThresholdBits ramThresholdBits You can loop over changing these values. details. details.Slack.IO. details.timingpath.Mem_Bits. t = sim(model).FMax. details. details] = run_hw_compilation(<model>. details.M144K.Required. details. run the Quartus II software each time.dir. [success. details. details. For example: %% Run a simulation.M9K.Comb_Aluts.pwd such that >> disp(details) gives output something like: Logic: 4915 Comb_Aluts: 3213 Mem_Aluts: 377 Regs: 4725 ALM: 2952 DSP_18bit: 68 Mem_Bits: 719278 © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . details. change the destination directory.Mem_Aluts. details. details. details. details.FMax_unres.

4./') Interoperability with the Standard Blockset You can use the advanced blockset in a design flow that includes blocks from the DSP Builder standard blockset. '.1700 Slack: 0. Unused resources may appear as -1.. refer to Chapter 8. Learning to Use the Advanced Blockset To learn about the advanced blockset examine the design examples in Chapter 2 and perform the following tutorials in Chapters 3. The System Tutorial (Chapter 5) shows how you can plug blocks together to create a digital downconverter (DDC). f For information about interoperability. details] = run_hw_compilation(<model>.1–28 Chapter 1: About the DSP Builder Advanced Blockset Interoperability with the Standard Blockset M9K: 97 M144K: 0 IO: 116 FMax: 220. ■ ■ DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . rather than 0. and 5: ■ The ModelIP Tutorial (Chapter 3) shows how to use the ModelIP NCO block to create a customized NCO.1700 timingpath: [1x4146 char] dir: '.4581 Required: 200 FMax_unres: 220./quartus_demo_ifft_4096_natural_for_SPR_FFT_4K_n_2' command: [1x266 char] pwd: 'D:\test\script' 1 The Timing Report is in the timingpath variable. You must previously execute load_system before commands such as find_system and run_hw_compilation work. DSP Builder Standard and Advanced Blockset Interoperability. compile in the Quartus II software and return the details is: load_system(<model>). [success. sim(<model>). which you can display by disp(details.timingpath). and instantiates your design as a subsystem in the SOPC Builder. compiles your design in the Quartus II software. A useful set of commands to generate RTL. The Primitive Library Tutorial (Chapter 4) shows how you can use blocks from the ModelPrim library to build a simple design. The tutorial performs RTL simulation in ModelSim.

The PreLoadFcn and InitFcn callbacks specify the script. f For more information about these blocks.2. To view all the design examples. r © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . You can click DSP Builder Advanced Blockset in the Help window to expand the list and click on an entry to display a Help page for each design example. which you can access by clicking Model Properties on the File menu and is usually named setup_<demo name>. You can also open the models by typing a command of the following form in the MATLAB window: open_system('demo_nco'). ■ ■ ■ ■ ■ The functional subsystem in each design contains a Device block that marks the top-level of the FPGA device and controls the target device for the hardware. refer to the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSP Builder Handbook. reset. which you can use to learn from or as a starting point for your own design. This block generates synthesizable HDL and can therefore also be useful in a functional subsystem. The Edit Params block provides direct access to a MATLAB M-script that sets up MATLAB workspace variables that parameterize each block. Opening a Design Example To display the model corresponding to each design example click Open this model in the Help window. and memory bus signals that the simulation model and the hardware generation use. The Run Quartus II block loads the system into the Quartus II software. and the top-level memory-mapped bus interface widths. You can use other Simulink blocks to define the testbench logic. The Run ModelSim block loads the testbench into the ModelSim simulator. The testbench typically includes Simulink source blocks that generate the stimulus signals and sink blocks that display simulation results. Design Examples and Reference Designs The Altera DSP Builder advanced blockset provides a variety of design examples. The Demos tab opens in the Help window displaying a list of the available design examples. This section describes the available design examples. The testbench also includes the following blocks from the DSP Builder advanced blockset: ■ The Control block specifies information about the hardware generation environment. The ChanView block in a testbench allows you to visualize the contents of the TDM protocol. All the design examples have the same basic structure: a top-level testbench containing an instantiated functional block.m). type demo at the MATLAB command prompt. which represents the hardware design. The Signals block specifies information about the clock.

This folder contains the following design examples: ■ ■ ■ ■ ■ ■ ■ Primitive FIR with Back Pressure (demo_back_pressure) Primitive FIR with Forward Pressure (demo_forward_pressure) Kronecker Tensor Product (demo_kronecker) Rectangular Nested Loop Triangular Nested Loop Sequential Loops Parallel Loops ■ Platforms. These designs provide a starting point to build your own filter chain that meets your exact needs. This folder contains the following design examples that illustrate how you can implement a DDC or digital up converter (DUC) for use in a radio basestation. This folder contains the following design examples of cascaded integrator-comb (CIC) and finite impulse response (FIR) filters: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Decimating CIC Filter (demo_dcic) Interpolating CIC Filter (demo-icic) Single Rate FIR Filter (demo_firs) Decimating FIR Filter (demo_fird) Interpolating FIR Filter (demo_firi) Fractional Rate FIR Filter (demo_firf) Half Band FIR Filter (demo_firih) Root Raised Cosine FIR Filter (demo_fir_rrc) Fractional FIR Filter Chain (demo_fir_fractional) Super-Sample FIR Filter (demo_ssfiri) Filter Chain with Forward Flow Control (demo_filters_flow_control) Multiple Coefficient Banks Interpolating FIR Filter DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . ■ ■ ■ ■ ■ 16-Channel DDC (demo_ddc) 16-Channel DUC (demo_duc) 2-Channel DUC (demo_AD9856) 2-Antenna DUC for WiMAX (demo_wimax_duc) System (demo_ddc) ■ Filters.2–2 Chapter 2: Design Examples and Reference Designs Opening a Design Example or simply: demo_nco r The design examples are in the following folders: ■ Flow Control.

Two Banks NCO (demo_mc_nco_2banks_mem_interface) Four Channel. 64 Banks NCO (demo_mc_nco_64banks) ■ Primitive Blocks. Two Wires NCO (demo_mc_nco_8banks_2wires) Four Channel. Four Banks NCO (demo_mc_nco_4banks_mem_interface) Four Channel. 16 Banks NCO (demo_mc_nco_16banks) Four Channel. Eight Banks. This folder contains the following design examples built with primitive blocks from the ModelPrim library: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Hello World (helloWorld) Fibonacci Series (demo_fibonacci) Automatic Gain Control (demo_agc) Multi-Channel IIR Filter (demo_iir) 8×8 Inverse Discrete Cosine Transform (demo_idct8x8) Quadrature Amplitude Modulation (demo_QAM256) Radix 2 Streaming FFT (demo_fft16_radix2) Radix 4 Streaming FFT (demo_fft256_radix4) 4K FFT (demo_fft_4096_br) 8K FFT (demo_fft_8192_br) 4K IFFT (demo_ifft_4096_natural) 8K IFFT (demo_ifft_8192_natural) Test CORDIC Functions Using Primitive Blocks (demo_cordic_primitives) Test CORDIC Functions Using the CORDIC Block (demo_cordic_lib_block) Folded Color Space Converter Folded Single-stage IIR Filter Folded 3-stage IIR Filter Folded Primitive FIR Filter Hybrid Direct Form and Transpose Form FIR Filter Digital Predistortion Forward Path Run-time Configurable Decimating and Interpolating Half-rate FIR Filter Matrix Initialization of Vector Memories Matrix Initialization of LUT Vector Initialization of Sample Delay © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . This folder contains the following design examples that synthesize waveforms with a NCO or direct digital synthesis (DDS): ■ ■ ■ ■ ■ ■ ■ ■ NCO (demo_nco) Real Mixer (demo_mix) Complex Mixer (demo_complex_mixer) Four Channel.Chapter 2: Design Examples and Reference Designs Opening a Design Example 2–3 ■ Waveform Synthesis.

mdl file. This folder contains a design example showing how you can control memory-mapped registers: ■ Memory-Mapped Registers (demo_regs) ■ Base Blocks.2–4 Chapter 2: Design Examples and Reference Designs Design Examples ■ Host Interface. This folder accesses groups of reference designs that illustrate the design of DDC and DUC systems for digital intermediate frequency (IF) processing. 2-Antenna W-CDMA DDC (wcdma_picocell_duc_mixer) 4-Carrier. 2-Antenna W-CDMA DDC (wcdma_picocell_ddc_mixer) 4-Carrier. The first group implement IF modem designs compatible with the wideband Code Division Multiple Access (W-CDMA) standard: ■ ■ ■ ■ ■ 4-Carrier. Design Examples This section describes the available design examples. ensure that you also copy any corresponding setup_<name>. 2-Antenna High-Speed W-CDMA DUC at 368. 2-Antenna High-Speed W-CDMA DUC at 368. Altera provide separate models for one and two antenna receivers and transmitters: ■ ■ ■ ■ 1-Antenna WiMAX DDC (wimax_ddc_1rx) 2-Antenna WiMAX DDC (wimax_ddc_2rx_iiqq) 1-Antenna WiMAX DUC (wimax_duc_1tx) 2-Antenna WiMAX DUC (wimax_ddc_2tx_iiqq) This folder also accesses the Single-Channel 10-MHz LTE Transmitter./rtl by default).64 MHz with Total Rate Change 32 (wcdma_multichannel_duc_mixer_96x_32R) 4-Carrier.64 MHz with Total Rate Change 48 (wcdma_multichannel_duc_mixer_96x_48R) 4-Carrier. 2-Antenna W-CDMA DUC (wcdma_multichannel_duc_mixer) 1-Carrier. 2-Antenna High-Speed W-CDMA DUC at 307..m file that has the same name as the <name>. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . This folder contains design examples of the Scale and the LocalThreshold block: ■ ■ Scale (demo_scale) Scale (demo_nco_threshold) ■ Reference Designs. You may also want to change the location of the generated files that the Control block specifies for each design (which is set to the relative path . Copying a Design Example If you want to make a copy of a design example.2 MHz with Total Rate Change 40 (wcdma_multichannel_duc_mixer_80x_40R) ■ ■ The second group implements IF modem designs compatible with the Worldwide Interoperability for Microwave Access (WiMAX) standard. 2-Antenna W-CDMA DDC (wcdma_multichannel_ddc_mixer) 1-Carrier.

This signal prevents any new input (as flagged by valid) entering the FIR block.mdl. Primitive FIR with Back Pressure This design example uses primitive library blocks to implement a FIR design with flow control and back pressure. The FIFO buffer must be able to hold at least this much data after it asserts full. Not. You must AND this FIFO valid signal with the ready signal to consume the data at the head of the FIFO buffer. SampleDelay. If the AND result is high. Experiment with some values to find the right one. the design asserts the ready signal back to the upstream block. The full threshold must be at least this delay amount below the size of the FIFO buffer (64 – 32 in this design example). 20000*SampleTime). which allows you to use modular design techniques with local control. Mult. And. r After you run a simulation. Const. click on in the model window or type a command of the following form in the MATLAB window: sim('demo_nco'. This delay is not critical. 1 You can return to the normal Help page by clicking on the Help on core functionality of <block name> link. and Run Quartus II blocks. ChannelOut. If the FIFO buffer becomes half full. A FIFO buffer follows each FIR filter that can buffer any data that is flowing through the FIFO buffer. the top level of the FPGA device (marked by the Device block) and the synthesizable PrimitiveFIR subsystem (marked by the SynthesisInfo block) are at different hierarchy levels. In this design example. Run ModelSim. The top-level testbench includes Control. The model file is demo_back_pressure. you can consume data because it is available and you are ready for it. There are three FIR filters.Chapter 2: Design Examples and Reference Designs Design Examples 2–5 Running a Design Example To run a design example. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . and SynthesisInfo blocks. FIFO. This design example shows how back pressure from a downstream block can halt upstream processing. Add. The delay must be at least as big as the delay through the FIR filter. and no ready signal has to feed back further than one block. Signals. Simulink replaces the Help page for each DSP Builder advanced blockset block (which displays when you click Help on the popup menu for the blocks) by a page showing information about the actual block usage. The design example shows how you use the primitive FIFO block to implement back pressure and flow control. The PrimitiveFIR subsystem includes ChannelIn. The FirChip subsystem includes the Device block and a lower-level PrimitiveFIR subsystem. The delay in the feedback loop represents the lumped delay that spreads throughout the FIR filter block. You can chain several blocks together in this way. The FIFO buffers always show the next data if it is available and the valid signal is asserted high. Mux.

The Chip subsystem includes the Device block and a lower-level KroneckerSubsystem subsystem. You can also use vectors to implement the constant multipliers and adder tree. and observe the valid output data only. Add.2–6 Chapter 2: Design Examples and Reference Designs Design Examples The final block uses an external ready signal that comes from a downstream block in the system. The design example has a regular filter structure. which also speeds up simulation. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . the top level of the FPGA device (marked by the Device block) and the synthesizable PrimitiveFIR subsystem (marked by the SynthesisInfo block) are at different hierarchy levels. You need not enable everything in the filter (multipliers. Mux. preventing invalid data polluting the datapath. Then observe the output valid signal. Run ModelSim. adders. Kronecker Tensor Product This design example generates a Kronecker tensor product. and so on). The design example has a sequence of three FIR filters that stall when the valid signal is low. Mult. In this design example. just the blocks with state (the registers). Run ModelSim. In this design example. The design example shows how to use the Loop block to generate datapaths that operate on regular data. Signals. Signals. and Run Quartus II blocks. The model file is demo_forward_pressure. The FirChip subsystem includes the Device block and a lower-level PrimitiveFIR subsystem. The design example shows how you can add a simple forward flow control scheme to a FIR design so that it can handle invalid source data correctly. Const. DualMem.mdl. which DSP Builder pipelines with the logic. the top level of the FPGA device (marked by the Device block) and the synthesizable KroneckerSubsystem subsystem (marked by the SynthesisInfo block) are at different hierarchy levels. Loop. The top-level testbench includes Control. ChannelOut. and SynthesisInfo blocks. and SynthesisInfo blocks. SampleDelay. Const. and Run Quartus II blocks. You can improve the design example further by using the TappedDelayLine block from the Vector Utils library. Mult. ChannelOut. The KroneckerSubsystem subsystem includes ChannelIn. The PrimitiveFIR subsystem includes ChannelIn. but with a delay line implemented in single-cycle latches— effectively an enabled delay line. The top-level testbench includes Control. Primitive FIR with Forward Pressure This design example uses primitive library blocks to implement a FIR design with forward flow control.

The design example daisy chains the ld port of InnerLoopA to the ls port of InnerLoopB rather than connecting it directly to the bd port of OuterLoop. step. At the corners (at the end of loops) there may be cycles where the count value goes out of range. the counter effectively walks through a triangular set of indices.Chapter 2: Design Examples and Reference Designs Design Examples 2–7 The model file is demo_kronecker. The model file is forloop_parloop. The two inner loops are started simultaneously by duplicating the control token but finish at different times. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . and limit values are constant. The inner loops execute in parallel rather than sequentially. so that the next loop iteration of this loop starts immediately after the previous iteration. The RendezVous block waits until both of them finish and then passes the control token back to the outer loop.mdl.mdl. then the output valid signal from the loop is low. The model file is forloop_seqloop. which is typical of applications where the control token is generated afresh for each activation of the outermost loop. The ls port of the outer loop connect to external logic and the ld port of the outer loop is unconnected. step. Parallel Loops This design example has two inner loops nested within the outer loop. except for the parameterization of the loops. The token-passing structure is typical for a nested-loop structure. The token-passing structure for this loop is identical to that for the rectangular loop.mdl. Rectangular Nested Loop In this design example all initialization. Triangular Nested Loop The initialization.mdl. and limit values do not have to be constants. The bs port of the innermost loop (ForLoopB) connects to the bd port of the same loop. two inner loops (InnerLoopA and InnerLoopB) both nest within the outer loop. The model file is forloop_rectangle. the ld port of the inner loop loops back to the bd port of the outer loop.mdl. The bs port of the outer loop (ForLoopA) connects to the ls port of the inner loop. Thus each activation of InnerLoopA is followed by an activation of InnerLoopB. By using the count value from an outer loop as the limit of an inner loop. Each iteration of the outer loop runs a full activation of the inner loop before continuing on to the next iteration. Sequential Loops In this design example. The model file is forloop_triangle.

This resynchronizes the data correctly. interpolating CIC and FIR filters up convert eight complex channels (16 real channels). and Run Quartus II blocks. RegBit. Decimating CIC and FIR filters down convert eight complex carriers (16 real channels) from 61. The Sync subsystem is a primitive subsystem that shows how to manage two data streams coming together and synchronizing. This subsystem shows how you can use processor-visible register blocks to control a datapath element. DSP Builder integrates several primitive subsystems into the datapath. The total decimation rate is 64. The total interpolation rate is 50. Signals. and Run Quartus II blocks.m script.m script. NCO.44 MHz. DSP Builder writes the data from the NCOs to a memory with the channel as an address: the data stream using its channel signals to read out the NCO signals. InterpolatingCIC. plus a ChanView block that deserializes the output bus. Run ModelSim. Run ModelSim. An Edit Params block allows easy access to the setup variables in the setup_demo_ddc. DecimatingCIC. This design example shows how you can integrate ModelIP blocks with primitive subsystems: ■ There is a programmable Gain subsystem at the beginning of the datapath.mdl. Alternatively. Mixer. The DUC16 subsystem includes InterpolatingFIR. The testbench isolates two channels of data from the TDM signals using a channel viewer. ModelBus. The model file is demo_ddc. NCO. The DUCChip subsystem includes a Device block and a lower level DUC16 subsystem. Scale. A real mixer and NCO isolate the eight carriers. 16-Channel DUC This design example shows how to build a 16-channel DUC as found in modern radio systems using ModelIP. ComplexMixer. An Edit Params block allows easy access to the setup variables in the setup_demo_duc. and Scale blocks. An interpolating filter chain is presented. The top-level testbench includes Control. and RegField blocks. plus a ChanView block that deserializes the output bus. The DDCChip subsystem includes Device. and ModelPrim blocks. ■ Extensive use is made of Simulink multiplexer and demultiplexer blocks to manage vector signals.2–8 Chapter 2: Design Examples and Reference Designs Design Examples 16-Channel DDC This design example shows how to use using ModelIP and ModelBus blocks to build a 16-channel digital-down converter for modern radio systems. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . you can simply delay the NCO value by the correct number of cycles to ensure that the NCO and channel data arrive at the Mixer on the same cycle. Signals. Decimating FIR. 1 This design example uses the Simulink Signal Processing Blockset. The top-level testbench includes Control.

CompareEquality.mdl. plus a ChanView block that deserializes the output bus. Sub. and SynthesisInfo blocks. The model file is demo_duc. ChannelOut. and Run Quartus II blocks. The model file is demo_wimax_duc.mdl. SingleRateFIR. A NCO and Mixer subsystem combine the complex input channels into a single output channel. and SynthesisInfo blocks. Interpolating CIC and FIR filters up convert a single complex channel (2 real channels). The top-level testbench includes Control. Sync. InterpolatingCIC. RegField blocks. SingleRateFIR. Run ModelSim. 2-Channel DUC This design example shows how to build a 2-channel DUC as found in an ASSP chip. A primitive block implements the mixer in this design example as the data rate is low enough to save resource using a time-shared hardware technique. CompareEquality.Chapter 2: Design Examples and Reference Designs Design Examples 2–9 It also includes lower level Gain. and CarrierSum subsystems which make use of other ModelBus and ModelPrim blocks including AddSLoad. The DUCIQ subsystem includes Const. Scale blocks. Not. The top-level testbench includes Control. Const. ChannelIn. Run ModelSim. Mult. ComplexMixer. InterpolatingFIR. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . and Run Quartus II blocks. RegBit. The Mixer subsystem includes ChannelIn. The DUCChip subsystem includes a Device block and a lower level DUC2Antenna subsystem. Mult. Mux. The DUC2Antenna subsystem includes InterpolatingFIR. The AN9856 subsystem includes a Device block and a lower level DUCIQ subsystem. Signals. And. NCO. Delay. 1 This design example uses the Simulink Signal Processing Blockset. 1 This design example uses the Simulink Signal Processing Blockset. NCO. Signals.m script. BitExtract. This design example shows how quick and easy it is to emulate the contents of an existing datapath. The model file is demo_AD9856. 1 This design example uses the Simulink Signal Processing Blockset. And. ChannelOut. BitExtract. An Edit Params block allows easy access to the setup variables in the setup_demo_AD9856. DualMem.mdl. SampleDelay. and Scale blocks. plus a ChanView block that deserializes the output bus. Or. and a lower level Mixer subsystem. Const. Const. 2-Antenna DUC for WiMAX This design example shows how to build a 2-antenna DUC to meet a WiMAX specification.

mdl. The top-level testbench includes Control.mdl. 1 This design example uses the Simulink Signal Processing Blockset. The model file is demo_firs. Single Rate FIR Filter This design example uses the SingleRateFIR block to build a 16-channel single rate 49-tap FIR filter with a target system clock frequency of 360 MHz. Signals. An Edit Params block allows easy access to the setup variables in the setup_demo_dcic. Run ModelSim. The CICSystem subsystem includes the Device and DecimatingCIC blocks. plus ChanView block that deserialize the output buses. 1 This design example uses the Simulink Signal Processing Blockset. 1 This design example uses the Simulink Signal Processing Blockset. The FilterSystem subsystem includes the Device and InterpolatingCIC blocks.m script.mdl. Signals. and Run Quartus II blocks. The top-level testbench includes Control. plus ChanView block that deserialize the output buses. and Run Quartus II blocks. plus ChanView block that deserialize the output buses. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . Signals. Interpolating CIC Filter This design example implements an interpolating CIC filter. The model file is demo_icic. “System Tutorial” on page 5–1 describes this design example. The model file is demo_dcic.m script. Decimating CIC Filter This design example implements a decimating CIC filter. and Run Quartus II blocks. An Edit Params block allows easy access to the setup variables in the setup_demo_icic. The FilterSystem subsystem includes the Device and SingleRateFIR blocks. Run ModelSim.m script. Run ModelSim. The top-level testbench includes Control. An Edit Params block allows easy access to the setup variables in the setup_demo_firs. 1 This design example uses the Simulink Signal Processing Blockset.2–10 Chapter 2: Design Examples and Reference Designs Design Examples System The system tutorial describes the 16-channel DDC design example in detail and shows how you can combine blocks to build a system-level design.

The FilterSystem subsystem includes the Device and FractionalRateFIR blocks. 1 This design example uses the Simulink Signal Processing Blockset. Fractional Rate FIR Filter This design example implements a fractional rate FIR filter. Signals. The model file is demo_fird. The model file is demo_firf. The FilterSystem subsystem includes the Device and InterpolatingFIR blocks.m script. Signals. 1 This design example uses the Simulink Signal Processing Blockset. The top-level testbench includes Control. and Run Quartus II blocks. The top-level testbench includes Control. The FilterSystem subsystem includes the Device and Decimating FIR blocks. Run ModelSim. plus ChanView block that deserialize the output buses. plus ChanView block that deserialize the output buses.mdl. and Run Quartus II blocks. An Edit Params block allows easy access to the setup variables in the setup_demo_fird.mdl. symmetrical. An Edit Params block allows easy access to the setup variables in the setup_demo_firf.m script. and Run Quartus II blocks. Run ModelSim. The top-level testbench includes Control. 49-tap FIR filter with a target system clock frequency of 360 MHz. Signals.Chapter 2: Design Examples and Reference Designs Design Examples 2–11 Decimating FIR Filter This design example uses the Decimating FIR block to build a 20-channel decimate by 5. An Edit Params block allows easy access to the setup variables in the setup_demo_firi. Half Band FIR Filter This design example implements a half band interpolating FIR filter. 49-tap FIR filter with a target system clock frequency of 240 MHz. The model file is demo_firi.m script. Run ModelSim. Interpolating FIR Filter This design example uses the InterpolatingFIR block to build a 16-channel interpolate by 2.mdl. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . 1 This design example uses the Simulink Signal Processing Blockset. plus ChanView block that deserialize the output buses.

2–12 Chapter 2: Design Examples and Reference Designs Design Examples The top-level testbench includes Control.m script. 33-tap FIR filter. and Run Quartus II blocks. The input sample rate is twice the clock rate and is interpolated by three by the filter to six times the clock rate. The FilterSystem subsystem includes the Device and Decimating FIR blocks. Super-Sample FIR Filter This design example shows how the filters cope with data rates greater than the clock rate. The model file is demo_fir_fractional. The top-level testbench includes Control. and Scale blocks. Signals. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . An Edit Params block allows easy access to the setup variables in the setup_demo_fir_rrc. which is visible in the vector input and output data connections. plus ChanView block that deserialize the output buses. Root Raised Cosine FIR Filter This design example uses the Decimating FIR block to build a 4-channel decimate by 5.mdl. Decimating FIR.m script. plus ChanView block that deserialize the output buses.mdl. The design example uses the InterpolatingFIR block to build a single channel interpolate by 3. The model file is demo_firih. Run ModelSim. 1 This design example uses the Simulink Signal Processing Blockset. InterpolatingFIR. and Run Quartus II blocks. The FilterSystem subsystem includes the Device block and two separate InterpolatingFIR blocks for the regular and interpolating filters.mdl. and six samples are output each cycle. Signals. Run ModelSim. An Edit Params block allows easy access to the setup variables in the setup_demo_fir_fractional. 1 This design example uses the Simulink Signal Processing Blockset. The FilterSystem subsystem includes ChanView. plus ChanView block that deserialize the output buses. The model file is demo_fir_rrc. 199-tap root raised cosine filter with a target system clock frequency of 304 MHz. Signals. An Edit Params block allows easy access to the setup variables in the setup_demo_firih. Fractional FIR Filter Chain This design example uses a chain of InterpolatingFIR and DecimatingFIR blocks to build a 16-channel fractional rate filter with a target system clock frequency of 360 MHz. symmetrical. The input receives two samples in parallel at the input. Run ModelSim. 1 This design example uses the Simulink Signal Processing Blockset.m script. The top-level testbench includes Control. and Run Quartus II blocks.

1 This design example uses the Simulink Signal Processing Blockset. Filter Chain with Forward Flow Control This design example builds a filter chain with forward flow control.mdl. An Edit Params block allows easy access to the setup variables in the setup_demo_mix. The top-level testbench includes Control. An Edit Params block allows easy access to the setup variables in the setup_demo_filters_flow_control. InterpolatingCIC. Run ModelSim.mdl. select Help and scroll down to the input and output data format sections. The NCOSubSystem subsystem includes the Device and NCO blocks. InterpolatingFIR.mdl. plus ChanView blocks that deserialize the output buses. Multiple Coefficient Banks Interpolating FIR Filter This design example builds an interpolating FIR filter that regularly switches between coefficient banks. Signals. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . Signals. 1 This design example uses the Simulink Signal Processing Blockset. and Run Quartus II blocks.Chapter 2: Design Examples and Reference Designs Design Examples 2–13 After simulation. NCO This design example uses the NCO block from the Waveform Synthesis library to implement an NCO. Signals. plus ChanView block that deserialize the output buses. The top-level testbench includes Control. and Run Quartus II blocks. The FilterSystem subsystem includes FractionalRateFIR. Real Mixer This design example shows how to mix non-complex signals. Const and Scale blocks. Run ModelSim. The top-level testbench includes Control.m script.mdl.m script.m script. and Run Quartus II blocks. A Simulink double precision sine or cosine wave compares the results. An Edit Params block allows easy access to the setup variables in the setup_demo_nco. 1 This design example uses the Simulink Signal Processing Blockset. The model file is demo_filters_flow_control. The model file is demo_firi_multibank. The model file is demo_nco. The model file is demo_ssfiri. right-click on the FIR. plus ChanView block that deserialize the output buses. Run ModelSim.

You should write a new value into the phase increment memory register for each bank to change the NCO output frequencies after 8. The FilterSystem subsystem includes the Device and ComplexMixer blocks.8000)] This configuration ensures that a new phase increment value for bank 0 is written at 7000 steps when the NCO is processing bank 1. To avoid writing new values to the active bank.000 steps before switching to the other. Two banks of frequencies exist in this design example with each bank processed for 2. An Edit Params block allows easy access to the setup variables in the setup_demo_complex_mixer. 1 This design example uses the Simulink Signal Processing Blockset.mdl.mdl.m script. Signals.2000) 1 1 1 1 zeros(1. Run ModelSim.000 steps during simulation. The top-level testbench includes Control.7000) 1 1 1 1 zeros(1. The write data is also made up of two parts with each part writing to one of the registers feeding the selected phase increment accumulators. the addresses [1000 1001 1002 1003 1012 1013 1014 1015] write to the phase increment memory registers of channels 1 and 2 in bank 1. With the base address of the phase increment memory map set to 1000 in this design example. and a new phase increment value for bank 1 is written at 9000 steps when the NCO is processing bank 0. The model file is demo_mix. A BusStimulus block sets up an Avalon-MM interface that writes into the phase increment memory registers. The input for the bank index is set up so that it alternates between the two predefined banks with each one lasting 2000 steps. It shows how you can use the Avalon-MM interface to dynamically change the frequencies of the NCO-generated sinusoidal signals at run time. Four Channel.2–14 Chapter 2: Design Examples and Reference Designs Design Examples The MixerSystem subsystem includes the Device and Mixer blocks. This design example uses a 16-bit memory interface (as the Control block specifies) and a 24-bit the accumulator in the NCO block. and Run Quartus II blocks. This design example demonstrates frequency-hopping with the NCO block to generate four channels of sinusoidal waves that you can switch from one set (bank) of frequencies to another. 1 This design example uses the Simulink Signal Processing Blockset. and to the registers of channels 3 and 4 in bank 2. The design example requires two registers for each phase increment value. plus ChanView block that deserialize the output buses. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . the design example configures the write enable signals in the following way: [zeros(1. The phase increment values are set directly into the NCO Parameter dialog box as a 2 (rows) × 4 (columns) matrix. Two Banks NCO This design example implements a NCO with four channels and two banks. The model file is demo_complex_mixer. Complex Mixer This design example shows how to mix complex signals.

The scope of the select channel shows the sinusoidal waves of the channel you select. Each new phase value needs two registers due to the size of the memory interface. Signals.000 steps before switching to the other. the design example configures the write enable signals in the following way: [zeros(1. and a new phase increment value for bank 3 is written at 21000 steps when the NCO is processing bank 2. a new phase increment value for bank 2 is written at 19000 steps when the NCO is processing bank 1. The top-level testbench includes Control.2000) 1 zeros(1. and new values for channel 3 and 4 into bank 1. You can also see the frequency changes after 8000 steps where the phase increment value alters through the memory interface. Two Banks NCO design. where the fifth peak shows the changes the design example writes through the memory interface. The NCOSubSystem subsystem includes the Device and NCO blocks. a new value for channel 3 into bank 2. Hence. and Run Quartus II blocks. This design example is similar to the Four Channel. There are five peaks on each spectrum plot. the design example requires only one phase increment memory register for each phase increment value—refer to the address and data setup on the BusStimulus block inside this design example.15000) 1 zeros(1. The spectrum scope shows that there are three peaks for a selected channel with the first two peaks representing the two banks and the third peak showing the frequency that you specify through the memory interface.000 steps during simulation.8000)].m script.2000) 1 zeros(1. Each new phase value needs only one register due to the size of the memory interface. There is one write for each bank to write a new value for channel 1 into bank 0. Run ModelSim. There are four banks of frequencies set up in this design example with each bank processed for 2. but it has four banks of frequencies defined for the phase increment values. plus ChanView blocks that deserialize the output buses. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_2banks_mem_interface.2000) 1 zeros(1. You should write a new value into the phase increment memory register for each bank to change the NCO output frequencies after 16. The design example uses a 32-bit memory interface with a 24-bit accumulator.' This configuration ensures that a new phase increment value for bank 0 is written at 15000 steps when the NCO is processing bank 3.Chapter 2: Design Examples and Reference Designs Design Examples 2–15 Four writes for each bank exist to write new values for channel 1 and 2 into bank 0. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . and a new value for channel 4 into bank 3. Four Channel. Four Banks NCO This design example implements a NCO with four channels and four banks. BusStimulus. a new value for channel 2 into bank 1. a new phase increment value for bank 1 is written at 17000 steps when the NCO is processing bank 0. The model file is demo_mc_nco_2banks_mem_interface. To avoid writing new values to the active bank. You can zoom in to see that smooth and continuous sinusoidal signals at the switching point.mdl. 1 This design example uses the Simulink Signal Processing Blockset.

the sample time for the NCO requires two wires to output the four channels of the sinusoidal signals. 1. BusStimulus. Because there are two wires for the NCO output. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_4banks_mem_interface. from the scope display.. because the design example uses the different values of phase increment values between the selected banks. BusStimulus. you can see that the sinusoidal wave is no longer smooth at the switching point. Signals. and Run Quartus II blocks. which you can switch from one set (bank) of frequencies to another in the 16 predefined frequency sets.2–16 Chapter 2: Design Examples and Reference Designs Design Examples The top-level testbench includes Control. The model file is demo_mc_nco_8banks_2wires. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . CompareEquality.mdl model after you run demo_mc_nco_8banks_2wires. Hence. The Select_bank_out subsystem contains Const. Run ModelSim. Run ModelSim. and Run Quartus II blocks. Signals.mdl. but has only eight banks of phase increment values (specified in the setup script for the workspace variable) feeding into the NCO. Two Wires NCO This design example implements a NCO with four channels and eight banks. 3 to 0 . Four Channel. 1 This design example uses the Simulink Signal Processing Blockset.m script. The NCOSubSystem subsystem includes the Device and NCO blocks. Furthermore. The design example outputs the data to the workspace and plots through with the separate demo_mc_nco_extracted_waves. Eight Banks. Four Channel. and AND Gate blocks. the channel indicator is from 0 . each wire only contains two channels. plus ChanView blocks that deserialize the output buses.mdl.mdl. plus ChanView blocks that deserialize the output buses. The top-level testbench includes Control. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_8banks_2wires. However. This design example demonstrates frequency-hopping with the NCO block to generate 4 channels of sinusoidal waves.mdl. This design example uses an additional subsystem (Select_bank_out) to extract the NCO-generated sinusoidal signal of a selected bank on a channel.. You can only run the demo_mc_nco_extracted_waves. 1 This design example uses the Simulink Signal Processing Blockset. which demonstrates that the output of the bank you select does represent a genuine sinusoidal wave. 16 Banks NCO This design example implements a NCO with four channels and 16 banks. 16 Banks NCO design.m script. The NCOSubSystem subsystem includes the Device and NCO blocks. This design example is similar to the Four Channel. The model file is demo_mc_nco_4banks_mem_interface. You can inspect the eight peaks on the spectrum graph for each channel and see the smooth continuous sinusoidal waves on the scope display.

An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_16banks. 52. The model file is demo_mc_nco_64banks. 9. 21. The input for the bank index is set up so that it cycles through banks 0. 43. and Run Quartus II blocks. Run ModelSim. The NCOSubSystem subsystem includes the Device and NCO blocks. 28. 35. You can zoom in to see that the design example generates smooth and continuous sinusoidal signals at the switching point. The NCOSubSystem subsystem includes the Device and NCO blocks. A workspace variable phaseIncr defines the 64 (rows) × 4 (columns) matrix for the phase increment input with the design example calculating phase increment values inside the setup script. Run ModelSim. The input for the bank index is set up so that it cycles from 0 to 15 with each bank lasting 1200 steps.Chapter 2: Design Examples and Reference Designs Design Examples 2–17 A workspace variable phaseIncr defines the 16 (rows) × 4 (columns) matrix for the phase increment input with the phase increment values that the setup script calculates.mdl. Signals. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . This design example demonstrates frequency-hopping with the NCO block to generate 4 channels of sinusoidal waves that you can switch from one set (bank) of frequencies to another in the 64 predefined frequency sets. The top-level testbench includes Control. An Edit Params block allows easy access to the setup variables in the setup_demo_mc_nco_64banks. plus ChanView blocks that deserialize the output buses.m script. and Run Quartus II blocks. The top-level testbench includes Control.mdl. The model file is demo_mc_nco_16banks. 1 This design example uses the Simulink Signal Processing Blockset. Four Channel. The scope of the selected channel shows the sinusoidal waves of the selected channel. Signals.m script. The spectrum display shows clearly that there are 16 peaks for the selected channel indicating that the design example generates 16 different frequencies for that channel. 1 This design example uses the Simulink Signal Processing Blockset. 64 Banks NCO This design example implements a NCO with four channels and 64 banks. and 63 with each bank lasting 1200 steps. plus ChanView blocks that deserialize the output buses. 15. The spectrum display shows that there are 11 peaks for the selected channel indicating that there are 11 different frequencies generated for that channel. The scope of the selected channel shows the sinusoidal waves of the selected channel. 5. You can zoom in to see that the design example generates smooth and continuous sinusoidal signals at the switching point. 61.

and SynthesisInfo blocks. The design example uses Simulink ports for simplicity although they prevent the automatic testbench flow from working. the top-level of the FPGA device (marked by the Device block) and the synthesizable primitive subsystem (marked by the SynthesisInfo block) are at the same level. 1 This design example uses the Simulink Signal Processing Blockset. designs can achieve high data rates by the pipelining algorithms. and Run Quartus II blocks. Fibonacci Series This design example generates a Fibonacci sequence.mdl. and Run Quartus II blocks. Mux. An external input enables a counter that addresses a lookup-table (LUT) that contains some text. This design example shows that even for circuitry with tight feedback loops and 120-bit adders. The top-level testbench includes Control.mdl. Lut. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . Counter. or GPOut blocks. Hello World This design example is a simple primitive design example that outputs a simple text message that it stores in a look-up table. 1 In this design example. The top-level testbench includes Control. ChannelOut. and SynthesisInfo blocks. The Chip subsystem includes the Device block and a lower level FibSystem subsystem. Run ModelSim. The FibSystem subsystem includes ChannelIn. You can examine the contents with a char(message) command in the MATLAB command window. This design example does not use any ChannelIn. 1 In this design example. Add. The Chip subsystem includes Device. The design example writes the result to a MATLAB array. the top-level of the FPGA device (marked by the Device block) and the synthesizable primitive subsystem (marked by the SynthesisInfo block) are at different hierarchy levels. The model file is demo_fibonacci. Run ModelSim. Signals. The model file is helloWorld. SampleDelay. GPIn.2–18 Chapter 2: Design Examples and Reference Designs Design Examples ModelIP The ModelIP design example describes how you can build a NCO design with the NCO block from the Waveform Synthesis library. Signals. ChannelOut. “ModelIP Tutorial” on page 3–1 describes this design example.

and Run Quartus II blocks. masking the subsystem provides the benefits of a black-box IP block but with visibility. The AGC subsystem includes RegField. and SynthesisInfo blocks.Chapter 2: Design Examples and Reference Designs Design Examples 2–19 Automatic Gain Control This design example implements an automatic gain control. The AGC_Chip subsystem includes the Device block. a RegField block and a lower level AGC subsystem. SampleDelay.mdl. The model file is demo_iir. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . in the callbacks for the masked subsystem. 1. The model file is demo_agc. and Run Quartus II blocks. Signals. The design example spreads a lumped delay around the circuit to satisfy timing while maintaining correctness. ChannelOut. a] = ellip(2. Add. Run ModelSim. The top-level testbench includes Control. and SynthesisInfo blocks. Sub. The multiple channels provide more latency around the circuit to ensure a high clock frequency result. This design example shows a complex loop with several subloops that it schedules and pipelines without inserting registers. Convert. Convert. Sub. Abs.mdl. 0. Lumped delays allow you to easily parameterize the design example when changing the channel counts. SampleDelay. Lut. plus ChanView block that deserialize the output buses. Processor visible registers control the thresholds and gains.3). the zero-latency blocks make it easy to follow a data value through the circuit and investigate the algorithm without offsetting all the results by the pipelining delays. SharedMem. Run ModelSim. The coefficients for the filter are set from [b. ChannelOut. In complex algorithmic circuits. Signals. The design example implements all the pipelined delays in the circuit automatically. Multi-Channel IIR Filter This design example implements a masked multi-channel infinite impulse response (IIR) filter with a masked subsystem that it builds from primitive blocks. 10. BitExtract. Mult. Add. For example. You can look under the mask to see the implementation details of the IIRSubsystem subsystem which includes ChannelIn. Select. The top-level testbench includes Control. This primitive design example has many feedback loops. CmpGE. Const. ChannelIn. Mult. The IIRCHip subsystem includes the Device block and a masked IIRSubsystem subsystem. Const. Shift.

streaming. Run ModelSim. there are additional levels of hierarchy for the different stages but because the SynthesisInfo block is at the row or column level. The top-level testbench includes Control. Run ModelSim. BitCombine. BitExtract. Signals. BitExtract. The top-level testbench includes Control. and SynthesisInfo blocks. Lut. Run ModelSim. DSP Builder Advanced Blockset User Guide Preliminary © December 2010 Altera Corporation . Sub. and column transformation (Col) functions. corner turner (CornerTurn). An Edit Params block allows easy access to the setup variables in the setup_demo_fft16_radix2. Shift. which are 16 and 15 for this design example. and Run Quartus II blocks. Mult. Add. the design example flattens these subsystems before synthesis. fast Fourier transform. GPIn. Separate subsystems perform the row transformation (Row). and SynthesisInfo primitive blocks.mdl. OR Gate. The QAM256Chip subsystem includes Add. ChannelOut.2–20 Chapter 2: Design Examples and Reference Designs Design Examples 8×8 Inverse Discrete Cosine Transform This design example uses the Chen-Wang algorithm to implement a fully pipelined 8×8 inverse discrete cosine transform (IDCT).m script. Quadrature Amplitude Modulation This design example implements a simple quadrature amplitude modulation (QAM256) design examplewith noise addition. Radix-2. The design example synthesizes each separate subsystem separately. and Run Quartus II blocks. The IDCTChip subsystem includes the Device block and a lower level IDCT subsystem. and Run Quartus II blocks. The design example specifies these values with the Wordlength and FractionLength variables in the setup script. 1 This design example uses the Simulink Communications Blockset. The testbench uses various Simulink blocks. Const. In the Row and Col subsystems. The IDCT subsystem includes lower level subsystems that it describes with the ChannelIn. The model file is demo_QAM256. Sequence. The top-level testbench includes Control. Signals. SampleDelay.mdl. Signals. Not. BitCombine. The model file is demo_idct8x8. GPOut. 1 The CornerTurn turn block makes extensive use of Simulink Goto/From blocks to reduce the wiring complexity. Radix 2 Streaming FFT This design example implements a complex. 1 The FFT designs do not inherit width in bits and scaling information.

SampleDelay. Convert. Radix 4 Streaming FFT This design example implements a 256 point. and SynthesisInfo blocks. Run ModelSim. 1 The FFT designs do not inherit width in bits and scaling information. DualMem. Convert. DualMem. radix 4. which are 16 and 15 for this design example. To save resources. This design example accepts data in bit reversed order. single channel.m script. and Run Quartus II blocks. Complex SampleDelay. Signals. which are 16 and 19 for this design example. ChannelOut. and BFII blocks from the FFT library. and BFI blocks from the FFT library. Most applications do not need the maximum width in bits. You can also set the maximum width in bits by setting the MaxOut variable. It also includes ChannelIn. Lut. Counter. 1 The FFT designs do not inherit width in bits and scaling information. The model file is demo_fft16_radix2. BitExtract. Lut. An Edit Params block allows easy access to the setup variables in the setup_demo_fft256_radix4. There is also a BitReverse subsystem that is very similar to the more general purpose BitReverseCore masked subsystem in the FFT library. The design example specifies these values with the Wordlength and FractionLength variables in the setup script. and Run Quartus II blocks. The DUT subsystem includes the Device block and a lower level FFTChip subsystem. The default value of inf allows worst case bit growth. SampleDelay.096 point. The top-level testbench includes Control. complex fast Fourier transform. The model file is demo_fft256_radix4. Complex SampleDelay. and SynthesisInfo blocks. © December 2010 Altera Corporation Preliminary DSP Builder Advanced Blockset User Guide . ChannelOut. but without the channel signal.mdl. which makes the testbench easier to understand. The design example includes a bit-reversal block before the FFT algorithm. There is also a BitReverse subsystem that is very similar to the more general purpose BitReverseCore masked subsystem in the FFT library. The FFTChip subsystem uses the ComplexMult. It also includes ChannelIn. Run ModelSim. The FFTChip subsystem uses the ComplexMult. The top-level testbench includes Control. Radix 22 fast Fourier transform. Signals.m script. but without the channel signal. An Edit Params block allows easy access to the setup variables in the setup_demo_fft_4096_br. BFI. Counter.Chapter 2: Design Examples and Reference Designs Design Examples 2–21 The DUT subsystem includes the Device block and a lower level FFTChip subsystem. set a threshold value for this variable. 4K FFT This design example implements a 4. BitExtract.mdl. The design example specifies these values with the Wordlength and FractionLength variables in the setup script. but the data is in natural order at the output of the FFT.

This design exam