A3949 DMOS Full-Bridge Motor Driver

Features and Benefits
▪ Single supply operation ▪ Very small outline package ▪ Low RDS(ON) outputs ▪ Sleep function ▪ Internal UVLO ▪ Crossover current protection ▪ Thermal shutdown protection

Designed for PWM (pulse width modulated) control of DC motors, the A3949 is capable of peak output currents to ±2.8 A and operating voltages to 36 V. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of VBB and VCP , and crossover current protection. The A3949 is supplied in a power package, a 16-pin plastic SOIC with a copper batwing tab (part number suffix LB). The packages are lead (Pb) free, with 100% matte tin leadframes.


Package LB, 16-pin SOIC with internally fused pins Not to scale

Functional Block Diagram
.22 μF 25 V VREG 0.1 μF CP1 CP2

Low Side Gate Supply


Charge Pump

VCP 0.1 μF VBB Load Supply

MODE 0.1 μF 100 μF



ambient temperature. Range S Peak < 2 μs Notes Rating 36 38 –0.508. 115 Northeast Cutoff Worcester.3 to 7 0.S. DO NOT exceed the specified IOUT or TJ. 2-oz. Massachusetts 01615-0036 U. Under any set of conditions. Inc. Repetitive Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Symbol VBB VIN VSENSE IOUT TA TJ(max) Tstg Output current rating may be limited by duty cycle.853. SOIC Packing 1000 per reel Absolute Maximum Ratings Characteristic Load Supply Voltage Logic Input Voltage Sense Voltage Output Current. copper each side *Additional information is available on the Allegro website. and heat sinking.allegromicro.8 –20 to 85 150 –55 to 150 Units V V V V A ºC ºC ºC Package Thermal Characteristics* Characteristic Symbol RθJA Note 2 Rating 52 Units °C/W Package Thermal Resistance Measured on 2-layer PCB with 2 in.5 ±2. Allegro MicroSystems.A.com 2 .A3949 DMOS Full-Bridge Motor Driver Selection Guide Part Number A3949SLBTR-T Package 16-pin. www. 1.5000.

1 1 6 3 – – – – – < 1.8 A Sink diode.3 8. IOUT = –2. Thermal Shutdown Hysteresis TJ ΔTJ VBB rising – – – – 6 250 170 15 – – – – V mV °C °C VIN(1) VIN(0) VIN(1) VIN(0) IIN(1) IIN(0) IIN(1) IIN(0) IIN(1) IIN(0) tpd tCOD VIN = 2. .4 .8 A fPWM < 50 kHz Motor Supply Current IBB Charge pump turned on. TJ= 125°C Body Diode Forward Voltage VF Source diode.508. .8 V VIN = 2. 1. outputs disabled Sleep mode Logic Input Voltage PHASE.3 1. Massachusetts 01615-0036 U. IOUT = –2.8 – 0.8 A. TJ= 125°C Sink driver.8 A.com 3 .5 10 – 0.3 . 115 Northeast Cutoff Worcester. TJ= 25°C Output-On Resistance RDSON Source driver.68 .8 A. Inc. IOUT = –2.8 A.allegromicro.0 – 2. MODE Logic Input Voltage SLEEP Logic Input Current PHASE. – – – – – – – – – 2.7 – – – – – – – – – – Typ.0 < –2.8 V From PWM change to source or sink turn on From PWM change to source or sink turn off Min. IOUT = 2.0 V VIN = 0.43 – 1.5 4. TJ= 25°C Sink driver. ENABLE.8 V VIN = 2.A.7 V VIN = 0.8 20 –20 100 40 50 10 – – – Units Ω Ω Ω Ω V V mA mA μA V V V V μA μA μA μA μA μA ns ns ns Allegro MicroSystems.S.0 V VIN = 0.853.5000.A3949 DMOS Full-Bridge Motor Driver ELECTRICAL CHARACTERISTICS at TA = 25°C.0 40 16 27 <1 600 100 500 Max. VBB = 8 V to 36 V (unless otherwise noted) Characteristics Symbol Test Conditions Source driver.48 – .576 1. IF = 2. MODE pins Logic Input Current ENABLE pin Logic Input Current SLEEP pin Propagation Delay Times Crossover Delay Protection Circuitry UVLO Enable Threshold UVLO Hysteresis Thermal Shutdown Temp. IF = –2. www.

allegromicro. 1. Inc.508.com 4 .A3949 PWM Control Timing Diagram SLEEP ENABLE PHASE MODE DMOS Full-Bridge Motor Driver VBB OUTA 0V VBB OUTB 0V IOUT 0A A 1 2 3 4 5 6 7 8 9 VBB VBB 6 7 OUTA 1 3 2 4 5 8 OUTB OUTA 9 OUTB A Charge pump and VREG power-up delay (approximately 200 us) Allegro MicroSystems. Massachusetts 01615-0036 U. 115 Northeast Cutoff Worcester.S.A.5000.853. www.

508. the outputs of the device are disabled. A 0. The maximum current can be approximated by VBEMF / RL. After coming out of Sleep mode. A 0. www. The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates.com 5 . This disables much of the internal circuitry.A3949 DMOS Full-Bridge Motor Driver Functional Description VREG. the outputs of the device are disabled.1 uF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high side DMOS devices.22 F capacitor to ground.S.allegromicro. Inc. Control input SLEEP is used to minimize power consumption when the A3949 is not in use. The VREG pin should be decoupled with a 0. This supply voltage is used to operate the sinkside DMOS outputs. A logic low on this pin puts the device into Sleep mode. the outputs of the device are disabled until the fault condition is removed. to allow the charge pump to stabilize. and applying an enable chop command.5000. this configuration effectively shorts out the motor-generated BEMF. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations of high speed and high inertial loads.853. 1. Sleep Mode. Because it is possible to drive current in both directions through the DMOS switches.1 uF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. Shutdown. the outputs go to the high impedance state as the current approaches zero. At power-up. 115 Northeast Cutoff Worcester. Charge Pump. the user should wait 1 ms before applying PWM signals. as long as the enable chop mode is asserted on the ENABLE pin. and in the case of a fault condition. Control Logic Table PHASE ENABLE MODE 1 0 X 1 0 X 1 1 0 0 0 X X X 1 0 0 X SLEEP 1 1 1 1 1 0 OUTA H L L L H Hi-Z OUTB L H L H L Hi-Z Function Forward Reverse Brake (slow decay) Fast decay SR* Fast decay SR* Sleep mode * To prevent reversal of current during fast decay SR (synchronous rectification).A. In the event of a fault due to excessive junction temperature. the UVLO circuit disables the drivers. A logic high allows normal operation. Braking. Massachusetts 01615-0036 U. Allegro MicroSystems. VREG is internally monitored and in the case of a fault condition. The braking function is implemented by driving the device in slow decay mode via the MODE pin. The VCP voltage is internally monitored. or low voltage on VCP or VREG. including the low-side gate supply and the charge pump.

allegromicro. 115 Northeast Cutoff Worcester.S. Inc. www. 1. Massachusetts 01615-0036 U.A3949 DMOS Full-Bridge Motor Driver LB Package N/C MODE PHASE GND SLEEP ENABLE OUTA SENSE 1 2 3 4 5 6 7 8 16 N/C 15 VREG 14 VCP 13 GND 12 CP2 11 CP1 10 OUTB 9 VBB Name N/C MODE PHASE GND SLEEP ENABLE OUTA SENSE VBB OUTB CP1 CP2 GND VCP VREG N/C Not used Logic input Description Number 1 2 3 4* 5 6 7 8 9 10 11 12 13* 14 15 16 Logic input for direction control Ground Logic input Logic input Output A for full bridge Power return Load supply voltage Output B for full bridge Charge pump capacitor Charge pump capacitor Ground Reservoir capacitor Low side gate supply decoupler Not used *These pins are internally connected.5000. Allegro MicroSystems.853.508.A.com 6 .

or to affect the safety or effectiveness of that device or system.30 9. and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown Pins 4 and 13 fused internally A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-16M) All pads a minimum of 0.65 1. assumes no responsibility for its use. However.27 7. gate burrs.S. if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system.10 C 0. nor for any infringement of patents or other rights of third parties which may result from its use. Allegro MicroSystems.27 0.20 SEATING PLANE 2.com 7 . from time to time.allegromicro. The information included herein is believed to be accurate and reliable.25 B PCB Layout Reference View 16X 0. Allegro’s products are not to be used in life support devices or systems. 115 Northeast Cutoff Worcester.allegromicro.41 1.com Allegro MicroSystems.508.20 mm from all adjacent pads. 1.A3949 DMOS Full-Bridge Motor Driver LB 16-Pin SOICW 10.84 2. or manufacturability of its products. Massachusetts 01615-0036 U. Inc.27 0. reserves the right to make. visit our website: www.30 4º 16 0.5000. Inc. such departures from the detail specifications as may be required to permit improvements in the performance. reliability. Allegro MicroSystems.853.50 0.50 A 10. Before placing an order. Allegro MicroSystems.65 MAX C SEATING PLANE GAUGE PLANE All dimensions nominal. Inc. Inc. adjust as necessary to meet application process requirements and PCB layout tolerances Copyright ©2003-2010. not for tooling use Dimensions in millimeters (reference JEDEC MS-013 AA) Dimensions exclusive of mold flash. For the latest version of this document. the user is cautioned to verify that the information being relied upon is current.A.25 1 2 0. www.

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