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Dr. P. Sudhakara Rao, Dean Switching Theory and Logic Design

UNIT -2

BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS

o o o o o o Fundamental postulates of Boolean algebra Basic theorems and properties Switching functions Canonical and Standard forms Algebraic simplification digital logic gates, properties of XOR gates Universal gates Multilevel NAND/NOR realizations

o

Boolean Algebra: Boolean algebra, like any other deductive mathematical system, may be defined with a set of elements, a set of operators, and a number of unproved axioms or postulates. A set of elements is any collection of objects having a common property. If S is a set and x and y are certain objects, then x ∈ S denotes that x is a member of the set S, and y ∉S denotes that y is not an element of S. A set with a denumerable number of elements is specified by braces: A = {1,2,3,4}, i.e. the elements of set A are the numbers 1, 2, 3, and 4. A binary operator defined on a set S of elements is a rule that assigns to each pair of elements from S a unique element from S.

Example: In a*b=c, we say that * is a binary operator if it specifies a rule for finding c from the pair (a,b) and also if a, b, c ∈ S. CLOSURE: The Boolean system is closed with respect to a binary operator if for every pair of Boolean values, it produces a Boolean result. For example, logical AND is closed in the Boolean system because it accepts only Boolean operands and produces only Boolean results. A set S is closed with respect to a binary operator if, for every pair of elements of S, the binary operator specifies a rule for obtaining a unique element of S. For example, the set of natural numbers N = {1, 2, 3, 4, … 9} is closed with respect to the binary operator plus (+) by the rule of arithmetic addition, since for any a, b ∈ N we obtain a unique c ∈ N by the operation a + b = c. ASSOCIATIVE LAW: A binary operator * on a set S is said to be associative whenever (x * y) * z = x * (y * z) for all x, y, z ∈ S, for all Boolean values x, y and z. COMMUTATIVE LAW: A binary operator * on a set S is said to be commutative whenever x * y = y * x for all x, y, z ∈ S IDENTITY ELEMENT: A set S is said to have an identity element with respect to a binary operation * on S if there exists an element e ∈ S with the property e * x = x * e = x for every x ∈ S

Vignan Institute of Technology and Science

Page |1

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jntuworld. ∴ no subtraction or division. Dean Switching Theory and Logic Design INVERSE: A set S having the identity element e with respect to a binary operator * is said to have an inverse whenever. (•) whenever x * (y • z) = (x * y) • (x * z) HUNTINGTON POSTULATES: Closure with respect to the operator + and • Identity element with respect to + (0) and • (1) x+0=0+x=x. Distributive Postulate 5 Vignan Institute of Technology and Science x+0=x x+y=y+x x (y + z) = xy + xz x + x’ = 1 x•1=x xy = yx x + yz = (x + y)(x + z) x • x’ = 0 Page |2 www. Huntington postulates do not include the associative law.www. Distributive over + and • . Boolean algebra deals with only two elements. there exists an element x’ ∈ B such that (a) x + x’ = 1 and (b) x • x’ = 0. However. x•y = y•x. x+(y•z) = (x+y) •(x+z) … Not valid in ordinary algebra For every element of x ∈ B. The operator complement is not available in ordinary algebra. this law holds for Boolean algebra. Commutative Postulate 4. x•1=1•x=x Commutative with respect to + and • . x+y = y+x. Boolean algebra does not have additive or multiplicative inverses. x•(y+z) = (x•y) + (x•z). * is said to be distributive over.1} with rules for the two binary operators + and (•) as shown in the following operator tables: x 0 0 1 1 y 0 1 0 1 x•y 0 0 0 1 x+y 0 1 1 1 x’ 1 1 0 0 Verify that the Huntington postulates hold true. for every x ∈ S. BASIC THEOREMS & PROPERTIES OF BOOLEAN ALGEBRA: Duality Principle states that every algebraic expression deducible from the postulates of Boolean algebra remains valid if the operators and identity elements are interchanged. there exists an element y ∈ S such that x * y = e DISTRIBUTIVE LAW: If * and (•) are two binary operators on a set S.com . Ordinary algebra deals with real numbers. There exists at least two elements x.jntuworld. The distributive law of + over (•) is valid for Boolean algebra but not for ordinary algebra. P.com Dr. TWO-VALUED BOOLEAN ALGEBRA: A two-valued Boolean algebra is defined on a set of two elements. Sudhakara Rao. B = {0. Postulates a and b Postulate 2 Postulate 3. y ∈ B such that x ≠ y.

P. If x + x' = 1 and x. Sudhakara Rao. also called De Morgan duality.com . Absorption a x+x=x x+1=1 ( x’ )’ = x x + (y + z) = (x + y) + z (x + y)’ = x’y’ x + xy = x x•x = x x•0=0 x • (y• z) = (x • y) • z (x•y)’ = x’ + y’ x (x + y) = x b Proof of Theorem 1(a) x+x =x x + x = (x + x) ⋅ 1 by postulate 2(b) = (x + x) ⋅ (x + x’) by postulate 5(a) = x + xx’ by postulate 4(b) =x+0 by postulate 5(b) =x by postulate 2(a) Proof of Theorem 2(a) x+1 =1 = 1•(x+1) = (x+x’)(x+1) = x + x’•1 = x +x’ =1 Proof of Theorem 3 (x’)’ = x We know that x' is the complement of x.jntuworld. then x + x' = 1 x' + x =1 and x. asserts that Boolean algebra is unchanged when all dual pairs are interchanged. Associative Theorem 5.com Dr.www. Page |3 www.jntuworld.x = 0 complement of x x is the complement (x')' = x Proof of Theorem 4(a) x + (y + z) = (x + y) + z Let A = x + (y + z) and B = (x + y) + z To Show: A = B First. DeMorgan Theorem 6.x' = 0. Involution Theorem 4. Dean Switching Theory and Logic Design BASIC THEOREMS & PROPERTIES OF BOOLEAN ALGEBRA: Theorems a and b Theorem Theorem 1 Theorem 2 Theorem 3. xA = x [x + (y + z)] = xx + x(y+z) = x + x(y+z) = x(1 + (y+z)) =x xB = x[(x + y) + z] = x(x + y) + xz = x + xz = x Vignan Institute of Technology and Science Proof of Theorem 1(b) x•x =x xx = xx+0 = xx + xx’ =x(x+x’) =x•1 =x Proof of Theorem 2(b) x•0 = 0 by duality Postulate 2(a) Postulate 5(b) Postulate 5(a) Postulate 2(b) The Duality Principle. x' = 0 x'.

Thus the proof consists of showing that (A*B)*( A + B) = 0.jntuworld. Vignan Institute of Technology and Science Page |4 www. x'A = x'[x + (y + z)] = x'x + x'(y + z) = xx' + x'(y + z) = 0 + x'(y + z) = x'(y + z) x'B = x'[(x + y) + z] = x'(x + y) + x'z = (x'x + x'y) + x'z = (xx' + x'y) + x'z = (0 + x'y) + x'z = x'y + x'z 0 = x'(y + z) Therefore x'A = x'B = x'(y + z) Finally. A A = 0 and A + A = 1. Sudhakara Rao. (A + B) = A* B b. and that X + Y = 1. P. Dean Switching Theory and Logic Design Therefore xA = xB = x Second.www. X = Y. we have shown that x + (y + z) = (x + y) + z Proof of Theorem 5(a) (x + y)’ = x’y’ X (x+y) (x + y)’ 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 DeMorgan's Theorems: a. By the uniqueness of the complement. X = Y. A*B = A + B Note: * = AND operation Y x’ 1 1 0 0 y’ 1 0 1 0 x’y’ 1 0 0 0 Proof of DeMorgan's Theorem (b): For any theorem X=Y.com Dr.jntuworld. A=A•1 = A(x + x') = Ax + Ax' = xA + x'A = xB + x'A = xB + x'B = Bx + Bx' = B(x + x') =B•1 =B Since A = x + (y + z) and B = (x + y) + z. if we can show that X Y = 0. and also that (A*B) + ( A + B) = 1. then by the complement postulates.com .

A*B is the complement of A + B. P.com Dr. (note that ' = complement or NOT . DeMorgan's Theorem (a) may be proven using a similar approach. The involution theorem states that A'' = A. Thus by the involution theorem.double bars don't show in HTML) Thus A*B= (A + B)''.www. Parenthesis Prove x + x’y = x + y x + x’y = (x+x’)(x+y) = 1•(x+y) = x+y Prove xy+x’z+yz = xy+x’z = xy+x’z+yz (x+x’) = xy + x’z + xyz + x’yz =xy(1+z) + x’z(1+y) =xy+x’z Simplify x’y’z + yz + xz = z ( x’y’ + y + x) =z (x’ + y + x) = z (1 + y) = z( 1) = z 2. This proves DeMorgan's Theorem (b). and (A*B) + ( A + B) =1.jntuworld. OR Vignan Institute of Technology and Science Page |5 www. Sudhakara Rao. Proof of Theorem 6(a) x + xy = x x + xy = x•1 + xy = x(y+1) =x •1 = x Proof of Theorem 6(b) x(x+y) = x By duality Operator Precedence: 1. AND 4. Dean Switching Theory and Logic Design Prove: (A*B)*( A + B) = 0 (A*B)*( A + B) = (A*B)*A + (A*B)*B) by distributive postulate = (A*A)*B + A*(B*B) by Associativity postulate = 0*B + A*0 = 0+0 =0 (A*B)*( A + B) = 0 by Complement postulate by Nullity theorem by identity theorem Prove: (A*B) + ( A + B) =1 (A*B) + ( A + B) =(A + A + B))*(B + A + B) by distributivity B*C + A = (B + A)*(C + A) (A*B) + ( A + B) =(A + A + B))*(B + B + A) by associativity postulate =(1 + B)*(1 + A) by complement postulate =1*1 by nullity theorem =1 by identity theorem (A*B) + ( A + B) =1 Since (A*B)*( A + B) = 0.jntuworld.com . (A + B)'' = A + B. meaning that A*B=(A + B)'. NOT 3.

Ans : A’C’ + A[BD + D’(B’+C)] ii) T(A. Dean Simplify (x+y) [ x’ (y’+z’)]’ +x’y’+x’z’ = (x+y) [x + (y’+z’)’] +x’y’+x’z’ = (x+y) (x + yz) + x’y’ + x’z’ = x + xyz +xy +yz +x’y’ +x’z’ = x + xy + yz +x’y’ +x’z’ = x + yz + +x’y’ +x’z’ = x + y’ + yz + x’z’ = x + z’ + y’ + z =1 Switching Theory and Logic Design SWITCHING FUNCTIONS Let T(x1.www. P. x3.com Dr.1) = 0’1 +01’ +0’1’ = 1 + 0 + 0 = 1. Ans : A’B + BD +ACD’ Vignan Institute of Technology and Science Page |6 www.D) = A’C’ + ABD + BC’D + AB’D’ +ABCD’ ………………. x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 f 1 0 1 1 0 0 1 1 g 0 1 0 1 1 0 1 0 f’ 0 1 0 0 1 1 0 0 g’ 1 0 1 0 0 1 0 1 fg 0 0 0 1 0 0 1 0 f+g 1 1 1 1 1 0 1 1 Simplify i) T(A. f’ and g’ can easily built. xn) be a switching expression. Each of the variables can assume any of two values 0 or 1 and hence there are 2n combinations for determining the values of T.jntuworld.0. x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 T 1 1 0 1 1 0 1 0 When built a truth table for T = x’z + xz’ + y’z’. this will be identical to the above. For example T = x’z + xz’ + x’y’.D) = A’B + ABD + AB’CD’ + BC ……………….C. (f+g). If a truth table is given for functions say f and g.B. x2. …. Hence different switching functions may produce the same assignments.B. Similarly T can be computer for every combination and a truth table may be built.com . Sudhakara Rao.jntuworld.C. then (fg). Then T(0.

com . A Minterm is a product of all variables taken either in their direct or complemented form. All three-variable Minterms are listed in the following table: Vignan Institute of Technology and Science Page |7 www. A Maxterm is a sum of all variables taken either in their direct or complemented form.jntuworld. all possible logic products of three variables x = (x2. For example y = c · a’ + c · b = c(a’ + b) = c(c’ + b + a’) Each algebraic form entails specific gate implementation. n-to-2n Decoders Consider. x0). Dean IEEE Standard Logic Symbols Switching Theory and Logic Design Exclusive OR Gates Exclusive NOR Gates CANONICAL AND STANDARD FORMS A Boolean (logic) function can be expressed in a variety of algebraic forms.com Dr. Where x’ represents either variable x or its 2 1 0 complement x’. P. Sudhakara Rao. There are 23 = 8 different Minterms that can be written in the form mi = x x x . or in one of the canonical forms.jntuworld.www. for example. A Boolean function can be uniquely described by its truth table. x1. Minterms. Two dual canonical forms of a Boolean function are available: (a) The sum of Minterms (SoM) form (b) The product of Maxterms (PoM) form.

Dean x x2 0 0 1 0 2 0 3 0 4 1 5 1 6 1 7 1 x1 0 0 1 1 0 0 1 1 x0 0 1 0 1 0 1 0 1 Minterms m0 = 1 Switching Theory and Logic Design m0 m1 0 1 0 0 0 0 0 0 m2 0 0 1 0 0 0 0 0 m3 0 0 0 1 0 0 0 0 m4 0 0 0 0 1 0 0 0 m5 0 0 0 0 0 1 0 0 m6 0 0 0 0 0 0 1 0 m7 0 0 0 0 0 0 0 1 xxx m =x x x m =x x x m =x x x m =x x x m =x x x m =x x x m =x x x 2 1 2 1 2 2 0 1 0 0 0 0 0 0 0 2 2 2 2 1 1 0 0 3 4 1 1 1 0 0 5 6 7 2 0 2 1 0 The logic circuit that generates all Minterms is called an n-to-2n decoder: 0 1 2 3 4 5 6 7 m0 = x 0 x 0 x x x xxx 2 1 0 0 1 2 m4= xxx 2 1 0 m7= xxx 2 1 0 x1 Example: Logic structure of a 2-to-4 decoder x x2 0 0 1 0 2 0 3 0 x1 0 0 1 1 x0 0 1 0 1 Minterms m0 = 1 x0 M2 0 0 1 0 M3 0 0 0 1 M4 0 0 0 0 m0 = M0 0 M1 0 1 0 0 xx m =x x m =x x m =x x 1 1 2 2 3 1 0 0 0 x x 1 0 m1= m2= 1 1 0 0 m3= X1 X0 Vignan Institute of Technology and Science Page |8 www.com . Sudhakara Rao.jntuworld.www. P.com Dr.jntuworld.

all three-variable Maxterms are listed in the following table: X 0 1 2 3 4 X2 0 0 0 0 1 X1 0 0 1 1 0 X0 0 1 0 1 0 MAXTERMS x M =x M =x M =x M =x M0= 6 5 4 3 2 2 2 2 + x1 + x0 M0 0 1 M1 1 0 1 1 1 M2 1 1 0 1 1 M3 1 1 1 0 1 M4 1 1 1 1 0 M5 1 1 1 1 1 M6 1 1 1 1 1 M7 1 1 1 1 1 + x1 + x 1 1 0 + x + x0 +x +x 0 1 1 1 2 + x1 + x0 Vignan Institute of Technology and Science Page |9 www..jntuworld. • A Maxterm is a complement of an equivalent Minterm For example.5... P. say. Dean Switching Theory and Logic Design The Sum-of-Minterms (SoM) canonical form of a logic function Any logic function y of n variables can be expressed as the logic sum of products of Minterms and the respective values of the function. Mi... x0 ) = Example of a 3-variable function x x2 x1 x0 y mj 0 0 0 0 0 1 0 0 1 0 2 0 1 0 1 m2 3 0 1 1 0 4 1 0 0 1 m4 5 1 0 1 1 m5 6 1 1 0 0 7 1 1 1 1 m7 ∑ forall j such that y j =1 m j y = 0 · m0 + 0 · m1 + 1 · m2 + 0 · m3 + 1 · m4 + 1 · m5 + 0 · m6 + 1 · m7 = m2 + m4 + m5 + m7 ∑ 2. Sudhakara Rao...4..www...... that is: y = f (x n−1 .7 —a commonly used short notation = xxx+xxx+xxx+xxx 2 1 0 2 1 0 2 1 0 2 1 0 MAXTERMS A logic sum (OR) of all variables taken in their direct or complemented form is called a Maxterm....com Dr....com ..... yj = 1 y = f (xn−1. x0 ) = ∑ y i =0 2 −1 n i m i It is clearly equivalent to the sum of minterms for which the values of the function are 1..jntuworld.

B.5. F = ABC + ABC’ + AB’C + AB’C’ + A’BC’ = = m7 + m6 +m5+m4 + m2 Vignan Institute of Technology and Science P a g e | 10 www.com Dr. Firstly expand all terms with all three variables (A. P. Sudhakara Rao. build a truth table (for F= A +BC’) and derive the expression A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 1 0 1 1 1 1 Now the equation is formed by identifying the values of ABC for all combinations that produce ‘1’ as output (F).4. . ∑ 2.7 Alternately.www. Dean Switching Theory and Logic Design 5 6 7 1 1 1 0 1 1 1 0 1 M2= 1 x +x +x M =x +x +x 2 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 0 M0 = 1 1 0 x +x +x 2 The logic circuit that generates all Maxterms is also called an n-to-2n decoder: x 0 x 0 x x x 0 1 2 0 1 2 3 4 5 6 7 M0= M3= x +x +x 2 1 0 x +x +x 2 1 0 M7 = x +x +x 2 1 0 Example Express the Boolean function F = A + BC’ in a sum of the (Products) Minterms.jntuworld.B.C). F= A +BC’ = A(B+B’) + BC’ = AB +AB’ + BC’ = AB(C+C’) + AB’(C+C’) + BC’ (A+A’) = ABC + ABC’ + AB’C +AB’C’ + BC’A + BC’A’ = Repeat Terms = ABC + ABC’ + AB’C + AB’C’ + A’BC’ = m7 + m6 +m5+m4 + m2 This may also be expressed in short notation as F(A.com .jntuworld.C) = .

OR. For example F = (x’ + y)(z + x) ( z + y). Let us convert each term into a three variable term (x’ + y) = x’ + y + zz’ = (x’ + y +z)(x’ + y + z’) (z + x) = z + x + yy’ = (x + y + z)(x = y’ + z) ( z + y) = z + y + xx’ = (z + y + x)( z + y + x’) F = (x’ + y +z)(x’ + y + z’) (x + y + z)(x + y’ + z) (z + y + x)( x’ + y + z) F = ( x’ + y + z) + (x’ + y + z’) + (x + y + z)(x + y’ + z) F = M4 + M5 + M0+M2 Conveniently it is written as F(x..5) Conversion between canonical forms Example. where as F = ABC + ABC’ + AB’C + AB’C’ + A’BC’ is in sum of Minterms form. XOR and XNOR gates are usually found as 2-input gates.6.y. However in standard form the expression will be in most minimal and completely simplified form.jntuworld.4.C.Can be two level or Three level Implementation --------------------------- Algebraic simplification digital logic gates. F (A.5. In the above example F = A + BC’ is in standard form or it is in sum of the products form. Examples: F1 = y’ + xy + x’yz’ ……… Sum of the products …. These gates are particularly useful in arithmetic operations as well as error-detection and correction circuits. properties of XOR gates In addition to AND. Vignan Institute of Technology and Science P a g e | 11 www. Dean Switching Theory and Logic Design Product of Maxterms: Example: F = xy + x’z .B.7 The complement of this is F’(A.3) Standard Forms: This is other way to express Boolean function. Sudhakara Rao. P. Similarly for the case of Maxterms too. exclusive-OR (XOR) and exclusive-NOR (XNOR) gates are also used in the design of digital circuits. NAND and NOR gates.3 = m0+m2+m3 . These have special functions and applications. Complement of this is F = (m0+m2+m3)’ = m0’•m2’•m3’ = M0•M2•M3 = ∏(0. express this in terms of Maxterms F = xy + x’z = (xy + x’)(xy + z) = (x’+xy )(z + xy ) = (x’ + y)(z + x) ( z + y) However this function has three variables. where as F = ( x’ + y + z) + (x’ + y + z’) + (x + y + z)(x + y’ + z) is in Product of Maxterms form.2. All Minterms and Maxterms must have all the variables in each term.C. in two level implementation F2 = x(y’+z)(x’ + y + z’) ……………….com Dr.Product of Sums…… in two level implementation F3 = AB + C(D+E) …….jntuworld. Non-Standard form ------.2.z) = ∏(0.D) = ∑ 0.www.2. The Maxterms will have all the variables in each term where as in standard form it will be in simplified form and called Product of Sums.com ..4. NOT.B. This is in a standard form and also said to be the Product of Sums.D) = ∑ 1.

com . The result is 1 when either both X and Y are 0’s or when both are 1’s. Sudhakara Rao. and A Θ(B Θ C) = (A Θ B) Θ C Vignan Institute of Technology and Science P a g e | 12 www. and it performs the following logic operation: X ⊕ Y = X Y’ + X’ Y The graphic symbol and truth table of XOR gate is shown in the figure. XNORe: The exclusive-NOR (XNOR). operator uses the symbol ⊕. operator uses the symbol Θ.jntuworld. and AΘB=BΘA 2. This can also be shown by algebraic manipulation as follows: (X ⊕ Y)’ = (X Y’ + X’ Y)’ = (X Y’)’ (X’ Y)’ = (X’ + Y) (X + Y’) = (XY + X’Y’) =XΘY Properties of XOR/XNOR Operations: 1.Commutativity A ⊕ B = B ⊕ A. and it performs the logic operation.www.Associativity A ⊕ (B ⊕ C) = (A ⊕ B) ⊕ C. That is why this gate is often referred to as the Equivalence gate. P.com Dr. X ΘY = X Y + X’ Y’ = (X ⊕ Y)’. The graphic symbol and truth table of XNOR (Equivalence) gate is shown in the figure.jntuworld. Dean Switching Theory and Logic Design XOR Gate: The exclusive-OR (XOR). The truth tables clearly show that the exclusive-NOR operation is the complement of the exclusive-OR.

Vignan Institute of Technology and Science P a g e | 13 www.com . The following figure shows a step-by-step approach starting by the logic circuit corresponding to the left-hand-side of the identity and performing equivalent gate transformations till a circuit is reached that corresponds to the right-hand-side of the identity. Dean Switching Theory and Logic Design Basic Identities of XOR Operation: Any of the following identities can be proven using either truth tables or algebraically by replacing the ⊕ operation by its equivalent Boolean expression: X⊕0=X X ⊕ 1 = X’ X⊕X=0 X ⊕ X’ = 1 X ⊕ Y’ = X’ ⊕ Y = (X ⊕ Y)’ = X Basic Identities of XOR Operation: Any of the following identities can be proven using either truth tables or algebraically by replacing the ⊕ operation by its equivalent Boolean expression: X⊕0=X X ⊕ 1 = X’ X⊕X=0 X ⊕ X’ = 1 X ⊕ Y’ = X’ ⊕ Y = (X ⊕ Y)’ = X ΘY The figure provides a graphical presentation of important XOR/XNOR rules and gate equivalence. P.jntuworld.com Dr.www. Example: Show that (A Θ B) ⊕ (C Θ D) = A ⊕ B ⊕ C ⊕ D Proving the above identity is easier done using graphical equivalence between gates as specified by the previous figure.jntuworld. Sudhakara Rao.

as shown in figure. The circuit that generates the parity bit at the transmitter side is called a parity generator. The complement of an odd function (an even function) is obtained by replacing the output gate with an exclusive-NOR gate. Vignan Institute of Technology and Science P a g e | 14 www. IFF the number of 1’s in the input combination is odd. EVEN Function: The complement of an odd function is an even function. A ⊕ B ⊕ C ⊕ D = 1. In general.www.jntuworld. The message. X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Odd 0 1 1 0 1 0 0 1 Likewise.com . An error is detected if the checked parity does not correspond with the one transmitted. P. IFF (if and only if) the number of 1’s in the input combination is odd. is transmitted and then checked at the receiving end for errors. including the parity bit. Sudhakara Rao. The circuit that checks the parity at the receiver side is called a parity checker.com Dr. the 3-input XOR function is implemented by means of two 2-input XOR gates. an exclusive-OR function of n-variables is an odd function which has a value of 1 IFF the number of 1’s in the input combination is odd. Parity Generation and Checking: Exclusive-OR functions are very useful in systems using parity bits for error-detection.jntuworld. Dean Switching Theory and Logic Design ODD Function: X ⊕ Y ⊕ Z = 1. otherwise it has a value of 0. as shown in figure. A parity bit is used for the purpose of detecting errors during transmission of binary information. The even function is equal to 1 when the number of 1’s in the input combination is even. A parity bit is an extra bit included with a binary message to make the total number of 1’s in this message (including the parity bit) either odd or even. Since XOR gates are only designed with 2 inputs.

jntuworld. The table below shows the truth table for the even-parity checker. Therefore.com . It is worth noting that the parity generator can also be implemented with the circuit of this figure if the input P is connected to logic-0 and the output is marked with P. The table shows the truth table for the even parity generator. The three bits. The 4 bits (X.com Dr. For even parity. whenever the message bits (X. where they are applied to a paritychecker circuit to check for possible errors in the transmission. Since the information was transmitted with even parity. Vignan Institute of Technology and Science P a g e | 15 www. consider a 3-bit message to be transmitted together with an even parity bit. Y. The logic diagram for the even parity generator circuit is shown in the figure. This is because Z ⊕ 0 = Z. Y& Z) have an odd number of 1’s. P must be 0. The 1logic diagram of the even-parity checker is shown in the figure. P. X. P can be expressed as a three-variable exclusive-OR function: P = X ⊕ Y ⊕ Z. the parity checker error output signal C is given by the following expression: C = X ⊕ 0Y ⊕ Z ⊕ P.jntuworld. the parity bit P must be 1. Received Data x 0 0 0 0 0 0 0 0 y 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 p 0 1 0 1 0 1 0 1 Parity Error Check C 0 1 1 0 1 0 0 1 Received Data x 1 1 1 1 1 1 1 1 y 0 0 0 0 1 1 1 1 z 0 0 1 1 0 0 1 1 p 0 1 0 1 0 1 0 1 Parity Error Check C 1 0 0 1 0 1 1 0 Obviously. constitute the message and are the inputs to the even parity generator circuit whose output is the parity bit P. Sudhakara Rao. The parity checker generates an error signal (C = 1). Z & P) are transmitted to their destination. whenever the received four bits have an odd number of 1’s.www. causing the value of Z to pass through the gate unchanged. Otherwise. Dean Switching Theory and Logic Design x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Parity Bit 0 1 1 0 1 0 0 1 As an example. Y. and Z. the received four bits must have an even number of 1’s.

com Dr. then x Not x If x. the same circuit can be used for both parity generation and checking. To achieve this. Sudhakara Rao. P. OR and NOT. In other words any logic circuit with AND gates in first level and OR gates in second level can be converted into a NAND-NAND gate circuit. then y NOT-AND Binary Constant Vignan Institute of Technology and Science P a g e | 16 www.Y. Any logic function can be implemented using NAND gates. first the logic function has to be written in Sum of Product (SOP) form. But there are some rules that need to be followed when implementing NAND or NOR based gates. Universal Gates: Universal gates are the ones which can be used for implementing any gate like AND.com .W The above expression can be implemented with three AND gates in first stage and one OR gate in second stage as shown in figure olean function F0 = 0 F1 = xy F2 = xy’ F3 = x F4 = x’y F5 = y F6 = xy’ + x’y F7 = x + y F8 = (x + y)’ F9 = xy + x’y’ F10 = y’ F11 = x + y’ F12 = x’ F13 = x’ + y F14 = (xy)’ F15 = 1 Operator Symbol x. then is very easy to implement using NAND gate.jntuworld. NAND and NOR gates are universal gates.jntuworld.y x/y y/x x⊕y x+y x ↓y (x⊕y ’ y’ x⊂y X’ x⊃ y x↑y Name NULL AND Inhibition Transfer Inhibition transfer Exclusive . Once logic function is converted to SOP. Consider the following SOP expression F = W.Z + Y.Y + X.Z. Dean Switching Theory and Logic Design The advantage of this is.www. or any combination of these basic gates.OR OR NOR Equivalence Complement Implication Complement Implication NAND Identity Comments Binary Constant 0 x and y x but not y x’ y but not x Y x or y but not both x or y Not-OR X equals y Not y If y.X.

com . Ten functions with binary operator that defines eight different operations: AND.jntuworld. Hence for a multiple in-put NAND or NOR shall be understood as multiple input OR gate followed by an inverter only for NOR and multiple input AND gate followed by an inverter only for NAND. Sudhakara Rao. Equivalence.jntuworld.com Dr. Dean Switching Theory and Logic Design 1. ExOr.. z’ y z (y+z)’ x ≠ [(y+z)’ + x]’ =(y+z) . NAND. P. For NOR gates (x ↑y ) ↑z ≠ x ↑ (y ↑z ) …. Two functions that produce 0 or 1 2. OR. Positive Logic and Negative LOGIC 1 H 0 L Positive Logic x y A x A y Vignan Institute of Technology and Science P a g e | 17 www. Nonassociativity of NAND and NOR Gates (x ↓y ) ↓z ≠ x ↓(y ↓z ) …. x’ 0 H 1 L x y A Negative Logic 0 0 0 0 1 1 1 0 1 1 1 1 x 1 1 0 0 y 1 0 1 0 A 1 0 0 0 The same can be proved even for NAND gate. For NAND gates x y z (x+y)’ [(x+y)’ + z]’ = (x+y) . inhibition and implication. NOR.www. Four functions with unary operator: Complement and transfer 3.

4.13.13.7. Sudhakara Rao.com Dr. Dean Multilevel NAND/NOR realizations Incompletely Specified Function Switching Theory and Logic Design A 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 B 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 C 0 0 1 1 0 1 0 1 0 1 1 0 0 1 0 1 D 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 OUT 0 1 1 0 0 1 1 1 0 1 0 D D D D D A’B’C’D+ A’B’CD’+ A’BCD’+ AB’C’D+ AB’CD’+ ABCD’+.C. 2.15) 3.15) Simplify Vignan Institute of Technology and Science P a g e | 18 www.D) = ∏m(3.com .jntuworld.11.B.12..13.12. F (A. Don’t Care Terms.7. F as given in (1) Assignments Implement the following expressions using i) NOR gates only ii) NAND gates only 1.www.11. Can be assigned ‘0’ or ‘1’ for minimisation processes Examples: 1.D) = Σm(11.C.15) 2.. P.C.. F = [(ab)’ + (cd)’ + e]’ F = a’[b’+c(d+e’)+f’g’] +hi’j + k F = [(a+b’)c + d]e’ +f F1 = (A’ + B)C+F’+DE …. F (A.12.B. 3..B..jntuworld.D) = Σm(3. F (A.14.

(a)Simplify the following Boolean functions to minimum number of literals: i. Y.com Dr. Realize this using AND. X. C. Dean Switching Theory and Logic Design SOME QUESTIONS 1. OR.C) whose minterms are 1.3. (a) List the Minterms and Maxterms for three binary variables. Simplify the following Boolean expressions using K-map and implement them using NOR gates: (a) F (A. Z) = W’X’Y’Z’ + WXY’Z’ + W’X’YZ + WXYZ 3.B.(a)State and prove the following Boolean laws: i.Draw the truthtable and express the Boolean function F(A. Obtain the truth table.com . F = X’Y’ + XYZ + X’Y ii. Commutative ii. Sudhakara Rao. 4. b’d + a’bc’ + acd + a’bc (c) Which gate can be used as parity checker? Why? *** Vignan Institute of Technology and Science P a g e | 19 www. ( a + b )’ ( a’ + b’ )’ ii.7as Canonica Sum of Minterms form. (b) Simplify the following Boolean functions to minimum number of literals: i. List Boolean laws and their Duals. F = X + Y[ Z + (X+Z)’ ] (c) For the logic expression Y = AB’ + A’B: i. Name the operation performed. Associative iii. NOT gates.(a)State Duality theorem. y(wz’ + wz) + xy (b) Prove that AND-OR network is equivalent to NAND-NAND network. 6.(a)What are don’t-care conditions? Explain its advantage with example. P. F = (A+B)’ (A’+B’).jntuworld.www. F = ABC + ABC’ + A’B ii. ii. (c) State Duality theorem. D) = AB’C’ + AC + A’CD’ (b) F (W.List Boolean laws and their Duals. 5. B. iii. (b)Find the complement of the following Boolean functions and reduce them to minimum number of literals: i. Distributive. (bc’+ a’d) (ab’ + cd’) ii. (b)Simplify the following Boolean functions to minimum number of literals: i.jntuworld.5 . (c)Realize XOR gate using minimum number of NAND gates 2.

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