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State the associative law of boolean algebra.(May/june-2008) a)LAW1(of addition):A+(B+C)=(A+B)+C b)LAW2 (Of multiplication):(AB)C=A(BC) 3.Explain the demorgans theorem in Boolean algebra.(May-2011) 4.name the two basic types of Boolean algebra.(May- 2007) Standrad SOP and standard POS forms. 5.express F=BC+AC in A canonical SOP form.(Dec-2003) F=BC+AC = (A+A`)BC`+(B+B`)AC =ABC`+A`BC`+ABCAB`C 6.How many inputs are required for W=AB`D+ACD`+EE?(Dec-2004) Six inputs. 7.simply the following Boolean expression to a minimum number of literals;(Dec-2005) a) (X+Y) (X+Y`) =XX+XY`+XY+0 =X+X(Y`+Y) =X+X=X b) XY+X`Z+YZ=XY(Z+Z`)+X`Z(Y+Y`)+YZ(X+X`) =XYZ+XYZ`+X`YZ`+X`Y`Z+XYZ+X`YZ =XYZ+XYZ`+X`YZ+X`Y`Z =XY(Z+Z`)+XZ`(Y+Y`) =XY+X`Z. 8.simply the Boolean expressions:(May-2005) ab`c`+ab`c+abc=ab`c`+ac(b`+b) =ab`c`+ac = a(b`c`+c) (A+A`B=A) =a(b`+c) =ab`+ac 9.what is variable mapping?(May-2007) Representing the miterms of the sum of product expression in the K-MAP of appriate variables is known as variable mapping. 10.difference between completely and incompletely specified function(May/june2009). completely incompletely All the input conditions occur. Certain input conditions occur Each output corresponding to input output corresponding to non occuring conditions is defined. input conditions are undefined Each output has certain logical Undefined output doesnt have certain value,either 0 or 1 logical value,,but it isindicated by X,or d in truth tables F(a,b,c)=m(1,3,4,5) F(a,b,c)=m(1,3,4,5)+d(3,4)

11.what are the prime implicants?(dec-2005) All the implicants of a function determined using a K-MAP are called prime implicants. 12.state the features of tabular method(dec-2004) i)it is an extract method to simplify the Boolean expression. ii)it can used to simplify expression wity 7,8,or even 10 varibles. 13.why digtal circuits are more frequently used with NAND and NOR gate?(dec2006/may-2009) i)by using universal gates it is possible to reduce the number of ICS required to implement combinational circuit. 14.implement EX-OR gate using only NAND gate.(dec 2006) 15 .show that the bubbled AND gate works like a NOR gate.(may-2004) 16.how can a NAND gate works like a inverter.(may-2004) 17.Relize the function f(A,B)= AB`+A`B BY USING only NAND gate.(nov-2008) 18.give an application for XOR function.(may-20008) XOR function can be used as an inverter by connecting one input to logic 0.it can used as a module adder. 19.define combinational circuit.with an example.(may-2008) When the gates connected together to produce a specified output for a certain function of input variables with no storage involved the resulting circuit is called cominational circuit(.eg:AB+BC+CA). 20.Give the circuit of a half adder-subractor.(may-2007) 21.implement half adder using gates.(dec 2007) 22.what is the difference between half adder and full adder(dec-2007) 23.what will be the maximum number of outputs for a decoder with a 6-bit Data word?(may-2009) 2^6=64 24 mention the uses of decoder(dec-2007) 25.why MUX is called as data selector?(may-20011) 26.distingunish between decoder and demux.(may 2004) 27 distingunish between mux and demux.(may 2009) PART-B 1.State and prove DEmorgans theorem(dec2008,8marks) 2.plot K-MAP and simplify f(W,X,Y,Z)=(0,1,2,4,5,6,8,9,12,13,14).(dec2005,6marks) 3.solve g(w,x,y,z)=m(1,3,4,,6,11)+d(0,8,10,12,13)(may 2010,8marks) 4.express the function as the SOP using K-MAP f(a,b,c,d)=(0,2,4,5,6,,8,10,15)+d(7,13,14)(may 2005,12marks) 5.simplify the swithching function using K-MAP F(A,B,C,D)=(0,5,7,8,9,10,11,14,15)+D(1,4,13)(DEC2003,11MARKS) 6.simplify us using only K-MAP to obtain a minimum POS expression: (A`+B`+C+D)(A+B`+C+D)(A+B+C+D`)(A+B+C`+D`)(A`+B+C+D`) (A+B+C`+D)(MAY 2004)

7.simplify the five variable swithching function f(EDCBA)=(3,5,6,8,9,12,13,14,19,22,24,25,30) (DEC 2003) 8.Find the minimal SOP form for the following 6 variable switching function F(x1,x2,x3,x4,x5,x6)=m(2,3,6,7,10,14,18,19, 22,23,27,37,42,43,45,46,58,59) Implement the reduced function using NAND gates only.(may 2008,16marks) 9.obtain the minimum SOP USING quine MCCLUSKEY method using K-MAP F=m0+m2+m4+m8+m9+m10+m11+m12+m13.(dec2010,june 2007,8marks) 10,determine the prime implicants of the following function and verify using KMAP F=(A,B,C,D)=(3,4,5,7,9,13,14,15)(MAY-2009,16MARKS) 11.minimize the following using Quine Mccluskey method m(0,1,2,8,9,15,17,21,24,25,27,31) (nov-2008,7MARKS) 12.Relize i)OR gate ii)AND gate using only NOR gate,(may 2005,4 marks) 13.using K-MAP simplify:Y(A,B,C,D)=m1+m3+m5+m7+m8+m9+m0+m2+m10+m12+m13 Indicate the prime implicants,essentialand non essential primr implicants .draw the circuit using AND-OR-INVERT gates and also using NAND gates.(may2006,16marks). 16.implement the following function with NAND gates F(x,y,z)=(0,6).(dec2005,6marks) 17 A majority gate is a digital circuit whose output is equal to 1 if the majority of inputs are 1s .The output is 0 otherwise .using a truth table ,find the Boolean function implemented by a 3-input majority gate.simplify the function and implement with gates.(dec 2007,8marks). 18.The inputs to a circuit are the 4 bits of the binary number D3D2D1D0.The circuit produces a 1 if all of the following conditions hold i)MSB is 1 or any of the other bits are a 0. ii)D2 is a 1 or any of the other bits are a 0. iii)any of the 4 bits are a 0.Obtain a minimal expression for the output.(dec2008,8marks) 19.design a full adder .draw the logic circuit and truth table of full adder.(nov2010,6marks) 20.what is the drawback in binary parallel adder?how can it rectified?(dec2007,3marks) 21.design a BCD to EX-3 code converter using binary parallel adder.(dec-2007,6 marks)

UNIT-2 1.Define a sequential logic circuit .with an example.(may 2008) 2.what are synchronous sequential circuit?(may2010) 3.difference between combinational and sequential circuit(nov-2008) 4.give the meaning for edge triggering in flip flop.(dec-2006) 5.Draw the circuit of SR flip flop.(may-2010) 6.Draw the circuit of clocked JK flip flop.(may-2008)

7.With reference to JK flip flop what is racing?(may-2004,nov-2008) 8.give the characteristic equation and state diagramof JK flip flop.(april 2010) 9if the input frequency of a T FF is 1600 KHZ ,what will be the output frequency ? give reason for your answer.(dec-2006) 800KHZ,because it toggles at every clock pulse 10.give the exciaton table of SR,JK flip flop.(dec2008) 11.Give the state diagram ofJK FF(May-2007) 12.convert JKFF to D FF.(MAY 2007) 13What is the difference between parallel and serial transfer.what type of register is used in each case?(dec-2007) 14.define state.(dec 2006) 15 what is a mealy machine?give an example. 16. what are state diagrams and state tables(may 2006) 17. explain about state reduction ?(may-2009) 18.what is a self starting counter?(may-2010) 19.what is the minimum number of flip flops required to implement a modulo 21 synchronous counter?(dec 2003) 20. what is the minimum number of flip flops needed to design a counter of modulus 60?(may 2004) PART-B 1.design a BCD to EX-3 code converter using binary parallel adder.(dec-2007,6 marks). 2.Design a logic circuit to convert the 8421 BCD to excess -3 code.(may2010,12marks) 3.design and implement a 8421 to gray code converter .realize the converter using only NAND gates.(june-2009,16marks) 4.implement the following multiple output combinational logic circuit using a 4line to 16 line decoder. F1=m(1,2,4,7,8,11,12,13),F2=m(2,3,9,11),F3=m(10,12,13,14) F4=m(2,4,8).(DEC-2008,10MARKS) 5.Design and implement a full adder circuit using 3:8 decoder(may-2011,5marks) 6.explain the concept and working of quadruple 2 to 1 line mux.(may 2007,6marks) 7.implement the given function using multiplexer.F(x,y,z)= (0,2,6,7) (may 2007,10marks) 8. implement a full adder circuit using 8 :1 mux (may 2011,5 marks) 9.realize SR flip flop using NOR gates and NAND explain its operation . (dec2005,10marks) 10,derive the characteristics equation of a SR flip flop.(may 2004,8marks) 11.Explain of the working JK flip flop (may2006-8marks)

12.what is race condition and how is it overcome ?explain these concepts with its relevant timing diagrams.(may2006,8marks) 13.Explain the operation of JK master slave flip flop ,with its application.(dec2008.8marks) 14.convert a SR flipflop to D flip flop (dec-2008,8marks) 15.difference between synchronous and asynchronous sequential circuit. (may2006,4marks) 16.compare moore and mealy model (may 2005-4marks) 17.Explain the various steps in the analysis of synchronous sequential circuit with suitable example.(dec-2003,8marks) 18.A sequential circuit with 2D FF s A and B and input X and output Y is specified by the following next state and output equations . A(t+1)=AX+BX B(t+1)=A`X Y=(A+B)X`i).Draw the logic diagram of the circuit .ii)derive the state table.iii)derive the state diagram.(DEC2006,16MARKS) 19 A sequential circuit has four FF s ABCD and an input X is defined by the following state equations: A(t+1)=(CD`+C`D)X+(CD`+C`D`))X` B(t+1)=B D(t+1)=C i)Obtain the sequence of states when X=1 ,Starting from state ABCD =0001 ii)Obtain the sequence of states when X=0,Starting from state ABCD =0000.(DEC 2007,16MARKS) 20.A sequential circuit has one flipflop Q two inputs x and y and one output S .it consists of a full adder circuit connected to a D flip flop as shown below .derive the state table and state diagram of the sequential circuit.(dec-2007,12marks)

(diagram)

22.Design a counter with the sequence 0,1,3,7,6,4,0 (dec 2010,16marks) 23.design a BCD up/down counter using SR flip flop(nov-2008,6marks) 24.design a synchronous counter using JK flip flop to count the follwing sequence 7,4,3,1,6,0,7.(may-2009,16marks) 25.design and implement a synchronous decade counter using T flip flop .draw the timing diagram.(may 2008,16marks) 26.design a 3 bit synoronous gray code counter using T flip flop (dec 2005,10marks) page no 4,58) 27.design BCD ripple counter using JK flip flop(may 2010,16marks) UNIT-3 1.What is an asynchronous sequential circuit?(dec -2004)

2.how does the operation of an asynchronous input differ from that of synchronous input?(dec-2005) 3.what is a fundamental mode asynchronous sequential circuit?(dec-2003) 4.what are the types of asynchronous circuits? 5.define critical race and non critical race. 6.define secondary variables and excitation variables. 7.what are the different techniques used in state assignment? 8.what are races? 9.what is fundamental mode asynchronous sequential circuit?(dec-2003) PART-B 1.Illustrate pulse mode asynochronous circuit.(nov2006,8marks) 2design a pulse mode circuit having two input lines x1 and x2 and one output line z,as shown in fig below .the circuit should produce an output pulse to coincide with the last input pulse in the sequence x1-x2-x2.no other input sequence should produce an output pulse.(may 2008,16marks)(5.11) 3design a pulse mode circuit having two input lines x1 and x2 and one output line z,as shown in fig below .the output should change from 0 to 1 ,only for input sequence x1-x2-x3 occurs while z=0 ,also the output z should remain in 1 until x2 occurs .use SR flip flops for the design(june 2009,16marks) 4.list and explain the steps used for analyzing an asynchronous sequential circuit. (nov 2010,8marks) 5describe the steps involved in design of asynronous sequential circuit in detail with an example(may 2011,16 marks) 6.develop the state diagram and primitive row flow table for a logic system that has two input S and R and a single output Q .the device is to be an edge triggered SR flip flop but without a clock.the device changes state on the rising edges of the two inputs.static input values are not to have any effect in changing the Q output.(dec2006,16marks)(5.24) 7.define asynoronous sequential circuit ,cycles,critical race,non critical race(dec2008,8marks) 8.when do you get the critical and non critical races ?how will you obtain race free conditions?(dec-2010,10marks) 9.design an asynchronous sequential circuit with two inputs X and Y and with one output Z.whenever Y is 1,input X is transferred toZ .When Y is 0 ,the output does not change for any change inX.(MAY 2003,16MARKS) 10Design an asynchronous sequential circuit that has two inputs X2 and x1 and one Output Z.when X1=0,the output Z is 0.the first change in X2 that occurs while X1 is 1 will cause output Z tobe 1.the output Z will remain 1 untill X1 returns to 0. (dec-08june-09 16marks)

11.design a two input (x1,x2),two output (z1,z2) fundamental mode circuit that has the following specifications .when x1x2=00,z1z2=00.the output10 will be produced following the occurrence of the input sequence 00-01-11.the output will remain at 10 untill the input returns to00 at which time it becomes 00.an output of 01 will be pr oduced following the receipt of the input sequence 00-10-11. and once again ,the output will remain at 01 untill a 00 input occurs ,which returns the output to 00.(may2008,16 marks) UNIT-4 1.Define memory cell.give an example(dec-2004) 2.define a memory location.(may-2006) 3.what is a votile memory?give example.(dec-2007) 4.name the types of ROM.(MAY-2011) 5.what is PLA?(MAY-2008) 6.Whether PLA is same asPLA?explain.(DEC 2003) 7 what are the advantages of PLA over ROM?(MAY 2010) 8.what is FPGA? 9..Classify the basic families that belong to the bipolar families and to the MOS families.(may-2006) 10.define noise margin(nov-2008) 11.what is fan out of a gate?(dec-2006) 12.define power dissipation and propagation delay.(may-2005) 13.why does the propagation delay occur in logic circuits?(dec-2006) 14.differentiate source and sink current(may -2007) 15.distinguish between 7400 series and 5400series(may-2004) 16.what is meant by tristate capability?(may-2007) 17.give an application of open collector logic.(may-2007) 18.list the advantages of ECL as comparaed to ttl logic family(dec-2003) 19.what are the major difference between ECL and TTL? 20.which is faster TTL or ECL? Which requires more power to operate?(dec20007) 21.what is the effect of increasing the supply voltage on the propagation delay of the CMOS gates?(may-2009) 22.what is the major difference between ECL and TTL?(DEC2006) PART-B 1.Write a description note on memories.(may 2006,16 marks) 2.write notes on ROM and its types (dec-2007,16marks) 3.describe the characteristics of all types of memories.(april 2011,6marks)

4.describe the working of EPROM .list the applications of EPROM. (DEC2010,8MARKS) 5.Describe the concept and working and applications of the PLD. (MAY2007,3MARKS) 6.Design a combinational circuit using ROM .The circuit accepts 3-bit number and generate an output binary number equal to square of input number (april 2010,16 marks) 7.design ROM for the following functions F1=(1,2,3) F2=(0,2) (MAY 2011 ,7MARKS) 8.Discuss the concept working and applications of PLA.(DEC2006,6MARKS) 9Draw a PLA circuit to implement the logic functions A`BC+AB`C+AC` and A`B`C`+BC(NOV 2008,6MARKS) 10.Implemant the following two Boolean functions with a PLA F1(A,B,C)=(0,1,2,4) F2(A,B,C)=(0,5,6,7) (MAY 2011,10MARKS) 11.A combinational circuit is defined by functions F1(A,B,C)=(3,5,6,7) F2(A,B,C)=(0,2,4,7) .implement the circuit with a PLA having three inputs ,four product terms and two outputs (dec 2005.6marks) 12.generate the following boolean functions with a PAL with 4 inputs and 4 outputs. Y3=A`BC`D+A`BCD`+ABC`D,Y2=A`BCD`+A`BCD+ABCD.Y1=A`BC`+A`BC +AB`C+ABC`,Y0=ABCD.(DEC 2004,8MARKS) 13.A combinational logic circuitis defined by the following function F1(a.b,c)= )=(0,1,6,7) F2(a.b,c)= )=(2,3,5,7).implement the circuit with a PAL having three inputs ,three product terms and two outputs.(may 2005,10marks) 13.describe the concept ,working and applications of FPGA.(DEC 2010,6MARKS) 14.Explain the concept operation and characteristics of TTL family.(dec-2010 8marks) 15.draw the TTL inverter circuit.(dec 2004.10marks) 16.explain the working of 2 input TTL totem-pole NAND gate circuit (may/june2008,8marks) 17 explain the working of a 3-input TTL totem pole NAND gate.(dec2008,10marks) 18.draw the circuit diagram and explain the working of TTL INVERTER with tristate output.(may 2009,8marks) 19.discuss about the TTL parameters(dec-2004,10marks) 20.explain the concept operation and characteristics of CMOS technology.(dec2010,8marks) 21.sketch the typical transfer characteristics of a CMOS inverter.(may2004,4marks) 22.draw the circuit of a CMOS two input NAND gate and explain its operation. (dec,june-2008,8marks) 23.draw and explain the circuit diagram of a CMOS NOR gate.(may 2004,12marks) 24.explain the characteristics of CMOS family.(dec/may-2007,8marks)

25.explain the concept and implementation ,characteristics of ECL family. (dec2006,8marks) 26.Compare the various digital logic families (nov/dec-2008,10marks)

UNIT-5 1.When can RTL be used to represent digital systems?(may-2011) 2.what are the various modeling techniques in HDL?(APRIL-2010) 3.Write HDL for half adder(may-2010) 4.write VHDL code for AND gate(dec2010) 5.list the operators available in VHDL(DEC 2010) 6.What are ASM?(may-2011) 7.draw the basic RTL circuit.(nov-2010) 8.define test bench.(nov2010) 9write a behavioural description of 2-to-1line mux(nov 2010) PART-B 1.Write a VHDL code for mod 6 counter (may 2011,16marks) 2.explain the design procedure of RTL using VHDL.(MAY 2010.10MARKS) 3.Describe the RTL in VHDL.(MAY 2011,16MARKS) 4 Write a note on VHDL testbench (dec2010,6marks) 5.Explain e design unit entity,architecture and configurationrelated to VHDL with its syntax 6.design a 2:1 mux using when else,with select,case and if else statement

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