AMD-640

Application Note

TM

Chipset BIOS Design

© 1997 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this publication. This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or systems without AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of AMD products except as provided in AMD’s Terms and Conditions of Sale for such product.

Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. AMD-640, AMD-645, K86, AMD-K5, and AMD-K6 are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks, and Windows NT is a trademark of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Audience It is assumed that the reader possesses the proper knowledge of the AMD-640 Chipset. This document contains information on a product under development at Advanced Micro Devices. Document #: 21338 Issue Date: March 1997 Rev. order# 21095. The information is intended to help you evaluate this product. which includes the AMD-640TM System Controller and the AMD-645TM Peripheral Bus Controller. and programming requirements to understand the information presented in this document. the x86 architecture. and the AMD-645TM Peripheral Bus Controller Data Sheet. order# 21090. The information provided is for demonstration purposes. There can be more than one way to implement the functionality detailed in this document. AMD reserves the right to change or discontinue work on this proposed product without notice.AMD-640TM Chipset BIOS Design Application Note AMD-640TM Chipset BIOS Design This document highlights the BIOS modifications required to fully support the AMD-640 T M Chipset. This document is a supplement to the AMD-640TM System Controller Data Sheet. A Amendment/0 .

1. and 3 are addressed in the same 32-bit physical register. If bit 31 is cleared. and assert byte enable 2 (clear C/BE2). the AMD-640 System Controller passes the data through as an I/O transaction. and function number of the AMD-640 System Controller are all 0000h. Figure 1 shows a layout of the target address numbers within I/O addresses 0CFBh–0CF8h. specifies the configuration register offset number. in conjunction with the PCI byte enable lines C/BE3–C/BE0. write bits 7–2 of 52h (010100b) to the register number (bits 7–2 of I/O address 0CF8h). and function number of the AMD-645 Peripheral Bus Controller are all 00000000_00001_XXXb. device number. function. For example. described in PCI Local Bus Specification Revision 2. Table 1 shows the registers from a logical/functional standpoint by describing them as distinct 8-bit or 16-bit entities. the Non-Cacheable Control register is described as residing at offset 52h. To access this register. This mechanism. employs I/O locations 0CF8h–0CFBh to specify the target address. Offsets 0.1. device number. 2 . PCI Mechanism #1 Target Address Layout (I/O Address 0CFBh–OCF8h) To specify the PCI configuration space. The register number addresses a 32-bit word which. and locations 0CFCh–0CFFh for data to or from the target address. The target address includes the PCI bus. and register numbers of the PCI device. device. 31 En bit 30 – Reserved bit 24 bit 23 – Bus Number bit 16 bit 15 – bit 11 10 – 8 bit 7 – bit 2 1 0 0 0 Device Number Function # Register Number Figure 1. 2. The bus number.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 PCI Configuration Mechanism The AMD-640 Chipset uses PCI configuration mechanism #1 to convey and receive configuration data to and from the host processor. set bit 31 (the enable bit) to 1. The bus number.

order# 21090. IO_CNTRL IO_DATA32 IO_EVEN_DATA16 IO_ODD_DATA16 IO_0_DATA8 IO_1_DATA8 IO_2_DATA8 IO_3_DATA8 Configuration Port Register Summary I/O Address 0CF8h 0CFCh 0CFCh 0CFEh 0CFCh 0CFDh 0CFEh 0CFFh Type RW RW RW RW RW RW RW RW Default Value 0000_0000h 0000_0000h 0000h 0000h 00h 00h 00h 00h Size 32 32 16 16 8 8 8 8 Register Name AMD-640TM System Controller Initialization All programmable features in the AMD-640 System Controller are controlled by the PCI configuration registers. see the AMD-640TM System Controller Data Sheet. Table 1. Access types are indicated as follows: s s s RW—Read/Write RO—Read Only RWC—Read: write 1’s to clear individual bits 3 . This section summarizes the register functions. access types. which are normally written to only during system initialization.21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 1 shows the ports used to access the AMD-640 System Controller and AMD-645 Peripheral Bus Controller. default values. and addresses (offset numbers). For more detailed descriptions of the configuration registers.

AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Table 2 shows the PCI defined registers read by the BIOS during system initialization. Rev E = 03 and Rev F = 04. Table 3. 512k bytes L1=L2=WB PCI concurrency Disabled Disabled RW RW RW RW RW RW Access 50h 51h 52h 53h 55h–54h 57h-56h Cache Control 1 Cache Control 2 Non-Cacheable Control System Performance Control Non-Cacheable Region #1 Non-Cacheable Region #2 00h 00h 02h 00h 0000h 0000h 83h 01h 96h 78h – – 4 . Offset 01–00h 03-02h 05-04h 07-06h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h–3Fh Note: Configuration Space Header Registers PCI Header Vendor ID Device ID Command Status Revision ID Program Interface Bus Class Code Base Class Code Cache Line Size Latency Timer Header Type Built-In Self Test (BIST) Reserved Default 1106h 0595h 0017h 02A0h nn* 00h 00h 06h 00h 00h 00h 00h 00h Access RO RO RW RWC RO RO RO RO RO RW RO RO – * nn changes for each device revision. PBSRAM 1 bank. Table 3 shows device-specific cache control registers and recommended values. Offset Configuration Space Cache Control Registers Cache Control Default Setting Recommended Result Normal operation. Table 2. Rev D = 02 is the current revision as of publication of this document.

ensure acceptable performance but may not be optimal for a particular system. Table 4. Offset Configuration Space DRAM Control Registers Cache Control Default Setting Recommended Result 10 bit Col banks 0-3 populated 64M—02 for 8 Meg 64M—04 for 8 Meg 64M—06 for 8 Meg 64M—08 for 8 Meg 64M—08 for no RAM 64M—08 for no RAM Fast Page Mode banks 0–3 EDO mode Video BIOS disable main BIOS slowest initially 60 nsec EDO 60 nsec FP Page open Fast decode Latch delay 64 bit DRAM – 15 µsec CBR – 24 ma drive – – RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h DRAM Configuration Register #1 DRAM Configuration Register #2 DRAM Bank 0 Ending [HA29-22] DRAM Bank 1 Ending [HA29-22] DRAM Bank 2 Ending [HA29-22] DRAM Bank 3 Ending [HA29-22] DRAM Bank 4 Ending [HA29-22] DRAM Bank 5 Ending [HA29-22] DRAM Type Shadow RAM Control Register #1 Shadow RAM Control Register #2 Shadow RAM Control Register #3 DRAM Timing 40h 05h 01h 01h 01h 01h 01h 01h 00h 00h 00h 00h ABh 44h 03h 10h 20h 30h 40h 50h 60h 00h 05h CAh 00h 22h FFh 4h 57h A4h 65h DRAM Control Register #1 00h 66h 67h 69h–68h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh DRAM Control Register #2 32-Bit DRAM Width Control Register Reserved DRAM Refresh Counter DRAM Refresh Control Register SDRAM Control Register DRAM Drive Strength Control Register ECC Control Register ECC Status Register 00h 00h – 00h 00h 00h 00h 00h 00h 00h 00h – 43h 80h 00h 4Fh 00h 00h RW RW – RW RW RW RW RW RO 5 . These values.21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 4 shows the recommended values for Fast Page mode. EDO. and SDRAM. which are programmed during initialization.

Table 5. write 1’s to clear individual bits 6 . access types. REQ based CPU has priority. This section summarizes the register functions. For more detailed descriptions of the configuration registers. which are programmed during initialization.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Table 5 shows the PCI control registers. Access types are indicated as follows: s s s s RW—Read/Write RO—Read Only WO—Write Only RWC—Read. default values. and addresses. which are normally written to during system initialization. Offset Configuration Space PCI Control Registers Cache Control Default Setting Recommended Result Enable Write Buffers and prefetch Post writes to DRAM and Merge Reduce FRAME STOP control Enhance Commands PCI has priority. These registers. control the processor bus to PCI bus. Override 75 RW RW RW RW RW RW RW Access 70h 71h 72h 73h 74h 75h 76h PCI Buffer Control 1 Processor to PCI Flow Control #1 Processor to PCI Flow Control #2 PCI Target Control PCI Initiator Control PCI Arbitration Control #1 PCI Arbitration Control #2 00h 00h 02h 00h 00h 00h 00h E0h DEh ECh 8Dh C0h 00h 80h AMD-645TM Peripheral Bus Controller Initialization All programmable features in the AMD-645 Peripheral Bus Controller are controlled by the PCI configuration registers. see the AMD-645TM Peripheral Bus Controller Data Sheet. order# 21095.

Port 20h 21h 20h 21h Note: Master Interrupt Controller Registers Register Name Master Interrupt Control Master Interrupt Mask Master Interrupt Control Shadow Master Interrupt Mask Shadow Default n/a n/a n/a n/a Recommended Setting n/a n/a n/a n/a Result * * RW RW Access * RW. Table 6. which are provided for backwards compatibility. 7 . There are 16 Master DMA control registers.21338A/0—March 1997 AMD-640TM Chipset BIOS Design Legacy I/O Registers Table 6 contains registers that control Master DMA channels 0 – 3. Port Master DMA Controller Registers Register Name Default Recommended Setting Result RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO RW Access 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh Ch 0 Base/Current Address Ch 0 Base/Current Count Ch 1 Base/Current Address Ch 1 Base/Current Count Ch 2 Base/Current Address Ch 2 Base/Current Count Ch 3 Base/Current Address Ch 3 Base/Current Count Status/Command Write Request Write Single Mask Write Mode Clear Byte Pointer F/F Master Clear Clear Mask RW All Mask Bits n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Table 7 shows the registers for the master hardware interrupt controller channels 0–7. Table 7. if shadow registers are disabled.

AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Table 8 shows the timer/counter registers. Table 10. These registers are used for ISA REFRESH and speaker sounds. Table 8. Port Keyboard Controller Registers Register Name Default Recommended Setting Result RW RW RW Access 60h 61h 64h Keyboard Controller Data Miscellaneous Functions and Speaker Control Keyboard Controller Command/Status n/a n/a n/a n/a n/a n/a Table 10 shows the registers used for controlling the storing of system configurations saved in CMOS. Table 9. CMOS/RTC/NMI Registers Port 70h 71h 72h 73h 74h 75h Register Name CMOS Memory Address & NMI Disable CMOS Memory Data (128 bytes) CMOS Memory Address CMOS Memory Data (256 bytes) CMOS Memory Address CMOS Memory Data (256 bytes) Default n/a n/a n/a n/a n/a n/a Recommended Setting n/a n/a n/a n/a n/a n/a Result WO RW RW RW RW RW Access 8 . Port Timer/Counter Registers Register Name Default Recommended Setting Result RW RW RW WO Access 40h 41h 42h 43h Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter Control n/a n/a n/a n/a n/a n/a n/a n/a Table 9 shows the registers used for controlling the commands and status of the keyboard and mouse interfaces.

21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 11 shows the registers used to access the upper 8 bits of the DMA address space (A16– A23). if shadow registers are disabled. hard disk activity LED. Table 11. 9 . DMA Page Registers Port Register Name Default Recommended Setting 87h 83h 81h 82h 8Fh 8Bh 89h 8Ah DMA Page—DMA Channel 0 DMA Page—DMA Channel 1 DMA Page—DMA Channel 2 DMA Page—DMA Channel 3 DMA Page—DMA Channel 4 DMA Page—DMA Channel 5 DMA Page—DMA Channel 6 DMA Page—DMA Channel 7 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Result RW RW RW RW RW RW RW RW Access Table 12 shows a system control register that is used for fast A20 switching. These registers are use to control the hardware interrupts 8–15. Table 12. Slave Interrupt Controller Registers Port Register Name Default Recommended Setting A0h A1h A0h A1h Note: Access Result * * RW RW Slave Interrupt Control Slave Interrupt Mask Slave Interrupt Control Shadow Slave Interrupt Mask Shadow n/a n/a n/a n/a n/a n/a n/a n/a * RW. Table 13. The bits for A0 – A15 are shown in Table 6 on page 7 and in Table 14 on page 10. and high-speed resets. System Control Registers Port Register Name Default Recommended Setting 92h System Control n/a n/a Result RW Access Table 13 shows the registers used to control the slave interrupt controller.

These channels are used to control the system DMA channels 4–7. Slave DMA Controller Registers Port Register Name Default Recommended Setting C0h C2h C4h C6h C8h CAh CCh CEh D0h D2h D4h D6h D8h DAh DCh DEh Ch 0 Base/Current Address Ch 0 Base/Current Count Ch 1 Base/Current Address Ch 1 Base/Current Count Ch 2 Base/Current Address Ch 2 Base/Current Count Ch 3 Base/Current Address Ch 3 Base/Current Count Status/Command Write Request Write Single Mask Write Mode Clear Byte Pointer F/F Master Clear Clear Mask RW All Mask Bits n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Result RW RW RW RW RW RW RW RW RW WO WO WO WO WO WO RW Access 10 . Table 14.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Table 14 shows channels 0–3 of the slave DMA controller.

Table 15. Configuration Space PCI-to-ISA Header Registers Offset PCI Header Default Recommended Setting 01h–00h 03h–02h 05h–04h 07h–06h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 3Fh–10h Vendor ID Device ID Command Status Revision ID (00h = first silicon) Program Interface Sub Class Code Base Class Code Reserved (Cache Line Size) Reserved (Latency Timer) Header Type Built-In Self Test (BIST) Reserved 1106h 0586h 000Fh 0200h – 00h 01h 06h 00h 00h 80h 00h 00h n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Result RO RO RW RWC RO RO RO RO – – RO RO – Access 11 .21338A/0—March 1997 AMD-640TM Chipset BIOS Design PCI Function 0 Registers—PCI-to-ISA Bridge Table 15 shows configuration registers of the PCI-to-ISA bridge.

IDE — Wait for PGNT before Grant to ISA Master/DMA 4Ah IDE Interrupt Routing 04h C4h Access ports 00-FFh via SD IDE Primary Channel IRQ14 Secondary Ch IRQ 15 4Bh 4Ch 4Dh 4Fh–4Eh Reserved DMA/Master Mem Access Ctrl 1 DMA/Master Mem Access Ctrl 2 DMA/Master Mem Access Ctrl 3 00h 00h 00h 0300h 00h 00h 00h F300h — PCI memory hole bottom address HA[23–16]=0 PCI Memory hole top address HA[23–16]=0 Top of PCI memory for ISA=16Mbytes Forward 00000h-9FFFFh access to PCI — RW RW RW RW RW RW RW RW RW RW RW RW RW — Access 12 . Table 16.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Table 16 shows the registers used to control the ISA bus. ISA Bus Control Registers Offset 40h 41H 42h 43h 44h 45h 46h 47h 48h 49h Register ISA Bus Control ISA Test Mode ISA Clock Control ROM Decode Control Keyboard Controller Control Type F DMA Control Miscellaneous Control 1 Miscellaneous Control 2 Miscellaneous Control 3 Reserved Default Setting 00h 00h 00h 00h 00h 00h 00h 00h 01h 00h 00h 01h 00h 00h 01h 00h 10h C0h 01h 00h Recommended Result Normal ISA Timing Refresh test mode ISA clock=PCICLK/4 ROMCS F0000h-FFFFFh Disable mouse lock Set DMA type F if needed Disable Post Memory Write INIT as CPU reset Enable PCI delay transaction Enable USB.

Plug and Play Control Registers Offset Register Default Setting 50h 53h–51h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Fh–5Ch Note: Recommended Result — — PIRQs inverted edge trigger/ Non-inverted level trigger MIRQs disabled INTB routes to IRQ11 INTA disabled INTD routes to IRQ5 INTC routes to IRQ7 MIRQ2 disabled Configure as MASTER Enable Int RTc. PS2 mouse. Test enable — Access Reserved (do not program) Reserved PCI IRQ Edge/Level Selection PnP Routing for External MIRQ0–1 PnP Routing for PCI INTB–A PnP Routing for PIC INTD–C PnP Routing for External MIRQ2 MIRQ Pin Configuration XD Power-On Strap Options Internal RTC Test Mode Reserved 24h 00h 00h 00h 00h 00h 00h 04h * 00h 00h 24h 00h 00h 00h B0h 57h 00h 04h F7h 00h 00h RW — RW RW RW RW RW RW RW RW — * Power-up default value depends on external strapping. 13 . SRAM access enable. Int KBC RTC reset enable. Table 17.21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 17 shows the registers used to control plug and play routing to ISA IRQs.

AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Table 18 shows the registers used to control Distributed DMA. Table 18. Distributed DMA Offset 61h–60h 63h–62h 65h–64h 67h–66h 69h–68h 6Bh–6Ah 6Dh–6Ch 6Fh–6Eh FFh–70h Register Channel 0 Base Address/ Enable Channel 1Base Address/ Enable Channel 2 Base Address/ Enable Channel 3 Base Address/ Enable Reserved Channel 5 Base Address/ Enable Channel 6 Base Address/ Enable Channel 7 Base Address/ Enable Reserved Default Setting 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 00h Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled — Recommended Result RW RW RW RW — RW RW RW — Access 14 .

21338A/0—March 1997 AMD-640TM Chipset BIOS Design PCI Function 1 Registers—IDE Control Table 19 shows configuration registers used for enhanced IDE and PCI. Table 19. Configuration Space IDE Header Registers Offset PCI Header Default Recommended Setting 01h–00h 03h–02h 05h–04h 07h–06h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 13h–10h 17h–14h 1Bh–18h 1Fh–1Ch 23h–20h 2Fh–24h 33h–30h 3Bh–33h 3Ch 3Dh 3Eh 3Fh Vendor ID Device ID Command Status Revision ID (00h = first silicon) Program Interface Sub Class Code Base Class Code Reserved (Cache Line Size) Latency Timer Header Type Built-In Self Test (BIST) Base Address—Primary Data/Command Base Address—Primary Control/Status Base Address—Secondary Data/Command Base Address—Secondary Control/Status Base Address—Bus Master Control Reserved (unassigned) Reserved (expansion ROM base address) Reserved (unassigned) Interrupt Line Interrupt Pin Minimum Grant Maximum Latency 1106h 0571h 0080h 0280h — 8Ah 01h 01h 00h 20h 00h 00h 000001F0h 000003F4h 00000170h 00000374h 0000CC01h 00h 00h 00h 0Eh 00h 00h 00h n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Result RO RO RW RW RO RW RO RO — RW RO RO RW RW RW RW RW — — — RW RO RO RO Access 15 .

DIOR and DIOW pulse width set to 17 PCI clocks Pri non-1F0 Port Access.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Tab l e 2 0 shows re g is t ers u se d t o c o n t ro l I DE c on t rol parameters. Configuration Space IDE Registers Offset 40h 41h 42h 43h Chip Enable IDE Configuration Reserved (do not program) FIFO Configuration Register Default Setting 04h 02h 09h 3Ah 0Bh E2h 09h 3Ah Recommended Result Enable Pri and Sec Channel Enable Pri and Sec read prefetch buffer Enable Pri Post Write Buffer – Allocate 8 word buffers in both Pri and Sec Channel Set threshold to 1/2 44h 45h 46h Miscellaneous Control 1 Miscellaneous Control 2 Miscellaneous Control 3 68h 00h C0h 68h 00h C0h Master Read/Write Cycle IRDY 1 wait state FIFO output Data 12 clock advance No channel interrupts swap Pri and Sec Ch Read DMA FIFO flush enabled No limit in DRDY pulse width 4Bh–48h 4Ch 4Dh 4Eh Drive Timing Control Address Setup Time Reserved (do not program) Sec Non-1F0h Port Access Timing Pri Non-1F0h Port Access Timing UltraDMA33 Exit Timing Control Reserved A8A8A8 A8h FFh 00h FFh A8A8A8 A8h FFh 00h FFh DIOR and DIOW pulse width set to 11 PCI clocks Recovery time set to 9 clocks Address setup time 4T – Sec non-1F0 Port Access. Table 20. DIOR and DIOW pulse width set to 17 PCI clocks Pri and Sec Drive 0 and 1 Mode enabled by Set Feature command Disabled UltraDMA33-Mode – – RW RW RW RW RW RW RW RW RW RW RW Access 4Fh FFh FFh 030303 03h 00h RW 53h–50h 57h-54h 03030303h 00h RW 16 .

21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 20. Configuration Space IDE Registers (continued) Offset Register Default Setting 5Fh–58h 61h–60h 67h–62h 69h–68h FFh–6Ah Reserved Primary Sector Size Reserved Secondary Sector Size Reserved A8A8A8 A8h 0200h 00h 0200h 00h A8A8A8 A8h 0200h 00h 0200 00 Recommended Result – 200h bytes per sector – 200h bytes per sector – – RW – RW – Access Table 21 shows the registers used for controlling IDE. These registers are provided for backwards compatibility. Table 21. IDE Controller I/O Registers Offset Register Name Default Recommended Setting 00h 01h 02h 03h 07h–04h 08h 09h 0Ah 0Bh 0Fh–0Ch Primary Channel Command Reserved Primary Channel Status Reserved Primary Channel PRD Table Address Secondary Channel Command Reserved Secondary Channel Status Reserved Secondary Channel PRD Table Address 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Result RW — RWC — RW RW — RWC — RW Access 17 .

Configuration Space USB Header Registers Offset PCI Header Default Recommended Setting 01h–00h 03h–02h 05h–04h 07h–06h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h–1Fh 23h–20h 3Bh–24h 3Ch 3Dh 3Fh–3Eh Vendor ID Device ID Command Status Revision ID (00h = first silicon) Program Interface Sub Class Code Base Class Code Reserved (Cache Line Size) Latency Timer Header Type Built-In Self Test (BIST) Reserved Base Address Reserved Interrupt Line Interrupt Pin Reserved 1106h 3038h 0000h 0200h n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Result RO RO RW RWC RO RO RO RO RO RW RO RO Access – 00h 03h 0Ch 00h 16h 00h 00h 00h 0000301h 00h 00h 04h 00h – RW – RW RW – 18 . Table 22.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 PCI Function 2 Registers—USB Controller Table 22 shows configuration registers used for the universal serial bus (USB). This implementation of USB is compatible with UHCI v1.1.

Table 23. MWI ISB Data Length 1280 40h Miscellaneous Control 1 00h 00h Disable USB Power Management DMA 16 DW burst access PCI zero wait state 41h 43h–42h 45h–44h 47h 5Fh–48h 60h BFh–61h FFh–C2h Miscellaneous Control 1 Reserved Reserved (do not program) Reserved Reserved Serial Bus Release Number Reserved Reserved 00h 00h 00C2h 0Ch 00h 10h 00h 2000h 00h 00h 00h 00C2h 0Ch 00h 10h 00h 2000h 00h Always set trap 60/64 status bit A20 gate pass through RW RO RW RW Access – – – – Always read 10h – – RO – Always read 2000h – RO C1h–C0h Legacy Support – – Table 24 shows registers used to access the USB through I/O. Configuration Space USB Registers Offset Register Default Setting Recommended Result Support MRL.21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 23 shows registers used to control the USB. Table 24. MRM. USB Controller I/O Registers Offset 1h–0h 3h–2h 5h–4h 7h–6h Bh–8h Ch 11h–10h 13h–12h Register Name USB Command USB Status USB Interrupt Enable Frame Number Frame List Base Address Start of Frame Modify Port 1 Status/Control Port 2 Status/control Default 0000h 0000h 0000h 0000h 00000000h 40h 0080h 0080h Recommended Setting n/a n/a n/a n/a n/a n/a n/a n/a Result RW RWC RW RW RW RW RWC RWC Access 19 .

Configuration Space Power Management Header Registers Offset PCI Header Default Recommended Setting 01h–00h 03h–02h 05h–04h 07h–06h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h–1Fh 23h–20h 3Fh–24h Vendor ID Device ID Command Status Revision ID (00h = first silicon) Program Interface Sub Class Code Base Class Code Reserved Latency Timer Header Type Built-In Self Test (BIST) Reserved I/O Register Base Address Reserved 1106h 3040h 0000h 0280h — 00h 00h 00h 00h 16h 00h 00h 00h 00000001h 00h n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Result RO RO RW RWC RO RO RO RO RO RW RO RO — RW — Access 20 . Table 25.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 PCI Function 3 Registers—Power Management Power Management Configuration Space Registers Table 25 shows configuration registers used for the Advanced Configuration Power Interface (ACPI) and legacy power management.

Table 26.21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 26 shows registers used to control ACPI through the PCI bus. Configuration Space Power Management Registers Offset Register Default Setting 40h Pin Configuration C0h C0h Recommended Result Define pin 136 as GPIO4 Define pin 92 as GPIO4 Disable PWRBTN debounce 41h General Configuration 00h 00h Disable ACPI Timer Reset ACPI 24-bit timer count 32us Clock Throttling 42h 43h SCI Interrupt Configuration Reserved 00h 00h 0000h 0000h 00h 00h 0000h 0000h Disable Pri interrupt Channel Disable Sec interrupt Channel Disable Conserve Mode 53h–50h GP Timer Control 00000000h 00000000h Disable Sec Event Time Disable GP1 Timer Disable GP0 Timer 54h–60h Reserved 61h 62h 63h Programming Interface Read Value Sub Class Read Value Base Class Read Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h RW Disable SCI interrupt RW RW RW RW RW RW Access 45h–44h Primary Interrupt Channel 47h–46h Secondary Interrupt Channel – Value to be returned by register at offset 09h Value to be returned by register at offset 0Ah Value to be returned by register at offset 0Bh – WO WO WO 64h–FFh Reserved – – 21 .

Table 28. Table 29. General Purpose Power Management Registers Offset Register Name Default Recommended Setting 21h–20h 23h–22h 25h–24h 27h–26h General Purpose Status General Purpose SCI Enable General Purpose SMI Enable Power Supply Control 00h 00h 00h 00h n/a n/a n/a n/a Result RWC RW RW RW Access 22 .AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Power Management I/O Space Registers Table 27 shows registers used to control legacy power management features through I/O. Processor Power Management Registers Offset Register Name Default Recommended Setting 13h–10h 14h 15h Processor Control Processor Level 2 Processor Level 3 0000h 00h 00h n/a n/a n/a Result RW RO RO Access Table 29 shows registers used to control SCI and SMI features. Table 27. Basic Power Management Control/Status Registers Offset Register Name Default Recommended Setting 01h–00h 03h–02h 05h–04h 0Bh–08h Power Management Status Power Management Enable Power Management Control Power Management Timer 00h 00h 00h 00h n/a n/a n/a n/a Result RWC RW RW RW Access Table 28 shows power management registers used to control SPTCLK.

Table 31. Table 30. Generic Power Management Registers Offset Register Name Default Recommended Setting 29h–28h 2Bh–2Ah 2Dh–2Ch 2Fh 33h–30h 37h–34h 3Bh–38h Global Status Global Enable Global Control SMI Command Primary Activity Detect Status Primary Activity Detect Enable GP Timer Reload Enable 00h 00h 00h 00h 00h 00h 00h n/a n/a n/a n/a n/a n/a n/a Result RWC RW RW RW RWC RW RW Access Table 31 shows registers used to control I/O features of SCI and SMI.21338A/0—March 1997 AMD-640TM Chipset BIOS Design Table 30 shows registers used to control generic global power management registers. General Purpose I/O Offset Register Name Default Recommended Setting 40h 42h 44h 47h–46h 49h–48h GPIO Direction Control GPIO Port Output Value GPIO Port Input Value GPO Port Output Value GPI Port Input Value 00h 00 input 0000 input n/a n/a n/a n/a n/a Result RW RW RO RW RO Access 23 .

Timing dependent software that relies on the specific latencies of other processors should be retested for proper operation with the AMD-K6 processor. Pa r t i c u l a r a t t e n t i o n s ho u l d b e p a i d t o m e m o ry -se t u p subroutines that determine the type of DRAM in the system. retesting should be performed on components with variable timing (i. Some chipsets may not tolerate a DRAM mode change (i. the Intel 84437VX chipset does not tolerate having its memory refresh enabled prior to changing memory mode types.. memory modules.AMD-640TM Chipset BIOS Design 21338A/0—March 1997 Additional Considerations Software Timing Dependencies Relative to Memory Controller Setup The AMD-K6 MMX processor differs from other processors with regards to instruction latencies and the order or priority of processor bus cycles. Note: As a general rule.e. 24 . the AMD-K6 processor write allocate feature should not be enabled during memory sizing and typing algorithms. In addition. and timers).e. oscillators. For example. Refresh should only be enabled after the memory type has been determined. EDO to SDRAM) on the same clock as a DRAM refresh cycle.