1st sem 2009-10
Course Credit: 3 units (2 hours lecture + 3 hours laboratory) Course Description: Combinational and sequential circuits. Structured design. Digital design using programmable devices. HDL-based digital design. Simulation. Testing of digital circuits. Prerequisites: CoE 23 and EEE 41 Co-requisites: EEE 105
Lecture 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Lec00: Introduction Lec01: HDL Overview Lec02: Simulation Lec 03: VHDL Part 1 Lec04: VHDL Part 2 Lec05: Verilog Lec06: Structured design Lec07: Programmable Devices Lec08: Issues in Digital Design Review for Exam 1 Lec 09: Review of Synchronous Sequential Circuits Lec10: Review of Synchronous Sequential Circuits Lec11: Review of Asynchronous Sequential Circuits Lec12: Review of Asynchronous Sequential Circuits Lec13: State identification Homing Sequences Lec14: Distinguishing trees Synchronizing trees Lec15: Adaptive Distinguishing trees Review for Exam 2 Lec16: Testing and Reliability Lec17: Fault Models and Simulation Lec18: Fault Analysis Lec19: Design for Test Lec20: Built-in Self Test Lec21: Complete Picture Review for Exam 3 Topic

Policy and Grade Distribution: • • Your final grade will compose of 50% lab grade and 50% lec grade. You must pass both lab and lec to pass the subject. The grading scale to be used will be the standard UP grading scale with a passing grade of 60%. Your lecture grade will be computed using the following grade distribution: 10 % Attendance and Quizzes 15 % Problem Sets and Homeworks 75 % Long Exam 1
DEEE Building, Velasquez Street, University of the Philippines Diliman Campus, 1101 Quezon City, Philippines Tel: 9818500 local 3301 TeleFAX: 925-2957 URL: http://www.up.edu.ph/~eee

1998. Weyerer and G. Digital Design • Hill and Peterson. Prentice Hall. Complaints regarding the grading of an exam must be made at most a week after the exam papers are returned. • S. Corrections after such time will no longer be entertained. 2 DEEE Building.• • • Students arriving late during exams will not be given extra time for the exam. Students arriving 30 minutes after the start of an exam will no longer be allowed to take the exam. Addison-Wesley Publishing Company. Application-Specific Integrated Circuits. 1992. 1991. • Smith. The Verilog Hardware Description Language. Weste and K. • D. Principles of CMOS VLSI Design: A Systems Perspective. 1992. Eshraghian. • R. Agrawal. Testability of Electronic Circuits. VHDL Starter's Guide. Navabi. Memory. VHDL Switching Theory and Logical Design. Philippines Tel: 9818500 local 3301 TeleFAX: 925-2957 URL: http://www. Thomas and P. Carl Hanser Verlag. Yalamanchili. 1998. • N. VHDL Analysis and Modeling of Digital Systems. Goldemund. Digital Systems: Principles and Applications.5”x11” answer sheets a week before each exam. 2nd ed. Kluwer Academic Publishers. Velasquez Street. • M. and Mixedsignal VLSI Circuits. References: VHDL and Verilog • Z.J. 1991. Essentials Of Electronic Testing For Digital. Testing • M. Foundation Series Quick Start Guide. • Xilinx. Students are required to submit 8. Tocci. 1101 Quezon City. Moorby. Bushnell and V. Prentice Hall. University of the Philippines Diliman Campus. USA.up.ph/~eee . 1998.edu.