MSP430F261x MSP430F241x

www.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011

MIXED SIGNAL MICROCONTROLLER
1

FEATURES
Low Supply Voltage Range 1.8 V to 3.6 V Ultra-Low Power Consumption – Active Mode: 365 µA at 1 MHz, 2.2 V – Standby Mode (VLO): 0.5 µA – Off Mode (RAM Retention): 0.1 µA Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Three-Channel Internal DMA 12-Bit Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan Feature Dual 12-Bit Digital-to-Analog (D/A) Converters With Synchronization 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers On-Chip Comparator Four Universal Serial Communication Interfaces (USCIs) – USCI_A0 and USCI_A1 – Enhanced UART Supporting Auto-Baudrate Detection – IrDA Encoder and Decoder – Synchronous SPI – USCI_B0 and USCI_B1 – I2C™ – Synchronous SPI Supply Voltage Supervisor/Monitor With Programmable Level Detection Brownout Detector Bootstrap Loader • Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse Family Members: – MSP430F2416 – 92KB + 256B Flash Memory – 4KB RAM – MSP430F2417 – 92KB + 256B Flash Memory – 8KB RAM – MSP430F2418 – 116KB + 256B Flash Memory – 8KB RAM – MSP430F2419 – 120KB + 256B Flash Memory – 4KB RAM – MSP430F2616 – 92KB + 256B Flash Memory – 4KB RAM – MSP430F2617 – 92KB + 256B Flash Memory – 8KB RAM – MSP430F2618 – 116KB + 256B Flash Memory – 8KB RAM – MSP430F2619 – 120KB + 256B Flash Memory – 4KB RAM Available in 80-Pin Quad Flat Pack (LQFP), 64-Pin LQFP, and 113-Pin Ball Grid Array (BGA) (See Table 1) For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2007–2011, Texas Instruments Incorporated

MSP430F261x MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs. The MSP430F261x and MSP430F241x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, a comparator, dual 12-bit D/A converters, four universal serial communication interface (USCI) modules, DMA, and up to 64 I/O pins. The MSP430F241x devices are identical to the MSP430F261x devices, with the exception that the DAC12 and the DMA modules are not implemented. Typical applications include sensor systems, industrial control applications, hand-held meters, etc. The 12x12-mm LQFP-64 package is also available as a non-magnetic package for medical imaging applications. Table 1. Available Options (1)
TA PACKAGED DEVICES (2) PLASTIC 113-PIN BGA (ZQW) MSP430F2416TZQW MSP430F2417TZQW MSP430F2418TZQW MSP430F2419TZQW MSP430F2616TZQW MSP430F2617TZQW MSP430F2618TZQW MSP430F2619TZQW PLASTIC 80-PIN LQFP (PN) MSP430F2416TPN MSP430F2417TPN MSP430F2418TPN MSP430F2419TPN MSP430F2616TPN MSP430F2617TPN MSP430F2618TPN MSP430F2619TPN PLASTIC 64-PIN LQFP (PM) MSP430F2416TPM MSP430F2417TPM MSP430F2418TPM MSP430F2419TPM MSP430F2616TPM MSP430F2617TPM MSP430F2618TPM MSP430F2619TPM MSP430F2618TPMR-NM

-40°C to 105°C

(1) (2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Development Tool Support
All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy-to-use development tools. Recommended hardware options include: • Debugging and Programming Interface – MSP-FET430UIF (USB) – MSP-FET430PIF (Parallel Port) • Debugging and Programming Interface with Target Board – MSP-FET430U64 (PM Package) – MSP-FET430U80 (PN Package) • Standalone Target Board – MSP-TS430PM64 • Production Programmer – MSP-GANG430

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Copyright © 2007–2011, Texas Instruments Incorporated

MSP430F261x MSP430F241x
www.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011

Device Pinout, MSP430F241x, 80-Pin PN Package
AV CC DVSS1 AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P8.7/XT2IN P8.6/XT2OUT
DVCC1 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN VREF+ XIN XOUT Ve REF+ VREF-/VeREFP1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 DVSS2 DVCC2 P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK P5.4/MCLK P5.3/UCB1CLK/UCA1STE P5.2/UCB1SOMI/UCB1SCL P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P4.7/TBCLK P4.6/TB6 P4.5/TB5

80-PIN PN PACKAGE (TOP VIEW)

P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCA1TXD/UCA1SIMO P3.7/UCA1RXD/UCA1SOMI P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4

P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 P7.7

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MSP430F261x MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti.com

Device Pinout, MSP430F241x, 64-Pin PM Package
AV CC DVSS1 AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DVCC1 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN VREF+ XIN XOUT Ve REF+ VREF-/VeREFP1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P5.4/MCLK P5.3/UCB1CLK/UCA1STE P5.2/UCB1SOMI/UCB1SCL P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/UCA1RXD/UCA1SOMI P3.6/UCA1TXD/UCA1SIMO P3.5/UCA0RXD/UCA0SOMI 64-PIN PM PACKAGE (TOP VIEW)

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P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO
Copyright © 2007–2011, Texas Instruments Incorporated

MSP430F261x MSP430F241x
www.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011

Device Pinout, MSP430F261x, 80-Pin PN Package
AV CC DVSS1 AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P8.7/XT2IN P8.6/XT2OUT
DVCC1 P6.3/A3 P6.4/A4 P6.5/A5/DAC1 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT Ve REF+/DAC0 VREF-/VeREFP1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK/CA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80-PIN PN PACKAGE (TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 P7.7
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 DVSS2 DVCC2 P5.7/TBOUTH/SVSOUT P5.6/ACLK P5.5/SMCLK P5.4/MCLK P5.3/UCB1CLK/UCA1STE P5.2/UCB1SOMI/UCB1SCL P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P4.7/TBCLK P4.6/TB6 P4.5/TB5

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/ROSC/CA5 P2.6/ADC12CLK/DMAE0/CA6 P2.7/TA0/CA7 P3.0/UCB0STE/UCA0CLK P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P3.4/UCA0TXD/UCA0SIMO P3.5/UCA0RXD/UCA0SOMI P3.6/UCA1TXD/UCA1SIMO P3.7/UCA1RXD/UCA1SOMI P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4

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MSP430F261x MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti.com

Device Pinout, MSP430F261x, 64-Pin PM Package
P5.7/TBOUTH/SVSOUT

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DV CC1 P6.3/A3 P6.4/A4 P6.5/A5/DAC1 P6.6/A6/DAC0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT Ve REF+/DAC0 VREF-/Ve REFP1.0/TACLK/CAOUT P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 P5.4/MCLK P5.3/UCB1CLK/UCA1STE P5.2/UCB1SOMI/UCB1SCL P5.1/UCB1SIMO/UCB1SDA P5.0/UCB1STE/UCA1CLK P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/UCA1RXD/UCA1SOMI P3.6/UCA1TXD/UCA1SIMO P3.5/UCA0RXD/UCA0SOMI

64-PIN PM PACKAGE (TOP VIEW)

XT2OUT

XT2IN

P5.6/ACLK P3.3/UCB0CLK/UCA0STE

P5.5/SMCLK
41 40 39 38 37 36 35 34 33

TDI/TCLK

RST/NMI

AV CC

DVSS1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P3.1/UCB0SIMO/UCB0SDA P2.6/ADC12CLK/DMAE0/CA6 P3.4/UCA0TXD/UCA0SIMO
Copyright © 2007–2011, Texas Instruments Incorporated

TDO/TDI P2.7/TA0/CA7

P6.2/A2

P6.1/A1

P6.0/A0

AV SS

TMS

TCK

P3.0/UCB0STE/UCA0CLK

P2.0/ACLK/CA2

P2.1/TAINCLK/CA3

P2.5/ROSC/CA5

P2.3/CA0/TA1

P2.4/CA1/TA2

P1.5/TA0

P1.6/TA1

P1.7/TA2

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P3.2/UCB0SOMI/UCB0SCL

P2.2/CAOUT/TA0/CA4

113-Pin ZQW Package NOTE For terminal assignments.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Device Pinout. see Table 2.ti. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C11 C12 D1 D2 D4 D5 D6 D7 D8 D9 D11 D12 E1 E2 E4 E5 E6 E7 E8 E9 E11 E12 F1 F2 F4 F5 F8 F9 F11 F12 G1 G2 G4 G5 G8 G9 G11 G12 H1 H2 H4 H5 H6 H7 H8 H9 H11 H12 J1 J2 J4 J5 J6 J7 J8 J9 J11 J12 K1 K2 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Copyright © 2007–2011. Texas Instruments Incorporated Submit Documentation Feedback 7 .MSP430F261x MSP430F241x www.

SPI USCI B1 SPI.x/P6.ti. MACS Timer_B7 Watchdog WDT+ 15-Bit Timer_A3 3 CC Registers 7 CC Registers.x P3.x 2x8/ 1x16 ACLK Oscillators Basic Clock SMCLK System+ MCLK Flash 120KB 116KB 92KB 92KB RAM 4KB 8KB 8KB 4KB ADC12 12-Bit 8 Channels Ports P1/P2 2x8 I/O Interrupt capability Ports P3/P4 P5/P6 4x8 I/O Ports P7/P8 2x8/1x16 I/O USCI A0 UART/ LIN.com Functional Block Diagram.x/P8. Shadow Reg Comp_A+ 8 Channels USCI A1 UART/ LIN. I2C 16MHz CPU 1MB incl. 16 Registers MAB MDB Emulation JTAG Interface Brownout Protection SVS. I2C RST/NMI Functional Block Diagram. 16 Registers MAB MDB Emulation JTAG Interface Brownout Protection SVS. IrDA. MPYS. IrDA. SVM Hardware Multiplier MPY. MPYS. MACS Timer_B7 Watchdog WDT+ 15-Bit Timer_A3 3 CC Registers 7 CC Registers.x 2x8 4x8 P7. MAC. MSP430F241x. 80-Pin PN Package XIN/ XT2IN XOUT/ XT2OUT 2 2 DVCC1/2 DVSS1/2 AVCC AVSS P1.x/P6.x/P2.x/P4. SVM Hardware Multiplier MPY. Texas Instruments Incorporated .x P5.x P3. IrDA. I2C 16MHz CPU 1MB incl. MAC.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. 64-Pin PM Package XIN/ XOUT/ XT2IN XT2OUT 2 2 ACLK Oscillators Basic Clock SMCLK System+ MCLK DVCC DVSS AVCC AVSS P1. SPI USCI B0 SPI. MSP430F241x.x/P2. SPI USCI B1 SPI.x P5.x/P4. Shadow Reg Comp_A+ 8 Channels USCI A1 UART/ LIN. SPI USCI B0 SPI. IrDA.x 2x8 4x8 Flash 120KB 116KB 92KB 92KB RAM 4KB 8KB 8KB 4KB ADC12 12-Bit 8 Channels Ports P1/P2 2x8 I/O Interrupt capability Ports P3/P4 P5/P6 4x8 I/O USCI A0 UART/ LIN. I2C RST/NMI 8 Submit Documentation Feedback Copyright © 2007–2011.

I2C 16MHz CPU 1MB incl. IrDA.x P3.x 2x8/ 1x16 ACLK Oscillators Basic Clock SMCLK System+ MCLK Flash 120kB 116kB 92kB 92kB 56kB RAM 4kB 8kB 8kB 4kB 4kB ADC12 12-Bit 8 Channels DAC12 12-Bit 2 Channels Voltage Out Ports P1/P2 2x8 I/O Interrupt capability Ports P3/P4 P5/P6 4x8 I/O Ports P7/P8 2x8/1x16 I/O USCI A0 UART/ LIN. MPYS.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Functional Block Diagram. SVM Hardware Multiplier MPY. MSP430F261x. SPI USCI B1 SPI.x 2x8 4x8 P7. IrDA. I2C RST/NMI Functional Block Diagram. 16 Registers MAB MDB Emulation JTAG Interface Brownout Protection SVS. 16 Registers MAB MDB Emulation JTAG Interface Brownout Protection SVS.MSP430F261x MSP430F241x www. I2C 16MHz CPU 1MB incl. MSP430F261x. Shadow Reg Comp_A+ 8 Channels USCI A1 UART/ LIN. IrDA.x/P6.x 2x8 4x8 ACLK Oscillators Basic Clock SMCLK System+ MCLK Flash 120kB 116kB 92kB 92kB 56kB RAM 4kB 8kB 8kB 4kB 4kB ADC12 12-Bit 8 Channels DAC12 12-Bit 2 Channels Voltage Out Ports P1/P2 2x8 I/O Interrupt capability Ports P3/P4 P5/P6 4x8 I/O USCI A0 UART/ LIN. SVM Hardware Multiplier MPY.x/P6.ti. SPI USCI B1 SPI. Shadow Reg Comp_A+ 8 Channels USCI A1 UART/ LIN.x P5. 64-Pin PM Package XIN/ XT2IN XOUT/ XT2OUT 2 2 DVCC DVSS AVCC AVSS P1. Texas Instruments Incorporated Submit Documentation Feedback 9 . MAC. MACS DMA Controller 3 Channels Timer_B7 Watchdog WDT+ 15-Bit Timer_A3 3 CC Registers 7 CC Registers. SPI USCI B0 SPI. SPI USCI B0 SPI.x/P8.x/P4.x/P2.x/P4. 80-Pin PN Package XIN/ XT2IN XOUT/ XT2OUT 2 2 DVCC1/2 DVSS1/2 AVCC AVSS P1. I2C RST/NMI Copyright © 2007–2011. MAC. MPYS.x P3. MACS DMA Controller 3 Channels Timer_B7 Watchdog WDT+ 15-Bit Timer_A3 3 CC Registers 7 CC Registers.x/P2. IrDA.x P5.

Analog supply voltage. compare: Out0 output/Comparator_A input General-purpose digital I/O pin/USCI_B0 slave transmit enable/USCI_A0 clock input/output General-purpose digital I/O pin/USCI_B0 slave in/master out in SPI mode. B3 A1 A3 F12 E12 G2 H1 H2 J1 J2 K1 K2 L1 M1 M2 M3 L3 L4 M4 J4 L5 M5 L6 M6 L7 M7 L8 M8 L9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Analog supply voltage. positive terminal. Supplies only the analog portion of ADC12 and DAC12. compare: Out2 output General-purpose digital I/O pin/SMCLK signal output General-purpose digital I/O pin/Timer_A.6/TA1 P1.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. USCI_A0 slave transmit enable General-purpose digital I/O pin/USCI_A transmit data output in UART mode. capture: CCI2A input. Supplies only the analog portion of ADC12 and DAC12. SCL I2C clock in I2C mode General-purpose digital I/O/USCI_B0 clock input/output. Digital supply voltage. negative terminal. Supplies all digital parts. compare: Out2 output/Comparator_A input General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency/Comparator_A input General-purpose digital I/O pin/conversion clock . slave data in/master out in SPI mode General-purpose digital I/O pin/USCI_A1 receive data input in UART mode.5/ROSC/CA5 P2.2/CAOUT/TA0/CA4 P2. General-purpose digital I/O pin/Timer_A.1/TA0 P1. compare: Out0 output General-purpose digital I/O pin/Timer_A.1/UCB0SIMO/ UCB0SDA P3.4/SMCLK P1.3/UCB0CLK/ UCA0STE P3.7/UCA1RXD/ UCA1SOMI (1) 10 MSP430F261x devices only Submit Documentation Feedback Copyright © 2007–2011. compare: Out1 output General-purpose digital I/O pin/Timer_A.12-bit ADC/DMA channel 0 external trigger/Comparator_A input General-purpose digital I/O pin/Timer_A.com Table 2.0/UCB0STE/ UCA0CLK P3. capture: CCI0A input.5/TA0 P1.6/UCA1TXD/ UCA1SIMO P3. capture: CCI0B input/Comparator_A output/BSL receive/Comparator_A input General-purpose digital I/O pin/Timer_A. positive terminal. capture: CCI1A input. Supplies all digital parts.6/ADC12CLK/ DMAE0 (1)/CA6 P2.3/CA0/TA1 P2. clock signal TACLK input/Comparator_A output General-purpose digital I/O pin/Timer_A. SDA I2C data in I2C mode General-purpose digital I/O pin/USCI_B0 slave out/master in in SPI mode. Terminal Functions TERMINAL NO. compare: Out1 output General-purpose digital I/O pin/Timer_A.7/TA0/CA7 P3. Supplies all digital parts. negative terminal. Supplies all digital parts. Digital supply voltage. clock signal at INCLK General-purpose digital I/O pin/Timer_A.2/TA1 P1.0/ACLK/CA2 P2.ti. compare: Out0 output/BSL transmit General-purpose digital I/O pin/Timer_A.4/UCA0TXD/ UCA0SIMO P3.0/TACLK/ CAOUT P1. Digital supply voltage. slave data in/master out in SPI mode General-purpose digital I/O pin/USCI_A0 receive data input in UART mode. compare: Out1 output/Comparator_A input General-purpose digital I/O pin/Timer_A.7/TA2 P2. Texas Instruments Incorporated .4/CA1/TA2 P2. slave data out/master in in SPI mode General-purpose digital I/O pin/USCI_A1 transmit data output in UART mode. negative terminal.5/UCA0RXD/ UCA0SOMI P3. positive terminal.2/UCB0SOMI/ UCB0SCL P3. Digital supply voltage. compare: Out2 output General-purpose digital I/O pin/ACLK output/Comparator_A input General-purpose digital I/O pin/Timer_A. NAME 64 PIN 64 62 1 63 80 PIN 80 78 1 79 52 53 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 113 PIN A2 B2.1/TAINCLK/CA3 P2.3/TA2 P1. slave data out/master in in SPI mode I/O DESCRIPTION AVCC AVSS DVCC1 DVSS1 DVCC2 DVSS2 P1.

ti.12-bit ADC/DAC12. capture: CCI0A/B input. compare: Out5 output General-purpose digital I/O pin/Timer_B.4/MCLK P5. capture: CCI5A/B input.4 P7.0/UCB1STE/ UCA1CLK P5.3/UCB1CLK/ UCA1STE P5. compare: Out1 output General-purpose digital I/O pin/Timer_B.1/TB1 P4.3 P7.7/TBOUTH/SVSOUT P6.12-bit ADC General-purpose digital I/O pin/analog input A5 .2/A2 P6.0 P7. clock signal TBCLK input General-purpose digital I/O pin/USCI_B1 slave transmit enable/USCI_A1 clock input/output General-purpose digital I/O pin/USCI_B1 slave in/master out in SPI mode.0 output General-purpose digital I/O pin/analog input A7 .1 (2) MSP430F261x devices only Submit Documentation Feedback 11 Copyright © 2007–2011.12-bit ADC General-purpose digital I/O pin/analog input A2 . NAME 64 PIN 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 59 60 61 2 3 4 5 6 80 PIN 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 75 76 77 2 3 4 5 6 54 55 56 57 58 59 60 61 62 63 113 PIN M9 J9 M10 L10 M11 M12 L12 K11 K12 J11 J12 H11 H12 G11 G12 F11 D4 A4 B4 B1 C1 C2 C3 D1 D2 E11 D12 D11 C12 C11 B12 A12 A11 B10 A10 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General-purpose digital I/O pin/Timer_B.12-bit ADC General-purpose digital I/O pin/analog input A4 .MSP430F261x MSP430F241x www.1 P7.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Table 2.5/TB5 P4. capture: CCI3A/B input.2/TB2 P4.0 P8.6/A6/DAC0 (2) P6.1/UCB1SIMO/ UCB1SDA P5. compare: Out3 output General-purpose digital I/O pin/Timer_B.5/A5/DAC1 (2) P6.12-bit ADC General-purpose digital I/O pin/analog input A1 .7/TBCLK P5.1/A1 P6.4/TB4 P4.1 output General-purpose digital I/O pin/analog input A6 . capture: CCI4A/B input.5/SMCLK P5.4/A4 P6.6 P7. SDA I2C data in I2C mode General-purpose digital I/O pin/USCI_B1 slave out/master in in SPI mode.7 P8.0/A0 P6. compare: Out2 output General-purpose digital I/O pin/Timer_B. capture: CCI1A/B input. compare: Out4 output General-purpose digital I/O pin/Timer_B. capture: CCI6A input.1 output/SVS input General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin I/O DESCRIPTION P4. USCI_A1 slave transmit enable General-purpose digital I/O pin/main system clock MCLK output General-purpose digital I/O pin/submain system clock SMCLK output General-purpose digital I/O pin/auxiliary clock ACLK output General-purpose digital I/O pin/switch all PWM digital output ports to high impedance .12-bit ADC/DAC12.0/TB0 P4. Texas Instruments Incorporated .12-bit ADC/DAC12.3/A3 P6.3/TB3 P4. SCL I2C clock in I2C mode General-purpose digital I/O/USCI_B1 clock input/output. compare: Out6 output General-purpose digital I/O pin/Timer_B.6/TB6 P4.5 P7.2 P7.12-bit ADC General-purpose digital I/O pin/analog input A3 . Terminal Functions (continued) TERMINAL NO.Timer_B TB0 to TB6/SVS comparator output General-purpose digital I/O pin/analog input A0 . compare: Out0 output General-purpose digital I/O pin/Timer_B. capture: CCI2A/B input.6/ACLK P5.2/UCB1SOMI/ UCB1SCL P5.7/A7/DAC1 (2)/SVSIN P7.

G4. J5. J6. E4. H8. G5. E9. H4. or bootstrap loader start (in flash devices). AVSS recommended. L11.7/XT2IN XT2OUT XT2IN RST/NMI TCK TDI/TCLK TDO/TDI TMS VeREF+/DAC0 (3) VREF+ VREF-/VeREFXIN XOUT Reserved (3) (4) 52 53 58 57 55 54 56 10 7 11 8 9 74 73 71 70 72 10 7 11 8 9 B5 A5 A6 B7 B6 F2 E2 G1 E1 F1 (4) I/O 113 PIN D9 A9 B9 B8 A8 A7 I/O I/O I/O I/O O I O I I I I I/O I I O I I O NA General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin General-purpose digital I/O pin DESCRIPTION 64 PIN 80 PIN 64 65 66 67 68 69 General-purpose digital I/O pin/Output terminal of crystal oscillator XT2 General-purpose digital I/O pin/Input port for crystal oscillator XT2. G9. The device protection fuse is connected to TDI/TCLK.4 P8. F9. H6.0 output Output of positive terminal of the reference voltage in the ADC12 Negative terminal for the reference voltage for both sources. J8. F5. Texas Instruments Incorporated . TDO/TDI data output or programming data input terminal. Test mode select. D7. H5. J7. NAME P8. D8. Output port for crystal oscillator XT1. Output terminal of crystal oscillator XT2 Input port for crystal oscillator XT2 Reset input. E5. F4. Test data output port. Input for an external reference voltage/DAC12. or an external applied reference voltage Input port for crystal oscillator XT1. E7. TCK is the clock input port for device programming test and bootstrap loader start. H9. nonmaskable interrupt input port.2 P8. TMS is used as an input port for device programming and test. E8. G8.com Table 2. F8. MSP430F261x devices only Reserved pins are L2. the internal reference voltage.ti.3 P8. Connection to DVSS.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. D6. H7. Test clock (JTAG). Reserved pins. D5. Standard or watch crystals can be connected. 12 Submit Documentation Feedback Copyright © 2007–2011. Terminal Functions (continued) TERMINAL NO. Test data input or test clock input.6/XT2OUT P8. Standard or watch crystals can be connected.5 P8. E6. B11. Only standard crystals can be connected.

R11 MOV 2(R5).Tab(R6) MOV @R10+. and control buses. Table 3 shows examples of the three types of instruction formats. destination only Relative jump.MSP430F261x MSP430F241x www.TONI EXAMPLE MOV R10.Y(Rm) MOV EDE.Rm MOV #X. Instruction Word Formats INSTRUCTION FORMAT Dual operands. Four of the registers. Texas Instruments Incorporated Submit Documentation Feedback 13 .com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations. source-destination Single operands.ti. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Instruction Set The instruction set consists of 51 instructions with three formats and seven address modes. R8-> PC Jump-on-equal bit = 0 Table 4. are dedicated as program counter. and can be handled with all instructions.TONI M(R10) -> M(Tab+R6) M(R10) -> R11 R10 + 2-> R10 #45 -> M(TONI) S = source. status register. and constant generator respectively.Y(Rm) MOV @Rn+. The register-to-register operation execution time is one cycle of the CPU clock.Rd MOV X(Rn). Table 4 shows the address modes. are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.&TCDAT MOV @Rn. D = destination Copyright © 2007–2011. R0 to R3.R5 CALL R8 JNE OPERATION R4 + R5 -> R5 PC ->(TOS). Address Mode Descriptions ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate (1) S (1) D (1) SYNTAX MOV Rs. other than program-flow instructions. Peripherals are connected to the CPU using data. un/conditional EXAMPLE ADD R4.6(R6) OPERATION R10 -> R11 M(2+R5)-> M(6+R6) M(EDE) -> M(TONI) M(MEM) -> M(TCDAT) ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ MOV @R10.R11 MOV #45. The CPU is integrated with 16 registers that provide reduced instruction execution time. stack pointer. Table 3. The remaining registers are general-purpose registers.TONI MOV &MEM. address. Each instruction can operate on word and byte data.

service the request.com Operating Modes The MSP430 has one active mode and five software-selectable low-power modes of operation. The following six operating modes can be configured by software: • Active mode (AM) – All clocks are active • Low-power mode 0 (LPM0) – CPU is disabled – ACLK and SMCLK remain active – MCLK is disabled • Low-power mode 1 (LPM1) – CPU is disabled – ACLK and SMCLK remain active.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti. MCLK is disabled – DCO's dc-generator is disabled if DCO not used in active mode • Low-power mode 2 (LPM2) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc-generator remains enabled – ACLK remains active • Low-power mode 3 (LPM3) – CPU is disabled – MCLK and SMCLK are disabled – DCO's dc-generator is disabled – ACLK remains active • Low-power mode 4 (LPM4) – CPU is disabled – ACLK is disabled – MCLK and SMCLK are disabled – DCO's dc-generator is disabled – Crystal oscillator is stopped 14 Submit Documentation Feedback Copyright © 2007–2011. An interrupt event can wake the device from any of the five low-power modes. and restore back to the low-power mode on return from the interrupt program. Texas Instruments Incorporated .

DAC12_1IFG (2) (4) (8) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges. highest (Non)maskable. In I2C mode: UCALIFG. Interrupt Sources INTERRUPT SOURCE Power-up External reset Watchdog Timer+ Flash key violation PC out-of-range (1) NMI Oscillator fault Flash memory access violation Timer_B7 Timer_B7 Comparator_A+ Watchdog Timer+ Timer_A3 Timer_A3 USCI_A0/USCI_B0 receive USCI_B0 I2C status USCI_A0/USCI_B0 transmit USCI_B0 I2C receive/transmit ADC12 I/O port P2 (eight flags) I/O port P1 (eight flags) USCI_A0/USCI_B1 receive USCI_B1 I2C status USCI_A1/USCI_B1 transmit USCI_B1 I2C receive/transmit DMA DAC12 See (1) (2) (3) (4) (5) (6) (7) (7) (8) INTERRUPT FLAG PORIFG RSTIFG WDTIFG KEYV See (2) NMIIFG OFIFG ACCVIFG (2) (3) TBCCR0 CCIFG (4) TBCCR1 to TBCCR6 CCIFGs. A 0AA55h at this location disables the BSL completely.7 (2) (4) P1IFG. In UART/SPI mode: UCB0TXIFG.0 to P2IFG. TBIFG (2) (4) CAIFG WDTIFG TACCR0 CCIFG (4) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 31.7 (2) (4) (2) (5) UCA1RXIFG. A zero disables the erasure of the flash if an invalid password is supplied. DMA2IFG (2) (4) DAC12_0IFG. Copyright © 2007–2011. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example. UCB1TXIFG (2) (6) DMA0IFG. UCB0TXIFG. ICSTTIFG. UCSTPIFG. Texas Instruments Incorporated Submit Documentation Feedback 15 . (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable 0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0FFDEh 0FFDCh 0FFDAh to 0FFC0h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 15 to 0. The address 0FFBEh is used as bootstrap loader security key (BSLSKEY). UCNACKIFG. In I2C mode: UCB0RXIFG. (Non)maskable. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if necessary.0 to P1IFG. but the general interrupt enable cannot. DMA1IFG. UCB0RXIFG (2) (5) UCA0TXIFG.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. UCB0TXIFG (2) (6) ADC12IFG (2) (4) P2IFG. Interrupt flags are located in the module. In SPI mode: UCB0RXIFG. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. Table 5. Multiple source flags (Non)maskable: the individual interrupt-enable bit can disable an interrupt event. UCB1RXIFG UCA1TXIFG. lowest TACCR1 CCIFG TACCR2 CCIFG (2) (4) UCA0RXIFG.MSP430F261x MSP430F241x www. flash is not programmed) the CPU enters LPM4 immediately after power-up.

Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 4 3 UCB0TXIE rw-0 2 UCB0RXIE rw-0 1 UCA0TXIE rw-0 0 UCA0RXIE rw-0 UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE USCI_A0 receive interrupt enable USCI_A0 transmit interrupt enable USCI_B0 receive interrupt enable USCI_B0 transmit interrupt enable Table 7.com Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Simple software access is provided with this arrangement. SFR bit is not present in device.ti. Special function register bits not allocated to a functional purpose are not physically present in the device. Set on VCC power-up. Set via RST/NMI pin 7 6 5 4 3 UCB0TXIFG rw-1 2 UCB0RXIFG rw-0 1 UCA0TXIFG rw-1 0 UCA0RXIFG rw-0 UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG USCI_A0 receive interrupt flag USCI_A0 transmit interrupt flag USCI_B0 receive interrupt flag USCI_B0 transmit interrupt flag 16 Submit Documentation Feedback Copyright © 2007–2011. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. Set on a reset condition at RST/NMI pin in reset mode. External reset interrupt flag. Inactive if watchdog mode is selected.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. Bit can be read and written. It is reset or set by PUC. Interrupt Flag Register 1 and 2 Address 02h 7 6 5 4 NMIIFG rw-0 WDTIFG OFIFG PORIFG RSTIFG NMIIFG Address 03h 3 RSTIFG rw-(0) 2 PORIFG rw-(1) 1 OFIFG rw-1 0 WDTIFG rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation. Table 6. Active if Watchdog Timer is configured in interval timer mode. Legend rw: rw-0. Bit can be read and written. Flag set on oscillator fault. Reset on VCC power-up. It is reset or set by POR.1): Bit can be read and written. Power-On Reset interrupt flag. Interrupt Enable Register 1 and 2 Address 00h 7 6 5 ACCVIE rw-0 WDTIE OFIE NMIIE ACCVIE Address 01h 4 NMIIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0 Watchdog Timer interrupt enable.1: rw-(0. Texas Instruments Incorporated .

or as a group with segments 0 to n.1 22 .P2. PN PACKAGE PINS 13 . Table 9.P1. After reset segment A is protected against programming and erasing.1 M3 . Memory Organization MSP430F2416 MSP430F2616 Memory Main: interrupt vector Main: code memory RAM (total) Extended Mirrored Information memory Boot memory RAM (mirrored at 0x18FF to 0x01100) Peripherals Size Flash Flash Size Size Size Size Flash Size ROM Size 16-bit 8-bit 8-bit SFR 92KB 0x0FFFF-0x0FFC0 0x18FFF-0x02100 4KB 0x020FF-0x01100 2KB 0x020FF-0x01900 2KB 0x018FF-0x01100 256 Byte 0x010FF-0x01000 1KB 0x00FFF-0x00C00 2KB 0x009FF-0x00200 0x001FF-0x00100 0x000FF-0x00010 0x0000F-0x00000 MSP430F2417 MSP430F2617 92KB 0x0FFFF-0x0FFC0 0x19FFF-0x03100 8KB 0x030FF-0x01100 6KB 0x030FF-0x01900 2KB 0x018FF-0x01100 256 Byte 0x010FF-0x01000 1KB 0x00FFF-0x00C00 2KB 0x009FF-0x00200 0x001FF-0x00100 0x000FF-0x00010 0x0000F-0x00000 MSP430F2418 MSP430F2618 116KB 0x0FFFF-0x0FFC0 0x1FFFF-0x03100 8KB 0x030FF-0x01100 6KB 0x030FF-0x01900 2KB 0x018FF-0x01100 256 Byte 0x010FF-0x01000 1KB 0x00FFF-0x00C00 2KB 0x009FF-0x00200 0x001FF-0x00100 0x000FF-0x00010 0x0000F-0x00000 MSP430F2419 MSP430F2619 120KB 0x0FFFF-0x0FFC0 0x1FFFF-0x02100 4KB 0x020FF-0x01100 2KB 0x020FF-0x01900 2KB 0x018FF-0x01100 256 Byte 0x010FF-0x01000 1KB 0x00FFF-0x00C00 2KB 0x009FF-0x00200 0x001FF-0x00100 0x000FF-0x00010 0x0000F-0x00000 Bootstrap Loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Each segment in main memory is 512 bytes in size. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each.2 Flash Memory The flash memory can be programmed via the JTAG port.P2. The CPU can perform single-byte and single-word writes to the flash memory. • Flash content integrity check with marginal read modes Copyright © 2007–2011. BSL Pin Functions BSL FUNCTION Data Transmit Data Receive PM. Segments A to D are also called information memory. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. Texas Instruments Incorporated Submit Documentation Feedback 17 . For complete description of the features of the BSL and its implementation.MSP430F261x MSP430F241x www.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Memory Organization Table 8.ti. • Segment A contains calibration data.2 ZQW PACKAGE PINS H1 . or each segment may be individually erased.P1. Access to the MSP430 memory via the BSL is protected by a user-defined password. • Segments 0 to n may be erased in one step. • Segments A to D can be erased individually. the bootstrap loader. see the MSP430 Programming Via the Bootstrap Loader (BSL) User's Guide (SLAU319). or in-system by the CPU.

and a high-frequency crystal oscillator. The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A. Labels Used by the ADC Calibration Structure LABEL CAL_ADC_25T85 CAL_ADC_25T30 CAL_ADC_25VREF_FACTOR CAL_ADC_15T85 CAL_ADC_15T30 CAL_ADC_15VREF_FACTOR CAL_ADC_OFFSET CAL_ADC_GAIN_FACTOR CAL_BC1_1MHZ CAL_DCO_1MHZ CAL_BC1_8MHZ CAL_DCO_8MHZ CAL_BC1_12MHZ CAL_DCO_12MHZ CAL_BC1_16MHZ CAL_DCO_16MHZ 18 CONDITION AT CALIBRATION / DESCRIPTION INCHx = 0x1010. DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. Oscillator and System Clock The clock system in the MSP430F241x and MSP430F261x family of devices is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator.ti. the sub-system clock used by the peripheral modules. REF2_5 = 0. For complete module descriptions. It is organized in a tag-length-value (TLV) structure. sourced either from a 32768-Hz watch crystal or the internal LF oscillator. see the MSP430x2xx Family User's Guide (SLAU144). TA = 30°C REF2_5 = 1.5 V.5 V. The basic clock module provides the following clock signals: • Auxiliary clock (ACLK). TA = 30°C External VREF = 1. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. fADC12CLK = 5 MHz SIZE word word word word word word word word byte byte byte byte byte byte byte byte ADDRESS OFFSET 0x000E 0x000C 0x000A 0x0008 0x0006 0x0004 0x0002 0x0000 0x0007 0x0006 0x0005 0x0004 0x0003 0x0002 0x0001 0x0000 Submit Documentation Feedback Copyright © 2007–2011. and control buses and can be handled using all instructions. an internal very low-power low-frequency oscillator.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. fADC12CLK = 5 MHz External VREF = 1. TA = 30°C REF2_5 = 0. TA = 30°C INCHx = 0x1010. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. the system clock used by the CPU. • Main clock (MCLK). REF2_5 = 1. an internal digitally controlled oscillator (DCO).com Peripherals Peripherals are connected to the CPU through data. REF2_5 = 1. Using the DMA controller can increase the throughput of peripheral modules. TA = 85°C INCHx = 0x1010. the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Calibration Data Stored in Information Memory Segment A Calibration data is stored for the DCO and for the ADC12. Texas Instruments Incorporated . For example. Table 10. address. Tags Used by the TLV Structure NAME TAG_DCO_30 TAG_ADC12_1 TAG_EMPTY ADDRESS 0x10F6 0x10DA VALUE 0x01 0x08 0xFE ADC12_1 calibration tag Identifier for empty memory areas DESCRIPTION DCO frequency calibration at VCC = 3 V and TA = 25°C at calibration Table 11. TA = 85°C INCHx = 0x1010. REF2_5 = 0. • Sub-Main clock (SMCLK). The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.

If the selected time interval expires. • Each I/O has an individually programmable pullup/pulldown resistor. and interrupt condition is possible. enhanced UART with automatic baudrate detection (LIN). Universal Serial Communication Interface (USCI) The USCI modules are used for serial data communication. • Ports P7/P8 can be accessed word-wise. enhanced UART. The CPU begins code execution after the brownout circuit releases the device reset. The USCI module supports synchronous communication protocols such as SPI (3 pin or 4 pin) or I2C. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is not automatically reset). Supply Voltage Supervisor (SVS) The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.ti. • Any combination of input. and asynchronous combination protocols such as UART. No additional clock cycles are required. • Read/write access to port-control registers is supported by all instructions. and IrDA. Digital I/O There are up to eight 8-bit I/O ports implemented—ports P1 through P8: • All individual I/O bits are independently programmable. VCC may not have ramped to VCC(min) at that time. output. • Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2.MSP430F261x MSP430F241x www. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. The USCI_B module provides support for SPI (3 pin or 4 pin) and I2C Copyright © 2007–2011. The module performs 16x16. UART. If desired. the SVS circuit can be used to determine when VCC reaches VCC(min). 8x16.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Brownout. 16x8. and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. However. The user must ensure that the default DCO settings are not changed until VCC reaches VCC(min). Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. Watchdog Timer (WDT+) The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. Texas Instruments Incorporated Submit Documentation Feedback 19 . the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. The USCI_A module provides support for SPI (3 pin or 4 pin). a system reset is generated. If the watchdog function is not needed in an application. and IrDA.

4 J1 .P1.P2.P1.P1.P1.7 24 . Timer_A3 Signal Connections INPUT PIN NUMBER ZQW G2 .P2.P1.3 L1 .2 14 .P2.4 20 Submit Documentation Feedback Copyright © 2007–2011. PWM outputs.3 TA2 ACLK (internal) DVSS DVCC CCI2A CCI2B GND VCC CCR2 TA2 15 .0 DEVICE INPUT SIGNAL TACLK ACLK SMCLK M2 .1 H1 .P1. Timer_A3 can support multiple capture/compares.2 18 .P2.P2. PN ZQW ADC12 (internal) DAC12_0 (internal) DAC12_1 (internal) J1 .2 TAINCLK TA0 TA0 DVSS DVCC H2 .1 M3 .P2.1 13 . Texas Instruments Incorporated .3 H2 .P2. Table 12.7 H1 .5 L5 .P1.2 21 .P2. Timer_A3 also has extensive interrupt capabilities.6 23 .3 15 .5 27 . Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.P2.1 17 .6 L3 . PN 12 .P1.P1.P1.3 CCR0 TA0 13 .P1.0 PM.ti.2 K2 .P1.P1.P1.P1.P2. and interval timing.com Timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers.P1.7 MODULE BLOCK Timer MODULE OUTPUT SIGNAL NA OUTPUT PIN NUMBER PM.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.1 K1 .1 22 .P1.P1.7 L4 .3 19 .P1.2 TA1 CAOUT (internal) DVSS DVCC MODULE INPUT NAME TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCR1 TA1 14 .P1.

1 ADC12 (internal) J9 .7 DEVICE INPUT SIGNAL TBCLK ACLK SMCLK K11 .3 39 .3 CCR2 TB2 38 .P4.P4.P4.P4.0 M9.7 M9 .2 38 .P4.P4.2 38 .P4.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Timer_B7 Timer_B7 is a 16-bit timer/counter with seven capture/compare registers.P4.P4.P4.P4.2 M10 .P4. PN 43 .P4.4 CCR3 TB3 39 .5 M12 .7 PM.4 M11 . PN ZQW Copyright © 2007–2011.P4.P4. and interval timing.0 MODULE BLOCK Timer MODULE OUTPUT SIGNAL NA OUTPUT PIN NUMBER PM.P4.P4.3 L10 .1 37 .6 L12 .P4. Texas Instruments Incorporated Submit Documentation Feedback 21 . Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.P4.4 TB4 TB4 DVSS DVCC M12 .6 TB6 ACLK (internal) DVSS DVCC MODULE INPUT NAME TBCLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCI3A CCI3B GND VCC CCI4A CCI4B GND VCC CCI5A CCI5B GND VCC CCI6A CCI6B GND VCC CCR6 TB6 42 .5 CCR4 TB4 40 .P4.2 CCR1 TB1 37 .2 TB2 TB2 DVSS DVCC L10 .0 43 .P4.0 ADC12 (internal) M9 .5 41 .5 M12 .0 36 . Timer_B7 also has extensive interrupt capabilities.MSP430F261x MSP430F241x www.P4.P4.P4.P4. PWM outputs.3 TB3 TB3 DVSS DVCC M11 .4 40 .P4.P4.P4. Timer_B7 Signal Connections INPUT PIN NUMBER ZQW K11 .P4.P4.P4.P4.P4. Table 13.1 CCR0 TB0 36 .P4.P4.P4.6 CCR5 TB5 41 .4 40 .P4.P4. Timer_B7 can support multiple capture/compares.7 36 .1 TB1 TB1 DVSS DVCC M10 .1 J9 .P4.ti.P4.2 DAC_0 (internal) DAC_1 (internal) M10 .4 M11 . Timer_B3.3 39 .5 TB5 TB5 DVSS DVCC L12 .P4.0 TBCLK TB0 TB0 DVSS DVCC J9 .3 L10 .1 37 .P4.P4.5 41 .6 42 .P4.

The DAC12 may be used in 8-bit or 12-bit mode and may be used in conjunction with the DMA controller. they may be grouped together for synchronous operation. Texas Instruments Incorporated . DAC12 The DAC12 module is a 12-bit R-ladder voltage-output digital-to-analog converter (DAC). 22 Submit Documentation Feedback Copyright © 2007–2011. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. sample select control.com Comparator_A+ The primary function of the Comparator_A+ module is to support precision slope analog-to-digital conversions.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. The module implements a 12-bit SAR core. battery-voltage supervision. and a 16-word conversion-and-control buffer. reference generator. When multiple DAC12 modules are present. and monitoring of external analog signals. ADC12 The ADC12 module supports fast 12-bit analog-to-digital conversions.ti.

MSP430F261x MSP430F241x www. Peripherals File Map MODULE DMA (1) REGISTER DMA channel 2 transfer size DMA channel 2 destination address DMA channel 2 source address DMA channel 2 control DMA channel 1 transfer size DMA channel 1 destination address DMA channel 1 source address DMA channel 1 control DMA channel 0 transfer size DMA channel 0 destination address DMA channel 0 source address DMA channel 0 control DMA module interrupt vector word DMA module control 1 DMA module control 0 SHORT FORM DMA2SZ DMA2DA DMA2SA DMA2CTL DMA1SZ DMA1DA DMA1SA DMA1CTL DMA0SZ DMA0DA DMA0SA DMA0CTL DMAIV DMACTL1 DMACTL0 DAC12_1DAT DAC12_1CTL DAC12_0DAT DAC12_0CTL ADDRESS 0x01F2 0x01EE 0x01EA 0x01E8 0x01E6 0x01E2 0x01DE 0x01DC 0x01DA 0x01D6 0x01D2 0x01D0 0x0126 0x0124 0x0122 0x01CA 0x01C2 0x01C8 0x01C0 DAC12 (1) DAC12_1 data DAC12_1 control DAC12_0 data DAC12_0 control (1) MSP430F261x devices only Submit Documentation Feedback 23 Copyright © 2007–2011.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Peripheral File Map Table 14. Texas Instruments Incorporated .

Texas Instruments Incorporated .com Table 14.ti. Peripherals File Map (continued) MODULE ADC12 Interrupt vector word register Inerrupt enable register Inerrupt flag register Control register 1 Control register 0 Conversion memory 15 Conversion memory 14 Conversion memory 13 Conversion memory 12 Conversion memory 11 Conversion memory 10 Conversion memory 9 Conversion memory 8 Conversion memory 7 Conversion memory 6 Conversion memory 5 Conversion memory 4 Conversion memory 3 Conversion memory 2 Conversion memory 1 Conversion memory 0 ADC memory-control register15 ADC memory-control register14 ADC memory-control register13 ADC memory-control register12 ADC memory-control register11 ADC memory-control register10 ADC memory-control register9 ADC memory-control register8 ADC memory-control register7 ADC memory-control register6 ADC memory-control register5 ADC memory-control register4 ADC memory-control register3 ADC memory-control register2 ADC memory-control register1 ADC memory-control register0 REGISTER SHORT FORM ADC12IV ADC12IE ADC12IFG ADC12CTL1 ADC12CTL0 ADC12MEM15 ADC12MEM14 ADC12MEM13 ADC12MEM12 ADC12MEM11 ADC12MEM10 ADC12MEM9 ADC12MEM8 ADC12MEM7 ADC12MEM6 ADC12MEM5 ADC12MEM4 ADC12MEM3 ADC12MEM2 ADC12MEM1 ADC12MEM0 ADC12MCTL15 ADC12MCTL14 ADC12MCTL13 ADC12MCTL12 ADC12MCTL11 ADC12MCTL10 ADC12MCTL9 ADC12MCTL8 ADC12MCTL7 ADC12MCTL6 ADC12MCTL5 ADC12MCTL4 ADC12MCTL3 ADC12MCTL2 ADC12MCTL1 ADC12MCTL0 ADDRESS 0x01A8 0x01A6 0x01A4 0x01A2 0x01A0 0x015E 0x015C 0x015A 0x0158 0x0156 0x0154 0x0152 0x0150 0x014E 0x014C 0x014A 0x0148 0x0146 0x0144 0x0142 0x0140 0x008F 0x008E 0x008D 0x008C 0x008B 0x008A 0x0089 0x0088 0x0087 0x0086 0x0085 0x0084 0x0083 0x0082 0x0081 0x0080 24 Submit Documentation Feedback Copyright © 2007–2011.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.

Peripherals File Map (continued) MODULE Timer_B7 Capture/compare register 6 Capture/compare register 5 Capture/compare register 4 Capture/compare register 3 Capture/compare register 2 Capture/compare register 1 Capture/compare register 0 Timer_B register Capture/compare control 6 Capture/compare control 5 Capture/compare control 4 Capture/compare control 3 Capture/compare control 2 Capture/compare control 1 Capture/compare control 0 Timer_B control Timer_B interrupt vector Timer_A3 Capture/compare register 2 Capture/compare register 1 Capture/compare register 0 Timer_A register Reserved Reserved Reserved Reserved Capture/compare control 2 Capture/compare control 1 Capture/compare control 0 Timer_A control Timer_A interrupt vector Hardware Multiplier Sum extend Result high word Result low word Second operand Multiply signed +accumulate/operand 1 Multiply+accumulate/operand 1 Multiply signed/operand 1 Multiply unsigned/operand 1 Flash Flash control 4 Flash control 3 Flash control 2 Flash control 1 Watchdog Watchdog Timer control TACCTL2 TACCTL1 TACCTL0 TACTL TAIV SUMEXT RESHI RESLO OP2 MACS MAC MPYS MPY FCTL4 FCTL3 FCTL2 FCTL1 WDTCTL REGISTER SHORT FORM TBCCR6 TBCCR5 TBCCR4 TBCCR3 TBCCR2 TBCCR1 TBCCR0 TBR TBCCTL6 TBCCTL5 TBCCTL4 TBCCTL3 TBCCTL2 TBCCTL1 TBCCTL0 TBCTL TBIV TACCR2 TACCR1 TACCR0 TAR ADDRESS 0x019E 0x019C 0x019A 0x0198 0x0196 0x0194 0x0192 0x0190 0x018E 0x018C 0x018A 0x0188 0x0186 0x0184 0x0182 0x0180 0x011E 0x0176 0x0174 0x0172 0x0170 0x016E 0x016C 0x016A 0x0168 0x0166 0x0164 0x0162 0x0160 0x012E 0x013E 0x013C 0x013A 0x0138 0x0136 0x0134 0x0132 0x0130 0x01BE 0x012C 0x012A 0x0128 0x0120 Copyright © 2007–2011. Texas Instruments Incorporated Submit Documentation Feedback 25 .MSP430F261x MSP430F241x www.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Table 14.

Texas Instruments Incorporated .ti. Peripherals File Map (continued) MODULE USCI_A0/B0 USCI_A0 auto baud rate control USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI_B0 I2C Interrupt enable USCI_B0 baud rate control 1 USCI_B0 baud rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address USCI_A1/B1 USCI_A1 auto baud rate control USCI_A1 transmit buffer USCI_A1 receive buffer USCI_A1 status USCI_A1 modulation control USCI_A1 baud rate control 1 USCI_A1 baud rate control 0 USCI_A1 control 1 USCI_A1 control 0 USCI_A1 IrDA receive control USCI_A1 IrDA transmit control USCI_B1 transmit buffer USCI_B1 receive buffer USCI_B1 status USCI_B1 I2C Interrupt enable USCI_B1 baud rate control 1 USCI_B1 baud rate control 0 USCI_B1 control 1 USCI_B1 control 0 USCI_B1 I2C slave address USCI_B1 I2C own address USCI_A1/B1 interrupt enable USCI_A1/B1 interrupt flag Comparator_A+ Comparator_A port disable Comparator_A control2 Comparator_A control1 REGISTER SHORT FORM UCA0ABCTL UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCLT UCB0TXBUF UCB0RXBUF UCB0STAT UCB0CIE UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA UCA1ABCTL UCA1TXBUF UCA1RXBUF UCA1STAT UCA1MCTL UCA1BR1 UCA1BR0 UCA1CTL1 UCA1CTL0 UCA1IRRCTL UCA1IRTCLT UCB1TXBUF UCB1RXBUF UCB1STAT UCB1CIE UCB1BR1 UCB1BR0 UCB1CTL1 UCB1CTL0 UCB1SA UCB1OA UC1IE UC1IFG CAPD CACTL2 CACTL1 ADDRESS 0x005D 0x0067 0x0066 0x0065 0x0064 0x0063 0x0062 0x0061 0x0060 0x005F 0x005E 0x006F 0x006E 0x006D 0x006C 0x006B 0x006A 0x0069 0x0068 0x011A 0x0118 0x00CD 0x00D7 0x00D6 0x00D5 0x00D4 0x00D3 0x00D2 0x00D1 0x00D0 0x00CF 0x00CE 0x00DF 0x00DE 0x00DD 0x00DC 0x00DB 0x00DA 0x00D9 0x00D8 0x017E 0x017C 0x0006 0x0007 0x005B 0x005A 0x0059 26 Submit Documentation Feedback Copyright © 2007–2011.com Table 14.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.

MSP430F261x MSP430F241x www.ti. SVS Port PA (2) SVS control register (reset by brownout signal) Port PA resistor enable Port PA selection Port PA direction Port PA output Port PA input Port P8 (2) Port P8 resistor enable Port P8 selection Port P8 direction Port P8 output Port P8 input Port P7 (3) Port P7 resistor enable Port P7 selection Port P7 direction Port P7 output Port P7 input Port P6 Port P6 resistor enable Port P6 selection Port P6 direction Port P6 output Port P6 input Port P5 Port P5 resistor enable Port P5 selection Port P5 direction Port P5 output Port P5 input Port P4 Port P4 selection Port P4 resistor enable Port P4 direction Port P4 output Port P4 input Port P3 Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input REGISTER SHORT FORM BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL SVSCTL PAREN PASEL PADIR PAOUT PAIN P8REN P8SEL P8DIR P8OUT P8IN P7REN P7SEL P7DIR P7OUT P7IN P6REN P6SEL P6DIR P6OUT P6IN P5REN P5SEL P5DIR P5OUT P5IN P4SEL P4REN P4DIR P4OUT P4IN P3REN P3SEL P3DIR P3OUT P3IN ADDRESS 0x0053 0x0058 0x0057 0x0056 0x0055 0x0014 0x003E 0x003C 0x003A 0x0038 0x0015 0x003F 0x003D 0x003B 0x0039 0x0014 0x003E 0x003C 0x003A 0x0038 0x0013 0x0037 0x0036 0x0035 0x0034 0x0012 0x0033 0x0032 0x0031 0x0030 0x001F 0x0011 0x001E 0x001D 0x001C 0x0010 0x001B 0x001A 0x0019 0x0018 (2) (3) 80-pin PN and 113-pin ZQW devices only 80-pin PN and 113-pin ZQW devices only Submit Documentation Feedback 27 Copyright © 2007–2011. Peripherals File Map (continued) MODULE Basic Clock Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control Brownout. Texas Instruments Incorporated .com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Table 14.

com Table 14. Peripherals File Map (continued) MODULE Port P2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Functions SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 REGISTER SHORT FORM P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN IFG2 IFG1 IE2 IE1 ADDRESS 0x002F 0x002E 0x002D 0x002C 0x002B 0x002A 0x0029 0x0028 0x0027 0x0026 0x0025 0x0024 0x0023 0x0022 0x0021 0x0020 0x0003 0x0002 0x0001 0x0000 28 Submit Documentation Feedback Copyright © 2007–2011. Texas Instruments Incorporated .MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti.

MSP430F261x MSP430F241x www.6 V Supply Voltage −V Note: Minimum processor frequency is defined by system clock.8 V.6 3. All voltages referenced to VSS.1 V -0. The JTAG fuse-blow voltage. Legend : 16 MHz System Frequency −MHz Supply voltage range during flash memory programming 12 MHz Supply voltage range during program execution 7. Recommended Operating Conditions MIN VCC VSS TA Supply voltage (AVCC = DVCC = VCC (1)) Supply voltage (AVSS = DVSS = VSS) Operating free-air temperature I version T version VCC = 1. Flash program or erase operations require a minimum VCC of 2. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Operating Area Copyright © 2007–2011. Duty cycle = 50% ± 10% fSYSTEM Processor frequency (maximum MCLK frequency) (2) (3) VCC = 2. See the specification of the respective module in this data sheet.15 MHz 1.7 V 3. Texas Instruments Incorporated Submit Documentation Feedback 29 . Modules might have a different maximum input clock specification.3 V to 4.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Absolute Maximum Ratings (1) Voltage applied at VCC to VSS Voltage applied to any pin (2) Diode current at any device terminal Tstg (1) (2) (3) Storage temperature (3) Unprogrammed device Programmed device -0. and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.3 V to VCC + 0. Figure 1.2 V. is allowed to exceed the absolute maximum rating.8 V 2.3 V.8 2. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Duty cycle = 50% ± 10% VCC ≥ 3.6 0 85 105 4.2 V 2. The MSP430 CPU is clocked directly with MCLK.5 MHz 4.3 V between AVCC and DVCC can be tolerated during power-up. Duty cycle = 50% ± 10% (1) (2) (3) During program execution During flash program/erase 1.3 V 3. VFB. The voltage is applied to the TEST pin when blowing the JTAG fuse.3 V ±2 mA -55°C to 150°C -55°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. A maximum difference of 0.15 12 16 MHz UNIT V V °C It is recommended to power AVCC and DVCC from the same source. These are stress ratings only.ti.2 0 -40 -40 dc dc dc MAX 3.7 V.

DIVMx = DIVSx = DIVAx = 11.100kHz Active mode (AM) current (100 kHz) (1) (2) All inputs are tied to 0 V or to VCC.2 V 3V 3V 3V VCC 2. OSCOFF = 0 fMCLK = fSMCLK = fDCO(0. Texas Instruments Incorporated .4kHz Active mode (AM) current (4 kHz) IAM. Program executes in flash. RSELx = 0. CPUOFF = 0. OSCOFF = 0 fDCO = fMCLK = fSMCLK = 1 MHz.1MHz Active mode (AM) current (1 MHz) IAM. CPUOFF = 0. fDCO = 0 Hz.2 V 2.2 V MIN TYP 365 375 515 525 330 340 460 470 2. CPUOFF = 0. Program executes in flash. DCOCTL = CALDCO_1MHZ. SELMx = 11. SCG0 = 0. SCG1 = 0.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS fDCO = fMCLK = fSMCLK = 1 MHz. Outputs do not source or sink any current. fACLK = 0 Hz. fACLK = 32768 Hz. 30 Submit Documentation Feedback Copyright © 2007–2011. The internal and external load capacitance is chosen to closely match the required 9 pF. SELS = 1. SCG1 = 0.1 15 3 19 67 80 84 99 MAX 395 420 560 595 370 390 495 520 9 31 11 32 86 99 107 128 µA µA µA µA UNIT IAM. SCG0 = 0. DCOCTL = CALDCO_1MHZ. CPUOFF = 0.1MHz Active mode (AM) current (1 MHz) 2. 0) ≈ 100 kHz.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. Program executes in RAM. SCG0 = 0.ti. fACLK = 32768 Hz. SCG0 = 1. OSCOFF = 1 TA -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C 3V 2. BCSCTL1 = CALBC1_1MHZ. SCG1 = 0. SCG1 = 0.2 V 3V 3V 2. BCSCTL1 = CALBC1_1MHZ. Program executes in flash. DCOx = 0. OSCOFF = 0 fMCLK = fSMCLK = fACLK = 32768 Hz/8 = 4096 Hz.2 V IAM.2 V 2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.

Figure 3.0 TA = 25 °C f DCO = 16 MHz f DCO = 12 MHz Active Mode Current − mA 5.0 0.0 6.2 V 4.0 5.0 f DCO = 1 MHz 1.0 7.MSP430F261x MSP430F241x www.0 1.0 4.0 3.0 0.5 2. Texas Instruments Incorporated Submit Documentation Feedback 31 .0 2.5 3.0 Active Mode Current − mA 8.0 1.0 16.0 ACTIVE MODE CURRENT vs DCO FREQUENCY TA = 85 °C 6.0 0.0 9. Copyright © 2007–2011.0 VCC − Supply Voltage − V f DCO − DCO Frequency − MHz Figure 2.ti.0 12.0 VCC = 3 V f DCO = 8 MHz TA = 85 °C 3.0 3.0 VCC = 2.0 TA = 25 °C 2.0 8.5 4.0 2.0 7.0 4.Active Mode Supply Current (Into VCC) ACTIVE MODE CURRENT vs SUPPLY VOLTAGE (TA = 25°C) 10.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Typical Characteristics .

SCG1 = 0. SCG0 = 1. fDCO = 1 MHz.3 7 24 1.7 14 MAX 63 98 105 125 49 62 55 73 33 46 36 55 1.5 0.5 7 24 UNIT ILPM0.2 V 3V 2.2 V ILPM2 Low-power mode 2 (LPM2) current (4) µA ILPM3. CPUOFF = 1.3 1. SCG0 = 1.4 0. OSCOFF = 0 85°C 105°C -40°C 25°C 85°C 105°C -40°C 25°C fDCO = fMCLK = fSMCLK = 0 MHz. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. OSCOFF = 1 85°C 105°C -40°C 25°C 85°C 105°C (1) (2) (3) (4) (5) All inputs are tied to 0 V or to VCC.2 7. fACLK = 32.768 Hz. Current for brownout and WDT clocked by ACLK included. DCOCTL = CALDCO_1MHZ.2 0. DCOCTL = CALDCO_1MHZ.768 Hz.5 0.2 4.9 1.5 24 1.1 0.2 V ILPM0. Current for brownout included. fACLK = 32.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. OSCOFF = 0 85°C 105°C -40°C 25°C 85°C 105°C -40°C 25°C fDCO = fMCLK = fSMCLK = 0 MHz. OSCOFF = 1 fMCLK = fSMCLK = 0 MHz.3 14 0.8 1 4.5 29. SCG1 = 1. fACLK = 0 Hz.6 0.2 V MIN (2) TYP 68 83 87 100 37 50 40 57 23 35 25 40 0. fSMCLK = fDCO(0.100kHz Low-power mode 0 (LPM0) current (3) µA 2. BCSCTL1 = CALBC1_1MHZ.VLO Low-power mode 3 (LPM3) current (4) µA ILPM4 Low-power mode 4 (LPM4) current (5) µA 32 Submit Documentation Feedback Copyright © 2007–2011. fSMCLK = fDCO = 1 MHz. Texas Instruments Incorporated .1MHz Low-power mode 0 (LPM0) current (3) µA 2. SCG1 = 1. fACLK = 32.2 V 3V 3V 3V VCC 2.1 4 13 0. SCG0 = 1. 0) ≈ 100 kHz. RSELx = 0.5 0. BCSCTL1 = CALBC1_1MHZ. Outputs do not source or sink any current. SCG1 = 1.6 5 16.5 0. CPUOFF = 1.2 1. SCG0 = 0.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS fMCLK = 0 MHz. SCG0 = 0. OSCOFF = 0 fMCLK = 0 MHz.5 4. SCG1 = 0. DCOx = 0. SCG0 = 0.6 14 0.2 1.ti. CPUOFF = 1. CPUOFF = 1.5 6 23 0.1 5. fACLK = 0 Hz. 3V 2.5 8 30 1 1 6. CPUOFF = 1.2 V 3V 2. OSCOFF = 0 TA -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C to 85°C 105°C -40°C 25°C fDCO = fMCLK = fSMCLK = 0 MHz. fACLK from internal LF oscillator (VLO).LFXT1 Low-power mode 3 (LPM3) current (3) µA ILPM3. Current for brownout and WDT clocked by SMCLK included.5 17 0.768 Hz. SCG1 = 1. CPUOFF = 1.

6 V 7.0 12.0 14.0 Vcc = 2.0 100. Copyright © 2007–2011.8 V 0.0 8.0 5.0 1.0 20.0 −40.0 10.0 V 6.0 80.0 13.0 11.0 3.0 0.MSP430F261x MSP430F241x www.0 TA − Temperature − °C ILPM4 − Low−power mode current − µA Figure 4.0 Vcc = 3.2 V 4.0 40.0 Vcc = 1.0 Vcc = 3.ti.0 −20.0 2.LPM4 Current LPM4 CURRENT vs TEMPERATURE 16. Texas Instruments Incorporated Submit Documentation Feedback 33 .0 120.0 60.0 9.0 15.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Typical Characteristics .

2 V 3V MIN 0.00 1.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.35 0. RST/NMI.ti.25 VCC 0.6 VCC UNIT V V 34 Submit Documentation Feedback Copyright © 2007–2011.65 2.55 VCC 1. unless otherwise noted.20 1. Standard Inputs (RST/NMI) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIL VIH Low-level input voltage High-level input voltage TEST CONDITIONS VCC 2.2 V 3V VITNegative-going input threshold voltage 2.2 V 3V Vhys RPull CI (1) Input voltage hysteresis (VIT+ .75 VCC 1.2 V/3 V MIN VSS 0. JTAG.65 1 1 50 V kΩ pF V V UNIT Inputs (Ports P1 and P2) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER t(int) (1) External interrupt timing TEST CONDITIONS Port P1.75 0.x.2 V/3 V 2. Texas Instruments Incorporated .2 V/3 V MIN MAX ±50 UNIT nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s).com Schmitt-Trigger Inputs (Ports P1 Through P8. Leakage Current (Ports P1 Through P8) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) High-impedance leakage current (1) (2) TEST CONDITIONS VCC 2.55 0. XIN.8 VCC MAX VSS + 0.VIT-) Pullup/pulldown resistor Input capacitance XIN and XT2IN in bypass mode only For pullup: VIN = VSS.3 20 35 5 TYP MAX 0.2 0. and XT2IN) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ Positive-going input threshold voltage TEST CONDITIONS VCC 2. External trigger pulse width to set interrupt flag (1) VCC 2. The port pin is selected for input and the pullup/pulldown resistor is disabled.x to P2.25 0. P2: P1. The leakage of the digital port pins is measured individually.2 V/3 V MIN 20 MAX UNIT ns An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set even with trigger signals shorter than t(int). For pulldown: VIN = VCC VIN = VSS or VCC 2.45 VCC 1.

6 VSS VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS + 0. CL = 20 pF.6 UNIT I(OHmax) = -1. CL = 20 pF.4/SMCLK.6 VCC .4/MCLK.25 VSS + 0. XT1 mode P5. DCO P1. I(OHmax) and I(OLmax).25 VSS + 0. CL = 20 pF.5 mA (1) I(OLmax) = 6 mA (2) V (1) (2) The maximum total current. I(OHmax) and I(OLmax). RL = 1 kΩ (1) (2) VCC 2.2 V 2.25 VCC .4/MCLK. The maximum total current.6/ACLK.MSP430F261x MSP430F241x www. XT2 mode P1.6/ACLK.2 V 3V MIN dc dc dc dc 30 40 40 50% 15 ns 40 50% 15 ns TYP MAX 10 12 12 16 UNIT MHz MHz P2.4/SMCLK.0. CL = 20 pF.5 mA (1) V VOL Low-level output voltage I(OLmax) = 6 mA (2) I(OLmax) = 1.0/ACLK/CA2. LF mode P5. P1. The output is connected to the center tap of the divider.y fPort°CLK Port output frequency (with load) Clock output frequency TEST CONDITIONS P1.2 V 3V 3V 2.2 V 3V 3V MIN VCC .6 VSS + 0.5-kΩ resistors between VCC and VSS is used as load.5 mA VOH High-level output voltage I(OHmax) = -6 mA (1) (2) VCC 2.5 mA (1) I(OHmax) = -6 mA (2) I(OLmax) = 1. Output Frequency (Ports P1 Through P8) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fPx. CL = 20 pF.2 V 2. CL = 20 pF. CL = 20 pF (2) P5. for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.0. CL = 20 pF.4/SMCLK. Texas Instruments Incorporated Submit Documentation Feedback 35 .2 V 3V 2. for all outputs combined should not exceed ±12 mA to hold the maximum voltage drop specified.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Outputs (Ports P1 Through P8) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS I(OHmax) = -1. Copyright © 2007–2011. XT1 mode 50 50 70 60 60 50% + 15 ns 60 50% + 15 ns % t(Xdc) Duty cycle of output frequency P5. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. DCO (1) (2) A resistive divider with two 0.4/SMCLK.25 VCC .0.0.

5 0.0 0.0 10.0 −30.0 TA = 85°C 30.0 2.0 LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50. HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE −10.0 TA = 25°C TA = 85°C TA = 25°C 15.5 2. HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 0. 36 Submit Documentation Feedback Copyright © 2007–2011.0 3.5 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V Figure 5.com Typical Characteristics .0 1.5 1.0 0.0 20.5 20.2 V P4.5 −10.5 −5.0 −15. Figure 8.5 1.0 0.5 40.ti.0 −20.5 3.0 VCC = 3 V P4.0 2.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.0 5.0 3.5 2.0 I OL − Typical Low-Level Output Current − mA VCC = 2.0 1.5 2.0 2.5 1.0 −20.5 −50.0 0.0 0.0 TA = 85°C −40.5 VOH − High-Level Output Voltage − V VOH − High-Level Output Voltage − V Figure 7.0 10.0 TA = 25°C 0.5 2. Texas Instruments Incorporated .Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 25.0 0.0 1.0 2.0 Figure 6.0 0.0 0.5 1.5 3.2 V P4.0 I OL − Typical Low-Level Output Current − mA VCC = 3 V P4.0 I OH − Typical High-Level Output Current − mA I OH − Typical High-Level Output Current − mA VCC = 2.0 1.0 TA = 85°C TA = 25°C −25.

ti.71 210 2000 MAX UNIT V V mV µs µs The current consumption of the brownout module is already included in the ICC current consumption data. Texas Instruments Incorporated Submit Documentation Feedback 37 . POR/Brownout Reset (BOR) vs Supply Voltage Copyright © 2007–2011.8 V.2 V/3 V 2 TEST CONDITIONS dVCC/dt ≤ 3 V/s dVCC/dt ≤ 3 V/s dVCC/dt ≤ 3 V/s 70 130 VCC MIN TYP 0.7 × V(B_IT-) 1.MSP430F261x MSP430F241x www.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 POR/Brownout Reset (BOR) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(start) V(B_IT-) Vhys(B_IT-) td(BOR) t(reset) (1) See Figure 9 See Figure 9 through Figure 11 See Figure 9 See Figure 9 Pulse length needed at RST/NMI pin to accepted reset internally 2. VCC Vhys(B_IT−) V(B_IT−) VCC(start) 1 0 t d(BOR) Figure 9. The voltage level V(B_IT-) + Vhys(B_IT-)is ≤ 1.

VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal 38 Submit Documentation Feedback Copyright © 2007–2011.com Typical Characteristics . Texas Instruments Incorporated .001 VCC(drop) VCC 3V t pw 1 t pw − Pulse Width − µs 1000 1 ns 1 ns t pw − Pulse Width − µs Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 VCC = 3 V VCC(drop) − V 1.001 t f = tr 1 t pw − Pulse Width − µs 1000 tf tr Typical Conditions 3V t pw t pw − Pulse Width − µs Figure 11.5 1 VCC(drop) 0.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.5 1 0.POR/Brownout Reset (BOR) 2 VCC = 3 V Typical Conditions VCC(drop) − V 1.5 0 0.5 0 0.ti.

94 3.8 1.2 3. external voltage applied on A7 ICC(SVS) (1) (2) (3) (3) TEST CONDITIONS dVCC/dt > 30 V/ms (see Figure 12) MIN 5 TYP MAX 150 2000 UNIT µs µs µs V mV V mV 150 1.24 3.46 2.29 3.05 2.4 2.004 × V(SVS_IT-) 4.69 2.9 3.83 2.5 3.2 10 120 300 12 1. switch from VLD = 0 to VLD ≠ 0.11 3. The current consumption of the SVS module is not included in the ICC current consumption data.58 2.ti.55 70 0.37 2.4 1. external voltage applied on A7 V(SVS_IT-) VLD = 2 to 14 VLD = 15 VLD = 1 VLD = 2 VLD = 3 VLD = 4 VLD = 5 VLD = 6 VCC/dt ≤ 3V/s (see Figure 12 and Figure 13) VLD = 7 VLD = 8 VLD = 9 VLD = 10 VLD = 11 VLD = 12 VLD = 13 VLD = 14 VCC/dt ≤ 3 V/s (see Figure 12 and Figure 13).25 2.1 1.48 2.6 V.5 2.24 2.71 2.3 15 V VLD = 15 VLD ≠ 0.2 V/3 V µA tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD value somewhere between 2 and 15.13 3. Copyright © 2007–2011.43 1.14 2.76 (2) 3. VCC = 3 V VLD ≠ 0 (1) VLD ≠ 0.65 2.61 (2) 3.05 3.94 2. The overdrive is assumed to be > 50 mV. Supply Voltage Monitor (SVM) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER t(SVSR) td(SVSon) tsettle V(SVSstart) dVCC/dt ≤ 30 V/ms SVSon.7 (2) 1.2 2.8 2. Texas Instruments Incorporated Submit Documentation Feedback 39 .33 2.86 3 3.05 2.60 2. VCC/dt ≤ 3 V/s (see Figure 12) VLD = 1 VCC/dt ≤ 3 V/s (see Figure 12) Vhys(SVS_IT-) VCC/dt ≤ 3 V/s (see Figure 12).9 2.99 (2) 1.1 2.MSP430F261x MSP430F241x www. VCC = 2. The recommended operating voltage range is limited to 3.016 × V(SVS_IT-) 20 2.3 2.35 3.42 3.7 155 0.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Supply Voltage Supervisor (SVS).

MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti.com Software sets VLD >0: SVS is active AVCC V(SVS_IT−) V(SVSstart) V(B_IT−) VCC(start) Brownout Region Brownout Region Vhys(SVS_IT−) Vhys(B_IT−) Brownout 1 0 SVS out 1 0 Set POR 1 t d(BOR) SVS Circuit is Active From VLD > to V CC < V( B_IT−) t d(BOR) td(SVSon) undefined td(SVSR) 0 Figure 12. VCC(min): Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1) 40 Submit Documentation Feedback Copyright © 2007–2011. SVS Reset (SVSR) vs Supply Voltage VCC 3V t pw 2 Rectangular Drop 1. Texas Instruments Incorporated .5 VCC(min) − V Triangular Drop 1 1 ns 0.5 VCC 3V 0 1 10 100 1000 VCC(min) t f = tr tf tr t pw − Pulse Width − µs t pw 1 ns VCC(min) t − Pulse Width − µs Figure 13.

3) DCO frequency (15.00 4.2 V/3 V 2.10 1.00 4.2 V/3 V 2.2 V/3 V 2.DCO) SDCO = fDCO(RSEL.54 0.2 3.60 13.2 V/3 V 2.2 V/3 V 2. MODx = 0 RSELx = 3. 3) DCO frequency (15. DCOx = 0. 3) DCO frequency (2..3) fDCO(14. RSELx = 14 overlaps RSELx = 15. 3) DCO frequency (11.2 V/3 V 2.6 3.06 0. 3) DCO frequency (12. MODx = 0 RSELx = 12.2 V/3 V 2.DCO+1) DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER RSELx < 14 VCC fDCO(0. MODx = 0 RSELx = 9. DCOx = 3. DCOx = 3.30 5.MSP430F261x MSP430F241x www. . The frequency fDCO(RSEL.DCO+1)/fDCO(RSEL. DCOx = 3.0 1.2 V/3 V 2. DCO control bits DCOx have a step size as defined by parameter SDCO. 3) DCO frequency (9.3) fDCO(10. 7) Frequency step between range RSEL and RSEL+1 Frequency step between tap DCO and DCO+1 Duty cycle RSELx = 14 RSELx = 15 RSELx = 0. Modulation control bits MODx select how often fDCO(RSEL.3) fDCO(4.06 1.3) fDCO(2. DCOx = 3. DCOx = 3. 3) DCO frequency (4.6 3.3) fDCO(1.0) fDCO(0. MODx = 0 RSELx = 0. DCOx = 3. DCOx = 3.07 0. MODx = 0 RSELx = 6. 3) DCO frequency (10.40 0. DCOx = 3. 3) DCO frequency (8. DCOx = 3. DCOx = 3. DCOx = 3.3) fDCO(5. DCOx = 3.10 3.2 V/3 V 2. MODx = 0 RSELx = 8. MODx = 0 RSELx = 15. MODx = 0 RSELx = 7. 0) DCO frequency (0. MODx = 0 RSELx = 2. MODx = 0 SRSEL = fDCO(RSEL+1. DCOx = 3.60 2.30 6.3) fDCO(9.9 18.3) fDCO(7.3) fDCO(3.20 0.14 0. MODx = 0 RSELx = 15.4/SMCLK 2.50 3.3) fDCO(8.3) fDCO(6.2 V/3 V 3V 3V 2.60 12.ti. DCOx = 7. 3) DCO frequency (14.08 50 TEST CONDITIONS VCC MIN 1.3) fDCO(15.2 V/3 V 2. 3) DCO frequency (5.2 V/3 V 2.10 0.50 7.30 9.8 2..05 40 1.0 16.DCO) Measured at P1.0 TYP MAX 3.3) fDCO(13. MODx = 0 RSELx = 1.DCO)/fDCO(RSEL.54 0.55 1.2 V/3 V 2.0 0.50 2.DCO) + (32 – MOD) × fDCO(RSEL. The frequency is an average equal to: faverage = 32 × fDCO(RSEL. MODx = 0 RSELx = 5. 3) DCO frequency (6.77 1.3) fDCO(12.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Main DCO Characteristics • • • All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1. DCOx = 3. Texas Instruments Incorporated Submit Documentation Feedback 41 .2 V/3 V 2. MODx = 0 RSELx = 13. 3) DCO frequency (3.7) SRSEL SDCO Supply voltage DCO frequency (0.2 V/3 V 2. 3) DCO frequency (1.14 0.5 26.DCO+1) is used within the period of 32 DCOCLK cycles.28 0.3) fDCO(11.20 0.2 V/3 V 2.28 0. MODx = 0 RSELx = 11.2 V/3 V 2.39 0.2 V/3 V 1.6 0. DCOx = 3.12 60 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ratio ratio % V UNIT Copyright © 2007–2011.17 0. DCOx = 3. MODx = 0 RSELx = 4.2 V/3 V 2. MODx = 0 RSELx = 10.80 1.DCO+1) MOD × fDCO(RSEL.DCO) is used for the remaining cycles. 3) DCO frequency (7. MODx = 0 RSELx = 14.DCO) × fDCO(RSEL.00 8.3) fDCO(15. 3) DCO frequency (13.

64 11. Gating time: 2 ms TEST CONDITIONS TA 25°C 25°C VCC 3V 3V MIN -1 0. Gating time: 5 ms BCSCTL1 = CALBC1_8MHZ.6 V 3V 0°C to 85°C 3.800 7.48 16.com Calibrated DCO Frequencies .6 V 2. Gating time: 5 ms BCSCTL1 = CALBC1_12MHZ.0 1 1 1 8 8 8 12 12 12 16 16 MAX +2.2 V 0°C to 85°C 3V 3.00 TYP ±0. Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ.990 TYP ±0.36 12.36 16. DCOCTL = CALDCO_16MHZ.64 11. Gating time: 5 ms BCSCTL1 = CALBC1_8MHZ.Tolerance at Calibration over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Frequency tolerance at calibration fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ.0 ±2.0 ±1. Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ.920 8 8.010 UNIT % MHz fCAL(8MHz) 8-MHz calibration value 25°C 3V 7. DCOCTL = CALDCO_16MHZ. Gating time: 2 ms TEST CONDITIONS TA 0°C to 85°C 0°C to 85°C 0°C to 85°C 0°C to 85°C VCC 3V 3V 3V 3V 2.760 7.970 0.600 11.16 MHz Calibrated DCO Frequencies .ti.5 +3 1.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.030 8.5 +2. DCOCTL = CALDCO_1MHZ.24 12.2 V 0°C to 85°C 3V 3.970 7.52 15.2 V 0°C to 85°C 3V 3.12 MHz fCAL(16MHz) 16-MHz calibration value 25°C 3V 15.5 ±1. DCOCTL = CALDCO_12MHZ.20 8.025 1.030 1. Texas Instruments Incorporated .975 0.080 MHz fCAL(12MHz) 12-MHz calibration value 25°C 3V 11.5 -2.5 +2. Gating time: 5 ms BCSCTL1 = CALBC1_12MHZ.88 12 12. DCOCTL = CALDCO_8MHZ.2 1 MAX +1 1. DCOCTL = CALDCO_1MHZ. DCOCTL = CALDCO_8MHZ.6 V MIN -2.6 V 2.Tolerance Over Temperature 0°C to 85°C over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER 1-MHz tolerance over temperature 8-MHz tolerance over temperature 12-MHz tolerance over temperature 16-MHz tolerance over temperature fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ. DCOCTL = CALDCO_12MHZ.64 15.48 MHz MHz MHz MHz UNIT % % % % fCAL(8MHz) 8-MHz calibration value fCAL(12MHz) 12-MHz calibration value fCAL(16MHz) 16-MHz calibration value 42 Submit Documentation Feedback Copyright © 2007–2011.5 -2.5 -3 0.40 8.36 12.84 16 16.

DCOCTL = CALDCO_12MHZ.ti.6 V MIN -5 -5 -5 -6 0.6 V 2. Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ.8 V to 3.6 V 2.6 V 1.6 V 7.6 V 1.76 8 8. DCOCTL = CALDCO_16MHZ.8 V to 3.8 V to 3.2 V to 3. DCOCTL = CALDCO_1MHZ.48 MHz Calibrated DCO Frequencies .4 MHz fCAL(12MHz) -40°C to 105°C 2.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Calibrated DCO Frequencies . Gating time: 5 ms BCSCTL1 = CALBC1_8MHZ. DCOCTL = CALDCO_1MHZ.8 V to 3.03 UNIT % % % % MHz fCAL(8MHz) 8-MHz calibration value 25°C 1.6 V 11. Gating time: 2 ms TEST CONDITIONS TA -40°C to 105°C -40°C to 105°C -40°C to 105°C -40°C to 105°C -40°C to 105°C VCC 1. DCOCTL = CALDCO_16MHZ.24 MHz fCAL(12MHz) 12-MHz calibration value 25°C 2.6 V 3 V to 3.8 V to 3.6 8 8.4 12 12.05 UNIT % % % % MHz fCAL(8MHz) -40°C to 105°C 1.6 V 15 16 16.8 V to 3. Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ. Texas Instruments Incorporated Submit Documentation Feedback 43 . Gating time: 5 ms BCSCTL1 = CALBC1_12MHZ.2 V to 3. Gating time: 2 ms TEST CONDITIONS TA 25°C 25°C 25°C 25°C 25°C VCC 1.97 TYP ±2 ±2 ±2 ±2 1 MAX +3 +3 +3 +3 1.95 TYP ±2 ±2 ±2 ±3 1 MAX +5 +5 +5 +6 1.Overall Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER 1-MHz tolerance overall 8-MHz tolerance overall 12-MHz tolerance overall 16-MHz tolerance overall fCAL(1MHz) 1-MHz calibration value 8-MHz calibration value 12-MHz calibration value 16-MHz calibration value BCSCTL1 = CALBC1_1MHZ.MSP430F261x MSP430F241x www.6 V 1.6 V 1. DCOCTL = CALDCO_8MHZ.2 V to 3.2 V to 3.6 MHz fCAL(16MHz) -40°C to 105°C 3 V to 3.36 MHz fCAL(16MHz) 16-MHz calibration value 25°C 3 V to 3.8 V to 3. Gating time: 5 ms BCSCTL1 = CALBC1_8MHZ. DCOCTL = CALDCO_8MHZ.6 V 7.6 V 11.Tolerance Over Supply Voltage VCC over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER 1-MHz tolerance over VCC 8-MHz tolerance over VCC 12-MHz tolerance over VCC 16-MHz tolerance over VCC fCAL(1MHz) 1-MHz calibration value BCSCTL1 = CALBC1_1MHZ. Gating time: 5 ms BCSCTL1 = CALBC1_12MHZ.8 V to 3.6 V 3 V to 3.64 12 12.6 V MIN -3 -3 -3 -6 0. DCOCTL = CALDCO_12MHZ.6 V 15 16 17 MHz Copyright © 2007–2011.

CALIBRATED 16-MHz FREQUENCY vs SUPPLY VOLTAGE 12.7 11.5 4. CALIBRATED 12-MHz FREQUENCY vs SUPPLY VOLTAGE 12.0 2.85 7.99 TA = −40 °C 0.9 TA = 25 °C TA = 85 °C 15.05 8. Figure 17.0 2.90 7.01 Frequency − MHz TA = 105 °C 1.98 1.7 1.5 3.5 Frequency − MHz 8.com Typical Characteristics .00 7.20 TA = 105 °C 8.8 TA = 105 °C 11.5 2.5 4.5 3.0 TA = −40 °C 15.ti.0 2. 44 Submit Documentation Feedback Copyright © 2007–2011.5 4.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.0 3.0 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 16. Texas Instruments Incorporated .9 Frequency − MHz 16.15 1.0 3.0 TA = 25 °C TA = 85 °C 11.80 1.0 2.0 3.5 4.6 1.1 TA = −40 °C Frequency − MHz 12.95 7.Calibrated DCO Frequency CALIBRATED 1-MHz FREQUENCY vs SUPPLY VOLTAGE 1.0 15.5 2.0 2.2 16.10 8.0 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 14.02 8.00 TA = 85 °C TA = 25 °C 0.5 TA = −40 °C TA = 25 °C CALIBRATED 8-MHz FREQUENCY vs SUPPLY VOLTAGE TA = 85 °C 2.0 3.8 TA = 105 °C 15.5 3.5 3.1 Figure 15.

Parameter applicable only if DCOCLK is used for MCLK. DCOCTL = CALDCO_16MHZ tCPU.LPM3/4 2.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Wake-Up From Lower-Power Modes (LPM3.ti.5 µs 1 1 UNIT tDCO.LPM3/4 The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example. Texas Instruments Incorporated Submit Documentation Feedback 45 .LPM3/4 (1) (2) CPU wake-up time from LPM3/4 (2) 3V 1 / fMCLK + tClock. DCOCTL = CALDCO_12MHZ BCSCTL1 = CALBC1_16MHZ.2 V/3 V VCC MIN TYP MAX 2 1. Typical Characteristics . Copyright © 2007–2011. LPM4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS BCSCTL1 = CALBC1_1MHZ. port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK).00 DCO Frequency − MHz 10.10 1.DCO Clock Wake-Up Time From LPM3/4 DCO WAKE-UP TIME FROM LPM3 vs DCO FREQUENCY 10.00 DCO Wake Time − µs 1.10 0. DCOCTL = CALDCO_8MHZ BCSCTL1 = CALBC1_12MHZ.MSP430F261x MSP430F241x www.00 RSELx = 0 to 11 RSELx = 12 to 15 0. DCOCTL = CALDCO_1MHZ DCO clock wake-up time from LPM3/4 (1) BCSCTL1 = CALBC1_8MHZ.00 Figure 18.

TA = 25°C DCOR = 1. DCOx = 3.8 1.00 1000.6 W with 1% tolerance and TK = ±50 ppm/°C. 0. DCOx = 3. Figure 20. type 0257. RSELx = 4.2 V.00 0.95 ±0.00 100.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. MODx = 0 DCOR = 1.00 100. RSELx = 4. TA = 25°C DCO Frequency − MHz DCO Frequency − MHz RSELx = 4 1. Metal film resistor. MODx = 0. Typical Characteristics .00 0.00 ROSC − External Resistor − kW ROSC − External Resistor − kW Figure 19.00 10000.01 10. RSELx = 4.10 0.2 V 3V 2.2 V/3 V TYP 1.00 RSELx = 4 1.00 10000.com DCO With External Resistor ROSC (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fDCO.01 10.10 0. DCOx = 3.1 10 MHz %/°C %/V UNIT ROSC = 100 kΩ.ROSC DT DV (1) DCO output frequency with ROSC Temperature drift Drift with VCC TEST CONDITIONS DCOR = 1.00 10.00 1000.00 DCO FREQUENCY vs ROSC VCC = 3 V. 46 Submit Documentation Feedback Copyright © 2007–2011. Texas Instruments Incorporated . TA = 25°C 10.DCO With External Resistor ROSC DCO FREQUENCY vs ROSC VCC = 2. MODx = 0 VCC 2.ti.2 V/3 V 2.

50 1.00 0.00 1. Texas Instruments Incorporated Submit Documentation Feedback 47 .25 1.50 2.50 1.5 2.0 TA − Temperature − °C VCC − Supply Voltage − V Figure 21.75 1.25 1.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Typical Characteristics .25 DCO Frequency − MHz DCO Frequency − MHz 2.0 0.25 0.0 25.ti. Copyright © 2007–2011.75 0.MSP430F261x MSP430F241x www.00 −50.5 3.25 ROSC = 1M 50.50 ROSC = 270k ROSC = 270k ROSC = 1M 0.75 1.0 2.0 3.00 1.00 0.0 ROSC = 100k ROSC = 100k 2.0 0.DCO With External Resistor ROSC (continued) DCO FREQUENCY vs TEMPERATURE VCC = 3 V 2.50 2.00 1.5 4.50 0.0 75. Figure 22.25 DCO FREQUENCY vs SUPPLY VOLTAGE TA = 25°C 2.0 −25.75 0.0 100.

LF mode XTS = 0.logic LFXT1 oscillator crystal frequency.8 to 3.8 V) 48 Submit Documentation Feedback Copyright © 2007–2011.MIN(1.2 V/3 V 2. it is recommended to verify the correct load by measuring the ACLK frequency.LF = 32768 Hz.8 V to 3. CL.8 to 3. LF mode (2) fFault.6 V 10000 MIN TYP 32768 32768 500 kΩ 200 1 5.eff Integrated effective load capacitance. fLFXT1. Frequencies below the MIN specification set the fault flag.LF = 32768 Hz XTS = 0.eff = 6 pF XTS = 0. ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fVLO dfVLO/dT dfVLO/dVCC (1) (2) VLO frequency VLO frequency temperature drift (1) VLO frequency supply voltage drift (2) 25°C TA -40°C to 85°C 105°C VCC 2. LF mode (3) (2) (3) (4) To improve EMI on the XT1 oscillator.(-40°C)) Calculated using the box method: (MAX(1.6 V . Measured with logic-level input frequency but also applies to operation with crystals. LFXT1Sx = 0.6 V 1.2 V/3 V 2.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.5 11 2.8 V to 3. Measured at P2. XCAPx = 0 (4) OALF CL.ti.5 4 MAX 20 22 UNIT kHz %/°C %/V Calculated using the box method: I: (MAX(-40 to 85°C) . (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.LF. Frequencies above the MAX specification do not set the fault flag.MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C . For a correct setup. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.eff = 12 pF XTS = 0.LF fLFXT1. Includes parasitic bond and package capacitance (approximately 2 pF per pin). LFXT1Sx = 3. XCAPx = 0 LF mode Oscillation allowance for LF crystals XTS = 0. XCAPx = 3 Duty cycle. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fLFXT1. XCAPx = 1 XTS = 0.MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C . Because the PCB adds additional capacitance. XCAPx = 2 XTS = 0.1.com Crystal Oscillator LFXT1. Texas Instruments Incorporated . LF mode 0.6 V MIN 4 TYP 12 0.0/ACLK. CL.LF = 32768 Hz. the following guidelines should be observed. LFXT1Sx = 3.8 V to 3.5 8.8 to 3.6 V) / (3. (b) Design a good ground plane around the oscillator pins. (a) Keep the trace between the device and the crystal as short as possible.LF (1) Oscillator fault frequency.2 V/3 V 30 10 50 70 10000 % Hz pF 50000 MAX UNIT Hz Hz LFXT1 oscillator logic level square wave input frequency.(-40°C)) T: (MAX(-40 to 105°C) . XTS = 0. fLFXT1. fLFXT1. XCAPx = 0 XTS = 0. LFXT1Sx = 0.2 V/3 V 1. the effective load capacitance should always match the specification of the crystal that is used. 1 TEST CONDITIONS XTS = 0. LFXT1Sx = 0 or 1 VCC 1.6 V) . (f) If conformal coating is used.6 V)) / MIN(1. Frequencies in between might set the flag.

HF mode 2 LFXT1 oscillator logic-level square-wave input frequency. (b) Design a good ground plane around the oscillator pins.eff = 15 pF XTS = 1. This signal is no longer required for the serial programming adapter. XCAPx = 0. LFXT1Sx = 3. ensure that it does not induce capacitive/resistive leakage between the oscillator pins.4 1 2 2 2 0.HF = 4 MHz. CL. LFXT1Sx = 2. and frequencies in between might set the flag.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Crystal Oscillator LFXT1. XCAPx = 0. For a correct setup. Measured with logic-level input frequency.HF2 XTS = 1.8 V to 3. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. CL.HF = 16 MHz (4) MIN 0.6 V MHz 2700 800 300 1 40 2. CL. HF mode 1 LFXT1 oscillator crystal frequency.4 0. the effective load capacitance should always match the specification of the used crystal.HF = 10 MHz XTS = 1. Because the PCB adds additional capacitance. (f) If conformal coating is used. Includes parasitic bond and package capacitance (approximately 2 pF per pin).0/ACLK.4 0. HF mode 0 LFXT1 oscillator crystal frequency. frequencies above the MAX specification do not set the fault flag.HF1 LFXT1 oscillator crystal frequency. XCAPx = 0 (3) XTS = 1.6 V 1.eff Integrated effective load capacitance. Measured at P2. LFXT1Sx = 1. XCAPx = 0 (5) (2) (3) (4) (5) To improve EMI on the XT2 oscillator the following guidelines should be observed: (a) Keep the trace between the device and the crystal as short as possible. Texas Instruments Incorporated Submit Documentation Feedback 49 . LFXT1Sx = 0. Values are specified by crystal manufacturers. High-Frequency Mode (1) PARAMETER fLFXT1. Measured at P2. it is recommended to verify the correct load by measuring the ACLK frequency.6 V 1. XCAPx = 0 VCC 1. LFXT1Sx = 2. XCAPx = 0 XTS = 1. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.ti.6 V 3 V to 3. HF mode fFault.HF.8 V to 3.2 V to 3. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.HF0 fLFXT1.HF = 16 MHz. XCAPx = 0.eff = 15 pF CL.6 V fLFXT1. LFXT1Sx = 3.eff = 15 pF OAHF Oscillation allowance for HF crystals (see Figure 23 and Figure 24) XTS = 1. Copyright © 2007–2011.6 V XTS = 1.MSP430F261x MSP430F241x www. fLFXT1.6 V 1. LFXT1Sx = 1.2 V/3 V 40 2. XCAPx = 0.0/ACLK. HF mode TEST CONDITIONS XTS = 1. XCAPx = 0 XTS = 1. Requires external capacitors at both terminals. fLFXT1.8 V to 3. fLFXT1.4 TYP MAX 1 4 10 12 16 10 12 16 UNIT MHz MHz MHz fLFXT1.HF (1) Oscillator fault frequency XTS = 1. fLFXT1.2 V to 3. Frequencies below the MIN specification set the fault flag. HF mode (2) XTS = 1. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. LFXT1Sx = 0. fLFXT1.logic 2.2 V/3 V 30 50 60 300 kHz 50 60 % pF Ω Duty cycle. XCAPx = 0 2.6 V 3 V to 3. but also applies to operation with crystals. XCAPx = 0.HF = 1 MHz.8 V to 3.

eff = 15 pF. 50 Submit Documentation Feedback Copyright © 2007–2011.00 10.00 0.LFXT1 Oscillator in HF Mode (XTS = 1) OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL. OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL.00 1000.00 LFXT1Sx =0 LFXT1Sx = 1 10.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti. TA = 25°C 1500 1400 1300 XT Oscillator Supply Current − µA 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 4 8 12 16 20 Crystal Frequency − MHz LFXT1Sx = 0 LFXT1Sx = 1 LFXT1Sx = 2 Figure 24.00 Crystal Frequency − MHz Figure 23.com Typical Characteristics .00 Oscillation Allowance − W 10000.00 100. Texas Instruments Incorporated .00 LFXT1Sx = 2 100. TA = 25°C 100000.10 1.eff = 15 pF.

2 V/3 V 30 50 60 300 kHz 50 60 % pF Ω Duty cycle Oscillator fault frequency. fXT2 = 16 MHz XT2Sx = 3 (5) fFault (1) (2) (3) (4) (5) To improve EMI on the XT2 oscillator the following guidelines should be observed: (a) Keep the trace between the device and the crystal as short as possible. Because the PCB adds additional capacitance.4 1 2 2 2 0. (c) Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.6 V 3 V to 3.4/SMCLK.eff = 15 pF XT2Sx = 2.8 V to 3.eff Integrated effective load capacitance. fXT2 = 16 MHz. mode 1 XT2 oscillator crystal frequency.2 V to 3. CL.ti.4 TYP MAX 1 4 10 12 16 10 12 16 UNIT MHz MHz MHz 2. but also applies to operation with crystals. Includes parasitic bond and package capacitance (approximately 2 pF per pin). ensure that it does not induce capacitive/resistive leakage between the oscillator pins.2 V fXT2 XT2 oscillator logic-level square-wave XT2Sx = 3 input frequency XT2Sx = 0.eff = 15 pF CL. and frequencies in between might set the flag. For a correct setup.2 V to 3.4 0. (d) Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins. Copyright © 2007–2011.6 V 1. Requires external capacitors at both terminals. CL. Texas Instruments Incorporated Submit Documentation Feedback 51 .MSP430F261x MSP430F241x www. CL. (f) If conformal coating is used. mode 0 XT2 oscillator crystal frequency.6 V 1. the effective load capacitance should always match the specification of the used crystal.6 V 3 V to 3. Measured with logic-level input frequency.2 V/3 V 40 2.4 0. fXT2 = 1 MHz. mode 2 TEST CONDITIONS XT2Sx = 0 XT2Sx = 1 VCC 1.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Crystal Oscillator XT2 (1) PARAMETER fXT2 fXT2 XT2 oscillator crystal frequency. (b) Design a good ground plane around the oscillator pins. fXT2 = 4 MHz.6 V MHz 2700 800 300 1 40 2. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.8 V to 2.8 V to 3. fXT2 = 10 MHz Measured at P1.eff = 15 pF OA Oscillation allowance (see Figure 25 and Figure 26) XT2Sx = 1. it is recommended to verify the correct load by measuring the ACLK frequency. Values are specified by crystal manufacturers.4/SMCLK. HF mode (2) See (3) MIN 0.6 V 1. HF mode (4) Measured at P1. frequencies above the MAX specification do not set the fault flag.8 V to 2. Frequencies below the MIN specification set the fault flag.2 V fXT2 XT2Sx = 2 2.

00 10. 52 Submit Documentation Feedback Copyright © 2007–2011.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.XT2 Oscillator OSCILLATION ALLOWANCE vs CRYSTAL FREQUENCY CL.00 XT2Sx = 2 100.00 100.eff = 15 pF.00 0. Texas Instruments Incorporated .com Typical Characteristics .10 1. TA = 25°C 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 4 XT Oscillator Supply Current − µA XT2Sx = 2 XT2Sx = 1 XT2Sx = 0 8 12 16 20 Crystal Frequency − MHz Figure 26.00 1000. OSCILLATOR SUPPLY CURRENT vs CRYSTAL FREQUENCY CL.ti.00 Crystal Frequency − MHz Figure 25.00 XT2Sx = 0 XT2Sx = 1 10.eff = 15 pF. TA = 25°C 100000.00 Oscillation Allowance − W 10000.

MSP430F261x MSP430F241x www. TA2 VCC 2. ACLK External: TACLK.2 V/3 V 20 MIN TYP MAX 10 16 MHz ns UNIT Copyright © 2007–2011.2 V 3V 2. Texas Instruments Incorporated Submit Documentation Feedback 53 .cap Timer_B clock frequency Timer_B capture timing TEST CONDITIONS Internal: SMCLK. TB1. INCLK Duty cycle = 50% ± 10% TB0. TA1. ACLK External: TACLK.cap Timer_A clock frequency Timer_A capture timing TEST CONDITIONS Internal: SMCLK.ti. TB2 VCC 2.2 V 3V 2.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fTA tTA. INCLK Duty cycle = 50% ± 10% TA0.2 V/3 V 20 MIN TYP MAX 10 16 MHz ns UNIT Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fTB tTB.

2 V 3V 2. ACLK Duty cycle = 50% ± 10% 2.2 V 3V 2. STE high to SOMI high impedance SIMO input data setup time SIMO input data hold time SOMI output data valid time UCLK edge to SOMI valid. For the master's parameters tSU.SI(USCI). tSU. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.SI tVALID.SI tHD.2 V/3 V 2. USCI (SPI Slave Mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 29 and Figure 30) PARAMETER tSTE.MO(Master) see the SPI parameters of the attached slave.MI tVALID. tSU.SO(Slave).SI(Slave).MI tHD. see the SPI parameters of the attached slave. STE low to SOMI data out STE disable time.MI(Master) and tVALID. Texas Instruments Incorporated .ACC tSTE. STE low to clock STE lag time.2 V 3V 2. USCI (SPI Master Mode) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 27 and Figure 28) PARAMETER fUSCI tSU.2 V 3V 20 15 10 10 75 50 110 75 10 50 50 MIN TYP 50 MAX UNIT ns ns ns ns ns ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID.SI(Slave) and tVALID. For the slave's parameters tSU.DIS tSU.2 V/3 V 2.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.MO(Master) + tSU. ACLK External: UCLK Duty cycle = 50% ± 10% 2.SO(Slave)).LEAD tSTE.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fUSCI fBITCLK tτ (1) (2) USCI input clock frequency BITCLK clock frequency (equals baud rate in MBaud) (1) UART receive deglitch time (2) CONDITIONS Internal: SMCLK.2 V/3 V 2. CL = 20 pF TEST CONDITIONS VCC 2.MI(USCI) + tVALID.2 V 3V 50 50 150 100 VCC MIN TYP MAX fSYSTEM 1 600 600 UNIT MHz MHz ns The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.MO(USCI) + tSU. 54 Submit Documentation Feedback Copyright © 2007–2011.MO (1) USCI input clock frequency SOMI input data setup time SOMI input data hold time SIMO output data valid time UCLK edge to SIMO valid.2 V/3 V 2.2 V/3 V 2.SO (1) STE lead time.MI(Master) + tVALID.ti. Last clock to STE high STE access time. CL = 20 pF TEST CONDITIONS SMCLK.2 V 3V 110 75 0 0 30 20 VCC MIN MAX fSYSTEM UNIT MHz ns ns ns fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID.2 V 3V 2.LAG tSTE.SO(USCI)).

MI SOMI tVALID.MSP430F261x MSP430F241x www.MI tHD.MO SIMO Figure 27.MI SOMI tHD.MI tVALID. CKPH = 1 Copyright © 2007–2011. SPI Master Mode.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU.ti. SPI Master Mode. Texas Instruments Incorporated Submit Documentation Feedback 55 . CKPH = 0 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU.MO SIMO Figure 28.

ACC SOMI tVALID.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ACC SOMI tVALID.SO tSTE.LAG tSTE.ti.SI SIMO tSTE.DIS Figure 30. CKPH = 0 tSTE. Texas Instruments Incorporated . SPI Slave Mode. CKPH = 1 56 Submit Documentation Feedback Copyright © 2007–2011.com tSTE.SI tHD. SPI Slave Mode.LEAD STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU.LAG tSTE.SI tSTE.LEAD STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLO/HI tLO/HI tSU.SI SIMO tHD.DIS Figure 29.SO tSTE.

2 V/3 V 2.ti.DAT tHD. Texas Instruments Incorporated Submit Documentation Feedback 57 .2 V/3 V 2.MSP430F261x MSP430F241x www.6 0 250 4 50 50 150 100 400 600 600 ns tHD.2 V/3 V 2.STA tSU.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 31) PARAMETER fUSCI fSCL tHD.STA VCC MIN TYP MAX fSYSTEM UNIT MHz kHz µs µs ns ns µs 0 4 0.DAT tSU.STO tSP USCI input clock frequency SCL clock frequency Hold time (repeated) START Setup time for a repeated START Data hold time Data setup time Setup time for STOP Pulse width of spikes suppressed by input filter fSCL ≤ 100 kHz fSCL > 100 kHz fSCL ≤ 100 kHz fSCL > 100 kHz TEST CONDITIONS Internal: SMCLK. ACLK External: UCLK Duty cycle = 50% ± 10% 2.2 V/3 V 2.STA tHD.DAT tSP tSU.STA tHD. I2C Mode Timing Copyright © 2007–2011.STO Figure 31.2 V/3 V 2.DAT tSU.7 0.2 V/3 V 2.STA SDA 1/fSCL SCL tSU.2 V 3V tSU.6 4.

No load at P2 3/CA0/TA1 and P2.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. CARSEL = 0. Overdrive 10 mV. Texas Instruments Incorporated .2 V 3V 2. CAREF = 0 CAON = 1. low to high and high to low (3) (see Figure 32 and Figure 33) PCA0 = 1. If CAON is set at the same time.1 0. ÷ VCC No load at P2 3/CA0/TA1 and P2.5 0.2 V 3V 2.com Comparator_A+ (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER I(DD) I(Refladder/RefDiode) VIC V(Ref025) V(Ref050) V(RefVT) V(offset) Vhys Common-mode input voltage range (Voltage at 0. Overdrive 10 mV. a settling time of up to 300 ns is added to the response time.2 V/3 V 2.2 V 3V 0 0. CAREF = 1. 58 Submit Documentation Feedback Copyright © 2007–2011. CARSEL = 1. No load at P2 3/CA0/TA1 and P2.8 2.5 540 550 30 1.23 0. CAREF = 3. Without filter: CAF = 0 TA = 25°C. CAREF = 1/2/3.24 0. CARSEL = 1. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.48 480 490 MIN TYP 25 45 30 45 MAX 40 60 50 71 VCC .25 0. CARSEL = 1.2 mV mV mV ns µs UNIT µA µA V (Voltage at 0.y) specification.25 VCC node) ÷ VCC TEST CONDITIONS CAON = 1.9 1. The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step and with Comparator_A+ already enabled (CAON = 1).ti.2 V 3V 2.4/CA1/TA2.9 0. The two successive measurements are then summed together.4/CA1/TA2 See Figure 35 and Figure 36 Offset voltage (2) Input hysteresis Response time.47 390 400 -30 0 80 70 1. No load at P2 3/CA0/TA1 and P2.4/CA1/TA2 VCC 2.2 V/3 V 2. CAREF = 2.2 V 3V 2.4/CA1/TA2 CAON = 1 PCA0 = 1.4 300 240 2.7 165 120 1.2 V/3 V 2. CARSEL = 0.5 VCC node) PCA0 = 1. TA = 85°C t(response) (1) (2) (3) The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.2 V/3 V CAON = 1 TA = 25°C.4 0. With filter: CAF = 1 2.2 V/3 V 2.

Comparator_A+ Short Resistance Test Condition Copyright © 2007–2011. Comparator_A+ Module Block Diagram Overdrive V− VCAOUT 400 mV V+ t (response) Figure 33. Texas Instruments Incorporated Submit Documentation Feedback 59 .0 µs Figure 32. Overdrive Definition CASHORT CA0 1 VIN + − Comparator_A+ CASHORT = 1 IOUT = 10µA CA1 Figure 34.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 0V 0 VCC 1 CAON CAF Low Pass Filter + _ 0 1 0 1 To Internal Modules V+ V− CAOUT Set CAIFG Flag τ ≈ 2.MSP430F261x MSP430F241x www.

00 VCC = 3. 60 Submit Documentation Feedback Copyright © 2007–2011.6V 1. Short Resistance − kW VCC = 1.6 0.2 0.0 VIN/VCC − Normalized Input Voltage − V/V Figure 37.com Typical Characteristics.2V 10.8V VCC = 2. SHORT RESISTANCE vs VIN/VCC 100.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.2 V V(REFVT) − Reference Volts −mV 600 Typical 550 600 Typical 550 500 500 450 450 400 −45 −25 −5 15 35 55 75 95 400 −45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 35.0V VCC = 3.00 0.4 0.ti.2 V) 650 VCC = 2.00 Figure 36. Comparator_A+ V(RefVT) vs TEMPERATURE (VCC = 3 V) 650 VCC = 3 V V(REFVT) − Reference Volts −mV V(RefVT) vs TEMPERATURE (VCC = 2. Texas Instruments Incorporated .8 1.0 0.

x/Ax parameter. SHT1 = 0.7/A7 terminals.7 0. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.≤ VAVCC (2) (3) (4) VCC MIN 0 MAX 1. Lower differential reference voltage levels may be applied with reduced accuracy requirements.x/Ax ≤ V(AVCC) fADC12CLK = 5 MHz. The accuracy limits the minimum positive external reference voltage. REFON = 1. limits verified by design. is also the dynamic load for an external reference during conversion. 0 ≤ × ≤ 7. P6.2 TYP MAX 3. The analog input voltage range must be within the selected reference voltage range VR+ to VR.8 0.ti.for valid conversion results. The input capacitance. Higher reference voltage levels may be applied with reduced accuracy requirements. (1) 12-Bit ADC External Reference PARAMETER VeREF+ VREF-/VeREF(VeREF+ VREF-/VeREF-) IVeREF+ IVREF-/VeREF(1) (2) (3) (4) over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VeREF+ > VREF-/VeREFVeREF+ > VREF-/VeREFVeREF+ > VREF-/VeREF0 V ≤ VeREF+ ≤ VAVCC 0 V ≤ VeREF. V(AVSS) ≤ VP6. ADC12DIV = 0 fADC12CLK = 5 MHz.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 (1) 12-Bit ADC Power Supply and Input Range Conditions PARAMETER AVCC Analog supply voltage TEST CONDITIONS over recommended operating free-air temperature range (unless otherwise noted) VCC MIN 2. unless a conversion is active.5 VAVCC 0.2 V/3 V 2.8 1 0.7 0. Not production tested. REFON = 1.x = 1. The internal reference supply current is not included in current consumption parameter IADC12. Consumption is independent of the ADC12ON control bit. REF2_5V = 0 Only one terminal can be selected at one time. The accuracy limits the maximum negative external reference voltage. P6Sel. Analog inputs selected in ADC12MCTLx register. ADC12ON = 0.6 UNIT V AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V All P6.7 40 2000 V IADC12 mA mA mA pF Ω IREF+ Operating supply current into AVCC terminal (4) CI RI (1) (2) (3) (4) (5) Input capacitance (5) (5) Input MUX ON resistance The leakage current is defined in the leakage current table with P6. Texas Instruments Incorporated Submit Documentation Feedback 61 . The accuracy limits minimum external differential reference voltage.2 V 3V V(P6.2 V 3V 3V 2. CI.65 0.x/Ax) Analog input voltage range (2) Operating supply current into AVCC terminal (3) 0 0.5 0.2 V 3V 2.4 VAVCC 1.5 0.MSP430F261x MSP430F241x www. ADC12ON = 1. Copyright © 2007–2011. Lower reference voltage levels may be applied with reduced accuracy requirements.x/Ax 0 V ≤ VAx ≤ VAVCC 2.2 V/3 V ±1 ±1 The external reference is used during conversion to charge and discharge the capacitance array. The internal reference current is supplied via terminal AVCC.4 VAVCC 2. SHT0 = 0. REFON = 0. ADC12ON = 0.2 UNIT V V V µA µA Positive external reference voltage input Negative external reference voltage input Differential external reference voltage input Static leakage current Static leakage current 1. The REFON bit enables settling of the built-in reference before starting an A/D conversion. REF2_5V = 1 fADC12CLK = 5 MHz.0/A0 to P6.

ax ≈ 0.2 V 3V IVREF+ = 500 µA ± 100 µA.5 V. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF-/VeREF.2 V 2.5 mA. CVREF+ = 5 µF. Analog input voltage ≈ 0.5 × VREF+. IVREF+max ≤ IVREF+ ≤ IVREF+min REF2_5V = 0 for 1.44 1.com 12-Bit ADC Built-In Reference over recommended operating free-air temperature range (unless otherwise noted) PARAMETER Positive built-in reference voltage output TEST CONDITIONS REF2_5V = 1 for 2. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+ 62 Submit Documentation Feedback Copyright © 2007–2011.6 2.66 x CVREF+ [ms] with C VREF+ in µF 1 µF 0 1 ms 10 ms 100 ms t REFON Figure 38.25 V. Analog input voltage ≈ 1.2 2.01 -0.2 V 17 ms (1) (2) (3) (4) Not production tested. VREF+ terminal (2) Capacitance at pin VREF+ (3) Temperature coefficient of built-in reference (2) Settle time of internal reference voltage (see Figure 38 ) (4) (2) 3V 2. positive built-in reference active IVREF+ Load current out of VREF+terminal mA IL(VREF)+ Load-current regulation. VREF+ = 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor.56 1.42 2.64 1.5 V.5 1.5 LSB.2 V/3 V 2. -0. CVREF+ 100 µF 10 µF t REFON ≈ .2 V 3V 3V TA -40°C to 85°C 105°C -40°C to 85°C 105°C VCC 3V 2. VAVCC = 2. Error of conversion result ≤ 1 LSB REFON = 1. REF2_5V = 1 IVREF+ = 100 µA → 900 µA.5 MAX 2.37 1.and AVSS: 10 µF tantalum and 100 nF ceramic. -1 mA ≤ IVREF+ ≤ IVREF+min 2.57 V UNIT VREF+ AVCC(min) AVCC minimum voltage.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. REF2_5V = 0 IVREF+ = 500 µA ± 100 µA. VREF+ terminal (1) LSB IDL(VREF) + CVREF+ TREF+ Load current regulation. 0 mA ≤ IVREF+ ≤ IVREF+max IVREF+ is a constant in the range of 0 mA ≤ IVREF+ ≤ 1 mA IVREF+ = 0. Texas Instruments Incorporated .5 -1 ±2 ±2 ±2 LSB V NOM 2.8 2.75 V.9 0. The settling time depends on the external capacitive load.2 V/3 V 5 10 20 ns µF ±100 ppm/°C tREFON 2. Not production tested.5 V. IVREF+max ≤ IVREF+ ≤ IVREF+min REF2_5V = 1. IVREF+max ≤ IVREF+ ≤ IVREF+min REF2_5V = 0.5 mA ≤ IVREF+ ≤ IVREF+min REF2_5V = 1.ti. limits verified by design.5 2. CVREF+ = 10 µF.01 0. limits characterized.5 1.4 2.2 V/3 V MIN 2. The condition is that the error in a conversion started after tREFON is less than ±0.

ti. Texas Instruments Incorporated Submit Documentation Feedback 63 . Supply Voltage and Reference Voltage Design VREF-/VeREF.MSP430F261x MSP430F241x www.External Supply From Power Supply DVCC + − DVSS 10 µ F 100 nF AVCC AVSS 10 µ F 100 nF VREF+ or V eREF+ + − Apply External Reference [V eREF+] or Use Internal Reference [V REF+] MSP430F261x MSP430F241x + − 10 µ F 100 nF Reference Is Internally Switched to A VSS VREF−/VeREF− Figure 40.= AVSS.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 From Power Supply DVCC + − DVSS 10 µ F 100 nF AVCC AVSS 10 µ F 100 nF VREF+ or V eREF+ + − Apply External Reference [VeREF+] or Use Internal Reference [VREF+] MSP430F261x MSP430F241x + − 10 µ F + − 10 µ F 100 nF 100 nF Apply External Reference VREF−/VeREF− Figure 39. Supply Voltage and Reference Voltage Design VREF-/VeREF. Internally Connected Copyright © 2007–2011.

Approximately ten Tau (τ) are needed to get an error of less than ±0.1 ±2 MIN TYP MAX ±2 ±1.VREF-/VeREF-).2 V/3 V 2.7 MHz to 6.VREF-/VeREF-) min ≤ (VeREF+ .ti.VREF-/VeREF-) min ≤ (VeREF+ .VREF-/VeREF.6 V < (VeREF+ .3 MHz 6.2 V/3 V 2. fADC12CLK = fADC12OSC CVREF+ ≥ 5 µF. MCLK. CI = 30 pF.2 V/3 V MIN 0. or SMCLK.) min ≤ (VeREF+ -VREF-/VeREF-). ADC12SSEL ≠ 0 See (2) VCC 2.RI = 1000 Ω. RS = external source resistance 12-Bit ADC Linearity Parameters over recommended operating free-air temperature range (unless otherwise noted) PARAMETER EI ED EO EG ET Integral linearity error TEST CONDITIONS 1.2 V/3 V 2.06 TYP MAX UNIT 5 5 6.3 MHz 3.51 13 × ADC12DIV × 1/fADC12CLK 100 µs µs ns ns tADC12ON tSample (1) (2) (3) Turn-on settling time of the ADC (1) Sampling time (1) RS = 400 Ω.7 2. Internal oscillator.VREF-/VeREF-).VREF-/VeREF-) min ≤ 1. The reference and input signal are already settled.2 V/3 V ±2 ±1. Texas Instruments Incorporated .VREF-/VeREF-) min ≤ (VeREF+ . CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) 64 Submit Documentation Feedback Copyright © 2007–2011.2 V/3 V 2.2 V 1220 1400 Limits verified by design The condition is that the error in a conversion started after tADC12ON is less than ±0. error CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) Offset error Gain error Total unadjusted error (VeREF+ . CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) (VeREF+ .45 3.VREF-/VeREF-) min ≤ VAVCC VCC 2. fADC12OSC = 3.2 V/3 V 2.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.7 ±1 ±4 ±2 ±5 UNIT LSB LSB LSB LSB LSB Differential linearity (VeREF+ . where n = ADC resolution = 12. τ = [RS +RI] × CI (3) 3V 2.4 V ≤ (VeREF+ .com 12-Bit ADC Timing Parameters over recommended operating free-air temperature range (unless otherwise noted) PARAMETER fADC12CLK fADC12OSC Internal ADC12 oscillator TEST CONDITIONS For specified performance of ADC12 linearity parameters ADC12DIV = 0.VREF-/VeREF-).6 V 1.3 MHz tCONVERT Conversion time External fADC12CLK from ACLK.5 LSB. CVREF+ = 10 µF (tantalum) and 100 nF (ceramic) (VeREF+ .2 V/3 V 2.5 LSB: tSample = ln(2n+1) × (RS + RI) × CI + 800 ns. Internal impedance of source RS < 100 Ω.

AVSS = DVSS = 0 V DAC12AMPx = 2. TA = 0°C ADC12ON = 1. The VMID is used during sampling. INCH = 0Bh. DAC12_xDAT = 0x0800.2 V 3V 2. Error of conversion result ≤ 1 LSB µA V tVMID(sample) (1) (2) (3) (4) (5) (6) The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1). The sample time required includes the sensor-on time tSENSOR(on) No additional current is needed.55 3.1 ± 0.5 ± 0.MSP430F261x MSP430F241x www. Limits characterized The typical equivalent impedance of the sensor is 51 kΩ. see Reference Input specifications. The temperature sensor offset can be as much as ±20°C. VMID is ~0. VREF = 1.2 V 3V 2.2 V/3 V IDD Supply current.55 MAX 120 160 UNIT µA Operating supply current into AVCC terminal (1) VSENSOR mV mV/°C TCSENSOR (3) tSENSOR(sample) (3) Sample time required if channel 10 is selected (4) ADC12ON = 1. Current into reference terminals not included.04 1. no additional on time is needed. ΔAVCC = 100 mV DAC12_xDAT = 800h. VeREF+ = VREF+= AVCC DAC12AMPx = 7. or (ADC12ON = 1 AND INCH = 0Ah and sample signal is high). DAC12_xDAT = 0x0800.04 µs IVMID VMID Current into divider ADC12ON = 1. DAC12IR = 1. VeREF+ = VREF+ = AVCC DAC12_xDAT = 800h. single DAC channel (1) (2) 2.2 V 3V 2. INCH = 0Ah. DAC12IR = 1.2 V 3V 2. Therefore it includes the constant current through the sensor and the reference. PSRR = 20 × log(ΔAVCC/ΔVDAC12_xOUT) VREF is applied externally. DAC12IR = 1.2 V/3 V 2. INCH = 0Ah. INCH = 0Bh. DAC12IR = 0.5 1400 1220 ns 1. ΔAVCC = 100 mV 2. The internal reference is not used. Texas Instruments Incorporated Submit Documentation Feedback 65 . INCH = 0Bh at channel 11 (5) AVCC divider at channel 11 Sample time required if channel 11 is selected (6) ADC12ON = 1.2 V 3V 700 70 1500 PSRR Power-supply rejection ratio (3) (4) dB 70 (1) (2) (3) (4) No load at the output pin. A single-point calibration is recommended to minimize the offset error of the built-in temperature sensor. TA = 25°C ADC12ON = 1. VREF = 1. DAC12_xDAT = 0x0800 DAC12AMPx = 2.1 1. INCH = 0Ah.5 V. 12-Bit DAC Supply Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER AVCC Analog supply voltage TEST CONDITIONS AVCC = DVCC. If DAC12IR = 1 current flows through the input divider.5 × VAVCC ADC12ON = 1.ti.2 V 3V 2.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 12-Bit ADC Temperature Sensor and Built-In VMID over recommended operating free-air temperature range (unless otherwise noted) PARAMETER ISENSOR (2) (3) TEST CONDITIONS REFON = 0.2 V/3 V -40°C to 85°C 105°C VCC TA MIN 2.2 50 69 50 TYP MAX 3.2 V/3 V 200 440 UNIT V 2. Copyright © 2007–2011. ADC12ON = 1. The on-time tVMID(on) is included in the sampling time tVMID(sample). DAC12_0 or DAC12_1. INCH = 0Ah VCC 2.5 V or 2. VeREF+ = VREF+ = AVCC DAC12AMPx = 5. DAC12_xDAT = 0x0800. assuming that the control bits for the shared pins are set properly.2 V 3V 2. Error of conversion result ≤ 1 LSB 30 30 NA (5) NA (5) 1.5 V.6 110 150 130 µA 2.2 V 3V MIN TYP 40 60 986 986 3.

5 V.5 V. DAC12IR = 1 VREF = 1.ti.0 LSB INL DNL Differential nonlinearity VREF = 1.5 V. 5.2 V 3V 2. DAC12IR = 1 VREF = 2. Offset calibration is triggered setting bit DAC12CALON.2 V/3 V 32 6 ms µV/C % FSR ppm of FSR/°C ±2. DAC12AMPx = 7. DAC12IR = 1 (1) VCC MIN 12 TYP MAX UNIT bits 2.0 LSB Offset voltage without calibration (1) (2) EO Offset voltage with calibration (1) (2) Offset error temperature coefficient (3) Gain error (3) Gain temperature coefficient (3) ±21 mV 2. DAC12IR = 1 VREF = 2. 7 (1) (2) (3) (4) Parameters calculated from the best-fit curve from 0x0A to 0xFFF. DAC12IR = 1 VREF = 2. 5 DAC12AMPx = 4. DAC12IR = 1.2 V 3V ±2.5 V VREF = 2. Texas Instruments Incorporated . DAC12AMPx = 7. 4. DAC12AMPx = 7. Parameters calculated from the best-fit curve from 0x0A to 0xFFF.2 V 3V 2.5 V. DAC12IR = 1. DAC12AMPx = 7. DAC12AMPx = 7.2 V 3V 2.5 dE(O)/dT EG dE(G)/dT VREF = 1. The best-fit curve method is used to deliver coefficients "a" and "b" of the first-order equation: y = a + b × x.2 V 3V 2. 6. The best-fit curve method is used to deliver coefficients "a" and "b" of the first-order equation: y = a + b × x.5 V.2 V/3 V 30 ±3. DAC12IR = 1 ±0. DAC12AMPx = 7.5 V. 7}.com 12-Bit DAC Linearity Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Resolution Integral nonlinearity (1) TEST CONDITIONS 12-bit monotonic VREF = 1.5 V. 3. DAC12AMPx = 7.5 V 2.2 V/3 V DAC12AMPx = 2 tOffset_Cal Time for offset calibration (4) DAC12AMPx = 3. The offset calibration can be done if DAC12AMPx = {2. The DAC12 module should be configured prior to initiating calibration.50 10 100 2.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. DAC12AMPx = 7. Linearity Test Load Conditions and Gain/Offset Definition 66 Submit Documentation Feedback Copyright © 2007–2011. 1}.5 V. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT. The offset calibration works on the output operational amplifier.0 ±8.4 ±1. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT. DAC12IR = 1 VREF = 2. 6. The output operational amplifier is switched off with DAC12AMPx= {0. DAC V OUT DAC Output RLoad = AV CC 2 CLoad = 100pF Offset Error Positive Negative Gain Error DAC Code VR+ Ideal transfer function Figure 41. DAC12IR = 1 VREF = 1. Port activity during calibration may affect accuracy and is not recommended.

5 1. VREF = 1.0 −0.2 V. Copyright © 2007–2011. Texas Instruments Incorporated Submit Documentation Feedback 67 . TYPICAL DNL ERROR vs DIGITAL INPUT DATA 2.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Typical Characteristics . Linearity Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL INL ERROR vs DIGITAL INPUT DATA 4 3 INL − Integral Nonlinearity Error − LSB 2 1 0 −1 −2 −3 −4 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT − Digital Code VCC = 2.5V DAC12AMPx = 7 DAC12IR = 1 Figure 43.5 −2.5V DAC12AMPx = 7 DAC12IR = 1 Figure 42.0 −1.5 −1.MSP430F261x MSP430F241x www.0 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT − Digital Code VCC = 2.5 0. VREF = 1.0 DNL − Differential Nonlinearity Error − LSB 1.0 0.2 V.ti.12-Bit DAC.

Texas Instruments Incorporated .MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.2 UNIT V MΩ For a full-scale output. the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance. VO/P(DAC12) = AVCC.VE(O)] / [3 × (1 + EG)]. DAC12AMPx = 7. RO/P(DAC12_x) Max AV CC 2 O/P(DAC12_x) CLoad= 100pF Min 0. DAC12_x Output Resistance Tests 12-Bit DAC Reference Input Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VeREF+ Reference input voltage range TEST CONDITIONS DAC12IR = 0 (1) (2) DAC12IR = 1 (3) (4) DAC12_0 IR = DAC12_1 IR = 0 Ri(VREF+). DAC12IR = 1. DAC12_xDAT = 0FFFh RLoad = 3 kΩ.ti. DAC12_xDAT = 0FFFh. VeREF+ = AVCC.2 V/3 V Ω 1 4 ILoad DAC12 RLoad AV CC Figure 44. For a full-scale output.005 UNIT AVCC V VO Output voltage range (1) (see Figure 44) 2.com 12-Bit DAC Output Specifications over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS No Load. DAC12AMPx = 7 (1) Data is valid after the offset calibration of the output amplifier. DAC12_xDAT = 0h.VE(O)] / (1 + EG). DAC12_1 IR = 1 DAC12_0 IR = DAC12_1 IR = 1. DAC12_xDAT = 0FFFh. DAC12AMPx = 7.2 V/3 V VCC 2. DAC12_xDAT = 0h RO/P(DAC12) Output resistance (see Figure 44) RLoad = 3 kΩ. Ri(VeREF+) Reference input resistance DAC12_0 IR = 1. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels.2 V 3V -0.2 V/3 V 0 AVCC 0. DAC12AMPx = 7 CL(DAC12) IL(DAC12) Maximum DAC12 load capacitance Maximum DAC12 load current RLoad = 3 kΩ. DAC12AMPx = 7 No Load.1 AVCC 100 0.5 1 250 250 pF mA 2. DAC12_1 IR = 0 DAC12_0 IR = 0.13 2.2 V/3 V 20 40 20 48 24 56 kΩ 28 MIN TYP AVCC / 3 AVCC MAX AVCC + 0.2 AVCC + 0.3V VOUT VCC MIN 0 AVCC 0. DAC12IR = 1. DAC12IR = 1. VO/P(DAC12) = 0 V.3 AV CC −0. Submit Documentation Feedback Copyright © 2007–2011. VeREF+ = AVCC.5 -1 150 150 0. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC . the reference input voltage can be as high as the maximum output voltage swing (AVCC). DAC12AMPx = 7 RLoad = 3 kΩ. the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). DAC12_0 SREFx = DAC12_1 SREFx (5) (1) (2) (3) (4) (5) 68 2. VeREF+ = AVCC.3 V.3 V < VO/P(DAC12) < AVCC .05 TYP MAX 0. DAC12AMPx = 7 RLoad = 3 kΩ. DAC12IR = 1. DAC12_xDAT = 0h. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC .2 V/3 V 2. VeREF+ = AVCC. 0.0.

35 1. Slew rate applies to output voltage steps ≥ 200 mV. 5 DAC12AMPx = 4. full scale DAC12_xDAT = 80h → F7Fh → 80h DAC12AMPx = 3. DAC12_xDAT = 800h DAC12AMPx = 7. Texas Instruments Incorporated Submit Documentation Feedback 69 .2 V/3 V 2.MSP430F261x MSP430F241x www.2 V/3 V tS(C-C) Settling time.5 LSB (1) (see Figure 45) DAC12_xDAT = 80h → F7Fh → 80h DAC12_xDAT = 3F8h → 408h → 3F8h BF8h → C08h → BF8h DAC12_xDAT = 80h → F7Fh → 80h DAC12AMPx = 0 → {2. Conversion 1 DAC Output ILoad RLoad = 3 kΩ AV CC 2 RO/P(DAC12. DAC12SREFx = 2. RLoad = 3 kΩ. 4}.2 V/3 V 0. 5 DAC12AMPx = 4.12 0. DAC12SREFx = 2.2 V/3 V 40 180 550 -80 2.2 V/3 V VCC MIN TYP 60 15 6 100 40 15 5 2 1 0.ti. ErrorV(O) < ±0. No load. RLoad = 3 kΩ. DAC12_xDAT = 800h DAC12_0DAT = 800h. full scale DAC12AMPx = 3.5 V. 7 DAC12AMPx = 2 DAC12AMPx = 3. Duty cycle = 50% DAC12_0DAT = 80h ↔ F7Fh.x) CLoad = 100pF +/− 1/2 LSB VOUT Glitch Energy Conversion 2 +/− 1/2 LSB Conversion 3 tsettleLH tsettleHL Figure 45. 6}. DAC12SREFx = 2. Settling Time and Glitch Energy Testing Copyright © 2007–2011. DAC12IR = 1 (see Figure 45 and Figure 46). 6. 6. fDAC12_0OUT = 10 kHz. DAC12_1DAT = 800h. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER tON DAC12 on-time TEST CONDITIONS DAC12_xDAT = 800h.7 600 150 30 nV-s V/µs µs MAX 120 30 12 200 80 30 µs µs UNIT BW-3dB Channel-tochannel crosstalk (1) (see Figure 48) (1) (2) RLoad and CLoad are connected to AVSS (not AVCC/2) in Figure 45. 7 DAC12AMPx = 2 Glitch energy. VDC = 1. 6.7 2.5 2. 3. VAC = 0.05 0. DAC12IR = 1.1 VPP (see Figure 47) DAC12AMPx = {2.2 V/3 V -80 dB kHz 2. 5 DAC12AMPx = 4. fDAC12_1OUT = 10 kHz. Duty cycle = 50% 2.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 12-Bit DAC Dynamic Specifications VREF = VCC. DAC12_1DAT = 80h ↔ F7Fh. 4} DAC12AMPx = 0 → {5. DAC12_xDAT = 800h DAC12AMPx = {5. DAC12IR = 1. DAC12IR = 1. code to code 2. 6. No load. 3. 7 DAC12AMPx = 2 SR Slew rate (2) DAC12AMPx = 3. 7 3-dB bandwidth. 6} DAC12AMPx = 0 → 7 DAC12AMPx = 2 tS(FS) Settling time. 5 DAC12AMPx = 4.2 V/3 V 2.

ti. Texas Instruments Incorporated .com Conversion 1 VOUT Conversion 2 Conversion 3 90% 90% 10% 10% tSRLH tSRHL Figure 46.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. Slew Rate Testing RLoad = 3 kΩ AV CC 2 CLoad = 100pF Ve REF+ DAC12_x AC DC ILoad DACx Figure 47. Test Conditions for 3-dB Bandwidth Specification RLoad AV CC 2 CLoad= 100pF VREF+ ILoad Ve DAC12_1 DAC1 CLoad= 100pF RLoad AV CC 2 V DAC12_yOUT V DAC12_xOUT fToggle DAC12_xDAT 080h V OUT 7F7h 080h 7F7h 080h ILoad DAC12_0 DAC0 Figure 48. Crosstalk Test Conditions 70 Submit Documentation Feedback Copyright © 2007–2011.

ti.2 V/3.2 257 TYP MAX 3.2 V/3. TCK. TMS. tBlock. Texas Instruments Incorporated Submit Documentation Feedback 71 . 0 1-63 End TEST CONDITIONS VCC MIN 2.2 V 3V 2.6 V 2. and TDI/TCLK (2) VCC 2. and TDI/TCLK pullup resistors are implemented in all versions. This parameter applies to all programming methods: individual word/byte write and block write modes.2 V/3.MSP430F261x MSP430F241x www. TCK. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(PGM/ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock. and JTAG is switched to bypass mode.6 476 UNIT V kHz mA mA ms ms cycles years tFTG tFTG tFTG tFTG tFTG tFTG Program and erase supply voltage Flash timing generator frequency Supply current from VCC during program Supply current from VCC during erase Cumulative program time (1) 2. no further access to the JTAG/Test and emulation feature is possible.6 V 2.6 V 2. JTAG Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER fTCK RInternal (1) (2) TCK input frequency (1) Internal pullup resistance on TMS.5 6 7 100 1 MAX UNIT V V mA ms Once the fuse is blown.2 V/3 V MIN 0 0 25 60 TYP MAX 5 10 90 UNIT MHz kΩ fTCK may be restricted to meet the timing requirements of the module selected.6 V TJ = 25°C (2) (2) (2) (2) (2) (2) 1 1 20 104 100 30 25 18 6 10593 4819 105 5 7 10 Cumulative mass erase time Program/erase endurance Data retention duration Word or byte program time Block program time for first byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time tMass Erase tSeg Erase (1) (2) The cumulative program time must not be exceeded when writing to a 64-byte flash block.2 V/3. RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage (1) TEST CONDITIONS CPU halted MIN 1. JTAG Fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(FB) VFB IFB tFB (1) Supply voltage during fuse-blow condition Voltage level on TEST for fuse blow Supply current into TEST during fuse blow Time to blow fuse TEST CONDITIONS TA = 25°C MIN 2.6 MAX UNIT V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. Copyright © 2007–2011. No program execution should happen during this supply voltage condition. tBlock.

0/TACLK/CAOUT P1.x 0 1 P1. Input/Output With Schmitt Trigger P1REN.x P1IES.1/TA0 P1.5/TA0 P1.x Interrupt Edge Select 72 Submit Documentation Feedback Copyright © 2007–2011.6/TA1 P1.3/TA2 P1.x Q Set P1IFG. Texas Instruments Incorporated .4/SMCLK P1.x Module X OUT P1SEL.x P1IRQ.ti.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.0 to P1.com APPLICATION INFORMATION Port P1 (P1.x EN P1SEL.2/TA1 P1.x Pad Logic DVSS DVCC P1DIR.x P1IN.7).7/TA2 EN Module X IN D P1IE.x 0 1 Direction 0: Input 1: Output 0 1 1 P1OUT.

7/TA2 4 5 6 7 P1.TA0 P1.4 (I/O) SMCLK P1.0 to P1.TACLK CAOUT P1. O: 1 0 1 I: 0.CCI1A Timer_A3.7) Pin Functions PIN NAME (P1.5 (I/O) Timer_A3. O: 1 0 1 I: 0.CCI2A Timer_A3.0/TACLK/CAOUT 0 Timer_A3.0 (I/O) P1. O: 1 1 P1SEL.6 (I/O) Timer_A3.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Table 15.MSP430F261x MSP430F241x www. Port P1 (P1.TA1 P1.5/TA0 P1.4/SMCLK P1.TA1 P1. Texas Instruments Incorporated Submit Documentation Feedback 73 .x I: 0.6/TA1 P1. O: 1 1 I: 0.TA2 FUNCTION CONTROL BITS / SIGNALS P1DIR.TA2 P1.1 (I/O) P1.x) x P1. O: 1 1 I: 0.2/TA1 2 Timer_A3. O: 1 1 I: 0.7 (I/O) Timer_A3.CCI0A Timer_A3.1/TA0 1 Timer_A3. O: 1 0 1 I: 0.x 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 Copyright © 2007–2011.ti.2 (I/O) P1.3 (I/O) P1.TA0 P1.3/TA2 3 Timer_A3. O: 1 0 1 I: 0.

3/CA0/TA1 P2.0/ACLK/CA2 P2.0 to P2.x P2IN.x Interrupt Edge Select 74 Submit Documentation Feedback Copyright © 2007–2011. Texas Instruments Incorporated . and P2.x P2SEL.x DVSS DVCC P2DIR.ti.2/CAOUT/TA0/CA4 P2.x P2IES.6/ADC12CLK/DMAE0/CA6 P2.x 0 1 Bus Keeper EN EN P2.x Module X OUT P2SEL. Input/Output With Schmitt Trigger Pad Logic To Comparator_A From Comparator_A CAPD.x P2IRQ.7).6.1/TAINCLK/CA3 P2.x P2REN.4.7/TA0/CA7 Module X IN D P2IE.4/CA1/TA2 P2.x 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.com Port P2 (P2.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. P2.x EN Q Set P2IFG.

Texas Instruments Incorporated Submit Documentation Feedback 75 .6/ADC12CLK/ DMAE0 (2)/CA6 6 ADC12CLK DMAE0 CA6 P2.TA2 CA1 P2.7/TA0/CA7 7 Timer_A3.INCLK DVSS CA3 P2.x 0 1 X 0 1 1 X 0 1 1 X 0 1 X 0 X 1 0 1 1 X 0 1 X Copyright © 2007–2011.x) x P2.3 (I/O) P2.x 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 P2DIR.7) Pin Functions PIN NAME (P2.3/CA0/TA1 3 Timer_A3.CCI0B CA4 P2. O: 1 1 0 X I: 0. O: 1 1 0 X I: 0.0 (I/O) P2.1 (I/O) P2.4 (I/O) P2. P2.2/CAOUT/TA0/CA4 2 CAOUT Timer_A3.x I: 0.0/ACLK/CA2 0 ACLK CA2 P2. Port P2 (P2.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Table 16.6.TA0 CA7 (1) (2) X = Don't care MSP430F261x devices only FUNCTION CONTROL BITS / SIGNALS (1) CAPD.4/CA1/TA2 4 Timer_A3. O: 1 1 X I: 0.ti.7 (I/O) P2. and P2.4.MSP430F261x MSP430F241x www. O: 1 1 X I: 0.TA1 CA0 P2.0 to P2. O: 1 1 X P2SEL. O: 1 1 X I: 0.1/TAINCLK/CA3 1 Timer_A3. O: 1 0 1 X I: 0.2 (I/O) P2.6 (I/O) P2.

O: 1 X 1 X P2SEL.5 0 1 Direction 0: Input 1: Output 0 1 1 P2OUT.com Port P2 (P2.5 I: 0.5 P2IES. Texas Instruments Incorporated .5 0 X 1 X 76 Submit Documentation Feedback Copyright © 2007–2011. (2) FUNCTION CONTROL BITS / SIGNALS (1) CAPD 0 0 0 1 or selected DCOR 0 1 0 0 P2DIR. it is connected to an external resistor.5) Pin Functions PIN NAME (P2.ti.5).5 Interrupt Edge Select Table 17.5 EN Q Set P2IRQ.5/ROSC/CA5 Bus Keeper EN EN Module X IN D P2IE. Input/Output With Schmitt Trigger Pad Logic To Comparator From Comparator CAPD.x) x P2.5 To DCO in DCO DCOR P2REN.x P2IN.5 (I/O) P2.5/ROSC/CA5 5 ROSC DVSS CA5 (1) (2) X = Don't care If ROSC is used.5 0 1 P2.5 DVSS DVCC P2DIR.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. Port P2 (P2.5 Module X OUT P2SEL.5 P2SEL.

5/UCA0RXD/UCA0SOMI P3.7/UCA1RXD/UCA1SOMI EN Module X IN D Table 18.6/UCA1TXD/ UCA1SIMO P3.2/UCB0SOMI/UCB0SCL P3.3 (I/O) UCB0CLK/UCA0STE P3.7).0 to P3.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Port P3 (P3.1/UCB0SIMO/ UCB0SDA P3.4/UCA0TXD/ UCA0SIMO P3.0 to P3. Input/Output With Schmitt Trigger Pad Logic P3REN.1 (I/O) UCB0SIMO/UCB0SDA (4) (5) P3.2/UCB0SOMI/ UCB0SCL P3.0/UCB0STE/ UCA0CLK P3. Texas Instruments Incorporated Submit Documentation Feedback 77 .0 (I/O) UCB0STE/UCA0CLK (2) (3) P3.x P3IN.x Module X OUT P3SEL.1/UCB0SIMO/UCB0SDA P3. The pin direction is controlled by the USCI module.4 (I/O) UCA0TXD/UCA0SIMO (4) P3.x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X = Don't care The pin direction is controlled by the USCI module.5/UCA0RXD/ UCA0SOMI P3.ti. Copyright © 2007–2011.7/UCA1RXD/ UCA1SOMI (1) (2) (3) (4) (5) x 0 1 2 3 4 5 6 7 P3. O: 1 X I: 0.5 (I/O) UCA0RXD/UCA0SOMI (4) P3. Port P3 (P3.6/UCA1TXD/UCA1SIMO P3.2 (I/O) UCB0SOMI/UCB0SCL (4) (5) P3. O: 1 X P3SEL. O: 1 X I: 0.x) P3.7) Pin Functions PIN NAME (P3. If the I2C functionality is selected.x I: 0. O: 1 X I: 0. the output drives only the logical 0 to VSS level.x Module direction 0 1 Direction 0: Input 1: Output 0 1 1 P3OUT.MSP430F261x MSP430F241x www.x DVSS DVCC P3DIR.7 (I/O) UCA1RXD/UCA1SOMI (4) (4) FUNCTION CONTROL BITS / SIGNALS (1) P3DIR. USCI_A0/B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected.x 0 1 P3. O: 1 X I: 0. If the pin is required as UCA0CLK input or output.0/UCB0STE/UCA0CLK P3.3/UCB0CLK/UCA0STE P3. UCA0CLK function takes precedence over UCB0STE function.4/UCA0TXD/UCA0SIMO P3. O: 1 X I: 0.6 (I/O) UCA1TXD/UCA1SIMO (4) P3. O: 1 X I: 0.3/UCB0CLK/ UCA0STE P3. O: 1 X I: 0.

O: 1 0 1 I: 0.1/TB1 1 Timer_B7.3 (I/O) P4. O: 1 1 P4SEL.7/TBCLK EN Module X IN D Table 19.5/TB5 P4.CCI4B Timer_B7.4/TB4 4 Timer_B7.CCI2A and Timer_B7.TB4 P4.7/TBCLK (1) X = Don't care 7 P4. O: 1 0 1 I: 0.4/TB4 P4.3/TB3 P4.0 (I/O) P4.5 (I/O) P4.0 to P4.CCI6A and Timer_B7.x DVSS DVCC P4DIR.2/TB2 P4.CCI2B Timer_B7.0/TB0 P4. Texas Instruments Incorporated .CCI3A and Timer_B7.ti.7) Pin Functions PIN NAME (P4.0/TB0 0 Timer_B7.2 (I/O) P4.TBCLK FUNCTION CONTROL BITS / SIGNALS (1) P4DIR. O: 1 0 1 I: 0.x 0 1 P4.1/TB1 P4.3/TB3 3 Timer_B7.CCI6B Timer_B7. O: 1 0 1 I: 0.CCI3B Timer_B7.CCI4A and Timer_B7.CCI5A and Timer_B7.x) x P4.CCI5B Timer_B7.x P4IN.com Port P4 (P4.2/TB2 2 Timer_B7.4 (I/O) P4.CCI0A and Timer_B7.7 (I/O) Timer_B7.x 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 78 Submit Documentation Feedback Copyright © 2007–2011. O: 1 0 1 I: 0.6/TB6 P4. Port P4 (P4.TB1 P4.5/TB5 5 Timer_B7.TB0 P4.CCI0B Timer_B7. O: 1 0 1 I: 0.6/TB6 6 Timer_B7.x I: 0.TB5 P4.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.x 0 1 Direction 0: Input 1: Output 0 1 1 Pad Logic P4OUT.CCI1B Timer_B7.TB2 P4.TB3 P4.1 (I/O) P4.CCI1A and Timer_B7. O: 1 0 1 I: 0.x Module X OUT P4SEL.0 to P4. Input/Output With Schmitt Trigger P4REN.6 (I/O) P4.TB6 P4.7).

2 (I/O) ACLK P5.x I: 0.5/SMCLK P5.0/UCB1STE/ UCA1CLK P5.x P5IN. If the I2C functionality is selected.0 (I/O) MCLK P5.0 to P5.5/SMCLK P5. Copyright © 2007–2011.1 (I/O) SMCLK P5.4/MCLK P5.x 0 1 P5.6/ACLK P5. O: 1 1 I: 0. O: 1 0 1 P5SEL.4/MCLK P5.3 (I/O) UCB1CLK/UCA1STE P5.7/TBOUTH/SVSOUT EN Module X IN D Table 20.3/UCB1CLK/UCA1STE P5.x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 X = Don't care The pin direction is controlled by the USCI module.1 (I/O) UCB1SIMO/UCB1SDA (2) (4) P5.x Module X OUT P5SEL.x DVSS DVCC P5DIR.0/UCB1STE/UCA1CLK P5.0 to P5. O: 1 X I: 0. O: 1 X I: 0.2 (I/O) UCB1SOMI/UCB1SCL (2) (4) P5.2/UCB1SOMI/UCB1SCL P5. Input/Output With Schmitt Trigger Pad Logic P5REN. O: 1 X I: 0.ti.2/UCB1SOMI/ UCB1SCL P5. the output drives only the logical 0 to VSS level. O: 1 1 I: 0.1/UCB1SIMO/ UCB1SDA P5. Texas Instruments Incorporated Submit Documentation Feedback 79 . UCA1CLK function takes precedence over UCB1STE function.7) Pin Functions PIN NAME (P5.7/TBOUTH/SVSOUT 7 TBOUTH SVSOUT (1) (2) (3) (4) (2) FUNCTION CONTROL BITS / SIGNALS (1) P5DIR.x Module Direction 0 1 Direction 0: Input 1: Output 0 1 1 P5OUT.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Port P5 (P5.0 (I/O) UCB1STE/UCA1CLK (2) (3) P5.1/UCB1SIMO/UCB1SDA P5. O: 1 X I: 0.x) P5.7 (I/O) P5.7). Port P5 (P5. O: 1 1 I: 0.3/UCB1CLK/ UCA1STE P5.6/ACLK x 0 1 2 3 4 5 6 P5. If the pin is required as UCA1CLK input or output USCI_A1/B1 will be forced to 3-wire SPI mode if 4-wire SPI mode is selected.MSP430F261x MSP430F241x www.

O: 1 X I: 0. O: 1 X I: 0.3 (I/O) A3 (2) FUNCTION CONTROL BITS / SIGNALS (1) P6DIR. O: 1 X I: 0.0/A0 P6.3/A3 P6.1/A1 P6.3/A3 P6.4) Pin Functions PIN NAME (P6.x DVSS DVCC P6DIR.0 to P6. O: 1 X P6SEL. 80 Submit Documentation Feedback Copyright © 2007–2011.4 (I/O) A4 (2) X = Don't care The ADC12 channel Ax is connected to AVSS internally if not selected.x P6IN. Input/Output With Schmitt Trigger Pad Logic ADC12 Ax P6REN.0 (I/O) A0 (2) P6.4/A4 (1) (2) x 0 1 2 3 4 P6.2 (I/O) A2 (2) P6.0/A0 P6.x 0 1 Bus Keeper EN EN P6.4/A4 Module X IN D Table 21.x 0 1 Direction 0: Input 1: Output 0 1 1 P6OUT.x I: 0.1 (I/O) A1 (2) P6.x Module X OUT P6SEL.4).2/A2 P6.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.2/A2 P6.x 0 1 (y = 0) 0 1 (y = 1) 0 1 (y = 2) 0 1 (y = 3) 0 1 (y = 4) P6.0 to P6. Port P6 (P6. Texas Instruments Incorporated .1/A1 P6.ti.x 0 1 0 1 0 1 0 1 0 1 INCH. O: 1 X I: 0.x) P6.com Port P6 (P6.

The DAC outputs are floating if not selected.x 0 1 X X 0 1 X X DAC12AMP > 0 0 0 0 1 0 0 0 1 INCH. Input/Output With Schmitt Trigger Pad Logic DAC12_0OUT DAC12AMP > 0 ADC12 Ax ADC12 Ax P6REN.6/A6/DAC0 Module X IN D Table 22.5 and P6.5/A5/DAC1 (2) 5 DVSS A5 (3) DAC1 (DAC12OPS = 1) (4) P6.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Port P6 (P6.x 0 1 Bus Keeper EN EN P6.x P6IN. O: 1 1 X X P6SEL. The DAC outputs are floating if not selected.6) Pin Functions PIN NAME (P6.ti. Copyright © 2007–2011.y 0 0 1 (y = 5) 0 0 0 1 (y = 6) 0 DAC0 (DAC12OPS = 0) (7) (1) (2) (3) (4) (5) (6) (7) X = Don't care MSP430F261x devices only The ADC12 channel Ax is connected to AVSS internally if not selected. Texas Instruments Incorporated Submit Documentation Feedback 81 .6 (I/O) P6.x 0 1 Direction 0: Input 1: Output 0 1 1 P6OUT.6/A6/DAC0 (5) 6 DVSS A6 (6) FUNCTION CONTROL BITS / SIGNALS (1) P6DIR.5/A5/DAC1 P6.MSP430F261x MSP430F241x www.x) x P6.x I: 0.6).5 and P6. O: 1 1 X X I: 0.5 (I/O) P6. Port P6 (P6.x DVSS DVCC P6DIR.x Module X OUT P6SEL. MSP430F261x devices only The ADC12 channel Ax is connected to AVSS internally if not selected.

MSP430F261x MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti.com

Port P6 (P6.7), Input/Output With Schmitt Trigger
Pad Logic to SVS Mux VLD = 15 DAC12_0OUT DAC12AMP > 0 ADC12 A7 from ADC12 P6REN.7 DVSS DVCC P6DIR.7 0 1 Direction 0: Input 1: Output 0 1 1

P6OUT.7 Module X OUT P6SEL.7 P6IN.7

0 1 P6.7/A7/DAC1/SVSIN Bus Keeper EN EN

Module X IN

D

Table 23. Port P6 (P6.7) Pin Functions
PIN NAME (P6.x) x P6.7 (I/O) P6.7/A7/DAC1 (2)/ SVSIN (2) DVSS 7 A7
(3)

FUNCTION

CONTROL BITS / SIGNALS (1) P6DIR.x I: 0; O: 1 1 X X X P6SEL.x 0 1 1 1 1 INCH.y 0 0 1 (y = 7) 0 0 DAC12AMP>0 0 0 0 1 0

DAC1 (DAC12OPS = 0) (4) SVSIN (VLD = 15)

(1) (2) (3) (4)

X = Don't care MSP430F261x devices only The ADC12 channel Ax is connected to AVSS internally if not selected. The DAC outputs are floating if not selected.

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MSP430F261x MSP430F241x
www.ti.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011

Port P7 (P7.0 to P7.7), Input/Output With Schmitt Trigger (5)
P7REN.x DVSS DVCC P7DIR.x 0 0 1 Direction 0: Input 1: Output 0 1 1 Pad Logic

P7OUT.x VSS P7SEL.x P7IN.x

0 1 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7

EN D

Module X IN

Table 24. Port P7 (P7.0 to P7.7) Pin Functions (1)
PIN NAME (P7.x) P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 (5) (1) (2) 80-pin devices only 80-pin devices only X = Don't care x 0 1 2 3 4 5 6 7 P7.0 (I/O) Input P7.1 (I/O) Input P7.2 (I/O) Input P7.3 (I/O) Input P7.4 (I/O) Input P7.5 (I/O) Input P7.6 (I/O) Input P7.7 (I/O) Input FUNCTION CONTROL BITS / SIGNALS (2) P7DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P7SEL.x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

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MSP430F261x MSP430F241x
SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.ti.com

Port P8 (P8.0 to P8.5), Input/Output With Schmitt Trigger (3)
P8REN.x DVSS DVCC P8DIR.x 0 0 1 Direction 0: Input 1: Output 0 1 1 Pad Logic

P8OUT.x VSS P8SEL.x P8IN.x

0 1 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 EN

Module X IN

D

Table 25. Port P8 (P8.0 to P8.5) Pin Functions (1)
PIN NAME (P8.x) P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 (3) (1) (2) 80-pin devices only 80-pin devices only X = Don't care x 0 1 2 3 4 5 P8.0 (I/O) Input P8.1 (I/O) Input P8.2 (I/O) Input P8.3 (I/O) Input P8.4 (I/O) Input P8.5 (I/O) Input FUNCTION CONTROL BITS / SIGNALS (2) P8DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P8SEL.x 0 1 0 1 0 1 0 1 0 1 0 1

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Texas Instruments Incorporated Submit Documentation Feedback 85 .x 0 1 1 Copyright © 2007–2011.6).7/XT2IN P8SEL.6/XT2OUT Module X IN D Table 26.MSP430F261x MSP430F241x www.6 Module X OUT P8SEL. Input/Output With Schmitt Trigger (3) BCSCTL3.6) Pin Functions (1) PIN NAME (P8.6 0 1 Bus Keeper EN EN P8.x) x P8. Port P8 (P8.6 0 1 Direction 0: Input 1: Output 0 1 Pad Logic 1 P8OUT.x I: 0.XT2Sx = 11 0 XT2CLK 1 XT2 off From P8.6 P8IN.6/XT2OUT 6 XT2OUT (default) DVSS (3) (1) 80-pin devices only 80-pin devices only FUNCTION CONTROL BITS / SIGNALS P8DIR. O: 1 0 1 P8SEL.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 Port P8 (P8.6 DVSS DVCC P8DIR.ti.6 (I/O) P8.7/XIN P8.7 P8REN.

x 0 1 1 86 Submit Documentation Feedback Copyright © 2007–2011.XT2Sx = 11 XT2 off P8. Texas Instruments Incorporated .7 0 1 Direction 0: Input 1: Output 0 1 1 Pad Logic P8OUT.7 0 1 Bus Keeper EN EN D P8.6 P8REN.7 0 DVSS DVCC P8DIR.7/XT2IN Module X IN Table 27.x I: 0.ti.6/XT2OUT 0 XT2CLK 1 P8SEL.com Port P8 (P8.7/XT2IN 7 XT2IN (default) VSS (2) (1) 80-pin devices only 80-pin devices only FUNCTION CONTROL BITS / SIGNALS P8DIR.7 Module X OUT P8SEL.7 (I/O) P8.7) Pin Functions (1) PIN NAME (P8.7). Port P8 (P8.7 P8IN.x) x P8. O: 1 0 1 P8SEL. Input/Output With Schmitt Trigger (2) BCSCTL3.MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www.

MSP430F261x MSP430F241x www. Input/Output With Schmitt Trigger TDO Controlled by JT AG Controlled by JTAG JTAG Controlled by JTAG TDI DVCC DVCC TDO/TDI Fuse Burn and Test Fuse Test and Emulation Module DVCC TMS TMS DVCC TCK TCK During Programming Activity and During Blowing of the Fuse. Texas Instruments Incorporated Submit Documentation Feedback 87 . TDI/TCLK.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 JTAG Pins: TMS.ti. Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry TDI/TCLK Copyright © 2007–2011. TDO/TDI. TCK.

the fuse check mode remains inactive until another POR occurs. When the TEST pin is again taken low after a test or programming session. After deactivation. the additional current flow can be prevented by holding the TMS pin high (default condition). The second positive edge on the TMS pin deactivates the fuse check mode. The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see Figure 49).MSP430F261x MSP430F241x SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 www. Time TMS Goes Low After POR TMS ITF ITDI/TCLK Figure 49.com JTAG Fuse Check Mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). a fuse check current. 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. After each POR the fuse check mode has the potential to be activated. Therefore. of 1 mA at 3 V. Fuse Check Mode Current 88 Submit Documentation Feedback Copyright © 2007–2011. the fuse check mode and sense currents are terminated. When activated. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. Texas Instruments Incorporated .ti. ITF .

CCI0B in P2.0/TACLK. Changed crystal signal names in Table 26 and Table 27. Added nonmagnetic package option to Description and Table 1.CCI1A and Timer_A3. Texas Instruments Incorporated Submit Documentation Feedback 89 .CCI0A to Timer_A3. Typos and formatting corrected. Corrected LFXT1Sx values in Figures 23 and 24 (page 52). Corrected the cumulative program time of the flash (page 75). P2.6 and P2. Corrected pin number of P3. to -55°C to 150°C in Absolute Maximum Ratings. P2.MSP430F261x MSP430F241x www. Changed Timer_A3.CCI2A and Timer_A3.4.2/TA1 row. Programmed device. Changed Timer_A3. and Table 23.7 pin functions table (page 80).3. Added the figure "typical characteristics . Corrected the port schematics. Release to market of MSP430F261x BGA devices Added the ESD disclaimer (page 1). DESCRIPTION SLAS541B SLAS541C SLAS541D SLAS541E SLAS541F SLAS541G SLAS541H SLAS541I SLAS541J Copyright © 2007–2011. Table 22. Corrected "calibration data" section (page 20).TA0 to Timer_A3. Changed value of TAG_ADC12_1 from 0x10 to 0x08 in Tags used by the TLV Structure (page 20).ti. Added reserved BGA pins to the terminal function list (pages 10 and following). Added preview of MSP430F261x BGA devices.com SLAS541J – JUNE 2007 – REVISED DECEMBER 2011 REVISION HISTORY LITERATURE NUMBER SLAS541 SLAS541A Product Preview release Production Data release Corrected the format and the content shown on the first page.0.3/TA2 row in Port P1 (P1.TA1 in P1.7) pin functions table (page 78). Renamed Tags Used by the ADC Calibration Tags table to Tags used by the TLV Structure (page 20).LPM4 current" (Page 33).TA0 to Timer_A3. Added CAOUT to P1. Changed TA0 to Timer_A3.TA2 in P1. P2.6 and P3.2/CAOUT/TA0/CA4 row of Port P2. Changed Tstg.7 in 64-pin package in the terminal function list. Corrected the references in the output port parameters (page 36). Changed limits on td(SVSon) parameter (page 40) Changed Control Bits/Signals in Table 21.CCI0A to Timer_A3. Corrected tCMErase MIN value from 200 ms to 20 ms and removed two notes in the flash memory table (page 75). Corrected XT2Sx values in Figures 25 and 26 (page 54).0 to P1.

com 23-Dec-2011 PACKAGING INFORMATION Orderable Device MSP430F2416TPM MSP430F2416TPMR MSP430F2416TPN MSP430F2416TPNR MSP430F2416TZQW Status (1) Package Type Package Drawing LQFP LQFP LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP LQFP PM PM PN PN ZQW Pins 64 64 80 80 113 Package Qty 160 1000 119 1000 250 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2416TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR MSP430F2417TPM MSP430F2417TPMR MSP430F2417TPN MSP430F2417TPNR MSP430F2417TZQW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PM PM PN PN ZQW 64 64 80 80 113 160 1000 119 1000 250 CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2417TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR MSP430F2418TPM MSP430F2418TPMR MSP430F2418TPN ACTIVE ACTIVE ACTIVE PM PM PN 64 64 80 160 1000 119 CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR Addendum-Page 1 .PACKAGE OPTION ADDENDUM www.ti.

ti.PACKAGE OPTION ADDENDUM www.com 23-Dec-2011 Orderable Device MSP430F2418TPNR MSP430F2418TZQW Status (1) Package Type Package Drawing LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR PN ZQW Pins 80 113 Package Qty 1000 250 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2418TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR MSP430F2419TPM MSP430F2419TPMR MSP430F2419TPN MSP430F2419TPNR MSP430F2419TZQW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PM PM PN PN ZQW 64 64 80 80 113 160 1000 119 1000 250 CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2419TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR MSP430F2616TPM MSP430F2616TPMR MSP430F2616TPN MSP430F2616TPNR MSP430F2616TZQW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PM PM PN PN ZQW 64 64 80 80 113 160 1000 119 1000 250 CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2616TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR Addendum-Page 2 .

ti.PACKAGE OPTION ADDENDUM www.com 23-Dec-2011 Orderable Device MSP430F2617TPM MSP430F2617TPMR MSP430F2617TPN MSP430F2617TPNR MSP430F2617TZQW Status (1) Package Type Package Drawing LQFP LQFP LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP LQFP LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP LQFP PM PM PN PN ZQW Pins 64 64 80 80 113 Package Qty 160 1000 119 1000 250 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2617TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR MSP430F2618TPM MSP430F2618TPMR MSP430F2618TPMR-NM MSP430F2618TPN MSP430F2618TPNR MSP430F2618TZQW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PM PM PM PN PN ZQW 64 64 64 80 80 113 160 1000 1000 119 1000 250 CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU SN Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2618TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR MSP430F2619TPM MSP430F2619TPMR MSP430F2619TPN ACTIVE ACTIVE ACTIVE PM PM PN 64 64 80 160 1000 119 CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR Addendum-Page 3 .

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package.ti. -.please check http://www.PACKAGE OPTION ADDENDUM www. (2) Eco Plan . Pb-Free (RoHS Exempt).com/productcontent for the latest availability information and additional product content details. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Peak Temp. OTHER QUALIFIED VERSIONS OF MSP430F2618 : • Enhanced Product: MSP430F2618-EP Addendum-Page 4 . Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0. and makes no representation or warranty as to the accuracy of such information. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. LIFEBUY: TI has announced that the device will be discontinued. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. Efforts are underway to better integrate information from third parties.ti. or Green (RoHS & no Sb/Br) . and a lifetime-buy period is in effect. but TI does not recommend using this part in a new design. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.1% by weight in homogeneous material) (3) MSL. and peak solder temperature. PREVIEW: Device has been announced but is not in production.1% by weight in homogeneous materials. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible). Where designed to be soldered at high temperatures.The planned eco-friendly classification: Pb-Free (RoHS). TI bases its knowledge and belief on information provided by third parties. TI Pb-Free products are suitable for use in specified lead-free processes. TI and TI suppliers consider certain information to be proprietary. or 2) lead-based die adhesive used between the die and leadframe. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. and thus CAS numbers and other limited information may not be available for release. including the requirement that lead not exceed 0. NRND: Not recommended for new designs.com 23-Dec-2011 Orderable Device MSP430F2619TPNR MSP430F2619TZQW Status (1) Package Type Package Drawing LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR PN ZQW Pins 80 113 Package Qty 1000 250 Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ACTIVE ACTIVE Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR MSP430F2619TZQWR ACTIVE ZQW 113 2500 SNAGCU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. TBD: The Pb-Free/Green conversion plan has not been defined. Device is in production to support existing customers.

com 23-Dec-2011 NOTE: Qualified Version Definitions: • Enhanced Product .Supports Defense.PACKAGE OPTION ADDENDUM www.ti. Aerospace and Medical Applications Addendum-Page 5 .

6 7.9 1.0 330.0 24.0 14.6 7.0 W Pin1 (mm) Quadrant 24.4 16.0 20.3 K0 (mm) 2.4 24.0 14.4 13.3 B0 (mm) 13.0 24.0 24.4 16.1 1.4 13.0 330.0 Q2 Q2 Q1 MSP430F2416TPMR MSP430F2416TPNR MSP430F2416TZQWR 1000 1000 2500 MSP430F2417TPMR MSP430F2417TPNR MSP430F2417TZQWR PM PN ZQW 64 80 113 1000 1000 2500 330.6 7.0 14.5 16.0 Q2 Q2 Q1 MSP430F2419TPMR MSP430F2419TPNR MSP430F2419TZQWR PM PN ZQW 64 80 113 1000 1000 2500 330.0 24.0 24.ti.4 13.3 2.4 16.0 12.6 7.0 16.4 24.3 13.0 24.3 13.6 7.0 330.0 24.0 24.0 Q2 Q2 Q1 MSP430F2418TPMR MSP430F2418TPNR MSP430F2418TZQWR PM PN ZQW 64 80 113 1000 1000 2500 330.0 20.1 1.3 2.0 14.0 24.6 7.3 13.com 22-Dec-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LQFP LQFP BGA MI CROSTA R JUNI OR LQFP LQFP BGA MI CROSTA R JUNI OR LQFP LQFP BGA MI CROSTA R JUNI OR LQFP LQFP BGA MI PM PN ZQW 64 80 113 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.9 1.0 16.0 330.5 16.PACKAGE MATERIALS INFORMATION www.9 1.4 13.5 P1 (mm) 16.0 14.4 24.0 14.0 16.0 16.6 7.5 16.0 330.9 1.0 330.4 16.0 20.0 12.0 20.1 1.3 2.0 Q2 Q2 Q1 Pack Materials-Page 1 .0 24.4 24.0 330.6 7.0 14.0 14.0 12.0 330.0 24.1 1.

3 2.0 13.0 12.1 1.0 20.0 24.4 16.0 330.0 330.6 7.0 14.0 12.0 20.3 2.0 330.0 14.0 330.9 1.0 12.1 2.com 22-Dec-2011 Device Package Package Pins Type Drawing CROSTA R JUNI OR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant MSP430F2616TPMR MSP430F2616TPNR MSP430F2616TZQWR LQFP LQFP BGA MI CROSTA R JUNI OR LQFP LQFP BGA MI CROSTA R JUNI OR LQFP LQFP LQFP BGA MI CROSTA R JUNI OR LQFP LQFP BGA MI CROSTA R JUNI OR PM PN ZQW 64 80 113 1000 1000 2500 330.4 13.9 1.6 7.0 330.0 24.3 13.0 Q2 Q2 Q1 Pack Materials-Page 2 .5 16.4 24.PACKAGE MATERIALS INFORMATION www.4 24.3 2.3 2.0 20.0 330.1 1.4 13.4 16.0 14.0 14.0 24.0 24.0 Q2 Q2 Q1 MSP430F2617TPMR MSP430F2617TPNR MSP430F2617TZQWR PM PN ZQW 64 80 113 1000 1000 2500 330.0 24.0 24.5 16.4 24.0 20.0 24.6 7.1 1.5 16.0 24.0 14.0 16.0 16.9 1.0 330.0 14.4 24.0 14.5 16.0 24.6 7.0 Q2 Q2 Q1 MSP430F2618TPMR MSP430F2618TPMR-NM MSP430F2618TPNR MSP430F2618TZQWR PM PM PN ZQW 64 64 80 113 1000 1000 1000 2500 330.0 16.0 330.6 7.0 14.0 16.0 Q2 Q2 Q2 Q1 MSP430F2619TPMR MSP430F2619TPNR MSP430F2619TZQWR PM PN ZQW 64 80 113 1000 1000 2500 330.6 7.4 16.0 13.4 24.3 13.9 1.3 13.0 16.0 24.6 7.4 13.0 24.1 1.4 13.6 7.0 330.4 16.0 12.3 13.0 24.0 24.ti.

0 Width (mm) 346.0 41.0 346.9 346.0 346.9 346.9 346.com 22-Dec-2011 *All dimensions are nominal Device MSP430F2416TPMR MSP430F2416TPNR MSP430F2416TZQWR MSP430F2417TPMR MSP430F2417TPNR MSP430F2417TZQWR MSP430F2418TPMR MSP430F2418TPNR MSP430F2418TZQWR MSP430F2419TPMR MSP430F2419TPNR MSP430F2419TZQWR MSP430F2616TPMR MSP430F2616TPNR MSP430F2616TZQWR MSP430F2617TPMR MSP430F2617TPNR Package Type LQFP LQFP BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR LQFP LQFP Package Drawing PM PN ZQW PM PN ZQW PM PN ZQW PM PN ZQW PM PN ZQW PM PN Pins 64 80 113 64 80 113 64 80 113 64 80 113 64 80 113 64 80 SPQ 1000 1000 2500 1000 1000 2500 1000 1000 2500 1000 1000 2500 1000 1000 2500 1000 1000 Length (mm) 346.0 41.6 41.0 346.0 28.0 346.0 346.0 41.0 41.0 Pack Materials-Page 3 .2 346.2 346.0 333.0 346.2 346.6 41.0 345.0 345.0 346.0 Height (mm) 41.9 346.6 41.2 346.0 28.0 345.0 346.0 28.PACKAGE MATERIALS INFORMATION www.0 28.0 333.0 333.0 41.0 346.0 333.6 41.0 28.0 346.0 345.0 346.ti.9 346.6 41.0 333.0 346.0 345.2 346.0 41.

com 22-Dec-2011 Device MSP430F2617TZQWR MSP430F2618TPMR MSP430F2618TPMR-NM MSP430F2618TPNR MSP430F2618TZQWR MSP430F2619TPMR MSP430F2619TPNR MSP430F2619TZQWR Package Type BGA MICROSTAR JUNIOR LQFP LQFP LQFP BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR Package Drawing ZQW PM PM PN ZQW PM PN ZQW Pins 113 64 64 80 113 64 80 113 SPQ 2500 1000 1000 1000 2500 1000 1000 2500 Length (mm) 333.0 346.2 Width (mm) 345.0 333.ti.6 41.9 346.9 Height (mm) 28.6 41.0 346.0 41.0 346.0 345.6 Pack Materials-Page 4 .0 346.PACKAGE MATERIALS INFORMATION www.2 346.0 28.0 345.0 333.0 41.0 41.0 346.0 28.2 346.0 346.9 346.

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20 SQ 11. B. D.05 MIN 0°– 7° 0.50 TYP 10.60 MAX 0.MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) 0.80 1. POST OFFICE BOX 655303 • DALLAS.45 Seating Plane 1.08 4040152 / C 11/96 NOTES: A.17 48 33 PLASTIC QUAD FLATPACK 0. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. TEXAS 75265 1 .20 SQ 9. C.27 0.35 16 Gage Plane 0.45 1.25 0.50 0.13 NOM 1 7.75 0. This drawing is subject to change without notice. All linear dimensions are in millimeters.80 12.08 M 49 32 64 17 0.

05 MIN 0°– 7° 0.13 NOM 21 1 9.25 0.45 Seating Plane 1.27 0.35 20 Gage Plane 0. This drawing is subject to change without notice.08 4040135 / B 11/96 NOTES: A.50 60 0.MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) 0.08 M 61 40 80 0. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS.45 1. C.80 1.20 SQ 13.80 14.17 41 PLASTIC QUAD FLATPACK 0.50 TYP 12.75 0.20 SQ 11. B.60 MAX 0. All linear dimensions are in millimeters. TEXAS 75265 1 .

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