JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD M.Tech.

VLSI DESIGN COURSE STRUCTURE AND SYLLABUS I YEAR Code - I Semester Group

Elective -I

Elective -II

Lab

Subject Microcontrollers for Embedded System Design CPLD & FPGA Architectures and Applications VLSI Technology & Design Algorithms for VLSI Design Automation Hardware Software Co-Design Digital System Design Device Modeling Advanced Digital Signal Processing Network Security & Cryptography Micro Electromechanical Systems Simulation Lab (VLSI) Seminar Total Credits (6 Theory + 1 Lab.)

L 3 3 3 3 3

P 0 0 0 0 0

Credits 3 3 3 3 3

3

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3

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3 -

2 2 22

1

Memory Controller and Memory arbitration Schemes. Embedded Hardware Units and Devices in system. 2. Rolin D. I/O Devices. Switched Capacitor blocks. Channel & IDMA.I Year – I Sem. 2 . Serial port Device Driver. Ethernet Protocol. ARM Systems Developers Guides. Interfacing Processor (8051. Continuous Timer blocks. Embedded Systems . Input/Output Ports and Circuits. Register Set. Device drivers for Internal Programmable timing devices Unit – V: Network Protocols Serial communication protocols. M. Embedded RISC Processor architecture – ARM Processor architecture. PIC).Mckinaly.. PH Inc. 2008.Tech (VLSI Design) MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN Unit – I: Introduction to Embedded Systems Overview of Embedded Systems. Processor Embedded into a system. Elsevier. Unit – II: Microcontrollers and Processor Architecture & Interfacing 8051 Architecture. Programming of PSOC.TMH.Design & Optimizing System Software . SDMA. Danny Causy – PE.Architecture Programming and Design – Raj Kamal. Valvano – Brookes / Cole. External Bus Interface TEXT BOOKS: 1. Thomas Learning.Andrew N. Modes of operation and overview of Instructions Unit – IV: Interrupts & Device Drivers Exceptions and Interrupt handling Schemes – Context & Periods for Context Switching. Sloss. Counters and Timers. 1998.John B. Designers Guide to the Cypress PSOC – Robert Ashpy. PIC Microcontroller and Embedded Systems – Muhammad Ali Mazidi. Elsevier. 3. Designing with PIC Microcontrollers. Formalization of System Design. Memory Interfacing. 1999. Embedded Microcomputer Systems. Real Time Interfacing – Jonathan W. REFERENCES: 1. Deadline & interrupt latency. 2. External Memory. Complex System Design. Device driver using Interrupt Service Routine. Unit – III: Embedded RISC Processors & Embedded System-on Chip Processor PSOC (Programmable System-on-Chip) architectures. Digital blocks. Chris Wright. Classification of Embedded Systems. Design Process in Embedded System. Embedded Software. 2nd ed. 2005. I/O blocks. 2004. Peatman. Dominic Symes. 3. PIC Controllers.

R.V Case studies of paraller adder cell paraller adder sequential circuits.Tech (VLSI Design) CPLD AND FPGA ARCHITECTURE AND APPLICATIONS UNIT –I Programmable logic : ROM.I Year – I Sem. 2007.K. Lattice PLST’s architectures – 3000 series – Speed performance and in system programmability.Francis. Elsevier. 2. Brown. PAL PLD. Cypres FLASH 370 Device technology. Field programmable gate array. routing architecture. Mourad. extended petrinetes for parallel controllers. 2003. PGA – Features. Prentice Hall.G.J.Oldfield. 1994. properties. multiplexers. REFERENCES : 1. PLA. 3. design flow technology mapping jfor FPGAs.CPLD (Mach 1to 5). programming and applications using complex programmable logic devices Altera series – Max 5000/7000 series and Altera FLEX logic-10000 series CPLD. S.Logic blocks.S. parellel controllers. Edr. J. 3 . UNIT – II FPGAs: Field Programmable gate arrays.Z. BSP.K. Field Programmable Gate Arrays. counters. Richard C Dore.Vranesic. 4. Digital Systems Design with FPGA’s and CPLDs – Ian Grout.3 and their speed performance UNIT-III Alternative realization for state machine chat suing microprogramming linked state machine one –hot state machine. Kluwer Academic Publications. 1994. Field Programmable Gate Array Technology . Wiley Publications. 2. UNIT-IV Digital front end digital design tools for FPGAs& ASICs: Using mentor graphics EDA tool (“FPGA Advantage”) – Design flow using FPGAs UNIT . M. Case studies Xitir x XC4000 & ALTERA’s FLEX 8000/10000 FPGAs: AT &T ORCA’s ( Optimized Reconfigurable Cell Array): ACTEL’s ACT-1.2. John V. BSP. petrinetes for state machines-basic concepts. P.Chan & S. Digital Design Using Field Programmable Gate Array. TEXT BOOKS: 1.Lala. Digital System Design using Programmable Logic Devices – Parag. Trimberger. AMD’s. 2009.Rose .

Design validation and testing. Clocking disciplines. A. K. M. Pearson Education. MOS.Tech (VLSI Design) VLSI TECHNOLOGY & DESIGN UNIT – I: Review of Microelectronics and Introduction to MOS Technologies: MOS. 2005. Simulation. Adisson Wesley. UNIT –IV: SEQUENTIAL SYSTEMS: Memory cells and Arrays. Highlevel synthesis. Essentials of VLSI Circuits and Systems.I Year – I Sem. Interconnect design. Power optimization.Wayne Wolf. Trends And Projections. Pass Transistor. Switch Logic. 3rd ed. CMOS.H. D. Resistive and Inductive interconnect delays. Switch logic networks. CMOS & BiCMOS Circuits: I ds-Vds relationships.Pucknell. 1997. Architecture for low power. Principals of CMOS VLSI Design – N. Gds and ωo. Power optimization. Scalable Design rules. off-chip connections.. 4 .. Latch-up in CMOS circuits.E Weste. UNIT – V: FLOOR PLANNING & ARCHITECTURE DESIGN: Floor planning methods. Modern VLSI Design . UNIT – II: LAYOUT DESIGN AND TOOLS: Transistor structures. Wires and Vias. 2nd ed. Architecture testing. 2. TEXT BOOKS: 1. Gm. K. Threshold Voltage Vt. REFERENCES: 1. SOCs and Embedded CPUs. Layout Design tools. MOS Transistor circuit model. UNIT – III: COMBINATIONAL LOGIC NETWORKS: Layouts. Zpu/Zpd. Alternative Gate circuits. Network delay. Gate and Network testing. LOGIC GATES & LAYOUTS: Static Complementary Gates. Low power gates. Eshraghian Eshraghian. BiCMOS Technology. PHI. Design. CMOS & Bi CMOS Inverters. Basic Electrical Properties of MOS.Eshraghian.

3rd Ed. WILEY Student Edition. Pearson Education Asia. Routing and Programmable MCM’s. Switch level Modelling and Simulation. partitioning and Routing staggered Models. Computational complexity. Modern VLSI Design:Systems on silicon – Wayne Wolf. UNIT VII PHYSICAL DESIGN AUTOMATION OF FPGA’S FPGA technologies. Integer Linear Programming. Internal representation of the input Algorithm. Allocation. Springer International Edition. High-level Transformations.I Year – I Sem.Gerez. Multiple stage routing. Some Scheduling Algorithms. MCM phsical design cycle. Local Search. TEXT BOOKS: 1. Two-Level logic Synthesis UNIT VI HIGH-LEVEL SYNTHESIS Hardware Models. Binary-Decision diagrams. 2005.H. Topologic routing. for segmented and UNIT VIII PHYSICAL DESIGN AUTOMATION OF MCM’S MCM technologies. Routing – Maze routing. 2... Genetic Algorithms. UNIT III LAYOUT COMPACTION. 2. FLOORPLANNING AND ROUTING Problems. Design Automation tools. Tabu search. John wiley & Sons (Asia) Pvt. PLACEMENT. 2nd ed. 5 . 1998. Wiley. UNIT IV MODELLING AND SIMULATION Gate Level Modelling and Simulation. M. 1999.Tech (VLSI Design) ALGORITHMS FOR VLSI DESIGN AUTOMATION UNIT I PRELIMINARIES Introduction to Design Methodologies. Integrated Pin – Distribution and routing. Algorithms for VLSI Design Automation. 1993. Branch and Bound. Assignment and Scheduling. Physical Design cycle for FPGA’s. REFERENCES: 1. Algorithms for VLSI Physical Design Automation – Naveed Sherwani.Chip Array based and Full Custom Approaches. UNIT V LOGIC SYNTHESIS AND VERIFICATION Basic issues and Terminology. UNIT II GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION Backtracking. Placement . Concepts and Algorithms. Comoputer Aided Logical Design with Emphasis on VLSI – Hill & Peterson. Simulated Annealing. S. Algorithimic Graph Theory. Tractable and Intractable problems. Partitioning. Ltd. Dynamic Programming. Some aqspects of Assignment problem.

future developments in emulation and prototyping architecture specialization techniques. UNIT – III COMPILATION TECHNIQUES AND TOOLS FOR EMBEDDED PROCESSOR ARCHITECTURES: Modern embedded architectures. implementation verification. embedded software development needs. Architecture for Data dominated systems (ADSP21060.DESIGN (ELECTIVE-I) UNIT –I CO. A Generic Co-design Methodology. LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN-II Heterogeneous specifications and multi language co-simulation the cosyma system and lycos system. interface verification UNIT – V LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN-I System – level specification. Springer. Target Architecture and Application System classes.I Year – I Sem.Design Models. concurrency coordinating concurrent computations. UNIT –II PROTOTYPING AND EMULATION: Prototyping and emulation techniques. Hardware / software co.Tech (VLSI Design) HARDWARE. System Communication infrastructure.SYNTHESIS ALGORITHMS : Hardware software synthesis algorithms: hardware – software partitioning distributed system co-synthesis. compilation technologies practical consideration in a compiler development environment. Wayne Wolf – 2009. UNIT – IV DESIGN SPECIFICATION AND VERIFICATION: Design. verification tools. the co-design computational model. TEXT BOOKS : 1.design Principles and Practice. interfacing components. Hardware / software co. prototyping and emulation environments. system communication infrastructure TARGET ARCHITECTURES: Architecture Specialization techniques. CO. 2002. 2. design representation for system level synthesis.SOFTWARE CO. Mixed Systems. kluwer academic publishers 6 . Languages. TMS320C60).design Principles and Practice – Jorgen Staunstrup. Architectures. design verification. co-design. system level specification languages. Architecture for control dominated systems (8051-Architectures for High performance control).DESIGN ISSUES Co. M.

Random testing. Kohavi . Transition Check Approach . 3. 4th Edition.D.Fault equivalence and fault location –Fault dominance – Single stuck at fault model – Multiple stuck at fault models –Bridging fault model Fault diagnosis of combinational circuits by conventional methods – Path sensitization techniques. Breuer and Arthur D. Digital Design – Morris Mano. M. 5th ed. N. 2. PHI REFERENCES: 1.I Year – I Sem. Machine identification.John Wiley & Sons Inc.State identification and fault detection experiment. Test generation and Testable PLA Design. Cengage Learning. Unit-IV: PLA Minimization and Testing PLA Minimization – PLA folding.State assignment for FPGA’s . Unit-II: Fault Modeling & Test Pattern Generation Logic Fault model – Fault detection & Redundancy.. Digital Systems Testing and Testable Design – Miron Abramovici. Logic Design Theory – N.Ciletti. Design of fault detection experiment. M. Signature analysis and test bridging faults. Switching and Finite Automata Theory – Z. PHI. TMH 2. State transition table. Friedman. Biswas. Lee . PHI 7 . Melvin A. Fault model in PLA. Unit-III: Fault Diagnosis in Sequential Circuits Circuit Test Approach. TEXT BOOKS: 1. Transition count testing. Roth.State Machine charts – Derivation of SM Charts – Realization of SM charts – Design Examples – Serial adder with Accumulator . 3. PODEM. 2nd ed. Digital Circuits and Logic Design – Samuel C. Boolean Difference method – Kohavi algorithm – Test algorithms – D algorithm. Fundamentals of Logic Design – Charles H.Tech (VLSI Design) DIGITAL SYSTEM DESIGN (ELECTIVE-I) Unit-I: Designing with Programmable Logic Devices Designing with Read only memories – Programmable Logic Arrays – Programmable Array logic – Sequential Programmable Logic Devices – Design with FPGA’s– Using a One-hot state assignment.Binary Multiplier – Signed Binary number multiplier (2’s Complement multiplier) – Binary Divider – Control logic for Sequence detector – Realization with Multiplexer – PLA – PAL. 2001. Fundamental mode model – Flow table – State reduction – Minimal closed covers – Races.Problem of Initial state assignment for One –Hot encoding . Cycles and Hazards. Unit-V: Minimization and Transformation of Sequential Machines The Finite state Model – Capabilities and limitations of FSM – State equivalence and machine minimization – Simplification of incompletely specified machines..

8 .Poon model. Prentice Hall. M.dynamic model. Mcgraw hill. Hetero Junction bipolar transistors (HBTs).Tech (VLSI Design) DEVICE MODELLING (ELECTIVE-I) UNIT I: Introduction to Semiconductor Physics: Review of Quantum Mechanics. Solid state circuits – Ben G.Silicon on insulator – CMOS process enhancements – interconnects circuit elements UNIT V: Modeling of Hetero Junction Devices: Band gap Engineering. 2. dependence of model parameters on structures UNIT II: Integrated Diodes: Junction and Schottky diodes in monolithic technologies – static and dynamic behavior – small and large signal models – SPICE models Integrated Bipolar Transistor: Types and structures in monolithic technologies – Basic model (Eber-Moll) – Gunmel . Fijedly. 2nd edition.p-welltwin tub. 1997. Wiley-Interscience. 1997 REFERENCES: 1. 2008.I Year – I Sem. Physics of Semiconductor Devices – Sze S. M. Modified current continuity equations. Boltzman transport equation. New York. SiGe TEXT BOOKS: 1. parasitic effects – SPICE model –parameter extraction UNIT III: Integrated MOS Transistor: nMOS and pMOS transistor – threshold voltage – threshold voltage equations – MOS device equations – Basic DC equations second order effects – MOS models – small signal AC characteristics – MOS FET SPICE model level 1. S. continuity equation. 3 and 4 UNIT IV: VLSI Fabrication Techniques: An overview of wafer fabrication. Streetman. 1981 1. 2. Introduction to Device Modeling and Circuit Simulation – Tor A. wafer processing – oxidation – patterning – diffusion – ion implantation – deposition – Silicon gate nMOS process – CMOS processes – n-well. John Wiley Student Edition. Introduction to Semiconductor Materials and Devices – Tyagi M. Bandgap Offset at abrupt Hetero Junction. Poisson equation Integrated Passive Devices: Types and Structures of resistors and capacitors in monolithic technology.

W. Algorithms & Applications . Properties of Linear Prediction Filters UNIT V Finite Word Length Effects: Analysis of finite word length effects in Fixed-point DSP systems – Fixed. FFT. 2000.P. Backward Linear Prediction. IIR Filters. DSP – A Pratical Approach – Emmanuel C.Manolokis. A. Schur Algorithm. 3.Gnanapriya. UNIT –IV Linear Prediction : Forward and Backward Linear Prediction – Forward Linear Prediction. 2. Solution of the Normal Equations: Levinson Durbin Algorithm. Pearson Education. Optimum reflection coefficients for the Lattice Forward and Backward Predictors. Floating Point Arithmetic – ADC quantization noise & signal quality – Finite word length effect in IIR digital Filters – Finite word-length effects in FFT algorithms.Ifeacher. TEXTBOOKS: 1. Multirate Systems and Filter Banks – P. Non-parametric Methods: Bartlett. Modern spectral Estimation : Theory & Application – S..Vallavaraj. 4th ed.I Year – I Sem. Filter design & Implementation for sampling rate conversion. PHI.G.Alan V Oppenheim & Ronald W Schaffer.. Digital Signal Processing: Principles. Decimation by a factor D.Vaidyanathan – Pearson Education Digital Signal Processing – S. Discrete Time signal processing .Proakis & D. AR Models .Salivahanan.Kay. Multirate Signal Processing: Introduction.TMH 9 .J. Jervis. 1988. Welch & Blackman & Tukey methods. Relation between auto correlation & model parameters. REFERENCES: 1. Comparison of all Non-Parametric methods UNIT III Parametric Methods of Power Spectrum Estimation: Autocorrelation & Its Properties. Applications of Multirate Signal Processing UNIT II Non-Parametric methods of Power Spectral Estimation: Estimation of spectra from finite duration observation of signals. Barrie. Interpolation by a factor I. M . PHI. Sampling rate conversion by a rational factor I/D. FIR Filters. 3. MA & ARMA models for power spectrum estimation.Yule-Waker & Burg Methods. C. Multistage Implementation of Sampling Rate Conversion. 2.G. PHI. 2 ed.Tech (VLSI Design) ADVANCED DIGITAL SIGNAL PROCESSING (ELECTIVE-II) UNIT I Review of DFT. M.

Key Management. Steganography. Hash functions. RIPEMD-160. PE.Tech (VLSI Design) NETWORK SECURITY AND CRYPTOGRAPHY (ELECTIVE-II) UNIT-I Introduction: Attacks. A Model for Internetwork security. Classical Encryption Techniques. UNIT-VII IP Security Overview. Diffie-Hellman Key exchange. UNIT-II Modern Techniques: Simplified DES. Blowfish.William Stallings. Fire Walls : Fire wall Design Principles. International Data Encryption algorithm. M. Message digest Algorithm. Architecture. Discrete logarithms. Secure sockets layer and Transport layer security.I Year – I Sem. UNIT-IV Number theory Prime and Relatively prime numbers. RC2. 2000. Services and Mechanisms. Security services.509 directory Authentication service.Classical Techniques: Conventional Encryption model. Message Authentication. Data Encryption standard.John Wiel 10 . Strength of DES. Web Security Web Security requirements. Security attacks. Viruses and Related threats. Block Cipher Principles. CAST-128. Secure Electronic Transaction. Fermat’s and Euler’s theorems. Characteristics of Advanced Symmetric block cifers. UNIT-V Hash and Mac Algorithms MD File. Key distribution. Viruses and Worms : Intruders. Authentication. TEXT BOOKS: 1. HMAC. UNIT-VI Authentication Applications: Kerberos. Algorithms: Triple DES. Digital signature standards. Secure Hash Algorithm. Encapsulating Security Payload. Public Key Cryptography Principles. Modular arithmetic. Random Number Generation. Cryptography and Network Security: Principles and Practice . Elliptic Curve Cryptography. Message authentication and Hash functions: Authentication requirements and functions. RC5. Euclid’s Algorithm. the Chinese remainder theorem. UNIT-VIII Intruders. Trusted systems. Security of Hash functions and MACs. UNIT-III Conventional Encryption Placement of Encryption function.Electronic Mail Security: Pretty Good Privacy. Block Cipher Design Principles and Modes of operations. Principles of Network and Systems Administration. S/MIME. Key Management. RSA Algorithm. X. Traffic confidentiality. REFERENCES: 1. Combining security Associations. Authentication Protocols. Digital signatures and Authentication protocols: Digital signatures. Differential and Linear Cryptanalysis. Mark Burgess. Testing for primality.

M. CRC Press. RF Switches for modulation. John wiley & Sons. wave shaping. UNIT –II Review of mechanical concepts like stress. Status of MEMS in the current electronics scenario. 3. Two terminal MEM structures. and Structures . Broad Response of Micro electromechanical systems (MEMS) to Mechanical (Force. London. UNIT – III Two terminal MEMS . strain. force temperature.Ristic L. critical fringe field – field calculations using Laplace equation. MEM Transducers for pressure. MEMS Theory.. compatibility of MEMS from the point of power dissipation. optical and magnetic stimuli. CBS publishers & Distributors.GABRIEL. UNIT – V MEM Technologies: Silicon based MEMS. M. deflection curves for canti-levers. Sensor Technology and Devices . R.Tech (VLSI Design) MICRO ELECTROMECHANICAL SYSTEMS (ELECTIVE-II) UNIT –I Introduction. Strength of Materials –Thimo Shenko. 2002.. (Ed) . converters. Fixed Beams diaphragms).) Thermal. Artech House. UNIT – IV MEM circuits & structures for simple GATES.fixed beam. Process flow and description of the processes. Deflection with voltage in C. MEMS and NEMS. pressure etc. Three terminal MEM structures – controlled variable capacitors – MEM as a switch and possible applications. . Metal Based MEMS: Thin and thick film technologies for MEMS. leakage etc.Lyshevski. bending moment. Deflection Vs Voltage curve. Electrostatic excitation – columbic force between the fixed and moving electrodes. deflection curve. moving layers spacers etc. Applications of variable capacitors.Servey E.F. distributed force. Applications for analog circuits like frequency converters. Systems Devices. Optical MEMS. OR.2003. 2. REFERENCES: 1. 2000.process flow – brief account of various processes and layers like fixed layer.I Year – I Sem. Discussion on the approximate solutions – transient response of the MEMS. Design and Technology .AND. basic structures of MEM devices – (Canti-Levers.capacitance Vs voltage Curve – variable capacitor. and etching technologies. distributed force.Review. Differential equations describing the deflection under concentrated force. Electrical. 11 . NOR.L. NAND. TEXT BOOKS: 1. Exclusive OR<simple MEM configurations for flip-flops triggering applications to counters. 1994.

CYCLE 2: 1. 3.I Year – I Sem. PEX) and post layout simulation. Run Physical Verification (DRC. Digital Circuits Description using Verilog.INV. Layout basics. PMOS Characteristics. 12 . Synthesis of Digital Circuits. 2. Extract the Layout. Verification of the functionality of designed Circuits using function simulator. For Experiments in cycle 2: 3.Tech (VLSI Design) SIMULATION LAB (VLSI) CYCLE 1: 1. 4. LVS. Transient Analysis. M.4. NMOS. 4. 3. Implementation of Designed Digital Circuits Using FPGA and CPLD devices. Altera. EXOR. NAND. 6. AC Characteristics. NOR. EXNOR. multiplexer.5: Draw the Schematics Perform Simulation. Timing Simulation for critical Path time calculation. Place and route techniques for major FPGA Vendors using Xilinx. Cypress etc. 5. MoS inverter DC Characteristics. 5.. Layout Comparator. Layout of adder. 2. subtractor.

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