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ARTICLE IN PRESS

Microelectronics Journal 41 (2010) 430–439

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Designing a compact soft-start scheme for voltage-mode DC–DC switching converters
Sizhen Li n, Xuecheng Zou, Xiaofei Chen, Quan Gan
Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China

a r t i c l e in f o
Article history: Received 15 August 2009 Received in revised form 23 April 2010 Accepted 3 May 2010 Keywords: DC–DC switching converter Soft-start scheme Inrush current Digital-controlled current limitation DAC

a b s t r a c t
In this paper, a compact soft-start scheme is proposed and successfully applied to typical voltage-mode DC–DC switching converters. The adaptive current limitation implemented through DAC control will largely reduce the overshoot voltage under a wide range of output current. Proven experimentally by a buck converter implemented in a 0.5 mm CMOS technology, the post-simulation results show that when the converter starts up, the maximum overshoot (2.7% at ILOAD ¼ 0 A) by the proposed soft-start scheme is less than that with the conventional scheme by 5% under the same condition. The start-up time can be adaptively adjustable depending on load current and the maximum start-up time is around 760 ms with 22 mF output capacitor. The circuits which realize the soft-start scheme can also be fully integrated into the control chip of DC–DC switching converter resulting in low cost. & 2010 Elsevier Ltd. All rights reserved.

1. Introduction DC–DC switching converters are widely used in portable electronic device for high efficiency and low power consumption [1]. In the DC–DC switching converter, during start-up, the large inrush current and the overshoot of the output voltage will damage the inductor and induce stability problem. As a result, soft-start scheme is normally adopted to eliminate the inrush current and reduce the overshoot voltage [2–4]. There are two types of soft-start implementation, one is through voltage-mode method; the other is by current-mode method. At present, voltage-mode method has been widely used in industrial catalog products for its simplicity [5,6]. However, most voltage-mode soft-start circuits need an external capacitor to regulate the soft-start time and the inrush current cannot be limited directly. It leads to cost increase and potential damagerisk in external components. The current trend of integrating numerous LDOs and switched-mode regulators and controllers on the same system-on-chip PMIC, each with its own start-up and power-up sequencing requirements, necessitates the design of a compact fully integrated soft-start circuit with higher safety requirements for low cost considerations [7]. As a result, the current-mode soft-start method will be more competent because it can directly limit the inrush current and can be fully integrated in the controller chip [8,9]. However, both approaches in [8,9] are

n

Corresponding author. Tel.: + 86 13545119211. E-mail address: lisizhen@gmail.com (S.Z. Li).

applied in current-mode switching converter and may not be appropriate for the voltage-mode switching converter as there is only one voltage feedback loop in the voltage-mode DC–DC converter. Fig. 1 describes the conventional current-mode soft-start scheme applied to a voltage-mode buck converter [10]. When starts up, the divided voltage of the output is much lower than the voltage reference Vref, the error amplifier is under unbalanced state. The output voltage of the error amplifier is at high voltage level. If there is not any limitation, the converter works under the 100% duty ratio; thus, large inrush current will flow into the output capacitor to generate output voltage overshoot. Current-mode soft-start method senses the current passing through the inductor L1 and limits the inductor peak current (ILpeak) through the current comparator to reduce the inrush current. It will generate potential overshoot of the output voltage under different loads because the current reference is usually set invariably higher than the typical output current. The output voltage Vo and inductor current IL of the converter under the softstart scheme are shown in Fig. 2. It can be obtained that the larger overshoot will be generated at the lighter load and the maximum overshoot occurs at the noload condition. Moreover, the approach of employing the currentmode soft-start scheme suffers from a dissatisfactory operating efficiency because of the power dissipated in the current sensor. Besides, the stability problem may also occur if the current limitation cannot be controlled fast. So far, there are very few papers published relating to the overshoot reduction technology of current-mode soft-start scheme for voltage-mode switching

0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.05.001

ð1Þ ð2Þ Fig. Fig. and thus the inductor peak current (ILpeak) can be limited by stages. fast comparator with clamping function and the driver with dedicated control contribute to the high stability. The current reference (IREF) is converted to voltage V1. Different from constant ILpeak control given in Fig. Finally. The proposed scheme is realized using transistor level. The experimental results are discussed in Section 3. 1. 2. In Section 2. As shown in Fig. Thanks to the digitalcontrolled current-limitation. the output signal Nsoft of the current comparator and the oscillator output signal CLK are used to lift the output voltage. Conventional current-mode soft-start scheme applied to a voltage-mode buck converter. During start-up. 1.1. When EN is set to logic high. 3. 4. 2. which features with simplicity is proposed to reduce the power dissipation. converter. In this paper. Besides. Proposed soft-start scheme 2. the soft-start function starts working. which is the same as that of oscillator. an improved soft-start scheme using DAC technique is proposed and applied to a voltage-mode buck converter as described in Fig.ARTICLE IN PRESS S. The soft-start circuit is fully integrated and applied to a voltage-mode buck converter in our design. The high bits of the counter (Qnc À2 Qnc À1 ) are used to generate the output codes D0D1D2. An innovative digitalcontrolled current sensor. The switching frequency of power transistors is fs (fs ¼1/Ts). The purpose is to reduce the overshoot voltage under different loads to a great extent. especially current-mode soft-start scheme with reduced current-sense power consumption and improved stability.Z. It should also be noted that . 1. T2 ¼ T3 ¼ 2nc À2 Ts . the conclusion is given in Section 4. (b) no load. it can be obtained that T1 ¼ ð2nc À2 À1ÞTs . EN is the enable signal of the counter. the principle of the scheme and the design of the circuits are presented in detail. Waveforms of conventional soft-start scheme using constant inductor peak current (ILpeak) control under: (a) full load. the output signal NPWM of the PWM comparator and the signal CLK are used to realize feedback control to regulate the output voltage. The signal NPWM is generated from PWM comparator as shown in Fig. Structure and operational principle Based on the principle of the conventional current-mode softstart scheme. The upper edge of the signal CLK turns the power transistor M1 on and the upper edge of the signal Nsoft turns M1 off. an improved current-mode soft-start scheme that offers overshoot reduction is proposed. The nc-bit counter calculates the switching cycles of power transistors. During normal state. 4 describes the soft-start key waveforms under full load and no load. 4a. the overshoot is largely reduced under a wide range of load currents. the principle of the proposed soft-start scheme is to have the current reference IREF rise step by step as shown in Fig. which are the inputs of the DAC. / Microelectronics Journal 41 (2010) 430–439 431 Fig. Li et al. the proposed scheme is not limited to buck converter but can be extended to voltage-mode DC–DC converter in general.

8Ia. with the decrease in load current soft-start time is reduced. from Eqs. ILpeak4/2. Thus. In our design. 0 o t ot1 . the average inductor current higher than the load current is used to enhance the output voltage. However. The voltage signal V2 is the output of the current-sense circuit and the capacitor is used to stabilize the output voltage as illustrated in Fig. t 4t3 RON ð6Þ where C is the value of the output capacitor.Z.2. Current sensor Among many current sensing techniques. the signal Nsoft changes the state from logic low to logic high such that the power transistor M1 turns off.6 A in our experiment under which the full-load current is 1. 16Ia. the average inductor current equals to the output current. That is. Thus. the inductor peak current is limited step by step during soft-start stage. when the sensed inductor current IL reaches the value of ILpeak. the inductor current is sampled through sensing the voltage Vsw. Thus. RON 12Ia R1 ¼ ILpeak3 ¼ . it can be derived that ILpeak ¼ ¼ ILpeak1 ¼ IREF R1 RON ð5Þ 4Ia R1 . the difference between QL and QR is reduced and the overshoot has been largely reduced. The simple and delicate design eliminates the potential large burr in V2 and the noise of the signal Nsoft. the output V1 is described as V1 ¼ Vin ÀIREF R1 : ð4Þ The power transistor M1 works in the deep linear region. NsoftN2 is ‘01’. RON 16Ia R1 ¼ ILpeak4 ¼ . feedback is used to control the output voltage V2 of the current-sense circuit. t1 o t o t2 . The overshoot can be estimated by DV ¼ Q L ÀQ R C ð7Þ When codes D0D1D2 are ‘000’. which will be discussed later. Theoretically. and in normal state. Moreover. Li et al. As shown in Fig. The circuit is given in Fig. 3. the more the current step is. the current passing through the inductor is IL. the start-up time mainly depends on the load current. In Eq. 5. the ILpeak is set constant at different values under different load current ranges. Vsw is controlled by the gate driving signals Vp and Vn. / Microelectronics Journal 41 (2010) 430–439 Fig. the output V2 is given by V2 ¼ Vin ÀIL RON : Set V1 ¼V2.Thus. the ILpeak is designed in steps of typically ILpeak4/4. the current passing through the resistor R1 (IREF) rises in steps of 4Ia. the more charge will transfer to the output capacitor during start-up and Vo will reach to the typical value Vtyp faster. 12Ia. we propose the digital-controlled current sensor which features with simplicity [12. the overshoot will approximately linearly increase as the load current decreases. The lighter the load is. which is the output of the current comparator as described in Fig. At 1. ‘111’ in turn. (7). ‘001’. From the above discussion. In that case. In addition. Q L is proportional to the predetermined value of ILpeak. delays between Vsw and N2 are introduced in our design as described in Fig. 6. we propose the circuit which senses the output voltage Vo. the transistor MP4 turns on and quickly steps up the voltage V2 to make the signal Nsoft return to ‘0’. ‘011’. the resistance is defined as RON.3 A. the extra current will flow to the capacitor to charge and . As Vo climbs higher than the typical value Vtyp. When NsoftN2 is ‘11’ that denotes over-current is detected and current-sense is disabled. t2 o t ot3 . 2. Q L the charge stored in the inductor. the value of ILpeak can be tuned into other value. To remove the burr. 3. Suppose that during sampling. The voltage Vsw has large transient change. (4) and (5). 3. solution with too many steps will make the circuit implementation complicated and increase the manufacture cost. In our proposed scheme. which are the outputs of the driver. The current-sense function is realized through sensing the voltage Vsw and is controlled by the signal N2 generated from the driver shown in Fig. 5a. the less the overshoot will be obtained. a 10-bit counter is adopted to ensure the a smooth soft-start [11]. 3/4ILpeak4 and then the typical current limit ILpeak4 is 1. QR the charge transferred to the load. to eliminate the noise of the signal Nsoft. When Nsoft returns to ‘‘0’’. RON 8Ia R1 ¼ ILpeak2 ¼ . when transition happens from soft-start phase to normal phase. 4.25 MHz switching frequency.13]. which may induce large burr in V2. On the other hand. during soft-start period. MP5 turns on to boost the voltage V2 to Vin waiting for the next sensing time. the control signal LD goes logic high to set code D0D1D2 to ‘111’ to end the soft-start. ILpeak is set constant and higher than the full current.ARTICLE IN PRESS 432 S. Simplified schematic of the synchronous voltage-mode buck converter with the proposed soft-start scheme. In conventional current-mode soft-start scheme. For different applications. Therefore. and the maximum counting period is TCOUNT ¼ T1 þ T2 þ T3 ¼ ð3 Â 2nc À2 À1ÞTs : ð3Þ result in voltage overshoot.

gm and gds denote transconductance and output conductance of a transistor. a folded cascode stage and a clamping stage [14]. The accuracy of . which are adequate to remove the large burr appearing in V2. The gain of the differential input stage is given by ! 1 .3. 8. (8) and (9).2 Þ R1. 7 show that the sampling delay td2 is around 10 ns and td1 is around 7 ns.2 Þ and the gain of the cascode stage is     1 1 1 : == ðgmðM9 Þ þ gmbðM9 Þ Þ ==R4 gmðM5.ARTICLE IN PRESS S. Current comparator The comparator is used to generate the over-current signal. It ensures the effectiveness of the current sensor with approximate zero DC power consumption. respectively. Li et al. ð8Þ gmðM1. shown in Fig. is implemented by a differential input stage. Simulation results as given in Fig. Fast response is needed to increase the control speed of the softstart stage. 4. Soft-start key waveforms under: (a) full load and (b) no load.6 Þ gdsðM11 Þ gdsðM9 Þ gdsðM6 Þ ð9Þ In Eqs. 2.2 == gdsðM1. / Microelectronics Journal 41 (2010) 430–439 433 Fig. This comparator.Z.

7. For the case without clamping. The simulation results show that the delay time has been reduced by 22% when the clamping stage is added. a driver with delicate control is necessary to provide buffer and dead-time control. 2. soft-start function stops working. M16 turns on and the voltage V1 is limited to V2 þ VSGðM16 Þ . Similarly. Current-sense circuit (a) the schematic (b) the logic. The 3. In addition. A6 are used to decrease the time needed for the gate voltage of M1 and M2 to rise and fall and to avoid the case that M3. Through the feedback signals at Vp and A2. a signal MNoff is also introduced to turn off M2 at light load to improve efficiency. N2 and Vsw. The clamping circuit is adopted to increase the speed of the comparator. When the clamping circuit is added. During normal state. When the drain voltage of the transistor M9 decreases to the level that can turn on the transistor M15. Buffer and dead-time control are needed to avoid shoot-through current loss. The timing of Nsoft. Driver In our design.6 V direct current voltage is put on the input in+. 10 shows the driver applied in our design. The divided voltage of Vo (Vfb) is sensed by Error amplifier (EA). 5. A5. power transistor M2 turns off. It will further increase the accuracy of the current sensor. 2. Fig. while those of Vn are only about 10 and 20 ns.7 to 2. Li et al. When the drain voltage of the transistor M9 increases to the level that can turn on the transistor M16. Vn is set to zero. 6. The simulation results show that the rise and fall times of Vp are only about 5 and 5 ns. Moreover. Vp is set to increase. M6 turn on simultaneously. The rectangle pulse with 500 ns width is connected with the input in À.Z.4. Vsw and V2. The basic principle is to use the feedback signals to control the gate driving signals such that the power transistors M1 and M2 do not turn on simultaneously. 10.ARTICLE IN PRESS 434 S. 11 shows the overall system. the range of V1 is from 0. A4. As Vo reaches the typical value. which is one kind of power losses in the switch mode converter [15]. The feedback signals at A3. respectively. N2. power transistor M1 turns on. Through the feedback signals at Vn and A1. the comparator is improved through high-gain amplification stage.6 V. System implementation Fig. power transistor M1 turns off. It results in that td1 and td2 can be observed as shown in Fig. Vp is forced to zero. the controller uses the output signal Nsoft of the soft-start circuit and oscillator output signal CLK to lift the output voltage. which will be discussed later. The simulated results of Nsoft. The output stage is used to increase the response of the comparator output signal. the signal NPWM and CLK are used to realize feedback control. The simulation results are shown in Fig. delay time exists between N2 and gate driving signals Vp and Vn.5. power transistor M2 turns on. M4 and M5. M15 turns on and the voltage V1 is clamped to Fig. Vn is forced to increase. respectively. the voltage V1 varies between 0 and 3. when Q is low. the driver generates the signal N2 to control the current sensor. Fig. 7. V3 ÀVGSðM15 Þ . When Q is high. and the dead-time is about 30 ns in this design. The output voltage of EA (Ver_out) is compared with saw tooth generator’s output signal Vramp to . During start-up. which control the voltage Vsw. / Microelectronics Journal 41 (2010) 430–439 Fig. From the schematic in Fig. The proposed soft-start circuit and power transistors have been integrated in the control chip of a DC–DC voltage-mode buck converter to reduce the cost.7 V. 9.

Moreover. Results and discussions The proposed soft-start circuit has been applied in a synchronous DC–DC voltage-mode buck converter with a standard 0. zero current detector (ZCD) is introduced to prevent inductor current from going negative at the boundary of continuous conduction mode (CCM) and discontinuous conduction mode (DCM).5 mA quiescent current. generate NPWM. which increases the reliability of the system. Waveforms of the comparator (a) without clamping and (b) with clamping. The upper edge of the signal CLK turns M1 on and as soon as Vramp exceeds Ver_out. This ZCD function can prevent the output capacitor discharge.5 mm CMOS process. Fig. which corresponds to about one twentieth of the total area of controller. Li et al. M1 is turned off. The proposed soft-start circuit occupies 0.6 V. including pads and ESD structures. Fig. All these features show that it is suitable for portable electronic devices. which are powered by battery. experiments have been performed to check the overshoot voltage. 3. 8. it adds current-limiting function. Fig. 3.06 mm2 on silicon. The input voltage of the converter is set to nominal value. Table 1 summarizes the post-simulation results for the main specifications of the proposed converter. 9. which is 3. The function of ZCD is to generate the signal MNoff to turn off M2 (M1 is closed already) when IL reaches zero [16]. Although the soft-start circuit introduces 53. The bandgap reference and bias circuits are included to generate voltage and current references of the controller chip. 12 shows the layout of the proposed controller. the output voltage is regulated at a stable value. Under the control. which will reduce the efficiency of converter.90 mm. / Microelectronics Journal 41 (2010) 430–439 435 Fig. .ARTICLE IN PRESS S. Its effective die area is 1. In order to verify the proposed soft-start technique.38 mm  0. Current comparator.Z. Signal LD is the internal signal of the soft-start circuit described in Fig. 13 shows the post-simulated key waveforms with the proposed soft-start scheme under no load and full load.

. ILpeak4/2. As soon as the output voltage climbs to Vtyp. / Microelectronics Journal 41 (2010) 430–439 Fig. Block diagram of overall system. The switch current is designed in steps of typically ILpeak4/4. the inductor peak current is limited step by step.8 V in our design. 11. the less the start-up time is. 10. Fig. 3/4ILpeak4 and then the typical current limit ILpeak4 is 1.Z. and when the converter enters in the normal state. Schematic of the driver. 1. CLK and the output signal NPWM of the PWM comparator control the switching of the power transistors.6 A. The lighter the load is. LD will change from logical low to high to end the soft-start process.3 A load current. Fig. The maximum start-up time of the converter is around 760 ms with 22 mF output capacitor under 1. 14 shows the post-simulated output voltage and inductor current of the same voltage-mode buck converter under conventional current-mode soft-start method described in Fig. The clock signal CLK and the output signal Nsoft of the soft-start circuit control the switching of the power transistors to transfer energy to the output. The results show that the start-up time can be intelligently adjustable by load current. The HSPICE simulation results show that the output voltage can stably start-up until the output voltage sets up. A comparison of start-up process is made using two soft-start methods. which is 1. Li et al. The results show that during soft-start.ARTICLE IN PRESS 436 S.

8 V. A comparison of overshoot is made using two soft-start methods mentioned above. Li et al.5 mA of current comparator) As a remark. . Conclusion This paper presents a compact soft-start scheme applied to voltage-mode DC–DC converters.5 mm CMOS technology.Z.6 V) 0.ARTICLE IN PRESS S. The soft-start circuit including low-power current sensor.8 V 1. Table 1 Overall chip performance.5 mA (16 mA of DAC-controlled current reference.6 A. when the load current decreases. Therefore.3 A 92% (max at Vin ¼ 3.7% at ILOAD ¼0 A) by the novel soft-start scheme is less than that with the conventional scheme by 5%.6 V) 350 mA 53.2 O (at VGS ¼3. The maximum overshoot (2. ILOAD ¼300 mA) 4. The overshoot curve ‘‘b’’ is obtained when the conventional current-mode method is applied.6–5. Fig. To further verify the improvement in the proposed soft-start technique. 37. The overshoot curve ‘‘a’’ is obtained based on the proposed soft-start scheme.3 O (at VGS ¼3.5 V 1. However. The layout of the proposed converter. Compared to conventional constant ILpeak control. fast current comparator and driver with delicate control has been designed and fully integrated. output voltage overshoot becomes large. The results show that the output voltage can stably start-up under full load. 12. / Microelectronics Journal 41 (2010) 430–439 437 Fig. Vo ¼1. which is realized through fixing the high bits of the counter (Qnc À2 Qnc À1 ) ‘11’ during the whole soft-start process in our design. Parameters Input voltage range (Vin) Output voltage Maximum output current Efficiency External inductance L1 External capacitance C1 External divided resistors Switching frequency Ripple voltage MOSFET model MOSFET sizing Rds (PMOS) Rds (NMOS) Input DC bias current DC bias current of soft-start circuit Results 2. 180 KO for R2 1.60 mm  0. 15 shows the simulated overshoot of the output voltage as a function of the output current. The results show that the overshoot voltage has been largely reduced in a wide range of load currents.80 mm 0. DAC-controlled ILpeak control is adopted to largely reduce the overshoot voltage. The proposed soft-start scheme has been successfully implemented and verified with a buck converter in a 0. 4. experiments are in good agreement with the theoretical analysis that introducing DAC-controlled soft-start circuit can effectively reduce the output voltage overshoot of the converter and ensure smooth output voltage when the converter starts up. the typical current limit ILpeak is also set to 1. especially when the load current is zero.25 MHz 30 mv (PWM) BSIM3V3 model (Normal Voltage) 0.6 V.7 mH 22 mF 470 KO for R1.

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