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A THESIS SUBMITTED TO THE GRADUATE SCHOOL OF NATURAL AND APPLIED SCIENCES OF MIDDLE EAST TECHNICAL UNIVERSITY

BY

ABDULLAH VOLKAN PEK

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN ELECTRICAL AND ELECTRONICS ENGINEERING

OCTOBER 2006

Approval of the Graduate School of (Name of the Graduate School)

Prof. Dr. Canan ÖZGEN Director

I certify that this thesis satisfies all the requirements as a thesis for the degree of Master of Science.

Prof. Dr. smet ERKMEN Head of Department

This is to certify that we have read this thesis and that in our opinion it is fully adequate, in scope and quality, as a thesis for the degree of Master of Science.

Prof. Dr. Mete SEVERCAN Supervisor Examining Committee Members (first name belongs to the chairperson of the jury and the second name belongs to supervisor) Prof. Dr. Yalçın TANIK Prof. Dr. Mete SEVERCAN Assoc. Prof. Dr. Sencer KOÇ (METU, EE) (METU, EE) (METU, EE)

Assist. Prof. Dr. Çağatay CANDAN (METU, EE) Ülkü DOYURAN (ASELSAN)

I hereby declare that all information in this document has been obtained and presented in accordance with academic rules and ethical conduct. I also declare that, as required by these rules and conduct, I have fully cited and referenced all material and results that are not original to this work.

Name, Last name : Abdullah Volkan PEK Signature :

iii

FPGA iv . the implementations of the monopulse amplitude comparison and phase comparison DF algorithms are performed on an FPGA platform. Block diagrams of the hardware implementations are given and explained in detail. Using the results of the simulations. Department of Electrical and Electronics Engineering Supervisor : Prof. 83 pages In this thesis work. Then simulations of hardware implementation of both algorithms are performed. Then the algorithms are implemented on an FPGA platform by utilizing platform specific software tools. DF accuracies under certain conditions are evaluated and compared to software simulations results.S.. Mete SEVERCAN October 2006.ABSTRACT IMPLEMENTATION OF A DIRECTION FINDING ALGORITHM ON AN FPGA PLATFORM PEK. Phase Comparison. Keywords: Direction Finding. Amplitude Comparison. After the mathematical formulation of the algorithms using maximum-likelihood approach is done. Interferometer. software simulations are carried out to validate and find the DF accuracies of the algorithms under various conditions. Abdullah Volkan M. Dr.

Genlik Karşılaştırma.ÖZ YÖN BULMA ALGOR TMASININ FPGA PLATFORMUNDA UYGULANMASI PEK. yazılım benzetim sonuçları ile karşılaştırılmıştır. Faz Karşılaştırma. Dr. genlik karşılaştırmalı ve faz karşılaştırmalı yön bulma algoritmaları FPGA platformunda gerçeklenmiştir. yazılım benzetimleri yapılarak algoritma geçerli kılınmış. Abdullah Volkan Yüksek Lisans Tezi. Her iki algoritmanın donanım uygulamasının benzetimi yapılmıştır. 83 sayfa Bu tez çalışmasında. Daha sonra platforma özel yazılım araçları kullanılarak algoritmalar FPGA platformunda uygulanmıştır. Benzetim çalışmalarının sonuçları kullanılarak belirli koşullar altındaki yön bulma doğruluğu değerlendirilmiş. Anahtar Kelimeler: Yön Bulma. Maksimum olabilirlik yaklaşımı kullanılarak algoritma matematiksel olarak formüle edildikten sonra. Donanım uygulamalarının blok şemaları verilerek detaylı bir şekilde anlatılmıştır. farklı durumlarda algoritmaların yön bulma doğrulukları bulunmuştur. FPGA v . Elektrik ve Elektronik Mühendisliği Bölümü Tez Yöneticisi : Prof. Mete SEVERCAN Ekim 2006.

To My Parents and To My Lovely Sister vi .

I would like to thank my parents for bringing up and trusting in me. Thanks a lot to all my friends for their great encouragement and their valuable help to accomplish this work. vii . for the resources and facilities that I use throughout thesis. Lastly. support and tolerance throughout the development and improvement of this thesis. I am also grateful to Aselsan Electronics Industries Inc. for giving me the strength and courage to finish this work. Dr. and Demet Salman. Metin Şengül and Serkan Sevim for their support throughout the development and the improvement of this thesis.ACKNOWLEDGMENTS I would like to thank Prof. I am grateful to Turgut Çelikadam. Mete Severcan for his valuable supervision.

...................................2 3.xiv CHAPTERS 1.............................. vii TABLE OF CONTENTS..............................x LIST OF FIGURES ................................................................................................................................3 Amplitude Comparison DF Systems ...... INTRODUCTION .........................................................15 3..........3.....v ACKNOWLEDGMENTS..........8 Phase Comparison Algorithm ...................................1 1...............................................................3.......1.....................................1...............................................................................1...........................17 2nd Approach....................1...............................2 Monopulse DF Systems............................................................7 Amplitude Comparison Algorithm.....................................3 2.............1.................. viii LIST OF TABLES......................................2........ DF ALGORITHMS ................1 3...............17 1st Approach .......2 3.................1 1..............1......................25 viii 3....................................................................1 The meaning of Monopulse ............................2 3...................................23 Hardware Implementation...........................20 Comparison of Approaches .....4 1.............1......................................................................3 Interferometer DF Techniques ................................................................8 3.................................................................TABLE OF CONTENTS ABSTRACT .......................................................................... iv ÖZ ........................................................ IMPLEMENTATION ...........................................2 1......................................................................................................15 Software Simulation Results ................................................... xi LIST OF ABBREVIATIONS .............1 Description of the Thesis .................................................2 1........................1 1..................................11 Amplitude Comparison...............................................................1 ...............................................................................................5 2..........1 3...1.............................................3 Direction Finding .............................................1...................................................................................24 Hardware Design ..1 2.......................4 1.7 Outline of the Thesis ........................................

...............80 ix .......................2.4 Simulation Results .................53 Phase Comparison ......2............2......................................................................77 B...............6 PC_Function_Calculation Block .........................................................2.............3.....................55 3...................2..80 C.................59 Part of PDW Generator Design ......1............1 Development Tool Flow ............3 Simulation Results ...........................1.........52 Hardware Design ............................................................58 3................1 Simulation Results ..........................................1 3.......1.........31 3........67 3............................2...............................2......................................2.....................1.............................3.............................................................4 PC_Angle_Counter Block ........................1.....................2..................44 Hardware Implementation....34 Software Simulation Results ....................................75 APPENDIX B...............2...........73 APPENDICES...............2..........................26 3...............................................3 AC_AOA_Estimator Block..................1................2......1...................75 A.1.............2.........................................................................................2.....2 3....33 3...................2........................77 APPENDIX C.....................63 3..........2..........39 3..............1.........................1..........................................................................................................................................................2.........2..................................2 3..............................3..........................1..1...............................................80 C......56 3....................................2 3.1...1..................2.................2.........68 4............64 3...............75 APPENDIX A ......................2 Xilinx System Generator ..5 PC_Address_Decode Block ... CONCLUSIONS ......................54 3..............6 Magnitude_Calculator Block......................................2 AC_Correlation_Computation Block...2 3.............................................2.....................................1 FPGA’s ......1.........................................................2.....7 PC_AOA_Estimator Block................5 I_ Q_Demodulator Block .....................................................1 Antenna Gain Pattern .............70 REFERENCES ..................1 AC_Angle_Counter Block ..............................

..........................37 Table 3-4 FPGA Resource Utilization Summary of Amplitude Comparison Implementation..20 Table 3-2 Mean and Standard Deviation of RMS Error (2nd Approach)............................................LIST OF TABLES Table 3-1 Mean and Standard Deviation of RMS Error (1st Approach).........69 x ............................................38 Table 3-5 FPGA Resource Utilization Summary of Phase Comparison Implementation.............................................................................................................................................................62 Table 3-6 Mean and Standard Deviation of RMS Error of Estimated AOA .................22 Table 3-3 Mean and Standard Deviation of RMS Error for Amplitude Comparison Hardware Implementation..............................................

.................................24 Figure 3.....16 Logic Diagram of the AC_Correlation_Computation Block ......27 Figure 3.....16 Figure 3.....................................31 Figure 3.. 25dB and 30dB ) ...............5 Figure 2................................ 25dB and 30dB) ..6 RMS Error vs.................................2 Amplitude Comparison Antenna Gain vs...........30 Figure 3......................33 Figure 3............................19 Figure 3...........14 Logic Diagram of AC_Address_Counter Block.............15 Search Interval for Amplitude Comparison Implementation ..................5 RMS Error vs.........................................1 Block Diagram of the Amplitude Comparison DF System..4 RMS Error vs.........................................21 Block diagram of the Phase Comparison DF system.............................................2 Phase Array Geometry .....................19 RMS Error vs AOA of Amplitude Comparison Hardware Implementation at 20dB SNR .............1 Circular Array Geometry (N=6) ......8 RMS Error vs....................................11 Figure 3..........20 RMS Error vs AOA of Amplitude Comparison Hardware Implementation at 30dB SNR ..........17 Logic Diagram of AC_AOA_Estimator Block .......1 Harmonic Binary Related Interferometer...11 Logic Diagram of AC_Angle_Counter Block.......................................... AOA (SNR is equal to 20dB.......9 Mean of RMS Error vs.......3 RMS Error vs........26 Figure 3...................... AOA (SNR is equal to 10dB and 15dB)... Angle .......................... AOA (SNR is equal to 10dB and 15dB).....36 Figure 3......18 Screen Shot from System Generator (Implementation of Amplitude Comparison) ..........................35 Figure 3. AOA (SNR is equal to 35dB and 40dB)...................12 Logic Diagram of AC_Max_Amplitude_Finder Block ......18 Figure 3.........29 Figure 3......................LIST OF FIGURES Figure 1...........13 Logic Diagram of AC_Max_PA_Selector Block ............................................ AOA (SNR is equal to 20dB.............................7 RMS Error vs..21 Figure 3..............................................39 xi .....8 Figure 2....36 Figure 3.......31 Figure 3......... AOA (SNR is equal to 35 dB and 40dB).............................................10 Block Diagram of the Amplitude Comparison Implementation...17 Figure 3.................19 Figure 3.........28 Figure 3............ SNR...22 Figure 3....21 Figure 3............................

................ AOA at d / λ value from 1 to 5 in steps of 0............ Frequency when fresolution=64 MHz (AOA=30 degrees)..........................................40 Logic Diagram of PC_Function Calculation Block.59 xii ....................................................44 Figure 3.................. d / λ Values for SNR=10dB................................................33 Mean of the RMS Error vs.. ............54 Figure 3...........................................................49 Figure 3...28 Phase Comparison RMS Error vs...........................................47 Figure 3....................................................43 Figure 3.......................30 Phase Comparison RMS Error vs......................................................................................................................43 Logic Diagram of the PC_AOA_Estimator Block ......39 Logic Diagram of the PC_Address_Decoder Block .....38 Logic Diagram of the PC_Angle_Counter Block......5 (SNR = 20 dB) .................................... Frequency when fresolution = 100 MHz (AOA=30 degrees).....56 Figure 3.............................. AOA at d / λ value from 1 to 5 in steps of 0.................. Frequency at SNR=20dB...........................42 Figure 3..........................................................................42 Logic Diagram of Complex_Multiplier_2 Block .................26 Typical Plot of J ' (φ ) vs..........43 Figure 3...... Frequency when fresolution = 50 MHz (AOA=30 degrees)...........58 Figure 3..34 The RMS Error vs...........22 Single Baseline Interferometer ..58 Figure 3..............................32 RMS Error vs.24 Real and Imaginary parts of Phase Comparison for d/λ=2 .............55 Figure 3....45 Figure 3....................41 Figure 3.......................................51 Figure 3.35 The RMS Error vs....27 Search Interval for Phase Comparison.........29 Phase Comparison RMS Error vs...31 Mean of RMS Error vs................36 The RMS Error vs...............5 (SNR = 30 dB) .........44 Screen Shot from System Generator (Implementation of Phase Comparison Algorithm) ....49 Figure 3...........................40 Figure 3.....23 Phase Comparison Antenna Layout... AOA when Frequency is varied from 2 GHz to 6 GHz in steps of 500MHz at SNR = 20dB...............52 Figure 3.........................51 Figure 3.37 Block Diagram of Phase Comparison Implementation.............Figure 3.....5 (SNR = 10 dB) ..............................46 Figure 3........ AOA for d / λ = 1 and d / λ = 5 (AOA=35) . 20dB and 30dB ..46 Figure 3.............. AOA at d / λ value from 1 to 5 in steps of 0.........................41 Logic Diagram of Complex_Multiplier_1 Block .............25 Phase Comparison Antenna Gain and Phase Pattern for d/λ=2.......57 Figure 3.................................................53 Figure 3.......................

...................51 Logic Diagram of I and Q Demodulator Block ......................................67 Figure 3.............54 Logic Diagram of Magnitude_Calculator Block .................................................Figure 3.....52 Magnitude Response of FIR Filter (Hilbert Transformation) ..............................................................1 Generated Antenna Pattern for Amplitude Comparison ......1 Virtex Family FPGA Logic Slice.......64 Figure 3.................47 Mean of the Estimated AOA vs.....61 Figure 3...78 Figure C............................... Frequency................................................48 RMS Error of Hardware Implementation due to Frequency Quantization ......................46 Mean and The Standard Deviation of RMS Error .......1 Function Block Parameters of a Xilinx Multiplier Block...68 Figure A...................53 Magnitude Response of FIR LPF ............................65 Figure 3................ AOA (SNR=20dB)......76 Figure B........55 Block Diagram of the Phase Comparison Implementation .82 xiii ..........................................49 Block Diagram of Phase Comparison Implementation............................66 Figure 3..............................65 Figure 3............66 Figure 3........60 Figure 3...............62 Figure 3.....50 I and Q Demodulation ...........................................45 Phase Comparison Hardware Implementation RMS Error vs........................................61 Figure 3..........................

LIST OF ABBREVIATIONS AC : Amplitude Comparison ADC : Analog to Digital Converter AOA : Angle of Arrival CW DF DSP FIR : Continuous Wave : Direction Finding : Digital Signal Processing : Finite Impulse Response DOA : Direction of Arrival ESM : Electronic Support Measures FPGA : Field Programmable Gate Arrays GSPS : Giga Samples per Second LPF : Low Pass Filter MPPS : Mega Pulse per Second MSPS : Mega Samples per Second PC PRI RF : Phase Comparison : Pulse Repetition Interval : Radio Frequency PDW : Pulse Descriptor Word RMS : Root Mean Square RWR : Radar Warning Receivers SNR : Signal to Noise Ratio TOA : Time of Arrival UCA : Uniform Circular Array ULA : Uniform Line Array xiv .

which can be calculated from the bearings of several direction finders.1 Direction Finding The ultimate aim for the Electronic Support Measurement (ESM) system is to identify the RF guided weapon. since emitters cannot change on pulse to pulse basis. Obviously the interactions between these parts must not be ignored. First the ESM system intercepts the radiations associated with that weapon. Choice of the array geometry and antennas. multiple antennas are arranged in various geometrical configurations. A direction finder is a passive device that determines the direction/angle of arrival (DOA/AOA) of radio-frequency energy [2]. Determining the DOA or AOA of signal is fundamental to ESM systems. Then the parameters of the selected signals are measured.CHAPTER I INTRODUCTION 1. sensitivity to system errors and the type of processing used to . Finally the weapon is identified by previously identified definitions of the weapons. There are many factors that should be considered in direction finding problem. Array geometry affects various aspects of the DF system such as resolution. the receiver structure and the optimum algorithm that is employed can be considered as main factors. Purpose of direction finding operations is to detect the position of the emitter. The antenna pattern and polarization are important parameters that affect the DF accuracy of the system. and then separates these signals from other intercepted signals. ESM system compares the parameters against a stored set of parameters to identify the type of the sensor. the ESM system provides information on the angular direction of the intercepted signal [1]. In DF systems. In the process of identifying the RF guided weapon. The general procedure of the identification against RF guided weapons can be summarized as follows.

It becomes very common because it clearly expressed the ability to collect. 1. whereas the older angle-sensing techniques of conical scan and lobe switching required several (at least four) pulses to form a pair of angle estimates. and be able to process as large as pulses per second to find the AOA. The structure which the elements are arranged uniformly around 360º in azimuth is called as a uniform circular array (UCA). Budenbom of the Bell Telephone Laboratories in 1946. because mono meaning one comes from Greek. The most commonly considered structures are the linear and circular arrays.produce DOA estimates. High resolution methods are more complex compared to monopulse. Uniform Line Array (ULA) is implemented with inter-element spacing less than or equal to λ/2. eigenvalue and eigenspace computations. 2 . The importance of non-uniform line array structures is that they are considerably more robust as compared to ULA’s with respect to their radiation characteristics. A linear array does not provide uniform resolution capability over the entire horizon. simpler. from each pulse. provide fast responses.T. which is an important drawback for many practical systems. the elements of an array are identical. They are based on correlation matrix. the information needed for a pair of two coordinate angle estimates. In most arrays. monopulse systems should operate in real time. There are various approaches to estimate the angular location of the emitter. UCA geometry is one of the most commonly used array geometry in DF systems [3]. while pulse comes from Latin. Computational costs of these methods are higher. It is a hybrid word. where λ is the wavelength at the center frequency. Antenna spacing over the specified geometry can be selected to be uniform or non-uniform. and more practical. which is often more convenient. One of the main advantages of a circular array over linear arrays is its 360º azimuthal coverage which is very important especially in ESM applications. The most commonly used methods are monopulse and high resolution methods. On the other side.2 The meaning of Monopulse It is stated in [4] that the word monopulse was first introduced by H.

The monopulse ratio is obtained by subtraction of the detected logarithmic signals.3 Monopulse DF Systems The two primary techniques used for monopulse direction finding are the amplitudecomparison method and the interferometer or phase comparison method.The term simultaneous lobing. and the bearing is computed from the value of the ratio [1]. It can be used passive mode to track a source of signals or noise such as transmitting antenna. Typically. most monopulse radars do not extract angle estimates from each pulse. information about amplitude and phase comparison systems will be given. but the amplitude-comparison method is used extensively due to its lower complexity and cost. which utilize squinted antenna elements that are usually equidistantly spaced to provide an instantaneous 360º coverage. from a pair of independent receiving channels. monopulse is not confined to pulsed radars.1 Amplitude Comparison DF Systems Virtually all currently deployed radar warning receiving (RWR) systems use amplitude-comparison direction finding. In amplitude comparison. 1. It is the simultaneity rather than “one pulse” that is essential. a jammer or the sun [4].3. Gaussian-shaped 3 . 1. and ultimately angle-of-arrival or bearing. A basic amplitude-comparison receiver derives a ratio. In the following chapters. although it is less commonly used. It can be used just as well in Continuous Wave (CW) or modulated CW radars. and wideband logarithmic video detectors provide the signals for bearing-angle determination. four or six antenna elements and receiver channels are used in such systems. As a matter of fact. typically broadband spiral antenna elements whose patterns can be approximated by Gaussian-shaped beams are used. synonymous with monopulse. The phasecomparison method generally has the advantage of greater accuracy. Furthermore. The usual practice is to smooth or integrate the raw single-pulse signals over some interval before forming the angle estimates. is a more accurate description of the technique.

The concept of using phase difference of the received signals can be used with circular array structures to cover 360 degrees azimuth from antennas mounted at a point. depending upon the RF octave band utilized [1]. Partial compensation of these effects. The difference of TOA will lead to a measurable phase difference.3. which is used for determination of the angle of arrival (AOA) information. gross compensation can be made. It is stated in [5] that the typical accuracies can be expected to range from 3 to 10 degrees RMS for multi-octave frequency band amplitude-comparison systems which cover 360 degrees with four to six antennas. including antenna squint. Usually. expanding to eight antennas would double the accuracy and provide 3 dB more gain. and low cost. Otherwise. As the number of antennas increases. Pattern shape variations cause a larger pattern crossover loss for high frequencies and reduced slope sensitivity at low frequencies. All antenna elements center may lie in a straight line at equal spacing (ULA) or at different spacing to obtain time of arrival (TOA) difference of the incoming waves. which result from the broad-beam antennas employed. reliability. The four-quadrant amplitudecomparison DF systems employed in RWRs have the advantage of simplicity. Both accuracy and sensitivity can be improved by expanding the number of antennas employed. both the antenna beamwidth and squint angle vary with frequency over the multi-octave bands used in RWRs. 1. a digital look-up table can be used to determine the angle directly.beams have the property that the logarithmic output ratio slope in dB is linear as a function of angle of arrival. it becomes appropriate to consider multiplebeam-forming antennas rather than just increasing the number of individual antennas. The disadvantages are poor accuracy and sensitivity. can be implemented using a look-up table if frequency information is available in the RWR.2 Interferometer DF Techniques Interferometer can be considered as specific cases of antenna arrays. However. 4 . Thus. only one antenna per quadrant is employed which covers the 2 to 18 GHz band. For example.

it limits the system sensitivity due to reduced antenna gain. An interferometer system consisting of two antennas in space causes an ambiguity in determination of AOA. however it is not clear from which half of the hemisphere the signal originated.1 Harmonic Binary Related Interferometer 5 . First. It is stated in [1] that the lack of directivity produces several deleterious effects. A harmonic binary related interferometer system divides each aperture baseline by a factor of 2 is given in Figure 1. spaced in line and located at different distances from the reference antenna in order to operate together. there are two types of choice of antenna element location. In multiple baseline interferometer systems. Practical interferometer systems solve this problem by using another system such as an amplitude monopulse DF system to select proper estimate of DOA or use quadrant arrays of antennas shielded from each other. called multiple baseline interferometers.1. Another method to resolve ambiguities is to use a multiple antenna elements. Second. In a typical design of multiple baseline interferometers. The system has coverage of 180 degrees in azimuth.Interferometer system antennas typically use broad antenna beams with beamwidths of the order 90 degrees. or a circular array of monopulses to cover a 360 degree field of view [6]. Figure 1. it open the system to interference signals often include multipath from strong signals which can limit the accuracy of the interferometer. there exists a reference antenna and a series of companion antennas.

In non-harmonic related spaced antennas. which is not necessarily λ / 2 . At the defined SNR value. it would only require a SNR of 20dB to achieve 0. it will provide a DF accuracy of 3 degrees. the angle of arrival can be determined. and in the event of single target in additive white Gaussian noise. In this configuration. When high DF accuracy is needed in an interferometer system. Within the 33 lobes. forming a λ / 2 baseline. ambiguity will be resolved by employing a third antenna element with λ / 2 baseline spacing. And the binary system is limited at the high-end frequency range to half-wavelength baseline spacing. solves the ambiguity problem and determines the AOA. In the selected quadrant. since it has a wide RF bandwidth of coverage. which requires less signal to noise ratio (SNR) to achieve same the DF accuracy. and then the next pair improves the resolution and achieves a better determination. For a two element interferometer with 16 λ spacing would end up 33 lobes through ±90 degree azimuth coverage. first antenna pair. the non uniform arrays found to provide significant improvement over arrays of the same number of elements which shows the importance of array geometry. is determined up to frequency to solve the ambiguity problem. The process continues up to longest baseline. Also it is stated in [3] that the performance of uniform and different nonuniform LA structures are compared. Although there are 33 ambiguous regions on the coverage range.1 degree accuracy [1]. The non-harmonic related spacing is more preferred to harmonic-binary related spacing antennas. the antenna element spacing.The number of ambiguities is increased as the spacing to the reference antenna is increased. alternatively antenna baseline spacing can be increased. knowledge of spacing or spacing ratios and the frequency of the incoming signal and utilization of look up tables and some logic algorithms. Nevertheless. ambiguities will be presented at many frequencies. which is sufficient to solve the ambiguity [1]. 6 . The increased baseline spacing results in multilobe structures along the coverage range.

the problem is constrained to estimate the DOA’s in azimuth only. baseline spacing etc. The sources and the antennas are assumed to be coplanar. along with the discussions related to the effects of different parameters. to solve the problem of estimating direction of arrival (DOA) of plane waves impinging on the antennas from unknown direction are employed. The implementation details of the design. namely amplitude comparison and phase comparison.5 Outline of the Thesis This thesis is organized as follows: In Chapter II. the root-mean-square (RMS) errors at different angles and various conditions are calculated. two algorithms based on monopulse DF techniques. Amplitude comparison and phase interferometer techniques are studied in this work by employing maximum likelihood estimation approach. Moreover some concluding remarks of these algorithms and hardware implementations are discussed in Chapter IV. Typical results of the software simulations are presented. discussions and comparisons of the simulation results of the algorithms are explained in detail. modifications and practical advantages related to the implementation of this algorithm on an FPGA platform are also discussed. Finally. in order to investigate the performance of the proposed algorithms. The algorithms are implemented on an FPGA platform and simulation results are obtained by varying parameters such as SNR.1. the amplitude comparison and phase interferometer DF algorithms based on ML estimation are developed and described in detail. Some practical limitations. assumptions. and therefore. both monopulse DF algorithms are summarized.4 Description of the Thesis In this work. The results of the implementation are compared with the expected values. In Chapter III. 1. the problem is stated and formulated. 7 .

1. It is assumed that there is a single transmitter and the signal arrives at the antenna at angle of θ .CHAPTER II DF ALGORITHMS 2.1 Circular Array Geometry (N=6) 8 .1 Amplitude Comparison Algorithm The DF system considered in this part consists of a circular array of N equally spaced antennas. The geometry of the antennas (for N=6) is given in Figure 2. Figure 2.

The probability density function (pdf) can be expressed as f ( A. since the maximum likelihood function is a monotonic function. θ = arg max ( f ( A. the problem is to estimate θ by using observations of the received signals si’s. which maximizes the joint density function.The received signal is defined by si = ARi (θ − θ i ) + ni Ri ( (2-1) where θ and A represents AOA and amplitude of the incoming signal respectively.2…N) antenna. θ i is the angular position of the ith (i=1. ) denotes the power pattern of the antenna. which is given by (2π / N )(i − 1) and ni is the receiver noise. θ )) θ (2-4) Maximizing the maximum likelihood function is equivalent to minimizing the negative of logarithm of it. θ ) = ∏ i =1 N 1 2πσ 2 − ( si − ARi (θ −θ i ))2 2σ 2 e (2-3) The maximum likelihood estimation for parameter θ is the estimate. First assumption is that the additive noise is assumed to be white Gaussian noise of variance σ 2 .θ )= ∑ (si − ARi (θ − θ i )) i =0 N −1 2 (2-5) 9 . two assumptions are made. By eliminating constant terms. Second one is that the additive noise of each receiver channel is independent of each other. The Gaussian distributed random variable having zero mean and a variance of σ 2 has the density function of the form f (x ) = 1 2πσ 2 − x2 2σ 2 e (2-2) Since random variables are independent from each other. their joint density function is the product of the densities for each Gaussian variable. At that point. the equation can be rewritten as J ( A. In this case.

θ )) θ (2-6) The maximum likelihood estimation is function of A and θ . θ = arg max(M (θ )) θ (2-11) 10 . Taking derivative of Eq.Therefore the estimate θ can be obtained by minimizing J as θ = arg min ( J ( A. which is not a function of θ . In order to find the minimum point of the function. a derivative with respect to A is taken and set to zero.(2-5) with respect to A yields to ∂J ( A. Rearranging the equation yields N −1 ∑ si Ri (θ − θ i ) M (θ )= i =0 2 ∑ R (θ − θ ) 2 i i i =0 N −1 (2-10) The AOA can be estimated by the value that maximizes M (θ ) . can be eliminated.(2-5) yields to N −1 ∑ si Ri (θ − θ i ) N −1 2 0 J (θ )= ∑ si − i =N −1 i =0 ∑ Ri2 (θ − θ i ) i =0 2 (2-9) Since main concern is the minimization of the Eq.(2-9) with respect to θ . the first term. θ ) N −1 = ∑ − 2 si Ri (θ − θ i ) + 2 ARi2 (θ − θ i ) = 0 ∂A i =0 ( ) (2-7) ˆ A= ∑ (s R (θ − θ )) i i i i =0 N −1 i =0 N −1 ∑ Ri2 (θ − θi ) (2-8) Substituting the estimate of A in Eq.

The array geometry of the antennas is given in Figure 2.2. 2). g (φ ) is the antenna pattern and ni is the receiver noise of the ith antenna (i=1. A is the amplitude and θ is the phase of the incoming signal.2 Phase Array Geometry The signals arriving to antennas at angle of φ are given by s= Ae jθ g (φ ) + n1 (2-12) d = Ae jθ e jψ g (φ ) + n2 (2-13) where.2 Phase Comparison Algorithm The DF system considered in this study consists of a linear phase array of two antennas. 11 . which are assumed to have identical gain patterns. φ ds in (φ ) φ x Figure 2.2. ψ is the phase difference between the signals arriving to the antennas.

(2-2). the maximum likelihood function becomes J ( A. The probability density function (pdf) is given by f ( A. φ ) = s − Ae jθ g (φ ) + d − Ae jθ h(φ ) 2 2 (2-19) 12 . h(φ ) is defined as h(φ ) = e jψ g (φ ) (2-14) Substituting Eq.θ . φ = arg max ( f ( A.(2-14) in Eq. The maximum likelihood estimate for parameter φ is the one which makes the given observations the most likely.(2-13).(2-12) and Eq. Therefore their joint density function is the product of the densities for each Gaussian variable. φ ) = 1 2πσ 2 − s − Ae jθ g (φ ) 2σ 2 2 e 1 2πσ 2 − d − Ae jθ h (φ ) 2σ 2 2 e (2-17) The principle is the same for all maximum likelihood estimation problems. φ ) .In order to make Eq. 2) is assumed to be white Gaussian noise with noise samples being independent of each other and having identical variances σ 2 . there are two independent random variables. θ . (2-17) is equivalent to minimizing the negative logarithm of the likelihood function.φ )) ϕ (2-18) Since logarithm is a monotonic function. The Gaussian distributed random variable having zero mean and a variance of σ 2 has the density function given in Eq.θ .θ .(2-13) more compact. In this case. it is the value that maximizes f ( A. received signals are redefined as s= Ae jθ g (φ ) + n1 (2-15) d = Ae jθ h(φ ) + n2 (2-16) The additive noise ni (i=1. In other words. By eliminating constant terms of the function. maximizing the Eq.

derivatives of the function must be taken with respect to A.θ . θ .(2-26) in Eq. θ and set to 0.jθ g * (φ ) + s*e jθ g (φ ) − (se .e . φ ) .φ )) φ (2-20) As it is observed in Eq.jθ h * (φ ) + d *e jθ h (φ ) =0 ∂θ ∂θ ∂θ ( ) ( ) (2-23) Simplifying and rearranging the terms yields to Im e − jθ sg * (φ ) + dh* (φ ) = 0 { ( )} (2-24) Since the imaginary part of the equation is zero. φ ) with respect to A and setting to 0 yields to ∂J ( A. φ = a rg min ( J ( A.θ . Taking derivate of J ( A. it can be rewritten as sg * (φ ) + dh* (φ ) = Ke jθ + jkπ (2-25) The estimated value of θ can be simplified as θˆ = arg(sg * (φ ) + dh* (φ )) (2-26) The estimate of A can be further simplified by substituting Eq. φ ) 2 2 = 2 A g (φ ) + 2 A h(φ ) − 2 Re se − jθ g * (φ ) − 2 Re de − jθ h * (φ ) = 0 ∂A { } { } (2-21) -jθ * -jθ * ˆ Re{s.g (φ )}+ Re{d.h (φ )} A= | g (φ ) | 2 + | h(φ ) | 2 (2-22) Taking derivate of J ( A.φ ) with respect to θ and setting to 0 yields to ∂J ( A. φ ) ∂ ∂ =− (se . the maximum likelihood estimation function is a function of A. θ .θ .(2-22) as ˆ A= sg * (φ ) + dh * (φ ) | g (φ ) |2 + | h(φ ) |2 13 (2-27) .Now the maximum likelihood problem can be estimated by the value that minimizes J ( A.(2-19). To estimate AOA.e .θ . θ and φ .

rearranging and simplifying gives J ( A. φ ) = s + d − 2 2 sg * (φ ) + dh * (φ ) 2 | g (φ ) | 2 + | h(φ ) | 2 (2-28) Since the magnitude of the complex signals are constant and constitute a DC value.(2-27) in J ( A. φ . φ ) . is estimated by the value which maximizes the maximum likelihood function J / (φ ) . the equation can be further simplified by eliminating the constant non-negative terms. sg * (φ ) + dh * (φ ) 2 φ = arg max 2 2 φ | g (φ ) | + | h(φ ) | (2-30) 14 . direction of arrival. 2 J / (φ ) = sg * (φ ) + dh * (φ ) | g (φ ) |2 + | h(φ ) |2 (2-29) In this method. θ .θ .Substituting the estimate of A found in Eq.

pulse amplitude. The purpose of this block is to extract the properties of the received signal. like frequency. The angle between the beam axes of two adjacent antennas is 60 degrees. It is assumed that there exists a Pulse Descriptor Word (PDW) Generator block. The block diagram of the system is given in Figure 3. Then pulse amplitudes of the received signal from each receiver channel are input to the amplitude comparison block. The DF system is designed to have six receiver channels following the antennas. The signals received by the antennas pass through RF sections and are sampled by Analog to Digital Converters (ADC).CHAPTER III IMPLEMENTATION 3. pulse width etc. they are directed to FPGA. implemented on FPGA platform. 15 . After the received signals are sampled by ADCs. The antennas are assumed to have identical antenna gain patterns.1.1 Amplitude Comparison The amplitude comparison system implemented in this work consists of six antennas uniformly located around a circular axis to have azimuth coverage of 360 degrees.

The gain pattern of the antennas is given in Figure 3. 16 . The specifications of the generated antenna pattern are given in Appendix A. gain pattern of the antennas are not identical in practical DF systems. Moreover. In this work.2. However. ideal antenna gain pattern is generated and utilized. the errors due to different operating frequencies and pattern mismatches are not handled. Throughout the experiments single operating frequency is considered. In this part of the study. The generated antenna pattern is quantized at 1 degree resolution. In other words. the gain pattern of the antennas changes as the operating frequency changes. each antenna has distinct characteristics at varying operating frequencies.1 Block Diagram of the Amplitude Comparison DF System The antenna plays a very important role in reception of the signals from the emitters.Figure 3. and distortion of the main beam axis direction and beamwidth are usually encountered.

Angle 3. In the software simulations.1. the signals received from each channel in the system are directly used in the algorithm for locating the angular position of emitter.2 Amplitude Comparison Antenna Gain vs. For each channel at specified SNR value.0 -5 -10 -15 Gain (dB) -20 -25 -30 -35 -40 0 50 100 150 200 Angle (degrees) 250 300 350 Figure 3.1. Therefore the received signals are simulated as if emitter is angularly located in steps of 1 degree with respect to the DF system.1 1st Approach In this approach. 17 . is simulated to obtain the DF accuracy of the algorithm taking into consideration different SNR values. which has a gain of 0dB.1 Software Simulation Results The amplitude comparison method. 3.1. complex receiver noise is generated as if the signal is received by an isotropic antenna. which is formulated in Chapter II. the estimation of emitter angular location has 1 degree resolution. Two approaches are proposed for applying the amplitude comparison algorithm. Since the antenna pattern is quantized at 1 degree resolution. complex noise is generated and is added to the received signal under consideration.

The antenna having a boresight of 60 degrees is taken as a reference. Search Interval is set to between 30 and 90 degrees.5 respectively. 50 45 40 RMS Error (degrees) 35 30 25 20 15 10 5 30 SNR=10dB SNR=15dB 40 50 60 AOA (degrees) 70 80 90 Figure 3. 3x104 trials are performed. SNR value is varied from 10dB to 40dB in steps of 5dB.3 RMS Error vs. since the gain patterns of the antennas are identical. AOA (SNR is equal to 10dB and 15dB) 18 .3.4 and Figure 3. Simulations results are given in Figure 3. Therefore AOA interval is selected between the intersections of gain patterns of the adjacent antennas.There exist six identical regions in the 360 degree azimuthal coverage. Figure 3. For each corresponding AOA.

5 0 30 40 50 60 AOA (degrees) 70 80 90 Figure 3.5 RMS Error vs. AOA (SNR is equal to 35dB and 40dB) 19 . AOA (SNR is equal to 20dB.5 SNR=35dB SNR=40dB RMS Error (degrees) 1 0.4 RMS Error vs.8 7 6 RMS Error (degrees) 5 4 3 2 1 0 30 SNR=20dB SNR=25dB SNR=30dB 40 50 60 AOA (degrees) 70 80 90 Figure 3. 25dB and 30dB) 1.

8.013 1.7 and Figure 3.467 Standard deviation (degrees) 9. are used instead of using all of the received pulse amplitudes.6. Figure 3.623 1. Table 3-1 Mean and Standard Deviation of RMS Error (1st Approach) Mean (degrees) RMS Error (SNR=10dB) RMS Error (SNR=15dB) RMS Error (SNR=20dB) RMS Error (SNR=25dB) RMS Error (SNR=30dB) RMS Error (SNR=35dB) RMS Error (SNR=40dB) 34.330 5. since they are mainly receiving the receiver noise.321 0. These three pulse amplitudes are taken into consideration to be used in the DF algorithm.The DF accuracies with varying SNR values are summarized in Table 3-1.2 2nd Approach In this approach the pulse amplitudes from three antennas. The antenna that receives the maximum pulse amplitude is determined.841 0.222 3.1.3741 2.591 0. which are directed to the emitter.273 2. mean and the standard deviation of the RMS error are given. The signals received by remaining three antennas are eliminated.395 12.105 0. The corresponding RMS Error curves for different SNR values from 10dB to 40dB in steps of 5dB are plotted in Figure 3.1. Then pulse amplitudes received from the antennas.344 1.448 0. 20 . where statistical indicators. are selected. which are adjacent to this antenna.

7 RMS Error vs. AOA (SNR is equal to 10dB and 15dB) 8 7 6 RMS Error (degrees) 5 4 3 2 1 0 30 SNR=20dB SNR=25dB SNR=30dB 40 50 60 AOA (degrees) 70 80 90 Figure 3. AOA (SNR is equal to 20dB.6 RMS Error vs. 25dB and 30dB ) 21 .26 24 22 20 RMS Error (degrees) 18 16 14 12 10 8 6 30 SNR=10dB SNR=15dB 40 50 60 AOA (degrees) 70 80 90 Figure 3.

840 0.588 0.636 11.964 1.8 RMS Error vs.319 0.221 22 .1.99 1.879 5. AOA (SNR is equal to 35 dB and 40dB) Mean and the standard deviation of the RMS Error are calculated for different SNR values and are given in Table 3-2.467 Standard deviation (degrees) 2.5 0 30 40 50 60 AOA (degrees) 70 80 90 Figure 3.62 1.222 2.097 0.446 0. Table 3-2 Mean and Standard Deviation of RMS Error (2nd Approach) Mean (degrees) RMS Error (SNR=10dB) RMS Error (SNR=15dB) RMS Error (SNR=20dB) RMS Error (SNR=25dB) RMS Error (SNR=30dB) RMS Error (SNR=35dB) RMS Error (SNR=40dB) 21.5 SNR=35dB SNR=40dB RMS Error (degrees) 1 0.377 1.

9 for both approaches. 2nd approach. located in the middle of the antenna boresights. However. within the beamwidth of the antenna. the slope of the antenna gain increases. become more accurate. AOA estimates of the sources. On the other hand as SNR increases. The main reason is that the antennas receive high levels of noise which prevents gathering proper measurement of the pulse amplitude. the 2nd approach is more preferable. even at the same SNR. as AOA gets further from the boresight. It is observed that. For low SNR cases DF accuracy of the 2nd approach is better than the 1st approach. are more accurate. which are located in the vicinity of direction of the antenna boresight. which uses pulse amplitudes from 3 antennas. 23 .3 Comparison of Approaches When two approaches are compared. At the boresight amplitude fluctuations due to the presence of noise affect the DF accuracy more. therefore 2nd approach is selected for the hardware implementation. Therefore. Consequently better DF accuracy is obtained.1. 3. Mean of the RMS error is plotted in Figure 3. in which pulse amplitudes from all receiving channels are used. is superior to 1st approach. However as SNR value increases both algorithms have approximately the same DF accuracy. considering the overall performance.1. The reason for this is that SNR is high and contribution of the other antennas to algorithm makes the DF accuracy better. because the antenna gain pattern is linearly stored and is very flat around the boresight. the RMS error alters along DOA of the source.According to simulation results. for the low SNR cases AOA estimate of the sources.

actually there are two signals that data width should be considered carefully. General information about the software tool and development tool flow is given in Appendix B.35 30 RMS Error Mean (degrees) 25 20 15 10 5 0 10 1st Approach 2nd Approach 15 20 25 SNR (dB) 30 35 40 Figure 3. Therefore the width of the data should be determined carefully. which is stored in the RAM. implementation of the amplitude comparison DF algorithm is implemented on an FPGA platform by using a commercial software tool. Here the question is how many bits are required for each signal to be represented in the FPGA. SNR 3.1. floating point double precision values were used to determine angular location. first one is the pulse amplitude. the number of bits used in the design is directly proportional to the resources used in FPGA.9 Mean of RMS Error vs. is discussed. In the software simulations. However. As a result the errors due to quantization are inevitable. In the design. fixed point arithmetic is used. As a general rule for hardware implementation. the other is the antenna gain pattern. when the algorithm is implemented on FPGA. 24 .2 Hardware Implementation In this part. Xilinx System Generator Tool.

After the signals are received by antennas, they pass through the RF sections and before processed in FPGA fabric, the IF signals are converted from analog to digital by ADCs. In today’s technology, throughput of commercial ADC varies from few MSPS to 12 GSPS [1]. Generally as throughput of the ADC increases, the number of bits that represent resolution decreases. In today’s technology, ADCs whose throughput rate is greater than 200 MSPS mostly have 8, 10 or 12 bits for resolution. Therefore, considering this fact and the process gains in FPGA, it is a good approximation to determine 12 bits for the pulse amplitude. The other parameter, whose data width should be determined, is the antenna gain pattern. Since data width of the received signal pulse amplitude is selected to be 12 bits, the antenna pattern data width should be comparable to data width of pulse amplitude. Large data widths of antenna gain pattern do not provide much resolution, since pulse amplitude is already limited to the 12 bits. Consequently, experiments were performed with 12 bit and 16 bit quantized antenna gain patterns, regarding different SNR cases.

3.1.2.1

Hardware Design

In the hardware design, inputs to the algorithm are pulse amplitude information from each receiver channel and a strobe, indicating that the pulse amplitudes are valid and ready for processing. The output of the hardware implementation is the AOA estimate of the emitter. Operating frequency is assumed to be constant. The hardware design is composed of three main blocks. These blocks are; • AC_Angle_Counter, which filters the necessary pulse amplitudes and generates a valid search interval. • • AC_Correlation_Computation, which calculates the ML function. AC_AOA_Estimator, which estimates the angular location of the emitter.

The purpose and the operational details of each of the implemented block are presented in the following parts of this chapter. The block diagram of the hardware implementation is given in Figure 3.10. 25

1 PA_1

double

PA_1 double PA_Max2 PA_2 double PA_3 double PA_4 double PA_5 double PA_6 AOA_Interv al_Counter Data_Ready PA_Max3 UFix_12_12 PA_Max3 PA_Max UFix_12_12 PA_Max C orrelation UFix_25_24 UFix_12_12 PA_Max2

2 PA_2

3 PA_3

4 PA_4

Sy stem Generator

5 PA_5

6 PA_6

UFix_10_0

Addr Correlation

7

double

Data_Ready

AC_Angle_Counter

AC_Function_Calculation z -6

UF ix_10_0 AngleIn AOA_Est UFix_9_0

1 AOA_Est

z -13

Bool

Delay_AOAInterval

Data_R eady

Delay_DataReady

AC_AOA_Estim ator

Figure 3.10 Block Diagram of the Amplitude Comparison Implementation

3.1.2.1.1 AC_Angle_Counter Block

The purpose of this block is to generate a search interval for estimation of AOA. In monopulse DF systems, not only the DF accuracy but also the process time needed to determine the AOA is very important. Since the speed of the algorithm is very crucial, it is better to make calculations in a smaller interval than making calculation for the entire coverage range. Implementation of the Angle_Counter consists of three hierarchical blocks. • AC_Max_PA_Index_Finder, which determines the index of the Antenna receving maximum pulse amplitude. • • AC_Max_PA_Selector, which selects the proper pulse amplitudes. AC_Address_Counter, which generates a valid search interval.

Logic diagram of the AC_Angle_Counter block is given in Figure 3.11.

26

Max_Index PA_Max 2

UFix _12_12

1 PA_M ax2

z -4 Del ay1

U Fix_12_12

PA_1 UFix _12_12 PA_2 UFix _12_12 PA_3 UFix_12_12 PA_4 UFix _12_12 PA_5 PA_Max 3 PA_6 UFix _12_12 PA_Max UFix _12_12

z -4 Delay2

z -4 Delay3

2 PA_M ax

z -4 Del ay4

z -4 Delay5

z -4 Del ay6

U Fix_12_12

3 PA_M ax3

AC_M ax_PA_Sel ector

1 PA_1 2 PA_2 3 PA_3 4 PA_4 5 PA_5 6 PA_6 7

U Fix_12_12

PA_1

U Fix_12_12

PA_2

U Fix_12_12

PA_3 U Fix_3_0

U Fix_12_12

PA-_4

Index

Antenna_N o AOA_Interv al_Counter D ata_R eady UFix _10_0

U Fix_12_12

PA_5

4 AOA_Interval _Counter

U Fix_12_12

PA_6 Bool

Bool

z -3 Delay

AC_Address_Counter

Data_R eady

Data_Ready

AC_M ax_PA_Index_Fi nder

Figure 3.11 Logic Diagram of AC_Angle_Counter Block

3.1.2.1.1.1

AC_Max_PA_Index_Finder Block

The purpose of this block is to determine the antenna, at which the maximum pulse amplitude is received. Pulse amplitudes of the received signals are input to this block and output is the antenna index. The logic diagram of the AC_Max_Amplitude_Finder block is given in Figure 3.12.

27

12 Logic Diagram of AC_Max_Amplitude_Finder Block 3. Logic diagram of the AC_Max_PA_Selector block is given in Figure 3. three pulse amplitudes are filtered.1. Depending on the Max_Index input.1.2. 28 .xllogical and Bool Bool xllogical or Logical3 Logical5 1 UFix_12_12 UFix_12_12 Bool xllogical and -1 z Logical1 Bool In1 2 In2 a Bool xlrelational a<b b z-1 Relational sel xlmux d0 d1 Mux UFix_12_12 xlinv Inverter5 not a Bool xlrelational a<b b z-1 Relational3 sel xlmux d0 d1 Mux4 UFix_12_12 Bool xllogical and z-1 Logical Bool 3 In3 UFix_12_12 4 In4 UFix_12_12 a Bool xlrelational a<b b z-1 Relational1 sel xlmux d0 d1 Mux1 UFix_12_12 xlinv Inverter4 not xllogical and Logical4 Bool a Bool xlrelational a<b b z-1 Relational4 z -1 Delay1 Bool hi xlconcat cat lo Concat UFix_3_0 5 In5 UFix_12_12 a b z-1 6 In6 a<b UFix_12_12 xlrelational Relational2 Bool sel xlmux d0 d1 Delay Mux2 UFix_12_12 xllogical and z-1 z -1 UFix_12_12 Bool xllogical or Logical2 Bool Logical6 d xlregister UFix_3_0 z-1 q en Register_AOA Delay2 7 Bool z -4 Bool 1 Index Data_Ready Figure 3.1.2 AC_Max_PA_Selector Block The block is designed to determine the maximum pulse amplitude and pulse amplitudes from antennas which are adjacent to the antenna receiving the maximum pulse amplitude.13. The inputs are pulse amplitudes from each receiver channel and the index of the antenna which received the maximum pulse amplitude.

13 Logic Diagram of AC_Max_PA_Selector Block 29 .a 1 UFix_3_0 k =0 a=b UFix_1_0 xl rel ati onal b z -1 Relational 1 Bool sel xl m ux d0 UFix_3_0 UFix_3_0 M ax_Index Constant5 k =1 UFix_1_0 a k =5 xladdsub UFix_3_0 a-b Constant4 b z-1 AddSub1 d1 M ux3 sel d0 d1 d2 m-1 xl ux z d3 d4 d5 M ux sel d0 d1 d2 m-1 xl z ux d3 d4 d5 M ux2 UFix_12_12 UFix_12_12 Constant2 1 PA_M ax2 2 PA_M ax a Bool a=b UFix_3_0 xl rel ati onal k =5 b z -1 Constant7 Relational 2 k =0 a xladdsub U Fix_3_0 Constant6 a+b b z -1 AddSub2 sel xlm ux d0 UFix_1_0 U Fix_3_0 d1 k =1 UFix_12_12 UFix_12_12 UFix_1_0 M ux4 sel d0 d1 d2 m-1 xl ux z d3 d4 d5 M ux1 UFix_12_12 Constant1 2 PA_1 3 PA_2 4 PA_3 UFix_12_12 3 PA_M ax3 5 PA_4 UFix_12_12 6 PA_5 UFix_12_12 7 PA_6 UFix_12_12 Figure 3.

15. The logic diagram of the AC_Address_Counter block is given in Figure 3.3 AC_Address_Counter Block The purpose of this block is to generate a sequential search interval for estimating AOA depending on the antenna. The possible search intervals are given in Figure 3.1.2. Taking into account the low SNR cases. 1 U Fix_3_0 sel U Fix_1_0 Antenna_No k =0 Constant7 k =128 Constant2 k =256 Constant3 k =384 Constant4 k =512 Constant5 k =640 Constant6 M ux k =1 2 Bool Bool U Fix_10_0 U Fix_10_0 U Fix_9_0 U Fix_9_0 U Fix_8_0 d0 d1 UF ix_10_0 d2 xlm ux z -1 Delay1 U Fix_10_0 d3 a xladdsub UF ix_10_0 a+b 1 b z -1 AOA_Interval_Counter AddSub d4 d5 rst d Bool xlregister rst z -1 q en Register out en Counter U Fix_7_0 k =118 Constant1 U Fix_7_0 a Bool xlrelational a=b b z -1 Relational Constant Data_Ready Figure 3. 3dB beamwidth. Then counter counts up to 120.1. The center of the search interval depends on the antenna. which receives the greatest pulse amplitude.14 Logic Diagram of AC_Address_Counter Block When Data_Ready strobe is high. the beginning of the AOA interval is determined. which is the predetermined search interval. According to the Antenna_No input. 30 . this interval should be greater than 60 degrees.3.14.1. which receives the signal at maximum amplitude. the counter value is reset. The determined search interval is 60 degrees around the boresight of this antenna.

15 Search Interval for Amplitude Comparison Implementation For the high SNR cases. This block is implemented for calculating M (θ ) .16. xlslice [a:b] Slice U Fix_12_0 xlcast force U F ix_12_12 a b U Fix_24_24 xlm ult (ab) -3 z Reinterpret1 M ult 4 Addr ROM xlslice [a:b] Slice2 U Fix_12_12 U Fix_12_0 U Fix_10_0 addr U Fix_36_0 xlslice [a:b] Slice1 U Fix_12_0 xlcast force U F ix_12_12 a b U Fix_24_24 xlm ult (ab) z -3 a xladdsub U Fix_25_24 a+b b z -1 AddSub a xladdsub U Fix_25_24 a+b 1 b z -1 Correlation AddSub3 U Fix_24_24 -1 xl register d z q Reinterpret2 M ult1 xlcast force U F ix_12_12 a U Fix_24_24 xlm ult (ab) b z -3 Reinterpret3 M ult2 Register2 1 PA_M ax2 2 U Fix_12_12 PA_M ax U Fix_12_12 3 PA_M ax3 Figure 3.1. (2. as stated in Chapter II. 3.Figure 3.16 Logic Diagram of the AC_Correlation_Computation Block 31 . It will be useful to rewrite the expression for M (θ ) here. which yields an improvement of total process time for the estimation of AOA.1.2 AC_Correlation_Computation Block In order to find the AOA of the incoming signal. N −1 ∑ s i Ri (θ − θ i ) 0 M (θ )= i =N −1 ∑ Ri2 (θ − θ i ) i =0 2 (2. This change will result in reduced computation time. alternatively the search interval can be decreased up to 3 dB beamwidth of the antenna.10) The logic diagram of the block is given in Figure 3.10).2. the algorithm tries to find the argument that maximizes M (θ ) in Eq.

At every angle. In order to minimize the process time. 32 . is used for addressing the ROM block and taking corresponding antenna gain value at the specified angle. The search interval. Normalization is performed according to the following equation. Taking the square root of the Eq. Taking the square root of both the denominator and the numerator does not affect the estimated AOA value. the products are summed up and released as an output of the block.AC_Correlation_Computation block inputs three pulse amplitudes and the AOA search interval from previous block. antenna pattern is normalized and stored. The overall pipelined latency of this block is 6 clock cycles for each angle value. Reading table data from the memory is performed in a single clock cycle. While forming antenna gain pattern tables. after a process delay 6 clock cycles. since si and Ri are non-negative real values. Therefore after addressing ROM block. At the hardware implementation phase. Ri′(θ ) = i N −1 i =0 R (θ − θ i ) 2 i ∑ R (θ − θ ) i (3-2) Each memory row in table contains three antenna gains at the same angle. Adr. multiplication and addition of the values are done in parallel in 5 clock cycles. Moreover. a modification is made on the above equation in order to simplify and eliminate the operation complexity in the hardware. the value of the function is ready at the output of the block for each AOA. simplifications will be quite useful for storing the modified antenna gain pattern. gains are quantized at n bits and merged into 3n bits wide. the value received is sliced into three parts and multiplied with the pulse amplitude values. (2-10) yields N −1 i =0 M ′(θ )= ∑ s R (θ − θ ) i i i ∑ R (θ − θ ) 2 i i i =0 N −1 (3-1) Antenna pattern is generated at each angle from 1 to 360 degrees at a resolution of 1 degree. As a result. To calculate M ′(θ ) at the specified angle.

the signals are delayed by using delay blocks in previous blocks.3 AC_AOA_Estimator Block This block is the final block that estimates the AOA of the incoming signal. The inputs to this block are the angle within the search interval. In order to synchronize the Correlation. at which maximum of the function occurs. over the predefined search interval. this value is presented as an output of the block.17. angle value corresponding to this point is latched. 1 UFix_25_24 Correla tion a Bool xlrelational a >=b b Rela tion_M axFlag d U Fix_25_24 -1 xlregister rst z q en Registe r_M axCorr xlslice [a:b] U Fix_7_0 2 AngleIn UFix_10_0 Slice_IndexNo d -1 xlregiste r UF ix_10_0 z q en Register d -1 xlregister U Fix_10_0 z q en Register_ AOA xlsli ce [a:b] UFix_3_0 sel U Fix_9_0 3 Bool Bool z -12 1 Sli ce_AntNo k =30 1 d0 Data_Ready De layLi ne Con stant2 U Fix_1_0 k =1 d1 Con stant1 U Fix_6_0 UFix_9_0 k =61 xlm ux d2 Con stant3 U Fix_7_0 k =12 1 d3 Con stant4 U Fix_8_0 k =18 1 d4 Con stant6 U Fix_8_0 k =24 1 d5 Con stant5 M ux2 a xladdsub UF ix_9_0 a a+b Bool b xlrelationa l a>b b z-1 Ad dSub Rela tional sel U Fix_9_0 xlm ux d0 1 AOA_Est a xla ddsub U Fix_9_0 a -b d1 U Fix_9_0 k =3 60 b z -1 Constant7 AddSu b1 M ux1 Figure 3. 33 . When a maximum point is found.17 Logic Diagram of AC_AOA_Estimator Block The function of this block is to find the angle. Output of this block is the estimated AOA value. and at the end of search interval. value of M ′(θ ) at this angle and the strobe.2. The logic diagram of the block is given in Figure 3.1. Angle_In and Data_Ready signals and to make proper AOA estimate. indicating that the pulse amplitudes are ready.1.3.

saturation arithmetic and rounding have area and performance costs [12]. search interval.2. the multiplication of two values. Estimated AOA and Data_Ready signals are plotted for each pulse. For the 12 bit simulation.. at which the maximum of the ML function is encountered. where SNR value is set to 30dB and AOA of the emitter is selected to be 250 degrees. Therefore the logic. regarding different SNR cases. can be used for implementation of other blocks. The latency is as follows.18. which is planned to be used for multiplication block. In the simulation. In the Figure 3. no FPGA resources are used. which corresponds to 5 ns of clock period. In addition. adjustments are made in order not to lose the precision at the output. the pulses are generated with pulse repetition interval (PRI) of 1 µs. The screenshot of the scope from the hardware implementation is given in Figure 3. the product is 28 bit unsigned where binary point in 28th bit. 34 . Therefore they are used only if necessary. The clock rate of the system is set to 200 MHz. This provides flexibility in hardware design.1. M ′(θ ) function. 12 bit unsigned where binary point 12th bit and 16 bit unsigned where binary point 16th bit. Since these multipliers are dedicated.After Data_Ready strobe makes a transition to high state. Similar procedure is also applied for 12 bit simulation. when performing a multiplication. 6 clock cycles to calculate the function M ′(θ ) 120 clock cycles to calculate the ML function and 4 clock cycles to find angle.2 Simulation Results As stated in the hardware implementation part.18. it is advantageous to use 18x18 dedicated embedded multipliers [11]. experiments were performed with 12 bit and 16 bit quantized antenna gain patterns. 7 clock cycles in AC_Angle_Counter block to determine the search interval. (5x103 Iterations were performed for each AOA value. 3. 137 clock cycles later AOA_Est is ready.) In the hardware design. While implementing multiplier blocks in FPGA.

there exist 6 identical zones in the 360 degree azimuth coverage that have the same antenna gain pattern.20 respectively.Figure 3. 35 .19 and Figure 3. RMS Error of the 12 bit and 16 bit hardware implementation simulations for 20dB SNR and 30 dB SNR are given in Figure 3. Therefore the experiments are performed in 60 degree interval at a resolution of 1 degree.18 Screen Shot from System Generator (Implementation of Amplitude Comparison) Since the antenna patterns are symmetric along the direction of the beam axis.

19 RMS Error vs AOA of Amplitude Comparison Hardware Implementation at 20dB SNR 2.4 1.8 1.2 RMS Error (degrees) 2 1.8 7 RMS Error (degrees) 6 5 4 3 2 30 12bit 16bit 40 50 60 70 AOA (degrees) 80 90 Figure 3.20 RMS Error vs AOA of Amplitude Comparison Hardware Implementation at 30dB SNR 36 .6 1.4 2.6 2.2 1 0.8 30 40 50 60 AOA (degrees) 70 80 90 12bit 16bit Figure 3.

Table 3-3 Mean and Standard Deviation of RMS Error for Amplitude Comparison Hardware Implementation Mean (degrees) RMS Error 12 bit (SNR = 20dB) RMS Error 16 bit (SNR = 20dB) RMS Error 12 bit (SNR = 30dB) RMS Error 16 bit (SNR = 30dB) 5. When these results are compared to software simulation results.245 5.994 0. According to simulation results.58 Table 3-3 summarizes the performance of two hardware implementations having different number of bits for representing the antenna gain pattern. 37 . storing the antenna gain pattern table 12 bit precision or 16 bit precision does not affect the DF accuracy of the algorithm much.Mean and standard deviation statistics of RMS Error of the 12 bit and 16 bit simulation results at 20dB and 30dB SNR are given in Table 3-3.240 1. since calculated quantization errors are very small. For the hardware implementation. Both 12 bits and 16 bits hardware implementations provide sufficient resolution. the utilization of the FPGA resources is given in Table 3-4. But it is observed that In 16 bit implementation mean of estimated AOA values are more accurate due to greater quantization steps.976 1.448 Standard deviation (degrees) 1.467 1.6 0. both implementation results are very close to the results obtained in software simulation. since the amplitude of the signal is limited by 12 bits.

00 < d < 3.00 d >= 5.338 ns The number of signals not completely routed for this design is: The average connection delay for this design is The maximum pin delay is: The average connection delay on the 10 worst nets is: Listing Pin Delays by value: (ns) d < 1.Table 3-4 FPGA Resource Utilization Summary of Amplitude Comparison Implementation Number of Slice Number of Slice Flip Flops Number of 4 input LUTs Number of IOBs Number of MULT18X18s Total equivalent gate count for design: 396 467 517 83 3 156. Requested Constraint : 5.813ns 0 ns 0. 38 . following results are obtained.00 < d < 2.00 1823 850 61 1 0 0 According to synthesis report all constraints were met and all signals are completely routed.00 < d < 4.827 ns 3. According to the generated clock report of the implementation.029 ns 2.176 It is useful to give some information about the timing constraints.00 < d < 5.000ns Actual Constraint : 4.

a phase difference of null arises at the boresight of the antenna. The phase difference is measured by two identical antennas in space. In the FPGA.21 Block diagram of the Phase Comparison DF system A single baseline interferometer is assumed in the phase comparison system.3. the signals received by the antennas pass through RF paths and are sampled by ADC. In this case. the phase difference would be zero. The block diagram of the system is given in Figure 3. it is assumed that Pulse Descriptor Word (PDW) Generator block measures parameters of the received signals in FPGA and extract the properties like pulse amplitude. the digital signals are directed to FPGA. pulse width etc.21.2 Phase Comparison The phase comparison system has two receiver channels following the antennas. After these phases. 39 .22. Part of this PDW Generator block supplies pulse amplitude and the frequency information of the received signal to phase comparison block. The antennas are assumed to have the same antenna gain patterns. If the source of the signal is located at equal distance from the antennas. frequency. The phase difference occurs from the extra time it took a plane wave to travel a greater distance to the further antenna. Similar to the amplitude comparison system. As shown in Figure 3. two antennas are located on a straight line with spacing of d. separated by a finite baseline. Figure 3.

signal received by Antenna 1 is given by S1 = Ae jwt − 2π λ ( X + d sin ϕ ) (3-4) Where.(3-3) yields to ln S 2 − ln S1 = j 2π λ d sin ϕ (3-5) 40 . Since the important parameter in this case is phase difference of the arriving signals. (2π / λ )X can be assumed to be zero. Subtracting the natural logarithm of the Eq.ds in (φ ) X Figure 3. In the same manner. A represents initial signal amplitude.(3-4) from the natural logarithm of the Eq. d sin ϕ term represents the additional path to Antenna 1 as reference to Antenna 2. λ is the wavelength of the traveling antenna and d is the distance between the antennas.22 Single Baseline Interferometer The signal received by Antenna 2 can be expressed as S 2 = Ae jwt − 2Π λ X X (3-3) where. X is the distance traveled by the signal to reach the Antenna 2.

since phase difference is not a multiple of 2 π . covering the 180 degree range. and like in the previous case. Therefore. In the experimental work. According to this interval. which reside in the first quadrant and in the second quadrant. Figure 3. the value of d/λ ratio is very crucial. When d/λ ratio is selected to be n. the phase difference is in the interval between 0 and 2 π n. where n is an integer greater than 1. there are two solutions. AOA of the signals propagating from first quadrant is assumed to be positive and AOA of the signals from the left side of boresight will be regarded as negative. n of which are in the first quadrant and the other n solutions reside in the second quadrant. Therefore θ can be expressed as θ = 2π d λ sin ϕ (3-6) As an examination of the above equation. the phase difference is between 0 and 2 π . In the same manner. if d/λ is chosen to be 1.23 Phase Comparison Antenna Layout 41 . When d/λ ratio is equal to 1/2. AOA will be determined in the interval between -90 and 90 degrees.Let θ be defined as a phase difference. AOA ϕ has two solutions. the phase difference θ is in the interval between 0 and π . In this case there are 2n solutions.

24 real and imaginary parts and in Figure 3. one of the antenna patterns is stored as complex valued. software simulations are performed. In software simulations antennas are assumed to be omni-directional. According to the phase comparison algorithm stated in Chapter II.5 0 -0. 1 real part imaginary part 0.24 Real and Imaginary parts of Phase Comparison for d/λ=2 42 .25 phase and gain of the antenna pattern is plotted when d / λ is equal to 2.As part of implementation of the phase comparison algorithm.5 -1 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Angle (degrees) 90 Figure 3. since the phase difference of the received signals is the primary concern. In Figure 3.

26 Typical Plot of J ' (φ ) vs.5 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 AOA (degrees) 20 30 40 50 60 70 80 90 Figure 3. 2.θ .θ . The typical plot of J ( A. φ ) is given in Figure 3.5 d/Lambda=1 d/Lambda=5 2 1. φ ) .26.1 phase (pi) gain (dB) 0. where direction of arrival is set to 35 degrees. AOA for d / λ = 1 and d / λ = 5 (AOA=35) 43 .25 Phase Comparison Antenna Gain and Phase Pattern for d/λ=2 The AOA of the received signals can be estimated by the argument that maximizes the function J ( A.5 -1 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Angle (degrees) 90 Figure 3.5 J() 1 0. The function is plotted for both when d / λ = 1 and d / λ = 5 .5 0 -0.

27 Search Interval for Phase Comparison Therefore. where θinput – ∆θ is smaller than -90. which create ambiguity. On the other hand if the search interval is determined to be small. At the boundary point in the first quadrant. 3. The factors that affect the choice of ∆θ are d / λ ratio. Figure 3.The most important point of this function is that in each quadrant it has more than one local maximum point for d / λ values greater than 1. due to ambiguities.2. the accuracy of phase comparison system under the defined SNR and the DF accuracy of the system that provides prior AOA estimate. the interval limit is set to 90 degrees. phase comparison systems work with another DF system to provide more accurate results. the other lobes. As declared in [6]. These points are possible AOA of the received signals. Main objective is to detect only the maximum point of the lobe of interest over the search interval for accurate DF sensing. where θinput + ∆θ is greater than 90 degrees. the determined search interval will not be appropriate. Therefore a search interval must be stated to find the maximum point of the function in order to determine the angular location. a search interval of θinput ± ∆θ is defined. 44 . prior information of possible AOA should be present. may exist in the search interval. If the search interval is determined to be large. If great d / λ value and poor DF accuracy of the prior AOA information is considered. the interval limit is set to -90 degrees. where θinput represents the prior AOA information provided by another DF system. At the second quadrant.1 Software Simulation Results In order to get rid of the ambiguities and determine angular location.

AOA at (SNR = 10 dB) d / λ value from 1 to 5 in steps of 0.30.5 d/lambda=4 d/lambda=4.5 45 .28 Phase Comparison RMS Error vs. To have a better understanding of d / λ ratio and the DF accuracy.28. Figure 3. Therefore to determine the search interval.5 d/lambda=3 d/lambda=3. the d / λ value and the DF accuracy of the other system should be considered and evaluated carefully where the DF accuracy of the phase comparison system should not be ignored.5 d/lambda=1 d/lambda=1. The results of the experiment varying d / λ ratio vs.29 and Figure 3.the peak of the desired lobe may not be detected. 10 d/lambda=0. RMS error plots at different SNR levels are given in Figure 3.5 d/lambda=2 d/lambda=2.5 d/lambda=5 9 8 7 RMS Error (degrees) 6 5 4 3 2 1 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 AOA (degrees) 20 30 40 50 60 70 80 90 Figure 3. some software simulations are performed. Consequently in both cases it will lead to errors in the measurement of AOA which is an unwanted situation.

AOA at (SNR = 30 dB) d / λ value from 1 to 5 in steps of 0.5 d/lambda=3 d/lambda=3.5 d/lambda=5 30 40 50 60 70 80 90 Figure 3.5 2 1.30 Phase Comparison RMS Error vs.5 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 AOA (degrees) d/lambda=0.5 d/lambda=1 d/lambda=1.5 d/lambda=2 d/lambda=2.5 4 3. AOA at (SNR = 20 dB) d / λ value from 1 to 5 in steps of 0.5 d/lambda=4 d/lambda=4.29 Phase Comparison RMS Error vs.5 d/lambda=2 d/lambda=2.5 d/lambda=4 d/lambda=4.5 5 4.8 d/lambda=0.5 46 .5 1 0.5 d/lambda=3 d/lambda=3.5 RMS Error (degrees) 3 2.5 d/lambda=5 7 6 RMS Error (degrees) 5 4 3 2 1 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 AOA (degrees) 20 30 40 50 60 70 80 90 Figure 3.5 d/lambda=1 d/lambda=1.

ignoring both ends of the entire azimuth 47 . Better DF accuracy is obtained for the signals arriving around boresight of the antenna.5 4 4. the RMS error curve has very steep increasing characteristics.31 Mean of RMS Error vs. For AOA greater than 60 degrees. 20dB and 30dB As d / λ increases.5 5 Figure 3.Phase comparison algorithm has different performance characteristics over the AOA. to cover a greater azimuthal range. as expected the algorithm has a better DF accuracy. To understand the overall DF accuracy of the experimental results. 7 SNR=10dB SNR=20dB SNR=30dB 6 RMS Error Mean (degrees) 5 4 3 2 1 0 0.31 for different SNR values. d / λ Values for SNR=10dB. In this configuration. the statistical information. If more DF accuracy is required. As the angle between the boresight of the antenna and the propagation vector of the signal increases.5 1 1. RMS error increases. For high SNR values. it is possible to diminish azimuth coverage from 180 degrees to approximately 120 degrees. mean of the RMS error as a function of d / λ is plotted in Figure 3.5 2 2.5 3 d/lambda 3. mean and the standard deviation of the RMS error decreases and provide a better angular location. For 30dB SNR. more than one interferometer systems can be used to operate together.

In phase comparison systems.5 cm. Software simulations were performed to compare with the hardware implementation results. 48 . Since d / λ value must be greater than ½. one of the most challenging problems is to determine the baseline spacing according to the operating frequency band.range where RMS error is large.5 cm. for d1 = 7. mostly below RMS error of 2 degrees. 1 < d / λ < 3. the baseline spacing is chosen to be to 15 cm and the frequency is varied between 2 GHz and 6 GHz. 3/2 < d / λ < 9/2. an RMS accuracy of 1 degree RMS error mean is reached for the d / λ values greater than 1. In this study. Here d / λ is varied between one and three proving a fair DF accuracy. For the simulation. The DF accuracy is directly proportional to the ratio of baseline spacing to the wavelength of the signal. the operating frequency band is determined to be between 2 GHz and 6 GHz corresponding to a maximum wavelength of 15 cm and minimum wavelength of 5 cm.32. For different baseline spacing corresponding d / λ intervals are given by 1/2 < d / λ < 3/2. for d2 = 15 cm. the minimum baseline spacing of the antennas is limited to 7. Therefore the baseline spacing is determined upon the specifications and the needs of the system.5 cm. Software simulation results are plotted in Figure 3. for d3 = 22.

prior information of AOA provided by another DF system must be available.32 RMS Error vs.2 2 R S E r M a (d g e M rro e n e re s) 1. the provided AOA is 49 .33 Mean of the RMS Error vs. In order to determine the search interval.5GHz freq=4GHz freq=4.6 freq=2GHz freq=2.5 3 3. In the simulations.5 4 4.5GHz freq=3GHz freq=3. 2. AOA when Frequency is varied from 2 GHz to 6 GHz in steps of 500MHz at SNR = 20dB.4 1.5GHz freq=6GHz 5 4 RMS Error (degrees) 3 2 1 0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 AOA (degrees) 30 40 50 60 70 80 90 Figure 3.5GHz freq=5GHz freq=5.2 1 0. Frequency at SNR=20dB.5 Frequency (GHz) 5 5.5 6 Figure 3.8 2 2.8 1.6 1.

50 .32). Hence it is good to consider search interval of 10 degrees in software simulations. considering this tradeoff.3. The minimized solution set of the condition is given by sin ϕ 2 − sin ϕ1 = 1 / 3 . In order to decide the search interval.9 percent of probability. where -90< ϕ <90 For this case. poor DF accuracy is obtained for small d/λ values and for the angles approaching ±90 degrees (Figure 3.assumed to be accurate. Considering the case when d/λ is equal to 1. According to Eq. When d / λ is equal to 3. sin ϕ k . the angle difference of the maximum of lobes that makes ambiguity must be taken into consideration. Therefore the angle between two lobes makes at least 19. Therefore. since main purpose is to calculate DF accuracy of the phase comparison system. First.5941 degrees. therefore it should not be the main consideration. Quantization errors due to frequency resolution must be evaluated to find an appropriate frequency resolution. Secondly. 2. solutions. Solutions are the points which create ambiguity in the ML function.1881 degrees.291 x 3) degrees. another point to investigate is the frequency resolution of the antenna gain patterns which will be stored in the RAM. where k=1. Before proceeding to hardware implementation of the phase comparison algorithm. the interval length is limited. minimizing the search interval. are calculated ±9. Storing the antenna gain patterns dense over defined frequency interval requires much memory. the RMS error is calculated as 3 degrees around 70 degrees at 20dB SNR. in which the estimates reside 99.(3-6). is obtained in reference [10] as (3. To the ends of the entire angle range. phase difference is θ + 2π (k − 1) = 2π . Therefore for the simulations θinput ± 10 degrees is a valid search interval. some cases are investigated. which is greater than defined search interval. whereas storing it sparse results in large quantization errors. The interval. maximum number of lobes are present in the calculated ML function. the quantization interval of the frequency should be determined carefully. 3 The ϕ k ’s that are satisfying the above condition are the solutions.

34 The RMS Error vs. the AOA of the source is set to 30 degrees and the simulation is performed when there is no noise and when SNR is equal to 20 dB. 1.For frequency resolution of 100 MHz and 50 MHz.5 Frequency (GHz) 5 5.35 The RMS Error vs. Therefore.4 1.5 3 3.4 0. In case of performing a division operation with fix point numbers.2 RMS Error (degrees) 1 0. the less quantization errors are obtained. Frequency when fresolution = 50 MHz (AOA=30 degrees) As a result.8 0.5 3 3.5 Frequency (GHz) 5 5. performing a shift 51 . there exists a quantization error even at the noise free case.2 0 2 2.2 0 2 2. In this case.4 1.5 4 4. Frequency when fresolution = 100 MHz (AOA=30 degrees) 1. which takes more time and more resource.6 0. corresponding quantization errors over the entire frequency range are plotted in Figure 3.8 0.5 6 Noise free SNR=20dB Figure 3.34 and Figure 3. For frequency resolution of 100 MHz. the smaller the frequency resolution is used.5 6 Noise free SNR=20dB Figure 3.6 0.5 4 4. frequency resolution of 50 MHz is more appropriate.2 RMS Error (degrees) 1 0.35 respectively.4 0. However in the implementation it is better to set the resolution to a number which is a power of 2.

the experiments are also performed for frequency resolution of 64MHz. Xilinx System Generator Tool (Appendix B) will be presented. the RMS error is smaller than 0. is implemented.2 Hardware Implementation In this part.2 0 Noise free SNR=20dB RMS Error (degrees) 2 2. Therefore. After implementation of the phase comparison algorithm. 3. 1.2 1 0.2.4 0.5 4 4.5 Frequency (GHz) 5 5.1 degrees for 20dB SNR and is getting smaller as the frequency is increasing over the entire frequency range.6 0.4 1.8 0. which performs I and Q demodulation and delivers the complex amplitude to the phase comparison block.5 3 3.5 6 Figure 3. Frequency when fresolution=64 MHz (AOA=30 degrees) According to Figure 3. the part of the PDW Generator. implementation of the phase comparison DF algorithm on an FPGA platform by using a commercial software tool. 52 .36.36 The RMS Error vs.operation takes less resource and is faster.

PC_Angle_Counter. which determines the memory address interval PC_Function_Calculation.1 Hardware Design In hardware implementation of the phase comparison algorithm. which specifies a valid search interval. The block diagram of the hardware implementation is given in Figure 3. the real and imaginary parts of the signals from each channel. • • • • The purpose of the each implemented block is presented in the following parts of the chapter.37 Block Diagram of Phase Comparison Implementation 53 .37. the frequency of the received signals. which computes the ML function. the estimate of the AOA that another DF system provides.2. • • • The output of the hardware implementation is the AOA estimate of the emitter. In the hardware design. the implementation of the phase comparison DF algorithm consists of 4 main blocks. PC_Address_Decoder. PC_AOA_Estimator. These blocks are.2. which estimates the AOA.3. 7 Data_Ready 2 AOA_input dbl STR dbl AOA fpt Data_Ready Angle_Count z -12 Delay1 Sy stem Generator fpt AOA_input PC_Angle_Counter Angle_Count Address 1 Frequency 3 s1_real 4 s1_imaginary 5 s2_real 6 s2_imaginary dbl freq dbl fpt z -3 Delay3 Frequency Address PC_Address z -5 Delay4 z -5 Delay5 s2_real Angle_Count AOA_Est s1_real fpt s1_inphase1 dbl fpt s1_imag Function Function s1_quad1 dbl fpt z -5 Delay6 fpt dbl 1 AOA_Est s2_inphase2 dbl fpt z -5 Delay7 mag4 s2_imag Data_Ready s2_quad2 PC_Function_Calculation z -16 Delay2 PC_AOA_Estimator Figure 3. the inputs to the designed core are.

The logic diagram of the PC_Angle_Counter block is given in Figure 3. It is represented as 8 bit signed integer. whose center is AOA_input. which another DF system provides. The inputs to this block are Data_Ready and AOA_input signals. The output is the search interval. AOA_input is the AOA value.4 PC_Angle_Counter Block The purpose of this block is to determine the search interval of the algorithm. Data_Ready signal is defined to be Boolean. In the design. Data_Ready signal gives information that a new data is ready for search interval calculation. k =1 1 Bool Bool rst d Bool -1 xl register rst z q en Regi ster out en Counter UF ix_8_0 z -3 Delay2 Bool Constant Data_Ready a xladdsub UFix_8_0 a+b b z-1 UF ix_8_0 180 AddSub M ax_Lim it a Bool xlrelational a>b b z -1 Rel ati onal1 sel d0 z -1 xlm ux d1 U Fix_8_0 a Bool xl rel ati onal a=b b Relational 2 F ix_8_0 AOA_input a xladdsub U Fix_8_0 a+b UF ix_7_0 b z -1 k =90 AddSub6 Mux_M axSearchInt UF ix_4_0 k =10 Constant5 Search_Interval a F ix_9_0 xladdsub a-b -1 UFix_8_0 b z k =0 AddSub1 M in_Lim it a Bool xl relational a<b b z -1 Relational2 sel d0 -1 xlm ux z d1 M ux_M inSearchInt F ix_9_0 a UFix_8_0 xladdsub a+b b AddSub5 1 Angle_Count Figure 3.38 Logic Diagram of the PC_Angle_Counter Block 54 .38. The output Angle_Count will be used for determining the memory address in the next block. Therefore it varies between 0 and 180 as an 8 bit unsigned integer.1.3. It is assumed that AOA_input is in the interval between 90 and -90 degrees. Angle_Count.1.2.

3. 1. It makes 63 steps to cover the 4GHz range. f quantized = 2032 + 64k where (k=0. The inputs to this block are the Frequency. corresponding angle count of the search interval. which is input to the hi port. In order to obtain minimum the quantization errors.39. … . frequency of the received signal and the Angle_Count. Memory address is formed up by concatenation of two signals.62) 55 .39 Logic Diagram of the PC_Address_Decoder Block The frequency range is defined between 2GHz and 6GHz. antenna gain patterns are quantized at frequencies according to the given equation below. The frequency signal. resulting in memory depth of 16 K. 2 UFix_13_0 Frequency 2000 Constant5 1 UFix_8_0 UFix_11_0 a xladdsub UFix_12_0 a-b b z-1 Subtractor X >> 6 xlshift Shift UFix_6_0 hi xlconcat UFix_14_0 cat lo Concat z -1 Delay UFix_14_0 1 Address Angle_Count Figure 3. will occupy the least significant bits (LSB) of the memory address. which can be represented with 6 bits.5 PC_Address_Decode Block The purpose of this block is to calculate the memory address of antenna gain pattern. The logic diagram of the PC_Adreess_Counter block is given in Figure 3. Therefore the total memory address is defined by 14 bits.2. The antenna gain patterns are stored in ROM block at frequencies changing in steps of 64MHz.1. will occupy the most significant bits (MSB) of the memory address. Angle_Count.1. input to the lo port of Concat Block. 2.

6 PC_Function_Calculation Block The purpose of this block is to calculate the ML function J / (φ ) in Eq. sg * (φ ) + dh * (φ ) 2 φ = arg max φ | g (φ ) | 2 + | h(φ ) |2 (2-30) For the implementation of the algorithm. 1 Address UFix_14_0 addr UFix_36_0 xlslice [a:b] Slice UFix_12_0 xlcast force UFix_12_11 z -1 Delay1 UFix_12_11 table_real product_real Fix_23_22 ROM 2 s1_real 3 s1_imag Fix_12_11 ant1_real z -2 Fix_12_11 signal_real product_imag signal_imag Fix_23_22 a xladdsub Fix_25_22 a+b b z-1 AddSub1 xlslice [a:b] Slice2 UFix_18_0 xlcast force force1 Fix_18_17 a b xlmult Fix_36_34 (ab) -3 z Mult3 Fix_12_11 Delay4 Fix_12_11 z -2 Delay5 Complex_Multiplier_1 a b xladdsub a+b -1 z UFix_20_19 1 Function xlslice [a:b] Slice1 xlslice [a:b] Slice2 4 s2_real 5 s2_imag Fix_12_11 Fix_12_11 UFix_12_0 xlcast force ant2_real Fix_12_11 z -1 Delay2 Fix_12_11 table_real product_real Fix_24_22 AddSub3 UFix_12_0 xlcast force Fix_12_11 z -1 Delay3 Fix_12_11 table_imag ant2_imag z -2 Delay6 z -2 Delay11 Fix_12_11 a signal_real product_imag Fix_24_22 a xladdsub Fix_25_22 a+b b z-1 AddSub xlslice [a:b] Slice3 UFix_18_0 xlcast force force2 Fix_18_17 b xlmult Fix_36_34 (ab) -3 z Mult1 Fix_12_11 signal_imag Complex_Multiplier_2 Figure 3. some simplifications are made on the equation in order to minimize the number of operations. and the memory address. the algorithm tries to find the argument that maximizes the ratio given in Eq.1. This will result in faster process time of the implemented algorithm. Taking the square root of the Eq.40 Logic Diagram of PC_Function Calculation Block In order to find the AOA of the incoming signal.2. which is rewritten below for convenience.40.3. The inputs to the block are the real and imaginary parts of the received signals.(2-30) does not affect the result of the algorithm. Therefore the algorithm becomes φ = arg max φ sg * (φ ) + dh * (φ ) | g (φ ) | 2 + | h(φ ) | 2 (3-7) 56 .(2-29). The logic diagram of the PC_Function_Calculation block is given in Figure 3.1.(2-30). s1 and s2.

The logic diagrams of the Complex_Multiplier_1 and Complex_Multiplier_2 blocks are given in Figure 3. Finally the magnitude of the products is calculated as an output of the block.42 respectively. hstored is complex valued. As explained in Chapter II. gstored is purely real. The antenna patterns are defined as g = stored g * (φ ) | g (φ ) |2 + | h(φ ) |2 (3-8) stored h= h * (φ ) | g (φ ) |2 + | h(φ ) |2 (3-9) The Eq. therefore only real part is stored in memory. two blocks are designed for performing complex multiplication operation. Since the signal and table values are complex valued. therefore real and imaginary parts are stored separately.41 Logic Diagram of Complex_Multiplier_1 Block 57 . 1 UFix_12_11 a b Fix_23_22 xlmult (ab) -3 z table_real 2 Fix_12_11 z -1 Delay1 Fix_23_22 1 product_real signal_real Mult 3 Fix_12_11 a b Fix_23_22 xlmult (ab) z-3 signal_imag z -1 Delay2 Fix_23_22 2 product_imag Mult2 Figure 3.Using 64 MHz frequency steps.(3-7) is simplified in order to find the maximum of sg stored + dhstored function. The other antenna pattern. Then the complex products of the designed blocks are added together separately as real and imaginary parts. the antenna gain patterns of two antennas are stored in the memory.41 and Figure 3. Real and imaginary parts are normalized between 1 and 1 interval.

43.42 Logic Diagram of Complex_Multiplier_2 Block 3. estimated AOA value.43 Logic Diagram of the PC_AOA_Estimator Block 58 . At the end of the search interval.1. 1 UFix_20_19 Function a Bool xlrelational a>b b d Relational UFix_20_19 xlregister rst z-1 q en Max_Point 2 UFix_8_0 Angle_Count d -1 xlregister UFix_8_0 z q en YonIndex d xlregister UFix_8_0 z-1 q en YonIndex2 k =90 Constant UFix_7_0 3 Bool z -20 DelayLine Bool a xladdsub Fix_8_0 a-b b AddSub 1 AOA_Est Data_Ready Figure 3.2. is presented as an output of the block. The inputs to the block are Data_Ready.1 Fix_12_11 Fix_12_11 a b table_real 3 Fix_23_22 xlmult (ab) -3 z signal_real Mult 2 Fix_12_11 a xladdsub Fix_24_22 a-b 1 b z-1 product_real Adder1 a b Fix_23_22 xlmult (ab) -3 z table_imag 4 Fix_12_11 signal_imag Mult1 a b Fix_23_22 xlmult (ab) z-3 Mult2 a b Fix_23_22 xlmult (ab) z-3 a xladdsub Fix_24_22 2 a+b b z-1 product_imag Adder2 Mult3 Figure 3.1. Angle_Count and Function signals.7 PC_AOA_Estimator Block The aim of this block is to find the angle at which maximum of the function occurs over the search interval. AOA_Est. The logic diagram of the PC_AOA_Estimator block is given in Figure 3.

2. 12 clock cycles in PC_Function_Calculation block to calculate the ML function and 22 clock cycles in PC_AOA_Estimator block to find the angle at which maximum of the ML function occurs. Angle_In and Data_Ready signals. 39 clock cycles later AOA_Est is driven as an output. 3 clock cycles in PC_Angle_Counter block to determine the search interval. After Data_Ready strobe is high.2 Simulation Results Similar to the amplitude comparison hardware implementation. these signals are delayed with proper delay blocks. Figure 3. Likewise. Antenna displacement was chosen as 15 cm. 3. The latency is as follows. the real and imaginary parts of the pulse amplitude are set to 12 bits.44 Screen Shot from System Generator (Implementation of Phase Comparison Algorithm) 59 . the number of bits for representing the complex antenna gain values is set to 12.To synchronize the Correlation. 2 clock cycle to find the appropriate address in PC_Address block.2. The operating frequency range is selected between 2 GHz and 6 GHz.

45. AOA curves corresponding to different frequencies are plotted in Figure 3. 6 freq=2GHz freq=3GHz freq=4GHz freq=5GHz freq=6GHz 5 RMS Error (degrees) 4 3 2 1 0 -80 -60 -40 -20 0 20 AOA (degrees) 40 60 80 Figure 3. The pulses are generated when SNR value is set 20dB and pulse repetition interval (PRI) is set to 250 ns.In Figure 3. The AOA is estimated according to the calculated J( ) function. 5x103 simulations are performed for each AOA from -90 to 90 degrees.45 Phase Comparison Hardware Implementation RMS Error vs. AOA (SNR=20dB) 60 . The simulations of the implementation were performed at frequencies from 2 GHz to 6 GHz in steps of 1 GHz at 20dB SNR.44 screen shot of the scope in hardware implementation is plotted. which is AOA of pulse in this case. RMS error vs. For each pulse the search interval is defined around 20 degrees.

16 2.256 2.2 Mean (degrees) 30 29.5 Frequency (GHz) Figure 3.4 30.064 2.47 Mean of the Estimated AOA vs.8 (degrees) 1. hardware simulations are performed.2 2 1.4 2 2.224 2.46 Mean and The Standard Deviation of RMS Error 2. at lower frequencies the quantization errors are greater due to linear scaling of the antenna gain table. Therefore in order to see the quantization effects.8 29.192 2.384 2. Compared to higher frequencies. Frequency 61 .096 2.5 3 6 To investigate the quantization errors.2.5 4 4.48 Figure 3. The mean of the estimated AOA is given in Figure 3.6 1.47.416 2.448 2. 30.288 Frequency (GHz) 2.032 2.128 2. simulations are performed when the operating frequency is varied between 2000 MHz and 2512 MHz in steps of 8 MHz and AOA is 30 degrees at 20 dB SNR.6 29.352 2.4 1.8 Mean Standard Deviation 2 3.32 2.2 1 0.5 5 5.

1.416 2.096 2.48.2 1.032 2.288 2.384 2.224 2.504 Frequency (GHz) Figure 3.448 2.482.25 Software Simulation Hardware Implementation 1.95 0.32 2.064 2.147.1 1. which are utilized for the phase comparison algorithm implementation.256 2.128 2.85 2 2.05 1 0. are given in Table 3-5.192 2.733 62 .The RMS Error of the hardware implementation due to quantization of frequency is calculated and is compared with software simulation results in Figure 3.48 RMS Error of Hardware Implementation due to Frequency Quantization The hardware resources. Table 3-5 FPGA Resource Utilization Summary of Phase Comparison Implementation Number of Slices Number of Flip Flops Number of 4 input LUTs Number of External IOBs Number of MULT18X18s Total equivalent gate count for design 555 863 410 78 8 2.16 2.15 RMS Error (degrees) 1.9 0.352 2.

000 ns Actual Constraint : 4.00 < d < 2.719ns 0 ns.00 < d < 4.00 < d < 5. which extracts the pulse amplitude of the received signals.908 ns.According to timing analysis.079 ns. Phase_Comparison. The hardware implementation consists of three main blocks. complex valued signals are used. which performs phase comparison algorithm. which calculates the magnitude of the signal. However in practical usage it is not likely to extract complex representations of each pulse or continuous wave at the time of sampling. the following results are obtained.2.3 Part of PDW Generator Design After evaluating test results of the hardware implementation of the phase comparison algorithm. 4. 3.2. which performs I and Q demodulation. 3. all constraints were met and all signals are completely routed. 0.00 d >= 5. These are. is implemented and fitted before the phase comparison algorithm. 63 . since it is vulnerable to affects of noise or incorrect measurements very much. Moreover it is not very usable. The number of signals not completely routed for this design is: The average connection delay for this design is: The maximum pin delay is: The average connection delay on the 10 worst nets is: Listing Pin Delays by value: (ns) d < 1. the part of the PDW generator. Magnitude_Calculator.00 2813 1056 169 69 4 0 According to synthesis report. Requested Constraint : 5. Therefore it is more acceptable to represent the received signal per pulse basis or for CW signals for a period of time.781 ns.00 < d < 3. In mathematical formulation and implementation. • • • I_Q_Demodulator.

04 24 Sl id er Gai n5 double double Ra ndom So urce2 DSP double 0.2. The block diagram of I and Q demodulation process is given Figure 3.3.49 Block Diagram of Phase Comparison Implementation 3. In this case one of the received signals is used as a local oscillator.In the simulations the signals are sampled at a rate of 200 MHz. and it is assumed that there is no modulation in the pulse or in the continuous wave. Then the received signals are defined by s1= A sin (wt ) s 2 = A sin (wt + ϕ ) (3-10) (3-11) where A denotes the pulse amplitude. double db l ST R db l AOA db l fre q fpt Bool Da ta_ Ready 18 S li der Ga in1 double Sy stem Generator double double double fpt Fix_8_0 Data_Ready AOA_in put 2032 double DSP fpt UFix_13_0 AOA_input 0.5 I_ Q_Demodulator Block The signals received by the antennas are real valued.49. t represents time and φ is the phase difference. 64 .0424 Frequ ency Sin e Wave1 double F req double double s 1_m ag Fix_12_11 s1 Fix_12_11 AOA_Est Fix_8_0 fp t dbl double si m out T o Worksp ace db l fpt Fix_12_11 s ignal_1 i_part Fix_12_11 I_part m ag4 Ra ndom So urce1 P rod uct double Gateway In1 s2_real s 2_real Pul se Ge nerato r1 Product1 Sl id er Gai n3 double double dbl fpt Fix_12_11 s ignal_2 q_part Fix_12_11 Q_part s2_im ag s 2_im ag Fix_12_11 Gateway In I_ Q_ Dem odul ator M agni tude_Ca lcula tor Pha se_Comp ari son 0 . The block diagram of the hardware implementation is given in Figure 3.50. There are several methods to decompose the signal into these components [8].2. Demodulation of signals is often done by obtaining inphase and quadrature components.6 S li der Ga in4 0. w is the operating frequency.6 double Sin e Wave3 Figure 3.

1 signal_1 F ix_12_11 z -29 Delay1 F ix_12_11 a b F ix_23_22 xlm ult (ab) -3 z F ix_40_37 xn 33 tapyn xlfir xlslice [a:b] Slice1 U F ix_20_0 xlcast force F ix_20_19 F ix_37_34 xn 64 tapyn xlfir xlslice [a:b] Slice3 U F ix_12_0 xlcast force F ix_12_11 1 i_part M ult Reinterpret1 FIR_Averaging1 Reinterpret3 FIR_LPF1 a b z -29 Delay F ix_12_11 F ix_23_22 xlm ult (ab) -3 z F ix_40_37 xn 33 tapyn xlfir xlslice [a:b] Slice2 U F ix_20_0 xlcast force F ix_20_19 F ix_37_34 xn 64 tapyn xlfir xlslice [a:b] Slice4 U F ix_12_0 xlcast force F ix_12_11 2 q_part Mult1 Reinterpret2 FIR_Averaging2 Reinterpret4 FIR_LPF2 2 signal_2 F ix_12_11 F ix_30_26 xn 33 tapyn xlfir xlslice [a:b] Slice UF ix_15_0 xlcast force F ix_15_14 Reinterpret FDAT ool FIR_HilbertT ransform FDAT ool FDAT ool1 FDAT ool Figure 3. after I and Q demodulation process. the amplitude and phase difference information of original incoming signal is preserved.(3-13). The logic diagram of the implementation of I and Q demodulation is given in Figure 3. sin(wt )A.50 I and Q Demodulation After the I and Q demodulation is applied.(3-12) and Eq. sin (wt ) A.Figure 3. the in-phase and quadrature components are obtained as I = A. sin (wt + ϕ ) = A Q = A.51. sin(wt + ϕ − 90) = A 1 LP [cos (2 wt + ϕ ) + cos ϕ ] Filter → A cos ϕ 2 2 (3-12) 1 [cos(2wt + ϕ − 90) + cos(ϕ − 90)] LPFilter → A sin ϕ 2 2 (3-13) According to Eq.51 Logic Diagram of I and Q Demodulator Block 65 . whereas frequency is information is lost.

The filter is designed to pass the signal that has a frequency smaller than 10 MHz. the signals are exposed to a low pass filter (LPF) to eliminate higher order frequencies. Figure 3.In order to lag the second signal by 90 degrees.52. which is an all pass and performs 90 degree phase shift. The magnitude response of the 33 tap filter is shown in Figure 3. (3-13).53.52 Magnitude Response of FIR Filter (Hilbert Transformation) According to Eq. Figure 3. The filter is designed to pass the signals between 10 MHz and 90 MHz. The filter performs a Hilbert Transformation. (3-12) and Eq.53 Magnitude Response of FIR LPF 66 . The magnitude of the 33 tap LPF is shown in Figure 3. an FIR filter is designed.

54 Logic Diagram of Magnitude_Calculator Block 67 . Alternatively more or less filter taps can be utilized depending on the pulse width of the received signal. the real part of the signal is represented by in-phase component.2. In the implementation the FIR filter has 64 taps with constant coefficients.2.54. The rearranged signals are given by ′ s1= s′ = 2 A 2 (3-14) A A cos ϕ + j sin ϕ 2 2 (3-15) The logic diagram of the Magnitude_Calculator block is given in Figure 3. 1 I_part Fix_12_11 d xlregister F ix_12_11 z-1 q en Register1 x z -33 y m ag F ix_12_11 1 s1_m ag 2 Q_part Fix_12_11 d -1 xlregister F ix_12_11 z q en Register2 atan CORDIC AT AN a b k =1 Constant Bool Bool z -200 F ix_23_22 xlm ult (ab) z -3 z -30 Delay1 F ix_23_22 xlslice [a:b] Slice1 UF ix_12_0 xlcast force F ix_12_11 2 s2_real M ult1 a b 1.After the signals are filtered through LPF. For the output.67651367188 Constant1 U Fix_13_12 Reinterpret1 Delay xlm ult (ab) -3 z M ult2 F ix_23_22 z -30 Delay2 F ix_23_22 xlslice [a:b] Slice2 UF ix_12_0 xlcast force F ix_12_11 3 s2_im ag Reinterpret2 Figure 3.3.6 Magnitude_Calculator Block The inputs to this block are in-phase and quadrature components and the output is the amplitude of the received signals. they are averaged by another FIR filter. 3. on the other hand the imaginary part is represented by quadrature component. The other input is accepted as a reference and only magnitude of the signal is calculated since the phase difference is contained in the first output.

55 Block Diagram of the Phase Comparison Implementation Several simulations are performed under various conditions to have information about the DF accuracies of the phase comparison algorithm. a minor modification is made in the hardware implementation.2. is removed. 68 . The imaginary part of s1. 1 Data_Ready Data_Ready Angle_Count z -12 Delay1 2 AOA_input AOA_input PC_Angle_Counter Angle_Count Address 3 Freq z -3 Delay3 Frequency PC_Address Address 4 s1 5 s2_real 6 s2_imag z -5 Delay5 s1 Function Function z -5 Delay6 s2_real Angle_Count AOA_Est 1 AOA_Est z -5 Delay4 s2_imag Data_Ready PC_Function_Calculation PC_AOA_Estimator z -16 Delay2 Figure 3.55. Since adequate simulation results are obtained for the hardware implementation of phase comparison algorithm. In order to see the affects of i and q demodulation and quantization. Since one of the input signals is represented as a pure real signal.2.4 Simulation Results The output of the PDW generator block is driven to the phase comparison block to locate the angular position. which is 0. in this part limited simulations will be performed and compared to previous results.3. simulations are performed once again. The modified block diagram of the phase comparison implementation is given in Figure 3.

First. Table 3-6 Mean and Standard Deviation of RMS Error of Estimated AOA Frequency 2032 MHz 2992 MHz 4016 MHz 5040 MHz 6000 MHz Mean (degrees) 20. again some precision is lost. the mean of the estimated AOA values are very precise.997 20. between these steps the signals are truncated and the number of bits is decreased since they grow up large.876 0.002 19. On the other hand. the outputs are averaged with a 64 tap FIR filter. while finding the magnitude of the in-phase and quadrature components. Regarding these points. is generated and is added to signal to obtain a SNR value of 20 dB.003 20. whose variance is equal to 1 and mean is 0. which are obtained in Chapter 3.458 According to the Table 3-6.176 0. the standard deviation of the estimations is slightly larger than the expected results. White Gaussian noise.451 0. Lastly. Clearly. averaging the outputs minimizes the affect of noise. 69 . Secondly.3. Simulation results are given in Table 3-6. where some precision is lost in the process.05 20.530 0. the signals are exposed to filters in I and Q demodulation phase. On the other side in I and Q demodulation process.2. In short mostly the error occurs due to quantization.001 Standard Deviation (degrees) 1. the DF accuracy is calculated to be slightly larger than the hardware implementation results. sampling rate is set to 200 MHz and AOA chosen as 20 degrees.In the simulations. There exist some reasons beneath this fact.

The phase comparison system considered consists of a linear phase array of two omni directional antennas. This AOA is taken as a center of a search interval. Over this search 70 . utilizing only three pulse amplitudes instead of pulse amplitudes from all channels provides a better DF accuracy at low SNR values. are determined. two well-known monopulse direction finding techniques. In both algorithms mathematical modeling is done using maximum likelihood approach. namely amplitude comparison and phase comparison algorithms are implemented on an FPGA platform. According to simulation results. Over this search interval. then the pulse amplitudes received from the antennas. the prior information of AOA is input to the algorithm. In both approaches the boresight of the antenna. The amplitude comparison system consists of a circular array of six equally spaced antennas. since it is directly related to the number of ambiguous points. AOA is estimated depending on the ML function. which receives the maximum pulse amplitude. In order to resolve ambiguity problem.CHAPTER IV CONCLUSIONS In this study. One of the most important parameter in a phase comparison system is the ratio of the antenna baseline spacing to the wavelength of the received signal. As the SNR value increases both approaches have similar DF accuracies. first the antenna that receives the maximum pulse amplitude is determined. Whereas in the second approach. is selected to be the center of the search interval of 120 degrees. In the first approach pulse amplitudes received from all of the antennas are used. These three pulse amplitudes are taken into consideration and used in the DF algorithm. which are adjacent to this antenna. Two approaches are proposed to locate the angular position of the emitter using the amplitude comparison algorithm.

Hardware simulations of both algorithms were performed at a FPGA clock frequency of 200 MHz. since FPGA is widely used in DSP and digital communication areas. The operations like division and taking square-root require more hardware resources and have long cycles of process time. Consequently AOA is estimated by examining the ML function. which is equivalent to 5 ns of clock period. Another important point is the number of bits required for each signal to be represented in the FPGA. Hence. Therefore the throughput is not limited directly by the core clock. multiplying with a constant or division in FPGA. Number of bits in the algorithm was chosen to be 12 for representing the signal amplitudes and antenna gain tables. The primary aim of the thesis is to evaluate both of the algorithms and to implement them on an FPGA platform. Hence while implementing the algorithms. throughput can be easily increased according to design specifications. The number of bits used in the design is proportional to the resources used in FPGA. in the hardware design these operations were avoided as much as possible. The calculated quantization errors were very small. since insignificant precision is lost regarding the FPGA resource allocation. By using parallel structures. In implementation phase of the algorithms. Target platform is selected to be FPGA. the performance and the resource allocation trade-off must be taken into consideration. the algorithms were modified and optimized in order to have a better performance with less complexity and less hardware resources while not distorting the DF accuracy of the algorithms. First. the ML function depending on complex pulse amplitudes and complex antenna gains are calculated. The amplitude comparison 71 . Therefore the results may contain large quantization errors. The form of antenna gain tables stored in RAM was modified to avoid the operations like taking square root. some limitations and modifications were considered to meet the desired results. The advantage of using FPGA is that highly parallel structures can be employed when compared to DSP chips or microprocessors. but limited by the FPGA resources.interval.

Actually the process time of both algorithms is directly proportional to the defined search interval. The results of both amplitude comparison and phase comparison algorithm simulations indicate that the RMS error varies depending on the angular location of the emitter. The same improvements. which means processing of nearly 1.1 degrees over the 2GHz and 6 GHz frequency range. it takes 20 clock cycles to determine the AOA of emitter. the throughput can be increased.9 and 2.2 degrees at 20dB SNR. Therefore mean of the RMS error is taken as an evaluation criterion at fixed SNR. Phase comparison algorithm has better DF accuracy when compared to amplitude comparison algorithm. The cost of using parallel structures is to allocate more resource in the FPGA. mean of the RMS error obtained in software simulations is nearly 5. since FPGA platform designs are highly configurable and flexible. 72 . which means processing of nearly 10 MPPS. For the amplitude comparison algorithm. The amplitude comparison blocks can be used in parallel or some adjustments may be performed in algorithm like minimizing the search interval. The results of the hardware implementation of both algorithms in FPGA with fixed point arithmetic clearly demonstrated that the errors due to quantization are very small. When SNR is equal to 20dB and the baseline spacing is set to 15 cm. If more speed is needed according to system needs. For the phase comparison algorithm.6 MPPS.algorithm implementation on FPGA is able to locate the angular position for 120 clock cycles. are keys to minimize the process time to determine the AOA. the mean of the RMS error alters between 0. like using parallel structures or shortening the search interval if possible.

Ph.REFERENCES [1] D. “Direction finding with a Uniform Circular Array via Single Snapshot Processing”. 1999. Ms. [5] Avionics Department of the Naval Air Warfare Center Weapons Division “Electronic Warfare and EW Systems”. 2001. Middle East Technical University. “Probability. “Direction Finding With a Uniform Circular Array Placed on a Moving Platform”. “Discrete Random Signals and Statistical Signal Processing”. [10] Athanasios Papoulis.D. Middle East Technical University. [6] Stephen E. “Microwave Passive Direction Finding”. ”Design of a Monopulse Comparison DF processor Using A Maximum Likelihood Algorithm”. Artech House. Random Variables and Stochastic 73 . [3] Arzu Tuncay Koç. “Electronic Warfare in the Information Age”. 1987 [7] Ferhat Arıkan. Curtis Schleher. 1993. [2] Evrim Anıl Evirgen. 1996. “Electronic Intelligence: The Analysis of Radar Signals”. 1992. Ms. Thesis. Wiley. “Monopulse Principles and Techniques”. Thesis. 1993. 1984. [9] Charles W. [8] Richard G. Thesis. [4] Samuel M. Lipsky. Wiley. Middle East Technical University. Artech House. Prentice Hall. Artect House. Therrien. 1992. Sherman.

[13] Steve Zack. A Tutorial Indroduction”. Xilinx Inc. McGraw-Hill Inc. 2002. 2004. [11] “Virtex-II Pro Platform FPGA Handbook”. 74 . [12] “Xilinx System Generator for DSP v6. [14] J.Processes”.”DSP Co-Processing in FPGAs: Embedding HighPerformance. “System Level Tools for DSP in FPGAs”. Milne. Xilinx Inc. B. 1991. Suhel Dhanani . Low-Cost DSP Functions”.3 User Guide. “TableCurve 2D”. Hwang.Xilinx Inc. 1994. 2001. 2004. [15] AISN Software.

The equation list is sorted by tool’s goodness-of-fit sort criteria and its contents can be filtered to only contain certain types of equations. c is equal to 180.APPENDICES APPENDIX A A. The graph can be scaled and formatted. A great variety of output options like full numeric evaluation of the selected equations are available.9999. d is equal to 28. b is equal to 0. 10dB beamwidth is selected to be 120 degrees. According to the design specifications. data references and a fit reference. 10dB beamwidth and minimum gain of the antenna. The software tool [15] is capable of displaying the X-Y data along with the fitted equation.7382 and e is equal to 0. the antenna pattern is obtained by fitting a Gaussian curve.1 Antenna Gain Pattern A software tool is utilized to generate the antenna gain pattern for the amplitude comparison method.9x10-05. The half-wave beamwidth of the antenna is determined to be 60 degrees. 75 . and the minimum gain along the antenna pattern is set to 40dB.4218. which is given by (1 − e ) ( x − c ) 2 2 d y = a + b (x − c ) 1 + e d 2 − e (A-1) where. and optionally with confidence and/or prediction intervals. The main design criteria considered for the generation of the antenna pattern are 3dB beamwidth. a is equal to 9.

is given in Figure A. 0 -5 -10 -15 Gain (dB) -20 -25 -30 -35 -40 0 30 60 90 120 150 180 210 Angle (degrees) 240 270 300 330 360 Figure A.The generated antenna pattern.1 Generated Antenna Pattern for Amplitude Comparison 76 .1. which is plotted in logarithmic scale.

APPENDIX B B. where performance is tied to the clock rate at which the processor can run. For example. tristate buffers. an FPGA can be reprogrammed. FPGA performance is derived from the ability they provide to construct highly parallel architectures for processing data. It is "programmed" by the designer rather than the device manufacturer. These resources include dedicated 18x18 bit multipliers. even after it has been deployed into a system. [12] There are wide ranges of DSP applications as digital up/down converters. which can perform a similar function in an electronic system. digital FIR filters etc that can be implemented only in custom integrated circuits (ICs) or 77 . Currently system frequencies of 100-200 MHz are commonly used today.1 FPGA’s A field programmable gate array (FPGA) is a general-purpose integrated circuit. and digital clock managers. An FPGA provides the user with a two-dimensional array of configurable resources that are used to implement a wide range of arithmetic and logic functions. Unlike an application-specific integrated circuit (ASIC). the raw memory bandwidth of a large FPGA running at a clock rate of 150 MHz can be hundreds of terabytes per second. FPGAs are high performance data processing devices. lookup tables (LUTs). FPGA performance is tied to the amount of parallelism that can be brought to bear in the algorithms making up a signal processing system. Compared to a microprocessor or DSP processor. multiplexers. registers. A combination of increasingly high system clock rates and highly distributed memory architecture gives the system designer an ability to exploit parallelism in DSP applications that operate on data streams. dual port memories.

which allows a design to be modified. even after deployment in an end application. Figure B.specifically in an FPGA. the LUTs can also be used to build fast adder/subtractors and multipliers of essentially any word size.1 Virtex Family FPGA Logic Slice Logic Slice is the fundamental unit of the logic fabric array. and gates used for creating slice based multipliers. Each logic slice contains two 4-input lookup tables (LUTs). each LUT can also be configured as a 16x1 bit RAM or as a shift register (SRL16). Each LUT can implement an arbitrary 4-input Boolean function. An SRL16 shift register is a 78 . dedicated carry logic. which is given in Figure B. Advantages of using an FPGA include significantly lower non-recurring engineering costs than those associated with a custom IC (FPGAs are commercial off-the-shelf devices). It is instructive to take a closer look at the Virtex family logic slice construction. multiplexers.1. In addition to implementing Boolean functions. and the configurability of an FPGA. two configurable D-flip flops. shorter time to market. Coupled with dedicated logic for implementing fast carry circuits.

but also dedicated circuitry for fast adders. especially in the areas of digital communications. video. field-programmable gate arrays (FPGAs) have become key components in implementing high performance digital signal processing (DSP) systems. The memory bandwidth of a modern FPGA far exceeds that of a microprocessor or DSP processor running at clock rates two to ten times that of the FPGA. multiplexers. The logic fabric of today's FPGAs consists not only of look-up tables. distributed and block memory. In recent years. networking. giga-bit I/O). 79 .synchronously clocked 16x1 bit delay line with a dynamically addressable tap point.g.. this makes the FPGA ideally suited for creating high-performance custom data path processors for tasks such as digital filtering. and I/O processing (e. Coupled with a capability for implementing highly parallel arithmetic architectures. and imaging. fast Fourier transforms. multipliers. registers. and error correcting codes [14].

APPENDIX C

**C.1 Development Tool Flow
**

Using MATLAB® and Simulink® from MathWorks, coupled with Xilinx System Generator™ for DSP, signal processing algorithms can be modeled, simulated, and verified specific to target hardware platform in the Simulink environment. When the simulation is run, various signals can be stored as variables in the workspace providing to make post simulation analysis. The design flow typically involves the following steps: First hardware model is developed and verified by the using industry tools. Then, Xilinx System Generator generates an HDL circuit representation that is bit- and cycle-true meaning that the behavior is guaranteed to match the functionality seen in the simulation model. Finally, the Integrated Software environment (ISE) design tools synthesize the design and produce a bitstream that is used to program the FPGA. The error-prone and timeconsuming phase, which is translating the hardware design into HDL, is automatically done by the software tool [13].

**C.2 Xilinx System Generator
**

System Generator is a new system level tool built on top of Simulink. It facilitates DSP design for FPGAs. Simulink provides a convenient high level modeling environment for DSP systems, and consequently is widely used for algorithm development and verification. System Generator maintains an abstraction level while keeping the traditional Simulink blocksets. System Generator automatically translates designs into hardware implementations. The implementation is faithful in that the system model and hardware implementation are bit-identical and cycleidentical at sample times as designed in Simulink. The implementation is made efficient through the use of Intellectual Property (IP) cores that provide a range of 80

functionality from arithmetic operations to complex DSP algorithms. These cores have been carefully designed to run at high speed and be area efficient [14]. System Generator provides two main Matlab Simulink simulation libraries, the "Xilinx Blockset" and "Xilinx Reference Blockset". Each library contains blocks that are used to construct models in Simulink environment. These blocks provide arithmetic, logic, memory, and signal processing abstractions suitable for implementing DSP systems in an FPGA platform. In addition to these simulation libraries, System Generator provides implementations for each function, and code generation software for translating subsystems comprised of Xilinx blocks into hardware descriptions of the system model. The simulation models are bit-accurate to the hardware description, and at sample rates observable in Simulink, are also clock cycle accurate to the hardware. Consequently, the detailed hardware behavior can be understood from the Simulink simulation [12]. A System Generator model is constructed of blocks from the Xilinx blocksets, each of which contributes to the hardware description created by the code generator. One of the primary advantages of designing hardware using System Generator is the rich simulation framework Simulink provides to stimulate, debug, and analyze the executable model [12]. Each realizable signal which is to be translatable into hardware, must be sampled and be either a fixed-point or Boolean type. Since System Generator’s goal is to model realizable digital systems, it does not support modeling of continuous time signals. Data types and sample rates are propagated through a System Generator model under normal Simulink propagation rules. This means that any source to a System Generator subsystem must be sampled and quantized. Signals passing from Simulink blocks to Xilinx blocks must go through Xilinx gateways, which enforce these constraints [12]. An output data type of Xilinx blocks can be boolean, unsigned, or signed (two's complement), with a user-defined numerical precision. Figure C.1 shows a Xilinx Multiplier that forces outputs to be a 16-bit unsigned value, with 15 fractional bits. 81

Quantization parameter can be truncate or round (unbiased: /- Inf). In the user defined parameters overflow parameter must be selected one of wrap, saturate or flag as error.

Figure C.1 Function Block Parameters of a Xilinx Multiplier Block

As seen in Figure C.1, FPGA provides flexibility in defining arbitrary fixed point arithmetic precision throughout the design and computation. The amount of FPGA hardware resources are directly related to the data width that is defined throughout design. Therefore it is wise to request only the data width and precision needed. Otherwise the FPGA resources are used excessively. This will cost more money, less circuit speed, and much power dissipation. System Generator is particularly useful for algorithm exploration, design prototyping and model analysis. When these are the goals, the tool is used to flesh out an algorithm in order to get a feel for the design problems that are likely to be faced, 82

and there is little need to translate the design into hardware. a designer assembles key portions of the design without worrying about fine points or detailed implementation.and perhaps to estimate the cost and performance of an implementation in hardware. Work is preparatory. Experiments using hardware generation can suggest the hardware speeds that are possible. In this setting. Resource estimation gives a rough idea of the cost of the design in hardware.m code provide stimuli for simulations. 83 . and for analyzing results. Simulink blocks and MATLAB .

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