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Computer design is concerned with [01D01] The determination of what hardware should be used and how the parts be connected. 2. A digital computer with more than one processor is called as [01D02] Multiprocessor System 3. Computer Organization is concerned with [01M01] The way hardware components operate and connected together to form Computer system. 4. Computer architecture is concerned with [01M02]The structure and behavior of the computer as seen by the user. 5. In a computer system control information is transferred in [01M03] control bus only 6. The part of the hardware of computer that controls the transfer of information between computer and the outside IOP 7. The part of the hardware of computer that is used to manipulate data is [01S02] CPU 8. The functional entity of computer system that does not have physical existence is [01S03] Software 9. Digital computers use [01S04] Binary number system 10. A system software is [01S05] A program to make effective use of computer 11. Which of the following statement(s) is(are) correct? [01S06] Instructions in a stack-based organization take up less memory than general purpose register organization instructions. 12. Signed 1's complement representation of -14 with eight bits is [02D01] 11110001 13. 2's complement representation of -32 with eight bits is [02D02]11100000 14. The 1' s complement of decimal number 21 in binary is [02M01] 01010 15. Signed 2's complement representation of +14 with eight bits is [02M02] 00001110 16. 2's complement representation of 16 with eight bits is [02M03] 00010000 17. The complement of decimal number 85 is [02S01]14 18. The complement of decimal number 65 is [02S02] 35 19. The 1's complement of binary number 01011011 is [02S03] 10100100 20. The 2's complement of binary number 01010001 is [02S04] 10101111 21. Signed magnitude representation of -7 with eight bits is [02S05] 10000111 22. The advantage with normalized floating-point number is [03D01] provide maximum possible precision 23. A floating point number is said to be normalized [03D02] if the most significant digit of the mantissa is nonzero 24. In floating point representation the radix [03M01] is assumed and not represented physically 25. In floating point representation the radix position [03M02] is assumed and not represented physically 26. A normalized floating-point decimal number is [03M03] 3.456 27. The two parts in floating-point representation are [03S01] mantissa , exponent 28. The part in floating-point representation that denotes position of the radix point is [03S02] exponent 29. In floating point representation, the fixed point mantissa [03S03]may be fraction or integer 30. In floating point representation, the fixed point mantissa [03S04] is signed number 31. A normalized floating-point binary number is [03S05] 1.010 32. Odd parity generator can be implemented with [04D01] Exclusive - OR & Exclusive - Nor function 33. If 3 bit messages are transmitted suffixing with P (odd) bit the erroneous message is [04D02] 1010 34. Parity checker networks are constructed with logic circuits comprising [04M01]exclusive OR logic gates 35. Even parity generators can be implemented with [04M02] exclusive OR functions 36. If 3 bit messages are transmitted suffixing with P (even) bit the erroneous message is [04M03] 0100 37. If a 3 bit message 010 is transmitted with suffix of even parity bit , the resultant message is [04S01]0101 38. If a 3 bit message 101 is transmitted with suffix of even parity bit , the resultant message is [04S02] 1010 39. If a 3 bit message 110 is transmitted with suffix of odd parity bit , the resultant message is [04S03]1101 40. If a 3 bit message 011 is transmitted with suffix of odd parity bit , the resultant message is [04S04] 0111 41. Even parity generator is constructed with logic circuits comprising [04S05] exclusive OR logic gates 42. A Common bus system is connected with four registers of 4-bit capacity using binary MUXs . The number of MUXs 4 43. A Common bus system is connected with four registers of 4-bit capacity using binary MUXs. The size of each MUX each 4 X 1 44. The function that allows register transfer under a predetermined condition is [05M01] Control function 45. The state of the three-state gate when input is not connected to output is [05M02] high impedence state

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The logic micro operation that denotes complement of B is [07S05] F_B’ 67.46. In IAS computer address part specifies [09S02] Address of operand in memory 84.. If the content of 8 bit register R1 is 11010011. The arithmetic micro operation denoting decrementing the content of R1 by one is [06S03] R1_R1-1 58. The arithmetic micro operation denoting 2's complement is [06M03] R1_ R1’+1 55. The symbolic notation used to describe the micro operation transfers among registers is called [05S02]Register Transfer language 49. 2ns to decode the instruction. The arithmetic micro operation R2_ +1 denotes [06M01]2's complement of R2 53. Techology News. The content of register R1 after execution of R1_shl R1 micro operation 10100110 74. The arithmetic micro operation R3_R1+ +1 denotes [06D01] Subtraction of R2 from R1 51. The operation executed on data stored in registers is called [05S01] Micro operation 48. The content of register R1 after execution of R1 _ ashr R1 micro operation is [08S04]11101001 76. The part of instruction code that specifies operation to be performed is [09S01] opcode 83. In direct addressing mode address part of instruction specifies [09M01] Address of operand in memory 79. The logic micro operation that denotes exclusive NOR is [07S04] F<-(A+B)’ 66. If it takes 5ns to read an instruction from memory. The general-purpose computer register is [09D01] Accumulator 78. If the content of 8 bit register R1 is 11010011. The arithmetic micro operation denotes [06S01]The sum of R1 and R2 is transferred to R3 56. The category of micro operation used for serial transfer of data is [08D01] shift micro operation 68. 3ns to read the register file. Address 18 bits 87. The arithmetic micro operation denoting negation is [06D02] R2 R2_ +1 52. The logic Micro operation that denotes clear is [07S01] F_0 63. Opcode 5bits. what is the maximum 62. The instruction that clears start stop flip flop and stops sequence counter from counting is [10M01] HLT 100 % free SMS ON<space>UandIStar to 9870807070 for JNTU Alerts. The arithmetic micro operation denoting subtraction of R3 from R1 is [06M02] R1_R1+ R3’+1 54. The symbolic form used to denote transfer of content of register R1 into register R2 is [05S03] R2<-R1 50. Register 8bits. Register transfer denoting memory write operation is [05M03] M {[AR]}_DR 47. an operation code. In indirect addressing mode address part of instruction specifies [09S03]Address of memory location containing address of operand 85. The instruction has fourparts: an indirect bit. The shift micro operation used to divide signed binary number by 2 is [08M02]Arithmetic shift right 71.5 MHz 82. . The logic micro operation used to selectively set bits is [07G02]F_B A 61.. The content of register R1 after execution of R1_Cir R1 micro operation 11000110 75. The shift micro operation used to multiply signed binary number by 2 is [08M01] Arithmetic shift left 70. The computer register used to hold address of instruction is [09M02] Program counter 80. 4ns to perform the computation requiredby the instruction.. The function denoted by arithmetic operation F=A-1 is [08S05] decrement 77. A binary instruction code is stored in one word of memory. The arithmetic micro operation denoting 1's complement is [06S04] R1_ R1’+1 59.. The logic micro operation that denotes transfer A is [07S03] F_A 65. The logic micro operation used to selectively clear bits is [07G03] F_A U’B 62. The function denoted by arithmetic operation F=A+B+1 is [08M03] Add with carry 72. The computer register that specifies memory address is [09M03] Address register 81. The logic micro operation that denotes AND is [07S02] F_A U’B 64. The function denoted by arithmetic operation F=A+ is [08D02] subtraction with borrow 69. JOB Alerts & more. The arithmetic micro operation denoting complement is [06S05]R1_R1’ 60. If the content of 8 bit register R1 is 11010011 . a register code part to specify one of 64 indirect 1bit. and 2ns to write the result into the register file. Tips/Tricks. The content of register R1 after execution of R1_shr R1 micro operation 01101001 73. A computer uses a memory unit with 256K words of 32 bits each. The computer register used to hold instruction code is [09S04] Instruction register 86. If the content of 8 bit register R1 is 10001101.. On executing the arithmetic micro operation R2_ [06S02] Content of R2 is Complemented 57.

The program control instruction that sets the status bits by performing a subtraction between two operands is CMP 124. The addressing mode in which the address part of the instruction gives address of effective address of operand is Indirect Address Mode 114. The CPU organization in which all operations are performed with two or three register fields is [12M01] General register organization 109. Immediate i. In Register Stack the stack pointer register (SP) contains The address of the word that is currently on top of stack 110. A computer uses a instruction format that has three parts: an indirect part. Direct ii.) Multiple memory references 2. The addressing mode in which the address part of the instruction gives effective address of operand is [13M01] Direct Address mode 113. The bus is constructed with multiplexers. The memory reference instruction that denotes operation M[AR]_M[AR]+1. Tips/Tricks. The addressing mode that specifies register operands is [13S03] Register Mode 118.. In the instruction cycle the phase that reads instruction into instruction register from memory is [10S01] Fetch 93. The addressing mode that specifies operand in the instruction itself is [13S02] Immediate Mode 117. The addressing mode that specifies register containing address of operands is [13S04] Register Indirect Mode 119. The program control instruction that do not change program sequence directly is [14D01] CMP 121. The addressing mode in which the address part of the instruction is added to program counter in order to obtain effective address is [13D01] Relative Address Mode 111. In the process of information transfer to input register from input device the initial value of control flip-flop FGI is 0(Zero) 105. The input-output instruction that denotes operation If (FGI =1) then PC_PC+1 is [11M02] SKI 100. The Input-Output Instruction that denotes operation If (FGO =1) then PC_PC+1 is [11M03]SKO 101.. if M[AR]+1=0 then PC_PC+1 is [11D01]ISZ 97.. 083. . The CPU organization that does not use an address field for the instructions is [12D02] Stack organization 108. The interrupts that arise from illegal or erroneous use of an instruction or data are [14M03]Software interrupts 125. The DATA manipulation instruction is [13M03] MUL 115. The characteristic that is not applicable for RISC architecture is [14S03] Micro program control 128. The CPU organization in which all operations are performed with an implied accumulator register is [12D01] Single accumulator organization 107.88. The addressing mode that specifies operands implicitly in the definition of the instruction is [13S01] Implied Mode 116. The memory reference instruction that denotes operation M[AR]_PC. In the process of information transfer to output register from accumulator the initial value of control flip-flop FGO is 1 (one) 106. 021 89. The status bit that is set to 1 if the exclusive-OR of the last two carries is equal to 1 is [14D02] V (Overflow) 122. A832. In the instruction cycle the phase that reads effective address from memory location is [10S02] Read effective address 94. Techology News. The instruction that increments accumulator is [10S03] INC 95. The memory reference instruction that denotes operation PC _AR is [11M01] BUN 99. The program control instruction that does not need an address field is [14S02] SKP 127. The characteristic that is not applicable for CISC architecture is [14S04]Fixed Length instruction format 100 % free SMS ON<space>UandIStar to 9870807070 for JNTU Alerts. The program control instruction that is used in conjunction with subroutines is [14S01] RET 126. A digital computer has a common bus system for 16 registers of 32 bits each. Match the following: 1.) No memory reference 3.. The DATA transfer instruction is [13D02] MOV 112. The memory reference instruction that denotes operation M[AR]_AC is [11S02] STA 103. Which of the following statement(s) is(are) correct? [10M03]CISC has more complex circuitry than RISC 90.PC _AR+1 is [11D02] BSA 98. and an address part. The memory reference instruction that denotes operation AC _ AC _ M[AR] is [11S01] AND 102. The shift instruction is [13S05] ROR 120. 1:ii. 3:i 91. B8F2.. The memory reference instruction that denotes operation AC _ M[AR] is LDA 104. The instruction that clears accumulator is [10S04] CLA 96. JOB Alerts & more. Indirect iii. How many selection inputs are 4 92. One of the operand is AC and is 022.) One memory reference [10M04] b. 2:iii. and operation code. The program control instruction that sets the status bits by performing logical AND of the two operands is [14M01]TST 123.

150. The 9`s complement of a BCD number is obtained by complementing the bits in the coded representation with a correction. What will be the quotient and remainder when is divided by in 2's complement binary representation? [17M05] Quotient 00000. The program that translates symbolic micro program into its binary equivalent is [16M02] Assembler 144. In adding two signed magnitude numbers. The symbolic microinstructions that loads SBR with a new value is [16D02] CALL 142. Let A(0111) and B(1001) be two BCD numbers. A system uses a control memory of 1024 words of 32bits each.129. microprogram iii. 146. [16S02] Horizontal microinstruction. 1:i. Remainder 01011 158. The sum of A and B in BCD is [17M02] 0110 with a carry of 1 154. Remainder 10101 157. parallel adder is implemented with [17M01] full adders 153. Sequence of microoperations [16S05]. Tips/Tricks. Branch address. Operations executed on data stored in registers 2. The 9's complement of BCD number 0111 is [17S01] 0010 159. Which of the following statement(s) is(are) correct ? [16S03] The horizontal microinstruction requires more bits than vertical microinstruction. The Pseudo-instruction that specifies first address of a micro program routine is [16D01] ORG 141. Most computers based on RISC architecture [16M01] use hardwired control unit 143. The address of next microinstruction is stored in [15M03] Control address Register (CAR) 135. microinstruction ii. 149. The microinstruction has three fields: Condition. Consider register A holding decimal 8760 in BCD.. Sequence of microinstructions3. The register used to store return address of sub routine is [15S05] Sub routine register (SBR) 140. Internal interrupts are also called as [14S05]Traps 130. [17S02] 0000 1000 0111 0110 100 % free SMS ON<space>UandIStar to 9870807070 for JNTU Alerts. The microinstruction has two fields: Address and Microoperation fields. The process of transferring instruction code bits to an address in control memory where the routine is located is referred as [15M02] Mapping 134. hardwired implementation. In performing addition and subtraction of signed 2's complement data. The micro operation dshr A (Decimal shift right register A) produces. The alternate way of implementing mapping function instead of ROM is [15D02] Programmed Logic Array 132.. If the microoperation has 13bits. and Microperation fields. The most computers based on RISC architecture concept use [15D01] program counter 131. how many bits are there in the branch address field and the condition field? [16M03] Branch address has 10 bits and condition field has 6 bits 145. microoperation i. [16S01] Vertical microinstruction. Match the following:1. Arrange the following with the increasing speed of execution. The correction is [17M04] binary 10 (1010) is added to each complemented digit and the carry is discarded after each addition 156. What will be the quotient and remainder when is divided by in 2's complement representation? [17M06] Quotient 00000. Micro instructions are stored in [15S04] Control memory 139. The function of control unit in digital computer is [15S01] to initiate sequence of micro operations 136. If the control signals are generated using hardware with conventional logic design techniques then the control unit is said to be [15S02] Hardwired 137. . The memory that is part of control unit is [15S03] Control memory 138. 3:ii 151. Techology News. Which of the following statement(s) is(are) correct? [16S04]Variable microinstruction format increases complexity of microprogram control unit. Assume that the control memory is 24 bits wide. BCD adder performs sum in binary and converts the binary sum to valid BCD representation whenever the binary sum is greater than 1001.. vertical microinstruction.. hardwired implementation 148. 147. 2:iii. If the microoperation field has 16 bits. horizontal microinstruction. Invalid binary sum is corrected by [17M03] adding binary 6 (0110) to the binary sum 155. JOB Alerts & more. Arrange the following with the increasing logic of circuitry. The next address generator in a micro programmed control unit is referred to as [15M01] Sequencer 133.. if an overflow occurs [17D01]there will an erroneous results in AC 152. how many bits are there in the address field and what is the size of the control memory? [16M04] Address field has 11 bits and the size of the control memory is 2048x24 bits.

[18D05] 0 1000 0110 0010 0111 1000 0000 0000 000 169.. or subtractions . Use IEEE single-precision floating-point numbers to compute (147. BCD adder performs sum in binary and converts the binary sum to valid BCD representation whenever the binary sum C=K+Z8Z4$+Z8Z2 178. Which of the following statement(s) is(are) in correct? [18M03] Binary division operation may never result in a quotient overflow. The 10's complement representation of in BCD is [17S06] 1001 0111 0010 0101 164. Consider register A holding decimal 8760 in BCD.. What value is represented by the following IEEE single precision floating-point number 1 0111 1010 1000 0000 0000 0000 0000 0000 000 [19D02]c. Techology News. -. In floating point arithmetic operation. Which of the following statement(s) is(are) correct? [18M04] There can be no mantissa overflow after a multiplication operation in floating point representation 173.5) +(0. In decimal arithmetic the symbolic designation represents [20S02] 9's complement of B 188. The signed magnitude representation of in BCD is [17S04] 1001 0010 0111 0101 162. JOB Alerts & more. Which of the following statement(s) is(are) correct? [19M04] For a fixed format. Express the number -1/32 in IEEE 32-bit floating point format [18D02]1 0111 1010 0000 0000 0000 0000 0000 000 166. Decimal arithmetic operations use [20M02] BCD adders 186.160. In decimal multiplication the sequence counter (SC) is set to [20D01]number digits in multiplier 184. In decimal arithmetic the symbolic designation +1 represents [20S03]10's complement of B 189. In decimal arithmetic the symbolic designation A_A+B represents [20S01]add decimal numbers A and B and transfer sum into A 187. In decimal arithmetic the symbolic designation dshr A represents [20S04] decimal shift right register A 190. 182. . What is the sum of in BCD? [18M05] 0000 0001 1000 174. Use IEEE single-precision floating-point numbers to compute the (32) X(16) . for each arithmetic operation [19S01] the results will be normalized 183. Tips/Tricks. when the multiplier bit is identical to the previous multiplier bit [18M01] The partial product does not change 170. In decimal arithmetic the symbolic designation dshl A represents [20S05] decimal shift left register A 100 % free SMS ON<space>UandIStar to 9870807070 for JNTU Alerts. a larger exponent base gives a greater range of expressible values at the expense of less precision. Which of the following statement(s) is(are) correct? [18M02] An overflow can be detected in addition whenever the carry into the sign bit position and the carry out of the sign bit position are not equal in binary addition 171. To perform multiplication of two signed 2's complemented numbers using Booths algorithm. Use IEEE single-precision floating-point number to compute (32) ÷ (16) .046875 176. 172.25) . Division of two floating point numbers requires [19M02]Subtraction of exponents and division of mantissas 180. if two exponents are not equal then [19D01] mantissa having smaller exponent is shifted to the right 175.. In performing floating-point addition. [18D04] 0 0000 0000 1000 0000 0000 0000 0000 000 168. In Decimal Arithmetic operations decimal number are stored in [20M01] BCD form 185.0.. Express the number in IEEE 32-bit floating-point format [18D01] 0 1000 0111 1000 0000 0000 0000 0000 000 165. The 9's complement representation of in BCD is [17S05]1001 0111 0010 0100 163. BCD adder performs sum in binary and converts the binary sum to valid BCD representation whenever the binary sum c=k+z8z4+z8z2 177. What is the signed binary product of in binary? [19M03]1101110001 181. The micro operation dshl A (Decimal shift left register A) produces.. [17S03] 0111 0110 0000 0000 161. [18D03] 0 1000 1000 0000 0000 0000 0000 0000 000 167. Multiplication of two floating point numbers requires [19M01]Addition of exponents and multiplication of mantissas 179.

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