) 1 (
1
2
) (
2
V
V
THD
i
i
) 1 (
1
2
) ( ) (
2 2
V
V W
TIF
i
i i
1
2
) ( ) (
2 2
.
i
i i
V W T V
1
2
) ( ) (
2 2
.
i
i i
I W T I
1
1
2
) (
1
2
2
) (
i
i
V
i
i
V
DIN
increases linearly with frequency, while the C
message weights are free of this consideration
2.6 Flicker Factor (F)
If the voltage flicker (the low
frequency voltage fluctuations) are sinusoidal of
frequency
f
rad/s, the nominal instantaneous bus
voltage, Vm cos(
f
t) may be considered as being
modulated by the signal V
f
cos(
0
t) where V
f
is the
flicker amplitude. Thus flicker component of bus
voltage in
V
f
(t) = V
f
cos (
f
t). Vm cos (
0
t),
And the total bus voltage is
V (t) = Vm Cos (
0
t) + V
f
(t)
= (1+V
f
cos (
f
t)) Vm cos (
0
t).
The F = Vf

Vm.
If bus voltage flicker is not a sinusoidal
modulation effect ,the flicker factor cannot be used to
quantity flicker. In the frequency domain, the low
frequency components of the Fourier transform of bus
voltage gives a measure of the energy contained in the
flicker.
2.7 Transient Phenomena
The majority of power quality indices
discussed, which are applicable to periodic functions,
is based on the convenience of Fourier Series and the
concentration of the signal frequency at discrete
frequencies. These conveniences are lost in the case
of nonperiodic signals. In this case, however, there
are some characteristics that may be used to assess the
power quality impactthese characteristics include the
maximum signal value (e.g. the largest voltage over a
specified period of time),the greatest excursion of the
signal from the specified desired sinusoidal value, the
energy content of either the actual wave or the
difference between the wave and the desired wave, the
characteristics of the wave in a transformed space (e.g.
in the frequency domain under Fourier transform),or
some combination of these characteristics. (such as
time  band width product.)
2.7.1 Frequency Domain Indices
Band width (Bw) : is the width of the frequency
band which contains the given signal spectrum,V ()
to the frequency where /V()/drops to 70% of
maximum value /V()/ ie the 3d b point. For signals
which contain dc component, BW is specified as the
frequency at which /v( )/drops to the 3 db point.
Maximum frequency.
Area under the /V() characteristic.
2.7.2 Time Domain Indices:
Maximum value of V(t)
Manimum value of /v(t)  Vm cos (
o
t)/
Maximum rate of rise of a signal
2.7.3 Energy Intensity:
Noting that the (area under a wave)
times the crest in dimensionally equal to energy, the
index termed as energy intensity I.e. is defined as
energy
Ie = 
area * crest
It is to be noted that no signal index will
accurately will measure and predict the Power
Quality problem. In many applications, a
combination of the cited indices may be of value in
assessing the potential for problems. Further, the
indices discussed under transient phenomena have
not been standardized to the same degree as has been
done for indices of periodic phenomena.
Even though there are no standard
waveforms for the purpose of specifying power
quality problems, three waveforms have been
recommended by IEEE/ANSI guide for surge
voltages in low voltage AC Power circuits (ANSI
62.41). The three waveforms are the 1.2s by 50s
and 8s by 20 s rise/decay impulse waveforms and
the damped sinusoid with time constant 0.5s and
frequency of ringing of 100 kHz. In the damped
sinusoid, each successive peak amplitude is 60% of
the previous peak.
2.8 Standards, Recommended Practices, and
Guides
The main IEEE and ANSI (American
National Standard guides, recommended practices,
and standards are listed in Table 1. The guide is
intended as an example of typical design or
operating practice. Guides usually have typical
parameters and representative solutions to
commonly encountered problems. Recommended
practice recognizes that there are many solutions to
Power Quality problems, but the indicated method is
recommended over others. A recommended practice
is usually derived from a guide as an update and
upgrade. Standards are consensus codes adopted by
industry, government and users as to the proper
procedure to test, measure and manufacture
equipment and systems. There are numerous
additional Power Quality Standards and documents
from other than IEEE and ANS such as British
Standards (BS), European Norms (EN) etc. The
main function of these standards are to provide
uniform terminology and test procedures, to set
limits and standardized measures and values, and to
provide a common basis on which a wide range of
engineering is referenced.
Table 2 gives the selected Guide lines,
Recommended practice and standard limits of THD,
TIF, V.T and IT Product.
The IEEE standard 519 is a recommended
practice for power factor correction and harmonic
impact limitation at static power converters.
2
s . m . r
2
i
1 i
i i
2
i
1 i
i
2
i
1 i
i i
I
) I C (
) I (
) I C (
C
Table 3 gives the recommended limit on
harmonic current at the point where the static power
converter load is connected to the electric utility
company. This point is termed as the point of
common coupling (PCC).
Table 4 (from IEE standard 519) Cites
recommended limits for the harmonic distortion of
the voltage at PCC buses.
TABLE (1)
IEEE and ANSI Guides, Recommended Practices, and Standards on Electric Power Quality
Source Coverage
IEEE 18 Shunt power capacitors
IEEE/ANSI C37 Guide for surge withstand capability (SWC) tests; includes event recorders,
relay testing
ANSI/IEEE C50 (1982) Harmonics and noise from synchronous machines
ANSI/IEEE C57 (1986)
Recommended practice for establishing transformer capability when supplying
nonsinusoidal load currents
ANSI/IEEE C62 (1980)
(IEEE 587)
Guide on surge voltage in low voltage AC power circuits; includes guide for
lightning arrester applications
ANSI 70 The National Electrical Code
IEEE C114 (1973)
"The Green Book", Recommended practice for grounding of industrial and
commerci al power sytems
ANSI 368 Telephone influence factor
ANSI 377 Spurious radio frequency emissions from mobile communications equipment
IEEE 465 Test specifications for gas tube surge protective devices
IEEE 446
"The Orange Book", IEEE Recommended practi ce for emergency and standby
power systems for industrial and commercial applications
IEEE 472 Event recorders
IEEE 519 (1991)
Recommended practice for harmonic control and reactive compensation of
static power converters
IEEE P1100 Recommended practi ce on powering and grounding sensitive electronic
equipment in commercial and industrial power systems
TABLE (2)
Selected Guidelines, Recommended Practices, and Standard Limits of THD, TIF, V.T and I.T Product
Application Type of limit
(source)
Applicable equipment
ratings
Limit Electrical
quantity
Dedicated static
converters
Recommended
practice. (IEEE Std.
5191964)
2.4  69kV
above 69 kV
THD 8%
THD 1.5%
Bus voltage
Distribution
systems
Recommended
practice (IEEE Std.
5191964)
2.4  69kV
above  69kV
THD 5%
THD 1.5%
Bus voltage
Distribution
systems
Standard (ANSI
Std., 368)
Unlikely telephone
interference
Possible telephone
interference
Probable telephone
interference
IT 10000
10000IT25000
IT>25000
Line current
Subtransmission
systems
Typical values  60  69kV
19  44 kV
Balanced Residual
IT = 1400 60 <800
VT = 700 15<VT<30
Line current
Bus voltage
Subtransmission
systems
Typical maximum
values
60  69kV
60  69kV
Balanced Residual
KIT = 6
0.1<KIT<1KVT=50<V
T<400
Line current
Bus voltage
Synchronous
Machines
Standard (ANSI Std.
C50.121982)
519.999 MVA
20 MVA and above
Balanced Residual
TIF<100 TIF<75
TIF<70 TIF<50
Load
(source)
current
Synchronous
Generators
Standard (ANSI
Std., 368)
"Properly designed"
Generators
5<TIF<10 Generator
Current
Cylindrical
Rotor
Synchronous
Machines
Standard (ANSI Std.
C50.13  1977)
62.5299 kVA
300699
700999
10004999
500019999
2000099999
100000 & above
Balanced Residual
TIF<350
TIF<250 TIF< 40
TIF<150 TIF<100
TIF<150 TIF< 75
TIF<100 TIF< 50
TIF< 70 TIF < 30
Line
Current
Distribution
Transformers
Distribution
engineering
guideline
110 V
IT<66 for each kVA
rating of unit
Line
Current
TABLE (3)
IEEE Standard 519 Harmonic Current Distortion Limits at a Point of Common Coupling
Harmonic current distortion in %
Harmonic order
<11
1122
2335
>35
Total harmonic
distortion
<20 4.0 1.5 1.0 0.5 5.0
2049.9 7.0 2.5 1.5 0.8 8.0
5099.9 10.0 4.0 2.0 1.2 12.0
100999 12.0 5.0 2.5 1.5 15.0
>100 15.0 8.0 4.0 1.8 20.0
TABLE (4)
IEEE Standard 519 Recommended Harmonic Voltage Limits for Power Producers
Harmonic Voltage Distortion in % at PCC
2.368.9
kV
69138
kV
>138
kV
Maximum for individual harmonic 3.0 1.0
Total Harmonic Distortion 5.0 1.5
===============
POWER SYSTEM MODELLING AND HARMONIC ANALYSIS
Dr. R. Sreerama kumar
Asst.Professor,Dept. of Elect. Engg.
R.E.C., Calicut
1.0 Introduction.
Recent advances in the field of
power electronics have led to a growth in the number
and diversity of harmonic producing loads. This has
prompted the need for more accurate models for
power system components in order to accurately
predict harmonic distortion resulting from the
installation of waveform distorting loads. In
particular, the power system planners are concerned
with the determination of resonant frequencies. This
lecture note is concerned with modeling of various
system components and harmonic analysis. By
modeling the power system impedances as a function
of frequency, a study can be made to see the effect of
the harmonic contributions from nonlinear loads on
the voltage and current waveform.
2.0 Modeling
The difficulty of accurate harmonic
monitoring, particularly on high voltage
transmission networks has led to the development of
software models for the calculation of harmonic
impedances at any specific location required. Bus
admittance matrix and linear transformation
techniques are used to interconnect various power
plant components of a network represented by their
equivalent circuits. Since the harmonic currents
injected in to the system will in general be
unbalanced, for accurate harmonic frequency
analysis, threephase modeling the system
components is necessary. The admittance matrices
for each frequency have the same non zero element
positions but their values are determined by the
frequencydependent component models. In this
section, the modeling of various system components
for harmonic analysis is discussed.
2.1 Transformer
Fig.1. shows the modeling of
transformer with offnominal turnsratio. Fig.2
shows the modeling of phaseshifting transformer.
Three winding transformers are modelled using
equivalent star connection between the windings.
Fig.3 shows the modeling of threewinding
transformTransform parameters given in Fig.1 to
Fig. 3 corresponds to fundamental frequency. At
any other frequency, impedance is given by
Z
th = Rt
(a
o
+ a
1
h
b
+a
2
h
2
)+jx
t
h ;
where
R
t :
transformer's short circuit
resistance
X
t
: transformer short circuit
reactance
For large system transformers, typical values of a
and b parameters are
a
o =
0.750.80, a
1
= 0.100.13, a
2
= 0.10.13
and b= 0.91.4,
under the condition that a
0
+a
1
+a
2
= 1.0
2.2 Transmission Lines
Lines/cables are modelled using
equivalent 3phase  circuit. For each harmonic
order, the following data are required.
3 x 3 complex series impedance in ohms/km.
3 x 3 complex, shunt admittance matrix
(half of line charging susceptance ) in mho/km
2.3 Generator
Usually generator subtransient
reactance (Xd") is considered for harmonic study.
Impedance of the generator at frequencies other than
the fundamental frequency is modelled as
Z
gh
= R h + x d
h
2.4 Filter
In the harmonic study, any filter
consisting of resistors, inductors and capacitor is
represented as the equivalent shunt admittance from
the filter bus to ground, computed at the harmonic
frequency, bus voltage and base MVA
2.5 Converters
Converters and other similar
harmonic generating equipment's are represented as
current sources at each harmonic frequency knowing
the dc current (Idc), control angle () and over lap
angle (), the harmonic currents of converters are
computed as :
2.6 Load
Various load models at fundamental
frequency used for harmonic study are shown in fig
4.In model (1), loads are modelled as a parallel
combination of inductive reactance and resistance
whose values are:
R = V
2
/Pf X = jV
2
/KQf
Where V = Nominal Voltage
K = 0.1h + 0.9
h = harmonic order
P
f
Q
f
= Real and Reactive Power at
fundamental frequency
In model (2), reactance is assumed to be frequency
dependent while the parallel resistance is kept
constant. In model (3) ,load impedance calculated at
fundamental frequency remains constant for all
frequencies.In model (4), loads are modelled as a
series combination of resistance and reactance,
whose values are
R = (V
2
h)/pf and X = V
2
h/Qf
3.0 Harmonic Analysis
With the threephase models of
various components and the respective impedance
values established, a harmonic analysis study
should analyze the system under steady state
condition s for normal power flow and harmonic
current flow (referred to as harmonic power flow)
for all harmonics being modelled and for as many
system switching conditions as required.
A typical range of harmonic
frequencies may be from the fifth (300 Hz) to the
37
th
(2220 Hz) harmonic. The harmonic resonant
point at a particular location will probably differ
under each separate switching condition so all
normal modes of operation should be modelled as a
separate case in the analysis.
For complex systems that can
exhibit a large number of switching configurations,
it is sometime advantageous to initially reduce the
number of switching configurations to be modelled
by the use of what is referred to as resonance scans
or impedance scans. A resonance scan calculates the
impedance of the system as a function of frequency
as seen from the harmonic source and plots its
magnitude accordingly. By noting the maximum
(parallel resonance) and minimum (series resonance)
impedance values, switching conditions which are
not resonant near the harmonic frequencies
generated may be eliminated from further
consideration. Only those switching conditions
resonant near the generated harmonic frequencies
need to be evaluated.
The basic procedure for harmonic analysis is
follows:
Calculate the equivalent impedance of each
branch as a function of frequency
Successively Parallel the branch impedance's to
an equivalent Zh as seen by the current source.
For each injected harmonic current, compute the
resulting harmonic voltage generated as
V
h
= Z
h
* I
h
.
For each harmonic voltage, compute the
harmonic current in each branch as
I
h
(branch) = V
h
/Z
h
(branch)
For each harmonic current in each branch,
calculate the harmonic voltage across each
element in the branch.
A typical harmonic analysis software package gives
the following:
Various harmonic transfer and driving point
impedances in phases A,B & C, impedances at
each bus
Various injected harmonic current in phases
A,B & C at each bus
Various harmonic line flows.
Harmonic distortion factors at each bus.
Harmonic voltages at each bus.
Impedance Loci for various harmonic order at
each bus.
4.0 Application of Harmonic Studies
The principal applications of the
harmonic power flow study are in the calculat ion of
harmonic signal levels for the purpose of assessing
the adequacy of shunt capacitor voltage ratings and
reactor current ratings; communications influence
and interference; and possible faulty relay operation.
Let the bus voltage and load current Fourier series
be
v (t) = a
i
cos (i
o
t +
i
) & i(t) = b
i
cos
(i
o
t +
i
)
i = 1 i = 1
Applications of harmonic power
flow study algorithm to capacitor and reactor sizing
require the calculation of the peak voltage and the
total RMS current respectively. The former is
calculated by numerically evaluating Vmax;
Vmax = max (v(t))
0 t 2
The total RMS current is Irms,
n
Irms = ( bi
2
)
0.5
i=1
Where n is the highest harmonic considered.
Applications in communications influence
and interference assessment require the calculation
of line currents. Mutual coupling impedance's Z,
and Z2 in the positive and negative sequence (at the
fundamental frequency) describe the induced single
phase voltage in the communications circuit in terms
of the phase  a power circuit current,
(k) (k)
Vind = I
line
[Re (2
1
) + j k Im (2
1
)] k =
1,7,13,
(k) (k)
Vind = I
line
[Re 2
2
) + j k Im (2
2
)] k =
5,11,17,..
The subscript k denotes the harmonic
number. Zero sequence is usually omitted due to
very high mutual admittance and the low level of
zero sequence line currents due to delta connected
transformers. Even order harmonics are absent due
to the fact that most nonlinear loads produce load
currents, which are odd functions. The total induced
RMS Voltage is
K
(Vind RMS)
2
= [(I
line
)
2
[(Re(Z
1
(k)
1k
+ Z
2
(k)
2k
))
2
k = 1,5 ,7, +
(
Im(Z1(k)
1(k) +
)
2
Where
1k
= 1 When k = 1,7,13 & zero other wise
2k
= 1 When k = 5,11,17 and zero
otherwise.
Note that sequence protective relays
may malfunction in the presence of harmonic signals
since high levels of negative sequence (due to 5
t h
harmonic signals for example) may be sufficient to
operate the relay. This has been known to occur
near generating stations at which negative sequence
relays are located. The harmonic power flow study
calculates the separate line and bus sequence
components. If trip levels are known for the
protective relay, the total negative sequence RMS
values are readily calculated as the square root of the
sum of the squares of the individual negative
sequence components.
============
HARMONICS AND EMI FROM POWER ELECTRONIC EQUIPMENT
Dr.N.Prabhakaran
Professor,Dept. of Elect. Engg.
R.E.C.,Calicut
1. Introduction
All power electronic converters generate harmonic currents, which will be injected into the utility
grid, causing distortion of the utility waveform.. They also become a source for the generation of EMI, which
may affect the communication systems and certain sophisticated equipment. The problems due to current
harmonics in the input current of a power Electronic (P.E) load can be explained with the help of a utility
connected to a combined loads of PE type and general load, as shown in Fig. I
The source current i
s
consists of a
sinusoidal fundamental component i
1
and harmonic
current i
h
. The internal impedance L
s
of the source
will cause distortion in the voltage waveform at the
point of common coupling (PCC) to other loads. In
addition to voltage distortion ,the harmonic current
may also cause
(i) additional heating
(ii) over voltage due to resonant condition
(iii) errors in metering
(iv) malfunction of utility relays
(v) interference with communication and
control signals
(vi) notches in the power utility voltage
waveform and
(vii) low power factor
Large scale use of P.E systems and loads will result in significant negative impact on the utilities
as well as on the customers. We have two alternative approaches to minimize the impact of harmonics generated
by the PE load.
1 Using suitable filters to filter the harmonic currents and the EMI
2 Design the P.E equipment such that harmonic current and the EMI are prevented from being generated or
minimized.
2. Generation of current harmonics
In many power electronic equipment (SMPS, UPS, motor drives etc), ac to dc converters are
used as the interface with the supply. Uncontrolled dc output voltage can be obtained with diode rectifiers while
controlled dc output voltage can be obtained by using thyristor converters. Typical current and voltage
waveforms at the input side of a singlephase diode rectifier are shown in fig.2. The circuit is assumed ideal
with no source inductance present.
The r.m.s. value of the source current I
s
= I
d
r.m.s value of the fundamental component I
1
= 22/. I
d
= 0.9 I
d
r.m.s value of all harmonics I
h
= I
5
2
 I
1
2
= 0.435
Total harmonic distortion; THD = I
h
/I
1
= 48.43%
The harmonic components in the source current are shown in fig.2.
It is clear from fig 2 that the angle between the source voltage Vs and this fundamental component of input
current is zero. Therefore the displacement power factor (DPF) for a diode rectifier is unity
i.e. DPF = 1
The Input Power = (Power/VoltAmp) = (I
1
/I
s
)xDPF
In the case of fully controlled ac to dc thyristor converters, the DPF will be same as cosine of the
delay angle resulting in further deterioration of the power factor.
Thus, the use of rectifier introduces large amount of harmonies into the source current. If the
source is having a finite inductance as shown in fig.1, the voltage distortion at the point of common coupling can
be substantial. The higher the internal source. Inductance Ls, the greater would be the voltage distortion.
3. Current harmonics and power factor
The power factor PF at which an equipment operator is an indicati on of the effectiveness of the
equipment in drawing power from the utility. At a low power factor of operation ,for a given voltage and power
level, the current drawn by the equipment will be large thus requiring increased volt ampere ratings of the utility
equipment such as transformers, transmission line and generators. In the case of actodc rectifier, the power
factor is afflicted by the harmonics in the source current.
PF = Power = Vs I1 cos = I 1cos
Volt ampere Vs Is Is
= ( I 1) DPF = 0.9 for a diode rectifier
Is
4. Harmonic Standards and Recommended Practice
In order to maintain good power quality, various international agencies recommend limits of
harmonic current injection into the utility. According to IEEE 519 standards the limits on the magnitudes of
harmonic currents and harmonic voltage distortion at various harmonics frequencies are specified, as given in
Tables1 and 2
Table 1. Harmonic Current Limits for non   linear Loads
Isc/I
1
h<11 11 h 17 11< h< 23 23 h<35 THD
< 20 4 2 1.5 0.6 5
2050 7 3.5 2.5 1 8
50100 10 4.5 4 1.5 12
1001000 12 5.5 5 2 15
Isc is the maximum short circuit current at PCC , I
1
is the maximum fundamental frequency load
current.
Table 2 Harmonic Voltage Limits for power producers
2.3  69 kV 69  138 kV
Max. for individual
harmonies
3.0 1.5
Total harmonic distortion
(THD)
5.0 2.5
The Table 2 lists the quality of the voltage that the power producer is required to furnish a user. It
is based on the voltage level at which the user is supplied.
Because of the large harmonic content in the Power Electronic equipment, the THD and
individual harmonic content may exceed the limits (Table 1 and 2) . In addition to the effect on the power line
quality, the poor waveform of the input current also affects the PE equipment itself in the following ways.
i) The power available from the outlet is reduced to approximately two thirds.
ii) The D.C. side filter capacitor is severely stressed due to large peak pulse currents.
iii) The losses in the diode rectifiers becom e higher.
iv) The EMI filter components at the input to the rectifier bridges must be designed for higher peak
pulse currents.
5. Electromagnetic Interference
The switching or commutation of power semiconductor devices generates voltage and current
transients that are characterized by a whole spectrum of frequencies. A thyristor working at 50 Hz radiates a
large amount of EMI in the range of 200 Hz to 30 MHz. The thyristor is normally switched on when the anode
is at a higher potential with respect to the cathode. During turn on, the voltage across the device suddenly
becomes zero resulting in a sudden collapse of electric field. Similarly when the device turns off, a sudden
collapse of electromagnetic field takes place. Due to the sudden collapse of electromagnetic field during turn off
causes the generation of EMI,
The use of high frequency switching devices such as IGBTs and Power Mosfets for inverter
application causes the generation of EMI much above the standards set up by the International Electrotechnical
Commission (IEC1000). Filter circuits for suppressing EMI in high power Inverters are not economically viable.
The solution to this problem lies in the design of PE equipment that generate minimum EMI. This can be
achieved by switching the devices ON and OFF at zero voltage and zero current conditions.
A new class of converters known as resonant converters employing zero voltage and /or zero
current switching has come into existence in order to meet the EMI regulation . The principle of zero V/I
switching and various types of resonant converters are dealt with in the subsequent discussion.
6. Switchmode Inductive Current Switching
Let us consider one of the legs of a fullbridge of a dct oac inverter as shown in Fig. 3 . The
output current can be assumed to be constant at a magnitude I
o
due to the load inductances during the switching
interval. The load current can be in either direction. The switching characteristics of the switch is shown in
Fig.4(a). Initially the load current I
o
is assumed to be flowing through T
B
. When T
B
is switched off the voltage
across T
B
increases to Vd. A small overshoot may take place due to source inductances. The current through T
B
decays to zero. After the turn off of T
B
,the load current flows through D
A
.Since the device supports both
voltage and current during the interval of commutation, power loss takes place in the devices.
Let us now consider the turn on process of T
B
. Prior to the turn on of T
B
the load current flows
through D
A
.When T
B
is turned on i
T
increases to I
o
plus the peak  reverse recovery current of the diode.
Subsequently the diode D
A
recovers and switching power loss takes place in T
B
due to V
T
and I
T
during turn on .
The vi characteristics during turn on and turn off are shown in fig.4(b).
In addition to the switching losses during the turn on and turn off, the switch mode operation
results in large di/dt and dv/dt which produce EMI. Diodes with poor reverse recovery characteristics
significantly add to this phenomenon
7. ZeroVoltage and ZeroCurrent Switching
It is clear from the discussion in the previous section that the switch mode operation results in
switching stresses, switching power loss and the EMI . These problems can be minimized if the turning on and
turning of each of the converter switches take place when the voltage across the switch and/or the current
through the switch is zero. If both turn on and turn off switching of the inverter legs occur under a zerovoltage
and/or zerocurrent conducting condition, the switching loci are very much different as shown in Fig.5. Such
switching loci reduce the switching stresses, switching power losses and the EMI.
8 Resonant  Switch Converters
In resonant switch converters additional LC resonant
circuits are added to the conventional switch mode converter
topologies so that resonant zero current and/or zero  voltage
switching can take place. The transformer leakage inductances and
the stray capacitance of the switching devices can also be
efficiently utilized to provide resonant inductor and the capacitor
needed for the resonant switch circuit .The resonant switch
converters are broadly classified as:
i) Zero  current  switching (ZCS) topology
ii) Zero  voltage  switching (ZVS) topology
iii) Zerovoltage switching, clamped voltage (ZVSCV) topology.
In the case of ZCS topology (Fig.6a), the switch turns on and turns off at zero current. In ZVS (Fig.6b), both
switching operations take place at zero voltage.
8.1 ZCS resonant switch converters
A ZCS dcdc step down converter is shown in Fig.6(a) where Cr and Lr form the resonant circuit.
The current produced by the LC resonant circuit flows through the switch,thus causing it to turn on and turn off
at current zero . The filter inductor Lf is sufficiently la rge so that the current i
o
can be assumed to be constant at
a magnitude I
o
. The steady state circuit waveforms and equivalent circuits at various modes are shown in Fig.7.
Let us assume that the switch is open, Io flows through the diode D and C
r
charges to Vd.At t=t
o
the switch is turned on. One cycle of operation consists of 4 modes as shown in Fig.7 (a).
Mode 1 (t
o
t t
1
)
In this mode , the current through the switch is less than I
o
,with the result that diode D
continues to conduct. The capacitor voltage will remain at +Vd and current through L
r
(and the switch) increases
linearly. This mode ends at t= t1 when the current IT is equal to Io .The equivalent circuit for this mode is shown
in Fig.7(b).
Mode 2 (t
1
t t
4
)
The diode stops conducting at t= t
1
when I
T
is equal to I
o
.Now LrCr becomes a parallel
resonant circuit.(Fig.7(c)).The Resonant current becomes maximum at t= t
2
with an amplitude of I
o
+(Vd/Z
o
) and
v
c
reaches zero. At t= t
3
the current I
T
is equal to I
o
and the capacitor voltage becomes negative maximum. The
current through the switch becomes zero at t= t
4
and it gets turned off at zero current.
Mode 3 (t
4
t t
5
)
At the beginning of this mode the capacitor voltage is negative and hence the diode is reverse
biased. All the load current (constant at I
o
) flows through C (Fig.7(d)) and the capacitor charges linearly to +Vd
at t= t
5
.
Mode 4 (t
5
t t
6
)
When v
c
becomes +Vd,the diode becomes forward biased and starts conducting(Fig.7(e)).This
will clamp the capacitor voltage and this mode will continue until the switch is again turned on at t= t
6
.
The main features of
ZCS Resonant Converters are :
1. The maximum voltage across
the switch is limited to Vd.
2. The peak current through the
switch is greater than the load
current.
3. The peak resonant current
(Vd/Z
o
) must be greater than the
load current.
4. When I
o
(Vd/Z
o
) ,natural
zero current turning off will not
take place.
5. By controlling the switch off
interval ,(t
6
t
5
) the power supplied to the output stage can be controlled.
9. ZVS Resonantswitch
Converter
The resonant circuit consists of
Lr,Cr and a diode as shown in Fig.8.The
resonant capacitor Cr which comes across the
switch produces a zero voltage. The switch
can be turned on or off at zero voltage
condition.Fig.9(a) shows the waveforms of I
L
and v
C
.The equivalent circuits at various modes are shown in Fig.9(b).The load current is assumed to be
constant at I
o
during a high frequency resonant cycle.Initially the switch is assumed to be conducting the load
current and hence the voltage across Cr is zero and the current through Lr is equal to load current. The cycle
starts at t
o
when the switch is turned off. One cycle can be divided into 4 modes as shown in Fig.9(a).
Mode 1 (t
o
t t
1
)
When the swit ch is turned off at
t
o
,the capacitor starts charging linearly. This
mode ends at t= t
1
when v
C
=Vd
.
The equivalent
circuit for this mode is shown in Fig.7(b).
Mode 2 (t
1
t t
4
)
The freewheeling diode D
becomes forward biased when v
C
=Vd
.
Cr and Lr
resonate. At t= t
2
current I
L
becomes zero and
v
C
becomes maximum with a magnitude of
Vd+I
o
Z
o
.At t= t
3
, v
C
=Vd
and I
T
= I
o
.At t= t
4
v
C
=0 and current can not reverse its polarity
because of the diode Dr.The diode Dr starts
conducting from this instant.
Mode 3 (t
4
t t
6
)
Beyond t
4
,the capacitor voltage
is clamped to zero by the diode Dr,which conducts a negative current IL.The gate drive to the switch is applied
once Dr starts conducting. The current IL now increases linearly .The current becomes zero at t 5 and increases
further to Io at t = t 6. The switch begins to conduct at t= t 5.
Mode 4 (t 6 t t7)
The s carries the load current I
o
that flows through the resonant inductor Lr while the ca voltage
remains at zero value . At t= t
7
, the switch is turned off at zero voltage condition.
The main features of ZCV Resonant Converters are :
1. The voltage across the switch is greater than Vd.It is Vd+I
o
Z
o
.The voltage ZoI
o
must be greater
than Vd for zero voltage switching.
2. The current through the switch does not go beyond I
o
.
3. By controlling the ON interval (t 7  t6), the power output can be controlled.
==========
P Q PROBLEMS CREATED BY DRIVES AND P Q IMPACT ON DRIVES
Dr. Madhu Mangal
Consultant in Power Electronics
Trivandrum
1 Introduction
The major source of problems with
power quality at the customer site is the arc welding
devices. The next group consists of uninterruptible
power supply (UPS) systems, variable speed DC and
AC drives, etc. These equipment draw large amount of
harmonic currents from the supply causing distortion
of the voltage and overheating of the transmission
system. In addition, they draw currents at low power
factor. Various types of rectifiers used in these
equipment mostly create the problems. In addition, the
quality of utility power affects the performance of
these power electronics equipment.
2 Rectifiers
Rectifiers convert the AC supply into DC
voltage source for either directly connecting to loads
such as heater coils, furnaces, DC motors, etc., or for
further conversion as in the case of UPS systems,
variable frequency AC drives (VFD), switched mode
power supplies (SMPSs), induction heating inverters,
etc. Basically there are two types of rectifiers called
uncontrolled rectifiers and controlled rectifiers. Most
power electronics equipment including Drives use
rectifiers at the input.
2.1 Uncontrolled Rectifiers
Uncontrolled rectifiers are used as
front end converters in SMPSs, VFDs, DC power
supplies, and some UPSs.The circuit diagram of
single phase uncontrolled rectifier is shown in fig.
2.1. Generally uncontrolled rectifiers are connected
directly to a DC smoothing capacitor.
Fig. 2.2 shows its input voltage and current
waveforms.It can be seen that the input current
waveform contains large amount of 3
rd
harmonic
component. The actual magnitude of this component
of current would depend on the output capacitance
value, the load current and the input line
inductance.One major problem encountered while
using single phase uncontrolled rectifiers distributed
in all the three phases is the large amount of neutral
current drawn in spite of the loads being
balanced.This happens because the pulse width of
current wave is narrow and the instantaneous values of
line currents do not add up to zero.
Fig 2.3 shows the circuit diagram of a three
phase uncontrolled rectifier. It consists of six diodes
connected in br idge configuration. Fig 2.4 shows the
input voltage and current waveforms. It can be seen
that in this case the predominant harmonic component
in the current waveform is the 5
th.
In this case, the
currents are balanced and there is no neutral current
problem.
In practical circuits of both above categories,
the predominant harmonic component could be as
high as 75% of the fundamental component. The
fundamental component of the input current would be
almost in phase with the respective phase voltage.
Thus the apparent input power factor is close to unity.
2.2 Controlled Rectifier
Controlled rectifiers are used in variable
speed DC drives DC power plants, induction heating
and welding furnace control, etc.
Fig. 2.5 shows the circuit diagram of the
singlephase fully controlled rectifier. The diodes of
the uncontrolled rectifier have been replaced with
thyristors. The controlled rectifier is normally
connected to a smoothing inductor on the DC side.
Thus the output current of the controlled rectifier
could be considered as constant.
Fig 2.6 shows the input voltage and current
waveforms. The predominant harmonic component in
the current waveform is the 3
rd
and the displacement
angle is .
Fig 2. 7 shows the circuit diagram of a three phase
fully controlled rectifier. Fig 2.8 shows the input
voltage and current waveforms. is the triggering
angle . The most predominant harmonic component
in the current waveform is the 5
th
and the
displacement an gle is
In the case of controlled rectifiers, it may be
noted that the fundamental component of current lags
the respective phase voltage by the triggering angle,
and the displacement factor would be cos. .
3 Effects on Power Quality
Rectifiers affect the quality of power
supply by reducing the power factor, by introducing
voltage distortions and by RF and EM interference.
3.1 Power Factor
When non sinusoidal current is drawn
from mains supply, the term power factor (PF) is not
just the cosine of the angle. The definition of power
factor is Power factor = Active Power / {RMS Voltage
x RMS Current} Since the voltage does not contain
harmonic components, the active power would be
equal to the product of RMS value of voltage (V),
RMS value of the fundamental component of current
(I
1
) and the cosine of the angle (cos. ) between
them. If I is the RMS value of the current including
all harmonic components.
PF = V I
1
cos. / (VI)
i.e., PF = (I
1
/ I) cos
In this case cos. is called the displacement
factor and (I1 / I) is called the distortion factor which is
the ratio of the RMS value of the fundamental
component of current and the RMS value of the total
current waveform. In an ideal case both these factors
should be unity.
3.2 Voltage Distortions
While using rectifier circuits, voltage
distortions take place due to two factors namely,
commutation notches and voltage clamping,
Commutation notches appear on the AC lines due to
momentary shorting of the lines through the power
devices while current transfers from the device on one
line to the device on another. This is more in case of
controlled rectifiers. The resulting notches appearing
on the supply would affect other equipment connected
to the same lines. Fig. 3.1 describes this phenomenon.
Voltage distortion due to voltage clamping occurs n
uncontrolled rectifiers. Fig. 3.2 shows this
phenomenon. When the diodes conduct, the input line
voltage gets clamped to the DC voltage across the
capacitor. This also can affect other equipment 
connected to the same supply.
These can be overcome if proper line snubber is used
for each rectifier that can absorb the difference in
voltages as shown in fig 3.3 . This circuit uses an
inductor (L), a resistor and a capacitor . This also
limits the di/dt and dv/dt on the devices.
3.3 RFI and EMI
Radio frequency interference and
electromagnetic interference are problems created by
rectifiers and other power electronic equipment due to
fast switching of voltage and current.
To reduce the effect of RFI, a capacitor filter
connected to the phases and to the earth terminal could
be used. To a large extent this prevents RFI going
into the supply lines. To reduce the effect of EMI, the
di/dt in the circuit should be kept within limits.
Presently soft switching circuits like resonant
converters are available which are used at low power
levels. For high power levels the way of preventing
these problems is to keep dv/dt and di/dt sufficiently
low
4 Power Quality Impact On Drives
The major power quality problems encountered
on the utility are:
1 Voltage surges  high voltage spikes of very low
duration appearing on the supply
2 Voltage dips  dips in voltage for a few cycles due
to faults appearing on the load side
3 High voltage sustained high voltage beyond rated
for long periods
4 Low voltage  sustained low voltage for long
periods
5 Brown outs loss of supply voltage for short
periods ( a few cycles)
6 Black outs  loss of supply voltage for long periods
The problems would affect any electronics
equipment connected to the supply. Variable speed
drives are no exception.
4.1 DC Drives
DC Drives use controlled rectifiers to
obtain variable DC voltage. The controlled rectifier
senses the zero crossing of line voltages to control the
firing angle of the thyristors. When the input voltage
waveform has multiple zero crossing due to voltage
spikes or sudden dips, this sensing would be erratic
and t he equipment misbehaves. Normally, all DC
Drives equipment are designed to trip on under
voltage over voltage and abnormal frequency
conditions.
In a regenerative drive which uses four
quadrant converter, if the equipment is regenerating
and an under voltage condition occurs, there would be
commutation failure resulting in fuse failure and shut
down of the equipment. Sane is the case with brown
out sand black outs.
4.2 AC Variable Frequency Drives
AC Drives, now a days, use uncontrolled
rectifier at the input followed by a Pulse Width
Modulated inverter. In modern AC drives, under
supply failure, the inertial energy in the mechanical
system is used to bring the speed down to zero, by
keeping the DC voltage clamped slightly more than
normal. Under brown outs, the drive equipment
would not trip but continue to work, probably bringing
the speed of the motor slightly down. Under sustained
over Voltage and under voltage conditions, the
equipment would be shut down . Voltage surges can
damage the power diodes connected at the input.
Snubber circuits help in preventing device failure
under input surge conditions to a certain extent.
As explained in section 3.2 voltage clamping
could take place if proper snubber circuits are not
used. The DC voltage of low rated equipment would
be forced down to those of higher rated equipment due
to this.
5 Conclusion
Variable Speed Drives and UPS systems
which do not pollute the input supply are being
introduced in the market. These use various
configurations of unity power factor sinusoidal current
rectifiers. IEEE has brought out statutory
requirements on the amount of harmonic current
components that can be drawn form the mains.
Already directive have been issued in many countries.
In India too actions are on to introduce them.
==============
POWER QUALITY AND COMPUTER LOADS
Dr.S.Thiruvengadam
Prof.&Head, Dept.of Elect.Engg.
Sri Venkateswara College of Engg.,Sri perumbudur
1.0 Introduction:
Computer loads and systems are found in
all of societys industrial, commercial and residential
sectors. These loads interact with the utility in two
ways. They distort the line current waveforms and
even significantly distort the supply voltage
waveforms. But in certain cases, surges in the power
line may damage the computer systems. Hence both
above aspects are discussed in this paper.
2.0 Computer systems and their PQ
characteristics:
The following basic questions are to be addressed in
this context.
1. If the phase current waveform of a
single computer workstation is known, then is
the phase current serving a number of
ident ical computer workstations a multiple of
the single workstation characteristics?
2. What is the total harmonic distortion
(THD) of a single computer workstations
phase current, and does it vary significantly
with loading patterns?
3. If the phase current waveform is
significantly distorted, will it significantly
distort the voltage waveform?
4. What are the dominant harmonics of a
computers phase current?
5. What is the harmonic distortion of
neutral to ground voltage at an individual
computer workstation and at electrical panel
serving a number of workstations.
To answer the above questions, detailed
study has to be conducted using power line monitors.
A set of samples is captured to determine the
harmonic characteristics of phase current, line
voltages, line neut ral voltages and neutral to ground
voltages of the various computer loads and systems. In
these systems sufficient monitoring time (e .g 27
days) was allowed to capture the essential harmonic
characteristics of the computer loads and systems and
correlate them with any computer system operational
problems.
3.0Single and Multiple computer workstation(s)
PQ characteristics:
A schematic diagram of a computer
workstation is shown in fig 1.
Fig. 1. Computer workstation schematic diagram.
3.1 Individual workstation Phase currents
(Normal range 0.92 0.95 rms.)
The typical phase current wave
shapes of each individual computer workstation are
illustrated in fig 1. The wave shapes of the phase
currents of a switched mode power supply of the
individual computer workstations were approximately
the same. A figure showing the percent THD and the
contributions of the dominant harmonic components
(i. e 3
rd
, 5
t h
, 7
th
and 9
t h
) of the phase current
characteristics a single computer workstation is
shown in fig 2.
Fig. 2. Phase current % THD and harmonic
contribution of an individual computer workstation
Each sample was taken at different times of
the day, to characterize the loading cycle of single
computer workstation.
The harmonic content of the
waveforms was dominated by odd harmonics. The
contributions of all the even harmonic components of
the phase current were negligible. The dominant phase
current harmonic was the third, followed by the fifth,
seventh and ninth harmonic. The total THD averaged
around 110% for all the samples obtained.
4.0 With the above data on a single computer
workstation on hand, the next step would be
to verify whether:
1. Phase current at the panel would have the same
wave shape.
2. The harmonic content of the phase
current measured at the electrical panel
would be identical.
3. The total phase current harmonic
distorted would be same as a single computer
work station.
4.1 Phase current at computer workstation
electrical panel:
Referring to fig 1, the phase current waveform
measured at the panel was not a multiple of a
single computer workstation. The unique
waveform of the phase current at the panel
remained essentially the same throughout the
monitoring period.
The harmonic content of the phase current
measured at the electrical panel is shown in figs
3 and 4.
Fig. 3. Phase current % THD and third harmonic at
Computer workstation electrical panel.
Fig. 4. Phase current dominant harmonic contributions
at the computer workstation electrical panel.
The total harmonic content of the panel phase
current (i.e. averaging around 700%) significantly
exceeded the THD of a single computer workstation
(i.e. 110%). The dominant phase current harmonics at
the panel were the third, followed by fifth, ninth and
fifteenth and not the third fifth, seventh and ninth
exhibited by a single computer workstation.
4.2 Due to neutral and line to line voltages at
computer workstations electrical panel
(120/208v rms.)
The THD of phase to neutral voltage
measured at a single computer workstation and at the
electrical panel is shown in the fig 5.
Fig. 5. Phase neutral voltage percent THD measured
at a single computer workstation and at the
electrical panel.
The THD remained constant (i.e. 3.7%) at
the terminals of individual computer workstations,
independent of change in workstation loading
patterns. The THD of line to line voltage measured at
the
Fig. 6. Line to line voltage percent THD at the
computer workstations electrical panel
electrical panel is shown in fig 6 and remained
constant at 1.4% significantly less than the THD of
phase to neutral voltages.
4.3 Neutral to ground voltage at a single
computer workstation and at the electrical
panel.
The THD of the neutral to ground
voltages measured at a single computer
Workstation and at the main electrical panel are
shown in fig 7.
Fig. 7. Neutral ground voltage % THD at a single
computer workstation and at the electrical panel.
The waveform of neutral to ground voltage was
constantly distorted and often did not exhibit any
cyclic behavior. The THD of neutral ground voltage at
a single computer station averaged 400%, while at
the electrical panel it averaged 225%.
5.0 Case studies:
Various dedicated circuits that supply the
computers at different facilities were monitored at
their electrical panels to evaluate the PQ
characteristics of dedicated circuits.
5.1 Heating plant computer supply:
Circuit phase current
The percent THD of phase curr ent and its magnitude
is shown in fig 8.
Fig. 8. Phase current percent THD heating plant
computer panel.
The THD of the phase circuit appears to
increase during light load conditions and decrease
during heavy load conditions. The THD for this
computer panel is significantly lower than the phase
current of the computer workstation (i.e.
approximately 40% compared to 700%) The
significant difference in THD was attributed to the
difference in the computer systems technology and
the diversity in the number of different types of
computer systems. The dominant harmonic
component of the phase current was the 3
rd
harmonic
and did not change significantly with load cycle.
5.2 Line to neutral and line to line voltages at
computer workstation electrical panel.
The percent THD of the phase neutral and
line line voltage is shown in fig 9.
Note that the THD for the phase neutral and
line to line voltages is approximately constant over
the entire loading cycle. The dominant harmonic
components of phase neutral and line voltage were
the 3
r d
and seventh harmonics.
Fig. 9. Phase neutral and line voltage percent THD
heating plant computer panel.
5.3 Neutral to ground voltages
The THD of neutral ground
voltage is shown in fig 10.
Fig. 10. N eutral ground voltage percent THD
heating plant computer panel.
Note that for this particular
computer panel, the THD of neutral ground voltage
remained fairly constant (i.e. 75% to 78.5%) almost
independent of the magnitude of phase current . The
dominant harmonic component of neutral ground
voltage was the 3
rd
harmonic. Note that for a dedicated
computer circuit, the THD of the phase to neutral and
line voltages are approximately equal, while the THD
of the phase neutral voltage at the panel was
significantly higher than the THD of line voltage (i.e.
3.7% as against 1.1%) indicating same distortion in
the phase voltage caused by the distorted phase
current.
5.4 Electron microscope PQ characteristics
The electron microscope is a fairly
sophisticated computerized system. The users of
electron microscopes experienced operational
problems with these systems. Hence it is necessary to
monitor and record their PQ characteristics.
5.4.1 Electron microscope phase currents
The phase currents are shown in
fig.11.
Fig. 11. Phase current percent THD department of
Anatomy electron Microscope.
Fig. 12. Phase neutral and line voltage percent THD
 department of Anatomy Electron microscope.
The phase current remained fairly constant during its
operational cycle. The percent THD of the phase
current is shown in figure. The THD averaged 77.5t
1% during its operational cycle. The THD of phase
current appears to increase during light load
conditions and decrease during heavy load. The THD
for an electron microscope is significantly lower than
the phase current of an individual computer
workstation (approximately 78% compared to 110%).
The dominant harmonic components of phase current
were the 3
rd
, 5
th
and seventh similar to an individual
computer workstation, except for the fact that the 3
rd
harmonic component is reduced by approximately
20%.
5.4.2 Line to Neutral and line line voltages at
the electron microscope
The percent THD of the phase neutral and
line to line voltage is shown in fig 12.
The phase to neutral voltage THD remained
constant at approximately 4.0% and the line line
voltage THD also remained constant averaging 1.2%
significantly less than the phase neutral voltage
THD. The dominant harmonic component of the phase
voltage was the third harmonic and it was the fifth for
the line voltage.
5.4.3 Neutral to ground voltage (0.58 0.60v)
The THD of the neutral to ground
voltage is shown in fig 13.
Even though t he phase current
remained constant, the THD of neutral to ground
voltage for this system varied significantly from a low
of 400% to a high of 1750% with the third harmonic
component of the neutral to ground voltage being
dominant.
Fig. 13. Neutral ground voltage percent THD
department of Anatomy electron microscope.
6.0 Summary of conclusions :
The PQ characteristics of various computer loads are summarized in Tables 1and 2.
TABLE I
Average Total Harmonic Distortion of the Monitored Electrical Vehicles
computer
system
% thd
phase
current
% thd
phase
neutral
voltage
% thd
lineline
voltage
% THD
NEUTRAL
GROUND
VOLTAGE
Individual Computer
workstation
1110.0 3.7 1.4 400.0
Multiple Computer
Workstations
(at panel)
700.0 3.7 1.4 225.0
Dedicated Computer
Circuit Heating Plant
40 (light load)
25 (heavy load)
1.1 1.1 77.0
Electron Microscope
Dept. of Anatomy
77.5 4.1 1.2 1772
(high)
Electron Microscope
Dept. of Biochemistry
79.5 2.6 0.6 7331
(high)
TABLE II
Dominant Harmonic Components and their Percentage contributions of the monitored Electrical Variables
COMPUTER
S YSTEM
DOMINANT
HARMONIC
And
Percent
Contribution( )
PHASE
CURRENT
DOMINANT
HARMONIC
And
Percent
Contribution( )
PHASE
NEUTRAL
VOLTAGE
DOMINANT
HARMONIC
And
Percent
Contribution( )
LINE
LINE
VOLTAGE
DOMINANT
HARMONIC
And
Percent
Contribution( )
NEUTRAL
GROUND
VOLTAGE
Individual
Computer
workstation
3
rd
(84%)
5
th
(55%)
7
th
(28%)
3
rd
(2.9%)
5
th
(1.9%)
9
th
(0.9%)
5
th
(1.3%)
3
rd
(0.4%)
13
th
(0.3%)
3
rd
(395%)
9
th
(132%)
5
th
(60%)
Multiple
Computer
Workstation
(at panel)
3
rd
(577%)
5
th
(111%)
9
th
(85%)
3
rd
(3.0%)
5
th
(1.9%)
9
th
(0.9%)
5
th
(1.3%)
3
rd
(0.4%)
13
th
(0.3%)
3
rd
(222%)
9
th
(71%)
7
th
(32%)
Dedicated
Computer
Circuit
Heating
Plant
3
rd
(36%)
5
th
(8.8%)
11
th
(4.7%)
3
rd
(0.9%)
7
th
(0. 7%)
13
th
(0.3%)
7
th
(0.7%)
3
rd
(0.5%)
5
th
(0.3%)
3
rd
(67%)
7
th
(20%)
11
th
(!5%)
Electron
Microscope
Dept. of
Anatomy
3
rd
(58%)
5
th
(45%)
7
th
(24%)
3
rd
(3.9%)
5
th
(0.7%)
9
th
(0.7%)
5
th
(0.9%)
11
th
(0.4%)
13
th
(0.3%)
3
rd
(1737%)
9
th
(309%)
15
th
(93%)
Electron
microscope
Dept. of
Biochemistry
3
rd
(62%)
5
th
(42%)
7
th
(22%)
3
rd
(2.4%)
9
th
(0.9%)
11
th
(0.9%)
7
th
(0.3%)
13
th
(0.3%)
5
th
(0.2%)
3
rd
(6910%)
9
th
(360%)
5
th
(130%)
Average THD of the phase current, phase neutral,
line to line, neutral ground voltages are shown in
Table 1.
1. The THD of an individual computer workstation
phase current averaged 110%, however the phase
current measured at the electrical panel serving 5
workstations was 700%.
2. THD of a phase current at a dedicated heating
plant computer circuit varied with load, but was
significantly less than the phase current
monitored at the computer workstation electrical
panel, even though the individual computers in
the dedicated circuit have PQ characteristics
similar to that of a single workstation.
3. The THD of 2 different types of electronics
microscopes averaged 80, despite the different
computer technologies involved in their design.
A scrutiny of the average picture yields the
following conclusions.
a. Phase currents were significantly distorted.
b. Phase neutral voltages THD ranged from 2.6
to 4.1 %.
c. THD of line voltages remained fairly constant
ranging from 0.6% to 1.4% and appeared to be
almost independent of wave shape of the phase
current at the loading levels studied.
d. The THD of neutral to ground voltage was
constantly high ranging from a 100 to
77% for a dedicated computer circuits to a high
of 733% for the microscopes
e. For the computer systems studied the dominant
harmonic component of phase current was the 3
rd
harmonic followed by 5
th
. The third harmonic,
component was the dominant harmonic in the
phase to neutral voltages and 5
th
harmonic
component dominant in line to line voltage. The
3
rd
and 9
th
harmonic components dominated the
neutral to ground voltage.
The following are certain specific question
that arises in the above context.
1.If the PQ characteristics (i.e. waveform) of an
individual computer are defined, what model can be
used to predict PQ characteristics of a multiple
number of computers?
2.It can be abinitio said that operations of multiple
computers are not independent. This is to be verified
by detailed long term monitoring with various
configurations.
3.Can the neutral ground voltage PQ characteristics
at an individual computer system be used as a good
indicator of
a. Poor wiring practices
b. Computer disruptions (susceptibility characteristics)
c. Peripheral equipment disruptions?
7.0 Computer systems and Power Transients
Understanding the general causes of, and remedies for,
power transients can help users of small, especially
standalone, protect their systems with simple
techniques. More complex systems may need the
attention of a specialist system designers should also
be aware of the way users hook up their systems, the
potential damage that could be caused by power
transients and side effects of incorrectly applied
measures.
7.1 Origin of transients
While the term transient is often
understood as a transient over voltage, it is also more
broadly interpreted as the occurrence of any
disturbance, either on the power line or the computer
systems data line. There are three major sources of
electrical disturbance:
1. Lighting strike The electromagnetic field
radiated by the lighting current couples with the
conductors of power lines or data lines, inducing
transient voltages along these conductors. Also as the
lighting current spreads into the ground, it produces
difference in potential at points that are normally at
ground potential, Conductors spanning some distance
between their ends in the area where the lighting
current is spreading will be exposed to these
differences of potential or to a transient over voltage.
2. Switching transients
A less obvious but more frequent source
of transients is switching sequences in the power
systems. Switching may be done to turn a load on or
off or it could occasionally involve clearing an
overload or short circuit. These switching transients
cover a wide range of frequencies and amplitude.
Some have a brief duration (nanoseconds) and
involve little energy (milliseconds). While they
present little risk of damage, their high frequency
spectrum makes them likely sources of interference.
Others have a longer duration (micro or even
milliseconds) and involve greater energy (up to
hundreds of joules) with lower frequencies. They
have the opposite trait of low risk of interference
(due to relatively low frequencies) and higher
damage or risk (due to longer duration and high
energy).
3. Occurrence of Under voltage
Another source of disturbance is the
occurrence of an under voltage (due to start up of
heavy loads or by distant faults). In this case, the
reduced energy associated with an under voltage
cannot be supplemented by a simple device.
Different methods are needed for a solution of that
problem.
7.2 Vulnerable stand alones :
Found in offices, laboratories and homes,
standalone systems can be disrupted or damaged by
two possible causes. First, transients with low
amplitudes (less than 1000v) are buffered by the
computers power supply but might still couple into
circuits and cause glitches. Transient of high
amplitudes (over 1000V) may at worst damage the
powerinput components and are likely to cause
glitches at best. Second, power interruptions (sags or
outages) can cause a momentary shut down.
Transient damage protection for
these systems is simple to achieve. The approach
depends on inserting a separate surge suppressor
(spike protector transient voltage suppressor) on the
power cord. The rating of this device should reflect 3
basic requirements
1. Nominal line voltage
2. Surge current capability
3. Clamping voltage during surge.
The second type of disturbance sag or outage
cannot be corrected by a surge suppressor. The
computer operation is interrupted when sag or outage
exceeds the capability of the interval dc supply to
power the logic and the many circuits cannot be
corrected by a surge suppressor. The computer
operations interrupted when the sag or outage exceeds
the capability of internal dc supply to power the logic
and memory circuits. Most computers have a built in
capability to maintain operation for a short time when
this power is lost, but that reserve is drained out if the
interruption is long enough. If the computer is using a
disk drive when the sag occurs, a shut down is likely;
in an office using several identical machines, some
ride through a disturbance while others, especially
those reading from a disk, since down and have to be
restarted. Protection against such sags and outages
requires an UPS.
7.3 Certain specific cases:
1. A power supply outage a sag on distributed
systems has the same effect as for standalone
systems. But in the case of sophisticated systems that
include automatic restart, or rebooting, it was reported
that damage was caused because of repeated sags
during automatic rebooting sequence, typically
occurring due to multiple lighting strokes or during
fault clearing with automatic reclosing by the utility
system.
2. In the case of surges, as soon as simple stand
alone system is augmented by peripherals, additional
remote terminals, networking, and sensors that require
a data link, the threat that the system will be affected
increases. Even what may appear as a stand alone
system, such as a simple desktop pair of a PC linked
with a printer, might be at risk if the 2 units are
plugged into different power receptacles fed by
separate branch circuits from the breakers.
In addition to the risk of interference
or damage from surges on power lines, the data line
input and output ports are also vulnerable. Several
mechanisms can inject interfering or damaging
transients into the data lines of distributed transients.
First, a problem could result because lines act as
antennas that can collect energy from e.m. fields and
feed it, as noise or surges, to the data port's input or
output , the driver or the receiver of the computer or
its peripherals.
3. Another mechanism that could cause trouble
is the difference in the potential of objects at nominal
ground potential occurring during surge events.
Most data links operate with the signal reference
conductor (Shield or one wire in a group) connected to
the chassis of the equipment. The chassis is in turn
connected to the grounding conductor of power cord
supplying the equipment. Thus if lighting or power
systems faults inject a high current in the sites ground
conductors, the potential of the ground points at the
two ends of data link differs. This potential difference
causes a current to flow into the data link, possibly
exceeding the capability of input or output
components. In such cases, the user can use optical
fiberlink. However if the conversion electronics at the
ends of the fiber link are disturbed by electrical noise,
this noise will be transmitted. If a conductive data link
is to remain, the remedy is to insert protective devices
that are complementary for the power and data lines.
These devices typically operate by limiting the over
voltage or attenuating the higher frequencies by
filtering, which works effectively on the power line
but not as the data link. Here, filtering is not possible
because it would affect the signals, limiting the over
voltages will eliminate that damage risk but might still
let through a spurious signal.
8.0 Summary:
Tables 3and 4 summarize details of
troublesome mechanisms, typical disturbances and
effective protective equipment in the area of power
quality considerations of computer loads.
References:
1. Understanding lighting
By Martin A. Uman
Academic Press, N.Y 1971.
2. Protection of Electronics circuits from
Overvoltages
Ronald B. Standlev
John Wiley & sons.
3. IEEE Guide for Surge voltages in low
voltage AC Power circuits
ANSI C62 41 1980.
4. Power Quality Site Surveys : Facts,
Fiction and fallacies
IEEE Trans I&A
November 1988
HARMONIC DISTORTION OF FLUORESCENT LAMPS
Ashok S.
Lecturer,Elect. Engg. Dept.
R.E.C., Calicut.
1. Introduction
At present India is facing an energy shortage
of 12% with a peak deficiency of 20%. The ever
increasing demand and the delays in capacity
additions widened the gap between the energy
demand and supply. As a solution to the energy
crisis, govt. is implementing energy conservation
programmes in all sectors.
Lighting is an important sector where about
32% of the total electrical energy is being consumed.
Not only that unlike any other loads, lighting load can
not be shifted to any other oftpeak period. One of the
best method of energy saving in lighting sector is the
implementation of energy efficient lamps. The
fluorescent tube lights (FTL) and compact fluorescent
lamps (CFL) are well known for their energy efficacy
as compared to incandescent bulbs (GLS). The overall
lighting efficacy for CFL is about 34 times that of GLS
and about 1.75  2 times that of the FTL.
It is clear that the use of FTL and CFL will cut down
the energy demand for lighting approximately by one
fifth. But the wide spread use of these lamps will
cause harmonic pollution and more reactive power
demand (being low power factor), if not properly
designed and selected , in addition to the normal
destructive effects of discharge lamps like mercuric
poisoning [ 5 ].
Hence a defiled study of power quality impact due to
the operation of these lamps will become necessary. In
this paper we have conducted experiments to find out
the effect of harmonics produced by FTL and CFL of
some deferent makes available in the Indian market.
2. Efficient Lamps for Domestic Sector
In India there are a number of agencies manufacturing
or distributing the fluorescent lamps with different
specifications. 40W/ 20W standard tubes,36W/18 W
slim tubes, 5/7/9/11/15/18/20/23....W CFL are some of
the FTL and CFLs available in the market .Some of the
manufacturers or suppliers are either importing partly
or fully the components of these lamps from their
collaborators. Among the energy efficient lamps, the
most common are 40 W FTL and 11W CFL. So we
have tested these lamps to find out the harmonic
impact.
3. Experiments
The lamps are connected to the Kerala power grid for
the performance evaluation. The grid is normally
operating at 240 V, 50 Hz. However the under
frequency operation (4850Hz) and wide voltage
fluctuations (170260V) are common in the Kerala
grid.To estimate the actual performance, we have
tested the items without any frequency settings. So
during testing frequency was only 47.9 Hz. Rated
performance may not be obtained under this operating
condition.
The voltage was varied using the autotransformer
to find out the starting voltage (Von) for the lamps from
the cold condition of the lamps. Thereafter the voltage
was varied in suitable steps and current, power, power
factor, lux, current and voltage waveforms and
distortions were observed. Total Harmonic
measurements (THD %)are done with ITT make ALM
3 Energy analyser in the Harmonic mode. Lamp glow
off voltage (Voff) is also measured. Lux was measured
at the top surface of a standard office table exactly
below the lamp. The lamp was kept at a height of 9
feet from the ground. All the measurements were
carried out in the dark room condition.
4. Results
Important observations are shown in tables 1 to 6.
We have tested 4 feet 40 W standard fluorescent
tubes of three different makes available in the market.
40 W FTL when operating with electromagnetic ballast
will have poor power factor (0.50.6 lag). THD is
minimum in the order of 78 %.( table1). Major
harmonic components are 3
rd
7.6%,5
th
2.4%,7
th
0.69%.
When 3 microfarad capacitor is connected across the
supply input, power factor is improved (0.8), but the
current wave from distortion increases to 28% (table 
2). A higher order capacitor will still improve the power
factor but distorts more the current mainly increasing
the 3
rd
and 7
th
harmonics. So with FTL while improving
the source power factor it must by taken into
consideration to eliminate the harmonics by suitable
filters so as to maintain reasonable power quality.
A wide variety of electronic ballasts are available in the
market . We have tested some of the electronic ballasts
available in the market.The local makes of electronic
ballasts are cheap but not long lasting and provide
current distortions upto 4050% with poor power
factor. It is found that current distortion levels are
better (in the order of 5 11%) with good power factor
of above 0.9 (leading) for reputed makes of electronic
ballast (tables 3&4).
For 11W CFL, both electromagnetic ballasts and
electronic ballasts are available in the market. As
shown, with electromagnetic ballast power factor of
operation is poor (040.6 lag) with low current
distortions (THD 78%). But with electronic ballasts
(builtin or separate) power factor becomes 0.45  0.6
leading and current distortions becomes as high as
50% (tables 5&6).
5. Percent Retrofit with CFL
In a building with 100 kVA load, if we provide CFL
instead of incandescent lamp the performance will be
as given in table 7. With 100 % CFL replacement i.e.
26.3 % of building load ,pf is reduced to 0.65 and
voltage distortion increased to 4.4 % (still with in IEEE
519 limit 5%) .But THD increased to 23.5%.
5 . Conclusion
There is no doubt that we shall go for fluorescent
lamps (FTL and CFL) instead of incandescent bulbs to
save energy and to improve lighting quality. But by
implementing the same, we must see that these shall
not affect the power quality of the system. Here we
have tested only a few makes of fluorescent lamps and
ballasts, that too with grid limitations.
It is observed that by providing electronic ballast of
reputed make and better quality with adequate
harmonic filters will improve the light intensity, quality
of light, power factor and reduce the distortion levels
from that with a simple capacitor for improving the
power factor. Manufactures and suppliers shall ensure
their products confirm the stipulated standards of
power quality besides energy efficiency.
T ABLE I
Performance Evaluation Of 240v, 40w FTL Of Various Makes With Electromagnetic Ballast
Make of
FTL
Voltage
V
Current
A
Power
W
Power factor
(lag)
V
on
/V
off
Lux THD%
.
A 240 0.36 49.9 0.565 167/133 93 8
B 240 0.37 50.3 0.541 171/140 88 7
C 240 0.38 53.2 0.570 169/121 102 8
TABLE 2
Performance Of 40w Fluorescent Tube With Electromagnetic Ballast With And Without Capacitor
(Make  Bajaj Tube with Bajaj Electromagnetic Ballast)
Voltage
V
Current
A
Power
W
Power factor THD%
without capacitor 240 0.372 53 0.593 8
with 3F capacitor 240 0.273 51.25 0.784 28
TABLE 3
Performance Evaluation Of Different Electronic Ballasts For 4o W Fluorescent Tube
(Tested with 40 W Fluorescent Tube  BAJAJ make)
Make of
ballast
Voltage
V
Current
A
Power
W
Power
factor(lead)
V
on
/V
off
THD%.
A 240 0.171 39.10 0.953 134/48 11
B 240 0.294 36.90 0.521 88/55 40
C 240 0.149 33.21 0.928 118/42 13
D 240 0.159 36.84 0.959 60/32 11
E 242 0.228 34.20 0.447 55/30 46
F 240 0.331 39.71 0.5 54/32 42
TABLE 4
Harmonic Components Of 40 FTL with A Typical Electronic Ballast
Component 3 5 7 9 11 THD %
% Harmonics 24.8 19.5 11.3 7.4 4.3 46
TABLE 5
Performance Evaluation Of 11w CFL Of Various Makes With Electromagnetic Ballast.
MM Make
of CFL
Voltage,
V
on
/ V
off
Current,
MilliAmp.
Power,
Watts
Power Factor (Lag) Lux
THD%
A
B
C
D
E
180/144
186/138
187/140
188/120
192/138
146.3
149.9
151.3
154.4
196.6
18.1
18.5
18.8
18.1
18.1
0.511
0.519
0.514
0.488
0.515
14
18
17
14
17
8
7
8
7
8
TABLE 6
Performance Evaluation Of 11w CFL Of Various Makes With Electronic Ballast.
MM Make
of CFL
Voltage,
Von / Voff
Current,
MilliAmp.
Power,
Watts
Power
Factor
(Lead)
Lux
THD%
A
B
C
D
E
100/56
82/54
98/56
142/84
94/64
104
114
112
121
109
11.8
13.5
12.8
13.4
11.9
0.511
0.519
0.514
0.488
0.515
24
23
20
19
24
40
48
42
46
50
TABLE 7
Impact Of CFL On 100 kVA Building Load
% CFL LOAD 1.5 4.1 9.4 26.3 50
TOTAL POWER FACTOR 0.84 0.82 0.78 0.65 0.54
% VOLTAGE
DISTORTION
0.3 0.7 1.5 4.4 5.4
%THD 1.7 4.5 9.8 23.5 55
VOLTAGE SAG ANALYSIS.
Dr.S.Thiruvengadam
Prof.&Head, Dept.of Elect.Engg.
Sri Venkateswara College of Engg.,Sri perumbudur
1.0 Introduction
Voltage sags and momentary power interruptions are probably the most important PQ problem
affecting industrial and large commercial customers. These events are usually associated with a fault at some
location in the supplying power system. Interruptions occur when the fault is on the circuit supplying the
customer. But voltage sags occur even if the f aults happen to be far away from the customer's site. Voltage sags
lasting only 45 cycles can cause a wide range of sensitive customer equipment to drop out. To industrial
customers, a voltage sag and a momentary interruption are equivalent if both shut their process down. A typical
example of voltage sag is shown in fig 1. The susceptibility of utilization equipment to voltage sag is dependent
upon duration and magnitude of voltage sags and can be defined by a susceptibility curve as shown if fig. 2 .
2.0 Characteristics of Voltage Sags:
Voltage sags which can cause equipment impacts are caused by faults on the power system.
Motor starting also results in voltage sags but the magnitudes are usually not severe enough to cause equipment
misoperation
2.1 How a fault results in voltage sag at a customer facility?
The one line diagram given below in fig. 3 can be used to explain this phenomenon.
Consider a customer on the feeder controlled by breaker 1. In the case of a fault on this feeder, the
customer will experience voltage sag during the fault and an interruption when the breaker opens to clear the
fault. For temporary fault, reclosure may be successful. Any way, sensitive equipment will almost surely trip
during this interruption.
Another kind of likely event would be a fault on one of the feeders from the substation or a fault
somewhere on the transmission system, In either of these cases, the customer will experience a voltage sag
during the actual period of fault. As soon as breakers open to clear the fault, normal voltage will be restarted at
the customer's end. Fig 4 is a plot of rms voltage versus time and the waveform characteristics at the customer's
location for one of these fault conditions.
This waveform is typical of the customer voltage during a fault on a parallel feeder circuit that is
cleared quickly by the substation breaker. The total duration of fault is 150m sec. The voltage during a fault on
a parallel feeder will depend on the distance from the substation to fault point. A fault close to substation will
result in much more significant sag than a fault near the end of feeder. Fig 5 shows the voltage sag magnitude at
the plant bus as a function of fault location for an example system.
A single line to ground fault condition results in a much less severe voltage sag than 3phase fault
condition due to a deltastar transformer connection at the plant.
Transmission related voltage sags are normally much more consistent than those related to distribution.
Because of large amounts of energy associated with transmission faults, they are cleared as soon as possible.
This normally corresponds to 36 cycles, which is the total time for fault detection and breaker operation
Normally customers do not experience an interruption for transmission fault. Transmission systems are
looped or networked, as distinct from radial distribution systems. If a fault occurs as shown on the 115KV
system, the protective relaying will sense the fault and breakers A and B will open to clear the fault. While the
fault is on the transmission system, the entire power system, including the distribution system will experience
voltage sag. Fig 6 shown the magnitude of measured voltage sags at an industrial plant supplied from a 115 kV
system.
Most of the voltages were 1030% below nominal voltage, and no momentary interrupts were measured at
the plant during the monitoring period (about a year). Fig7 given a threedimensional plot illustrating the
number of sags experienced as a function of both the voltage sag magnitude and the duration.
This is a convenient way to completely characterize the actual or expected voltage sag conditions at a
site. Evaluating the impact of voltage sags at a customer plant involves estimating the member of voltage sags
that can be expected as a function of the voltage sag magnitude and then comparing this with equipment
sensitivity.
The estimate of voltage sag performance are
developed by performing shortcircuit simulations to
determine the plant voltage as a function of fault
location throughout the power system. Total circuit
miles of line exposure that can affect the plant (area
of vulnerability) are determined for a particular sag
level. Historical fault performance (fault per year
per 100 miles) can, then be used to estimate the
number of sags per year that can be expected below
the magnitude. A chart such as the one in fig 8. Can
be drawn in splitting the expected number of voltage
sags by magnitude.
This information can be used directly by the
customers to determine the need for power
conditioning equipment at sensitive loads in the
plant.
3.0 VoltageSag Analysis Methodology
The methodology is outlined in chapter9 (proposed) of IEEE Gold book (IEEE standard 493,
Recommended practice for the design of reliable industrial and commercial power system)
The methodology basically consists of the following four steps:
3.1Load Flow:
A load flow representing the existing or modified system is required with an accurate zero
sequence representation. The machine reactance Xd" or Xd ' is also required. The reactance used is dependent
upon the post fault time frame of interest. The machine and zerosequence reactance are not required to
calculate the voltage sag magnitude.
3.2Voltage Sag Calculation :
Sliding faults which include lineline, line to ground, line to line to ground and three phase are
applied to all the lines in the load flow. Each line is divided into equal sections and each section is faulted as
shown in fig 9.
3.3 Voltage Sag Occurrence Calculation:
Based upon the utilities reliability data (the number of times each line section will experience a
fault) and the results of load flow and voltage sag calculations, the number of voltage sags at the customer site
due to remote faults can be calculated. Depending upon the equipment con nection, the voltage sag occurrence
rate may be calculated in terms of either phase or line voltages dependent upon the load connection. For some
facilities, both line and phase voltages may be required. The data thus obtained from load flow, Voltage sag
calculation, and voltage sag occurrence calculation can be sorted and tabulated by sag magnitude, fault type,
location of fault and nominal system voltage at the fault location.
3.4Study of Results of Sag Analysis:
The results can be tabulated and displayed in many
different ways to recognize difficult aspects. Area
of vulnerability can be plotted on a geographical
map or one  line diagram (fig 9).
These plots can be used to target
transmission and distribution lines for enhancements
in reliability. Further barcharts, and piecharts
showing the total number of voltage sags with
reference to voltage level at fault point, area/zone of
fault, or the fault type can be developed to help
utilities focus on their system improvements (fi gs.
10 and 11)
In addition to examining the existing system, system modifications aimed at mitigating or reducing
voltage sags can also be identified, thus enabling cost benefits analysis. Possible such system structural changes
that can be identified include.
Reconnection of a customer from one voltage level to another
Installation of ferroresonant transformers or time delayed under voltage, drop out relay to facilitate
easy ride  through the sag
Application of static transfer switch and energy storage system.
Application of fast acting synchronous condensers
Neighborhood generation capacity addition
Increase service voltage addition through transformer tap changing
By enhancement of system reliability
4.0 Equipment Sensitivity Studies:
A Process controllers can be very sensitive to voltage sags. An electronic component manufacturer was
experiencing problems with large chiller motors tripping offline during voltage sag conditions. A 15VA
process controller which regulates water temperature was thought to be causing individual chillers to trip. This
controller was tested using a voltage sag simulator for voltage sags from 0.51000 cycles in duration. The
controller was found to be very sensitive to voltage sags tripping at around 80% of voltage regardless of
duration.
B Chip Testers: Electronic chip testers are very sensitive to voltage variations, and because of the complexity
involved, often require 30 minutes or more to restart. In addition, the chips involved in the testing process can
be damaged and several days' later internal electronic circuit boards in the testers may fail. A chip tester consists
of a collection of electronic loads, printers, computers, monitors etc. If any one component of the total package
goes down, the entire testing process is disrupted. The chip testers can be 50KVA or larger in size.
C.DC Drives: DC drives are used in many industrial processes, including printing presses and plastics
manufacturing. The plastic extrusion process is one of the common applications where voltage sag can be
particularly important. The extruders melt and grind plastic pellets into liquid plastic. The liquid plastic may
then be blowup into a bag or processed in some other way before winder winds the plastic i nto spools.
During voltage sag, the controls to the D.C. drives and winders may trip. These operations are
typically completely automated and an interruption can cause very expensive cleanup and restarting
requirements. Losses may be of the order of Rs. 15 lakhs / event and a plant fed from a distribution system is
likely to experience at least one event per month. Extruders begin to have problems when the voltage sags to
only 88% of normal, which indicates a very high level of sensitivity. Faults May miles away from the plant will
cause voltage sags down to 88% level. Even protecting only the winders and controls does not serve the purpose
always. When they are protected and voltage sag occurs, the controls and winders continue to work properly.
However, the dc drives slow down. For severe voltage dips, the slowing down is so much that the process is
interrupted. Therefore D.C. drives also need to be helped to ride through all voltage sags.
D.Programmable Logic Controllers. Their overall sensitivity to voltage sags varies greatly by portions of an
overall PLC system have been found to be very sensitive The remote I/O units have been found to trip for
voltages as high as 90% for a few cycles.
E. Machine Tools: Robots or complicated machines used in cutting, drilling and metal processing can be very
sensitive to voltage variation. Any variation in voltage can affect the quality of the part that is being machined.
Robots generally need very constant voltage to operate properly and safely. Any voltage fluctuations
especially sags. May cause unsafe operation of robot. Therefore these types of machines re often set to trip at
voltage levels of only 90%
5.0 Solutions to Voltage Sag Problems:
Efforts by utilities and customers can reduce the number and severity of sags.
A. Utility solutions: Utilities can take two main steps to reduce the detrimental effects of sags  (1) Prevent
fault (2) Improve fault clearing methods
Fault prevention methods include activities like tree trimming, adding line arrests, washing insulators and
installing animal guards.Improved fault clearing practices include activities like adding line reclosers,
eliminating fast tripping, adding loop schemes and modifying feeder design. These may reduce the number and /
or duration of momentary interruptions and voltage sags but faults can not be eliminated completely.
B. Customer solutions: Power conditioning is the general concept behind these methods. Fig 12 is a schematic
of the general approach used.
Power conditioning helps to
1. Isolate equipment from high frequency noise and
transients.
2. Provide voltage sag ride through capability
The following are some of the solutions
available to provide ride  through capability to
critical loads.
Motor generator sets (MG sets)
Uninterruptible Power supply (UPS's)
Ferro resonant, constant voltage transformers
(CVT's)
Magnetic synthesizers
Super conducting storage devices (SSD's)
MG sets usually utilize flying wheels for energy storage. They completely decouple the loads
from electric power system Relational energy in the flywheel provides voltage regulation and voltage support
during under voltage conditions. MG sets have relatively high efficiency and low initial cost.
UPS's (Fig.13): utilize batteries to store energy which is converted to usable form during an
outage or voltage sag UPS technology is well established and there are many UPS configurations to choose
from.
CVT's can be used to enhance voltage sag ride through capability. CVT's are basically 1; transformers
which are excited high on their saturation curves, thereby supplying output voltage which is fairly independent
of input voltage variations. Magnetic synthesizers are generally used for larger loads. A load of at least several
KVA is needed to make these units cost effective. They are often used to protect large computers and other
sensitive electronic equipment, This is an electromagnetic device which generates a clean three phase ac output
way form regardless of input power quality (Fig . 14)
SSD's utilize a super conducting magnet (Fig.15) store energy in the same way a UPS uses
batteries to store energy. SSD's occupy less space and use fewer electrical connections as compared to UPS's
thus promising better reliabil ity. They are also expected to become economically competitive.
6.0 Conclusion:
The problems of voltage  sag has to be tackled in two ways. The customer will have to
improve the ride through capability of their sensitive equipment. If system power conditioning is expensive, it
may be economical in the long term to improve the actual process equipment.
The voltage sag integration program if implemented by utilities cab yield the following
benefits to utility,
1 New customers may be attracted by sag performance.
2 Existing customer satisfaction may be enhanced by quick correction of voltage sag
performance
3 Areas may be detected for system enhancement
4 Power quality disputes can be settled.
5 Public relations will be better.
6 Even current protection can be evaluated as it applies to duration of voltage sag.
References:
1 J.Lamoxee, et at"The impact of voltage sags on industrial plant loads"' presented at the First
international conference on Power Quality, Paris France Oct 1416,1991
2 L Connad etal" Predicting and preventing problems associated with remote fault clearing voltage
dips" IEEE Trans . I.A Vol.27 P 167172 Jan 1991
===============
EFFECT OF POWER SYSTEM HARMONICS
ON POWER SYSTEM EQUIPMENT & LOADS
Ashok.S
Lecturer,Dept. of Elect. Engg.
R.E.C,Calicut .
We know that the electronic based nonlinear
loads represent the sources of harmonic currents. A
nonlinear load connected to the bus with 50Hz
constant bus supply voltage draws current in a non
sinusoidal fashion and returns a distorted current wave
form to the system. Harmonic current generally will
flow towards the supply because the source impedance
is low. Now let us see the adverse effects of these
harmonics.
Single Phase Branch Circuits
Branch circuits have allowed one common neutral
conductor for three, single phase circuits. The logic
behind this design was that the neutral conductor
would carry only the unbalanced current. Under
balanced conditions supplying single phase, nonlinear
loads, the common neutral of three, single phase
branch circuits carries zero sequence triplen
harmonics which are addictive in the neutral
conductor. Under unbalanced conditions, the common
neutral carries currents comprised of the +ve
sequence, ve sequence currents from the unbalance
and the addictive zero sequence currents from the
triplen harmonics. A common neutral conductor can
thus easily becomes overloaded when supplying
balanced or unbalanced, nonsinusoidal loads. The
neutral current can be as high as 1.7 times phase
current.This excessive current in the neutral cause
higher than normal voltage drop between the neutral
and ground. Thus may disrupt the sensitive electronic
equipment operation like PCs. Unfortunately there are
no standards limiting these harmonics from these
single phase loads (except IEC  1000. part (3) ). The
best method to avoid overloading is to ensure that the
loads are balanced and to provide a separate full sized
neutral conductor. To manage heating effects due to
excessive currents, neutral conductors can be even
double sized some times.
Three Phase Equipment Circuits
Delta connected, three phase nonlinear loads like
UPS and VF drives cannot generate zero sequence
triplen harmonic currents in the supply circuit. The
+ve and ve sequence harmonic currents, however,
flow throw the phase conductors towards the source.
These will increase the conductor heating due to
higher rms currents flow and due to the skin effect.
The net result of the skin effect is that the effective
conductor cross sectional area is reduced as frequency
is increased. Higher the frequency, higher the ac
resistance. So when harmonic load current flows, Rac
equivalent will get increased amplifying 1
2
*Rac
copper losses.
To avoid overheating, we may derate the conductors to
1/Rac (but still skin effect and power losses) or
provide two or more parallel conductors per pha se.
For Y connected nonlinear loads, +ve and ve
sequence harmonic currents will mostly cancel at the
neutral bus. The addictive zero sequence triplen
harmonics and any unbalance phase currents will pass
the neutral conductor. There we may provide adequate
conductor size.
Conductor/Cable Heating  Loss of Life
As already pointed out, conductor heating due to
harmonics, can be not only due to skin effect but also
due to proximity effect. This is due to the magnetic
field of conductors distorting the current distribution
in adjacent conductors. In round wires, proximity
effect is much less than skin effect. Metal sheathed
conductors can also lead to proximity effect. The ratio
Rac/Rdc for a 5
t h
harmonic current can be 1.33 due to
proximity effect in adjacent conductor of 4/0 SWG.
Cable heating causes a degradation of dielectric, cable
jacket both in its dielectric role and in its mechanical
protection role, and a possible reduction of over all
ampacity of the cable. The dielectric may get oxidised
and hence life gets reduced due to heating.
Transformers
The effect of harmonics on transformers is two fold 
current harmonics cause an increase in copper losses
and stray flux losses  i.e. increase in heating,
insulation stresses, possible resonance at the harmonic
frequency between transformer winding and line
capacitance and possible small core vibrations.
The primary loss components are winding 1
2
R losses,
winding eddy current losses and stray flux losses. The
losses due to the 1
2
R component will be due to
conductor heating and the skin effect. Eddy current
losses in the conductor,
We(HF) = W(FF)
( n* In/Ir)
2
n=1 ,..,
will increase with square of the harmonic currents and
square of the frequencies. Other stray flux losses
increase with frequency at a power 1.7 1.8.
As the core is non linear, the effect of harmonic
voltages on the core loss is not apparent. However it
could also approximately vary as per the above
relationship.
The additional heating caused by harmonics
requires load capability derating to remain within the
temperature rating of the transformer or use of
speciality transformers designed for non  sinusoidal
load currents. Transformer life will be reduced as the
result of operating above rated temperature. Typical
loss of life in transformers due to harmonics depends
on the dielectric used as well as harmonic content.
Fig.1 shows typical loss of life verses THD.
The source of the harmonics in the
transformer magnetic flux may be due to transformer
itself. This is the result of over excitation ( i.e. high
applied voltage ) typical over excitation characteristics
is shown in Fig.2.
It shall be noted that the transformer losses caused by
both harmonic voltages and harmonic currents are
frequency dependent. The losses increase with
frequency. IEEE/ANSI C57 specifies a load current
distortion factor limit as 0.05 per unit. Current
standards outline transformer overvoltage rating on an
rms steady state basic. The maximum over voltage 5%
at rated load and 10. %. at no load, specified include
any contribution resulting of distortion
Additive sequence triplen harmonics in the
neutral pass through the distribution system until they
reach a delta wye transformer. There it is reflected in
to the delta primary winding where it circulates and
causes over heating and failures. These will not appear
in the primary lines hence can not be measured.
Oversizing transformers to compensate the
above will be more worse and cumulative as the larger
conductors accentuate the heating effects and allow
larger amounts of harmonic currents to flow in to the
system. This also violates NEC and Underwriter's
laboratory listing and labelling requirements. To meet
UL and NEC Requirements, Kfactor transformers
must be specified. Greater K  factor means increased
harmonic current capability.
Motors and Generators
As a group, they offer low impedance to
harmonics. The magnitude of the nth harmonic current
(rms) in a 3 phase induction motor may be
In = Vn/(n*f*L
n
)
where L
n
 effective leakage inductance of stator &
rotor w.r.t to stator
The effective inductance tends to decrease as n
increases, due to the skin effect. The min. value L
l
equals the external leakage inductance of stator and
rotor, when internal bar inductance is negligible.
So we have, In = Vn/(n*f*L
l
)
The motor losses due to these harmonic currents are
influenced by a wide range of parameters.
1
2
R type losses shall be  stator and rotor winding
losses and stray losses  influenced with effective
resistive variation with frequency. Additional core
losses due to harmonics will be small.
The total harmonic losses can be estimated as
P
h
= Pn =k Pr ( Vn
2
/ n
1.5
V
1
2
)
n=5,
Pr  machine loss at the rated load with sinusoidal
voltage. Approximate value of constant k,
k= (Ts/Tr)*E/ (1Sr) (1Er)
Er  Efficiency,Tr totque & Sr slip at rated load. Here
we have assumed that smaller harmonics are not
present ( n upto 4 ) , as is often. This indicates motors
with large deep bar or double cage will have highest
harmonic heating.
Core and stray loses may become significant
for an Induction motor with skewed rotors. An
increase in motor operating temperature will cause
reduction of the mot or life. Singlephase motors are
the most affected. The temperature rise is not uniform
through out the motor and hence hot spots appear near
the conductors with in the core. There are no limits
available on motor harmonics heating. However ve
sequence voltage at the motor terminals range from 1
5 % as per standard may give a general guideline.
In addition to heating, pulsating torque are
produced by interaction of the air gap flux due to the
fundamental and fluxes due to the harmonic currents.
Motor will have to withstand the pulsation. For
adjustable speed drives, an analysis of the mechanical
resonance speeds is necessary to avoid damages due to
amplification of pulsating torque.
Another problem is the excessive noise and
vibration due to the difference between time
harmonics and frequencies.
For synchronous machines, detailed analysis
becomes essential as the harmonic impedance is equal
to harmonic number of times the subtransient
reactance. Heating effects will be very similar to that
of induction motors. Harmonics can produce
mechanical oscillations due to oscillating ( pulsating)
torque. These oscillating torques has the potential for
simulating the turbo  generator in complex coupled
modes of vibration leading to damages.
Compared to transformers  heating effect of
nonlinear loads on generators is significantly greater.
A generator has much higher reactance and
impedance. The combination of high reactance and
high frequency flux changes is the basic cause of
heating the stator. High frequency currents will induce
currents in the pole faces and hunting winding and
hence cause rotor heating. Hence the generator
supplying nonlinear loads must be derated. The
derating depends on the generator reactance.
The fast rise time of the distorted current is
highly sensitive to the sub transient reactance (Xst).
Thus high level of sub: tr.: reactance results in high
level of voltage distortion. So it is better to keep
Xst<10 %.
AVR is to regulate the output voltage, which
is connected generally between a singlephase output
and neutral. This connection causes AVR circuit
undercorrect under non linear loads. So an AVR
should sense the average of the 3 phases, line to line.
In certain cases special pitch factors may be
provided during the design itself. Ex: a twothirds
pitch winding has lower impedance to 3
rd
harmonics,
but higher impedance to 5
th
& 7
th
harmonics. So an
exact load characteristics shall be known to determine
the correct pitch factor to compensate the distortion
effects.
Capacitors
The effect of the harmonics on the capacitor bank is to
cause additional heating, losses and increased
dielectric stress.
Increased losses due to harmonics
L = 2 fn C (tan )n Vn
2
n=2,..,
If high harmonic contents persist, it would cause
shortened the life or equipment failure.
Parallel resonance can occur in any distribution
system with capacitors. As f increases, Xl increases
and Xc decreases. During resonance at a particular
frequency, currents and voltages amplified. The
problem associated with parallel resonance is typically
harmonic heating. Resonant frequency can be
determined in line with
n = v (MVA sc/MVArc)
MVA
sc
 short circuit MVA available
MVA
rc  MVAr rating of the capacitor bank
For low voltage installations, following guidelines can
be accepted to reduce resonance effect:
(MVA of harmonic producing load / MVA rating
of transformer)
<10% No resonance anticipated
<10  30% Depends on MVAr of
capacitor banks
>30% Capacitors shall be applied
as filters
IEEE standard 18 stated that total operating
reactive power shall not be greater than 135% of its
rated value, current due to fundamental harmonic shall
not exceed 180% and peak voltage shall not exceed
120%. However it does not specify any limit on
individual hamonics.
Capacitive harmonic current will be
Ln = n V
n
If V
7
is 15%, I
7
= 105%. This demonstrates why
spurious fuse blowing in capacitors is often a
symptom of harmonic problems.
Fuses and Circuit breakers
Fuses respond to the true  rms heating value of the
load current and melt when the fuse element becomes
too hot. Significant harmonic current causes excess
heating that can cause shifts in the time cur rent
characteristics of the device. (particularly low
magnitude faults).Links in certain cases are
susceptible to skin effect heating by harmonics.
Harmonics can affect the current interruption
capacities of the circuit breaker. Harmonic
components can cause in high di/dt magnitudes at the
current zeros making interruption more difficult.
Failure of breakers has also been attributed to the
inability of the blow out coils to operate adequately
with harmonics. As the blow out coil effect is delayed,
which prolongs arcing and results in failure. Vacuum
breakers are less sensitive to distortions than air
magnetic breakers. Instantaneous mechanism of some
breakers is a solenoid that dissipates additional heat
due to losses for harmonics. The heat rises the temp.
which reduces the trip point.
Protective Relaying
Harmonic may cause relays to operate improperly or
to not operate when required. Relays exhibit a
tendency to operate slower or with higher pickup
under harmonics. The presence of excessive zero
sequence third harmonic current can cause ground
relays to false trip. Static under frequency relays were
susceptible to substantial changes in operating
characteristics due to distortions. Depending on
harmonic content, operating point, operating torque
and time may get changed for static relays.Harmonics
can impair high speed operation for differential relays.
Balanced beam impedance relays can exhibit both
under reach and overreach. Sympathetic interaction of
transformer is the result of malfunction of distance
relays.
Electronic loads
Electronic loads are affected by voltage wave
shape rather than magnitudes.Hence instead of voltage
distortion factor, voltage deviation factor shall be
used. Here, voltage deviation effects are complex as it
is affected by harmonic amplitude and phase angle.
A digital clock will rapidly advance the time
in the presence of added zero crossing from harmonic
distortion. Multiple crossings can change the
switching times of the semiconductor devices and
disrupt operation at the equipment. Electronic power
supplies use the peak voltage of the wave firm to
maintain the filter capacitors at full charge. Distorted
input wave forms will create crest factor deviations.
Voltage notching can also disrupt operation
of electronic equipment by amplification of power
supply resonance. Fractional and subharmonics can
affect Video displays or televisions. Loss of
memory/data in PCs and printers are common due to
harmonics in the supply voltages.
Telephone Interference
Human hearing sensitivity and telephone
response peak near 1kHz, power system harmonics
can present greater problem to communication. TIF
will present the effect of the harmonics on
communication.By loop induction, power line
magnetic field induces a voltage in the loop formed by
the two telephone lines. The loop may also be formed
between a telephone conductor and the earth.
Capacitive coupling between power and telephone line
can cause interference. Transposition of power lines,
twisting of telephone lines, shielding of telephone
lines may reduce interference effects. Conductive
coupling in which a local ground potential rise due to
the power neutral is applied to the grounded phone
conductor which creates abnormal local ground
potential rise resulting in interference.
Metering
The bandwidth or the frequency characteristics of
PTs/CTs/ meters are important as far as measurements
are considered. Generally PTs/CTs,and analog meters
are of low band width (below 300Hz).
RMS meters are not affected as long as the harmonics
are with in the operating bandwidth of the meters and
peak factor of waveform not excessively large.
Average responding meters calibrated in rms and peak
responding meters are not suitable with distorted
waves.
Wattmeters and watt hour meter show errors from the
frequency characteristic of the voltage and current
waves. Power factor of the harmonics can also affect
the errors. Errors can be reduced by digital sampling,
thermal quarters  square multiplication or translinear
multiplication. Registration of induction energy meter
is affected by the frequency characteristics and non 
linearity and resonance effects ( errors upto + 20% )
Lighting
Incandescent lamp is sensitive to increased heating
effects. A relative equation for bulb life is
L = (1/ V
n
) = 1/( V2 (1+DF
2
) )
n/2
V
1
 Per unit fundamental voltage
L  Per unit bulb life
A representative value of n is 13. Large
distortion factors (DF) will shorten the life.Under
continuous operation at 105% rated rms voltage, lamp
life gets reduced by 47%.
For discharge lamps, the operation of e.m. ballast
gets affected (resonance,heating,exess loss) by
distortion factors. For electronic ballast, break down
of semiconductor components leading to failure of
ballast will be the result from highly distorted supply
voltages. Audible noise is another important problem
due to harmonics. In fixtures with capacitors,
capacitors with ballast inductor and lamp may create
resonance problem.
Miscellaneous effects of harmonics
..Over voltage can lead to the inception of corona,
insulation degradation in power lines.
 Effect of voltage distortion on surge protective
devices sparkover and recovery of gapped devices
and heating of solid state devices.
 Erroneous operation of carrier systems which
control remote devices.
 Core saturation in PCs and certain machines
 Derating of equipment associated with neutral
grounding devices.
 Higher audible noise &occasional arcing in
coupling capacitor voltage transducers.
 Noise & malfunctioning of control systems.
==========
POWER AND ENERGY MEASUREMENTS
Ashok.S
Lecturer,Dept. of Elect. Engg.
R.E.C ,Calicut
1. Power and power measurements
Electric power is conventionally defined for
sinusoidal waveforms, using the phasor theory for
voltage and current, in terms of the complex power S.
S = V. I *
I * is the complex conjugate of the current phasor I.
Complex power S can be expressed as
S = P +jQ or S
2
= P
2
+Q
2
.
P  the active power is that part of apparant power
associated with the transfer of net energy to the load.
Q  the reactive power is that part of apparant power
associated with oscillating power flow in systems.
But this definition is applicable only for sinusoidal
conditions.
As we know, the time varying quantity power
can be taken as rate of change of energy. Hence
instantaneous power P(t) = d (W(t))/dt
But we know that
v(t) = d(W(t))/dq
i(t) = d(q(t))/dt
Hence p(t) = v(t) .i (t).
For sinusoidal conditions, the average value of both
v(t) and i(t) are zero. Their Fourier series contain only
one term each (fundamental).
So under s inusoidal case, average power
Pa = 1/2 {v(t)i (t) dt
Taking v(t) = Vm Cos (t) ; i(t) = lm Cos (t + ),
Pa =0.5Vm Im Cos ,
putting in r.m.s values P
a
= V.I Cos
Note that this average power is physically the time
rate of change of useful energy delivered. In complex
voltampere (apparent power) notation
P
a
= SCos = P where Cos is the power
factor.
Q = SSin . Sin is sometimes used as reactive
power factor.
Now in nonsinusoidal case,
P
a
= 2 V
n
  I
n
 Cos (
n
)
n = 0
Here voltage and currents are rms magnitudes of the
Fourier terms for the frequency component n and
n
is power factor for the nth harmonic waveforms.
Now let us examine whether the relationship S
2
= P
2
+
Q
2
is valid for non sinusoidal conditions. When both
voltage and current are nonsinusoidal and periodic
total reactive power can be
Q
= 2 V
n
  I
n
 Sin (
n
).
n = 1
But then,  S = V Iwill be greater than (P
2
+
Q
2
).The reason that the complex power is larger than
that in the purely sinusoidal case is that there are cross
forms in the product of Fourier series which
correspond to voltages and currents of different
frequencies. That is, active power P and reactive
power Q are corresponding to the product of voltages
and currents of the same frequency. So to account for
the cross terms, we can write S
2
= P
2
+ Q
2
+ D
2
where D is the distortion volt amperes. Or distortion
power or deactive power.
This distortion power corresponds to the
products of voltages and currents of dissimilar
frequencies in the Fourier series of V(t) and I(t). In
pure sinusoidal case, D = 0. D physically represents
the difference between apparent and active and
reactive powers.
D =  S
2
 P
2
Q
2
In the time domain approach, three
components either in the current or voltage associated
with active, reactive and distortion powers can be
distinguished.
I = i
p
+ i
q
+ i
D
where
i
p
= P/V
2
U (t)
IQ = (Q/V
2
)H u (t)
( Hilbert transform approach)
Now i
d
= i i
p
 i
q
Being the current components or orthogonal we have
I
2
= I
p
2
+ I
Q
2
= I
D
2
V
2
I
2
= V
2
I
p
2
+ V
2
I
Q
2
+V
2
I
D
2
So distortion power can be D = VI
D
.
Active power is traditionally measured with a
wattmeter (twowattmeter method in 3 phase
systems). The torque created is proportional to
average power (P
a
=P). The bandwidth of these
instruments is generally limited to 300 Hz. In digital
construction, A/D converters every T seconds digitize
voltages and currents (through the shunt resistors).
The quantity V(t)x I(t) is calculated by multiplier
elements. These products are summed over a cycle.
For N samples, P
a
= I/N V(I) I(I) dT. Where the
summation is over 1 to N.
Using FFT techniques,digital instruments can
measure active and reactive power. P = ( a
I
c
I
 b
I
d
I
) and Q= ( a
I
d
I
 b
I
c
I
) where I runs from 0 to M
and Fourier coefficients of voltages and currents are
aj+jbj and ej +jdi and M is the harmonic truncation
limit.
Using DSP techniques, IEEE committee has
recommended following arrangements for the
measurements of power components separately.
Here Deactive power corresponding to cross
correlation between the voltage and current
waveforms (sampled) is taken as
R
vi
(k) = (1/N) V(j) I (j k) ,j=0 to N1,k= 
(N+1) ,0,.(N1).
2. Energy Measurements
Energy measurement is needed at residential,
commercial, and industrial loads in power distribution
systems. Residential customers generally pay a
charge, which is a function of the energy consumed.
The function may be nonlinear and/or time dependent
(e.g., time of day billing), but the essence of the
payment is on the energy consumed. At commercial
and industrial loads, billing always includes an energy
component; it may, however, also include an
additional charge for the peak power in a given time
interval. (T.O.D. Metering).
The introduction disc Watt hour meter is
probably the most familiar energy measurement
device. The essence of the instrument is the induction
of a current in the disc that is proportional to the
circuit voltage. The disc current produces a magnetic
field that interacts with the magnetic field produced by
the current coil. A torque, which is designed to be
constant over a wide range of shaft speeds. The torque
produced by the electrical circuit is proportional to the
product of the voltage and the component of the
current that is in phase with the voltage. The average
torque causes the disc too turn, and therefore the disc
speed is proportional to VIcos ( ). That is, the speed is
proportional to the circuit active power (the average
power delivered to the load.) The disc is geared to a
register, which counts the revolutions of the disc in a
given interval. The register reading at the end of a
given period minus that at the beginning of the period
is proportional to the integral of the power (energy)
consumed in that period.
The equivalent circuit of the voltage coil and disc
of the induction disc Watt hour meter is shown in
Figure1. The disc resistance and inductance is shown
in the figure as r
d
and L
d.
If the current coil is not
considered, the frequency response of the current in
the disc as a function of the applied voltage and
current is readily found,
V
0
 I
s
r
s
= L
ss
sI
r
+ L
sr
I
s
I
r
(r
d
+sL
d
) = L
rr
sI
r
+ L
sr
sI
s
.
In these equations, the Laplace transform is used and
the voltage and currents are in the Laplace domain.
The inductances are the self and mutual inductances of
the disc. (with subscript rfor rotor) and voltage coil
(with subscript s for stator).
This frequency response has a single zero at s
= 0 and it has two real poles. The analysis is shown
ignores the nonlinear multiplicative effect of the
voltage and current in the circuit to be instrumented.
Also, it ignores nonlinearly of the frictional breaking
torque, and the effects of the magnetic field produced
by the current coil. For these reasons, the analysis can
only be qualitative. However, the frequency response
of an induction disc Watt hour meter is rather
wideband, at least to 600Hz, and the response is
nearly linear over the rated dynamic range of voltage,
current, power, and power factor. The elementary
analysis given above indicates that except for
frequency limitations of the various circuits involved.,
the induction disc meter should respond to high
frequency components in the current and voltage.
Although the induction disc instrument looked like an
induction motor, there is no counter rotating torque in
the meter at high frequency. Of course, the elementary
model breaks down as frequency is raised due to
losses in the disc and iron elements of the meter, stray
capacitances, and frequency response of the Iron and
Aluminium.
At this point, the question as to whether the
induction disc instrument reads high or low in the
presence of distorted waveforms is addressed.
Obviously the instrument will not read DC power,
although a DC bias in either the voltage or the current
(or both) can cause the instrument accuracy to be
degraded. Also, the instrument frequency response
falls with increasing frequency beyond a certain point.
Therefore, one woul d except that the induction disc
instrument reads low compared with the actual energy
flow through the device. However, a critical issue is
whether the high frequency power components are
serving a useful purpose in the load. If for example, a
fifth harmonic appears in the supply voltage to an
induction motor, the torque created by that signal will
average to zero over the normal revolution of the
rotor. Therefore , the induction disc Watt hour meter
will read higher than the useful power delivered to the
load. This is the case since the induction disc
instrument will read the fifth harmonic power, but the
induction motor load will not use this power.
At higher frequencies, for example above the
19th , the induction disc instrument may not respond.
Therefore it will read low whether or not the energy in
the harmonics is useful or not. For example, an exotic
heating load which uses high frequency chopping of
the load current will use all the energy passed to the
heating element, but the induction disc meter may not
read all of that energy.
The solid state Watt hour meter has an
increasing edge over the induction disc instrument.
This is because the solid state instrument can readily
be adapted to digital technologies. For example, if the
load power is instrumented and converted to digital
format, the load power can be logged hour by hour (or
more frequently). Also, the instrument can
automatically apply time of day penalties, it can retain
the highest power demand in a given period (in order
to calculate the power charge).
===========
TRANSFORMERS AND POWER QUALITY ISSUES
Dr.T.L.Jose
Professor,Dept. of Elect. Engg.
R.E.C.,Calicut
1. Introduction
In recent years, there has been an increased concern about the effects of non linear loads on the electric
power system. Nonlinear loads are any loads that draw current that is not sinusoidal and include such equipment
as arc furnaces, gas discharge lighting, solid state motor drives, battery chargers, UPS systems, and the
increasingly common electronic power supply. While nonlinear loads are not new, their increased use means a
larger percentage of any power system tends to be nonlinear. Additionally, nonlinear loads were once thought
to be a concern only to industrial power systems where large static power converters are used. Such is not the
case today. With the widespread application of electronics to virtually every electrical load, nonlinear loads are
also prevalent in commercial and even residential power systems.
Nonlinear loads generate harmonic currents that flow from the load toward the power source,
following the paths of least impedance. Harmonic currents are currents that have frequencies that are whole
number multiples of the fundamental (power supply) frequency. The harmonic currents superimposed on the
fundamental current result in the nonsinusoidal current waveforms associated with nonlinear loads.
Harmonic currents adversely affect virtually every component in the power system, creating additional
dielectric, thermal, and/or mechanical stresses. The harmonic currents flowing through the power system
impedances result in harmonic voltage drops that are observed as harmonic voltage distortion. Very severe
voltage distortion can result when the power system's inductive and capacitive reactances happen to be equal
(parallel resonance) at one of the nonlinear load's significant harmonic current frequencies (typically the 5th,
7th, 11th or 13th harmonic).
With today's increased use of modern electronics has come a corresponding concern about harmonic
currents and their effects on the power system. Most modern electronic equipment contains static power
converters that generate harmonic currents. Harmonic currents flow in the power system as reactive power
(VAR), adding to the apparent power demand (VA). In addition to the increased apparent power demand of non
linear loads, the harmonic currents cause additional heating and stresses in the power system components due to
their higher frequencies. In some circumstances, the non linear load's harmonic currents can excite harmonic
resonances, cause undesirable system interactions, or cause misoperation of other equipment. Computers and
similar electronic loads have traditionally been nonlinear loads. While the development of switchmode power
supplies (SMPS) has been blamed for the harmonic current problems associated with computers, the earlier
"linear" power supplies also were nonlinear loads which generated similar harmonic currents but generally at
lower levels than the SMPS. It is arguable that improvements in computers which spawned the great
proliferation of singlephase, 230volt computers and electronics outside the protected environments of
traditional data processing rooms are responsible for the present industry attention to harmonics issues.
Nonetheless, there is great interest in harmonic current reduction techniques.
2. How Nonlinear Loads Create Voltage Distortion
By far the majority of the voltage distortion found in
today's distribution systems is produced by the loads
themselves, not the supply. Much of today's electrical
load is nonlinear, meaning they consume current in a
nonsinusoidal manner. Since, by definition, a non
sinusoidal waveform is composed of harmonic
currents; non linear loads are considered to be
harmonic current sources. In other words, by
consuming current in a nonsinusoidal manner, these
nonlinear loads produce harmonic currents that
circulate through the power distribution system. Most
voltage distortion is the result of the interaction of
these harmonic currents with the impedance of the
electrical distribution system. As the harmonic currents
pass through the system's impedance, they produce
voltage drops at each harmonic frequency in relation to
ohm's Law  V h = I h x Z h [Fig. 1]. The voltage drops appear as harmonic voltages and the accumulation of
these voltages at all the harmonic frequencies produces the voltage distortion.
The relationship is: V
TH
= (V
2
2
+ V
3
2
+ V
4
2
+... V
h
2
)
0.5
where V
THD
=Total harmonic distortion of voltage,
V
h
=Voltage at harmonic h V
1
=Fundamental voltage. Dist ortion levels can be quite high when system
impedance is high. A fatal combination is high densities of nonlinear loads in systems with high impedance or
low fault level. This situation is common when weak sources, such as UPS system or diesel generators, are used
to service electronic equipment. The problem is magnified further when the equipment is serviced by long cable
runs.
3. Voltage distortion demonstration setup
A simple way of demonstrating the relationship between harmonic voltage drop and voltage distortion is shown
in Figure 2. The objective is to show that the harmonic voltages, as measured across a harmonic current
generating load, are primarily the result of the voltage drop developing as the harmonic current passes through
the impedance of the power distribution system. In this demonstration, the nonlinear loads chosen are 23watt
compact fluorescent lamps (CFLs). The main reasons for choosing these loads are as follows:
Their current spectrum is quite typical of that found in today's electronic loads.(see phase current in Fig. 2)
The low wattage of the lamps means that very little voltage drop is created as the harmonic currents pass
through the impedance of the system. Voltage distortion can then be artificially increased by adding a
relatively small reactor to increase system impedance. The voltage drop across this known reactance is then
used to demonstrate how the voltage distortion is the result of voltage drops at each harmonic frequency.
The system impedance is artificially increased by inserting a 5% impedance, 3phase, coretype, line reactor in
series. Since the 3phase reactor presents a very low impedance to the zero sequence harmonics (those that run
on the neutral), a similar size singlephase reactor is inserted in the neutral as well. By applying Ohm's Law as
shown in Figure 1, the voltage drops at each harmonic can be calculated. Since the inductance of the reactor (20
mH) is significantly greater than the remaining inductance in the system, the following assumptions can be made
to simplify the voltage drop calculation:
Cable, transformer and source impedances are neglected since, in comparison with the reactor impedance,
they are insignificant.
Resistance in the reactor and the overall system is negligible as well.
This simplified the
demonstration setup system
impedance as follows:
Z
h
= Z
S
+ Z
T
+ Z
C
= Z
L
,
for each harmonic frequency
and since, Z = (R
2
+X
2
)
0.5
,
neglecting resistance then, Z
h
= X
L
= 2fL, for the 5th
harmonic (where h = 5, f =
300 Hz, and L = 20 mH) the
system impedance becomes:
Z 5 = X 5 = 2fL =
2(300)(.02) = 37.7
Ohms.Applying Ohm's Law,
and using the harmonic
current as measured with a
harmonics analyzer, the 5th
harmonic voltage drop is
calculated to be: I 5 = 0.13A
V h = I h x Z h = 0.13 x 37.68
= 4.9V .The above calculations are applied to all odd harmonics from the 3rd to the 13th and the results tabulated
in the accompanying table. By comparing the calculated voltage drops with the actual measured harmonic
voltage at each harmonic, you can see that they match quite closely. This confirms the harmonic voltages (which
define voltage distortion) are primarily the result of the accumulation of harmonic voltage drops.
Harmonic
No. Hz
Current in amps
(as measured)
Line Reactor
Reactance
(ohms)
Calculated
Voltage Drop
Measured
Harmonic
Voltage
3 180 0.81 22.6 18.3 14.5
5 300 0.13 37.7 4.9 5.4
7 420 0.04 52.8 2.1 2.1
9 540 0.05 67.8 3.4 3.0
11 660 0.02 82.9 1.6 1.3
13 780 0.02 98.0 2.0 1.8
The table also shows how the voltage drop across a neutral conductor creates a high neutralground voltage,
which is a form of commonmode noise. The 20 mH singlephase reactor inserted in the neutral in the
demonstration, produces a calculated voltage drop of 18.3 volts at the 3rd harmonic. The measured value of
neutralground voltage, at 13V (see Fig. 2), approaches this calculated value. Although levels this high are not
normally found in the field, it is now fairly common to find levels above 5 volts. An example is shown in Figure
1 where the neutralground voltage at the first site was 6.6 volts.
3. Some Harmonic Mitigation Techniques
One of the most popular methods of harmonic current reduction involves the use of passive harmonic
filters. Passive harmonic filters use inductors and capacitors tuned to
block or absorb particular harmonic currents. A typical harmonic
current filter is shown in Figure 3. Harmonic filters generally require
careful application to ensure their compatibility with the power
system and all present and future nonlinear loads. Harmonic filters
tend to be relatively large and can be expensive. Often, passive filters
cannot provide optimal harmonic current reduction without unwanted
side effects such as ringing transient response, unwanted resonances,
and overcompensation. Dioderectifier loads, typical of computer
power supplies, often require very little 50 Hz power factor
correction capacitance relative to the level of harmonic currents
generated. As such, it is extremely difficult to provide a passive Figure 3. Passive Harmonic
Filter
harmonic filter that does not overcompensate at 60 Hz, causing a
leading displacement power factor.
Active harmonic filters
Active harmonic filters (see Figure 4) are becoming
commercially available. In principle, with sophisticated power
electronics, it is possible to produce a device that either provides
variable harmonic impedance to absorb some or all of the harmonic
currents generated by the non linear load(s) or provides harmonic
currents of opposite polarity to cancel the nonlinear load's harmonic
currents. To date, active filters have been very costly and are not
widely available.
DeltaWye Transformers
Fig. 4. Active Harmonic Filter
Other harmonic current reduction techniques which have been
applied to computer loads involve the use of transformers to cancel certain
harmonic currents. In threephase, fourwire power systems supplying
singlephase nonlinear loads, deltawye isolation transformers (see Figure
5) will cancel the balanced triplen harmonic currents (3rd, 9th, 15th, ...).
The triplen harmonics, being zerosequence components, add instead of
cancel in the neutral of threephase, four wire power systems and are
responsible for neutral current being greater than the phase currents, even
with balanced loading. The triplen harmonics circulate in the delta of the
transformer with only the unbalanced portion present in the Fig.5. DeltaWye Transformer
transformer input line currents.
Zigzag Grounding Filter(ZZF)
Another way to protect the step down transformer and shared neutral conductor from triplen harmonics
is to cancel them near the load.Fig.6 shows a special zigzag grounding transformer that employs a threephase
autotransformer to cancel 3
rd
or triplen harmonics.because all the triplen harmonic currents (zero sequence
currents) are added in the neutral and flowing from loadside back to sourceside neutral,the parallel connected
autotransformer can provide a zero sequence current path and cancel the triplen harmonics.The basic harmonic
cancellation principle can be understood by looking at the transformer phase voltages:
v
a1
=v
a2
= V
m1
Sin t + V
m3
Sin3t + .....
v
b1
=v
b2
= V
m1
Sin( t 120
0
) + V
m3
Sin3(t 120
0
) + .....
v
c1
=v
c2
= V
m1
Sin( t+120
0
) + V
m3
Sin3(t +120
0
) + .....
where v
a1
, v
b1
,v
c1
are the threephase primary winding voltages,and v
a2
, v
b2
, v
c2
are the secondary winding voltages.
With phase to neutral win dings split and wound on two different legs of a three legged core, each pair on a leg is
reversed in polarity as shown in Fig 6(a) .Fig 6(b) is the phasor diagram showing the vector summation of the
phase winding voltages. By this method the balanced triplen harmonic voltages are cancelled in the phase
voltages,i.e.,
v
an
= v
a1
 v
b2
= 1.732 V
m1
Sin( t+30
0
) + 0 + 1.732 V
m5
Sin(5 t30
0
) + .......
This equation shows that the triplen harmonic voltages are not present in the phase voltages,and the
triplen currents are trapped in the zigzag transformer windings. By adding more phase shifted zigzag
windings,with different phase angle and winding arrangements,the positive and negative sequence harmonic
currents such as 5
th
and 7
th
can also be cancelled.
Recently, these same techniques (multi phase power sources) have been applied to computer
mainframes and other data processing equipment to reduce harmonic current distortion. Special isolation
transformers with multiple output windings have been devised to cancel particular harmonic currents. Typical
computer system requirements of balanced voltages to ground and a common ground reference require that the
multiple outputs be multiple wye outputs with a common neutral.
A dualoutput transformer (see Figure 7) is constructed with two wye outputs having a 30degree phase
shift. The delta primary allows cancellation of the balanced triplen
harmonic currents. The 30 degree phase shift between outputs provides
cancellation of the 5th, 7th, 17th, 19th, ... harmonic currents which are
balanced between the two outputs. For maximum harmonic current
cancellation, identical nonlinear loads need to be connected to each
output. If the harmonic current content of the loads on each output is
not identical in amplitude and phase displacement relative to the
applied voltage, then less than total cancellation of the harmonic
currents is obtained. This configuration is particularly applicable to
mainframe applications where virtually identical loads can be
connected to each output. Figure 7. Dual Output Transformer.
Another multiple wyeoutput transformer configuration is a
quadoutput with the outputs phasedisplaced in 15degree increments as
shown in Figure 8. The delta primary provides cancellation of the
balanced triplen harmonic currents, while the 15 degree phaseshifts
between outputs provide cancellation of the 5th, 7th, 11th, 13th, 17th,
19th, 29th, 31st, ... harmonic currents which are balanced across the four
outputs. Again, if the harmonic current content is not identical on all four
outputs, then less than total cancellation is obtained.
Figure 8. QuadOutput Transformer.
4. KFactor Rating for Transformers
The primary effect of the power system harmonics on transformers is the additional heat generated by
the losses caused by the harmonic content of the load current. Other problems include resonance between the
transformer inductance and system capacitance,mechanical insulation stresses (winding and lamination) due to
temperature cycling and possible small core vibrations.
The additional heating caused by system harmonics requires load capability derating to remain within
the temperature rating of the transformer or use of special transformers designed for nonsinusoidal load currents.
Transformer life will be reduced as the result of operating above rated temperatures.
The primary loss components are winding losses, winding eddycurrent losses and stray losses from
electromagnetic flux in areas such as windings , core,clamp assemblies and tanks. The losses due to the I
2
R
component will be due to conductor heating and the skin effect. Losses from the winding eddycurrents will
increase with the square of load current and the square of frequency. Other stray losses will also increase with
frequency although at a power slightly less than two.
Transformers directly supplying singlephase power supplies may require deratings of 30% to 40% to
avoid overheating. Underwriters laboratory (UL) recognised the potential safety hazards associated with using
standard transformers with nonlinear loads and developed a rating system to indicate the capability of a
transformer to handle harmonic loads. The ratings are described in UL1561 and are known as transformer K
Factors. KFactor is weighting of the harmonic load currents according to their effects on transformer heating, as
derived from ANSI/IEEE C57.110. A KFactor of 1.0 indicates a linear load (no harmonics). The higher the K
Factor, the greater the harmonic heating effects:
KFactor = (i
h
)
2
h
2
,where I
h
is the load current at harmonic h, expressed in a perunit basis such that the total
RMS current equals one amp, i.e., (i
h
)
2
=1.0
One problem associated with calculating KFactor is selecting the range of harmonic frequencies that
should be included. Some use up to the 15th harmonic, others the 25th harmonic, and still others include up to
the 50th harmonic. For the same load, each of these calculations can yield significantly different KFactors
because even very small current levels associated with the higher harmonics, when multiplied by the harmonic
number squared (e.g., 50
2
= 2500), can add significantly to the KFactor. Based on the underlying assumptions
of C57.110, it seems reasonable to limit the KFactor calcul ation to harmonic currents less than the 25th
harmonic. Sample calculations are shown in the table below.
KFactor Calculation for a Typical Nonlinear Load
h (harmonic number)
I
h
(nonlinear load
current)
(I
h
)
2
i
h
= (I
h
)/( (I
h
)
2
)
1/2
(i
h
)
2
(i
h
)
2
h
2
1 100.0% 1.000 0.792 0.626 0.626
3 65.7 0.432 0.520 0.270 2.434
5 37.7 0.142 0.298 0.089 2.226
7 12.7 0.016 0.101 0.010 0.495
9 4.4 0.002 0.035 0.001 0.098
11 5.3 0.003 0.042 0.002 0.213
13 2.5 0.001 0.020 0.000 0.066
15 1.9 0.000 0.015 0.000 0.051
17 1.8 0.000 0.014 0.000 0.059
19 1.1 0.000 0.009 0.000 0.027
21 0.6 0.000 0.005 0.000 0.010
23 0.8 0.000 0.006 0.000 0.021
25 0.4 0.000 0.003 0.000 0.006
Total 1.596 1.00 6.33
In establishing standard transformer KFactor ratings, UL chose ratings of 1, 4, 9, 13, 20, 30, 40, and
50. From a practical viewpoint, individual loads with KFactors greater than 20 are infrequent at best. Office
areas with some nonlinear loads and large computer rooms normally have observed KFactors of 4 to 9. Areas
with high concentrations of singlephase computers and terminals have observed KFactors of 13 to 17.
When multiple nonlinear loads are powered from the same source, lower total harmonic current levels
may be expected due to phaseshifts and cancellat ions. In one study of commercial buildings, single phase loads
with current distortions of 104% THD (total harmonic distortion) resulted in only a 7% THD at the service
entrance when added with other loads in the building. Additional studies of typical loads are beginning to
provide information that should aid in the development of additional rules ofthumb to use when direct load
measurements are not available.
KFactor transformers are designed to be operated fully loaded with any harmonic load having a K
Factor equal to or less than its KRating. For example, a K13 transformer can be fully loaded with any harmonic
load having a KFactor up to K13. If the load has a KFactor greater than 13, then the transformer cannot be
safely operated at full load and would require derating.
KFactor transformers differ from standard transformers. They have additional thermal capacity to
tolerate the heating effects of the harmonic currents. Beyond that, welldesigned KFactor transformers will also
minimise the winding eddy current losses through the use of parallel conductors and other winding techniques.
The KFactor indicates the multiple of the 50 Hz winding eddy current losses that the transformer can safely
dissipate: Transformer load losses consist of winding I
2
R losses plus stray losses. Using UL1561 test methods,
stray losses are assumed to be primarily winding eddy current losses for transformers 300 kVA and smaller. For
example, a transformer having winding I
2
R losses of 2000 watts and 50 Hz stray losses of 100 watts would, with
a K20 rating, be required to dissipate the 2000 watts of I
2
R losses plus 20 times the 50 Hz stray losses of 100
watts for a total load loss of 4000 watts without exceeding the maximum winding temperature rise. The result is
a larger, more expensive transformer.
For KFactor transformers, UL also requires that the neutral terminal and connections be sized to
accommodate twice the rated phase conductor size (double the minimum neutral capacity) of standard
transformers. Standard transformers, i.e., those not marked with a KFactor rating, may have some tolerance to
nonlinear loading, but their capability is unknown to the user and is not certified by a third party such as UL.
Currently, marking a transformer with a KFactor rating is not required by UL. Due to a conservative design or
application, some unmarked transformers may therefore have enough extra thermal capacity to tolerate
additional harmonic load heating. This is particularly true for 80
0
C; or 115
0
C; rise transformers built with 220
0
C
insulation materials which can safely withstand a 150
0
C winding temperature rise.
Additional overcurrent protection should be considered for all transformers supplying nonlinear loads.
The National Electrical Code allows primaryonly overcurrent protection at 125% of the transformer's primary
full load amps. With threephase transformers, the triplen harmonics are cancelled in the delta winding and do
not appear in the input current. The output current and transformer loading is greater than is apparent from the
input current. Therefore, the transformer can be overloaded without the primary over current protection ever
tripping. Adding transformer secondary overcurrent protection helps, but it still does not protect the transformer
from the heating effects of harmonic currents. The use of supplemental protection in the form of winding
temperature sensors can be used to provide alarm and/or system shutdown in case of overload, excessive
harmonic current, high ambient temperature, or inadequate cooling.
The use of derated standard transformers instead of KFactor transformers carries some disadvantages.
First is the issue of managing the derating when the transformer nameplate indicates greater capacity. Initially,
the transformer may be operated at the reduced loading, but in the future, the loading may be increased without
considering the intended derating. Second, if smaller overcurrent protection is used to intentionally limit the
loading, nuisance tripping may occur due to the transformer inrush current. Larger overcurrent protection may
be required for the oversized (derated) standard transformer resulting in larger conductor requirements with the
associated higher feeder costs. Third, transformers designed specifically for nonlinear loads minimise losses due
to the harmonic currents. They operate with the nonlinear loads more efficiently and generate less heat that
needs to be dissipated.
Because transformers are the power system component most affected by non linear loads, they were the
first to receive a harmonics capability rating system. KFactor ratings are based on the heating effects of
harmonics and are not necessarily applicable to other power system components. If harmonic rating systems for
other components are needed, they will have to be developed by other methods, e.g., THD, crest factor, or some
new and component specific weighting of harmonic currents.
4. Magnetic
Synthesiser for
Power Quality
Conditioning
One of the most successful
threephase power
conditioning products of the
last 15 years is a unique
product based on a three
phase ferroresonant circuit,
known as a magnetic
synthesiser .The schematic
diagram of the first
generation magnetic
synthesiser is shown in Figure
9. Fig.9 Magnetic Synthesiser Schematic Diagram
A simplified block diagram of the magnetic synthesiser is shown in Figure 10. The heart of the
magnetic synthesiser is the pulse transformer network, which consists of six interconnected saturating pulse
transformers whose outputs are combined to produce the output sine waves in a manner similar to that of a step
wave inverter. The pulse of each saturating transformer is determined by the construction of the transformer
(core geometry and windings), which establishes the available volt seconds. The magnetic synthesiser pulse
transformers are designed to saturate in 1/12th of the fundamental period. At any instant in time, five of the six
pulse transformers are in saturation. When one transformer core saturates, the transformer's impedance switches
from a higher impedance state to a lower impedance state which causes a reversal of voltage on another
transformer. This natural
saturation sequence is
depicted in Figure 11. The
numbers inside of the pulses
refer to the saturating
transformer winding (shown
in the magnetic synthesiser
schematic of Figure 9) that
produced it. For example,
pulse 3B is produced by the
"B" winding of the TX3. Figure 10. Magnetic Sy nthesiser Block Diagram
To see how the interconnec
ted transformer windings produce the sinewave output, trace the path through the saturating transformer
windings for any output phase voltage.
For example, to produce the output voltage between phases A and B, the path is through the windings
of TX4, TX1A, TX2B, TX3B, TX2A, and TX5, which are the same pulses shown to produce output voltage
phase AB in Figure 11. The pulse heights correspond to the sinewave function: that is, sine 30 is 0.5 times the
peak, sine 60 is 0.866 times the peak, sine 90 is 1.0 times the peak, etc. For a sinewave output, the pulse heights
of each winding of TX1, TX2, and TX3 are 0.5 times the desired peak output voltage whereas the pulse heights
of TX4, TX5, and TX6 are 0.866 times the desired peak output voltage. The resulting output voltage waveform
contains less than 4% total harmonic distortion.
Ferroresonance is used to ensure that the saturating pulse transformer cores go into hard saturation for a
broad range of input voltage conditions. Energy oscillates between the main capacitor bank (C1) and the pulse
transformer cores (TX1 to TX6). Unlike singlephase ferroresonant circuits, the value of the capacitance is not a
critical factor to determine the output voltage. The amount of capacitance is based on a minimum energy storage
capability to ensure saturation of six cores. As a matter of practical design, multiple parallelconnected
capacitors are used. An additional 10 to 20% capacitance is included in the unit for redundancy, which allows for
some capacitor failures without affecting unit performance.
Three nonlinear chokes (TX7, TX8,
TX9) are used to isolate the pulse transformer,
waveform synthesising network from the utility
source. The variable impedance of the non
linear chokes allows the regulated pulse
transformer network to operate at a voltage
level different from the input voltage source.
The variable impedance of the chokes
essentially converts the variable voltage utility
source into a current source which drives the
saturating pulse transformer network. The
frequency of the input power source is relied
upon to drive the saturation sequence timing
and thus determines the output voltage
frequency. Because the saturating pulse
transformer network is based on constant volt
second pulse areas, changing the input
frequency (which alters the "seconds") has a
direct effect on the output voltage level.
For example, reducing the input frequency by
1% causes the output frequency to be reduced
by 1% and the output voltage to be reduced by
about 1.2%. However, from a practical point of
view, any reasonable variations in frequency,
even on standby generator operation, are less
than +/3 Hz, which results in an output voltage Fig.11 Output Waveform Synthesis
variation of only 6%.
The output of the pulse transformer network is a regulated threephase voltage. A zigzag (grounding)
transformer (TX10) is used to derive the output neutral. The zigzag transformer is so named because of the
vector representat ion of the transformer windings that "zig" and "zag." Two equal windings on each phase are
interconnected such that the impedance of the transformer from phase to phase is high while the impedance from
the derived neutral to any phase is very low. The neut ral is used for grounding purposes and to supply output
linet oneutral loads. The pulse transformers have isolated primary and secondary windings with multiple
electrostatic shields between them to provide electrical isolation and common mode noise reject ion. The
synthesiser derives a neutral and maintains the input tooutput electrical isolation of a separately derived system
as defined by the National Electrical Code. The electrical isolation is maintained even when the unit is equipped
with an optional bypass circuit because a 4pole switch is used to switch the phase and neutral conductors.
The remaining magnetic elements (TX11 to TX16) of the magnetic synthesiser are connected with
capacitor banks C2 and C3 to form two sets of threephase seriesresonant filters (harmonic traps). One set is
tuned to filter the 2nd harmonic and the other is tuned to filter the 3rd harmonic. These traps are not used, as may
be expected, to filter the output voltage waveform under normal operation. Under normal operation, the
synthesised sinewave output voltage waveform (see Figure 5) does not contain any significant levels of 2nd or
3rd harmonic voltages. The lowest significant harmonic voltage in the synthesised output voltage waveform is
the 11th harmonic. However, at startup, before the saturation sequence is established, the harmonic traps are
needed to force the synthesiser into the desired saturation sequence. It was determined (and disclosed as part of
the first patent) that any saturation sequence other than the desired sinewave saturation sequence contained
significant levels of either the 2nd or 3rd harmonic frequency. By suppressing these harmonics, the synthesiser is
forced to start up with a sinewave output.
==============
MOTOR PROTECTION AGAINST dv/dt EFFECTS IN ADJUSTABLE SPEED DRIVES
Suresh Kumar.K.S
Asst.Professor,Dept.of Elect. Engg.,
R.E.C.,Calicut
1. Introduction
The evolution of power semiconductors has been so dramatic that today an insulated gate bipolar
transistor (IGBT) can be turned on in just 0. 1 micro second. This results in the voltage rising from zero to peak
in only onetenth of a microsecond. Unfortunately, there are many motors in existence that do not have sufficient
insulation to operate under these conditions.
High Peak Voltages can be experienced at the motor terminals especially when the distance between the
inverter (drive) and the motor exceeds about 15 meters. This is typically caused by the voltage doubling
phenomenon of a transmission line having unequal line and load impedance's. Motor terminal voltage can reach
twice the DC bus voltage in long lead applications. When the characteristic load impedance is greater than the
line impedance, then voltage (and current) is reflected from the load back toward the source (inverter). The
absolute peak voltage is equal to the sum of the incident peak voltage traveling toward the motor plus the
reflected peak voltage. If the load characteristic impedance is greater than the characteristic line impedance, then
the highest peak voltage will be experienced at the load (motor) terminal. If the DC bus voltage is 850 volts, then
motor terminal voltage could reach 1700 volts peak.
Fast Voltage Rise Times of 1600 volts per microsecond can be typical as the motor lead length exceeds
just a few hundred feet. Voltage rise time is referred to as dv/dt(change in voltage versus change in time). When
the rise time is very fast the motor insulation system becomes stressed. Excessively high dv/dt can cause
premature breakdown of standard motor insulation. Inverter duty motors typically have more phasetophase and
slot insulation than standard duty motors (NEMA design B).
When motors fail due to insulation stress caused by high peak voltage and fast voltage rise times (high
dv/dt) they have common symptoms. Most failures of these types occur in the first turn as either a phaseto
phase short or phase to stator short. The highest voltage is seen by the first turn of the winding and due to motor
inductance and winding capacitance of the motor, the peak voltage and dv/dt decay rapidly as the voltage travels
through the winding. Normally, the turn to turn voltage in a motor is quite low because there are many turns in
the winding. However, when the dv/dt is very high the volt age gradient between turns and between phase
windings can be excessively high, resulting in premature breakdown of the motor insulation system and
ultimately motor failure. This problem is most prevalent on higher system voltages (480 & 600 volts) because
the peak terminal voltage experienced often exceeds the insulation breakdown voltage rating of the motor.
Standard Motor Capabilities established by the National Electrical Manufacturers Association
(NEMA)and expressed in the MG I standard (part 30), indicate that standard NEMA type B motors can
withstand 1000 volts peak at a minimum rise time of 2 usec (microseconds). Therefore to protect standard
NEMA Design B motors, one should limit peak voltage to 1KVand reduce the voltage rise to less than 500 volts
per microsecond.
The phenomenon of reflection of electromagnetic (em) waves on an electric conductor is very similar to a
wave in water. At a given point, the magnitude of the water wave varies with time and its phase is retarded. As
one moves away from the origin of the wave, the amplitude diminishes and eventually subsides. However, if
there exists a barrier to the movement of the waves, there is reflection. Consequently, the amplitude of
oscillation at a given point is the sum of the incident and the reflected wave at that point. Similar results are
observed when em wave travels on a transmission line. If a load on a transmission line is physically at infinite
distance from the source, there exists no reflection  similar to a water wave originating in a pond with boundary
at infinity. One can electrically create an infinite transmission line (a line having no reflection) if the surge
impedance at the terminating end matches the cable surge impedance. However, in most cases the motor and
cable surge impedances are mismatched which causes voltage reflections; Voltage reflection further causes
voltage amplification at the motor terminals since usually the motor and the ASD are physically separated by
long lead lengths.
2. Long Transmission Line Theory as Applied to MotorASD Case
Let the voltage at any given point which is x meters away from the load end, be denoted by V
x
. This
voltage is the sum of incident and reflected waves at that point. Let the incident wave be denoted as v
+
and the
reflected wave be denoted as v

. V
x
is given by:
V
x
= v
+
+ v

(1)
Referring to Figure 1, the following is evident:
The incident wave, v
+
, is equal to the sum of the receiving end voltage and the drop across the surge impedance
of the cable. Similarly, the reflected wave, v

, is equal to the difference between the receiving end voltage and the
drop across the surge impedance. From these observations, one can rewrite the voltage at any given point on the
transmission line as follows:
V
x
= ((V
R
+I
R
Z
C
)e
ax
e
jbx
+ (V
R
I
R
Z
C
)e
ax
e
jbx
) / 2 (2)
V
x
is voltage at a point x units away from the receiving end;
V
R
is voltage at receiving end;
I
R
is current at receiving end;
Z
c
is characteristic impedance of line; = L/C;
L is phase inductance per unit length;
C is line ground capacitance per unit length;
The exponential terms are used in equation (2) to help explain the variations of the voltage waveform as a
function of the distance along the line. The first term in equation (2) denotes the "Incident" wave while the latter
term in equation (2) denotes the "Reflected" wave. Based on equation (2), the following points are worth noting:
(a) x is zero at the receiving end and increases as one moves away from the receiving end toward the point of
interest on the transmission line. On moving away from the receiving end (for increasing values of x), the
incident wave increases in magnitude and advances in phase;
(b) On moving away from the receiving end (for increasing values of x), the reflected wave diminishes in
magnitude and retards in phase;
(c) If the terminating point is at infinite distance from the point of interest (i.e., x is at infinity), then there exists
no reflected wave;
(d) If the terminating impedance is equal to the characteristic impedance, i.e., Z
R
= Z
C
, there exists no reflected
wave. A line terminated in its characteristic impedance is known as a flat line or an infinite line.
Bundled conductor lines have lower values of Z
C
as they have lower L and higher C than lines with single
conductors per phase;
(e) From equation (2), it is interesting to note that under no load conditions, I
R
= 0. This results in the incident
wave to be equal and in phase with the reflected wave at the point of termination, i.e., at x = 0. Hence, the actual
voltage at the point of termination that is given by equation (1), equa ls 2 times the incident voltage wave. This
shows the voltage doubling effect under open or no load conditions;
2.1 Coefficient of Reflection
As explained earlier, any em wave traveling on an electrical conductor exhibits the phenomenon of reflection,
exception being an infinite transmission line or a line terminated in its characteristic impedance. Referring to
Figure 1, the value of the terminating impedance, Z
R
, is given by the ratio of the voltage and current at the point
of termination. The voltage and current components are made up of the incident and reflected waves.
Mathematically, this can be represented as:
Z
R
= (v
R
+
+v
R

)/( i
R
+
+i
R

) (3)
ZR is the terminating impedance;
vR
+
is the incident voltage wave at termination;
v
R

is the reflected voltage wave at termination;
i
R
+
is the incident current wave at termination;
i
R

is the reflected current wave at termination;
Further, the incident and reflected current components can be expressed as:
i
R
+
= v
R
+
/Z
C
(4)
i
R

= v
R

/Z
C
(5)
Substituting for i
R
+
and i
R

in equation for Z
R
:
v
R

= ((Z
R
Z
C
)/(Z
R
+Z
C
))v
R
+
(6)
The ratio of the reflected wave to the incident wave is known as the "coefficient of reflection" and is denoted as
PR
at receiving end. For voltage, the coefficient is:
R
= (Z
R
Z
C
)/(Z
R
+Z
C
) = v
R

/ v
R
+
(7)
The reflection phenomenon exists at the sending end as well. The coefficient of reflection at the sending end is
denoted by PS. For voltage, the coefficient is:
S = (ZSZC)/(ZS+ZC) = vS

/ vS
+
(8)
From equations (7) and (8), a few interesting remarks can be made:
(a) If at point of termination there is a short circuit, then Z
R
= 0; and
PR
= 1; v
R

= v
R
+
and so the sum of reflected
and incident voltages at the point of termination is Zero, i.e.,
(v
R

+ v
R
+
= 0);
(b) If the point of termination is an open circuit, then Z
R
= ,
PR
=1; and so the sum of reflected and incident
voltages at point of termination is 2v
R
+
;
(c) If at the point of termination, Z
R
= Z
C
, then there exists no reflection since
PR
= 0;
(d) Mismatched impedance causes overvoltage when Z
R
>> Z
C
and
PR
approaches a value of Unity; If Z
R
<< Z
C
,
then
PR
is negative, and reflection exists but it does not result in voltage amplification at termination;
(e) As mentioned earlier, coefficient of reflection for Source (
PS
) exists as well. Typically, source impedance Z
S
,
is Zero and hence,
PS
is approximately 1. Note that under ideal conditions, the rms value of sending end voltage
does not change from its nominal value;
Applying the above theories to the case of a motor being fed via an ASD, one can come to a few
interesting conclusions. The mismatch between cable and motor surge impedance is the highest for small motors;
Also, in all cases, the coefficient of reflection is positive, which means that there always exists amplification of
the voltage at the motor terminals. Typical motor and cable surge impedances in ohms for popular sizes of
motors is given below.
HP ZR ZC PR
25 1500 80 0.9
50 750 70 0.83
100 375 50 0.76
200 188 40 0.65
400 94 30 0.52
Smaller Hp motors have larger inductance and less amount of slot Insulation which results in a higher surge
impedance compared to larger hp motors.
2.2 Critical Cable Length
The phenomenon of reflection occurs irrespective of the distance between the motor and the ASD
as evidenced from the discussions in the preceding paragraphs. The magnitude of the voltage at a given point on
the transmission line is a function of the distance x from the terminating point as shown by equation (2). The
worst case of reflection at the terminating point occurs under open circuit conditions. In order to estimate the
critical length at which the magnitude of the sum of the incident and reflected wave is higher than the peak value
of the incident wave, one has to know the speed of propagation of em waves on the transmission line.
If the speed of propagation of the em wave is assumed to be v and the rise time of the PWM wavefront
(defined as the time taken for the output to go from 10% to 90% of its peak value) is t
r
, then the distance
traveled by the wavefront during its rise time is simply v x t
r
. If the terminating point is at a position where the
incident wave has just reached 50% of its full value and if total reflect ion is assumed, i.e.,
PR
= 1.0, then the sum
of the incident and reflected waves will yield 100% of the peak value of the incident wave. Any distance greater
than this critical length would allow the incident wave to build up to more than 50% of its peak v alue and if total
reflection is considered, the effective wavefront at the terminating point will be greater than 1.0 p.u. Thus the
critic cable length is given by: L
CR
=( v x t
r
)/2 (9)
The speed of propagation of a wavefront over the conductor depends on the inductance and capacitances per unit
length of the conductor. Mathematically, it is given by: v = 1/(LC) m/sec (10)
Typical values for the speed of propagation, v, range from 100 to 150 m/sec. The rise time of typical IGBTs
used in ASDs range from 0.4 to 0.6 sec. Using equation (10), the critical length is calculated to vary from 20 to
45 meters.
3. Mitigation Techniques
As shown in the preceding paragraphs, most long lead length cases involving induction motors fed from
ASDS, there exists voltage amplification. This overvoltage at the motor terminals can deteriorate the insulation
system of the motor thereby causing premature motor failures. Four different techniques are discussed in this
section which help alleviate the overvoltage problem encountered by motors fed from ASDs at long distances.
These four techniques are: (i) Use of 3phase load react ors; (ii) Use of RC snubbers at the motor terminals; (iii)
Applying low pass filter section to wave shape the output from an ASD; and (iv) Isolated form of the technique
used in (iii) above.
3.1 3Phase Load Reactors
Reactors have been used for many years to solve problems in variable speed drive installations. About ten years
ago the use of line reactors started to become more common as they helped to solve typical problems on the
input (line side) of variable frequency drives (VFD) and SCR controllers. They often have been used as low cost
substitutes for 1:1 isolation transformers. The typical problems that line reactors solved were drive nuisance
tripping, voltage notch reduction (for SCR controllers) and harmonic attenuation. They were called "line
reactors" because they were always used on the "line side" or input of a variable speed drive. Attempts to use
"line reactors" on the output side of a drive tended to fail because the line reactors typically overheated due to the
harmonic content of the output waveform.
In 1989 the industry experienced the introduction of Harmonic Compensated Reactors which now offered a
product that was suitable for use on either the input or output of a variable speed drive. Harmonic compensation
meant the reactor was designed to handle the harmonic spectrum and high frequency carrier waves which are
typical on the output side of a variable speed drive. Not only are the frequencies higher, but the RMS current is
also higher whenever harmonics are present. (Example: 100%fundamental current+100% harmonic current =
141% RMS current; via Pythagorean theorem). Harmonic compensated reactors would not only handle these
conditions from a thermal perspective, but they also offered full performance and inductance in the presence of
even severe harmonics. Therefore Harmonic Compensation offered an assurance of both safety and performance.
Now that reactors could be used on the output of a VFD, many more application problems could be solved. The
most typical problems included motor temperature rise, motor noise, motor efficiency, and VFD short circuit
protection. The benefits that accrue fro use of line reactors in VFDs are listed below.
Motor Temperature Reduction
Motors operated on a VFD tend to run warmer than when they are operated on pure 50Hz, such as in an across
theline stator application. The reason is that the output waveform of the VFD is not pure 50Hz, but rather it
contains harmonics which are currents flowing at higher frequencies. The higher frequencies cause additional
watts loss and heat to be dissipated by the iron of the motor, while the higher currents cause additional watts loss
and heat to be dissipated by the copper windings of the motor. Typically the larger horsepower motors (lower
inductance motors) will experience the greatest heating when operated on a VFD.
Reactors installed on the output of a VFD will reduce the motor operating temperature by actually reducing the
harmonic content in the output waveform. A five percent impedance, harmonic compensated reactor will
typically reduce the motor temperature by 20 degrees Celsius or more. If we consider that the typical motor
insulation system has a "Ten Degree C Half Life" (Continual operation at 10 degrees C above rated temperature
results in one half expected motor life), then we can see that motor life in VFD applications can easily be
doubled. Harmonic compensated reactors are actually designed for the harmonic currents and frequencies
whereas the motor is not.
Motor Noise
Because the carrier frequency and harmoni c spectrum of many Pulse Width Modulated (PWM) drives is in the
human audible range, we can actually hear the higher frequencies in motors which are being operated by these
drives. A five percent impedance harmonic compensated reactor will virtually eliminate the higher order
harmonics (11
th
& up) and will substantially reduce the lower order harmonics (5
th
& 7
t h
). By reducing these
harmonics, the presence of higher frequencies is diminished and thus the audible noise is reduced. Depending on
motor size, load, speed, and construction the audible noise can typically be reduced from 3  6 dB when a five
percent impedance harmonic compensated reactor is installed on the output of a PWM drive. Because we
humans hear logarithmically, every 3dB cuts the noise in half to our ears. This means the motor is quieter and
the remaining noise will not travel as far.
Motor Efficiency
Because harmonic currents and frequencies cause additional watts loss in both the copper windings and the iron
of a motor, the actual mechanical ability of the motor is reduced. These watts are expended as heat instead of as
mechanical power. When a harmonic compensated reactor is added to the VFD output, harmonics are reduced,
causing motor watts loss to be reduced. The motor is able to deliver more power to the load at greater efficiency.
Utility tests conducted on VFD's with and without output reactors have documented efficiency increases of as
much as eight percent (at 75% load) when the harmonic compensated reactors were used. Even great er efficiency
improvements are realized as the load is increased.
Short Circuit Protection
When a short circuit is experienced at the motor, very often VFD transistors are damaged. Although VFD's
typically have over correct protection builtin, the short circuit current can be very severe and its rise time can be
so rapid that damage can occur before the drive circuitry can properly react. A harmonic compensated reactor
(3% impedance is typically sufficient) will provide current limiting to safer values, and will also slow down the
short circuit current rise time. The drive is allowed more time to react and to safely shut the system down. You
still have to repair the motor but you save the drive transistors.
Insulation Stress
By using a 3phase load reactor in between the motor and the ASD, one can change the characteristic impedance
of the motor or that of the source depending on where the inductor is physically placed. Typical values of
impedance used is 0.03 p.u (3% impedance). A higher value of impedance can cause a larger drop across the
inductor thereby reducing the fundamental component of the voltage at the motor terminals. This can result in
torque reduction and in some cases yield unsatisfactory operation at low speeds and high torque loads. For
centrifugal load applications, inductance of 0.05 p.u. (5% impedance) may also be used without conspicuous
deterioration in torque characteristics at practical operating points.
Adding a 3phase load reactor at the motor end will result in altering the surge impedance of the motor. The line
inductance component of the surge impedance of the motor is artificially made high which causes the overall
surge impedance of the motor to be higher than normal. The mismatch between the surge impedances of the
motor and the cable is aggravated thereby resulting in a higher coefficient of reflection and a higher voltage at
the terminating point. Since the terminating point now has the 3phase inductor first and then the motor
terminals, the overvoltage is experienced by the windings of the reactor instead of the motor. The reflected
voltage traveling along the conductor back to the sending end will have a higher amplitude because of the larger
degree of mismatch at the terminating point.
Adding a 3phase load reactor at the ASD end will result in altering the surge impedance of the cable. Typically,
the surge impedance of the cable is lower than that of the motor. By increasing the surge impedance of the cable
artificially, the coefficient of reflection is made lower which reduces the magnitude of reflected wavefront. The
reflected voltage traveling back on the conductor toward the motor is hence reduced which helps reduce the
stress on the cable.
To demonstrate the effectiveness of a load reactor connected at the drive end of the motor cable, an experiment
was performed using IGBT inverter rated 3 HP to drive a motor which was located a distance of 750 feet from
the drive. Figure 2.1 illustrates the actual voltage waveform experienced at the motor terminals without any
mitigation device in use. Notice however, Figure 2.2 illustrates the same motor /drive combination only now a
load reactor (5 percent impedance) was added at the drive terminals and the motor was now moved to a distance
of 1000 feet.
No reactor
Motor at 750 feet
(200 Volts per division)
With 5% Impedance reactor
Motor at 1000 feet
(200 Volts per division)
Fig. 2.1
Fig. 2.2
Recommended percent impedance for typical applications :
3% Current surge protection
3% Voltage transient protection
3% Drive nuisance tripping
3% Voltage notch reduction (SCR's)
3% Capacitor switching spike protection
3% Motor short circuit protection
3% Multiple motor applications
5% Harmonic reduction
5% Motor temperature reduction
5% Motor noise reduction
5% Motor efficiency improvement
5% IGBT w/ long lead lengths
3.2 RC Snubbers
The RC snubber is the simplest and lowest cost of methods employed. In its simplest form it
consists of resistors and capacitors configured as shown in Fig. 3.1. The RC snubber is typically installed at the
motor terminals and acts as an impedance matching network. The snubber components are carefully selected to
cause the load impedance to match the characteristic impedance of the motor cables. When the motor surge
impedance is equal to the line characteristic impedance, then voltage reflection does not occur and excessive
voltage will not be experienced at the motor terminals.
Figure 3.1
Using the same drive/motor combination as above with the motor 1000 feet from the inverter, the
performance of the basic snubber network in Figure 3.3 was satisfactory. Of course Figure 3.2 repeats the
waveform for the motor voltage without any mitigating device when the motor is 750 feet from the inverter.
Motor Voltage (750 ft.)
(200 Volts per division)
Fig. 3.2
w/RC Snubber Network
Motor at 1000 feet
(200 Volts per division)
Fig. 3.3
The snubber network will also extend the voltage rise time to several microseconds while clamping
the peak voltage. As shown in Fig. 3.3 the snubber circuit (or impedance matching network) can effectively
minimize motor terminal voltage spikes and offer very good protection for the motor. Snubber networks must be
located at the motor terminals as they are a cable terminating device. In some cases it may be necessary to match
the snubber impedance to the actual line impedance in order to maximize its effect.
3.3 LC Filter
The LC filter combines a load reactor and acapacitor network to form a low pass filter as illustrated in
Figure 4.1 . The basic concept is that the filter network has a resonant frequency of approximately 1 to 1.5 kHz
and frequencies higher than that will be absorbed by the filter and not passed on to the motor. Of course it is
important that the inverter switching frequency be set to about 1kHz higher than this resonant frequency to
prevent excessive filter current and drive malfunction. In fact, it has been found that the performance of this
basic LC filter network, while very good at 2.0 or 2.5 kHz, actually improves as the switching frequency is
increased.
Figure 4. 1
The beauty of this filter, as one can see in Figure 4.3 is that the motor sees a voltage waveform that is nearly
sinusoidal. Figure 4.2 shows our original waveform while the motor was connected 750 feet away from the
inverter. Look at Figure 4.2 now to see the actual motor voltage waveform, using the LC filter, and with the
motor reconnected at 1000 feet distance from the inverter.
No FIlter, Motor at 750 feet
(200 Volts per division)
w/LC Filter
Motor at 1000 feet (200 Volts per division)
Fig. 4.2
Fig. 4.3
As the capacitor requirement (for tuning purposes) becomes greater, it is practical to add a damping resistor in
series with the capacitor network. An alternative to this however, is the LC filter with isolated capacitors.
3.4 LC Filter with Isolated Capacitor:
This network follows the same basic principles the basic LC filter except it utilizes an isolation
transformer to feed the capacitors. Large values of capacitance can be used because the transformer ratio reduces
the capacitor current on the transformer primary side. We get the full effect of the capacitor in conjunction with
the series inductor, while minimizing the capacitor current and capacitive reactance as seen by the inverter
output circuit. The transformer impedance offers the damping which is desirable for large values of capacitance.
The transformer also offers some inductance which allows the use of a lower inductance value of series reactor
thereby reducing the voltage drop and improving motor torque.
The waveforms accomplished with this isolated capacitor technique are quite similar to the waveforms
captured with the basic LC filter as the concept is the same. Overall system performance is optimized with this
filter network because a sinusoidal waveform is provided for the motor while voltage drop is minimized. Motor
life is extended due to the improved waveform.
(Note This lecture note was compiled from material found in various Web sites of firms dealing with ASDs and
Line Reactors in the Internet.The Web Site http://www.mte.comis acknowledged in particular.)
ACTIVE POWER FACTOR CORRECTION IN ACDC CONVERTERES I
Surersh Kumar.K.S
Asst.Professor,Dept. of Elect.Engg
R.E.C,Calicu t
1. Introduction
Single Phase and Three Phase controlled and uncontrolled rectifiers form a major source of
current harmonics in the power distribution system. Single Phase Rectifiers are usually of low capacity;however
they are used in a large number and in a variety of equipment and hence pose a more serious harmonic threat at
the 440V and 11kV power distribution system levels. In addition ,the current harmonics injected by them into
the power distribution system is more detrimental due to the predominant triplen harmonic content in them. The
figure below shows a Single Phase rectifier supplying an SMPS load and the supply line current drawn by it.
This line current is dominated by third harmonic(to the extent of 130% usually) and results in noticeable sag at
the peak of line volts.
Fig. 1 A conventional diode bridge feeding a SMPS load
Fig. 2 Waveforms of the Circuit
A large number of such Single Phase Rectifier loads in a distribution system results in serious
overloading of neutral conductor due to addition of triplen harmonic content in the neutral conductor.Triplen
harmonic content drawn by all the uncontrolled rectifiers will be more or less in phase and hence possibility of
cancellation due to phase difference does not exist. Thus, triplen harmonic content in neutral conductor will be
sum of triplen harmonic content of all the uncontrolled rectifiers in the three phase of the distribution system
(irrespective of whether the rectifier loads are balanced among the Three Phases or not).
Use of Power Electronics in a variety of office/house hold/commercial/industrial equipment
has resulted in widespread incidence of uncontrolled rectifier loads in LT and HT power distribution systems in
the recent years. This coupled with stringent international standards on permissible harmonic injection levels has
resulted in the development of Active Power Factor Corrected designs for Single Phase and Three Phase AC
DC Converters.
Various passive correction schemes aimed at improving the power factor and THD(Total
Harmonic Distortion) of Single Phase uncontrolled rectifiers at low power levels (typically less than 50W) are in
use ;especially in electronic ballast for Fluorescent Lamps and CFLs. However, Active PFC is preferred at power
levels above 50W.This twopart lecture dwells on Active PFC using Boost Conversion technique in Single Phase
context. The principles, control strategies,design considerations etc. will remain applicable for Three Phase
systems too. However, all explanations will be with reference to Single Phase units for the sake simplicity. First
part of the lecture will deal with the most common Active PFC topology viz. Single Switch Boost Type
PFC(SSBPFC) and the second part will cover the Bilateral ACDC Converter based PFC(BCPFC).
2. Single Phase Boost Type PWM Rectifier
A simplified schematic of a Single Phase Boost Type PWM Rectifier is shown below. The a.c
line is full wave rectified using a conventional diode rectifier and the rectified output is applied to the boost
converter stage which is controlled to maintain a constant DC Voltage across the output capacitor against
variations in dc side load and ac side voltage.
The Principle
Assume that by a suitable starting control strategy a DC side voltage Vo (which should be greater than the
maximum of line i.e. Vm for proper operation of this converter) has been created. Now,if the switch Q is kept on
,the current in the inductor L increases from whatever
it was at the instant of switch closure. Hence, it is
possible to increase the current in L by closing the
switch. And,if the switch Q is opened ,whatever current
that was flowing in the inductor at the instant of
opening the switch will force itself into Co through the
diode D since current in an inductor can not be broken
instantaneously in a system which is devoid of impulse
voltages. But then ,if D conducts the voltage across L
changes polarity(because Vo is assumed to be more
than even Vm) and hence current in it decreases from
its initial value. Thus, it is possible to increase the
current in L by closing Q and to decrease the current in Fig .3 A Single Switch Boost Type PFC
L by opening the switch Q.If it is possible to raise or
lower the inductor current by controlling Q ,it follows that it must be possible to make the inductor current track
a prespecified wave shape by suitably controlling the swit ch on/off periods.Using this strategy, the current in L
in this converter is made to follow a Full Wave Rectified wave shape. If the current in L is full wave rectified in
shape, the line current in the a.c side will be pure sinusoidal and in phase with supply voltage due to the
modulation process involved in the bridge rectifier. This is the principle of operation of boost type single phase
PFC circuit.
The Control Loops
The ideal control requirements of the PFC circuit under steady state are (i) maintain a pure
D.C. output voltage of constant value and (ii) maintain input current wave shape as pure sinusoidal at u.p.f i.e.
essentially emulate a resistor in the a.c side.
Under steady state the D.C. side load removes energy from capacitor at constant average rate
and the capacitor voltage can be maintained constant only if the incoming power from the diode side is equal in
value to the outgoing power in the average. The D.C. side load need not be linear always and the incoming
power is anyway not constant on an instant to instant basis. Hence, even if the average powers are equal the
instantaneous values are not and the mismatch will flow into the capacitor thereby producing a.c ripple across it.
Use of a large valued capacitor will reduce this ripple to acceptable level.
It is the voltage control loop , which ensures that the input power from the a.c side is equal to
the output power demand plus losses at the specified output voltage. This loop senses the output
voltage,increases the current drawn from the line if output voltage tends to decrease from the set value and
decreases the current drawn from a.c side when output voltage tends to increase.
But the voltage control loop can not ask the PFC circuit to draw the required power at an
arbitrary current wave shape. The wave shape of line current should be pure sine at u.p.f or equivalently the
current in inductor L has to be pure full wave rectified shape. Hence, only the amplitude of this full wave
rectified shape is the free variable to be decided by the voltage control loop. There has to be another control loop
to see that the inductor current has the desired wave shape and the amplitude as commanded by the voltage
control loop. The current control loop fulfils these functions.
Thus there are two control loops the outer voltage control loop which monitors output
voltage and decides the amplitude of full wave rectified current that should flow in the boost inductor and the
inner current control loop which monitors the boost inductor current and forces it to track the desired wave shape
with an amplitude decided by the outer loop.
3. Current Control Strategies
Different control strategies exist for the control of wave shape of boost inductor current. They
can be broadly classified into discontinuous conduction methods and continuous conduction methods. In
discontinuous conduction strategies, the inductor current ramps down to zero every time the switch is kept off. It
is switched on again only after inductor current touches zero or remains at zero for some time. In the continuous
conduction methods, the inductor current remains above zero always. Two popular discontinuous methods and
two continuous methods are detailed below.
3.1 Controlled ON time Zero Current Switching Technique
In this scheme, the voltage control
loop controls the ON period of the switch direcly. The
voltage control loop senses the output
voltage,compares it with the set reference level,forms
the processed error signal and converts this error signal
into a proportional pulse widt h. The width of this pulse
decides the ON time of the boost switch in a switching
period and will remain constant under steady state.
During the OFF period of the switch the inductor
current ramps down and is allowed to go to zero. The
current zero is sens ed (using a current sense resistor)
and the switch is switched ON when the current
touches zero.
Fig.4 Boost Inductor Current and Switch Control Signals
Thus in every switch cycle the inductor starts at zero current ,ramps up linearly to a peak value
proportional to the value of a.c voltage at that time(since ON period is kept constant in all switch cycles),and
then ramps down to zero linearly. Hence over a switching period the inductor current will be a triangle with a
peak value proportional to the a.c voltage value. The average current in L during one switching period is the
average of this triangle and is equal to half the peak value ,and hence, is proportional to a.c voltage value. Thus,
the inductor current average will have sinusoidal shap e. Strictly speaking , there is no current control loop in this
scheme and control of current wave shape is implicitly done. The inductor current waveform and the switch
control signal are illustrated in the figure above.
The advantages of this scheme are simplicity of control,absence of diode reverse recovery
related problems etc. But the peak switch current and diode current will be twice the required line current and
will be excessive at low line voltage conditions. This increases the current stresses in the Switch(usually
MOSFETs or IGBTs) and diodes. The switching ripple content in the inductor current is almost as large as the
required average current and this calls for large filter components in the line side to smooth the line current and
for RFI filtering. These considerations limit the applicability of this strategy to low power applications typically
under 300W.
The Power Factor Controller IC UC 3852 ,brought out by Unitrode Corporation,is tailor made
to implement this control strategy. This IC also permits implementation of feed forward control of switch ON
time to achieve fast control against line voltage variations.
3.2 Peak Current Sensing Zero Current Switching Technique
This technique is similar to the technique described above and is a discontinuous current
control scheme. The above scheme suffers from inaccuracies in the waveform shape control due to host of
factors like quality of inductor winding ,switching times of switch and diode and their variation with load and
voltage ,errors in volt age to pulse width conversion etc. 'Peak Current Sensing Zero Current Switching'
technique results in better control of current wave shape and results in lower THD.
The two control loopsvoltage control loop and current control loop are explicitly pre sent in
this scheme. The voltage control loop monitors the output voltage and outputs the reference current, which
should flow in the boost inductor. This current will have the full wave rectified shape and an amplitude suitable
for meeting the power balance requirement and it becomes the input into the current control loop. The current
control loop keeps the Switch ON until the Switch Current reaches a level equal to twice reference current at
that instant. At that point Switch is opened and inductor current is allowed to ramp down to zero. The zero
current condition is sensed and the Switch is allowed to go ON at that instant. Hence the average inductor
current in a switching cycle follows the reference current waveform (which is full wave rectified in shape).In
fact the inductor current wave shape and switch control signal will be identical for both the above schemes if all
the components are ideal. The zero current sensing can be done either by resistive current sensing in the inductor
path or by sensing the sudden change in polarity of inductor voltage when the diode stops conducting. This is
done by a secondary winding of suitable turns in the inductor. This method is preferred since another current
sensing (switch current )is already involved for detecting the peak current condition. The switch current is
sensed either by a resistor in series with the switch or by a current transformer in the switch line.
Both the current control schemes suffer from (i) high peak currents in the devices (ii) excessive
switching ripple making ripple and RFI filtering more difficult (iii) excessive EMI levels due to large range
current changes involved and (iv) switching frequency which varies with line voltage waveform and magnitude
and with load. The variable swit ching frequency makes it still more difficult to design suitable RFI filters.
Peak Current Sensing Zero Current Switching method has been made popular by a tailor
made power factor controller IC from Motorola MC34262.This IC makes it very easy to implement this
control strategy with a few external components. It employs resistive Switch current sensing and secondary
winding on boost inductor for current zero sensing. The D.C. supply needed for the IC is also derived from the
secondary winding. The IC also offers some protection features. This control strategy, implemented with the
help of MC34262, will be the most economical choice for the power range 50W500W.Above 500W it becomes
difficult to maintain good efficiency ,esp. at low input voltage levels . And RFI filtering becomes very difficult.
3.3 Hysterisis Current Control
This is a continuous current ,variable switching frequency current control scheme. The boost
inductor current is continuously compared with the reference current waveform ( which is obtained from the
voltage control loop ) and the error signal after amplification is fed into a Hysterisis Comparator. When the
actual inductor current goes above the reference current by the comparator hysterisis band the comparator
changes state. This state change is used to switch off the boost switch and the current ramps down. When the
inductor current goes below the reference current by camparator hysterisis band it changes state again and this
state change is used to turn the boost switch on. Thus, the inductor current is always maintained within t V
where 2 V is the total hysterisis band.
The ripple content in the inductor current can be reduced by decreasing the hysterisis band and
that will result in higher switching frequency. The switching frequency varies as function of instantaneous value
of input voltage and also with the D.C. side load. The ripple content in the inductor current is not timeposition
dependent since the hysterisis band is constant. This results in a very high attenuation requirement in the ripple
filter in the line side to avoid distortion near zero crossing of current waveform. Also, the ripple content in the
inductor current is independent of load and hence filtering requirements will be stringent at low load conditions.
Ripple filtering is made more difficult by the varying nature of the switching frequency. This is the most
important disadvantage of this scheme. Variable hysterisis band,error triangularisation etc are techniques that
have been proposed to overcome the switching frequency variation in the hysterisis control scheme. However
incorporating such techniques will offset the advantage obtained by opting for hysterisis control i.e. simplicity
of control is compromised.
The figures below show the simulated line current waveforms and switch control waveforms
for a 1kW PFC employing hysterisis current control ,working from 230V supply ,at two load levels. The RFI
Filter was removed in the simulation to show the hysterisis action in the current. It may be seen that at full load
the averaged line current is a close approximation to a sine wave whereas at 25% load the averaged current is
distorted. This is due to the inability of inductor to follow the reference current at zero crossing due to large
value of hysterisis band used in the simulation. The value of inductance used in the simulation was high at 25mH
and was intentionally made high to reduce switching frequency. However with a non zero value of inductance
some distortion at zero crossing in the current waveform is inevitable .The amount of distortion depends on the
value of inductance,value of hysterisis band etc.
Fig.5 Supply Current and Switch Current Signals of a 1kW PFC employing Hysterisis Current Control
3.4 Average Current Control
This is a fixed switching frequency control strategy. The figure below shows the various
components of the control scheme. The negative input of the PWM Comparator is fed with a ramp of magnitude
Vs and frequency equal to desired switching frequency. The boost switch is kept on until the ramp voltage equals
the error amplifier output voltage Vca.The error amplifier compares the actual inductor current with the
reference current represented by a current signal Icp in the figure. The capacitor Cfz will have a value enough to
behave as short at switching frequency and hence at switching frequency the amplifier gain will be Rf/R1.This
gain has to be limited suitably;otherwise the switching ripple in inductor current getting through the error
amplifier can lead to subharmonic oscillations and instability which are well known in the context of current
mode control of SMPS circuits. The amplified inductor current downward slope at one input of the PWM
comparator must not exceed the oscillator ramp slope at the other input to avoid the instability in the current
mode control. This consideration will decide the value of Rf/R1.
With this instability removed,the control scheme is essentially a high bandwidth PI controller
which can follow the reference current(which contains only low frequency components) very accurately with
almost zero tracking error i.e. the average value(averaged over switching periods) of boost inductor current will
follow reference current with good accuracy.
The smallsignal control to output gain of the boost regulator is (RsxVo)/(VsxsL) where Vo is
the output voltage ,Vs is the ramp amplitude,Rs is the current sense resistor and sL is the Laplace impedance of
boost inductor. With the known value of Rf/R1 and the above
control to output gain , the overall current loop cross over
frequency can be estimated and the zero Rf Cfz can be located
suitably to obtain about 45 degree phase margin. The function
of Cfp is to provide zero gain at very high frequencies to
avoid maloperation due to switching noise present the sensed
current signal and it does not interfere otherwise with the
operation of the control system. This control scheme has the
advantages of excellent and fast current tracking and constant
switching frequency.
The inductor current will have a ripple band
superposed on the full wave rectified shape (as in hysterisis
control).The amount of ripple can be reduced by increasing the
switching frequency or increasing the inductance. Fig.6 Average Current Mode Control of PFC
The power factor controller IC UC 3854 manufactured by Unitrode Corporation is designed to
implement this average current mode control with the help of few external components. PFC implemented with
the help of this IC will result in a THD which is as low as 0.5%.
4. The Voltage Control Loop
Fig.7 The Boost PFC Circuit with the complete Voltage Control Loop
The voltage control loop of boost type PFC is shown in the figure above. The boost
switch,boost diode,current sensing elements,current control loop etc. are absorbed in the block called 'high
power factor switching preregulator'.This block accepts the current reference Imo as shown and delivers it as
Ichg into the capacitor node.
The boost inductor is small in value thanks to the high switching frequency used in practice.
The magnetic energy storage and its time variation can therefore be ignored in the power balance analysis. Also
as a first approximation, the converter can be taken as loss free. Then the average power delivered to the D.C.
side load should be equal to average power taken at the line input. Whatever power is drawn from the line on an
instant to instant basis must flow into the capacitor node through the diode if no power is lost in the converter
elements and no power is spent in changing the stored energy of the inductor. But instantaneous power drawn
from mains has second and higher harmonic content in addition to average content. Hence second and higher
harmonic power components flow into output capacitor and result in a predominantly second harmonic ripple
across the capacitor. The capacitor size is mainly decided by the ripple that can be tolerated at the output.
The output D.C. is sensed and compared with a set reference in the error amplifier. The
amplified error is converted into current reference waveform by multiplying it with a waveform template, which
represents the desired current wave shape in the boost inductor. This desired shape is that of full wave rectified
shape and is readily available at the output of the rectifier bridge. Hence waveform template is taken across the
bridge output via Rvac.The analog multiplier output ( usually implemented by transconductance technique)
drives the current control loop.(The role of squarer and divider will be explained soon,but if the line voltage is
steady the effect of these will be only that of a multiplication constant between multiplier output and current
control loop.)
The harmonic components of the waveform template which goes into the multiplier consists of
D.C., second harmonic and higher even harminics. The output voltage contains second harmonic ripple. If this
ripple is passed on to the output of error amplifier and to the multiplier the second and higher harmonic content
in the multiplier output get disturbed through cross products. The output ripple does not result in the production
of new harmonic components in the multiplier output,but they affect the magnitude and phase of second and
higher harmonics present in the multiplier output. It does not look full wave rectified any more. This results in
production of third harmonic components in the a.c side current through the modulation process involved in the
rectifier bridge. Hence, error amplifier should be dominant pole compensated with a bandwidth much less than
100 Hz.This of course will result in slow loop response. The capacitor across the feedback resistor in the error
amplifier effects the required ripple filtering.
Assume that the squarer and divider in the figure above were absent and the multiplier output
was given directly to the current control loop. The open loop gain from multiplier input (i.e. error amp output
point) to the output voltage for small variations at the multiplier input will be decided by the template amplitude
i.e. the Vm of line voltage and the capacitor value. Change in multiplier input results in change in line current
and power and the capacitor integrates the power change and converts it into change in output voltage. It is
basically a first order pro cess dominated by Capacitor Load Resistance time constant and the gain depends on
the value of square of Vm,the line voltage amplitude(change in power change in current x Vm).Hence the loop
gain and hence the closed loop dynamics will depend directly on square of line voltage and will vary over a
range of 1:9 for a PFC with universal input range i.e. 90V270V.If the closed loop response is adjusted to be
critically damped at 90V and full load ,it will be very much underdamped and excessively oscillatory at 270V,no
load.Conversely if the dynamics is set for critical damping at 270V,no load condition ,it will be dead slow at
90V,full load condition and will suffer from too high a transient dip in output voltage which lasts too long when
load is suddenly applied at output at 90V line condition.It is virtually impossible to maintain satisfactory
dynamic performance over a 1:3 line voltage range and 1:10 output load range.This is where the squarer and
divider come in.
The squarer produces a D.C. output which is proportional to square of Vm.The divider pre 
scales the error amplifier output by dividing it by square of Vm.This means that a fixed % change in the error
amplifier output always results in the same amount of increase in the power taken from the line,irrespective of
line voltage. Or equivalently the open loop gain has been made independent of line voltage amplitude. Now
control dynamics changes only due to load change and it is possible make the transient performance satisfactory
at least over a 1:3 load range by fixing the error amplifier gain and band width properly.
Load throw off is the most severe transient in a PFC.The output voltage rises and this rise is
registered only slowly by the feedback system due to its low bandwidth (usually between10 20 Hz,has to be
low to avoid passing on the capacitor ripple to the a.c side current as explained before) and by the time the
control loop acts the output voltage may go to a high level and cause damage to the driven load and/or PFC
itself. Also ,due to the unilateral nature of power flow in this kind of PFC,the capacitor voltage will not easily
come down having hit the ceiling onceunless there is load or considerable leakage in capacitor. The voltage
control loop can do nothing to bring down
capacitor voltage under such conditions since
power can not flow from D.C. side to a.c side.
Additional protection in the form of a fast
overvoltage detector resulting in blocking of the
switch control signal is needed to clamp over
voltage before it goes too high during startup and
load throwoff.
The power factor controller IC
UC3854 implements the voltage control loop
explained in this section fully. The Motorola IC Fig.8 Power Circuit of a Boost type PFC System MC
34262 implements the voltage control loop without
the squarer and divider part,but incorporates soft start up and over voltage protection.
5. Power Circuit Design Aspects
The power circuit components of the PFC are shown in Fig. 8.The resistance Rloss represents
the loss resistance of the boost inductor and the two inductors Ls1 and Ls2 represent the wiring
inductances.These inductances have a profound impact on the power circuit design and decide the achievable
efficiency more or less directly.The switch is usually a MOSFET or IGBT.The diode is an ordinary power diode
in the case of PFCs with discontinuous current control and is a fast recovery diode in the case of PFCs with
continuous current mode control. The losses in the PFC take place in the form of (i) heating in the current sense
resistance (ii) winding and core losses in the inductor (iii) diode conduction and switching losses and (iv) switch
conduction and switching losses.The achievable efficiency ranges from 95% to 98% at full load depending upon
design and control strategies.Most of the losses (80% to 95% of total losses) take place in the MOSFET/IGBT
used as the boost switch.The current control strategy selection has direct impact on the conduction and
switching losses in the MOSFET.
The switch in the closed condition is an almost linear resistance in the case of MOSFETs and a
nonlinear resistance in the case of IGBTs.The MOSFET onresistance depends strongly on temperature
especially in the case of high voltage devices.The on resistance of the switch results in conduction losses during
the time when it conducts current.IGBTs of comparable die size have much lower conduction losses than
MOSFETs.
During the switching on or off of a switch there is a definite period during which the switch
has considerable voltage across it and consid erable current through it i.e. there is a voltagecurrent overlap
period which may last for hundreds of nano seconds to few micro seconds depending upon the switching speed
of the device and gate/base drive design.This overlap period is one of considerab le dissipation and the average
power loss due to this mechanism (called Switching Loss) is directly proportional to the switching frequency and
inversely proportional to the switching speed of the device.
Assume that the switch was on and it is being turned off.It is possible to turn off a MOSFET at
a very rapid rate i.e. the device stops conducting almost abruptly and switching energy will be small.But once the
switch stops carrying current the current that was flowing in Ls1 will push into the output capacitance of the
MOSFET.This capacitance has a small value.Also,unless this capacitance charges to Vo the diode cannot
conduct.Thus the current in boost inductor and Ls1 become energy sources for a highly underdamped circuit
comprising Ls1,Ls2,DrainSource capacitance of MOSFET and diode transition capacitance.The ensuing
oscillations result in prominent voltage overshoot across the MOSFET and may lead to device damage.Also
these oscillations take place at a very high frequency and contribute to EMI.Thus the price paid for reduced
switching loss(by switching off the MOSFET very fast) is in terms of over voltage across it and high EMI (both
inside the equipment and outside).Employing an RC snubber across MOSFET will reduce the over voltage
,damp the oscillations and reduce EMI without affecting the turn off switching loss level.But the next time
MOSFET goes on it has to discharge the snubber capacitor and this results in increased turn on loss.Also the
periodic charging and discharging of snubber capacitor invol ves CV
2
f power loss which can be excessive at
high frequencies.The value of snubber capacitor depends on the stray inductance level and the worst case load
current.Thus the implication of high level of stray inductance during switching off of the MOSFET is either over
stress on the device and EMI or reduced efficiency due to snubber loss.
Now consider the other switching i.e. diode was conducting and MOSFET is being turned on.
A conducting diode has charge storage in it and it remains conducting even after external voltage across it
changes polarity till all the charge inside is removed. And the MOSFET is switched on fast in an effort to reduce
switching loss. But diode does not let up and hence MOSFET continues to support more or less Vo and the full
inductor current is transferred to it at full voltage level. But that is not the end of rise of current in MOSFET.At
that instant the diode current becomes zero, but diode continues to be a short since the charge has not gone out of
it. Hence the output voltage pumps current in the reverse direction through diode and into the MOSFET.The
current through MOSFET rises much above the load current and voltage across it all the while high. This is an
extremely high dissipation period for the MOSFET.This situation prevails until all the diode charge flows out
under the action of reverse current through it. When all the charge is removed the reverse current in the diode
and hence corresponding component in the MOSFET snap and current tends to go to the load current level. But
now the two stray inductances, which had been carrying the reverse recovery current component, will resist the
current snap action of diode and their magnetic energy storage will cause horrendous ringing of voltage across
the just now recovered diode. The diode will fail on over voltage usually. This process of reverse current flow is
called reverse recovery of a diode and associated losses taking place in the MOSFET is called reverse recovery
losses. The reverse recovery current peak can be up to about 10 to 20 times the rated full load current if the diode
is not a fast recovery type. The solutions to the reverse recovery problem are (i) use an ultra fast and soft (i.e.
nonsnappy) diode (ii) reduce the switching on speed of the MOSFET. Reducing the turn on speed of MOSFET
increases the overlap component of switching loss in it and reduces the recovery loss component. Usually an
optimum speed can be found out. RC snubber across the diode is almost unavoidable except when it is a super
fast recovery diode and stray inductance level is very low.
It should be clear from the above discussion that minimising wiring inductances everywhere in the
power circuit layout is crucial for reliable and efficient operation of high power PFC circuits. The MOSFET and
diode should be mounted on the same heat sink and the drain of MOSFET should be connected to anode of the
diode by the shortest link practically possible. Similarly inductance in the source wire of MOSFET should be
minimised to preserve the switching speed of the MOSFET.Copper clad plate structure should be employed in
the D.C. side to minimise the surge impedance of the D.C. bus. Discontinuous mode current control is easy on
the reverse recovery problem since the MOSFET is switched on when the inductor current touches zero. Hence,
turn on losses and reverse recovery losses in the MOSFET will be negligible. However, this gain is partially
offset by increase in the turn off losses due to higher current levels in discontinuous current control. Also ,
increased current levels result in higher conduction losses in these schemes.Continuos current control schemes
have to handle the reverse recovery problem by selection of an ultra fast recovery diode and requires careful
circuit layout. However switching ripple is at a low level in these schemes and hence ripple filtering is easy.
Current stresses in the active devices also is less.
5.1 A Design Example
Fig.9 A 1kW Boost PFC Design using average current mode control
The Fig. 9 shows the circuit diagram of a single phase PFC using average current mode control
and rated for 1kW.It can accept input voltages in the range 150230V.It has an efficiency of 93.8% at full load
and the MOSFET losses under that condition is 50 W and is high due to slow switching.
Fig.10 Current waveforms at full load for the 1kW design
The Fig.10 shows the simulated boost inductor current and line current waveforms for full
load at 230V line. The switching frequency is 50kHz.
ACTIVE POWER FACTOR CORRECTION IN ACDC CONVERTERES II
Surersh Kumar.K.S
Asst.Professor,Dept. of Elect.Engg
R.E.C,Calicut
1. Introduction
Active power factor correction using a single switch and boost topology was dealt with in the
first part of this lecture. In this part, a bilateral ACDC converter functioning as a switched mode rectifier is
examined. Control of the converter from synchronous link principle and current regulated PWM inverter
principle will be covered. The operation of unipolar PWM in a single phase DCAC converter will be examined
in some detail for the sake of completeness. Single phase topology will be used throughout with brief references
to three phase topologies wherever applicable.
2. The Single Phase DCAC Inverter
Fig.1 A Single Phase Bilateral DCAC Converter using IGBTs and related output filter circuit.
Fig.1 shows a single phase DCAC inverter circuit. Inverter circuit solves the low efficiency
problem of linear power amplifiers in DCAC conversion by operating the active devices in switch modei.e.
either device has current through it with voltage at zero or it has voltage across it with zero current. But then ,
with a DC supply and 'Switch' mode of operation of devices , only three values of voltage can be delivered to the
output namely +V, V and 0.But what is desired at the output is a continuous wavecommonly a sinusoid. Pulse
Width Modulation (PWM) solves the problem of generating a real value range of (+V,V) for the output from
three discrete values of +V,V and 0.
The Principle of PWM
(i) Divide the period of the desired sine wave output into a large number of evenly spaced small intervals.
A carrier frequency is employed for this.
(ii) In each such interval apply +V for some time and V for the remaining time such that the average
applied value over that interval is equal to the value of desired output in that interval.This scheme
where +V and V are used to synthesise the output is called Bipolar PWM.Another scheme where +V,0
are applied to synthesise the output during positive half cycle and V,0 are applied to synthesise
negative half cycle of output is called Unipolar PWM
(iii) The output will now be a pulse waveform which contains the desired output waveform in its Fourier
series along with frequency components at or around harmonics of switching frequency ,i.e. the carrier
frequency(or related to it)
(iv) The desired output can be extracted by a simple LC low pass filter since the frequency of desired output
and the switching frequency will be widely separated.
2.. 1 Bipolar PWM Vs Unipolar PWM
Bipolar PWM output contains either +V or V always. Hence, each state change involves a
transition by 2V.Hence switching harmonic content in this scheme is more. In addition, the switching harmonic
content is the highest when the PWM is trying to generate zero volt output after the averaging filter. Hence, it is
difficult to synthesise good 'zero crossings' in a bipolar scheme unless heavy filtering(with consequent
degradation in response time) is used.
Unipolar PWM uses +V and zero to make positive outputs and V and 0 to make negative
outputs. Switching Harmonic Content in this case will be small and will be zero at zero crossings. Filtering will
be easy in this case. Unipolar PWM is assumed in this lecture.Fig.2 shows an implementation of Unipolar PWM
and Fig.3 shows the carrier wave,sine reference and its inverted version and gate signals for the two top
switches.
Fig.2 Implementation of Unipolar Pulse Width Modulation
Fig. 3 Waveforms of the Unipolar PWM Circuit
The carrier frequency was set at around 1.2kHz during Pspice simulation to render clarity to the above
waveforms. In practice, carrier frequency in the range of 1020kHz will be used. The Modulation Voltage was
taken as a 50 Hz sine wave and the simulated waveforms at the output of the bridge and output of the LC filter
are shown Fig.4.The spectral content of the inverter output (running from a 400V D.C Source) is shown in
Fig.5.The 50Hz content is not shown. Notice that the lowest switching frequency content is at around twice the
carrier frequency and not at the carrier frequency as it would have been in the case of Bipolar PWM.This is
another attractive feature of Unipolar PWM.The LC filter used in the Pspice simulation had L=40mH,C=4.7uF
&Load=100ohms.
Fig.4 Inverter Output and Filtered Output Fig.5 High Frequency Spectrum of Inverter Output
The triangle wave sets the interval for pulse width coding and the comparison of triangle wave
with modulation voltage and its inverted version results in coding of instantaneous value of modulating signal
into pulse width. It is possible to see that Vo= (Vmod/Vt)xV where Vmod is the modulating signal (usually sine
wave),Vt is the triangle amplitude ,V is the D.C voltage and Vo is the filtered output of the inverter. Thus the
switches,filter and the circuitry needed to implement Unipolar PWM together can be treated as a single block
called 'PWM Modulator' which implements a multiplication (modulation) of D.C side voltage by the modulating
signal to provide the product as the filtered output.
This PWM Modulator is bidirectional. The diodes connected across the switches will prevent
a reversal of polarity in the D.C side. However, current can flow into or out of the D.C source. In fact , if the
load on the A.C side of the inverter is reactive ,power will flow from the A.C side to D.C side for part of the a.c
cycle. Thus, the converter has four quadrant capability in the A.C side and two quadrant capability in the D.C
side. Thus, it is bidirectional in power flow.
If the D.C side is a source (battery, rectified D.C or even a charged capacitor) and the A.C side
terminated in passive load ,average power flow is from the D.C source to A.C side load. If the A.C side is
terminated in a source and D.C side is loaded by resistor ,power flow is from A.C side to D.C side(provided
suitable control strategy is implemented).If both sides are terminated in sources power can flow in either
direction depend ing on the command from the control system. Thus, whether this PWM Modulator is an Inverter
or Rectifier or ACDC Link or for that matter a Static Condenser or an Active Power Filter depends on the
Control Strategy involved.
3. Synchronous Link Based PWM Rectifier with Unity Power Factor
A Synchronous Link is a pair of A.C sources with same frequency connected together through
an inductive reactance. It is well known that (i) in a Synchronous Link, active power flows from the leading
source to lagging source and is = (V1V2/X) Sin where is the angle of lead , V1,V2 are magnitudes of source
voltages and X is the link reactance (ii) the reactive power flows from the higher voltage magnitude source to the
lower voltage magnitude source and is = (V1/X)(V1V2) Cos .A Synchronous Link is shown in Fig.6.
Usually the angle is small and
Cos is unity. Hence in a practical Synchronous
Link,the active power flow is proportional to phase
angle and reactive power is more or less decided by
difference in voltage magnitudes. Hence the source V2
can absorb active power from V1 and maintain the
power factor at source V1 at unity if it can (i) control
its own phase shift with respect to V1 and (ii) control
its own magnitude to be equal to the magnitude of
V1.This is what is done in a Synchronous Link based
PWM Rectifier.The source V2 is synthesised using a
PWM Modulator described in the last section. This
PWM Modulator runs from a charged Capacitor at its
D.C side. The voltage across the D.C side capacitor is the output of PWM Rectifier.The control system prepares
the required modulation voltage in such a way that the phase angle and magnitude of voltage synthesised by the
Inverter have the right values.Fig.7 shows the power circuit diagram for this rectifier.
3.1 The Control Loops
The control objectives are (i) maintain the D.C voltage across Co at a set constant level against
variations in the DC side load and A.C side voltage and (ii) maintain the a.c source current pure sinusoid at unity
power factor. The control strat egy will be to (i) sense D.C side voltage,compare it with reference and form the
error signal, process the error signal (ii) use this processed error signal to decide the phase shift of the
modulating signal which is a phase locked sine wave and (iii) sense the a.c source voltage and decide the
amplitude of the modulating signal to produce an inverter output voltage which is equal to the sensed a.c source
voltage. A block diagram representation of the strategy is given in Fig. 8.
Fig. 8 Block Diagram of the Control System for Synchronous Link PFC
The PLL based SineWave generator generates a fixed amplitude sine wave that has same
frequency as that of the a.c source and is in phase with it. This wave is given a phase lag which is proportional to
the control voltage coming from the error amplifier. The phase shifted sine wave amplitude is adjusted in the
variable gain amplifier .The gain of the amplifier is decided by the magnitude of the a.c source as calculated by
the rectifier and averaging filter block. The final phase shifted ,amplitude adjusted sine wave becomes the
modulating signal for the PWM Modulator.
The PLL Sine Wave generation is usually done digitally .High frequency clock, which is
frequency locked with a.c source, is produced by frequency multiplication using PLL.This clock is used to run a
binary UP/DOWN counter. The counter output is used as the address bytes for an EPROM which has the sine
table written in it. The read out value is converted into analog value by DACs.Phase shifting is achieved by
manipulating the counter reset signal. In this scheme ,the phase angle can be adjusted only once in a cycle.
Error Amplifier
and Processor
Voltage
Controlled
Phase Shifter
Variable Gain
Amplifier
PLL based
Sine Wave
Generator
Vo
Sine
Sine
Modulation
Signal for
the Inverter
Line Voltage
Rectifier and
Averaging
Filter
Vo Reference
The D.C side capacitor will have a second harmonic content due to the same reason as
explained in the case of Single switch boost PFC in the first part. This second harmonic has to be filtered out in
the error amplifier if third harmonic distortion is to be avoided in the a.c side current. This filtering contributes to
reduction of open loop bandwidth. In addition, the rectification and averaging filter on the a.c voltage also
reduces open loop bandwidth. And,in any case ,phase angle between the inverter output and a.c source can be
adjusted only once in a cycle. To conclude ,the system response will be slow. If this slow response goes along
with an inductor which is too small in value,the closed loop system will be slow and under damped resulting in
severe power flow oscillations in the link. The inductor has to be large enough to limit the amplitude of power
flow oscillations under transient conditions. But , with a large inductance,the drop across it due to the active
current flow may not be negligible and hence power factor will only be close to unity and will not be unity.
The compensator design for this control system can be tricky due to factors mentioned above.
Also the link containing the capacitor,PWM Modulator,link inductor and a.c source has a second order
dynamics due to L and Co and this dynamics will be usually very much under damped. In addition,the open loop
gain is heavily dependent on the d.c side load and a.c side voltage magnitude.
4. Current Regulated Bilateral Converter Based PFC
In the Synchronous Link scheme ,the D.C output was controlled by controlling the lag angle of
the inverter generated voltage and power factor was controlled by maintaining equality between the inverter
output voltage and a.c source voltage. Both are indirect ways to achieve the control objectives. In Current
Regulated scheme , the Converter is first converted into a regulated current source under feed back action i.e. the
inverter is gated in such a way that the current flowing through the filter inductance at the output follows a
reference current wave form on an instant to instant basis. This current reference wave form is then constrained
to have sinusoidal shape and to be in phase with the a.c line voltage. Its amplitude is left as free variable ,to be
decided by the d.c output voltage control loop. Thus, there are two control loopsthe inner current control loop
which ensures that the switches are gated in such a way that the inverter output current tracks the reference
current rapidly and without error and an outer voltage control loop which maintains the d.c output voltage
constant by driving the current control loop suitably. The link inductance L is unnecessary. It is not that this is
not a synchronous link. It is. The phase angle and magnitude of inverter output will be according to the
principles brought out earlier with the filter inductance taking on the role of link reactance. It is that we do not
try to control phase and magnitude of inverter output ,rather we catch the quantity we want control and control it
directlythat quantity is the a.c side current.
As in the case of boost type PFC, there are many current control schemes for Bilateral
Converter also. Prominent among them are hysterisis current control and feed forward current control. Hysterisis
current control is covered in this lecture. Feed forward current control will be covered in another lecture in
another context.
4.1 Hysterisis Current Control
In hysterisis current control,the filter inductance current is sensed by means of a CT and is
compared with the reference current waveform received from the voltage control loop. The current error is
amplified and presented to a hysterisis comparator. The comparator changes state when the error exceeds a
Fig.9 Block Diagram of Current Controlled Bilateral Converter PFC with Hysterisis Current Control
Error Amplifier
and Processor
Multiplier
Hysterisis
Comparator
PLL based
Sine Wave
Generator
Vo
Sine
Sine
Line Voltage
Vo Reference
From CT i n the
Lfilter line
Gate
Signal
Generation
Gate Signals
preset value in positive and negative directions. The comparator state change is used to decide which of the
switches should be on and which should be off. For e.g. say the actual current drawn by the inverter from a.c line
is less than what it should be, then the inverter should present a lower voltage against the line so as to increase
the current drawn and hence the gate logic switches off A+ and B and switches on A and B+. A block diagram
of this control strategy is shown in Fig.9.
The disadvantages of this control scheme are variable switching frequency,bipolar PWM and
the related high level of switching harmonics,bad wave shape in the line side when d.c side is not loaded etc.
These are the usual disadvantages associated with hysterisis schemes.
The current control virtually eliminates one order (that of induct ance) from the dynamics since
it effectively converts the inductor line into a current source line. This results in ease of design of the voltage
control loop and faster response against variations in the D.C output voltage. The open loop dynamics is of first
order contributed by the output capacitor and D.C. load .The voltage control loop dynamics and loop design is
similar to the design in the case of single switch boost type PFC covered in the first part of this lecture and is not
repeated here.
The disadvantages associated with fixed error band hysterisis current control can be alleviated
largely by employing either variable band scheme or by using error triangularisation. However, both strategies
will add to control hardware complexity. Many fixed frequency current control strategies exist for the control of
this PWM rectifier. The are not covered here due to paucity of space.
4.2 Comparison with Single Switch Boost type PFC
If rectification is the aim, it looks as if one does not need bilateral power flow capability in the
PFC conveter. However, there are definite advantages in choosing the bilateral structure as the underlying
converter.
The Single Switch PFC can not bring down the output capacitor voltage quickly down to set
point if it overshoots during load throw or start up. The error amplifier saturates and the circuit reduces the
current into capacitor to zero. However, the circuit is incapable of discharging the capacitor into the a.c supply.
The Bilateral Converter based PFC has this capability and results in a tighter control of output voltage.
Boost type PFC line current waveform will show distortion at zero crossings due to cut in
behavior of diodes. In addition, it can enter discontinuous mode of operation with current distortion and
increased ripple level at low loads. Both these effects are eliminated in Bilateral Converter based PFC.
Bilateral Converter based PFC can be controlled in such a manner that it can deliver lagging
reactive power into the a.c source. It can, thereby, work as a rectifier and static capacitor simultaneously if
necessary.
===============
SOME CASE STUDIES IN POWER QUALITY
Suresh Kumar.K.S
Asst.Professor,EED,R.E.C.,Calicut
Case Study 1  Voltage Transients Causing Diode Failures
Environment  A plastic extrusion manufacturer in the midWest had a 480V delta feeding a plastic extrusion
machine. The ASDdriven synchronous motor in the extruder had a halfwave bridge rectifier circuit to provide
excitation voltage to the pole coils.
Problem Diodes on the halfwave bridge exciter circuit were
blowing out, and the filters to the SCRs were being damaged.
Monitoring Survey  Three channels of the voltage supply
feeding the extruder were monitored for just two seconds before
enough data was collected to determine the cause of the failures.
A burst of transients would occur three times a second. The
RMS voltage did not change significantly during these
transients. Closer examination of the waveforms showed that
the transients were actually a repetitive series of voltage
transients, occurring six times a cycle on all three phases. An
example of the voltage waveforms for one phase is shown in
Figure 1..
These repetitive voltage transients are referred to as voltage
notches. The maximum voltage of the transient could produce
damage, and the voltage notches that cross the zero
axis could result in zero crossing errors. Closer
examination of the transients is shown in Figure 2.
Analysis
The following were calculated values of this voltage
disturbance monitoring period:
Number of transients: 192 Amplitude: 580 volts.
Worst Absolute amplitude (from zero crossing): 864.
Rise time: 1.0851 microseconds Frequency (1/4*rise):
230.4kilohertz.
Number of zero crossing errors this frame: 146. Worst
zero crossing width: 61440 microseconds. Worst zero
crossing delta voltage: 168 volts.
Worst notch area: 0.021475 volt seconds.
Transient Analysis
The absolute amplitude value confirmed the cause of
the damage to the diodes, as this voltage exceeded the
ratings of the di odes in the halfwave bridge. The very
fast rise time and equivalent frequency greater than
100KHz of the transient indicates that the source of the
transient is relatively close to the measuring point. This
would indicate that the origin of these transients was an
electronic switching load such as a bridge rectifier used on
many electronic motor drives. The transients on other
phase voltage channels were not the same polarity, but
occurred at relatively the same time, as shown in Figure 3.
Zero crossing errors can cause timing problems with phase
controlled and electronic loads. Clocks can run faster and
power electronics, such as SCRs and switching diodes, can
misfire and be damaged. Notching can also trip protective
relaying, stress power electronics, and cause excessive
heat in motors and transformers.
Figure 2. Single Transient Waveform
Figure 3. Three Phase Voltages Overlaid.
Harmonic Analysis
The following harmonic analysis in Figure 4of the initial waveform event of Phase BC Voltage. This channel's
total harmonic distortion was 11.2%. The highest harmonic was the 2nd, at 8.3%. The high values of even
harmonics is attributed to the halfwave rectifier, whose Fourier expansion is made up of solely even harmonics.
Figure 4.Harmonic Analysis of Phase C
Probable cause
Repetitive voltage transients are usually caused by phaseangle controlled loads, such as three phase converters.
A voltage notch results from two phases being momentarily short  circuited during the commutation period. In
this cause, they were creating by the ASD drive itself, which converts the AC to DC and then back to AC to
control the motor's speed and torque. The halfwave bridge used as the voltage exciter was the source of the
abnormally high even harmonics.
Solution
The solution employed was to place MOVs with appropriate clamping voltage across the diodes in the bridge to
prevent their destruction. Though not used at this site, special filters, such as certain line tracking filters, can be
used to alleviate zero crossing errors. In addition, power conditioning devices, chokes or special filters could be
used to "fill in" the notches and smooth out the waveform.
Case Study 2  Utility Power Factor Capacitor Bank Switching Problem
Environment  A medical clinic in Las Vegas, Nevada, employing sensitive computed tomography (CT Scan)
system. Power was brought to the system from a 480 volt service feeding a 480to208 volt isolation transformer.
Problem  CT Scan system was experiencing repeated computer lockups and component failures.
Measurements  The medical equipment service company installed a power monitor on site to analyze the
power to the system. A single day of monitoring was enough to identify the case of the failures. Figure 1shows
the disturbance on the line caused by a utility power factor correction capacitor bank located just one block
away. Figure 2 shows the attenuation effect of the isolation transformer, still not enough to protect the CT Scan .
Figure 1. Disturbance caused by utility capacitor bank Figure 2. Output of isolation transformer which does little
to minimize disturbance
Solution  Expansion of the waveform data, Figure 3,
revealed the ringing frequency of the system, when
energized by the capacitor bank, was between 1 kHz
and 1.5 kHz. This allowed the specification of a
treatment device to mitigate the problem.The medical
equipment company recommended the use of an
activetracking filter specifically designed for this type
of disturbance around 1 kHz. The filter was installed
on the 480 volt line to protect all of the downstream
equipment. Figure 4 shows the difference between the
input (Channel C) and output (Channel B) of the filter
during a subsequent capacitor bank switching
operation. Figure 3. Waveform expansion shows ringing frequency
Figure 4. Input waveform (above) and Figure 5 output waveform (right) shows disturbance attenuation effect of
filter during capacitor switching.
Case Study 3Loose Buss Bar Bolts Cause Sags
Environment  An administration building in a government complex in New Jersey had a transformer with a
4KV primary, 120/208V wye, 800A secondary. The buss duct ran up to a second floor panel, which supplied an
office area.
Problem Computer misoperations and lights flickering were occurring randomly for nearly two years.
Emergency lighting was also flickering.
Measurements Three voltages and corresponding currents were monitored at the second floor panel for three
days. During this time, two types of power quality phenemona were observed: sags and voltage fluctuations.
Figure 1 shows a time
plot of several of the
sags. What appears to
be the first sag at 14:00
is actually a series of
nine sags.
The most severe sags
were to 57 and 76 volts,
both for 3 cycles. The
voltage and current
waveforms for the 57 V
sag are shown in Figure
2. Note the RMS of the
current reduced during
the intial part of the sag,
then swelled as the
voltage returned to
normal. The second sag
shown on the timeplot is
a more severe sag,
lasting seven cycles and
having a minimum
RMS value of 29 Vrms,
as shown in Figure 3. Figure 1. Timeplot of Channel A voltage over part of the monitoring period.
The other PQ phenomena observed
were RMS voltage fluctuations, as can
be seen in Figure 4. If you connect the
negative peaks of the voltage together
(red line), you will see that it produces
a low frequency curve of its own.
Impedance Analysis
The source and load impedance
calculations for Channel A shown in
Table 1 did not show any abnormal
results. Though the approximated
source impedance Figure 2. Voltage and Current Waveforms during 3 cycle sag
was a little on the high side, the
results were what one would expect in
this type of environment.
Sag Analysis
Three of the sags observed during the
monitoring period were significant
enough to cause equipment mis
operation (depending on the actual
susceptability of the equipment.) All
three of the sags appear to be coming
from the source, not the load, relative
to the monitoring point. The source, in this case, was towards the electric utility: from the breaker panel, back
down through the buss ,to the transformer. This was determined beca use no large increase in current was noted
when the sag began. In addition, the current decrease for the first couple cycles, followed by a slight swell. This
would be consistent for loads of rectifiedinput, switchedmode power supplies (as found in most electronic
equipment, such as PCs) and fluorescent lights found in an office complex.
Table1
Voltage Current Load Z delta V delta I Source Z
114.63 4.33 26.55 3.52 0.29 1.28
Flicker Analysis
Figure 4 shows the variations
of the voltage of channel A
often referred to as voltage
fluctuations. When the
frequency of this modulation
is below 30 Hz, the human
eye can perceive such as light
flicker, depending on the
percent fluctuation. The 8%
modulation of Channel A is
around 10 Hz, and is very
near the most perceptible
point for the human eye
(0.25%variation at 8.8 Hz).
Harmonic Analysis
The following harmonic
analysis in Figure 5 is very
similar to that for fluorescent
Figure 4. Voltage Fluctuation.
lighting, where the third harmonic is the largest
component, the 5th is half of the third, the 7th
and 9th are one quarter of the third, and the 2nd
is slightly smaller than the 7th.
Rectifiedinput, switched mode power supplies
will also contribute signficant odd harmonics, in
a 1/h amplitude ratio (where 'h' is the harmonic
number).
Probable Cause
As the analysis had shown, the cause of the
problems was probably between the breaker
panel and the source. It was determined that the bolts on the Phase A buss bars had become loose.
Solution
Tightening the buss bar bolts eliminated the sags that caused the computer malfunctions, and the voltage
fluctuations that resulted in the light flickering.The probability of this kind of problem can increase in situations
where there are high harmonic currents that vary during the day. Thechange can result in expansion/contraction
cycles that can loose bolts and other electromechanical connections.
.
Case Study 4  Computer on Shared Branch Circuit
Environment  Engineering laboratory adjacent to offices.
Problem  A computer system used by laboratory personnel exhibited intermittent fail ures and data errors.
Typically these would start around 10 a.m. On some days there were no failures.
Measurements A power monitor was installed at the panelboard serving the computer system. The monitor
was connected, linetoneutral (Channel A) and neutraltoground (Channel B). The recorded linet oneutral
waveforms were
Figure 1. Graphic summary reveals Figure 2. Shows regular nature of these sags (top), plus
linet oneutral repetitive sags. corresponding swells on the neutral (bottom).
relatively undistorted sine waves, which gave no clues as to
the source of the line disturbances.
An event summary of the RMS voltage, Figure 1, revealed a
pattern of repetitive sags in the RMS voltage, beginning just
after 10 a.m. The regular nature of these sags, as well as
corresponding swells on the neutral, were made even clearer
by increasing the resolution to a few minutes, Figure 2.
Solution  The regular repetition of the voltage sags was a
powerful clue, indicating automatic switching of another
load on the circuit.
Figure 3. Neutraltoground waveforms demonstrate load was essentially linear
The neutraltoground waveform, Figure 3, indicated the load was linear.
A little more detective work soon located a laser printer in one of the nearby offices whose print fusing heater
switched on every minute or so. The high current demand and resulting potential developed on the neutral was
causing the computer errors. The printer was usually powered up around 10 a.m., after the user had created text
to be printed. Moving the printer to another branch circuit removed the source of computer interference.
Case Study 5  Harmonic Distortion of Current
Environment
Office building with personal computers, terminals, copiers and other electric office equipment supplied by
threephase wye service.
Problem
Facility engineers at this site experienced repeated problems with the failure of electrical distribution equipment.
A distribution transformer overheated and failed, circuit breakers were tripping and electrical connectors were
burning out. These problems are all symptomatic of overload conditions.
However, initial measurements of phase currents using a true RMS ammeter showed current readings of 257 to
298 amps. These values did not exceed equipment ratings.
Measurements
The real problem started to become apparent when readings were taken of the current in the common neutral
conductor. The neutral was carrying 229 amps, nearly equal to the phase currents, even though the phase loads
were well balanced.
Further analysis was performed using a power monitor. Figure 1 shows the wave form of Phase A current. The
nonsinusoidal shape is due to harmonic currents typical of switching mode power supplies which are used in the
majority of modern office automation equipment. These are nonlinear loads. The peak current shown here is 475
amps. If the wave form was sinusoidal, its peak current would be only 363 amps. As shown in the plot of Figure
2 total harmonic distortion is about 32 percent, of which the third harmonic contributes about 31 percent.
When phase currents are distorted to this extent, the normal threephase cancellation, which results in near zero
neutral current, does not take place. The odd harmonics produced at 180 Hz, 300 Hz and higher frequencies in
the phase conductors result in large currents being carried by the neutral at predominantly 180 Hz. This is shown
in Figure 3.
The net effect on facility wiring is that the common neutral conductor will frequently be carrying current beyond
its rated capacity. In severe cases this can well exceed phase currents. These high frequency currents can be
damaging to transformers and other devices harmonic content designed to operate at 60 Hz.
Solution
In the short term these problems can be addressed by oversizing neutral conductors and derating transformers
to a more conservative value of 60 percent.
(Note These case studies have been abstracted from similar case studies published by M/s DranetzBMI
Corporation, a prominent PQ Monitoring Equipment manufacturer in USA at their web site
http://www.dranetz.com)
PWM VOLTAGE SOURCE INVERTER BASED STATIC VAr COMPENSATORS
(SVC) FOR POWER QUALITY ENHANCEMENT
Surersh Kumar.K.S
Asst.Professor,Dept. of Elect.Engg
R.E.C,Calicut
1. Introduction
PWM Voltage Source Inverter based Static VAr Compensators (referred to as SVC here
onwards) began to be considered a viable alternative to the existing passive shunt compensators and Thyristor
Controlled Reactor (TCR ) based compensators from mideighties onwards. The disadvantages of
capacitor/inductor compensation are well known. TCRs could overcome many of the disadvantages of passive
compensators. However they suffered from two major disadvantages ;namely slow response to a VAr command
and injection of considerable amount of harmonic currents into the power system which had to be cancelled by
special transformers and filtered by heavy passive filters.
It became clear in the early eighties that apart from the mundane job of pumping
lagging/leading VArs into the power system at chosen points ,VAr generators can assist in enhancing stability of
the power system during large signal and small signal disturbances if only they were faster in the time domain.
Also ,they can provide reactive support against a fluctuating load to maintain the bus voltage regulation and to
reduce flicker problems,provide reactive support to control bus voltages against sag and swell conditions and
provide reactive support to correct the voltage unbalance in the source if only they were fast enough. PWM
SVCs covered in this lecture are capable of delivering lagging/leading VArs to a load or to a bus in the power
system in a rapidly controlled manner.
High Power SVCs of this type essentially consist of a three phase PWM Inverter using
GTOs,Thyristors or IGBTs, a D.C. side capacitor which provides the D.C. volt age required by the inverter,filter
components to filter out the high frequency components of inverter output voltage,a link inductor which links the
inverter output to the a.c supply side,interface magnetics (if required) and the related control blocks. The Inverter
generates a threephase voltage, which is synchronized with the a.c supply ,from the D.C. side capacitor and the
link inductance links up this voltage to the a.c source. The current drawn by the Inverter from the a.c supply is
controlled to be mainly reactive(leading or lagging as per requirement) with a small active component needed to
supply the losses in the Inverter and Link Inductor (and in the magnetics,if any).The D.C. side capacitor voltage
is maintained constant( or allowed to VAry with a definite relationship maintained between its value and the
reactive power to be delivered by the Inverter) by controlling this small active current component. The currents
are controlled indirectly by controlling the phase angle of Inverter output Voltage with respect to the a.c side
source voltage in the "Synchronous Link Based Control Scheme" whereas they are controlled directly by current
feedback in the case of "Current Controlled Scheme".In the latter case the Inverter will be a Current Regulated
one ,i.e. its switches are controlled in such a way that the Inverter delivers a commanded current at its output
rather than a commanded voltage (the voltage required to see that the commanded current flows out of Inverter
will automatically be synthesized by the Inverter).Current Control Scheme results in a very fast SVC which can
adjust its reactive output within microseconds of a sudden change in the reactive demand.
However,current control schemes will require high frequency switching in the Inverter
switching frequencies which are so high that low frequency devices like thyristors and GTOs are ruled out.
Hence they have to be based on MOSFETS or IGBTS.The latter seems to be the current choice with its high
voltage and high current rating availability with low conduction losses. However, at present, they are limited to
applications in the low voltage systems (400V,1.1kV etc) and at distribution power level rather than transmission
and subtransmission power levels. This is because of the limited maximum voltage/current ratings available in a
single device/module.
When it comes to transmission/sub transmission level GTOs are the preferred devices and they
can take switching frequencies below 13 kHz. Hence ,at these levels,SVCs are made with the Synchronous Link
Control Scheme which gates the Inverter to deliver a voltage output (rather than a regulated current).This kind of
Inverter operation makes it possible to implement one of the many specialized PWM switching schemes aimed
at minimizing the switching frequency while keeping acceptable level of harmonic content in the Inverter
output.
Summing up,SVCs are fast responding generators of reactive power with leading VAr/lagging
VAr capability which can provide steady state reactive compensation as well as dynamic compensation during
power system transients,sags, swells,flicker etc. Thereby they can contribute significantly to enhancement of
Power Quality.High Power SVCs are usually made with devices of low switching frequency capability and
hence need special PWM patterns to optimize switching behaviour. Such SVCs use Synchronous Link principle
in the control blocks. This lecture deals with this kind of SVCs. The reader is urged to go through the lecture
notes on Synchronous Link based Single Phase PWM Rectifier (pages 7075 ) before reading on. Much of what
was discussed there is relevant in the SVC context too.
2. The Basic Principle of Synchronous Link Based SVC
In a synchronous link where two a.c sources of same frequency are connected together by
means of a link inductor, active power flows from the leading bus to the lagging one and reactive power flows
from the source with higher voltage magnitude to the one with lower voltage magnitude. The active power flow
is almost entirely decided by the lead angle whereas the reactive flow is almost entirely decided by the difference
in voltage magnitudes provided the inductor is loss free ,the lead angle is small (less than 15 degrees) and the
voltage magnitude difference is small(less than 0.1 p.u) . The situation changes slightly if the link contains
resistance. If two sources V1 with a phase angle of and V2 with a phase angle of 0 are connected together by
means of an inductive link of impedance (R+jX) ohms and if the active power flowing into the source V2 is
constrained to be zero (because this represents the SVC situation) the power delivered by the source V1 (which
will not be zero and it will be equal to the power absorbed by the resistance in the link ) and the reactive power
delivered to the link by the source V2 will be given by the following relations (after a little algebra along with the
assumptions that is small and R << X ).
Active Power Delivered by V1,P = (V1
2
/R)
2
Watts  (1)
Reactive Power Delivered by V2,Q = (V1V2/R) VArs  (2)
Also , Q = V2(V2V1)/X VArs
where the powers are for a phase and voltages have phase values. These relations can be used upto about 20
degrees for .Active Power drawn from the source V1 is independent of sign of phase angle (only V1 can
supply losses in R because of the zero active power constraint at V2) whereas the reactive power delivered by
V2 is directly proportional to the phase angle. In the SVC context,the source V1 is the power system voltage at
the bus where the SVC is connected,V2 is the a.c voltage generated by the Inverter in the SVC, R is the total loss
resistance in the link comprising the winding losses in the link inductor,interface magnetics and the inverter
switches and snubbers etc. It is also possible to derive the following useful relationships in this context.
The Phase Angle of V1 w.r.t V2 , = (R/X) (V2V1)/V1  (3)
This shows that the relative phase angle is linearly related to the voltage magnitude difference (for small
differences) and hence the reactive power delivered by V2 is proportional to the voltage magnitude difference.
Thus Q is proportional to or equivalently to (V2 V1). Both points of view will be useful later to understand the
two different ways in which this SVC can be controlled.
In the SVC, the required a.c voltage source V2 is generated by inverting the D.C. voltage, which is assumed
available across the capacitor in the D.C. side. But if the active power which goes into the inverter from the
mains is kept zero, the initially charged capacitor will soon discharge down to zero due to active power losses in
the Inverter which the D.C. side will have to supply. The D.C. side voltage will remain constant (or at least
controlled) if the power drawn from mains is just enough to supply all the losses which take place everywhere
due to the flow of demanded reactive current. The following relation may be derived for the D.C. side ca voltage
under this condition.
The D.C. side voltage ,Vd = (V1/k)(1(X/R) ) volts  (4)
Where V1 is the rms phase voltage of a.c mains,k is a constant, which also absorbs the modulation index of
PWM process in the Inverter.
From the relations cited above two control strategies emerge for the control of a Synchronous
Link Based SVC.They are described below. The reference signal to the controller is assumed to be the desired
reactive power flow from the SVC.
1. Keep the D.C. side voltage constant by controlling the value of .And control the reactive power from
the inverter by directly changing (V2 V1) by controlling the modulation depth (i.e. the multiplication
factor that comes between the D.C. voltage and the amplitude of a.c output in the Inverter).It should be
obvious from the equations 1 to 4 that this strategy will result in an interacting control system.
2. Let the D.C. side voltage vary according to equation(4) and use control to control the reactive power
delivered by the SVC.There is only one control variable and that is .The modulation index of the
Inverter is kept constant and D.C. voltage is allowed to vary. The D.C. voltage increases when the SVC
delivers increasing lagging VAr and it decreases when SVC delivers leading VArs.Here the control of
VAr is indirect. When the reactive power reference changes, it causes a change in value. The residual
voltage across link inductor changes resulting in more active power flow into/out of the
Inverter .Increased active power flow into/out of the Inverter results in increase/decrease in the energy
storage in the D.C. side capacitor resulting in an increase/decrease in the D.C. side voltage. With a fixed
modulation index ,the increase/decrease in the D.C. voltage is straight away passed on to Inverter
output voltage V2.Change in the Inverter output voltage results in the desired reactive power change.
Obviously the response time is decided by the link inductor and D.C. side capacitor and will be
relatively slow.
In the constant D.C. voltage scheme, the D.C. voltage dynamics is going to be slow since the
same mechanism described above will be responsible for maintaining the D.C. voltage. However,the
reactive power flow is controlled by controlling V2 directly by changing the modulation index of the
Inverter and this dynamics can be fast. The components which decide the dynamics will be the loss
resistance,link inductor value,Inverter filter components and the feed back system parameters.
3. The Inverter and Programmed Harmonic Elimination PWM
A ThreePhase Inverter
using IGBTs is shown in Fig.1.In certain
cases the neutral wire may not be present and
the D.C. side capacitor may be a single one.
However, for the purpose of explanation, a
neutral point may always be imagined. With
this the three phase Inverter becomes three
separate singlephase half bridge Inverters
sharing the same D.C. source. Bipolar and
unipolar PWM schemes using a triangular
carrier frequency was discussed in another
lecture (page 7072) in the context of single
phase full bridge converters. Much of the
same is applicable here too except that only
bipolar PWM is possible for a half bridge
topology since no combination of switching
patterns for the upper and lower switches of a
half bridge can apply zero potential at the load point. Bipolar PWM using a triangular carrier and sinusoidal
modulating voltage can be applied here with the modulating waves of the three half bridge sections forming a
balanced three phase signal set.
However,the switching frequency required in Sinusoidal Pulse Width Modulation using
triangular Carrier to achieve reduction in output harmonics is usually excessive as far as high power devices like
GTOs are concerned. Hence, programmed harmonic elimination techniques is preferred at high power levels.
Like in any other PWM scheme, +Vd/2 and Vd/2 pulses are applied across the load in the
programmed harmonic elimination technique also. But in this scheme the position and duration of these pulses
are precalculated offline in such a way that (i) certain chosen harmonics are completely eliminated completely
in the output and (ii) the fundamental component of the output has a desired value. By a general formulation of
Fourier series coefficients of a pulse wave it is possible to derive a set of equations involving angle positions of
the positive and negative pulses to satisfy the conditions on elimination of chosen harmonics and on the
fundamental amplitude. The maximum possible amplitude will be available when the output is a full square
wave(i.e. no harmonics are eliminated) and will be 1.275(Vd/2).But when harmonics are to be eliminated it is
not possible to reach this value of fundamental voltage. For every selection of harmonics to be eliminated there
exists a maximum value the fundamental component can have and it will be less than 1.275(Vd/2).For example
,it is 1.188(Vd/2) for a scheme where fifth and seventh harmonics are eliminated.Fig.2 shows the normalized
pulse pattern which appears at A phase output when fifth and seventh harmonics are sought to be eliminated. The
switching frequency of each
will be 350Hz with this
pattern.
The equations which
yield the angular positions for
a chosen elimination format
and fundamental amplitude is
transcendental algebraic in
nature and require numerical
techniques for solution.
Moreover for the same
harmonic elimination format
the switching angles will vary
with the fundamental
amplitude desired;and the
variation can be highly
nonlinear. See Fig.3.The
nature of equations make an
online implementation of
pattern generation very
difficult. In addition, the
nonlinear angular position
variation with changes in the desired fundamental component makes it difficult to generate the PWM pattern in
real time by analog/digital logic. However, it is possible to implement this scheme using micro
processors/controllers and EPROMs.
A sinusoidal reference wave at frequency equal to the desired output frequency of the Inverter
is frequency multiplied in a PLL system. The square wave from VCO of PLL is used to clock a UP/DOWN
counter. The counter output is used as address bytes of an EPROM which has the required switching pattern at
that instant written in it(by offline
computation and EPROM programming).The
EPROM has patterns
stored for various quantised values of
fundamental amplitude. The control signal
which sets the fundamental amplitude is A/D
converted and the code is used to decide the
range of EPROM memory locations to be read
out by the counter output. Once in a
fundamental cycle the counter is forcibly reset
(at zero crossing of reference sine wave
usually), to avoid subharmonic components in
the output due to jitter in the PLL and other
similar errors everywhere. Note that it is
possible to shift the phase of the fundamental
component of Inverter output with respect to
reference sine by shifting the counter reset
point with respect to the zero crossing point of
reference sine. A threephase pattern can be
similarly generated. However, large memory may be required for fine control of output voltage fundamental
value.
4. Phase Angle Control of SVC
Fig.4. shows an SVC configured to keep the reactive power delivered by the Source at a zero
value as long as the reactive demand from the load is within the SVC rating. Thus, the p.f of the Source will be
maintained at unity under steady state conditions by the SVC.The control of SVC reactive power is by pure
control and the D.C. bus voltage is allowed to vary. This scheme, though somewhat slow, results in simplified
control hardware.
The source side voltages and currents are sensed and the reactive power is calculated by
analog/pulse circuitry. This calculated value is compared with the desired value (usually zero) and the error is
processed in a proportionalintegral controller. The error output decides the phase shift needed in the inverter
output in order to develop the required D.C. bus voltage such that the inverter output voltage magnitude will be
sufficient to make the Inverter deliver the VArs required by the load. The Inverter is gated by a fixed PWM
pattern optimised for eliminating chosen harmonics (usually fifth, seventh, eleventh etc; triplen harmonics need
not be eliminated since they do not result in current flows in a three wire system). The needed PWM pattern is
stored in an EPROM and is read out using the scheme described in the last section. This is by far the most
popular scheme used in high power SVCs.
The open loop dynamics of the SVC features a third order transfer function (for small signals)
between and Qc, the reactive power delivered by the Inverter.The transfer function has a pair of complex
zeros, a real pole and a pair complex poles. Various research workers have derived the following transfer
function for the SVC.
Q
c
(s)/(s) = N(s)/D(s) where N(s)=(Vs
2
/L){s
2
+(R/L)s+(k
2
/2LC)} and
D(s)=s
3
+(2R/L)s
2
+{(R/L)
2
+(k
2
/2LC)+
2
}s+(k
2
R/2L
2
C) where all the parameters have the already defined
meaning and is the system frequency.The step response usually features a rise time ranging from 37 cycles of
a.c.It is possible to employ a PI controller with suitable gain characteristics to compensate the closed loop system
and to obtain a step response rise/f all time between 1 to 3 a.c cycles.
It is not necessary to sense the reactive power in all three phases of the source in the case of
balanced operation.However if the source or load is unbalanced all the three phases will have to be monitored to
calculat e the total source reactive power.But the SVC will be configured to deliver this total demand by dividing
it equally among three phases to ensure current balance in SVC.If exact cancellation of reactive power in all the
three phases is required under unbal anced conditions a three phase SVC made of three single phase units with
entirely independent control will yield better results.
5. SVC with Constant D.C Bus Voltage
The above scheme suffers from the disadvantage of variable D.C. voltage across the Inverter
input and sluggish response to changes in reactive demand.The solution is to control the D.C. voltage by phase
angle control and to control the reactive power flow by control of modulation index control.Two separate control
loops (which interact with each other ) are involved here.But by separating the time scale of dynamics it is
possible to decouple the interaction to a satisfactory degree.
Control of modulation index i.e. control of fundamental component of inverter output voltage
with a constant value of D.C. voltage can not be easily achieved without complex hardware with a large memory
requirement as explained before.Hence this scheme of control is better suited for SVCs with Sinusoidal Pulse
Width Modulation (SPWM) in the Inverter.While it is true that programmed harmonic elimination is better than
SPWM in terms of switching frequency minimisation for a given level of harmonic reduction,SPWM with a
synchronised triangle wave carrier at around 2 to 3kHz can be a viable alternative; especially when the
fundamental amplitude is to be controlled.This is true even for GTO based inverters using state of the art GTOs.
Only bipolar PWM is possible for a three phase Inverter.Hence SPWM in bipolar format using
a triangular carrier in the frequency range of 1 to 3 kHz is assumed in this section.The carrier wave has to be
synchronised to the modulating signal (i.e. sine wave) to eliminate subharmonic components in the output.The
process of SPWM produces a fundamental component equal to (Vd/2)(V
sm
/V
t
) at the invert er output terminals
where V
sm
is the amplitude of the modulating signal and V
t
is the amplitude of the triangle wave.The harmonics
are sufficiently shifted in frequency by the PWM process to allow easy filtering.Now the inverter output voltage
can be controlled by controlling the amplitude of modulating signal .
Fig.5 shows the block diagram of the SVC with D.C. voltage control.The D.C. voltage is
sensed,compared with reference level and the error is processed in a PI controller.The output of the PI cont roller
is converted into a time marker pulse which is time shifted from zero crossing of phase voltage by an amount
proportional to the output voltage of PI controller.This time marker pulse will reset the counter in the phase
locked sine wave generator and thereby effect phase shift in the Inverter modulating signal .The VAr in the line
is calculated in the VAr calculator and this forms the actuating voltage on an analog multiplier which scales up
or down the fixed amplitude sine wave generated by PLLCounter EPROMDAC system.The phase shifted and
amplitude adjusted sine wave becomes the modulating signal for a SPWM block and the Inverter reproduces the
signal at its output after amplification by Vd/2.
The VAr control loop here is essentially of first order due to link inductor and system losses. A high gain PI
controller will accelerate the step response of this loop to a level where VAr commands are followed in less than
a cycle. The slower voltage control loop will carry out the slow adjustment of phase angle needed to maintain the
D.C. voltage constant. A combination of large valued capacitor, low valued inductor, fast VAr control loop and
slow D.C. voltage control loop will ensure rapid VAr control with much reduced current amplitude oscillations
in the link inductor. This scheme can very effectively provide reactive support during the power system transient
conditions and can compensate a highly fluctuating load like an arc furnace.
6. The Reactive Demand Calculator
The speed of response of the SVC is decided by two time delays the rise time of SVC when a
step change is applied to its reactive power command input and the rise time behavior of the reactive demand
calculator when the actual reactive flow in the source line changes suddenly. Hence, the Reactive Power
Calculator has to extract the reactive component of the source current rapidly.The reactive command was shown
as a VAr flow till now. However, the reactive component of the line current is enough for control purposes. A
simple method to extract the reactive content in the current is explained here. Let the source current in one phase
be i(t) = I
0
+I
1
Sin (t+
1
) +I
5
Sin (5t+
5
) + I
7
Sin (7t+
7
)+....... This covers the possibility of a nonlinear load
which draws harmonic currents and D.C. offsets too. Form the product of this current with unit amplitude cosine
wave which is at 90 degrees in phase with that phase voltage. This product signal is called p(t).
P(t) = I
0
Cost+I
1
Cost
Sin (t+
1
) +I
5
Cost Sin (5t+
5
) + I
7
Cost Sin (7t+
7
)+......
The integral of this product over integral number of fundamental periods will have content only from
(I
1
Sin
1
)/2 since all other products have zero average over fundamental period.Thus, the strategy is to form this
product,integrate it for one period,sample the integrator output and hold the sample,reset the integrator after
sampling and allow it integrate the product for the next period.The sampled integrator output will be a quantity
proportional to the reactive component of the current.This out put can be used as the reactive power signal in the
SVC control block.The sampling and integrator reset are performed at zero crossing of sine wave and the
product current is taken with the cosine wave.The cosine wave has to be pure,without harmonics.The required
sinusoidal templates are obtained by PLLCounterEPROMDAC technique already described.
6. SVCs for PQ Enhancement at Transmission/Subtransmission Level
The SVCs discussed until now were configured for compensating the reactive power taken by
a load and for maintaining the utility power factor at unity. Even in this configuration SVC results in PQ
enhancement since it can respond rapidly to a rapidly varying load like arc furnace;large hammer mills,stone
crushers,ball mills etc;large motors with frequent starts/stops etc.These are potentially troublesome loads from
Power Quality point of view.They can cause flicker and sag .Fast responding SVC renders support to bus voltage
against these loads.
However, at transmission/subtransmission level the issue of providing voltage support at buses
is addressed more directly and SVCs are connected to deliver/take as much reactive power to/from the bus as
required to maintain the bus voltage within predecided limits. SVC does not try to maintain the power factor at
the bus at unity anymore. Rather, it tries to maintain the bus voltage by injecting leading or lagging VArs into
the system. In this case there will be an outer control loop which senses the bus voltage, compares it with a set
value and processes the error in a PI Controller and sets the reactive reference for the inner control loop. The
effectiveness of a given SVC with a specified rating in providing voltage support at a particular bus will depend
on the short circuit capacity at that bus. Low value of S.C. capacity implies that the Thevenin's impedance
behind the bus voltage is large. In addition, the SVC there will be more effective than similarly rated SVC at
another bus with a higher short circuit capacity. But then, a bus with a higher value of short circuit capacity will
have better immunity against sags/flickers/swells due to problems elsewhere and hence probably does not need a
SVC at all.
ACTIVE POWER FILTERING TECHNIQUES FOR HARMONIC ELIMINATION
Suresh Kuamr.K.S
Asst. Professor,Dept. of Elect. Engg.
R.E.C ,Calicut
1. Introduction
The increasing use of power electronics based loads (adjustable speed drives, switch mode
power supplies, etc.) to improve system efficiency and controllability is increasing the concern for harmonic
distortion levels in end use facilities and on the overall power system. The application of passive tuned filters
creates new system resonances which are dependent on specific system conditions. In addition, passive filters
often need to be significantly overrated to account for possible harmonic absorption from the power system.
Passive filter ratings must be coordinated with reactive power requirements of the loads and it is often difficult
to design the filters to avoid leading power factor operation for some load conditions. Active filters have the
advantage of being able to compensate for harmonics without fundamental frequency reactive power concerns.
This means that the rating of the active power can be less than a comparable passive filter for the same non
linear load and the active filter will not introduce system resonances that can move a harmonic problem from one
frequency to another.
The active filter concept uses power electronics to produce harmonic current components that
cancel the harmonic current components from the nonlinear loads. The active filter uses power electronic
switching to generate harmonic currents that cancel the harmonic currents from a nonlinear load. The active
filter configuration investigated in this lecture is based on a pulsewidth modulated (PWM) voltage source
inverter that interfaces to the system through a system interface filter as shown in Figure 1. In this configuration,
the filter is connected in parallel with the load being compensated. Therefore, the configuration is often referred
to as an active parallel or shunt filter. Figure 1 illustrates the concept of the harmonic current cancellation so that
the current being supplied from the source is sinusoidal. The voltage source inverter used in the active filter
makes the harmonic control possible. This
inverter uses dc capacitors as the supply
and can switch at a high frequency to
generate a signal that will cancel the
harmonics from the nonlinear load.
The active filter does not
need to provide any real power to cancel
harmonic currents from the load. The
harmonic currents to be cancelled show up
as reactive power. Reduction in the
harmonic voltage distortion occurs
because the harmonic currents flowing
through the source impedance are reduced.
Therefore, the dc capacitors and the filter
components must be rated based on the
reactive power associated with the
harmonics to be cancelled and on the
actual current waveform (rms and peak
current magnitude) that must be generated
to achieve the cancellation.
The current waveform for cancelling harmonics is achieved with the voltage source inverter in
the current controlled mode and an interfacing filter. The filter provides smoothing and isolation for high
frequency components. The desired current waveform is obtained by accurately controlling the switching of the
insulated gate bipolar transistors (IGBTs) in the inverter. Control of the current waveshape is limited by the
switching frequency of the inverter and by the available driving voltage across the interfacing inductance.
The driving voltage across the interfacing inductance determines the maximum di/dt that can
be achieved by the filter. This is important because relatively high values of di/dt may be needed to cancel higher
order harmonic components. Therefore, there is a tradeoff involved in sizing the interface inductor. A larger
inductor is better for isolation from the power system and protection from transient distur bances. However, the
larger inductor limits the ability of the active filter to cancel higher order harmonics.
The Inverter (threephase unit or singlephase unit as the case may be) in the Shunt Active
Power Filter is a bilateral converter and it is controlled in the Current Regulated mode i.e. the switching of the
Inverter is done in such a way that it delivers a current which is equal to the set value of current in the current
control loop. This mode of operation of a PWMVSI has been covered in detail in an earlier lecture. Thus the
basic principle of Shunt Active Power Filter is that it generates a current equal and opposite in polarity to the
harmonic current drawn by the load and injects it to the point of coupling thereby forcing the source current to be
pure sinusoidal. This type of Shunt Active Power Filter is called the Current Injection Type APF.
2. A Single Phase Current Injection Type Active Power Filter
SinglePhase topology is assumed for purposes of explanation for the sake of simplicity.
Whatever is covered here will be equally applicable for threephase systems also with minor modifications. A
simplified diagram of a singlephase APF is given in Fig.2 below.
The control system maintains the average voltage across the capacitor constant against
variations in line and filtering load on the APF.The Inverter is gated in such a way that the current IL follows a
reference current waveform set by the concerned control system. The voltage required at the terminals of
Inverter output will be automatically made suitable for maintaining the required current in the Lf line,i.e. the
Inverter is controlled in the 'current regulated' mode. The current delivered by the source I
s
= I
o
 I
L
and it is
desired that this current be a pure sinusoidal wave even when the load draws a highly distorted current wave.
This is accomplished by making I
L
equal to the harmonic current required by the load. Thus,there has to be a
harmonic current calculator which will calculate the harmonic current to be generated by the Inverter in order to
maintain the source current harmonic free. Under a loss free situation, the Inverter does not need to draw any
active power. However,there will be losses in the resistances of inductor,switches etc. and switching losses when
the Inverter is generating current. Unless these losses are compensated , the capacitor voltage will come down
steadily. Hence the control of capacitor voltage involves drawing an in phase sinusoidal component of current
from the source along with the required harmonic currents, i.e. the reference current for I
L
should contain an
appropriate amount of 180
0
component to maintain the D.C voltage across the capacitor.
It is indeed possible to make the Inverter deliver the reactive current demanded by the load
along with its harmonic current requirement by providing suitable reference. In that case APF becomes an SVC 
cumAPF or an APFcumSVC.In fact,it should by now be clear that, whether it does reactive compensation or
not, the operation and control of this APF is almost the same as that of the SVC with Current Regulated Control
covered earlier in the lecture on SVCs. The basic principles involved are the same. But,usually in an SVC
harmonic filtering is not attempted along with Fundamental frequency VAr compensation since the range of
switching frequencies needed for APF action is much higher than the frequency needed for SVC action. The
kVAr rating of SVC for a load will be much higher than the kVA rating needed for an APF.Hence it is better to
use a small kVA rated Inverter with high switching frequency(thereby demanding IGBTs/MOSFETs) for the
APF function and a high power Inverter with low switching frequency for ( thereby permitting the use of
thyristors and GTOs) for SVC action. In fact , if the two jobs are separ ated this way,it is possible to run the SVC
at a still lower frequency with the APF helping to cancel the harmonics generated by the low frequency
switching of SVC partially. Such systems have been made at subtransmission level. Notwithstanding the above,
the continuous improvement in the voltage and current ratings of IGBTs and MOSFET power modules has made
it possible to combine both SVC and APF functions in the same Inverter at distribution levels(i.e. at
440V,1.1kV,3.3kV,6.6kV and 11kV levels).
The control of a singlephase APF using hysterisis current control is given in Fig.3.The D.C
voltage across the capacitor is sensed,compared with reference and the error is processed in a PI controller. This
error multiplies a fixed amplitude sine wave which is pure and is in 180
0
phase with the source. The product
forms one component of the current reference of the Inverter.The harmonic current calculator receives the load
current signal from the CT in the load line and a pure sine wave template from the control system and calculates
the harmonic current component in the load in real time. The output of this calculator forms the second
component of reference current. These two components are added together and given as current reference into a
hysterisis current co ntroller. The working of this control scheme was already explained in the context of SVCs
and is not repeated here.
3. Current Control Schemes Suitable for APF
The above block diagram assumed hysterisis current control and hysterisis current control is
indeed suitable if only low order harmonics (like 3
r d
,5
th
, 7
th
etc.) need be compensated. However,if harmonics
upto 25
t h
or so are to be cancelled ,hysterisis control will require excessively high switching frequency. In
addition, the variation in switching frequency which is basic to hysterisis control makes it difficult to choose
filter components. Hence constant switching frequency,unipolar switching schemes are preferred for
implementing current control of Inverter in APF application as a rule.
In one constant switching frequency current control scheme,the filter inductor current is sensed
and compared directly with the reference current to form the current error. This error is amplified and used as the
modulating signal in the unipolar pulse width modulator which controls the gating of switches. This scheme
suffers from some disadvantages. First,the current sensed will have switching ripple in it and it will have to be
filtered before getting into the high gain error amplifier. This filtering introduces a time delay. Already the
system is of second order due to the L
f
and C
f
.This second order dynamics has sharp phase angle variation near
its resonance frequency due to its underdamped nature. In addition,the phase delay contributed by it depends
strongly on the operating condition. Now if a high gain stage with a first order filter is put in the feedback path ,
the system easily becomes unstable. Even if it is stable, its transient response will not be satisfactory. This will
call for reduction of gain in the error amplifier which will affect the ability of the APF to track the reference
current adversely. If a high gain has to be used then a high switching frequency becomes mandatory.
Secondly,the current that is being sensed is current in a switching syst em and will be corrupted by the inevitable
high frequency switching noise. The control loop usually gets thoroughly upset with this noisy feedback.
These limitations of feedback control scheme provided the motivation for the development of a
feedforward control scheme for the control of current in the Inverters.The principle of this scheme follows.
Assuming the control is successful,the current that will flow through Lf is known apriori and it
is equal to the reference current. Then,if the IL value is known before hand ,the voltage that the Inverter should
generate in order to make this current flow can be calculated and the calculation result(a voltage signal) can be
given as the modulating signal for the unipolar PWM generator. The voltage that the Inverter should generate is
given below by applying K.V.L.
V
inv
= V
ac
+ RI
ref
+ L
f
(dI
ref
/dt) where I
ref
is the current commanded by the control system,R is
the equivalent loss resistance(includes winding resistance,switch power loss etc.) , L
f
is the filter inductance and
V
ac
is the source voltage. A simple Opamp circuit can implement the above equation by accepting a stepped
down version of source voltage and the reference current signal as the inputs .The output of the circuit is given to
the unipolar PWM circuit after suitable scaling. Then the Inverter generates the right voltage and hence the
current in L
f
will have to be I
ref
.
However, this requires the knowledge of accurate values of R and L
f
.The value of R is
operating point dependent (through switch power losses) and can not be known accurately. If these values are
precisely known the current control would have been 'free of dynamics' i.e.,the bandwidth of current control loop
would have been infinite. But there are inaccuracies in the estimation of the parameters and inaccuracies in the
measurement of V
ac
.Also the differentiator operation has to be band limited in practise due to the well known
sensitivity of differentiator to noise and high frequency signals. These imperfections make the current contro l
logic deviate from the ideal and a small amount of actual current feedback will be needed along with the other
components to correct the minor deviations. However, now the role of current feedback is only to correct second
order effects and hence can be of low gain. Moreover, for the same reason no filtering is needed in the feedback
path. With this term added ,the Inverter voltage control equation becomes:
V
inv
= V
ac
+ RI
ref
+ L
f
(dI
ref
/dt) +K ( I
ref
 I
L
) where K is the feedback gain and is usually very
small. This scheme is capable of rise time of 50s 250 s and yields a high bandwidth current control loop
which is highly desirable in APF since APF is expected to track up to 25
th
harmonic and more.
K is the feedback gain,Kpwm is the gain of Inverter and Z
0
(s) is the equivalent load impedance
connected at the a.c source point.
4. The D.C Voltage Control Loop
The D.C voltage control loop in APF is similar to the D.C control loop of SVC or PWM
Rectifier and similar considerations apply. Since the 50 Hz current in the Inverter line of an APF is small ,the
DC side capacitor will not have second harmonic ripple and hence not much filtering is required on this voltage
before it gets into the control loop. By the same reason, the D.C loop control can be faster in APF compared to
SVC.
5. The Harmonic Current Calculator
This is the most important component in the control system. It accepts the load current and
sinusoidal templates from the PLLSine wave generator and returns the value of harmonic content of the load
current for further control purposes. The D.C side capacitor should not be asked to supply even a fraction of the
active power required by the load since it will run down rapidly if that happens. Hence, the Calculator must
ensure that neither under steady state nor under load transient conditions the calculated current will contain an
active fundamental component. However, it is not possible to ensure this under transient conditions strictly. Then
the Calculator must reduce the active component to zero as fast as possible. Any delay on the part of this
Calculator in removing the active power component in its output will be translated as higher and higher value for
the D.C side capacitor.
K
R/KsKpwm
(Lf/KsKpwm)d/dt
Kpwm
R
Ks 1/sLf
Zo(s) 1/Kpwm
+
+
+
+ +
Iref
+
+
+
 

+
+
+
IL
Fig.4 Feedforward Current Control Scheme
+
+
The method for extracting the reactive fundamental component contained in a sinusoidal
current was described earlier in connection with SVC.The same strategy can be used here too. The sensed load
current is multiplied with unit amplitude sine and cosine waves. The products are integrated over one cycle. The
value of integrated outputs are sampled and held at the end of the cycle period and after sampling the integrators
are reset briefly to start the next cycle of integration. The sampled outputs will be the amplitude of active and
reactive component respectively. The unit sine and cosine templates are multiplied by these amplitudes to re
create the active and reactive fundamental components and their sum is subtracted from the total load current.
The result will be the instantaneous harmonic content in the load current and this is sent to the output.
Obviously, the maximum delay in the calculation is one cycle time.
6. Determining Active Filter Ratings for Nonlinear Load Types
One of the confusing aspects of applying active filters is trying to figure out the active filter
rating that is required to compensate for the harmonics from a particular load. A parallelconnected active filter
should be rated in terms of the rms current it can provide. Then the task is to figure out the rms current required
to compensate for the harmonics from different types of loads. Simulations will be needed for a number of
typical nonlinear loads to develop some guidelines for active filter ratings.
One advantage of the parallel connected active filter, as compared to passive filters, is that it is
selflimiting in terms of the harmonic cancellation provided. There is no concern for overloading the filter due to
harmonics from the utility supply system or under rating the filter for the loads involved. The worst case
scenario if the filter is under rated is that it just won't completely compensate for all the nonlinear load current
harmonics. In fact, it may not be necessary to compensate for all the harmonics from a nonlinear load. With the
active filter, the size can be selected to achieve any desired level of cancellation. One good way to use this
concept would be to provide only enough compensation so that the load/filter compensation was within some
specified guidelines for harmonic generation (e.g. IEEE 5191992).
7. Effect of Load Waveform on Filtering Effectiveness
The effectiveness of the active filter in compensating for harmonic components of the load
current depends on the specific load current waveform involved. Two different waveforms may have the same
rms harmonic content but the active filter may do a better job of compensating for one of the waveforms because
of the waveshapes involved.
An ac
voltage regulator is used for
illustration. Two cases are
compared in Figure 6. The
only difference between the
two cases is the load of the
ac regulator. In the
waveforms on the left side
of the figure, the load is a
pure resistance. The
waveforms on the right side
are for the case where the
load is a series combination
of resistance and reactance.
The performance is much
better for the smoother load
current waveform (RL
load). It is worthwhile to
note that the majority of
applications for the active
filter will involve
waveforms like thoseon the
right hand side of Figure 6
(e.g. adjustable speed drives
with diode bridge rectifiers or Fig.6 APF Performance for an a.c voltage regulator with R & RL Load
single phase electronic loads),
rather than the left side.
In general, the current waveform of an ac regulator with resistive load is an example of the
waveshape that poses the severest challenge for an active filter. The problem is the high di/dt that is required of
the filter to compensate for the high di/dt at turn on of the regulator. The problem is most severe when the
regulator is turned on with a firing angle close to 90 degrees because this is when the available driving voltage
stored on the dc capacitor is at a minimum. The output di/dt capability can be raised either by increasing the dc
voltage setting or by reducing the size of the interfacing inductance. The limiting factor for increasing the dc
voltage is the voltage withstand capability of the IGBT devices. The limiting factors for reducing the interfacing
inductance include the IGBT di/dt withstand capability, control requirements, the interface passive filter
requirement, and overall system stability. If the interfacing inductance becomes too small, the dc voltage cannot
be kept constant for normal operation.
8. SteadyState Rating Requirements
The best way
to provide a rating for an
active filter is in terms of
the rms current that it must
provide to compensate for
harmonics from nonlinear
loads. Table1 provides a
convenient summary of
different nonlinear load
types with example
waveforms and typical
levels of harmonic current
distortion associated with
each load. Using these
typical waveforms, it is
possible to calculate a
theoretical value for the
required harmonic
compensation from the
active filter. The summary
includes the THD for each
nonlinear load waveform
and the required active filter
rating in rms amps per kVA
of load rating. These ratings
assume that the active filter
rating should be based on
the total rms harmonic
current content of the load.
A simulation waveform
illustrating the active filter
effectiveness for each of
these waveforms is also
provided. The ratings in
Table 1 assume ideal active
filter characteristics. That is,
they assume that the active
filter can compensate for
every amp of harmonic current created by the nonlinear load.
Table 1
===================
SERIES ACTIVE POWER FILTERING BY HARMONIC VOLTAGE INJECTION
Suresh Kumar.K.S
Asst.Professor,Dept. of Elect. Engg.
R.E.C.,Calicut
1. Introduction
In Shunt Active Power Filtering ,the Inverter injects harmonic currents required for elimination
of harmonics in the source current and injects it at the node where the load is connected. The current drawn by
the Inverter is forced to contain a small inphase sinusoidal component in order to draw enough active power
from source to supply losses in the APF and to mai ntain the D.C side capacitor voltage constant. Series APF is
the dual of Shunt APF.
In Series APF the Inverter injects a voltage in series with the line which feeds the polluting
load through a transformer. The injected voltage will be mostly harmonic with a small amount of sinusoidal
component which is inphase with the current flowing in the line. The small sinusoidal inphase (with line
current) component in the injected voltage results in the right amount of active power flow into the Inverter to
compensate for the losses within the Series APF and to maintain the D.C side capacitor voltage constant.
Obviously, the D.C voltage control loop will decide the amount of this inphase component.
Depending upon the location of Series APF, nature of bus voltage and nature of load the
purpose of injecting harmonic voltage in series with the line can be one of the following.
(i) In this case the distribution bus (say 11 kV) is polluted and has nonnegligible harmonic
content. It is required to clean up this volt age before it reaches sensitive loads. Essentially we want to
remove the harmonic content in the voltage at the distribution substation before it is fed into a feeder
supplying harmonicsensitive loads. The bus voltage corruption may have been due to harmonic current
generating loads upstream. However, the Series APF is not aimed at that harmonic generation problem;
but is applied to protect other chosen loads from the already present harmonics in the source bus. In this
mode ,the Series APF senses the bus voltage and line currents and injects the right amount of harmonic
voltages in series with the line in such a way that the voltages after the filter will be harmonic free and
clean.Fig.1 shows the power circuit and control blocks of a Series APF working in this mode. This mode
of operation can be termed Harmonic Cancellation Mode since the Series APF in this mode cancels the
harmonics present in the source voltage before it gets to the load.
(ii) In the second context, a Series APF is used to help a shunt connected Passive Filter in diverting
the harmonic currents generated by a nonlinear load. Tuned LC filters are supposed to have zero
impedance at the tuning frequency. However, they will have nonzero value due to losses in the
inductor. Hence, the tuned filter shares the harmonic current with the line and source impedance instead
of absorbing it entirely. Moreover, the filter is easily detuned with ageing of components and
degradation in capacitors. In addition, changes in system frequency make the filter detuned. If the filter
is detuned, the harmonic current generated by the nonlinear load will flow in the source path partially
thereby reducing the filtering effectiveness of the Passive Filter.One way to increase the effectiveness
of the Passive Filter and make it absorb all the harmonic current is to insert a high impedance in series
with the line (source) before the load. Of course, this high impedance should be there only for harmonic
current flow and it should go to a zero value for fundamental current flow.
The Series APF in this mode of operation, senses the harmonic current flow in the line and
forces the Inverter to injects (through a transformer) a harmonic voltage proportional to this current in
series with the source in direction to oppose the current flowin short the Series APF simulates a high
resistance in series with the line for harmonic currents alone. With this high resistance in the source
side, the Passive Filter is forced to absorb all the harmonic current generated by the load even it has a
non zero impedance at the harmonic frequency due to detuning.
Of course, the load voltage will become distorted if the filter impedance is not zero. Moreover,
a single tuned LC filter will take care of only one harmonic component. It needs multiple LC filters to
handle all the major harmonics. All the LC sections will derive benefit from the same Series APF.If
there are harmonic components which the Passive Filters can not absorb without distorting load bus
voltage beyond acceptable levels, they will have to be permitted to flow into the source by Series APF
presenting a low or zero resistance those frequency components. The Series APF used in this mode of
operation is called Harmonic Isolator since it isolates the source bus at h frequencies from the polluting
load.
2. The Series APF in Harmonic Cancellation Mode
Fig.1 shows a Series APF in this mode. The source V
S
and inductance L
S
represent the
Thevenin's equivalent of the power system behind the distribution bus. V
sb
is the source bus voltage which
contains harmonics. Lline represents the line inductance of the feeder feeding the load bus.V
lb
is the load bus
voltage.The Series APF injects V
i
in series with the line as shown.SinglePhase topology is considered in the
interest of simplicity.
The line curr ent I is sensed by a CT and converted to electronic level and is fed into a PLL
CounterEPROMDAC type sine wave generator.This block generates unit amplitude pure Sine wave which is in
phase with the feeder line current.It also outputs a unit amplitude Cosine wave.The harmonic content of the
source bus voltage (and thereby the voltage that the APF must inject into line) can be found out by subtracting
the fundamental component of bus voltage from the total bus voltage.This requires the extraction of fundamental
component.
The sensed bus voltage is multiplied with unit Sine and Cosine respectively to extract the
fundamental orthogonal components of voltage.The products are integrated for a cycle duration and the value of
integrals is noted by a sample and hold mechanism at the end of cycle period.After sampling the integrators are
reset and allowed to perform the integration for the next period.The sampled values will give the amplitude of in
phase and quadrature (with respect to line current) fundamental components of voltage.These amplitudes are
multiplied with appropriate sinusoidal templates and added to reconstruct the net fundamental component of
voltage and then it subtracted from the total bus voltage to get the harmonic content.
The D.C side capacitor voltage will discharge down to zero unless sufficient power is drawn
from the line to meet the losses in the Inverter.This power is drawn by injecting a fundamental inphase
component against the line current flow. The amount of this component is decided by a PI controller which
monitors the D.C bus voltage.
The Inverter in the Series APF carries the full line current (after transformation). But the
voltage generated at the output has only a small fundamental component and has mostly harmonic components
(usually 5
th
,7
th
,11
t h
etc.).Therefore the a.c side power in the inverter will be at 4
th
, 6
th
,8
th
harmonic etc. Thus, the
reactive power flow into the D.C. side capacitor is at those frequencies and the ripple across the capacitor can be
made small due to high frequency nature of these power components. Also, the kVA rating of Inverter and D.C
side capacitor will be decided by the harmonic content in the voltage and the maximum line current.
The control system design considerations for the D.C. voltage control loop has been described
already described in other contexts (SVC,Shunt APF,PWM Rectifier etc.) and need not be repeated here. The
crucial control block in this application is the harmonic content calculator. The calculator has to ensure that the
output from it does not contain any inphase component. If it contains that the capacitor will either discharge fast
or overcharge and in order to limit the change in capacitor voltage before the voltage control loop can act ,it will
be necessary to use large valued capacitor. The calculator will ensure that there is no fundamental component in
its output under steady conditions. But under transient conditions (change in line current, changes in bus voltage
etc.), it may output fundamental component. The value of D.C side capacitor will be decided almost entirely by
the dynamic response of this Calculator block.
The most difficult thing about a Series APF is to protect it. Note that it is in series with the line
and has to carry all the load current (fundamental plus harmonic, if any) .Moreover,the fault currents also will
pass through it. It is not enough to shut down the Inverter based on fast over current sensing because if the
Inverter is shut down the transformer primary goes open and secondary imposes a large impedance in series with
the line. A Series APF is to be shorted to take it out of service i.e. it has to be taken out of line and a sort path has
to be put in its place. This can call for fast acting static transfer switches.
The Series APF effectively cancels the entire harmonic content of source bus voltage. Now
what if the load at the load bus is nonlinear ? The harmonic currents drawn by the load via the line will flow
through the Thevenin's impedance of the source (L
s
) and produce further harmonic voltages at the source bus.
But these also will get cancelled by the Series APF.i.e. the Series APF makes the harmonic impedance to its left
side zero. Hence the harmonic impedance of the line plus source is reduced by Series APF and any shunt filter
put at the load bus will have to compete with a lower harmonic impedance in the harmonic current sharing
process. In particular ,if this Series APF is installed at the load bus i.e. after the line ,a passive shunt filter (like
capacitor or tuned LC etc.) is going to be completely useless and all the harmonic current will go into the
line,thereby corrupting the voltage received by other loads which are not protected by a Series APF.
3. The Series APF as a Reactance Compensator
In the last section ,it was pointed out that the harmonic voltage calculator has the inphase and
outofphase sine waves available to it in order to arrive at an estimate of net fundamental component in the
voltage. The injected voltage is harmonic plus a little inphase fundamental component required to draw the loss
power. Now,if the injected voltage reference is made to have a sinusoidal component which is in quadrature with
line current , the Series APF will absorb or deliver fundamental frequency reactive power. It becomes a series
reactive power compensator or equivalently it becomes a reactance at fundamental frequency. Series APF in this
mode can provide series ca in this mode can provide series capacitor/inductor compensation to the line along
with harmonic cancellation. The required voltage reference can be obtained using the Cosine wave template
already available in the control system. Of course, the kVA rating of Inverter and other components will have to
be suitably chosen.
This series compensation capability can be made use of in two ways. In one case, it can be
controlled in such a way that it injects a fundamental voltage in quadrature with the line current in proportion to
the current magnitude. In that case, the Series APF becomes a fixed reactance value at fundamental frequency 
usually capacitive. The application of series capacitors in the transmission lines to improve power transfer
capability,system stability and voltage regulation is well known. Series APF can implement this series capacitor
compensation as explained above.
A second way in which the fundamental Var compensation capability of Series APF can be
employed is by using it to regulate the voltage after the Series APF location at a predecided value. This can be
done by sensing the voltage magnitude downstream ,comparing it with a set value,processing the error in a PI
Controller and using the error to multiply Cos ( t+180
0
) .The product is added along with the harmonic
reference coming from the Harmonic Content Calculator to form the net reference signal for the PWM
Inverter .Thereby the value of effective capacitive reactance at fundamental frequency simulated by the Series
APF is varied to maintain a constant amplitude a.c voltage at a point after the Series APF.
In both ways of implementing the Var compensation action,it is possible to derive additional
advantage from Series APF in the form of a fault current limiting reactance (provided the Series APF has high
overload capability for short duration).When the sensed line current indicates the occurrence of a fault(either by
p.f angle or by its magnitude) the Series APF fundamental reference can be shifted from Cos t to +Cos t.
Then the Series APF will simulate an inductive reactance and thereby limit the fault current.Series APF is used
for this function too in practise.
4. The Series APF in Harmonic Elimination Mode
Fig.2 shows a Series APF in harmonic isolation mode where it serves to isolate the source
from the harmonic currents drawn by the load.it does this by simulating a high resistance in series with the line
for harmonic current flow. Only one tuned passive filter is shown at the load bus and it is assumed that the load
draws one harmonic component predominantly. Otherwise more tuned filters are needed at the load bus.
The source current I
s
is sensed and a pure sine wave is in phase with it is generated by the PLL
subsystem. The sine thus generated is used to extract the harmonic content in the source current using the
orthogonal decomposition method which has been described in the last section. The extracted harmonic
component of I
s
is multiplied by a gain K and that (along with the small fundamental component needed to
draw the loss power) is given as the reference to the PWM Voltage Source Inverter.Thus,the Inverter injects a
harmonic voltage which is proportional to the harmonic current into the line ,thereby simulating a resistance of
value K ohms in the line (only for harmonic current flows).
Now, the harmonic current drawn by the load has two parallel paths to choosethrough the
filter and through the line which appears as a high resistance now. It chooses filter path predominantly even if
the filter is slightly detuned. Thus, the harmonic current into the source is reduced to very low levels.
Similar action takes place in the case of harmonic content in the source. The high resistance
simulated by the Series APF will absorb all the harmonic voltages present in the source bus and isolate the load
from supply side harmonics. This is a welcome feature since in the absence of Series APF, the tuned filter
would have drawn large currents from source if there were source side harmonics. This would have led to
overloading of the filter and would have called for parallel tuned LC section in series with the line to isolate
the series tuned filter from supply side harmonics.
With a series tuned LC filter,there is always a chance of system resonances due to parallel
resonance between line/source inductance and filter components. The Series APF in the resistance simulation
mode will damp these resonances well and will avoid dangerous harmonic amplification.
It is possible to combine series capacitor compensation along with harmonic isolation in this
system by suitably modifying the reference signal to the PWM Inverter.
==================
TOMORROW'S CUSTOM ENERGY CENTER USING EMERGING POWER
ELECTRONICS
Suresh Kumar.K.S
Asst. Professor,Dept. of Elect. Engg.
R.E.C.,Calicut
1. Introduction
(This lecture note is an abstracted version of a report on Custom Power Products developed by
Westinghous e Electric Corporation, Pittsburgh, USA, available at the Internet Web Site
http://www.powerquality.com.This report shows the direction of evolution of power electronics based
systems employed for Power Quality enhancement. It also records experience with distribution level power
electronic systems using high voltage/current power semiconductor devices.)
Traditionally, for power quality problems originating on the utility side of the revenue billing meter, the
approach has been to work on the customer side to desensitise critical loads while "cleaning up" the circuits on
the utility side. However, once these efforts have been accomplished, there are still many situations where it is
not possible to provide sufficient improvement. In these cases, the custom erside solutions usually become very
expensive, e.g. large uninterruptible power supply (UPS) systems, while on the utility side options to build new
dedicated circuits or substations may be very difficult and still not provide the needed degree of improv ement
(isolation).
A survey of utility industrial and commercial customers was conducted by the Electric Power Research
Institute (EPRI) between MayJune, 1992. The purpose of the survey was to determine the criteria used by these
customers in making decisions resulting in the purchase, installation and operation of power conditioning
equipment to assure acceptable disturbancefree electrical service. The results of the survey indicated that
improved quality of electrical service beyond what was available from the utility is desirable. The economic cost
of degraded electrical service to the customer's operations is significant enough to justify major expenditures for
equipment to improve electric service quality. Significantly, the majority of customers questioned stated that
they would prefer a utilityprovided solution as an alternative to the purchase, installation, and operation of their
own (customerowned) onsite equipment for the mitigation of power line disturbances.
2. Custom Power
Products
New technologies
utilising power electronics
based concepts have been
developed by Westinghouse
as part of the EPRI Custom
Power Program for
advanced distribution to
provide additional options
for the utility and its large
commercial and industrial
customers. Known as
Custom Power Products, the
technologies described
provide the utility with the
ability to offer individual
customers or groups of
customers (industrial or
office parks) opportunity to
obtain specified levels of
power quality from standard
service utility distribution
systems. A Custom Power
specification may include
provision for:
No power interruptions
"tight" voltage regulation including short duration sags or swells
"low" harmonic voltages
Acceptance of fluctuating and nonlinear loads without effect on terminal voltage.
The family of emerging power electronic devices being offered to achieve these Custom Power objectives
includes:
Distribution Static Compensator (DSTATCOM) to protect the distribution system from the effects
of a polluting, e.g. fluctuating, nonlinear (harmonics producing), load.
Dynamic Voltage Restorer (DVR) to protect a critical load from disturbances, e.g. sags, swells,
transients or harmonics, originating on the interconnected transmission or distribution system.
SolidState Breaker (SSB) to provide power quality improvement through instantaneous current
interruption thereby protecting sensitive loads from disturbances that conventional electromechanical
breaker cannot eliminate.
SolidState Transfer Switch (SSTS) to instantaneously transfer sensitive loads from a disturbance on
the normal feed to the undisturbed alternate feed.
Figure 1 shows how these devices can be deployed on the distribution system to provide power quality
improvement at the distribution feeder level for sensitive customers.
3. The Distribution Statcom (DStatcom)
The DSTATCOM has been developed by Westinghouse as part of the EPRI Custom Power Program
for advanced distribution. The DSTATCOM is a solid state dc to ac switching power converter that consists of
a threephase, voltagesourc forced aircooled inverter. In its basic form, the DSTATCOM injects a voltage in
phase with the system voltage, thus providing voltage support and regulation of VAR flow. Because the device
generates a synchronous waveform, it is capable of generating continuously variable reactive or capacitive shunt
compensation at a level up to the maximum MVA rating of the DSTATCOM inverter.
The DSTATCOM can also be used to reduce the level of harmonics on a line. The use of high
frequency pulsewidth modulated inverters to synthesise the necessary signal means that the device can inject
complex waveforms to cancel out voltage harmonics generated by nonlinear loads. Because the DSTATCOM
continuously checks the line waveform with respect to a reference AC signal, it always provides the correct
amount of harmonic compensation. By a similar argument, the DSTATCOM is also suitable for reducing the
impact of voltage transients.
When coupled with the SolidState Breaker (installed on the line side of the DSTATCOM) and energy
storage, the DSTATCOM can be used to provide full voltage support to a critical load during operation of the
feeder breaker that protects the distribution feeder on which the DSTATCOM is installed. In the event of a
source disturbance or feeder breaker operation the SSB isolates the DSTATCOM and the connected load
downstream from the breaker and the DSTATCOM supports the entire load from its energy storage subsystem.
The amount of load that can be supported is determined by the MVA rating of the inverters, and the length of
time that the load can be maintained by the amount of energy storage provided.
Connection to the distribution network is via a standard distribution transformer , thereby allowing the
DSTATCOM to be applied to all classes of distribution voltages. At the point of connection, the DSTATCOM
will, within the limits of its inverter, provide a highly regulated stable terminal voltage.
The DSTATCOM is available in ratings from 2 to 10 MVA in modular 2 MVA increments. The power
electronics equipment, coupling transformer and disconnecting switchgear is available in indoor lineup or
outdoor padmount designs. The prototype unit is being assembled in an optional portable trailer enclosure.
4. The Dynamic Voltage Restorer (Dvr)
The DVR has been developed by Westinghouse as part of the EPRI Custom Power Program for
advanced distribution. The DVR is a solidstate dc to ac switching power converter that injects a set of three
singlephase ac out put voltages in series with the distribution feeder and in synchronism with the voltages of the
distribution system. By injecting voltages of controllable amplitude, phase angle and frequency (harmonic) into
the distribution feeder in instantaneous real time via a series injection transformer, the DVR can "restore" the
quality of voltage at its loadside terminals when the quality of the sourceside terminal voltage is significantly
out of specification for sensitive load equipment.
The reactive power exchanged between the DVR and the distribution system is internally generated by
the DVR without any ac passive reactive components, i.e. reactors and capacitors. For large variations (deep
sags) in the source voltage, the DVR supplies partial power to the load from a rechargeable energy source
attached to the DVR dc terminal. The DVR, with its three singlephase independent control and inverter design
is able to restore line voltage to critical loads during sags caused by unsymmetrical linetoground, linetoline,
double linetoground, as well as symmetrical threephase faults on adjacent feeders or disturbances that may
originate many miles away on the higher voltage interconnected transmission system.
During normal line voltage conditions following the sag the energy storage device is recharged from the
ac system by the DVR. Even without stored energy, the DVR can compensate for the variations of terminal
voltage due to load variations by injecting a lagging voltage in quadrature with the load current thus providing
continuously variable series capacitive line compensation. The DVR can also limit fault currents by injecting a
voltage vector during the fault that opposes the source voltage and maintains the fault current to an arbitrarily
low value.
Connection to the distribution network is via three singlephase series transformers thereby allowing the
DVR to be applied to all classes of distribution voltages. At the point of connection, the DVR will, within the
limits of its inverter, provide a highly regul ated clean output voltage.
The DVR can also reduce the level of harmonic voltages on the feeder that would otherwise be seen by
the load. The use of high frequency pulsewidth modulated inverters to synthesise the necessary signal means
that the device can inject complex waveforms to cancel out voltage harmonics generated by nonlinear loads
elsewhere on the interconnected system. Because the DVR continuously checks the line waveform with respect
to a reference AC signal, it always provides the correct amount of harmonic compensation. Similarly, the DVR
is also suitable for mitigating voltage transients.
The DVR is available in ratings from 2 to 10 MVA in modular 2MVA increments. The power
electronics equipment, series injection transformers and disconnecting switchgear is available in indoor lineup or
outdoor padmount designs. An optional portable trailer enclosure is available. A 2MVA DVR in a portable
trailer enclosure with 1 MJoule of capacitor energy storage is designed to provide utilities and industry with a
flexible power quality solution capable of being redeployed as system and customer load changes occur.
5. SolidState "Instantaneous" Current Interruption
Westinghouse has incorporated advanced current interruption technology, utilising high power Solid
State Breakers (SSB), to solve most of the distribution system problems that result in voltage sags, swells, and
power outages. Westinghouse experience in SSB development and applications includes two units delivered in
1992 to provide a "soft start," current limiting, and instantaneous clearing for a 4.16kV distribution feeder to
critical test facilities. Recently the development of the 13.8kV SSB and current limiter has been placed in
service at a large U.S. utility.When combined with a current limiting reactor or resistor, the SSB can rapidly
insert the current limiting device into the distribution line to prevent excessive fault current from developing
from sources of high short circuit capacity, e.g. multisourced distribution substations.
The 15kV class SSB developed by Westinghouse for EPRI is designed to conduct inrush and fault
currents for several cycles and to disconnect faulty sourceside feeders in less than 1/2 cycle. The capability of
the SSB to provide this performance is dependent primarily on the rating and operating characteristics of the
power semiconductor devices used for the AC switches making up the breaker. At the power levels associated
with 15kV and higher voltage class systems, commercially available Gate Turn Off (GTO) thyristors and
conventional Thyristors (SCRs) can be used for the AC switch.
The SSB developed by Westinghouse for EPRI consists of two parallel connected circuit branches: a
solidstate switch composed of GTOs and a solidstate switch using SCRs in series with a current limiting
reactor or resistor. The GTO switch is the main circuit breaker used to clear sourceside faults. It is rated for the
maximum normal line current, but not rated for fault currents. It is normally closed and conducts current
uninhibited until the magnitude of the current reaches a preset level at which point it opens rapidly interrupting
the current flow.
The GTOs are assembled in antiparallel aircooled modules. To achieve the required SSB voltage for
application to the util ity 13.8kV primary distribution voltage up to six GTO modules are required in series
which provides for a oneunit redundancy. The six series modules make up a complete GTO SSB phase pole.
6. SolidState "Instantaneous" Load Transfer
Westinghouse is introducing a line of SolidState Transfer Switches capable of providing
uninterruptible power to critical distributionserved customers. Solidstate, fast acting (subcycle) breakers can
instantaneously transfer sensitive loads from a normal supply that experiences a disturbance to an alternate
supply that is unaffected by the disturbance. The alternate supply may be another utility primary distribution
feeder or a standby power supply operated from an integral energy storage system. In this application, the SSB
acts as an extremely fast conventional transfer switch that allows the restoration of power of specified quality to
the load within 1/4 cycle.
The SSTS consists of two threephase SSB's, each with independent control. The status of the three
individual phase switches in each SSB will be individually monitored, evaluated, and reported by continuous
realtime switch control and protections circuits. The operation of the two SSB's will be coordinated by the
transfer switch control circuit that monitors the line conditions of the normal and alternate power sources and
initiates the load transfer in accordance with operator selectable criteria.
The SSTS can be provided with either SCR or GTO switches depending upon the specific load transfer
speed requirements.SSTS voltage and current ratings are being developed for 4.16 to 34.5 kV and 300 to 1200
Arms continuous.
System protection practices are accommodated in the SSTS available control modes depending upon
the critical load requirements and utility preferences/practices. For example, standard utility practice may
prohibit transferring a customer side fault.
7. The Custom Energy Center
The existence of the Custom Power Products described above make possible the implementation of a
Custom Energy Center that would provide a guaranteed improvement in the quality of electrical service to the
tenants of the industrial (or commercial office) park. The concept envisions a new Custom Energy Center
providing significant benefits in improved power quality over a comparable "standard" electrical service
industrial park. Custom Power Products can provide electric distribution system design and operating
characteristics making possible the offer of a range of power quality. There are, of course, legal, environmental,
land use, licensing, regulatory and other institutional issues that would be associated with such a major
development.
A major benefit to the Custom Energy Center tenant would be that, in most cases, there would no
longer be a need for power factor correction capacitors on the tenant's power system. This equipment is a major
cause of harmonic resonance and overvoltage conditions. Power factor correction could be the responsibility of
the Energy Center and would be achieved by proper application of Custom Power Controllers on the Energy
Center's system.
Restrictions on tenants would include permission to monitor power system conditions within the
tenant's system. If a tenant's load characteristics change (detected by the monitoring system) in such a way that
requires additional enhancement by the Energy Center, the tenant may be moved to a different Custom Power
rate classification since the Custom Power rate would be a function of the degree of "clean up" required by the
tenant's processes and system.
One Energy Center design envisioned would include a utility corridor in the Energy Center with all
Custom Power load class connections available for tenant connection (or reconnection as loads change)
throughout the Energy Center versus designated Custom Power Class areas within the park.
A further benefit to tenants that results from the inplant electrical service monitoring by the Energy
Center operating center is that the tenant no longer needs power system experts or consultants on their payroll.
The Energy Center operating center will provide the necessary inplant power system engineering expertise for
all tenants. This is seen as a very significant plus for the Custom Energy Center concept. Power system
engineering expertise is increasingly difficult to find when needed and surveys show that utility customers prefer
a utilitysupplied solution to their electrical service disturbance problems.
Alternatively, Custom Power rate classifications for the Energy Center could be determined by "levels of
enhancement" in electrical service available from the utility defined simply as:
1. Standard Service
2. Improved Service
3. Premium Service
A measure of power quality, such as a Quality Factor Index, would be assigned to each class of service.
Certain weightings would be identified and assigned to the parameters which define power quality, i.e. sags,
swells, transients, interruptions, etc. A Quality Factor Index would be assigned to each class of service available
from the Custom Energy Center. Customers would then select the desired level of service and justify the higher
(premium) rates due to the improved quality of power available. Their justification for paying higher rates would
be based upon their need for the selected level of service to avoid costly downtime as well as the savings
achieved by not purchasing, operating, and maintaining internal power conditioning equipment.
Any cost comparison of Custom Power service with "standard" service must include both investment and
operating costs of "going it alone" versus the premium rate charges. Operating costs of conventional power
conditioning includes:
1. cost of losses
2. maintenance costs
3. communications costs/SCADA
4. spare parts inventory
5. indirect (overhead) costs associated with equipment, e.g. floor space, air conditioning, lighting, special
fire protection/monitoring, etc.
Costs would be expressed in such a manner to allow allocation over tenant energy consumption, peak
demand, tenant occupied space, sale of "corrected kWhr" or other measures. The cost of providing Custom
Power may include a "loss of business" insurance premium to cover utility liability exposure.
.
=================
POWER QUALITY MONITORING
Suresh Kumar.K.S
Asst. Professor,Dept. of Elect. Engg.
R.E.C.,Calicut
1. Introduction
Power Quality Monitoring involves measurement and recording of steady state quantities like
voltages,currents,powers,energy ,reactive energy etc for the three phases at the point of connection and recording
of harmonics and shortterm & longterm transient phenomenon like dips,surges,sag ,swell,flicker etc.The steady
state measurements can be usually done by dedicated low cost instruments called Power Demand
Analysers.These acquire the three phase voltages through potential transformers and the three line currents
through clamp CTs and digitise them using sampling and A/D conversion.There may be only one A/D channel
and the six signals are handled by mutiplexing.The sampling frequency is usually low at 4 kHz and is shared by
the six channels.Thus,this instrument can return accurate measurements only if the harmonic content in the
system is small.Also,with this kind of multiplexed sampling and A/D conversion it will not have enough data
points to carry out meaningful FFTs.These instruments are basically for energy consumption monitoring for
billing/auditing purposes.
Measurement of harmonics will require higher sampling rates and 6 to 8 independent sampling
and A/D conversion channels or a single very high speed multiplexed data acquisition channel.FFT calculations
can return erroneous values due to windowing and leakage when the sampling frequency is such that non
integral cycles are covered in the data points used for FFT calculation.Usually 1024 point FFT is used in these
Power System Harmonic Analysers.If one 50Hz cycle is to be covered in this many points it requires a sampling
frequency of 51.2kHz.But with this sampling frequency,it is possible to extract components up to about 25kHz
according to Nyquist's sampling theorem.In the power system harmonic measurement ,up to 50
th
harmonic will
be enough.That means that we do not need a sampling frequency higher than1.25 kHz theoretically.Practically
the sampling is done in the range 58 kHz.Say sampling is at 5.12kHz and fundamental frequency is 50 Hz.Then
there will be 10 cycles of signal in 1024 points sent to the FFT calculator and FFT calculation will not suffer any
inaccuracy from leakage(because integral number of waveform cycles are included in the FFT window). But
assume that the system frequency changes a liitle.Now,if the sampling frequency remains at 5.12kHz,the number
of fundamental cycles over which the 1024 FFT data points are distributed will not be an integer and the FFT
will be in error.Usually FFT under this condition reports the presence of even harmonics in the signal when
actually they are not present.This error can be removed if the sampling frequency is always kept locked to the
fundamental signal frequency through a PLL based frequency multiplication scheme.In that case ,when the
system frequency changes the sampling frequency also changes in step, thereby maintaining integral cycle
coverage in 1024 point FFT.Such a sampling scheme is called Synchronised Sampling Scheme and is used in
high end Power System Harmonic Analysers.
The monitoring instruments which monitor the other longterm and short term transient events
like sag ,swell ,outage,subcycle interruptions,flicker,surges etc. are called Power Line Monitors or Event
Recorders.These instruments also will have PT/CT front end with 6 to 8 independent data channels with
dedicated sampling and A/D conversion systems.But the sampling frequency will have to be much higher if
transient events are to be caught and recorded.Sampling frequencies in the MHz range are used in these
monitoring instruments. They typically monitor the line condition and start recording the event data when a PQ
event is detected.The definition of a recognisable PQ event is by setting thresholds in the instrument panel.When
an event is detected sample values from all the channels are stored ( i.e. the waveforms are stored ) till the event
is over.The basic problem in these monitors will be to set the thresholds prop erly. The memory of the instrument
will get filled up in no time if thresholds are set too low.
The above discussion made it out as if these three functions need three different instruments
invariably.Not so.There are comprehensive Power Quality Monitors available (in the price range of Rs. 7 to 10
Lakhs) which can carry out all the above steady state,harmonic and transient recording functions.Specialised
instruments for steady state monitoring,harmonic monitoring and PQ event monitoring are also available at
lower cost.A typical Power Demand Analyser suitable for three phase unbalanced systems with data storage and
PC interface capability along with data viewing software is available for about Rs.1.5 Lakhs in Indian
market.Similarly a Power system Harmonic Analyser which can carry out harmonic measurement upto 25
th
harmonic with data storage capability and PC interface capability comes at Rs.2.5 Lakhs.Single phase and three
PQ event recorders are also available in the price range of Rs.1 to 3 Lakhs.Invariably all these instruments come
along with a data downloading/viewing/processing software (usually Windows version) and some of them
include a software package which rummages through the volume of data stored in the instrument and prepares a
report for the customer automatically based on a Windows Word template.
Using a power monitor without having a high degree of familiarity and experience with it can
often be an exercise in frustration. A major source of frustration is the complicated set up procedure; if the set up
is incorrect, the monitor will not record useful information and the user must repeat the power survey, wasting
time and money. More frustration follows after data has been collected. The user is faced with the challenge of
sorting through a large volume of data and then trying to interpret the information. When investigating a power
quality problem, attempting to find significant events by searching through rolls of paper is tedious and time
consuming.
At the outset of a power survey, the user may not know exactly what to look for or how to set
up a monitor. For example, to ensure a robot on a production line does not malfunction due to power quality
problems such as transients or sags and swells, a monitor must be set up to record events. But how do we
establish the correct limits, and for which events? The problem may be distortion related, in which case the
monitor must record harmonics continuously. The voltage and current harmonics need to be related to the
operation cycle of the robot by comparing Total Harmonic Distortion (THD) to the power consumption
characteristics and Power Factor (PF) over time, as well as the RMS voltage and current.
Similarly, when installing adjustable speed drives, it is convenient to check the harmonic
distortion and notching of the waveform for power quality concerns while monitoring power consumption to
verify energy savings. Until recently, several different instruments were required to monitor power quality,
power consumption and harmonics simultaneously. These instruments all have the same failings, they require
very careful setup, and correlation of data between different types of instruments is difficult.
An approach called "Full Disclosure" power monitoring brings in a new power monitoring
philosophy to overcome these difficulties. It describes an approach with a single instrument, providing
comprehensive measurement in great detail of all aspects of power.This approach has been evolved at M/s
Reliable Power Meters,Los Gatos,California,USA and a Power Quality Monitor implementing this approach is
available from them at about Rs. 7 Lakhs.
2. Elements of Full Disclosure
The two key elements central to Full Disclosure monitoring are:
Breadth of measurements
Depth of measurements
The breadth of measurements refers to the ability to monitor all of the aspects of power, such as:
Power Consumption: e.g., watts, VA, VAR, PF (true and displacement), demand, and kWh
Voltage transients between 0.5ms and 8ms (half a cycle)
Voltage disturbances between half a cycle and 2s (typically wave shape changes and brief RMS events)
RMS voltage events greater than 2s (typically sags, swells, outages, etc.)
Voltage imbalance
Flicker: (periodic voltage fluctuations less than 25Hz as defined by IEC 868)
Ground loops: (Current in a noncurrent carrying conductor; often a problem in large networked
systems, usually caused by the interconnection of multiple peripherals or communications equipment to
processors) Harmonic Distortion: harmonic spectra for voltage and current for all conductors, THD
(Total Harmonic Distortion), TDD (Total Demand Distortion). Tracking of individual voltage and
current harmonics and harmonic power flow.
The depth of measurements refers to the thoroughness of measurement, or the detail of a specific
measurement. For example, newer technologies allow for the use of digital signal processing techniques to
measure RMS on every cycle, and other parameters such as watts, VA, VAR, PF, and THD on a cycle by cycle
basis.
The detail of a recorded transient or impulse event depends on sampling rates.A sampling rate of 8kHz
permits capture of transients and impulses down to 130 micro second duration.This is adequate for capturing
capacitor switching transients on the utility distribution system,but is not fast enough to capture impulses.Peak
capture can provide detection down to 1 ms (Fig.1) ,but does not yield any details on the waveform.To reveal a
detailed view of the impulse waveform (Fig.2) it requires high speed analog to digital sampling techniques at
rates of 2 MHz to 4 MHz to capture impulses down to 500 to 250 ns.Impulse waveforms help the user to
determine the source of the impulse and aids in the selection of proper mitigation strategy.
3. No Limits, No Thresholds
Capturing the amount and details of power quality information is dependent on setting limits
or thresholds. Older technology monitors require users to program thresholds and restrict the information
captured by the instrument. Setting threshold limits is a major source of frustration. If they are set too low, the
instrument collects too much data and runs out of memory or paper. If they are set too high, the monitor may not
record any significant events.
IEEE P1159 acknowledges the problem of determining the correct threshold settings, and
recommends either recording the first 20 events or spending 30 minutes observing event activity and resetting
the thresholds up or down if necessary. This procedure is repeated until the observed rate of capture is about one
event every 30 minutes. The problem with this method is that it requires the operator to be present to observe the
activity and manually manage the monitor's memory. The settings are only applicable for as long as the operator
remains with the monitor. As soon as the operator leaves, conditions may change and the last setting of
thresholds may be inappropriate. There is always the nagging fear with older instruments, that there may be
important information just below the thresholds. Full disclosure monitoring eliminates the threshold problem by
taking advantage of a large memory capacity to capture all events with adaptive thresholds. This allows the
instrument to record all the phenomena and eliminates the need for cross triggering.
The
diagram in Figure 3 shows
the architecture of a full
disclosure monitor that
uses an onboard digital
signal processor, an
internal 540MB hard disk
drive, and an imbedded
386 computer with a
coprocessor and 4 MB of
RAM. The 8kHz sample
and hold circuit and 14bit
analog to digital converter
takes a one cycle
"snapshot" on four voltage
and five current channels
and provides 128 samples
per cycle. The digital
signal processor performs a Fourier Transform on the sampled waveform data to the 63rd harmonic in 100us.
This process is repeated on every cycle. From the harmonics information all other parameters such as RMS,
watts, VA, VAR, PF, THD, etc., are also calculated on every cycle. These parameters are logged to provide
longterm summary graphs with one cycle resolution; the cycle by cycle data is summarised to show the
maximum and minimum values recorded on a single cycle, also average values.
4. Plotting Events Against Power Tolerance Curves
This type of monitor conveniently permits events to be plotted against power tolerance curves,
or chronologically, allowing the user to quickly and easily find events by severity or by time of occurrence.
Tolerance curves also provide the ability to view events in a random access fashion. The most common power
tolerance curves in use are the ANSI curve, whi ch defines the maximum excursions of voltage with respect to
time that can be expected at the service entrance from a utility, and the CBEMA curve (Figure 4), which
describes the sensitivity of electronic equipment.
The vertical
axis represents the magnitude
of the event and the horizontal
axis represents the duration of
the event. Therefore, an event
represented by a point plotted
against a curve has two
components: magnitude and
duration. A single point must
represent a steady state event,
and cannot represent an event
that is in flux. A steady state
event is always preceded by a
transition event and ends with a
transition event. We can use
this information to plot events
against a tolerance curve as
follows:
Event capture
operates by recording RMS on
a cycle by cycle basis. If the RMS voltage changes by 2.4 volts RMS on two successive cycles, the monitor
records the individual sample points (for AC sine wave information) and RMS values until the voltage stabilises
below 2.4 volts RMS on two successive cycles. Note that while events are recorded in this way, the monitor
continuously maintains recording RMS on a cycle by cycle basis.
Figure 5 shows a voltage sag of 107V RMS. Before the sag the voltage is at 120V RMS. The
beginning of the first transition
event is marked when the RMS
changes by 2.4 Volts and ends
when the RMS voltage reaches
107V and ceases to change. The
second transition from 107V to
120V is recorded in the same
way.The steady state event
between the two transitions has
a magnitude and a duration that
can be plotted against a
tolerance curve.
When a
plotted point is selected, the
RMS and AC waveform
information are linked together
by software to provide a graph
of the steady state event along
with the two transition events.
The transition ev ents can be expanded for further detail.
Instruments that require thresholds or limits to be programmed capture transient events but do
not track the steady state events; they capture by exception and exclude continuous recording. Setting limits and
thres holds also eliminates vast areas of a power tolerance curve because manual trigger values would be much
higher than 2.4v resulting in less data being collected. The duration and detail of transient events, and hence their
representation, depends entirely on the threshold settings.
A new curve has been proposed by the Information Technology Industry Council (ITIC) to
supersede the CBEMA curve. New families of curves are now beginning to appear from suppliers of sensitive
electrical and electronic equipment, such as lighting systems, robots and semiconductor equipment, describing
the power requirements for satisfactory operation. Modified ANSI curves are also being used to describe power
delivery limits from utilities, as well as backup and emergency power systems.
Curve editing software has been developed, allowing users to create any type of curve they
desire, or edit and resuperimpose a curve at any time after the power survey data has been collected. Curve
editing and full disclosure capture of power quality provide the basis for melting and monitoring any tolerance
curve, and provide a means to quickly and easily check that power delivery systems or sensitive equipment are
within expected or required tolerances.
5. Adaptive Thresholds
Event capture is limited to 1500 voltage triggered events per channel; for threephase plus the
neutral to ground channel a total of 6000 event is stored. (The total number of stored event plots is actually
12,000 as current is simultaneously captured along with voltage to provide dual trace plots.) Low, sensitive
thresholds are necessary for full disclosure monitoring. However, it is conceivable that when a high level of
activity is generating many events, the instrument memory could become saturated. This is a severe problem
with older monitors that will completely fill memory in 4 seconds and cease monitoring if thresholds are
incorrect.
The solution is "adaptive thresholds." These thresholds start at very low values and if the rate
of incoming events cause the memory to overflow before the monitoring period is over, the software raises the
thresholds in 0.125V increments on successive cycles to regulate the rate of capture of events. When event
activity slows down, the thresholds begin to lower in 0.125V increments; the threshold levels are constantly
readjusting to match the event activity and rate of capture to memory capacity.
Adaptive thresholds manage the instrument memory without the need for an operator's
presence. They prevent the monitor from coming to a halt in noisy, high activity situations, and ensures the
monitor will complete its monitoring cycle. In such a scenario the monitor, in effect, captures the worst case,
most severe events, but provides a continuous cycle by cycle record of RMS voltage and current history, plus
power consumption for the entire monitoring period.
6. Automatic Reports
Integrating the instrument with computer technology permits the data to be stored in PC type
files, allowing the data to be easily transferred to a word processing or aspreadsheet program. An automatic
report writer has been developed that sorts through the entire volume of survey data and builds a complete report
with text and graphs in a few minutes under Microsoft Word using a template. The report writer is organised into
chapters that can be selected to create as broad or as focused a report as the user desires. An automatic report
writer increases productivity and helps make sense of large volumes of data.
The user may also program in limits in the report writer to report on only those events outside
the limits. New technologies allow the limits to be set "after the fact" to operate on the captured data, and give
the user the option of compiling another report with a new set of limits.
(Note The information obtained from the Internet Web Sites http://www.powerquality.com and
http://www.reliablepower.com were used in the preparation of this lecture note and these web sites are
acknowledged.)
==================
UNINTERRUPTED POWER SUPPLIES (UPS) FOR ENHANCEMENT
OF POWER QUALITY
Suresh Kumar.K.S
Asst.Professor,Dept. of Elect.Engg.
R.E.C.,Calicut
1. Introduction
UPS is probably the only solution available to an individual customer faced with the problem
of ensuring high quality of power for critical loads.There are three broad categories of UPS topologies  Off
Line,OnLine and Line Interactive.There is considerable ambiguity on what is a line interactive UPS in the
Industry even now.However things are clear when it comes to the other two.
All UPS topologies contain a D.C to A.C Inverter which supplies the critical load from a
battery when the line power is either absent or of too low a quality.All the topologies contain a battery charger to
keep the battery fully charged by drawing charging power from mains when its quality is satisfactory. The three
topologies differ only in the way they serve the load when the mains is present and is healthy.In the pure offline
UPS the load is connected directly to the mains when the mains supply is available and is neither too high nor
too low.When outage/over voltage/under voltage conditions are detected on the mains the offline UPS transfers
the load to the Inverter.When the line is present, the battery charger charges the battery and the Inverter may
either be shut down or will be idling.Thus in an offline UPS there is a load transfer involved every time the
mains is interrupted and restored.This transfer is effected by change over relays or static transfer switches.In any
cas e there will be a brief period during which the load is not provided with voltage.If the load is a Computer
there is a chance that the Computer will reboot if the transfer time is more than about 5ms.In a pure offline UPS
the load is connected directly to mains when it is present and the quality of power to the load is only the inherent
quality of mains.Some modified designs incorporate a limited range of voltage regulation by transformer tap
changing and a certain degree of transient protection by using RFI filters and MOVs.But,essentially in an off
line UPS the load gets high quality supply only when mains power is not available.It is an economical and
simple topology and hence is preferred for small rating ,low cost units aimed at individual PC users'
market.When the load is really critical one an offline UPS is not acceptable.
In an online UPS the Inverter supplies the load always irrespective of whether mains power is
healthy or not.The load is always left connected to Inverter and hence there is no t ransfer process involved.When
the mains power is present it is rectified and put in parallel with the battery.The charging current through the
battery and the load current component come from the controlled rectifier when the mains is present.Hence all
the supply system transients are isolated at the battery node and the Inverter always delivers pure sine wave of
constant amplitude to the load.OnLine UPS affords maximum power quality enhancement to a critical load.The
flip side is that they tend to be somewhat complex in design,higher in cost,lower in efficiency,bigger in size and
tough on the battery compared to offline units.
2. OnLine UPS Topology
Fig.1 shows the online UPS topology in the single phase case.The mains input is stepped down
to a lower level (because (i) isolation is required (ii) the battery voltage is usually low compared to peak of
supply voltage and it may be desirable to run the SCR converter from a lower a.c voltage in order to reduce the
harmonic in the line and to improve the power factor in the mains) and applied to a thyristor based phase
controlled a.c to d.c converter employing (firing angle ) control.The d.c side choke Lf1 smoothes the current
delivered by the converter to near d.c.The PWM Inverter , which usually employs Sine Wave Pulse Width
Modulation using triangular carrier ,runs off the battery node.The output of the Inverter is filtered in Lf3 and Cf2
to remove the switching frequency components before feeding to the load.The PWM Inverter is switched in the
frequency range 520 kHz depending on the power rating and hence the d.c side current drawn by the Inverter
will contain switching frequency components.The capacitor Cf1 and inductor Lf2 prevent the switching
frequency currents from reaching the battery.The inductor Lf2 is usually small in value since it has to provide a
high reactance only at switching frequency.Quite often it is dispensed with and a large valued capacitor Cf2
along with the inevitably present battery internal resistance will be sufficient to filter the high frequency
components in the d.c side current of the Inverter.
The a.c side load on the inverter draws sinusoidal current (assuming linear load) and the
instantaneous power output is a sin
2
wt waveform.By the principle of power conservation,neglecting filter
energy storages and power losses in the Inverter,the d.c side instantaneous power must be equal to a.c side
power.Hence d.c side current will contain a sin
2
wt wave shape (embedded in the switching frequency ).The
switching frequency components go into Cf2 and the sin
2
wt component goes into the battery node.If Lf2 had a
large value it would have forced the Cf2 to absorb the 100 Hz component in the sin
2
wt wave shape and then the
current from the battery node would have been d.c.But the value of Lf2 is not high enough in practise since it is
required to provide a high impedance only at switching frequency. Thus 100 Hz component also flows from
battery node.Thus at the battery node the incoming current from the converter is almost d.c and the outgoing
current to the Inverter has prominent ripple along with d.c content.The difference in the average values of
incoming current and outgoing current will go into or out of battery as the charging or discharging current.The
control system will ensure that this difference is such that the battery will get a charging current (if it needs it).
But along with this charging current, the second harmonic component of d.c side current of the inverter also will
flow into the battery because the d.c side choke on the converter output will not permit it to flow into it.This
second harmonic is quite large in value (as large as the power bearing d.c component) and this represents
unnecessary strain on the battery even when the power is drawn from mains only and even when battery is
floating with full charge and zero charging current.This is one of the major disadvantages of this topology since
it affects the battery life adversely.
This problem of ripple current in the battery is severe in the case of a UPS with a short backup
time.Consider a 500VA UPS designed for 0.6 lag p.f and 15 minutes backup time running from a 24V battery. .
At full load, assuming about 80% efficiency the average content at the input of Inverter will be about 16
amp.The battery will have an AH rating of 7AH.And the battery will carry a second harmonic ripple of about 16
A amplitude when the mains is present and the output load is 300W resistance.The ripple will be more if there is
reactive load also at the output.The ripple current is more than two t imes the AH rating of the battery and battery
life will suffer considerably with this level of idle ripple current.Note that the d.c charging current in the battery
will be 0.7 amp only (about 10% of AH rating).A solution to this problem is to isolate the battery from the
converter output by means of a power diode in such a way that when mains is available current will not flow
from/into the battery from that node.This is accomplished by controlling the converter output voltage to be above
the battery voltage level and back biasing the diode with the difference.when the supply goes off the converter
output voltage falls ,the interconnecting diode gets forward biased and battery takes over the job of supplying the
inverter smoothly.The minus points of this scheme are the power loss in the interconnection diode and the need
for a separate charger circuit for the battery.But the required charging current is low (usually between 0.5A to
2A) and simple charger schemes can be used to do the job.In the absence of battery to absorb the d.c side current
ripple from the inverter ,the capacitor Cf2 should be large enough to absorb the ripple without distorting the d.c
bus voltage much.If there is distortion in the d.c bus voltage the inverter output will get distorted with third
harmonic content
When the mains is present, the load power flows though the converter, reaches the battery
node and from there flows into the Inverter i.e. there is double conversion of power.The converter, Inverter and
the two level shifting transformers incur power losses in this process.Hence the efficiency of this topology is
lower than in offline topology.And the power loss in the battery due to the flow of ripple current as explained
above results in further deterioration of efficiency.
The control of the Inverter is straight forward.The SPWM inverter modulation index is varied
to maintain the output voltage amplitude constant against variations in the output load and battery voltage.The
control of input converter is based on sensing the batt ery bus voltage and battery line d.c current.In a properly
designed control system the battery voltage is measured and compared with a set float value.The error is
processed in a proportional controller and the processed error decides the charging current that should flow into
the battery.This decision is influenced by the manufacturer's recommendation for charging the battery.Thus the
battery voltage control loop provides an output which becomes the reference input for an inner current control
loop.The inner current control loop has to be a feedback loop with PI control and should control the firing angle
of the thyristor converter in such a way that the battery current is maintained at the required value with zero
steady state error.When the load at the output increases the d.c current drawn by the Inverter from battery node
increases ,thereby causing a decrease in the battery charging current.This dip is sensed by feed back system and
firing angle is increased to such a level that the converter output current rises to the value needed to supply the
increased demand from the Inverter while maintaining the same old value of charging current in the battery.In
this scheme of control the battery never goes into a discharge mode while the mains is present. In addition, the
charging current in the battery will not change with the changes in the output load level on the UPS.
However, many commercial online UPSs available in the market (especially in the 0.5kVA to
10kVA range) dispense with the inner current control loop.The battery voltage is compared with the float voltage
level and the error is used to control the firing angle of the converter directly through a proportional controller.
In this scheme, the battery charging current will decrease with decrease in mains voltage and increase in the
output load. And often it is found that the battery is in discharging mode even when mains is present i.e. the
battery shares the load current with the mains.This happens when the mains voltage is low and/or the output is
loaded to above 75%.If such UPSs function at high loading levels in low supply voltage areas ,the battery will
never get an opportunity to charge up fully and consequently the back up time that the UPS yields will be much
below the rated value.Adding integral control in this scheme can redeem the situation but will bring in stability
problems and attendant issues of control system compensator design.
At high power ratings it is possible to avoid using the output transformer and provide isolation
only at the input side.This will require a 360V battery and the inverter will generate 230V straight from the 360V
battery bus.In fact, high battery voltage becomes unavoidable at higher ratings for reducing the level of current
to be switched in the Converter and Inverter. In addition, threephase input side will be preferred at higher
ratings(above 5kVA) in the interest of improved power factor,lower current harmonics at input and avoidance of
triplen harmonics in the a.c side current.
With stringent harmonic restrictions in the offing, online UPS systems will be required to
comply with harmonic injection standards in future. This will result in a replacing of thyristor phase controlled
converter by Boost type power factor corrector stage to ensure sinusoidal input current at unity power factor.
This system is especially attractive at higher ratings. The boost type PFC can work directly from line generating
current flow into a 360V battery node. The control is much simplified since the battery across the output of PFC
will make a voltage control loop redundant simple current control loop with a battery current reference set based
on the battery voltage will do. The inverter can run directly from the 360V bus and generate 230V output. An
output transformer is optional and is needed only if isolation from mains is essential.
3. The Line Interactive UPS Topology
There are many topologies in the literature, which claim the title of line interactive
UPS.However there is no agreement on the definition. One particularly popular topology, which has found its
way into the market, is described here.
Fig.2 shows the power circuit diagram of a line interactive UPS.The d.c side filter, which will
be needed to avoid switching frequency current flow into the battery, is not shown. In addition, isolation and
level translation, if required, will be effected by a 50 Hz transformer at the output of the inverter.
When the line is present ,the inverter (which is a unipolar PWM voltage source Inverter) is
gated in such a way that the current drawn from the mains will be a sine wave with active component sufficient
to meet the active power demand of load and battery charging and reactive component sufficient to meet the
reactive power requirement of load and to maintain the load voltage at a fixed amplitude. In this UPS the output
voltage is maintained constant by drawing varying amount of reactive power from the line when the line voltage
changes. When the mains go off the Inverter maintains supply to the load uninterrupted and the connection to the
mains will be broken to avoid back feeding into the line.
This UPS maintains almost comparable performance with that of online versions;especially
when isolation transformers are used and can be more efficient. However, the control is more complex.
The control scheme is similar to the scheme used in control of Shunt Active Power Filter using
feed forward current control.(See section 3 in the lecture on Active Power Filtering).The battery voltage is
sensed and compared with its float level to decide the amount of charging current that must flow into it. The
actual charging current is sensed and compared with this desired charging current. The error is multiplied with a
unit amplitude sine template (generated by phase locking the a.c source voltage) and the product forms one part
of current that must flow into the Inverter through the inductance L.
The load voltage magnitude is sensed and compared with a reference value. The error is
multiplied by a unit amplitude cosine template with proper polarity and the product forms the reactive current
that must flow into the inverter.
The two product contributions are added and the sum is given as the current reference into the
current controller, which gates the Inverter suitably. This current controller can be a hysterisis current controller
or feed forward current controller as in the case of SVC,Active Power Filter,PWM Rectifier etc.
The load may be nonlinear like a PC.Then it will draw harmonic currents. These harmonic
currents will flow into the inverter and not into the line since the line current is controlled to contain only pure
sine and cosine contributions. Even if current control is only approximate (for e.g. feed forward scheme without
any feed back from actual current ,in order to avoid a current sensing hardware) the harmonics will flow into
Inverter mostly since the inductance L (which will be much larger than the switching frequency filter inductance
Lf) will present a high impedance to harmonic current flow.
Thus this topology delivers high quality power to load (always from Inverter),maintains the
load voltage constant even when mains voltage varies,maintains constant current charging of the battery even
when the load/mains voltage change and does all this while maintaining the supply line current almost sinusoidal
i.e. it does active power filtering too. The only thing it does not do is to maintain the mains power factor at unity.
But then line p.f can not be unity if load voltage is to be constant when mains voltage varies. It is by controlling
the reactive power flow that the UPS maintain the load voltage constant.
================
PASSIVE FILTERS FOR MITIGATION OF HARMONICS IN POWER SYSTEM
Rijil.R
Lecturer,Dept. of Elect. Engg.
R.E.C.,Calicut
1. Harmonic Filters
Removal of harmonics in power system can be done in two ways.
1. By providing a low impedance path to ground for harmonic signals. For this we can use a passive tuned
filter.
2. By injecting harmonic signals which are 180
0
out of phase with the harmonic signals present in the system.
This can be done by using active filters.
But in the above mentioned two methods the least complicated and most economic method is using
tuned filters. Now, the exact choice of the method to attenuate harmonics or whether attenuation is required at all
is problem and system dependent. There are many instances where harmonic signals are tolerated with because
1. They are very low in amplitude.
2. The feeder under consideration does not suffer from harmonics.
Key factors which decide whether filter is required in a system or not are:
1. The voltage and power level of the system under consideration.
2. The circuit impedance.
3. The level of harmonic current present
3. Basic configuration of a tuned filter circuit
Fig.1(a) Fig. 1(b)
Figures above shows the basic configuration of series and parallel tuned filters. In the diagram
RLC elements may be either discrete elements or they may be equivalent components as seen from a particular
circuit bus. First, consider the series resonant circuit in which the circuit element resistance R and inductance L
may be the Thevenin's equivalent parameter as seen from the system bus at which the capacitor C is applied. The
network is a higher order system composed of many energy storing elements and it is not possible to represent
the Thevenin equivalent R + j L for all frequencies by a single R and L. But the network can be represented as
single R and L for a band of frequencies at which resonance occurs. Characteristic of both series and parallel
tuned circuits is the passage of the net circuit impedance (or admittance) through angle zero at resonance, and the
passage of Z or Y through an extremal value.
The Thevenin equivalent impedance as seen from a particular circuit bus is the driving point
impedance at that bus. This is the diagonal element of the bus ijmpedance matrix, Z
bus
. For balanced three phase
circuits which are operated in a balanced way , no zero sequence signals are present and modelling the ground
circuit is not required. For this case, the Z
bus
matrix is either the positive or negative sequence bus impedance
matrix referenced to ground. This mat rix may be found by forming the bus admittance matrix Y
bus
at the
frequency of interest and inverting this matrix,
Y
1
bus
= Z
bus
This expression gives the driving point impedance at all system buses; if only one such Thevenin equivalent
impedance is required, at bus k , the Ybus matrix may be factored into lower and upper triangular factors,
Ybus = L . U,
And a fictitious injection current may be applied at bus k. Subsequently, the voltage at bus k is solved and this
voltage is numerically equal to the driving point impedance z
kk
,
I
bus
= Y
bus
V
bus
= L U V
bus
From this it can be easily solved for V
bus
and the value of v
k
thus obtained will give the value of driving point
impedance at bus k, z
kk.
4. Shunt Capacitor Filter
The simplest form of filter, which is most often employed, is a shunt capacitor. The main advantages of using
shunt capacitors are
1. simplicity
2. economy
3. reactive volt amperes Q needed by distribut ion & transmission circuits.
When used as a harmonic filter, the shunt capacitor should be sized so that:
The resonance between shunt capacitor and inductive reactance does not occur exactly at an integral
multiple of the power frequency.
The sensitivity of the resonant point of capacitor with variation of capacitance value from its name plate
value due to tolerance of manufacturer, temperature, applied voltage or other factors.
The performance of the shunt capacitors at power frequencies should be evaluated.
When the capacitor is placed near any nonlinear device special care must be given in calculating the driving
point impedance.
An inductor may be placed in series with the capacitor to limit the sudden inrush of current at the time of
energization.
The IEEE 18 should be consulted in detail for the sizing and placement of shunt capacitors. According to
this there are variety of overlapping requirements for shunt capacitors used for power applications (216V
and above) .Important specifications given in this standard relates to the current, voltage and volt amperes
of the shunt capacitor. For continuous operation, maximum voltage limit is 110% of nameplate rated voltage
and limit for the crest voltage is 1.2 2 times the rated RMS voltage. The maximum voltamperes generated
by the shunt capacitor ( sum of voltamperes at the fundamental and the harmonics frequency) is 135% of
the nameplate rating. The total RMS (Fundamental and harmonic) Is limited to 180% of rated current. The
cited limitations are for capacitors rated at 2400V and higher.
If the rated current occurs when rated voltage is applied to it at
0
, we can write the following relationships
I
(1)
= V
(1)
and I
(h)
= V
(h)
Where I
(1)
=Fundamental current component (RMS) V
(1)
= Fundamental voltage component (RMS)
I
(h)
= Harmonic component of current (RMS) V
(h)
= Harmonic component of voltage(RMS)
Now the total reactive power in the presence of one harmonic and the fundamental frequency is
Using only one harmonic above the fundamental frequency, the Rms current and voltage are
Eliminating I
(1)
and I
(h)
, and apply the limitation on reactive volt amperes,
Solve for (V
(h)
)
2
and eliminate (V
(1)
)
2
. The result is
bus
LUV rowk
1
1
1
1
1
1
]
1
...
1
...
0
0
( ) ( ) ( ) ( )
35 . 1
1 1
+
h h
I V I V
( )
( )
( )
( ) ( )
2
) (
2
) 1 ( 2
2 2
) 1 ( 2
h
rms
h
rms
V V V
I I I
+
+
( ) ( )
( ) ( )
( ) ( ) 35 . 1
2
) (
2
) 1 (
2
) (
2
) 1 ( 2
2
) ( 2
2
) 1 ( 2
+
+
+
h
h
rms
h
rms
V h V
V V V
V h V I
This inequality equation holds when the stated limit on reactive power holds for conditions in the case of one
harmonic at frequency h0 , (In addition to the fundamental).
In addition to all these factors, we must consider the protection of the shunt capacitor very carefully
since they are intended to attenuate harmonic signals in the system. At distribution levels, fuses are used to
protect the capacitor. The other point to remember is the loss of life of capacitor when it is operated at elevated
voltages and high currents.
4. Simulation study of a system using a capacitance filter
The system shown in the figure above is used for the simulation study. In the system shown in
the figure a capacitor is placed at the 13.8kv_bus for both power factor improvement and also filtering the
harmonics. For the simulation study purpose we injecting a current of unit magnitude at a frequency of 5
0
. Now
we will be conducting the impedance scan on the system by keeping the system voltage at zero. Then simulation
is done using PSPICE and the plot for driving point impedance and frequency is obtained for various values of
capacitance. This driving point impedance includes impedance of added capacitor also.
) 1 ( 35 . 1
1
1
1
2 2
K K K
+
+
+
rms rms
I
h
V
h
h
5. Single Tuned LC Filters
A series tuned LC filter resonates at
r
,
Usually capacitors and inductors are specified in terms of their reactance at
0
, X
C
and X
L
, it is easy to
specify
The main problem that arises when we use a LC tuned filter is due to the resistance of the physical inductor.
In the case of some specific applications the losses in the inductor is very much of concern. The amount of
power dissipated in the inductor may be excessive for the structure of the physical component. A key
element in the loss evaluation is the Quality Factor of the inductor Q. The quality factor is given by
The loss in the inductor is
In most of the applications, the predominant current in the inductor is at the fundamental frequency;
therefore losses may be reduced substantially by placing an auxiliary LC circuit in parallel with the main
inductor as shown in the figure.
The auxiliary LC circuit shown in the above figure should resonate near
0
; thus the
fundamental frequency current will be by passed through the auxiliary LC circuit. Since the main inductor
will often intentionally have a lower Q in order to have a larger frequency band of effectiveness, its
resistance must be rather high. Therefore, the losses in the main inductor will be high. The use of the bypass
LC circuit avoids this difficulty since the Q of this circuit is very high compared to that of main ind uctor.
This application of the auxiliary bypass circuit will detune the main LC filter, due to this reason, the
impedance of the bypass circuit also must be considered when designing the resonant point of the main
filter.
Now we can think about the effect of quality factor of the tuned filter on the impedance characteristic of
the filter and hence its effectiveness in attenuating unwanted harmonic voltages at the bus. This analysis can
be started from a simple series RLC circuit whose impedance and resonant frequency are
If the frequency is normalized to ',
.
1
LC
r
L
C
r
X
X
0
.
R
X
R
L
Q
L
.
2
2 2
2
L
L
loss
X
Q
V
R
V
Q
X I
R I P
LC
C
L j R z
r
1
1
) (
,
_
The magnitude of the impedance becomes
For ' > 0, there is one minimum of z and this occurs at the resonant frequency ' = 1, and this minimum is
R. We can approximate the frequency band over which the filter impedance is a low impedance by
examining the band of frequencies for which z is near R. Let us define the bandwidth of the tuned filter as
the width of the frequency band for which z < 2 R, now band width, BW, can be readily foun d out: let
z
2
 = 2R
2'
. Solving for '.
In the last equation, there are four permutations of signs on the right hand side  the signs are not
synchronized. This is because the characteristic of z is the same for positive as well as negative
frequencies. Since there are two positive frequencies for which z = 2R, there will be two more negative
frequencies for the same condition. Examining the four values of ', we get
Introducing the quality factor in the above equation
Where
0
'
is the normalized power frequency,
Now it is clear from eqn. 2 that the bandwidth of the filter is inversely proportional to the quality factor of the
inductor. If a sharp filter is required a high Q is required. A broadband filter will necessitate low Q and this filter
will be lossy.
Additional points to be considered in the filter design
2
2
2
'
1
' ) ' (
,
_
C
L
R z
r
'
. 1
4 2
'
'
1
'
'
1
'
2
2 2
2
2
,
_
+ t t
,
_
,
_
L
C R
L
C R
L
C
R
C
L
R
L
C
R BW
L
C R
L
C R
L
C R
L
C R
BW
,
_
,
_
+ +
,
_
+ +
'
1
4 2
1
4 2
'
2
2 2
2
2 2
2
'
1
) 2 (
'
0 0
L L L
Q L
C
Q
L
BW
r
0
'
The continuous losses in inductor.
The possibility of ringing current in the filter due to transients in the system.
The need to select
r
below an integer multiple of the power frequency in order to allow for a guard band
which prevents high currents at the harmonic frequency of
0
.
For the case of a tuned LC filter in which the inductor is bypassed by a tuned LC auxiliary circuit, the analysis is
more complex. The effect of auxiliary circuit cannot be neglected at the resonant frequency of the main LC path.
Consider the fig. 1 in which L and C denote the main tuned filter and La and Ca denote the auxiliary circuit.
Now we will be introducing a convenient notation W to denote C
1
and Wa to denote Ca
1
and for
1
. Then
the impedance of L, C, La and Ca are jL, jW, jLa and jWa respectively. Then the impedance of main
inductor L and its parallel bypass is z
1
,
The resonant frequencies of the bypassed filter occur when z
1
is equal and opposite in sign to jW. Thus,
Introducing the notation
one finds that the resonant frequencies of the bypassed filter are given implicitly by
( )
( )
.
1
Wa La L j
Wa j La j L j
z
+
( )
( )
( ) ( )
LLa
WWaLLa LWa WLa WL LWa WLa WL
Wa La L j
Wa La L j
2
4
2
2
+ + t + +
,
1 1 1
2 2 2
ma mm aa
CLa LC LaCa
( ) ( )
2 2
2
2 2 2 2 2 2 2
4 2
aa mm aa mm ma aa mm ma
+ + t + +
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