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**Conventional versus Vedic mathematical method for Hardware implementation of a multiplier
**

Parth Mehta, Dhanashri Gawali

Department of Electronic and Telecommunication, Maharashtra Academy of Engineering, Alandi(D), Pune, India smilingparth@ymail.com, Dhanashree.gawali@gmail.com

Abstract- Aim of this paper is to compare and prove implementation of normal multiplication and Vedic multiplication (using Urdhva Tiryakbhyam Sutra) on digital hardware requires same number of multiplication and addition operations.It makes difference only for mental calculations. Few VHDL codes has been developed for this. All multipliers has been tested for 16X16 multiplications for comparison. Test vectors has been given through a text file. Implementation has been done for the Xilinx FPGA device, Virtex XCV 300 -6PQ240. Various multiplier implementations such as Array multiplier, Multiplier Macro, Vedic multiplier with full partitioning, Vedic multiplier using 4 bit macro, multiplier using 4 bit macro, fully Recursive Vedic multiplier, Vedic multiplier using 8 bit macro have been tested and compared for optimum area and speed. Keywords- Vedic mathematics, hardware multiplier.

Suppose we have to multiply 12 by 13 (i) We multiply the most significant digit 1 of multiplicand vertically by most significant digit 1 of the multiplier, get their product 1 and set it down as the most significant part of the answer (ii) We then multiply 1 and 3, and 1 and 2 crosswise, add the two, get 5 as the sum and set it down as the middle part of the answer and (iii) We multiply 2 and 3 vertically, get 6 as their product and put it down as the last the right hand most part of the answer. Thus 12 x 13 = 156. It bears a simple extendible form in a similar way for multi-digit multiplication [10].

I.

INTRODUCTION

We appreciate the efforts put by Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja to introduce Vedic Mathematics and acknowledge the work of various people regarding Vedic Mathematics. However conventional mathematics is an integral part of engineering education as most engineering system designs are based on various mathematical approaches. A multiplier is one of the key hardware blocks in most digital signal processing systems. With advances in technology, many researchers have tried to design multipliers which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. The Vedic mathematics approach is totally different and considered very close to the way a human mind works. The multiplication of numbers utilizing conventional mathematical methods (successive additions) needs no explanation. The Urdhva – Tiryagbhyam sutra under vedic mathematics is the general formula applicable to all cases of multiplication. The formula being very short and terse, consists of only one compound word and means “vertically and crosswise”. The application of this sutra will ensure simpler means to solve typical multiplication problems encountered in the engineering environment. A simple example will suffice to clarify the operation

978-0-7695-3915-7/09 $26.00 © 2009 IEEE DOI 10.1109/ACT.2009.162 640

The process is ascent and a descent, going forward with the digits on the upper row and coming crossway with the digits on the lower row. II. CONVENTIONAL VS. VEDIC MULTIPLICATION SCHEME Looking at figure 1(A) below, one can easily realize that Vedic method probably makes difference for mental calculations only. For mental calculations it can be proved more convenient; as we can easily visualize Vedic multiplication line diagram. If one tries to do multiplication mentally, in a conventional method, one would have to remember first row, then second row and like wise; and then add all of them. In this case it might be difficult to remember these many numbers at a time. But in Vedic method, to visualize line diagram and keep adding two consecutive product terms is easier for mental calculations. When it is done one need to memorize only few numbers. So, one may find Vedic multiplication faster or more convenient for mental calculations. However, on digital hardware, it will not result in a new circuit or strategy. Irrespective of whether you are thinking it in a Vedic way or conventional way,

1i Tool has been used for design and testing various multiplier implementations. [e] Array multiplier: It is an array multiplier with each cell operating as one bit multiplier and full adder. f. For simulation. However it is not true. except the fact that here 4*4 bit submultiplication is done using VHDL multiplication operator “*”. [d] Vedic Multiplier using 8 bit macro: Here 8*8 bit submultiplication has been done using VHDL operator “*”. simulated. 1(A) := 16 No. Same code can be used for multiplication of 4*4. 1(A) := 0 9 No. But from implementation point of view.Various simulations are done for early testing. 4 and 9]. III. Whatever difference one gets on hardware is just because of the implementation strategy or coding style. SIMULATION RESULT Few multipliers have been designed using VHDL. Essentially both are same. there is no difference in conventional multiplication and Vedic multiplication. synthesized and implemented on Xilinx 641 The results shown here are post place & route simulations for all the above implementations (a to g). All are 16X16 multipliers. II. which is generalized code for this kind of multiplication. c. Tool used is Xilinx ISE 8. there is no need of added zeros in shifted rows in conventional multiplication method. Figure 1(A) is obtained from [6] itself. random test vectors are applied and for those test vectors.In [6] author has put good efforts to show. Multipliers have been demonstrated for seven different implementation styles and compared.1 (A) Multiplication scheme using conventional method (B) Multiplication scheme using Urdhva – Tiryagbhyam sutra with line diagram Both are combinational multipliers requiring same number of addition and multiplication operations and hence the same amount of hardware. In both cases sub-multiplications can be performed in parallel. [c] Vedic multiplier using 4 bit macro: It is same as that of [a]. There is no difference in both from a circuit designer’s view. of Multiplications in fig. [a] Fully partitioned Vedic multiplier: Here. Synthesis reports and simulations (Post-route simulation) have been done for device Virtex XCV 300 -6PQ240. 32*32 bits and so on. Virtex XCV 300 -6PQ240 to prove above theory is true with practical results. Input has been given through a text file. 16*16 multiplication is done as proposed in [1. 1(B) : = 16 In [7] author has put good efforts to show. From the perspective of digital hardware. In fact it is the same thing. d are based on Vedic mathematical method while e. how Vedic Multiplication can be used for building faster multipliers. 8*8. No. Here each 4*4 bit sub-multiplication is also done using Vedic multiplication. which few people view differently. Design entered in the form of VHDL .performance of the multiplier circuit will ultimately depend upon how effectively you utilize hardware resources on which you are implementing multiplier. author has tried to show that using Vedic multiplication how 4*4 multiplier can be used for building 8*8 Multiplier and 8*8 multiplier for 16*16 multiplier and so on. Both will require same number of sub-operations for performing multiplication operation. each method’s waveforms are compared for speed. This way it shows conventional multiplication requires more number of additions. In [6].1i. We have extended author’s work and made recursive VHDL code. b. Author has generated whole hardware keeping this figure in mind. of Multiplications in fig. For 2*2 bit multiplication separate VHDL code has been written. 16*16. For 1 bit sub-multiplication. [b] Fully partitioned Recursive Vedic multiplier: It is implemented based on [6]. MULTIPLIER IMPLEMENTATION ON DIGITAL HARDWARE FPGA device. Fig. g are based on conventional mathematical method. A. of Additions in fig. 1(B) := 09 No. . of Additions in fig. how Vedic Multiplication gains benefits against conventional multiplication. [g] Multiplier using 4 bit macro: This has been made to demonstrate and compare the multiplier demonstrated in [c] for Vedic and conventional multiplication method. TESTING AND RESULTS: Xilinx ISE 8. Implementations shown in a. Then it is used for building 16*16 multiplier using Vedic scheme as shown in [6]. [f] Simple Multiplier: It is 16*16 multiplication done using VHDL operator “*”. for simulations Modelsim and for synthesis Xilinx Synthesis Tool has been used. AND gate has been used.

[2] S.. ECCTD 2007.169-173.398 ns 88. M. “An efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics” Vol. Vol. [9] M. The difference in hardware is due to the implementation strategy or coding style.B. pp. Tampa. SYNTHESIS RESULT Table. Both require same number of addition and multiplication operations.126-128.1462 – 1465. UICEE 2004 [6] Akhter S. Educ. No. "A High Speed Block Convolution Using Ancient Indian Vedic Mathematics. It is not due to Vedic mathematical method.math.G. Hanumantharaju. 1.C. M.com. Kumaravel. 4. Vedic Maths’: facts and myths.949 ns 25. Dani. Chidgupkar and Mangesh T. Kotiyal.360 ns 39. Delhi.edaindia. Among these. pp. H.. Motilal Banarsidass Publishers Pvt Ltd. H. 2007 [3] Himanshu Thapliyal. of slices out of 3072 384 350 237 180 293 148 183 CONCLUSION No. 2007 [10] Jagadguru Swami Sri Bharati Krsna Tirthaji Maharaja. Nov 14 2008. Srinivas. 826 – 828. pp. N. 2. Renuka. 472 – 475. of Engng. [7] Shripad Kulkarni. Ramalatha Marimuthu.res. Jayalaxmi. REFERENCES (e) (f) (g) Fig. area wise [D] is more efficient but speed wise it is slower than the other two. S. Hence. B. one may prefer macros generated by compiler for hardware multiplier.B.” Design and analysis of a novel parallel square and cube architecture based on ancient Indian Vedic mathematics ” Vol. University of South Florida..January 2001. A B C D E F G No. Hence for FPGA. 2. 48th Midwest Symposium on Circuits and Systems.713 ns Method Fully partitioned Vedic multiplier Fully partitioned Recursive Vedic multiplier Vedic multiplier using 4 bit macro Vedic multiplier using 8 bit macro Array multiplier Simple Multiplier Multiplier using 4 bit macro Vedic mathematical method is not very different multiplication method from normal multiplication from [1] Himanshu Thapliyal. [B] is more optimized for area and speed compare to [A]. [E] and [F] implementations are found to be the most efficient in terms of area and speed. vol. 642 . [B] Utilizes less granular addition macros than [A]." ICCIMA. "VLSI Implementation of High Performance RSA Algorithm Using Vedic Mathematics." ICCIMA. International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007). One India One People.tifr. R.(a) (b) (c) (d) hardware implementation point of view.285 ns 38. [D]. M.2: Synthesis Result S.718 ns 20. “VHDL implementation of fast NxN multiplier based on Vedic mathematic ” pp. “Discrete Fourier Transform (DFT) by using Vedic Mathematics”Papers on implementation of DSP algorithms/VLSI structures using Vedic Mathematics. “Vedic Mathematics for Faster Mental Calculations and High Speed VLSI Arithmetic”. Invited talk at IEEE Computer Society Student Chapter. vol. FL. since it uses more granular macros. International Conference on Computational Intelligence and Multimedia Applications. 20-21. pp. IC Design portal.205 ns 50. Among above all. “Vedic mathematics”. Srinivas.in/ dani). fundamentally it is not a different method from conventional method. www. 2006. of LUTs out of 6144 672 598 391 296 509 265 320 Maximum combinational Path Delay 42. 2005 [4] Thapliyal. 2001.K.8. (available on www. “The Implementation of Vedic Algorithms in Digital Signal Processing” Global J. pp.2 Post place & route simulation waveforms.. Vol 4/6.2. [8] S. Both require same number of sub-operations for performing multiplication operation. Karad. with latest EDA tools. 48th Midwest Symposium on Circuits and Systems. Ravishankar. 2005 [5] Purushottam D.

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