• FRITZE ET AL.

Subwavelength Optical Lithography with Phase-Shift Photomasks
VOLUME 14, NUMBER 2, 2003 LINCOLN LABORATORY JOURNAL 237
O
iricai iiruociaiu\ uas niix the pattern-
ing method of choice for the semiconductor
industry for over three decades, providing a
combination of resolution, cost effectiveness, and
production rate that is unmatched by alternative
technologies. (To learn the fundamentals of optical li-
thography, see the sidebar in the article entitled “Re-
cent Trends in Optical Lithography,” by Rothschild et
al.) By the mid-1990s, demand for minimum feature
sizes below the available exposure wavelengths ush-
ered in the era of subwavelength optical lithography.
In this challenging regime, diffraction effects can dis-
tort the pattern being imaged on the photoresist.
This article discusses resolution enhancement
methods that enable optical lithography to succeed in
the subwavelength regime. We focus on phase-shift-
photomask methods that significantly extend resolu-
tion and overcome such diffraction limitations as the
isodense-proximity effect and the spatial-frequency
effect. We demonstrate how these methods can be
used to fabricate highly scaled complementary metal-
oxide semiconductor (CMOS) devices, emphasizing
a cost-effective implementation for low-volume ap-
plications of interest to the Department of Defense.
The isodense-proximity effect, shown in Figure 1,
is caused by a loss of contrast as feature pitch—the
Subwavelength Optical
Lithography with
Phase-Shift Photomasks
Michael Fritze, Brian M. Tyrrell, David K. Astolfi, Renée D. Lambert,
Donna-Ruth W. Yost, Anthony R. Forte, Susan G. Cann, and Bruce D. Wheeler
■ Optical lithography has been the patterning method of choice for the
semiconductor industry for over three decades. Through a continual decrease in
exposure wavelength and increase in lens numerical aperture, this technology
has kept pace with the exponentially shrinking feature sizes predicted by Moore’s
law. In the mid-1990s, minimum feature sizes on semiconductor chips began to
drop below the available imaging wavelengths, ushering in the era of
subwavelength optical lithography. Imaging in this challenging regime has been
enabled by the development of resolution enhancement technologies (RETs)
that work to overcome diffraction limits on imaging resolution. We have
developed, as part of a Defense Advanced Research Projects Agency–sponsored
program in advanced complementary metal-oxide semiconductor (CMOS)
technology, phase-shift-photomask optical lithography processes capable of
imaging features as small as 16% of the exposure wavelength. We have applied
these processes to the development of advanced silicon-on-insulator (SOI)
device technology utilizing standard commercial optical lithography equipment.
We are also exploring methods of cost-effective implementation of this type of
resolution enhancement technology for applications that require high-resolution
imaging for relatively small quantities of wafers.
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
238 LINCOLN LABORATORY JOURNAL VOLUME 14, NUMBER 2, 2003
length of the feature plus the distance between two
adjacent features—decreases. The effect occurs when
dense and isolated features of identical size on the
photomask image with differing sizes on the wafer.
The spatial-frequency effect occurs because of the
finite spatial bandwidth of the optical projection lens.
The lens system behaves as a low-pass spatial fre-
quency filter acting upon the photomask features; the
high-order spatial frequencies are not passed by the
projection lens. The image patterned on the photore-
sist is therefore distorted—sharp corner features are
rounded (corner rounding) and narrow line ends are
shortened (line-end pullback).
To compensate for these effects, the optical lithog-
raphy community has developed a number of resolu-
tion enhancement technologies (RETs), including
optical proximity correction, off-axis illumination,
and phase-shift masks [1]. Figure 2 illustrates the op-
tical-proximity-correction method, which involves
adding correction features to the photomask, such as
mousebites, hammerheads, serifs, and scattering bars,
so that the pattern imaged on the photoresist more
closely resembles the desired pattern. When the re-
quired feature sizes are significantly below the imag-
ing wavelength, the correction features become more
intricate and the pattern on the photomask bears
little resemblance to the desired pattern on the wafer.
In this case, complex correction software is utilized to
design the photomask, and the photomask becomes
difficult to manufacture. Despite these challenges,
optical proximity correction enjoys widespread com-
mercial use because of its effectiveness in improving
the lithographic process.
Off-axis illumination uses an aperture to force the
illuminating laser beam to strike the photomask at an
angle with respect to the optical axis of the lithogra-
phy system. This technique helps improve the imag-
ing of dense features at a given wavelength. It is
simple to implement since modern lithography sys-
FIGURE 1. Illustration of the isodense-proximity effect. A
cluster of identical features images differently in the photo-
resist than an isolated feature of the same size.
FIGURE 2. Schematic diagram of optical proximity correc-
tion. The spatial-frequency effect distorts the image pat-
terned on the photoresist by rounding sharp corner features
and shortening narrow line ends. The addition of
photomask correction features such as mousebites, ham-
merheads, serifs, and scattering bars produces an image
closer to the desired result.
FIGURE 3. Comparison of conventional illumination source to several types of off-axis illumina-
tion sources. Note that the black areas are opaque, and the other areas are transparent.
Photomask top view
Cross section of photoresist features on wafer
Silicon wafer
Photomask
Actual photoresist
image
Photomask (desired image)
Corner rounding
Line-end pullback
Actual photoresist
image
Scattering
bar
Hammerhead
Mousebite
Serif
Conventional Quadrupole Annular Dipole
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
VOLUME 14, NUMBER 2, 2003 LINCOLN LABORATORY JOURNAL 239
tems feature built-in variable illumination options.
Because drawbacks include increased isodense-prox-
imity effect, off-axis illumination is usually combined
with some form of optical proximity correction.
Phase-shift photomasks represent the greatest reso-
lution enhancement method in the subwavelength re-
gime [2]. This method utilizes the phenomenon of
destructive interference to generate dark-line features
smaller than the wavelength of the illumination
source. In this approach, shown in Figure 4, features
are etched into the photomask glass surface to a depth
D corresponding to a half-wavelength path difference
for the particular illumination source used. For a 248-
nm lithography system, this depth is approximately
244 nm in quartz. When the illumination light shines
through a phase edge on the photomask, destructive
interference causes the formation of a dark-line fea-
ture in the photoresist. Our work involved the sim-
plest of many types of phase-shift masks—the
chromeless phase-shift photomask—in which the fi-
nal photomask pattern, etched in glass, does not con-
tain chrome in the regions with critical dimensions.
The resolution enhancement produced by a phase-
shift photomask is seen in Figure 5, which compares
cross-sectional intensity plots of a narrow, dark-line
feature imaged in the photoresist with a conventional
FIGURE 4. Schematic of a chromeless phase-shift photomask (left) and the features it creates in the
photoresist (right). The depth D of the photomask feature equals λ/2(n – 1), where λ is the illumina-
tion wavelength and n is the index of refraction of glass for this λ. D corresponds to a half-wave-
length path difference for the illumination light used. Note that the single relief feature in the glass
photomask produces two dark-line features in the photoresist, one along each phase edge.
Glass
Dark-line features in photoresist
Silicon
wafer
D =
λ
2(n – 1)
Phase edge
FIGURE 5. Simulated cross-sectional intensity plots of a narrow, dark-line feature imaged with a con-
ventional chrome-on-glass photomask (left) and a phase-shift photomask (right). The phase-shift-
formed dark line is significantly deeper and narrower.
R
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Relative position
–1.0 0 1.0
Conventional chrome-on-glass photomask
10
0
10
–1
10
–2
10
–3
10
–4
10
–5
10
0
10
–1
10
–2
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–3
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–4
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–5
Relative position
–1.0 0 1.0
Phase-shift photomask
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
240 LINCOLN LABORATORY JOURNAL VOLUME 14, NUMBER 2, 2003
chrome-on-glass photomask and with a phase-shift
photomask [3]. The dark-line feature imaged with
the phase-shift photomask is deeper and narrower,
which allows imaging of photoresist features at sizes
that are significantly smaller than the illumination
wavelength.
Because all edge features produce a dark line, only
closed patterns can be imaged with a phase-shift
photomask. Two exposures are typically required; the
second erasure exposure removes undesired features.
Fabrication for the phase-shift photomask is more
complex than for the standard chrome photomask,
and advanced computer-aided design (CAD) soft-
ware is required to decompose and verify the layout.
Applying Chromeless Phase-Shift Photomasks to
Complementary Metal-Oxide Semiconductors
Lincoln Laboratory has pursued the fabrication of
transistors with gate lengths in the 25-nm range. This
research was part of a Defense Advanced Research
Projects Agency (DARPA)–sponsored program in ad-
vanced complementary metal-oxide semiconductor
(CMOS) technology. Lincoln Laboratory collabo-
rated with Numerical Technologies, a start-up com-
pany that developed a novel method of double-expo-
sure phase-shift imaging. We also worked closely with
a photomask company, Photronics Inc., to fabricate
the necessary custom phase-shift photomasks.
Figure 6 shows the basic double-exposure, phase-
shift lithography approach developed by Numerical
Technologies [4]. The desired integrated-circuit fea-
ture pattern is decomposed into two photomask pat-
terns. The minimum-width features are placed on a
primarily opaque (dark field) phase-shift photomask,
and the interconnection and trim features are placed
on a primarily transparent (bright field) chrome
photomask. The first exposure images the narrow fea-
tures on the wafer, and the second exposure images
the interconnection features and trims the undesired
phase-shift edge features. Both exposures are per-
formed before the photoresist is developed. Numeri-
cal Technologies has developed sophisticated CAD
tools to decompose and verify typical circuit patterns
into such double-exposure photomask sets.
The double-exposure phase-shift technology al-
lowed us to achieve isolated 25-nm minimum feature
sizes, which are a remarkable 10% of the 248-nm illu-
mination wavelength used. Gratings with feature
pitch significantly smaller than any previously re-
ported were also fabricated. For our experiments, we
used a Canon EX-4 248-nm stepper, an industry
standard in 1999 and 2000, with a numerical aper-
ture of 0.6 and variable illumination. Compared to
single-exposure techniques, wafer production takes
longer with this method, but the improved patterning
makes it worthwhile for many applications.
Figure 7 shows electron-microscope images of a
ring oscillator circuit with 25-nm polysilicon gate
lengths [5]. The smooth sidewalls of the very small
polysilicon features, shown in the enlarged view, indi-
cate a well-designed pattern-transfer etch process.
These devices are made with fully depleted silicon-
on-insulator technology [6], a type of advanced
CMOS technology in which Lincoln Laboratory spe-
FIGURE 6. Schematic of the double-exposure phase-shift lithography process. The phase-shift and trim photomasks are se-
quentially exposed on the same region of the wafer. The final developed pattern of photoresist on the wafer is a combination of
these two exposures.
Trim photomask
0º 180º Chrome
Phase-shift photomask Final pattern on wafer
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
VOLUME 14, NUMBER 2, 2003 LINCOLN LABORATORY JOURNAL 241
cializes. At the time of this work (1999 to 2000),
these gate lengths were among the smallest features
ever imaged with optical lithography. This type of
phase-shift imaging has since been adopted by major
semiconductor companies, including Intel, United
Microelectronics Corporation, Motorola, Texas In-
struments, Lucent, and Samsung [7–9].
Our results were achieved by optimizing a number
of aspects of the phase-shift imaging process. We
chose to use chromeless features in the phase-shift
part of the double-exposure process, shown in Figure
6. We used an ultrathin photoresist layer (255 nm
thick) that performed well even when highly overex-
posed. Finally, we obtained the most effective illumi-
nation between the two exposures by using highly
spatially coherent light for the interference-based
phase-shift exposure, and light with moderate spatial
coherence for the interconnect exposure.
Figure 8 shows the process latitude for the double-
exposure phase-shift lithography technique. Figure
8(a) plots feature size versus focus for several exposure
doses. We find that a depth of focus in excess of 0.5
µm is maintained even at resist feature sizes of 40 nm
[10]. Figure 8(b) plots feature size versus exposure
dose to show the exposure latitude, the sensitivity of
the phase-shift lithography process to exposure dose.
These data indicate that for the chromeless phase-
shift process, the feature size is set by the exposure
dose and not the photomask feature size. Fitting this
exposure-dose curve with a power law results in an ex-
FIGURE 7. Electron-microscope images of a silicon-on-insulator circuit containing 25-nm polysilicon gate-length features. The
enlarged view at right of one transistor segment shows the desirable smooth sidewalls of these narrow transistor gates.
FIGURE 8. Process latitude for the double-exposure phase-
shift-lithography technology. (a) The plot of feature size ver-
sus focus shows that a depth of focus in excess of 0.5 µm is
maintained even at resist feature sizes of 40 nm. (b) The plot
of feature size versus exposure dose shows that the feature
size is set by the exposure dose and not the size of the
photomask feature. Note the power law behavior of the ex-
posure-dose curve.
140
120
80
60
100
40
20
F
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s
i
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(
n
m
)
100 140 180 220
Dose (mJ/cm
2
)
Dose ∝ (feature size)
–0.73
(b)
200 nm
25-nm polysilicon transistor gate
2 m µ
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(
n
m
)
200
180
120
60
160
100
40
140
80
20
0
–0.5 0 0.5 1.0 1.5
Focus ( m)
11.8 mJ/cm
2
15.4 mJ/cm
2
19.0 mJ/cm
2
20.8 mJ/cm
2
µ
(a)
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
242 LINCOLN LABORATORY JOURNAL VOLUME 14, NUMBER 2, 2003
posure latitude of 7.3 % independent of dose (up to
the critical value at which the pattern suddenly col-
lapses). This type of exposure latitude is in stark con-
trast to that obtained by using conventional chrome-
on-glass masks, where significant overexposure results
in a total loss of exposure latitude.
We used the double-exposure phase-shift lithogra-
phy process to image transistor gates onto the photo-
resist. Figure 9 shows a cross-sectional schematic of
the transistor design [5]. The silicon channel region
under the narrow phase-shift defined gate is quite
thin (7 to 15 nm), which is required to obtain good
electrical performance from a small gate-length device
in this technology. The rule of thumb for such a de-
sign is a silicon channel thickness of approximately
one-fourth the gate length. To transfer this photore-
sist gate pattern to the underlying polysilicon, we de-
veloped a plasma-etch process that further shrank the
40-nm resist features to 25 nm [11]. The etch re-
quired vertical profiles, some lateral linewidth loss,
and the ability to stop on thin 4-nm gate oxides.
Figure 10 shows a series of cross-sectional scan-
ning-electron micrographs of silicon-on-insulator
(SOI) transistors. These devices were imaged by using
the same phase-shift photomask and by simply vary-
ing the exposure dose. Note that the vertical profiles
for the polysilicon gate depict feature sizes as small as
9 nm, which corresponds to only 18 silicon lattice
constants in size and less than 4% of the exposure
wavelength.
By using the double-exposure phase-shift lithogra-
phy process, we were able to fabricate advanced SOI
FIGURE 10. Series of cross-sectional electron-microscope
images of SOI transistors fabricated by using the double-
exposure phase-shift lithography method illustrated in Fig-
ure 6. These transistors were imaged with the same phase-
shift photomask; we were able to achieve the order-
of-magnitude reduction in gate length shown by applying
different exposure doses. Figure 9 illustrates the transistor
design.
FIGURE 9. Schematic cross section of the type of silicon-
on-insulator (SOI) transistor we worked on. The device has
a fairly simple geometry, with key aspects being the phase-
shift defined gate and the locally thinned channel beneath
the gate.
Silicon substrate
Phase-shift-defined
gate
Thinned SOI
channel
Silicon nitride
spacer
4-nm gate oxide
Silicided SOI
Buried oxide
Gate length = 90 nm
Gate length = 25 nm
Gate length = 9 nm
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
VOLUME 14, NUMBER 2, 2003 LINCOLN LABORATORY JOURNAL 243
cantly below the exposure wavelength in this case,
showing the potential for applying phase-shift meth-
ods to quite dense patterns.
Cost-Effective Implementation of
Phase-Shift Lithography
The increased fabrication complexity associated with
phase-shift lithography can add substantial photo-
mask cost. Such increased photomask costs are diffi-
cult to amortize for applications that require a low-to-
moderate number of wafers exposed per photomask.
Application-specific integrated circuits (ASICs) and
system-on-a-chip (SOC) designs, such as those used
in the defense and telecommunications industries, are
produced in low volumes compared with the micro-
processors and memory found in personal computers.
For these applications, many of the advantages of
RET lithography are not economically viable. In ad-
dition, it is becoming increasingly difficult to correct
for image nonuniformities caused by the isodense-
proximity and spatial-frequency effects as feature sizes
become much smaller than the imaging wavelength.
transistors with gate lengths in the 25-nm size regime
specified by DARPA. We could then study the perfor-
mance of highly scaled SOI CMOS technology years
before its anticipated commercial introduction. The
advantages of this technology include low power per-
formance and improved scalability and radiation
tolerance.
Typical transistor characteristics for this design are
shown in Figure 11 for gate lengths of 85, 50, and 25
nm. The decline in performance for gate lengths of
50 nm or less indicates that the transistor design at
these gate lengths was not optimized.
Our device research required us to fabricate prima-
rily isolated narrow features, but we explored dense
grating imaging as well. For practical implementation
of phase-shift technology, narrow features must be
imaged through a wide range of pitch values. Figure
12 shows an example of a dense grating feature that
we fabricated using chromeless phase-shift imaging
[12]. This 212-nm pitch grating was imaged in the
photoresist by a 248-nm lithography tool with a nu-
merical aperture of 0.65. The feature pitch is signifi-
FIGURE 11. Performance test results for transistors of several different gate lengths. The decline in performance for gate
lengths less than or equal to 50 nm indicates that the transistor design at these gate lengths was not optimized.
85-nm gate length 50-nm gate length 25-nm gate length
Not optimized Not optimized
Gate voltage (V)
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–14
–1.0 –0.5 0 0.5 1.0 1.5 –1.0 –0.5 0 0.5 1.0 1.5 –1.0 –0.5 0 0.5 1.0 1.5
50 mV
0.5 V
1.5 V
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
244 LINCOLN LABORATORY JOURNAL VOLUME 14, NUMBER 2, 2003
addresses a number of issues, including high photo-
mask cost and proximity effect distortions [12]. We
have dubbed this method GRATEFUL, which stands
for gratings of regular arrays and trim exposures for
ultra-large-scale integration (ULSI) lithography. In
this method, all critical circuit features are imaged by
using simple one-dimensional phase-shift-grating
template photomasks, which are customized with
subsequent trim exposures. The template photomask
can be reused for a wide variety of designs together
with different trim masks. Simple grating phase-shift
photomask patterns are easier to fabricate and inspect
than arbitrary geometry masks, thus reducing their
cost and enhancing their yield. In addition, because
all fine feature imaging is done with dense gratings,
proximity effects are effectively eliminated along with
the complex photomask features typically used to cor-
rect them. This approach has two restrictions: all fine
features must be placed on the design grating grid,
and all pitch values must be integer multiples of the
minimum resolvable pitch.
FIGURE 12. Electron-microscope cross section of a 212-nm
pitch grating formed by using a chromeless phase-shift
photomask and a 248-nm exposure tool. In this case, the
grating pitch is smaller than the exposure wavelength.
Under the sponsorship of Lincoln Laboratory’s
Advanced Concepts Committee, we have developed
an implementation of phase-shift lithography that
FIGURE 13. Schematic diagram of the GRATEFUL imaging method, a cost-effective implementation of phase-shift lithography.
The acronym stands for gratings of regular arrays and trim exposures for ultra-large-scale integration (ULSI) lithography. Fea-
tures in the x-direction on the photoresist (top) are created by using a horizontal phase-shift photomask (x-oriented grating)
and a trim photomask. Features in the y-direction on a different photoresist layer (bottom) are created using the identical pro-
cess with a vertical phase-shift photomask (y-oriented grating) and a trim photomask. The final result on the photoresist com-
bines features in both directions.
Linewidth =
88 nm
Pitch (linewidth
+ spacewidth) =
212 nm
+ =
+ =
Horizontal phase-shift
photomask
Trim photomask
Vertical phase-shift
photomask
Trim photomask
Photoresist image
Photoresist image
Geometric union of
horizontal and vertical
photoresist features
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
VOLUME 14, NUMBER 2, 2003 LINCOLN LABORATORY JOURNAL 245
A schematic outline of the GRATEFUL method is
shown in Figure 13 [13]. The first step uses a one-di-
mensional grating in the x-orientation combined
with a trim exposure to form a series of narrow line
features in the x-direction. The photoresist is then
baked to make it insensitive to further developing,
and a second layer of photoresist is coated over these
features. The process is repeated with a y-oriented
phase-shift grating and trim. The final result is a com-
plex pattern with critical features in both orienta-
tions. This type of method limits feature geometries
to Manhattan (x-axis and y-axis) orientations.
Figure 14 shows an example of the GRATEFUL
method [12]. In this case, the circuit pattern has nar-
row line features in only the x-orientation. A simple
one-dimensional phase-shift grating was used to-
gether with a conventional trim exposure to create the
fine lines. The larger interconnect features were added
in the second layer of photoresist. Linewidths are
maintained through a large pitch range, which indi-
cates an absence of isodense-proximity effects.
Figure 15 shows a second GRATEFUL example
[13]. Here, fine features in the x- and y-orientations
were formed in separate layers of photoresist. A differ-
ent dose was used in each orientation, resulting in dif-
ferent feature sizes. Because the imaging was per-
formed in two layers of photoresist, spatial-frequency
corner-rounding effects were effectively eliminated,
as shown by the sharp corners. Figure 16 shows an ex-
ample of a circuit pattern with fine features in both x-
FIGURE 14. Experimental example of the GRATEFUL imag-
ing method applied to a circuit pattern with fine features ori-
ented only in the x-direction. Note the absence of isodense
proximity effects as shown by good feature size control
through a variety of pitch values.
FIGURE 15. Two magnifications of experimental example of the GRATEFUL imaging method applied to a test pattern with fine
features in two orientations. The sharp corner features produced in this manner, seen in the magnified view on the right, indi-
cate minimal spatial-frequency effects.
2 m µ 1 m µ
5 m µ
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Subwavelength Optical Lithography with Phase-Shift Photomasks
246 LINCOLN LABORATORY JOURNAL VOLUME 14, NUMBER 2, 2003
and y-orientations. The phase-shift photomask used
to create this pattern was a simple one-dimensional
grating.
We have performed a cost analysis of our template-
based lithography approach and compared it to cur-
rent methods used for critical-level lithography in in-
dustry [14]. We modeled the cost per critical level per
wafer as a function of the number of wafers per
photomask for 90-nm-node technology currently un-
der development. The model assumptions were a
stepper cost of $15 million with five-year deprecia-
tion, 7% maintenance cost per year, and 100% up-
time; a photomask set cost of $2 million, for a 30-
photomask set with highly critical gate and contact
level; a tool throughput of 130 wafers per hour; and a
resist processing cost of $5 per wafer. Labor and
clean-room costs were neglected. We also modeled di-
rect-write lithography, which does not require
photomasks, assuming a tool cost of $15 million and
an optimistic throughput of one wafer per hour.
Figure 17 summarizes the results of this analysis.
Three regions are clearly evident. For very low wafer
volume, direct write is the cheapest method, and for
very high volume, the one- or two-exposure custom
phase-shift-photomask method (currently practiced
by industry) is the most economical. In the large in-
termediate regime, however, template-based methods
such as GRATEFUL are the most cost effective, de-
spite the fact that some implementations require
more than two exposures and possibly two levels of
resist. Figure 17 also shows the results of a survey of
photomask usage conducted by the Semiconductor
Manufacturing Technology (SEMATECH) consor-
tium in 2000. Large peaks in industrial photomask
usage fall within the regime of template-based meth-
ods, and typical defense integrated-circuit applica-
tions at the low end of template methods and the
high end of direct write.
Summary
We have developed a phase-shift lithography process
capable of imaging feature sizes as small as 16% of the
248-nm exposure wavelength. Using this process to-
gether with a controlled etch bias, we have fabricated
transistor gates as small as 9 nm, corresponding to
only 18 silicon lattice constants in size. This lithogra-
phy method has allowed us to fabricate next-genera-
tion SOI transistors by using currently available opti-
cal-lithography equipment. We have also been
developing a method of phase-shift technology that
uses simple reusable template photomasks with fine
features. This method has the potential to make ad-
vanced phase-shift imaging cost effective for moder-
ate-to-low wafer counts per photomask, a situation
encountered in low-volume manufacturing applica-
tions such as ASICs used by commercial and Depart-
ment of Defense systems.
Acknowledgments
We thank Andy Curtis, Sandy Deneault, John
Jarmalowicz, Kyle Keenan, Doug Preble, and Dolly
Shibles for expert technical assistance. The Lincoln
Laboratory portion of this work was supported by
DARPA under its Advanced Microelectronics Pro-
gram and the Lincoln Laboratory Advanced Con-
cepts Committee.
FIGURE 16. GRATEFUL method applied to a circuit pattern
with fine features in both x- and y-orientations. The funda-
mental pitch is 280 nm, corresponding to k
1
= 0.34 for our
system. Note the absence of optical proximity effects.
2 m µ
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
VOLUME 14, NUMBER 2, 2003 LINCOLN LABORATORY JOURNAL 247
FIGURE 17. Comparison of 90-nm node lithography costs for various
fabrication methods: direct write, template photomask, and custom
photomask (top) and results of a 2000 survey of photomask usage con-
ducted by the Semiconductor Manufacturing Technology (SEMATECH)
consortium (bottom). At low wafer volumes, the direct-write method is
the most cost-effective. At high wafer volumes, the one- or two-expo-
sure custom phase-shift-photomask method is the most cost-effective.
Large peaks in industrial photomask usage, which includes application-
specific integrated circuits (ASIC) and dynamic random access memory
(DRAM) and microprocessor unit (MPU) chips, fall within the regime of
template photomasks.
90-nm node technology
0 10
1
10
2
Number of wafers
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• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
248 LINCOLN LABORATORY JOURNAL VOLUME 14, NUMBER 2, 2003
REF ERENCES
1. A.K.-K. Wong, Resolution Enhancement Techniques in Optical
Lithography (SPIE Press, Bellingham, Wash., 2001).
2. M.D. Levenson, N.S. Viswanathan, and R.A. Simpson, “Im-
proving Resolution in Photolithography with a Phase-Shifting
Mask,” IEEE Trans. Electron Devices 29 (12), 1982, pp. 1828–
1836.
3. M.D. Levenson, “Extending the Lifetime of Optical Lithogra-
phy Technologies with Wavefront Engineering,” Jpn. J. Appl.
Phys. 33 (12B, pt. 1), 1994, pp. 6765–6773.
4. H.-Y. Liu, L. Karklin, Y.-T. Wang, and Y.C. Pati, “The Appli-
cation of Alternating Phase-Shifting Masks to 140 nm Gate
Patterning (II): Mask Design and Manufacturing Tolerances,”
SPIE 3334, 1998, pp. 2–14.
5. M. Fritze, J. Burns, P.W. Wyatt, C.K. Chen, P. Gouker, C.L.
Chen, C. Keast, D. Astolfi, D. Yost, D. Preble, A. Curtis, P.
Davis, S. Cann, S. Deneault, and H.Y. Liu, “Sub-100 nm Sili-
con on Insulator Complementary Metal-Oxide Semiconduc-
tor Transistors by Deep Ultraviolet Optical Lithography,” J.
Vac. Sci. Technol. B 18 (6), 2000, pp. 2886–2890.
6. J.M Burns, C.L. Keast, J.M. Knecht, R.R. Kunz, S.C.
Palmateer, S. Cann, A. Soares, and D.C. Shaver, “Performance
of a Low Power Fully-Depleted Deep Submicron SOI Tech-
nology and Its Extension to 0.15 µm,” Proc. 1996 Int. SOI
Conf., 30 Sept.–3 Oct., Sanibel Island, Fla., pp. 102–103.
7. R. Schenker, H. Kirchauer, A. Stivers, and E. Tejnil, “Alt-PSM
for 0.10µm and 0.13µm Poly Patterning,” SPIE 4000, pt. 1,
2000, pp. 112–120.
8. C.-M. Wang, C.-W. Lai, J. Huang, and H.-Y. Liu, “Patterning
80-nm Gates Using 248-nm Lithography: An Approach for
0.13 Micron VLSI Manufacturing,” SPIE 4346, pt. 1, 2001,
pp. 452–463.
9. C. Nelson-Thomas, M. Kling, M. Thomson, R. Wang, N.
Cave, and C.-C. Fu, “Effects of Complementary Phase Shift
Imaging on Gate CD Control,” SPIE 4346, pt. 1, 2001, pp.
464–470.
10. M. Fritze, J.M. Burns, P.W. Wyatt, D.K. Astolfi, T. Forte, D.
Yost, P. Davis, A. Curtis, D.M. Preble, S. Cann, S. Deneault,
H.-Y. Liu, J.C. Shaw, N.T. Sullivan, R. Brandom, and M.
Mastovich, “Application of Chromeless Phase-Shift Masks to
Sub-100 nm SOI CMOS Transistor Fabrication,” SPIE 4000,
pt. 1, 2000, pp. 388–407.
11. D. Yost, T. Forte, M. Fritze, D. Astolfi, V. Suntharalingam, C.K
Chen, and S. Cann, “Dry Etching of Amorphous-Si Gates for
Deep Sub-100 nm Silicon-on-Insulator Complementary
Metal-Oxide Semiconductor,” J. Vac. Sci Technol B 20 (1),
2002, pp. 191–196.
12. M. Fritze, B. Tyrrell, D. Astolfi, D. Yost, P. Davis, B. Wheeler,
R. Mallen, J. Jarmalowicz, S. Cann, D. Chan, P. Rhyins, C.
Carney, J. Ferri, and B.A. Blachowicz, “Gratings of Regular Ar-
rays and Trim Exposures for Ultralarge Scale Integrated Circuit
Phase-Shift Lithography,” J. Vac. Sci. Technol. B 19 (6), 2001,
pp. 2366–2370.
16. B. Tyrrell, M. Fritze, R. Mallen, B. Wheeler, P. Rhyins, and P.
Martin, “Investigation of the Physical and Practical Limits of
Dense-Only Phase Shift Lithography for Circuit Feature Defi-
nition,” JM
3
1 (3), 2003, pp. 243–252.
17. B. Tyrrell, M. Fritze, R. Mallen, B. Wheeler, P. Rhyins, and P.
Martin, “Dense-Only Phase Shift Template Lithography,”
SPIE 5042, 2003, pp. 15–29.
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
VOLUME 14, NUMBER 2, 2003 LINCOLN LABORATORY JOURNAL 249
nniax x. rsnnrii
works in the Advanced Silicon
Technology group. His respon-
sibilities include the design of
analog and digital circuits,
which serve as demonstration
and characterization vehicles
for Lincoln Laboratory's
advanced silicon processes. He
also has responsibilities per-
taining to the development of
high-performance comple-
mentary metal-oxide semicon-
ductor (CMOS) imager sys-
tems. Prior to joining Lincoln
Laboratory, Brian received a
B.S.E. degree in electrical
engineering from the Univer-
sity of Pennsylvania, where he
worked on analog integrated
circuit design for the ATLAS
Large Hadron Collider experi-
ment at CERN. He is cur-
rently pursuing graduate study
at the Massachusetts Institute
of Technology through the
Lincoln Scholars Program.
xicnari vnirzr
is a staff member of the Ad-
vanced Silicon Technology
group. His current responsi-
bilities are in resolution-
enhanced optical lithography,
silicon-on-insulator (SOI)
device engineering, and SOI-
based photonics. Mike re-
ceived his B.S. degree in phys-
ics from Lehigh University in
1984 and M.S. and Ph.D.
degrees in physics from Brown
in 1988 and 1993, respec-
tively. Before joining Lincoln
Laboratory in 1995, he re-
searched the electrical and
optical properties of gallium-
arsenide (GaAs) quantum well
heterostructures in positions at
Bellcore and AT&T Bell
Laboratories.
navin ×. asroivi
provides process engineering
support for advanced metrol-
ogy and the advanced lithogra-
phy area of Lincoln Labor-
atory’s Microelectronics
Laboratory as an assistant staff
member of the Submicrometer
Technology group. For more
than 20 years, he has worked
on projects such as X-ray
lithography, bump bonding,
photonics, and 248-nm and
193-nm lithography process
development. Dave received
his B.S. degree in plant and
soil science from the Univer-
sity of Massachusetts,
Amherst.
nrxrr n. iaxnrnr
manages operations during the
second shift of the Microelec-
tronics Laboratory at Lincoln
Laboratory, which includes
supervising process and main-
tenance technicians as well as
handling any facilities, mainte-
nance, or process-related
issues. Renée also serves as the
cognizant area engineer for
deep ultraviolet lithography,
assisting in the development of
lithographic processes for the
fabrication of advanced devices
throughout the division. She is
also responsible for ensuring
that existing processes are
maintained. Before joining the
Laboratory in 2000, she served
as a process development
technician in the areas of ion
implantation and thin films
for On Semiconductor in East
Greenwich, Rhode Island. She
holds an associate degree in
chemical technology from the
Community College of Rhode
Island in Warwick.
• FRITZE ET AL.
Subwavelength Optical Lithography with Phase-Shift Photomasks
250 LINCOLN LABORATORY JOURNAL VOLUME 14, NUMBER 2, 2003
axrnoxs n. vonrr
was an assistant staff member
in the Submicrometer Tech-
nology group prior to his
untimely death in April 2002.
He began working at Lincoln
Laboratory in 1980 with the
Microelectronics group, con-
centrating primarily on the
development of dry-etched
processes for metals. He also
worked on the development of
noncrystal-lographic dry-etch
processes for gallium arsenide
(GaAs), as well as high-aspect-
ratio dry etching of silicon for
permeable base transistors. He
joined the Submicrometer
Technology group in 1988 to
develop plasma-deposited
electrochromic thin films for
use in 193-nm lithography.
His later work involved devel-
oping silylation processes for
top-surface imaging and the
corresponding dry-etch pro-
cesses for pattern transfer in
193-nm lithography. He
received an A.E. (associate of
engineering) degree in com-
puter engineering from the
Franklin Institute in Boston.
noxxa-nurn w. sosr
is an associate staff member of
the Advanced Silicon Technol-
ogy group, responsible for
developing and integrating
etch processes for fabricating
fully depleted silicon-on-
insulator (SOI) complemen-
tary metal-oxide semiconduc-
tor (CMOS) circuits. She has
been instrumental in develop-
ing poly-silicon gate etch
processes for sub-100-nm
transistors as well as deep-via-
etch processes used to connect
multiple wafer stacks for 3D
circuit integration. Prior to
joining the Laboratory in
1998, Donna worked as a
process engineer for fifteen
years with Lockheed Martin
(now BAE Systems) in
Lexington, Massachusetts, and
before that, with M/A COM
in Burlington, Massachusetts.
At both companies, she spe-
cialized in plasma etching and
deposition for a variety of
technologies, including vana-
dium oxide microbolometers,
mercury-cadmium-telluride
infrared detectors, and gal-
lium-arsenide millimeter-wave
devices. Donna earned a B.S.
degree in materials science and
engineering from Cornell
University in 1983.
susax o. caxx
is an engineering specialist in
the Submicrometer Technol-
ogy group performing material
analysis with high-resolution
electron microscopy, atomic-
force microscopy, and X-ray
photoelectron spectroscopy.
Susan joined the Laboratory in
1989, after working in the
medical field for nineteen
years. She earned a B.S. degree
in medical technology from
Vermont College/Norwich
University.
nnucr n. wnrrirn
is an engineering specialist in
the Advanced Silicon Technol-
ogy group. He lays out the
process monitor sections and
all alignment cells for photo-
mask sets, maintains the
computer-aided design (CAD)
process and rules files, and
does the post-design process-
ing and assembly of other
layouts into the photomask
sets. He earned a B.S. degree
in mechanical engineering
from the University of Massa-
chusetts in Lowell in 1984.

FIGURE 2. off-axis illumination.• FRITZE ET AL. Comparison of conventional illumination source to several types of off-axis illumina- tion sources. When the required feature sizes are significantly below the imaging wavelength. This technique helps improve the imaging of dense features at a given wavelength. Note that the black areas are opaque. serifs. The spatial-frequency effect distorts the image patterned on the photoresist by rounding sharp corner features and shortening narrow line ends. so that the pattern imaged on the photoresist more tion. The effect occurs when dense and isolated features of identical size on the photomask image with differing sizes on the wafer. In this case. hammerheads. closely resembles the desired pattern. A Mousebite Hammerhead Actual photoresist image cluster of identical features images differently in the photoresist than an isolated feature of the same size. It is simple to implement since modern lithography sys- Conventional Quadrupole Annular Dipole FIGURE 3. Subwavelength Optical Lithography with Phase-Shift Photomasks Photomask top view Photomask (desired image) Corner rounding Line-end pullback Actual photoresist image Scattering bar Serif Cross section of photoresist features on wafer Photomask Silicon wafer FIGURE 1. which involves adding correction features to the photomask. The lens system behaves as a low-pass spatial frequency filter acting upon the photomask features. and scattering bars. and the other areas are transparent. and the photomask becomes difficult to manufacture. the high-order spatial frequencies are not passed by the projection lens. complex correction software is utilized to design the photomask. 238 LINCOLN LABORATORY JOURNAL VOLUME 14. Despite these challenges. hammerheads. Off-axis illumination uses an aperture to force the illuminating laser beam to strike the photomask at an angle with respect to the optical axis of the lithography system. Illustration of the isodense-proximity effect. The addition of photomask correction features such as mousebites. Schematic diagram of optical proximity correc- length of the feature plus the distance between two adjacent features—decreases. To compensate for these effects. The spatial-frequency effect occurs because of the finite spatial bandwidth of the optical projection lens. serifs. optical proximity correction enjoys widespread commercial use because of its effectiveness in improving the lithographic process. and phase-shift masks [1]. the correction features become more intricate and the pattern on the photomask bears little resemblance to the desired pattern on the wafer. 2003 . and scattering bars produces an image closer to the desired result. including optical proximity correction. NUMBER 2. The image patterned on the photoresist is therefore distorted—sharp corner features are rounded (corner rounding) and narrow line ends are shortened (line-end pullback). Figure 2 illustrates the optical-proximity-correction method. the optical lithography community has developed a number of resolution enhancement technologies (RETs). such as mousebites.

The resolution enhancement produced by a phaseshift photomask is seen in Figure 5. Subwavelength Optical Lithography with Phase-Shift Photomasks Dark-line features in photoresist D= λ 2(n – 1) Phase edge Glass Silicon wafer FIGURE 4. The depth D of the photomask feature equals λ/2(n – 1).0 0 1. one along each phase edge. this depth is approximately 244 nm in quartz. The phase-shiftformed dark line is significantly deeper and narrower.0 Relative position Relative position FIGURE 5. dark-line feature imaged in the photoresist with a conventional Phase-shift photomask 10 0 10 –1 10 0 10 –1 10 –2 10 –3 10 –4 10 –5 –1. Simulated cross-sectional intensity plots of a narrow. D corresponds to a half-wavelength path difference for the illumination light used. This method utilizes the phenomenon of destructive interference to generate dark-line features smaller than the wavelength of the illumination source. etched in glass. dark-line feature imaged with a con- ventional chrome-on-glass photomask (left) and a phase-shift photomask (right). For a 248Conventional chrome-on-glass photomask nm lithography system. VOLUME 14. When the illumination light shines through a phase edge on the photomask. features are etched into the photomask glass surface to a depth D corresponding to a half-wavelength path difference for the particular illumination source used. Schematic of a chromeless phase-shift photomask (left) and the features it creates in the photoresist (right). tems feature built-in variable illumination options. does not contain chrome in the regions with critical dimensions. Phase-shift photomasks represent the greatest resolution enhancement method in the subwavelength regime [2]. Note that the single relief feature in the glass photomask produces two dark-line features in the photoresist. which compares cross-sectional intensity plots of a narrow. off-axis illumination is usually combined with some form of optical proximity correction. Our work involved the simplest of many types of phase-shift masks—the chromeless phase-shift photomask—in which the final photomask pattern. destructive interference causes the formation of a dark-line feature in the photoresist. NUMBER 2.0 Relative intensity 10 –2 10 –3 10 –4 10 –5 –1. 2003 LINCOLN LABORATORY JOURNAL 239 . shown in Figure 4. In this approach. Because drawbacks include increased isodense-proximity effect.0 0 1. where λ is the illumination wavelength and n is the index of refraction of glass for this λ.• FRITZE ET AL.

• FRITZE ET AL. chrome-on-glass photomask and with a phase-shift photomask [3]. Schematic of the double-exposure phase-shift lithography process. Both exposures are performed before the photoresist is developed. We also worked closely with a photomask company. Subwavelength Optical Lithography with Phase-Shift Photomasks Chrome 0º 180º Phase-shift photomask Trim photomask Final pattern on wafer FIGURE 6. but the improved patterning makes it worthwhile for many applications. an industry standard in 1999 and 2000. only closed patterns can be imaged with a phase-shift photomask. Photronics Inc. a start-up company that developed a novel method of double-exposure phase-shift imaging. and advanced computer-aided design (CAD) software is required to decompose and verify the layout. For our experiments. Figure 6 shows the basic double-exposure. shown in the enlarged view. the second erasure exposure removes undesired features. Gratings with feature pitch significantly smaller than any previously reported were also fabricated. with a numerical aperture of 0. The desired integrated-circuit feature pattern is decomposed into two photomask pat240 LINCOLN LABORATORY JOURNAL VOLUME 14. The dark-line feature imaged with the phase-shift photomask is deeper and narrower. Because all edge features produce a dark line. wafer production takes longer with this method. indicate a well-designed pattern-transfer etch process. The double-exposure phase-shift technology allowed us to achieve isolated 25-nm minimum feature sizes. which are a remarkable 10% of the 248-nm illumination wavelength used. 2003 terns. This research was part of a Defense Advanced Research Projects Agency (DARPA)–sponsored program in advanced complementary metal-oxide semiconductor (CMOS) technology. Applying Chromeless Phase-Shift Photomasks to Complementary Metal-Oxide Semiconductors Lincoln Laboratory has pursued the fabrication of transistors with gate lengths in the 25-nm range. which allows imaging of photoresist features at sizes that are significantly smaller than the illumination wavelength. and the interconnection and trim features are placed on a primarily transparent (bright field) chrome photomask. Fabrication for the phase-shift photomask is more complex than for the standard chrome photomask. The final developed pattern of photoresist on the wafer is a combination of these two exposures. The first exposure images the narrow features on the wafer. and the second exposure images the interconnection features and trims the undesired phase-shift edge features. Figure 7 shows electron-microscope images of a ring oscillator circuit with 25-nm polysilicon gate lengths [5].. Numerical Technologies has developed sophisticated CAD tools to decompose and verify typical circuit patterns into such double-exposure photomask sets. to fabricate the necessary custom phase-shift photomasks. a type of advanced CMOS technology in which Lincoln Laboratory spe- . The minimum-width features are placed on a primarily opaque (dark field) phase-shift photomask. The phase-shift and trim photomasks are se- quentially exposed on the same region of the wafer.6 and variable illumination. phaseshift lithography approach developed by Numerical Technologies [4]. These devices are made with fully depleted siliconon-insulator technology [6]. Two exposures are typically required. we used a Canon EX-4 248-nm stepper. NUMBER 2. Compared to single-exposure techniques. The smooth sidewalls of the very small polysilicon features. Lincoln Laboratory collaborated with Numerical Technologies.

5 µm is maintained even at resist feature sizes of 40 nm [10]. This type of phase-shift imaging has since been adopted by major semiconductor companies. Figure 8(b) plots feature size versus exposure dose to show the exposure latitude. The enlarged view at right of one transistor segment shows the desirable smooth sidewalls of these narrow transistor gates. the feature size is set by the exposure dose and not the photomask feature size. Figure 8 shows the process latitude for the doubleexposure phase-shift lithography technique. These data indicate that for the chromeless phaseshift process. and light with moderate spatial coherence for the interconnect exposure. (b) The plot of feature size versus exposure dose shows that the feature size is set by the exposure dose and not the size of the photomask feature. Finally. the sensitivity of the phase-shift lithography process to exposure dose. NUMBER 2. Texas Instruments. Note the power law behavior of the exposure-dose curve. We used an ultrathin photoresist layer (255 nm thick) that performed well even when highly overexposed. We find that a depth of focus in excess of 0. Fitting this exposure-dose curve with a power law results in an ex- 200 180 160 Feature size (nm) 140 120 100 80 60 40 20 0 –0. (a) The plot of feature size versus focus shows that a depth of focus in excess of 0. Subwavelength Optical Lithography with Phase-Shift Photomasks 2 µm 25-nm polysilicon transistor gate 200 nm FIGURE 7.0 1.5 140 120 11. VOLUME 14.8 mJ/cm2 (a) 0 0. cializes. Process latitude for the double-exposure phase- shift-lithography technology. 2003 LINCOLN LABORATORY JOURNAL 241 .4 mJ/cm2 19. We chose to use chromeless features in the phase-shift part of the double-exposure process. Lucent.73 100 80 60 40 (b) 20 100 140 180 220 Dose (mJ/cm2) FIGURE 8. we obtained the most effective illumination between the two exposures by using highly spatially coherent light for the interference-based phase-shift exposure. United Microelectronics Corporation.0 mJ/cm2 20. At the time of this work (1999 to 2000). Our results were achieved by optimizing a number of aspects of the phase-shift imaging process.5 1. Motorola. and Samsung [7–9]. Electron-microscope images of a silicon-on-insulator circuit containing 25-nm polysilicon gate-length features.5 µm is maintained even at resist feature sizes of 40 nm. shown in Figure 6. these gate lengths were among the smallest features ever imaged with optical lithography.5 Focus ( µm) Feature size (nm) Dose ∝ (feature size)–0. Figure 8(a) plots feature size versus focus for several exposure doses.• FRITZE ET AL. including Intel.8 mJ/cm2 15.

Series of cross-sectional electron-microscope images of SOI transistors fabricated by using the doubleexposure phase-shift lithography method illustrated in Figure 6. with key aspects being the phaseshift defined gate and the locally thinned channel beneath the gate. Note that the vertical profiles for the polysilicon gate depict feature sizes as small as 9 nm. By using the double-exposure phase-shift lithography process. Gate length = 90 nm posure latitude of 7. To transfer this photoresist gate pattern to the underlying polysilicon. We used the double-exposure phase-shift lithography process to image transistor gates onto the photoresist. The rule of thumb for such a design is a silicon channel thickness of approximately one-fourth the gate length. The silicon channel region under the narrow phase-shift defined gate is quite thin (7 to 15 nm). These transistors were imaged with the same phaseshift photomask. Subwavelength Optical Lithography with Phase-Shift Photomasks Phase-shift-defined gate Thinned SOI channel Silicon nitride spacer 4-nm gate oxide Silicided SOI Buried oxide Silicon substrate FIGURE 9. This type of exposure latitude is in stark contrast to that obtained by using conventional chromeon-glass masks. .• FRITZE ET AL. The device has a fairly simple geometry. Figure 9 shows a cross-sectional schematic of the transistor design [5].3 % independent of dose (up to the critical value at which the pattern suddenly collapses). The etch required vertical profiles. which corresponds to only 18 silicon lattice constants in size and less than 4% of the exposure wavelength. 2003 Gate length = 25 nm Gate length = 9 nm FIGURE 10. which is required to obtain good electrical performance from a small gate-length device in this technology. where significant overexposure results in a total loss of exposure latitude. These devices were imaged by using the same phase-shift photomask and by simply varying the exposure dose. Schematic cross section of the type of siliconon-insulator (SOI) transistor we worked on. NUMBER 2. we were able to fabricate advanced SOI 242 LINCOLN LABORATORY JOURNAL VOLUME 14. Figure 10 shows a series of cross-sectional scanning-electron micrographs of silicon-on-insulator (SOI) transistors. and the ability to stop on thin 4-nm gate oxides. some lateral linewidth loss. we were able to achieve the orderof-magnitude reduction in gate length shown by applying different exposure doses. we developed a plasma-etch process that further shrank the 40-nm resist features to 25 nm [11]. Figure 9 illustrates the transistor design.

5 Gate voltage (V) FIGURE 11.0 1. The feature pitch is signifi- cantly below the exposure wavelength in this case. Such increased photomask costs are difficult to amortize for applications that require a low-tomoderate number of wafers exposed per photomask. showing the potential for applying phase-shift methods to quite dense patterns.• FRITZE ET AL.5 0 0. 2003 LINCOLN LABORATORY JOURNAL 243 .5 0 0. NUMBER 2. We could then study the performance of highly scaled SOI CMOS technology years before its anticipated commercial introduction. Typical transistor characteristics for this design are shown in Figure 11 for gate lengths of 85. Our device research required us to fabricate primarily isolated narrow features. This 212-nm pitch grating was imaged in the photoresist by a 248-nm lithography tool with a numerical aperture of 0. many of the advantages of RET lithography are not economically viable.0 1. Figure 12 shows an example of a dense grating feature that we fabricated using chromeless phase-shift imaging [12]. narrow features must be imaged through a wide range of pitch values. Performance test results for transistors of several different gate lengths. it is becoming increasingly difficult to correct for image nonuniformities caused by the isodenseproximity and spatial-frequency effects as feature sizes become much smaller than the imaging wavelength. The decline in performance for gate lengths of 50 nm or less indicates that the transistor design at these gate lengths was not optimized. In addition.5 1. For these applications.0 –0. transistors with gate lengths in the 25-nm size regime specified by DARPA. and 25 nm. 50.0 –0.5 V 50 mV 0 0.5 Not optimized Not optimized 1. Cost-Effective Implementation of Phase-Shift Lithography The increased fabrication complexity associated with phase-shift lithography can add substantial photomask cost.5 V 0. The advantages of this technology include low power performance and improved scalability and radiation tolerance. Subwavelength Optical Lithography with Phase-Shift Photomasks 85-nm gate length 50-nm gate length 25-nm gate length 100 Drain current (A/7 µm) 10 –2 10 –4 10 –6 10 –8 10 –10 10 –12 10–14 –1. Application-specific integrated circuits (ASICs) and system-on-a-chip (SOC) designs.0 1.5 1. For practical implementation of phase-shift technology.5 –1.65. are produced in low volumes compared with the microprocessors and memory found in personal computers. VOLUME 14.5 1. The decline in performance for gate lengths less than or equal to 50 nm indicates that the transistor design at these gate lengths was not optimized. such as those used in the defense and telecommunications industries.0 –0. but we explored dense grating imaging as well.5 –1.

a cost-effective implementation of phase-shift lithography. In addition. we have developed an implementation of phase-shift lithography that addresses a number of issues. Subwavelength Optical Lithography with Phase-Shift Photomasks Linewidth = 88 nm Pitch (linewidth + spacewidth) = 212 nm FIGURE 12. because all fine feature imaging is done with dense gratings. In this method. thus reducing their cost and enhancing their yield. NUMBER 2. which stands for gratings of regular arrays and trim exposures for ultra-large-scale integration (ULSI) lithography. including high photomask cost and proximity effect distortions [12]. Features in the x-direction on the photoresist (top) are created by using a horizontal phase-shift photomask (x-oriented grating) and a trim photomask. Features in the y-direction on a different photoresist layer (bottom) are created using the identical process with a vertical phase-shift photomask (y-oriented grating) and a trim photomask. and all pitch values must be integer multiples of the minimum resolvable pitch. This approach has two restrictions: all fine features must be placed on the design grating grid. Simple grating phase-shift photomask patterns are easier to fabricate and inspect than arbitrary geometry masks. 244 LINCOLN LABORATORY JOURNAL VOLUME 14. In this case. Under the sponsorship of Lincoln Laboratory’s Advanced Concepts Committee. Electron-microscope cross section of a 212-nm pitch grating formed by using a chromeless phase-shift photomask and a 248-nm exposure tool. which are customized with subsequent trim exposures. all critical circuit features are imaged by using simple one-dimensional phase-shift-grating template photomasks. + = Horizontal phase-shift photomask Trim photomask Photoresist image Geometric union of horizontal and vertical photoresist features + = Vertical phase-shift photomask Trim photomask Photoresist image FIGURE 13. The acronym stands for gratings of regular arrays and trim exposures for ultra-large-scale integration (ULSI) lithography. The final result on the photoresist combines features in both directions. the grating pitch is smaller than the exposure wavelength. 2003 . Schematic diagram of the GRATEFUL imaging method. The template photomask can be reused for a wide variety of designs together with different trim masks.• FRITZE ET AL. proximity effects are effectively eliminated along with the complex photomask features typically used to correct them. We have dubbed this method GRATEFUL.

fine features in the x. The sharp corner features produced in this manner. The photoresist is then baked to make it insensitive to further developing. Here. indicate minimal spatial-frequency effects. The final result is a complex pattern with critical features in both orientations. Note the absence of isodense proximity effects as shown by good feature size control through a variety of pitch values. A simple one-dimensional phase-shift grating was used together with a conventional trim exposure to create the fine lines. Figure 16 shows an example of a circuit pattern with fine features in both x- 2 µm 1 µm FIGURE 15. A different dose was used in each orientation. as shown by the sharp corners. This type of method limits feature geometries to Manhattan (x-axis and y-axis) orientations. VOLUME 14. Figure 15 shows a second GRATEFUL example [13]. The process is repeated with a y-oriented phase-shift grating and trim. resulting in different feature sizes. and a second layer of photoresist is coated over these features. Figure 14 shows an example of the GRATEFUL method [12].• FRITZE ET AL. The first step uses a one-dimensional grating in the x-orientation combined with a trim exposure to form a series of narrow line features in the x-direction. NUMBER 2. Linewidths are maintained through a large pitch range. The larger interconnect features were added in the second layer of photoresist. 2003 LINCOLN LABORATORY JOURNAL 245 . A schematic outline of the GRATEFUL method is shown in Figure 13 [13]. Because the imaging was performed in two layers of photoresist. Two magnifications of experimental example of the GRATEFUL imaging method applied to a test pattern with fine features in two orientations. In this case.and y-orientations were formed in separate layers of photoresist. seen in the magnified view on the right. Subwavelength Optical Lithography with Phase-Shift Photomasks 5 µm FIGURE 14. spatial-frequency corner-rounding effects were effectively eliminated. the circuit pattern has narrow line features in only the x-orientation. which indicates an absence of isodense-proximity effects. Experimental example of the GRATEFUL imaging method applied to a circuit pattern with fine features oriented only in the x-direction.

In the large intermediate regime. despite the fact that some implementations require more than two exposures and possibly two levels of resist.or two-exposure custom phase-shift-photomask method (currently practiced by industry) is the most economical. and Dolly Shibles for expert technical assistance. Acknowledgments We thank Andy Curtis.• FRITZE ET AL. We also modeled direct-write lithography. We modeled the cost per critical level per wafer as a function of the number of wafers per photomask for 90-nm-node technology currently under development. 2003 We have developed a phase-shift lithography process capable of imaging feature sizes as small as 16% of the 248-nm exposure wavelength.and y-orientations. and for 246 LINCOLN LABORATORY JOURNAL VOLUME 14. This method has the potential to make advanced phase-shift imaging cost effective for moderate-to-low wafer counts per photomask. Labor and clean-room costs were neglected. Three regions are clearly evident. a tool throughput of 130 wafers per hour. for a 30photomask set with highly critical gate and contact level. corresponding to only 18 silicon lattice constants in size. Note the absence of optical proximity effects. Kyle Keenan. GRATEFUL method applied to a circuit pattern with fine features in both x. We have performed a cost analysis of our templatebased lithography approach and compared it to current methods used for critical-level lithography in industry [14]. the one. NUMBER 2. and y-orientations. The fundamental pitch is 280 nm. The Lincoln Laboratory portion of this work was supported by DARPA under its Advanced Microelectronics Program and the Lincoln Laboratory Advanced Concepts Committee. Doug Preble. however. and typical defense integrated-circuit applications at the low end of template methods and the high end of direct write. Large peaks in industrial photomask usage fall within the regime of template-based methods. The phase-shift photomask used to create this pattern was a simple one-dimensional grating. a situation encountered in low-volume manufacturing applications such as ASICs used by commercial and Department of Defense systems. assuming a tool cost of $15 million and an optimistic throughput of one wafer per hour. and 100% uptime. We have also been developing a method of phase-shift technology that uses simple reusable template photomasks with fine features. John Jarmalowicz. Summary FIGURE 16. For very low wafer volume.34 for our system. Figure 17 summarizes the results of this analysis. This lithography method has allowed us to fabricate next-generation SOI transistors by using currently available optical-lithography equipment. a photomask set cost of $2 million. . Using this process together with a controlled etch bias. Figure 17 also shows the results of a survey of photomask usage conducted by the Semiconductor Manufacturing Technology (SEMATECH) consortium in 2000. template-based methods such as GRATEFUL are the most cost effective. we have fabricated transistor gates as small as 9 nm. 7% maintenance cost per year. corresponding to k1 = 0. direct write is the cheapest method. Subwavelength Optical Lithography with Phase-Shift Photomasks 2 µm very high volume. which does not require photomasks. Sandy Deneault. and a resist processing cost of $5 per wafer. The model assumptions were a stepper cost of $15 million with five-year depreciation.

template photomask. Large peaks in industrial photomask usage. At high wafer volumes. At low wafer volumes. VOLUME 14. one exposure Custom. one wafer/hour 10 5 Cost/critical level/wafer (dollars) 10 4 10 3 10 2 10 1 Direct write Template photomasks 10 0 10 –1 0 10 1 10 2 10 3 Number of wafers 10 4 Custom photomasks 10 5 DRAM/MPU Respondents 50% ASIC 25% 0% 0 10 1 10 2 10 3 Number of wafers 10 4 10 5 FIGURE 17.or two-exposure custom phase-shift-photomask method is the most cost-effective. 2003 LINCOLN LABORATORY JOURNAL 247 . Subwavelength Optical Lithography with Phase-Shift Photomasks 10 6 90-nm node technology Custom. NUMBER 2. four exposures Direct write.• FRITZE ET AL. fall within the regime of template photomasks. three exposures GRATEFUL. and custom photomask (top) and results of a 2000 survey of photomask usage conducted by the Semiconductor Manufacturing Technology (SEMATECH) consortium (bottom). Comparison of 90-nm node lithography costs for various fabrication methods: direct write. the direct-write method is the most cost-effective. the one. two exposures GRATEFUL. which includes applicationspecific integrated circuits (ASIC) and dynamic random access memory (DRAM) and microprocessor unit (MPU) chips.

10µm and 0. “Dense-Only Phase Shift Template Lithography. A. Cave. 2366–2370.A. L. Shaw. 2003. pp. N. and C.R. Keast. M. C. 2001. Electron Devices 29 (12). Preble. S. 2–14. C. 191–196. C. 2000. “Sub-100 nm Silicon on Insulator Complementary Metal-Oxide Semiconductor Transistors by Deep Ultraviolet Optical Lithography.-M.C. “Effects of Complementary Phase Shift Imaging on Gate CD Control.W. Technol. H. Stivers. Astolfi.” SPIE 3334. Curtis. J. 2001). D. Brandom. Fu. C.M.-C. S. Fla. Davis.15 µm. D. Subwavelength Optical Lithography with Phase-Shift Photomasks REFERENCES 1. D. Rhyins. Wash. pp. 1. Pati. Mastovich. S. N. NUMBER 2. pp. Blachowicz. C. R. Mallen. P. Deneault. J. “Dry Etching of Amorphous-Si Gates for Deep Sub-100 nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor. and D. 102–103. Chen. pp. Wang. M.” J.” IEEE Trans. and B.13 Micron VLSI Manufacturing. Fritze. Cann.” SPIE 4346. 10. B.C. pt. R. pp. T. J. 6765–6773. D.K Chen. M. “Patterning 80-nm Gates Using 248-nm Lithography: An Approach for 0. Forte. P.” SPIE 4346. Chan. “Extending the Lifetime of Optical Lithography Technologies with Wavefront Engineering. Wang. V. 2. M. Vac. Liu.M Burns. Thomson. Wheeler. Tyrrell.C. and R. Palmateer.. pp. Fritze. Wong. Resolution Enhancement Techniques in Optical Lithography (SPIE Press. T. R. Vac. pp.K. Burns.• FRITZE ET AL. B. Forte. Sci. “Improving Resolution in Photolithography with a Phase-Shifting Mask. P. M. Yost. “Investigation of the Physical and Practical Limits of Dense-Only Phase Shift Lithography for Circuit Feature Definition. Tejnil. Y.C.-K.” J. Liu. P. 8. SOI Conf. and S. Yost. 464–470. Curtis. M. 6. 112–120. 30 Sept. H. Wyatt. Carney. Viswanathan.M. Fritze. 2001. Levenson. 1828– 1836. Sullivan. Cann. Shaver. Simpson. 2000. pp. Lai. C. Gouker. Jarmalowicz. B. D. 452–463. pt.–3 Oct. 1. B. Phys. D. 12. P. Cann. Tyrrell. 9. A.L.W.” Proc. Schenker. 388–407.-Y. Huang.-Y. B 18 (6). Wheeler. 2886–2890. D. Yost. S. 1998. C. 2003. M. pp. 33 (12B. R.” SPIE 4000. Rhyins. and P. 1994. and E. Liu. Martin. “Gratings of Regular Arrays and Trim Exposures for Ultralarge Scale Integrated Circuit Phase-Shift Lithography. S. Nelson-Thomas. D. B. Davis.-W.L. J. Sci Technol B 20 (1). Vac. H. J. Sci. pt. N. 1. 4.K. 16. Mallen. and H.” J. Astolfi.13µm Poly Patterning. 2002. pp. 5.D. Mallen. 1). Yost. M... 2000. J. “Alt-PSM for 0. Cann. and P. C. J. A.K. Bellingham. B 19 (6). J. S. Rhyins.” SPIE 4000. Liu.Y. 2001.D. 1.-T. Astolfi. and H. 1982. P.S. D. pt. Preble. pp. 11. Suntharalingam.” SPIE 5042. Kling. pp. “Performance of a Low Power Fully-Depleted Deep Submicron SOI Technology and Its Extension to 0. 1996 Int. pt. D. Tyrrell. Sanibel Island. pp. Deneault.A. Knecht. Astolfi. 243–252. Fritze. M. P. Fritze. Wheeler. Cann. 15–29. Chen. 7. D. P.M. and M. B. Karklin. Davis. P. C. 3. Keast. 17. A. Wang.” JM3 1 (3). Levenson. Ferri. “The Application of Alternating Phase-Shifting Masks to 140 nm Gate Patterning (II): Mask Design and Manufacturing Tolerances. and Y. R.T. Kunz. Wyatt. Fritze. Martin. R. 248 LINCOLN LABORATORY JOURNAL VOLUME 14.-Y. R. Burns. J. “Application of Chromeless Phase-Shift Masks to Sub-100 nm SOI CMOS Transistor Fabrication. M. Appl. S.” Jpn.. Kirchauer. 2003 . Technol. A. Soares.

For more than 20 years.  .S. photonics. and 248-nm and 193-nm lithography process development. VOLUME 14. Dave received his B. Before joining the Laboratory in 2000.  . She is also responsible for ensuring that existing processes are maintained. Prior to joining Lincoln Laboratory.S. degree in electrical engineering from the University of Pennsylvania.S. NUMBER 2. Rhode Island. bump bonding.E. she served as a process development technician in the areas of ion implantation and thin films for On Semiconductor in East Greenwich. he researched the electrical and optical properties of galliumarsenide (GaAs) quantum well heterostructures in positions at Bellcore and AT&T Bell Laboratories.  manages operations during the second shift of the Microelectronics Laboratory at Lincoln Laboratory. and Ph. assisting in the development of lithographic processes for the fabrication of advanced devices throughout the division. respectively. silicon-on-insulator (SOI) device engineering. degree in plant and soil science from the University of Massachusetts. He is currently pursuing graduate study at the Massachusetts Institute of Technology through the Lincoln Scholars Program. Renée also serves as the cognizant area engineer for deep ultraviolet lithography.• FRITZE ET AL. degrees in physics from Brown in 1988 and 1993. She holds an associate degree in chemical technology from the Community College of Rhode Island in Warwick. 2003 LINCOLN LABORATORY JOURNAL 249 . Subwavelength Optical Lithography with Phase-Shift Photomasks   is a staff member of the Advanced Silicon Technology group. He also has responsibilities pertaining to the development of high-performance complementary metal-oxide semiconductor (CMOS) imager systems. he has worked on projects such as X-ray lithography.  . or process-related issues. Brian received a B.D. Amherst. which includes supervising process and maintenance technicians as well as handling any facilities.  works in the Advanced Silicon Technology group. His current responsibilities are in resolutionenhanced optical lithography. Mike received his B. where he worked on analog integrated circuit design for the ATLAS Large Hadron Collider experiment at CERN. and SOIbased photonics. His responsibilities include the design of analog and digital circuits. degree in physics from Lehigh University in 1984 and M.  provides process engineering support for advanced metrology and the advanced lithography area of Lincoln Laboratory’s Microelectronics Laboratory as an assistant staff member of the Submicrometer Technology group. which serve as demonstration and characterization vehicles for Lincoln Laboratory's advanced silicon processes.S. maintenance. Before joining Lincoln Laboratory in 1995.

and gallium-arsenide millimeter-wave devices. mercury-cadmium-telluride infrared detectors. Donna earned a B. atomicforce microscopy. and before that. after working in the medical field for nineteen years. degree in materials science and engineering from Cornell University in 1983.  is an engineering specialist in the Advanced Silicon Technology group. He also worked on the development of noncrystal-lographic dry-etch processes for gallium arsenide (GaAs).  was an assistant staff member in the Submicrometer Technology group prior to his untimely death in April 2002. She earned a B. Massachusetts. NUMBER 2. maintains the computer-aided design (CAD) process and rules files.S. She has been instrumental in developing poly-silicon gate etch processes for sub-100-nm transistors as well as deep-viaetch processes used to connect multiple wafer stacks for 3D circuit integration. He began working at Lincoln Laboratory in 1980 with the Microelectronics group. Donna worked as a process engineer for fifteen years with Lockheed Martin (now BAE Systems) in Lexington. Subwavelength Optical Lithography with Phase-Shift Photomasks - . Massachusetts. Prior to joining the Laboratory in 1998. degree in medical technology from Vermont College/Norwich University. as well as high-aspectratio dry etching of silicon for permeable base transistors.  . she specialized in plasma etching and deposition for a variety of technologies. At both companies. Susan joined the Laboratory in 1989. 250 LINCOLN LABORATORY JOURNAL VOLUME 14. and X-ray photoelectron spectroscopy.  . and does the post-design processing and assembly of other layouts into the photomask sets. He joined the Submicrometer Technology group in 1988 to develop plasma-deposited electrochromic thin films for use in 193-nm lithography. His later work involved developing silylation processes for top-surface imaging and the corresponding dry-etch processes for pattern transfer in 193-nm lithography. responsible for developing and integrating etch processes for fabricating fully depleted silicon-oninsulator (SOI) complementary metal-oxide semiconductor (CMOS) circuits.  is an associate staff member of the Advanced Silicon Technology group. 2003 . He earned a B.  . (associate of engineering) degree in computer engineering from the Franklin Institute in Boston. with M/A COM in Burlington.E. He lays out the process monitor sections and all alignment cells for photomask sets. degree in mechanical engineering from the University of Massachusetts in Lowell in 1984.  is an engineering specialist in the Submicrometer Technology group performing material analysis with high-resolution electron microscopy. concentrating primarily on the development of dry-etched processes for metals. including vanadium oxide microbolometers.S.S.• FRITZE ET AL. He received an A.