MOS Transistor Operation

Gate S/D Channel width (W) Oxide n+ Channel Length (L) Substrate (p-Si) n+ S/D

Ø MOS is four-terminal device Ø if the fourth terminal is not shown it is assumed to be connected to the appropriated voltage (lowest and highest supply voltage value for NMOS and PMOS, respectively)
Prof. Gaetano Palumbo 1

VG < V to

V >V to G

Oxide n+
Depletion region

Oxide n+ n+ p n+ Inversion layer (channel)

Substrate region (p)

Ø The diffusion junction are reverse-biased (to achieve this condition the bulk voltage must in NMOS be always lower than the other node voltages) Ø A gate voltage greater than the Threshold Voltage, Vto, is needed to create a surface inversion Ø The depth of the inversion layer is independent from gate voltage
Prof. Gaetano Palumbo 2

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Gaetano Palumbo 3 VG > Vto VS = 0 Oxide Source n+ p Pinch-off point VD = VDSsat ID Drain n+ Ø The linear region holds until the drain voltage reaches the VDSsat value Ø Under this condition the inversion layer at the drain is reduced to zero: Pinch-off point Ø This condition is the border between the linear and the saturation region Prof. Gaetano Palumbo 4 2 .VG > Vto VS = 0 Oxide Source n+ p 0 < VD < VDSsat ID Drain n+ Ø When the inversion layer is established an n-type conduction channel between source and drain is formed Ø For small drain voltage a current proportional to drain voltage flows in the channel: linear behavior (linear or triode region) Ø in the linear region the MOS acts like a voltage-controlled resistor (the control input is the gate node) Prof.

Gaetano Palumbo 5 VG > Vto V =0 S Oxide Source n+ p Pinch-off point VD > VDSsat ID Drain n+ Ø The pinched-off (depleted) section absorbs most of the excess voltage drop VDS-VDSsat.VG > Vto V =0 S Oxide Source n+ p Pinch-off point VD > VDSsat ID Drain n+ Ø Beyond the pinch-off point (VD>VDSsat) a depleted surface region forms adjacent to the drain: Saturation region Ø The depleted surface grows toward the source with increasing drain voltage the effective channel length is reduced Prof. Gaetano Palumbo 6 3 . Ø Electrons arriving from the source through the channel are injected into the drain-depletion region and are accelerated toward the drain in this high electric field Prof.

Gaetano Palumbo 8 4 . it is Q VFB =φms − ox Cox Q Vt = VFB − 2φF − B Cox Ø VFB.is the built-in offset across the MOS structure. Gaetano Palumbo 7 Ø The Flat-Band voltage. φF and Cox (=εox/tox) are technology parameters Ø QB depends on the source-bulk voltage QB = − 2qNAεsi − 2φF +VSB Prof.MOS Threshold Voltage Ø It is due to 4 physical component 1) the work function difference between the gate and the channel (built-in potential of the MOS structure) 2) the voltage needed to change the surface potential 3) the voltage to offset the depletion region charge 4) the voltage to offset the fixed charge in the silico-oxide interface (and in the gate oxide) Q Q Vt = φms − 2φF − B − ox Cox Cox Prof.VFB.

Gaetano Palumbo 9 MOS Current-Voltage characteristic Ø Use of the gradual channel approximation Ø reduce the analysis to a one-dimensional current-flow problem Ø the approximation is heavy for small-geometry MOS VG > Vto VS = 0 Oxide Source n+ p Drain n+ 0 < VD < VDSsat ID x y=0 y y=L Prof.Vt =Vto +γ −2φF +VSB − −2φF ( ) Ø Vto. is the threshold voltage for VBS=0 QB0 = − 2qNAεsi − 2φF Q Vto = VFB − 2φF − B0 Cox 2qεsiN A Cox Ø γ is the body-effect coefficient γ= Prof. Gaetano Palumbo 10 5 .

µn. dR. the incremental resistance. Ex (allows to reduce the current flow only to the ydimesion) Ø The channel voltage. Ey. is QI ( y ) = −Cox ⋅ [VG − Vc ( y ) − Vto ] y=0 Channel length = L y=L Channel width = W dy Source end Inversion layer (channel) Drain end Ø Assuming all mobile electrons with a constant surface mobility. Gaetano Palumbo 11 Ø The total mobile electron charge in the surface inversion layer. Vto. is (the minus sign is for the negative polarity of QI(y)) dR = − dy W ⋅ µ n ⋅ QI ( y ) 12 Prof. QI(y). constant along the channel from y=0 to y=L (this is an approximation since the channel voltage is not constant) Ø Assume the electric field component.Ø Assume the threshold voltage.with respect to the bulk is: VC(0)=0 and VC(L)= VD Prof. Gaetano Palumbo 6 . VC(y). along the ycoordinate is dominant compared to the one along the xcoordinate.

Pinch-off occurs Ø The theoretical behavior of the drain current is decreasing after the peak. Gaetano Palumbo Saturation region 14 7 .Applying Ohm’s law along y-direction and then integrating from 0 to L dVc = I D ⋅ dR = − ID ⋅ dy W ⋅ µ n ⋅ QI ( y ) L 0 VDS 0 ∫ I D ⋅ dy = −W ⋅ µn ∫ QI ( y) ⋅ dVc I D ⋅ L = W ⋅ µ n ⋅ COX VDS 0 ∫ (VG − Vc − Vto ) ⋅ dVc µ ⋅C W 2 I D = n ox ⋅ ⋅ [ 2 ⋅ (VG − Vto )VDS − VDS ] 2 L Prof. but it is unrealistic and the current is ideally constant For VDS > VG-Vto = VDSsat µ ⋅C W I D = n ox ⋅ (VG − Vto ) 2 2 L Prof. Gaetano Palumbo Linear region 13 Ø The current voltage curves are inverted parabolas for each constant VG Ø The peak of the parabolas is at VDS = VG-Vto .

Ø Vt is both technological and electrical parameter Ø W/L is the design parameter Prof.µ ⋅C W 2 I D = n ox ⋅ ⋅ [ 2 ⋅ (VGS − Vt )VDS − VDS ] L 2 µ ⋅C W I D = n ox ⋅ (VGS − Vt ) 2 2 L ID VD VG VB VS ID VG ID V D VS VG VB VS V D Linear region Saturation region Depletion Vto<0 VG ID VD VB VS Ø µn. Gaetano Palumbo 16 8 . Gaetano Palumbo 15 PMOS Current-Voltage characteristic ID = µ p ⋅ Cox W 2 ⋅ ⋅ [ 2 ⋅ (VSG + Vt )VSD − VSD ] = 2 L µ ⋅C W 2 = p ox ⋅ ⋅ [ 2 ⋅ ( VGS − Vt ) VDS − VDS ] 2 L µ p ⋅ Cox W ⋅ (VSG + Vt ) 2 = 2 L µ p ⋅ Cox W = ⋅ ( VGS − Vt ) 2 2 L VG Linear region ID = Saturation region ID VS VB VD VG VB VD VS ID ID VS VD VG Prof. Cox are technological parameter.

01 ÷0. Gaetano Palumbo 18 9 .05 V-1 (20 V < 1/λ < 100 V ) µ C W I D ( sat ) = n ox ⋅ (VG − Vto ) 2 (1 + λVDS ) 2 L Ø λ is function of the length L. Gaetano Palumbo 17 Short channel MOS Ø Due to the high Electric field µn is not constant µn = µno 1+ VDS + η ( VGS − Vt ) Ey L Longitudinal field Ø In saturation VDS= VDSsat θ = 0.8 Vertical field µ θ = 1 + η ≈ 1 = no Ey L E y L vmax L µ no C W ⋅ (VG − Vto ) 2 (1 + λVDS ) I D ( sat ) = ox ⋅ 2 1 + θ (VGS − Vt ) L Prof.Channel Length Modulation VG > Vto V =0 S Oxide Source n+ p y=0 y L' ∆L L Drain n+ VD > VDSsat ID L ' = L − ∆L 1− ∆L L ≈ 1 − λ ⋅ VDS 0.01 V-1 < λ < 0. It is is higher for lower L Ø More accurately ∆L ∝ VDS − VDSAT Prof.

Gaetano Palumbo 19 10 .5 Prof.Sub-threshold MOS Ø If VGS ≈ Vt the transistor is not completely off: Subthreshoil region (or weak inversion) VGS  V − DS W nVT  nV ID = Kx e 1 − e T L        Ø Exponential model like bipolar transistor Ø Kx process parameter. Ø n≈1.