DHANALAKSHMI COLLEGE OF ENGINEERING

MANIMANGALAM- CHENNAI

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING
LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
FOR IV SEMESTER B.E (EEE)

NAME REG.NO

:………………………………………………… :…………………………………………………

131452-LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY
1. Study of Basic Digital IC’s.(Verification of truth table for AND, OR, EXOR, NOT, NOR,NAND, JK FF, RS FF, D FF) 2. 3. (a) Implementation of Boolean Functions (b) Design and Implement Adder/ Subtractor circuits (a) Design and Implementation of Combinational circuits for Code conversion, Parity generator and parity checker. (b) Design and implement Encoders and Decoders using suitable IC’s.

4. Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer. 5. Design and Implementation of Synchronous and Asynchronous Counters. 6. Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO Modes using suitable IC’s. 7. Timer IC applications: Study of NE/SE 555 timer in Astable, Monostable operation. 8. Application of Op-Amp: Slew rate verifications, inverting and non-inverting amplifier, Adder, comparator, Integrator and Differentiator. 9. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated IC’s. 10. Study of VCO and PLL ICs (a) Voltage to frequency characteristics of NE/ SE 566 IC. (b) Frequency multiplication using NE/SE 565 PLL IC.

The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each bus strip has two rows of contacts. Each of the two rows of contacts is a node. That is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily for power supply connections, but are also used for any node requiring a large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts is a node. You will build your circuits on the terminal strips by inserting the leads of circuit components into the contact receptacles and making connections with 22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power supply connections to separate bus strips.

Fig 1. The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs (Integrated circuits) used during the experiments. Incorrect connection of power to the ICs could result in them exploding or becoming very hot - with the possible serious injury occurring to the people working on the experiment!

10.Tidy the area that you were working in and leave it in the same condition as it was before you started. chips and all equipment and return them to the demonstrator. Not connecting the ground and/or power pins for all chips. (Pin 1 is often identified by a dot or a notch next to it on the chip package) 5. Building the Circuit Throughout these experiments we will use TTL chips to build circuits. 2. 5. Point all the chips in the same direction with pin 1 at the upper-left corner. At the end of the laboratory session. Turn the power off immediately before you begin to rewire the circuit. Make sure the power is off before you build anything! 3. It is better to make the short connections before the longer ones. Leaving out wires. Plug the chips you will be using into the breadboard. 6. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus strips on your breadboard. The steps for wiring a circuit should be completed in the order described below: 1. Not turning on the power supply before checking the operation of the circuit. Plugging wires into the wrong holes. Select a connection on your schematic and place a piece of hook-up wire between corresponding pins of the chips on your breadboard. Get one of your group members to check the connections. before you turn the power on. Common Causes of Problems 1. 7. . Mark each connection on your schematic as you go. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard. Turn the power (Trainer Kit) off before you build anything! 2. Driving a single gate input with the outputs of two or more gates 6. 4. collect you hook-up wires.Ensure that the power supply polarity and all components and connections are correct before switching on power. so as not to try to make the same connection again at a later stage. If an error is made and is not spotted before you turn the power on. 8. 9. Modifying the circuit with the power on. 3. 4.

components at the start of the experiment and return them to their proper place after you have finished the experiment. Fig 2. Remember that you must connect power to the chips to get them to work.B’. don't put it back in the box of chips for somebody else to use. . leads. Place your chips in the same direction. to save confusion at a later stage.In all experiments. The complete designed and connected circuit Sometimes the chip manufacturer may denote the first pin by a small indented circle above the first pin of the chip. If you damage a chip. you will be expected to obtain all instruments. inform a demonstrator. Please inform the demonstrator or technician if you locate faulty equipment. Example Implementation of a Logic Circuit Build a circuit to implement the Boolean function F =A’.

JK FF. Application of Op-Amp: Slew rate verifications.INDEX S. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D conversion using dedicated IC’s. Integrator and Differentiator. 8:1 multiplexer and Study of 1:4. Adder. (b) Frequency multiplication using NE/SE 565 PLL IC. inverting and non-inverting amplifier. PISO. Pg. (b) Design and implement Encoders and Decoders using suitable IC’s. Study of 4:1. Design and Implementation of Synchronous and Asynchronous Counters. EXOR. Parity generator and parity Checker.No Date Name of the Experiment Study of Basic Digital IC’s. Monostable operation.NAND. comparator. OR. RS FF. PIPO Modes using suitable IC’s Timer IC applications: Study of NE/SE 555 timer in Astable. D FF) (a) Implementation of Boolean Functions (b) Design and Implement Adder/ Subtractor circuits (a) Design and Implementation of Combinational circuits for Code conversion. Study of VCO and PLL ICs (a) Voltage to frequency characteristics of NE/ SE 566 IC. NOR.no Marks out of 10 Signature of staff 1 2 3 4 5 6 7 8 9 10 COMPLETED / INCOMPLETE / LATE SUBMISSION . SIPO.(Verification of truth table for AND. NOT. Design and implementation of 4-bit shift registers in SISO. 1:8 demultiplexer.

AVERAGE MARKS: .

AND GATE SYMBOL TRUTH TABLE OR GATE SYMBOL TRUTH TABLE NOR GATE SYMBOL TRUTH TABLE .

If any one of the input is 1. NAND Gate This is NOT-AND gate. then output is 0. then output Y = (A. 5. then output is 1. It is also called an Inverter. AND Gate The AND gate gives an output only when all its inputs are present. If A and B are inputs. A NAND gate will have an output of 1 when all its inputs are 0. IC7408 IC 7402. The output Y= A . may be defined as a table.No 1 2 3 Apparatus IC 7404. Gates: 1. the output is true only all inputs are false. It can be made out of an AND gate by connecting an inverter in its output. IC7400.Experiment No: Date: __/__/____ STUDY OF LOGIC GATES & FLIP FLOPS AIM: To realize logic functions using gates & verify the operation of flip-flops. OR Gate The OR gate has an output of 1 when either A or B or Both are 1. If A & B are inputs. 2. 3. B. then the output is Y = A+B. If A is an input. NOT Gate It is called so because its output is not the same as its input.B)’ . Hence this is an all-or-nothing gate whose output occurs only all its inputs are present. IC 7432. IC 7486 Digital trainer Board Connecting wires Specifications Quantity THEORY: A. The OR gate truth table. In a NAND gate. the output is true only all inputs are false. The AND gate has output 1 if both A & B are 1. In a NOR gate. because it inverts the input signal.In other words. it is an anyor-all gate because an output occurs when any or all inputs are present. A NOR gate will have an output of 1 only when all its inputs are 0. It has one input & one output. It can be made out of an OR gate by connecting an inverter in its output. If A & B are inputs. which give the output state for all possible input combinations. NOR Gate This is NOT-OR gate. then output Y = (A+B)’ 4. then Y= A’ is its output. Apparatus Required: S. If any one of the input is 1.

NOT GATE SYMBOL TRUTH TABLE X-OR GATE SYMBOL TRUTH TABLE 2-INPUT NAND GATE SYMBOL TRUTH TABLE .

Universal Gates The Universal gates are NAND and NOR gates because the logic gates like NOT. The major differences among various types of FFs are in the number of input they possess and in the manner in which the inputs affect the binary state. R=0. JK FF and T FF. as it depends on whether the output of gate 3 or gate 4 goes to 1 first. Clocked RS FF. and CP=1. It is also called Inequality Comparator. or latch in either stable state.6. the state of the circuit does not change. Nevertheless. The clocked RS flip-flop shown in fig consists of a basic flip-flop circuit and two additional NAND gates. information from the S or R inputs is allowed to reach the output. When the clock pulse goes back to 0 (while S=R=1). OR and AND can be realized using these gates.the output of gate 4 to remain at 1. The FF has two outputs. the inputs must be S=0.and the output of the FF at Q to go to1.  An indeterminate condition occurs when CP=1 and both the inputs S=1.  To change to the reset state. and CP=1.In other words. a fact which gives rise to different types of Flip-Flops. since it will hold. B. The different types of Flip Flops are RS FF. The FF is often called a latch. R=1. The FF can be used as memory device since it can maintain a binary state indefinitely (as long as power is delivered to the circuit) until directly by an input signal to switch states. The important applications of FFs are · Storage register · Shift register · Frequency divider · Counters 1. it is not possible to determine the next state. The output Y= A’ B + A B’ 7. if its input is same. This condition places 0’s in the outputs of gates 3 and 4 and 1’s in both outputs Q and Q’.In either case. This causes the output of gate 3 to go to 0. D FF. output is one if its input but not both is 1. R=1. This indeterminate condition makes this circuit difficult to manage and it is seldom used in practice. The outputs of NAND gates 3 and 4 stay at the logic 1 level as long as the clock input (abbreviated CP) remains at 0. Binary information can enter a flip-flop in a variety of ways. Clocked RS Flip-Flop: The operation of the basic FF can be modified by providing an additional control input that determines when the state of the circuit is to be changed. The output is 0. The set state is reached with S=1. EX-OR Gate In this gate. Flip-flops: Flip Flops is a bi-stable multivibrator circuit that has two stable states. It forms the heart of all sequential digital circuits. it has an output 1 if its inputs are different.  When the clock pulse input goes to 1.This is the quiescent condition for the basic FF. when CP returns to 0. one for the normal valve and another one for the complement value of the bit stored in it.  The clock pulse input acts as an enable signal for the other two inputs. the circuit remains in its previous state When CP=1 and both the inputs S and R are equal to 0. it is important circuit because all other flip-flops are constructed from it. .

LOGIC CIRCUIT SR .Flip Flop D.Flip Flop .Flip Flop JK.

Flip Flop .T.

JK flip-flop are never constructed. input data is loaded into the FF and appears at the output. Similarly. The one whose input is connected to the flip-flop output which is presently equal to 1. a circuit that needs only single data input. the output state of the flip-flop is complemented. the output of the lower AND gate becomes  a 1 and the flip-flop is set.  It is very important to realize that because of the feedback connection in the JK FF. clock pulse must have time duration that is shorter than the propagation delay time of FF. through gate 5. When the clock input goes high.  When both J and K are 1. For this reason. generation of two signals to drive a FF is a disadvantage in many applications. is applied to the R input. and its complement. If D is 1. output Q’ is AND-ed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q’ was previously 1. Thus if Q=1.  The restriction on the pulse width can be eliminated with a mater. This conforms to the requirement that the two inputs of a basic NAND flip flop remain initially at the 1 level.  A clocked JK flip-flop is shown in fig -5. that is if Q=1. This has lead to the D FF.slave or edgetriggered flip flop. the clock pulse is transmitted through one AND gate only. the output f gate 3 goes to 0. the output of gates 3 and 4 are at the 1 level and the circuit cannot change state regardless of the value of D. If D is 0. it switches to Q’ =0 and vice versa. and the flip-flop is cleared. a clock pulse that remains in the 1 state while both J=K=1 will cause the output to complement again and repeat complementing until the clock pulse goes back to 0. In either case.  The same reasoning applies to the T flip-flop. Then when the clock pulse goes low. since the operation of the circuit depends on the width of the pulses.  To avoid this indeterminate condition.  The D FF receives the designation from its ability to hold data into its internal storage. When both inputs J=K=1 simultaneously the flip-flop switches to its complement state.this is called Race-around condition in the FF. One way to eliminate the undesirable condition of the indeterminate state in the clocked RS FF is to ensure that inputs S and R are never equal to 1at the same time. This is a restrictive requirement. switching the flip-flop to the set state.  The characteristic equation shows that the next state of the flip-flop is the same as the D input and is independent of the value of the present state. As long as the clock pulse input is at 0. the output retains the data. Output Q is AND-ed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. switching the flip-flop to the clear state.  The D input is sampled during the occurrence of a clock pulse. . the output of the upper AND gate becomes 1 upon application of a clock pulse. 4. If Q’=1.  The D input goes directly to the S input. Inputs J and K behave like inputs S and R to set and clear the flipflop respectively. Delay Flip Flop The RS FF has two data inputs and therefore. the output of gate 4 goes to 0. J-K Flip Flop A JK flip flop is a refinement of the RS flip flop in that the indeterminate state of the RS type is defined in the JK type.3.

Truth table SR Flip Flop S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 1 1 0 0 1 1 X X D Flip Flop D Qn 0 0 0 1 1 0 1 1 JK Flip Flop J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Qn 0 1 0 1 0 1 0 1 Qn+1 1 1 0 0 1 1 1 0 Qn+1 0 0 1 1 T Flip Flop T Qn 0 0 0 1 1 0 1 1 Qn+1 0 1 1 0 .

4. 7400 & 7486 and connect ground to the 7th pin of IC s. What is a Logic gate? 3. What is Integrated Circuit? 2. Fix the IC s firmly and the connections are made as per the circuit diagram. To realize a particular gate using Universal gates. 2. Apply +5 V to the 14th pin of IC s 7404. Connect the IC s as shown in logic diagram and verify the truth table for that particular gate. Q (T+1)=Q’ that is the state of FF is complemented. The designation T comes from the ability of the flip-flop to “toggle” or complement its state. Toggle Flip Flop The Toggle flip-flop is a single input version of the JK flip-flop. PROCEDURE: 1. The T flip flop is obtained from a JK type if both inputs are tied together. What are the gates called universal gates? 5. Signature of the staff in charge . Apply inputs to the circuit & verify the outputs with Truth table. DISCUSSION QUESTIONS: 1.  The characteristic equation shows that when T=0. 7432. 7408. Q (T+1)=Q. Why NAND and NOR gates are called universal gates? 6. Regardless of the present state of the flipflop complements its output when the clock pulse occurs while input T is logic-1. 3. In a digital IC trainer board. What are the basic digital logic gates? 4.5. Repeat the same for other gates. that is next state is same as the present sate and no change occurs. When T=1. 7402. What are the properties of EX-NOR gate? Result: …………………………………….

Boolean function implementation K-Map (i) (ii) 0 1 3 2 0 1 3 2 4 5 7 6 4 5 7 6 12 13 15 14 12 13 15 14 8 9 11 10 8 9 11 10 F1= F2= Circuit Diagram .

2. ADDER/ SUBTRACTOR CIRCUITS. Draw up the truth tables and logic diagram for the design . AIM: To design and verify the truth table of the Adder and Subtractor circuits. Understand the design problem given to you. Apparatus Required: S.No Components Specifications Quantity . Pre-Laboratory : There are two tasks that you must perform prior to sitting this laboratory: 1.Experiment No: Date: __/__/____ IMPLEMENTATION OF BOOLEAN FUNCTIONS.

Truth Table (a) Half Adder (b) Half Subtractor (c) Full Adder (d) Full Subtractor .

THEORY: The most basic arithmetic operation is the addition of two binary digits. Full subtractor: A combinational circuit which performs the subtraction of three input bits is called full subtractor. whereas the output variables produce the sum and carry bits. The three input bits include two significant bits and a previous borrow bit. . but when the last operation is performed the sum is two digits. The input variables designate the minuend and the subtrahend bit. There are four possible elementary operations. namely. The three input bits include two significant bits and a previous carry bit. Full adder: A combinational circuit which performs the arithmetic sum of three input bits is called full adder. 0+0=0 0+1=1 1+0=1 1 + 1 = 0 with carry 1 The first three operations produce a sum of whose length is one digit. A full adder circuit can be implemented with two half adders and one OR gate. Half subtractor: A combinational circuit which performs the subtraction of two bits is called half subtractor. Half adder: A combinational circuit which performs the addition of two bits is called half adder. The higher significant bit of this result is called a carry and lower significant bit is called the sum. A full subtractor circuit can be implemented with two half subtractors and one OR gate. The input variables designate the augend and the addend bit. whereas the output variables produce the difference and borrow bits.

K-map Simplification Full Adder 0 1 3 2 4 5 7 6 Sum= 0 1 3 2 4 5 7 6 Carry= Full Subtractor 0 1 3 2 4 5 7 6 Difference= 0 1 3 2 4 5 7 6 Borrow= .

What is different between combinational and sequential circuit? 3. What is combinational circuit? 2. What is expression for sum and carry? . 2. Apply the inputs and verify the truth table for the half adder or s subtractor and full adder or subtractor circuits. DISCUSSION QUESTIONS: 1. List the properties of Ex-Nor gate? 5. What are the gates involved for binary adder? 4. The connections are given as per the circuit diagram. 3. Two 4 – bit numbers added or subtracted depend upon the control input and the output is obtained.PROCEDURE: 1.

CIRCUIT DIAGRAM

Full Adder

Full Subtractor

Result:

………………………………………….. Signature of the staff in charge

Truth Table (a) Code converter (i) Binary to Gray (ii) Gray to Binary

B3 B2 B1 B0 G3 G2 G1 G0

G3 G2 G1 G0 B3 B2 B1 B0

Parity generator and Parity checker. Apparatus Required: S. Draw up the truth tables and logic diagram for the design . Pre-Laboratory :There are two tasks that you must perform prior to sitting this laboratory: 1.Experiment No: Date: __/__/____ Design and Implementation of Combinational circuits for Code Conversion. Parity generator and parity checker.No Components Specifications Quantity . Understand the design problem given to you. 2. Aim: To Design and Implement the combinational code converters.

K-Map Simplification (a)Binary to Gray 0 1 3 2 0 1 3 2 4 5 7 6 4 5 7 6 12 13 15 14 12 13 15 14 8 9 11 10 8 9 11 10 G0= G1= G2= 0 1 3 2 G3= 0 1 3 2 4 5 7 6 4 5 7 6 12 13 15 14 12 13 15 14 8 9 11 10 8 9 11 10 .

THEORY: Binary to gray: The MSB of the binary code alone remains unchanged in the Gray code. The gray code is often used in digital systems because it has the advantage that only one bit in the numerical representation changes between successive numbers. . Gray to binary: The MSB of the Gray code remains unchanged in the binary code the remaining bits are obtained by EX – OR ing the corresponding gray code bit and the previous output binary bit. The remaining bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous bit in the binary code.

K-Map Simplification (b) Gray to Binary 0 1 3 2 0 1 3 2 4 5 7 6 4 5 7 6 12 13 15 14 12 13 15 14 8 9 11 10 8 9 11 10 B3= B2= B1= 0 1 3 2 B0= 0 1 3 2 4 5 7 6 4 5 7 6 12 13 15 14 12 13 15 14 8 9 11 10 8 9 11 10 .

What is error deducting code? 5.DISCUSSION QUESTIONS ON CODE CONVERSION: 1. What is ASCII code? 6. Why weighted code is called as reflective codes? 3. What is the need for code conversion? . What is a sequential code? 4. List the procedures to convert gray code into binary? 2.

CIRCUIT DIAGRAM (a) Code Converter Truth Table (b) Parity generator for 3-bit message .

The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. if the four bits received has an even number of 1’s. A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even.Parity Generator and Parity Checker A parity bit is used for the purpose of detecting errors during transmission of binary information. Since the information was transmitted with odd parity the four bits received must have an odd number of 1’s. In even parity the added parity bit will make the total number of 1’s an even amount and in odd parity the added parity bit will make the total number of 1’s an odd amount. The parity checker circuit checks for possible errors in the transmission. . An error occurs during the transmission if the four bits received have an even number of 1’s.. where they are applied to the parity checker circuit. indicating that one bit has changed during transmission. i.e. An error is detected if the checked parity does not correspond with the one transmitted. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs. The message including the parity bit is transmitted and then checked at the receiving end for errors.

Truth Table (c) Parity Checker for 3-bit message K-Map simplification (c) Even Parity generator 0 1 3 2 (d) Odd Parity generator 0 1 3 2 4 5 7 6 PE = PO = 4 5 7 6 .

What are the gates involved for parity generator? . What is parity bit? 2.DISCUSSION QUESTIONS ON PARITY BIT: 1. What is parity checker? 4. What is odd parity and even parity? 5. Why parity bit is added to message? 3.

K-Map simplification (e) Even Parity Checker 0 1 3 2 (f) Odd Parity Checker 0 1 3 2 4 5 7 6 4 5 7 6 12 13 15 14 12 13 15 14 8 9 11 10 8 9 11 10 ∑E = ∑O = CIRCUIT DIAGRAM (c) Even Parity generator (d) Odd Parity generator (c) Even Parity Checker (d) Odd Parity Checker .

Signature of the staff in charge ..Result: - ………………………………………….

Truth Table (a) Decoder .

Understand the design problem given to you.No Components Specifications Quantity . 2. Apparatus Required: S.Experiment No: Date: __/__/____ Design and implementation of Encoders and Decoders AIM: To design and implement encoder using IC 74148 (8-3 encoder) Pre-Laboratory: There are two tasks that you must perform prior to sitting this laboratory: 1. Draw up the truth tables and logic diagram for the design.

Truth Table (b) Encoder .

In 3-8 line decoder the three inputs are decoded into right outputs in which each output representing one of the minterm of 3 input variables. The output lines generate a binary code corresponding to the input values 8 – 3 encoder circuit has 8 inputs. Enable inputs E1 should be connected to ground and Eo should be connected to VCC Decoder: A decoder is a combinational circuit that converts binary information from n input lines to 2n unique output lines. IC 74155 can be connected as a dual 2*4 decoder or a single 3*8 decoder desired input in C1 and C2 must be connected together and used as the C input. G is the enable input and must be equal to 0 for proper operation.THEORY: Encoder: An encoder is digital circuit that has 2n input lines and n output lines. . G1 and G2 should be connected and used as the G (enable) input. one for each of the octal digits and three outputs that generate the corresponding binary number.

Circuit/diagram (or) Pin configuration Decoder Encoder .

Connections are given as per the logic diagram. What are the necessary steps for implementing higher order decoders? 3. How to convert BCD to Decimal decoder? 5. What is encoding? 8. 2. What is BCD encoder? RESULT: …………………………………………. Signature of the staff in charge . What is the use of code converters? 4. How the output line will be activated in decoder circuit? 2.PROCEDURE: 1. What is the other name of encoder? 7. The truth table is verified by varying the inputs. DISCUSSION QUESTIONS: 1. What are the applications of encoder? 9. What is seven segment displays? 6..

Truth Table (a) 4:1 Multiplexer K-Map .

Experiment No: Date: __/__/____ Study of Multiplexer and Demultiplexer AIM: Pre-Laboratory: There are two tasks that you must perform prior to sitting this laboratory: 1. 2. Understand the design problem given to you.No Components Specifications Quantity . Draw up the truth tables and logic diagram for the design. Apparatus Required: S.

Truth Table (a) 1:4 Demultiplexer K-Map .

Normally. The selection of a particular input line is controlled by a set of selection lines. Therefore. multiplexer is ‘many into one’ and it provides the digital equivalent of an analog selector switch. The basic multiplexer has several data input lines and a single output line.THEORY: Multiplexer is a digital switch which allows digital information from several sources to be routed onto a single output line. DESIGN: 4 X 1 MULTIPLEXER LOGIC SYMBOL . there are 2n input lines and n selector lines whose bit combinations determine which input is selected.

Circuit Diagram (a) 4:1 Mux (b) 1:4 Demux .

1X4 DEMULTIPLEXER LOGIC SYMBOL .A Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. The selection of specific output line is controlled by the values of n selection lines.

Study of Mux and Demux using MSI devices: (a) Mux (4-1) (b) De-Mux (1-4) ( c ) 8:1 Mux (IC 74XX151) (d) Demux 1:8 (IC 74X138) .

What is serial to parallel converter? 6. What is the other name of de-multiplexer? 2. Signature of the staff in charge . 2.. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply. How many select lines needed for four outputs of DE-MUX? 4. Apply the inputs and verify the truth table for the multiplexer & demultiplexer. What are the applications of multiplexer? Result: - …………………………………………. How to enable the multiplexer? 8. DISCUSSION QUESTIONS: 1. What is other name of multiplexer? 5.PROCEDURE: 1. Compare MUX and DE-MUX? 3. 3. Connections are given as per the circuit diagrams. What is the use of select lines? 7.

(a) Pin Configuration of IC7476 ( Dual JK Flip flop) State table diagram for Mod-9 Synchronous Up counter: State table for Mod-9 Synchronous counter: .

Modulus of a counter is the total number of states through which the counter can progress. Furthermore. AIM: To design a mod-5 Synchronous Counter and 3-bit Asynchronous binary Counter using JK Flip-Flop and Verify their function with the truth table. In a counter. · Synchronous or parallel counter · Asynchronous or serial counter An asynchronous or ripple counter in which each flip-flop is triggered by the output of the previous flip-flop and all the FF’s do not change states in exact synchronism with the applied clock pulses. This is called look-ahead logic. The triggers move . For example mod-8 counter has 8 states. or they may originate from an external source and may occur at prescribed intervals of time or at random. A second technique is to precondition the logic inputs to each FF in order to omit certain states. called count pulses may be clock pulses. Counter of any modulus can be constructed by incorporating logic. Apparatus Required: S. The first flip flop must change state before it can trigger the second FF. which causes certain states to be skipped over. There are basically two different types of counters. Counter has a natural count of 2n where ‘n’ is the number of flip-flop in the counter. Logic can be included such that the counter can operate in either a count-up or count-down mode. logic gates can be designed to uniquely decode each state of a counter. A equential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a ‘counter’. and the second FF has to change state before it can trigger the third FF and so on. the sequence of states may follow a binary count or any other sequence of states.No Components Specifications Quantity THEORY: A counter is one of the most useful and versatile subsystems in a digital system. The input pulses. One technique for skipping counts is to steer clock pulses to certain FFs at the proper timethis is called steering logic. or omitted.Experiment No: Date: __/__/____ Design and Implementation of Synchronous and Asynchronous Counters.

K-Map Simplification for Mod-9 Synchronous Up counters Logic circuit for Mod-9 Synchronous Up counter .

Let as examine the countdown sequence for a 3-bit binary down counter. B and A represent a 3-bit binary number with C as the most significant bit (MSB). 4. A binary 3-bit ripple counter can be constructed by using the clocked JK flip-flop. 3. The normal output of FF-A acts as the clock input for FF-B. the overall propagation delay time is sum of all the individual delays i. After the NGT (negative going transition) of the seventh clock pulse has occurred the counter FF’s are in the 111 condition. however the same effect can be accomplished by driving each FF clock input from inverted output of preceding FF. and so FF-B will toggle each time the FF-A output goes from 1 to 0. Working of Three Bit Asynchronous Binary Counter 1. Note that J= K=1 for all the FF’s. Similarly. The important applications are (i) counting pulse. Thus. and A outputs. 1. C changes states each time B goes from LOW to HIGH. A synchronous counter in which all flip-flops change states simultaneously since all clock inputs are driven by the same clock and the settling time is equal to the delay time of a single flip-flop. The basic function of a counter is to “memorize” how many clock pulses have been applied to the input.through the flip-flop like a ripple in water. 1. FF outputs C.e. which will count downward from a maximum count to zero. Thus FF-A will toggle (change to its opposite state) each time the clock pulse make a negative (HIGH to LOW) transition. . The waveforms at A. B and C show that B toggles whenever A goes LOW to HIGH (so that Ā goes HIGH to LOW) and C toggles whenever B goes LOW to HIGH. (ii) frequency division (iii)time measurement (iv) control and timing operations. On the eighth NGT. and so on. hence in the most basic sense counters are memory systems. If the FFs have clock inputs that respond to negative transitions (HIGH to LOW). Therefore the speed of operation is limited. B. Therefore the speed of operation can be increased. Down Counter: Down counter is one. except first. the FF-A goes from 1 to 0 which causes FF-B to go from 1 to 0. Because of this. Let’s assume that all FF are in the logic ‘0’ states. Up Counter: Up counter is one. It can be seen that FF-A (LSB) changes states (toggles) at each step in the sequence just as it does in up counter. which will count upward from zero to a maximum count. The FF-B changes states each time B goes from LOW to HIGH. from where it will begin new a counting cycle as subsequent clock pulses are applied. A clock pulse is applied only to the clock input of FF-A. 2. 2. in a down counters each FF. the counter has gone through one complete cycle (000 through 111) and has recycled back 000. must toggle when the preceding FF goes from LOW to HIGH. then an inverter can be placed in front of each FF clock input. 5. In other words. B and C represent the FF output states as the counter goes through its sequence.The Ā output serves as the clock input for FF-B. The waveforms in fig 1 show that a binary counting sequence from 000 to 111 is followed as clock pulses are continuously applied. the B’ output serves as clock for FF-C. This results in the desired down counting sequence at the C. where ‘n’ is the total number of FF. FF-C will toggle when FF-B goes from 1to 0. until the counter is in the 000 state. this is illustrated in fig 2 for a Mod 8 down counter. 3. The input pulses are applied to the FF-A . A. the total settling time is approximately equal to n delay time of single FF. 2.

(b) Circuit Diagram for 3-bit Asynchronous Up Counter Truth Table for 3-bit asynchronous up counter and Timing Waveforms .

where N=5.110 and 111 as don’t care condition. Step 1: State transition diagram The state diagram for Mod-5 counter can be drawn as shown in figure below here it is assumed that the state transition from one state to another takes place when the clock pulse is asserted.The counter is to designed by treating the unused states 101. the counter remains in present state. 110. When the counter reaches the zero state. a logic gate whose output then indicates that the preset number of pulses has occurred detects it.Applications: Down counters are not as widely used as up counters. . the input of each FF in the counter must be at the correct level to ensure that the FF goes to the correct state. Their major application is in situations where it must be known when a desired number of input pulses have occurred. Design Procedure: In order to design a MOD-5 counter the number of flip-flops required is three. The undesired states 101. Step 2: State transition table Use the state transition diagram to setup a table that lists all present states and their next states. 010.This is found from the equation 2n ≥N. Design Of Mod-5 Synchronous Counter Basic idea: In synchronous counters the FF’s entire are clocked at the same time. In these situations the down counter is preset to desired number and then allowed to count down as the pulses are applied. Let us assume that the MOD-5 counter has five states 000. The inputs to these decoder circuits will come from the outputs of one or more of the FF’s. when the clock is unasserted. the process of designing a synchronous counter then becomes one of designing the logic circuits that decode the various states of the counter to supply the logic levels to each FF input. 011 and 100. and 111 are considered as don’t care condition. 001. Therefore. the number states present in MOD-5 counter. Before each clock pulse.

(c) Circuit Diagram for 3-bit Asynchronous Down Counter .

.We must consider each of these as an output from its own logic circuit with inputs from flip-flops C. Step 4: Excitation Maps Design the logic circuits to generate the levels required at each J and K input using Karnaugh’s map. C.Step 3: J-K flip-flop excitation table Step 4: Circuit excitation table Our design uses 3 FFs. The entries under each J and K are obtained from state transition table and JK FF excitation table. The circuit excitation table. This complete table is called circuit excitation table. KB and JA. B and A of each one has J and k input. Step 5: Implement the final expressions The logic circuits for each J and K inputs are implemented from the expressions obtained from the K-Mapping. JC. B and A. Therefore. JB. KA . Then we must design circuit for each one. lists six J and K inputs. KC. we must add three new columns as shown in the table.

.

PROCEDURE: 1. byte and word. Define bit. Define MOD counter? 5.. What are the applications of counters? 6. What is propagation delay in ripple counter? 4. State the types of counter? 7. What is ripple counter? 3. Compare synchronous and asynchronous sequential circuits? 2. DISCUSSION QUESTIONS: 1. Signature of the staff in charge . Define address of a memory. 2. Apply the input and verify the truth table of the counter. Result: - …………………………………………. Connections are given as per the circuit diagrams. 8.

SISO circuit diagram .Pin configuration of IC 7474 Data input = 1100 1.

No Components Specifications Quantity . PISO/PIPO. Apparatus Required: S. Aim: To study shift register using IC 7474 in all its modes SIPO/SISO. SIPO. PIPO Modes using suitable IC’s. PISO.Experiment No: Date: __/__/____ Design and implementation of 4-bit shift registers in SISO.

SIPO logic circuit .2.

the parallel shifting method is much faster than the serial shifting method. a) Serial-in Serial-out Shift Register (SISO) b) Serial-in Parallel-out Shift Register (SIPO) c) Parallel-in Serial-out Shift Register (PISO) d) Parallel-in Parallel-out Shift Register (PIPO) D flip flop is used for constructing shift register. Applications 1. A register might be used to accept input data from an alphanumeric keyboard and then present this data at the input of a microprocessor chip.THEORY: A register is a group of flip-flops that can be used to store a binary number. For example. a register could be used to accept output data from a microprocessor chip and then present this data on a CRT screen. 2. Parallel shifting involves shifting all the data bit simultaneously with single clock transition. They are classified into following four types based on how binary information is entered or shifted out. . serial or parallel) and similarly two ways to shift the data out of the register. It can be connected to form a number of different types of counter. A group of flip-flops connected in such way that a binary number can be shifted into or out of the flip-flops is called shift register. Hence. There are two ways to shift data into a resister (i.Serial shifting involves shifting data 1 bit at a time in a serial fashion beginning with either the MSB or LSB. An ‘n’ bit register has a group of ‘n’ FFs and is capable of storing any binary information containing ‘n’ bits. 3.e. · They are often used to momentarily store binary data at the output of a decoder. There must be one flip-flop for each bit in the binary number. The shift forms a very important link between main digital system and the input –output channels.

PIPO logic circuit .3.

. Define shift registers. What are the modes of shift register? 3. What is register? 2. DISCUSSION QUESTIONS: 1. How ring counter is implemented using shift registers? 4.PROCEDURE: · Give the circuit connections as per logic diagram. Define sequence generator? 6. · Give the input and the clock pulse · Observe the output. What are the types of shift register? 7. Signature of the staff in charge . Influence is made from the observation . Result: - …………………………………………. Compare parallel and serial sub registers? 5.

Truth Table Input Data A Input Data B C 0 1 0 0 1 1 1 Addition S4 S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 B 1 1 0 0 0 0 0 Subtraction D4 D3 D2 D1 0 0 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 A4 A3 A2 A1 B4 B3 B2 B1 1 1 0 0 1 1 1 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 .

1. The carries are connected in chain through the full adder. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left. 3. 2. The input carry to the adder is C0 and it ripples through the full adder to the output carry C4. 4 BIT BINARY SUBTRACTOR: The circuit for subtracting A-B consists of an adder with inverters. with subscript 0 denoting the least significant bits. THEORY: 4 BIT BINARY ADDER: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. 1 1 1 1 40 . 4.No. COMPONENT IC EX-OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7483 IC 7486 IC 7404 QTY. with the output carry from each full adder connected to the input carry of next full adder in chain. The input carry C0 must be equal to 1 when performing subtraction. APPARATUS REQUIRED: Sl. 3.Experiment No: Date: __/__/____ DESIGN OF 4-BIT ADDER AND SUBTRACTOR AIM: To design and implement 4-bit adder and subtractor using IC 7483. placed between each data input ‘B’ and the corresponding input of full adder. It can be constructed with full adders connected in cascade.

4-bit Parallel Adder 4-bit Parallel subtractor .

PIN DIAGRAM FOR IC 7483: .4 BIT BINARY ADDER/SUBTRACTOR: The addition and subtraction operation can be combined into one circuit with one common binary adder. are first added in the top 4 bit adder to produce the binary sum. ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The mode input M controls the operation. When M=1. Since each input digit does not exceed 9. together with the input carry. The 2 decimal digits. When M=0. together with an input carry from a previous stage. the output sum cannot be greater than 19. the circuit is adder circuit. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. the 1 in the sum being an input carry. 4 BIT BCD ADDER: Consider the arithmetic addition of two decimal digits in BCD. it becomes subtractor.

4-bit Parallel Adder/subtractor .

Signature of the staff in charge .Result: - …………………………………………..