33

PCI BUS OPERATIONS

CONTENTS AT A GLANCE PCI Bus Configuration and Signals
PCI Bus layout Knowing the PCI signals

General Bus Troubleshooting Further Study

By the late 1980s, the proliferation of 32-bit CPUs and graphics-intensive operating
systems made it painfully obvious that the 8.33MHz ISA bus was no longer satisfactory. The PC industry began to develop alternative architectures for improved performance. Two architectures are now prominent: VL and PCI. Although the VL bus seems ideal, some serious limitations must be overcome. Perhaps most important is the VL bus dependence on CPU speed—fast computers must use wait states with the VL bus, and the VL bus only supports one or two slots (maximum). Another problem is that the VL standard is voluntary, and not all manufacturers adhere to VESA specifications completely. In mid-1992, Intel Corporation and a comprehensive consortium of manufacturers introduced the Peripheral Component Interconnect (PCI) bus. Where the VL bus was designed specifically to enhance PC video systems, the 188-pin PCI bus looks to the future of CPUs (and PCs in general) by providing a bus architecture that also supports peripherals, such as hard drives, networks, etc. This chapter shows you the layout and operations of the PCI bus.

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PCI BUS CONFIGURATION AND SIGNALS

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PCI Bus Configuration and Signals
The PCI architecture is capable of transferring data at 132MB/sec—a great improvement over the 5MB/sec transfer rate of the standard ISA bus. Another key advantage of the PCI bus is that it will have automatic configuration capabilities for switchless/jumperless peripherals. Auto-configuration (the heart of Plug and Play) will take care of all addresses, interrupt requests, and DMA used by a PCI peripheral. Table 33-1 lists the features for a PCI bus. The PCI bus supports linear bursts, which is a method of transferring data that ensures that the bus is continually filled with data. The peripheral devices expect to receive data from the system main memory in a linear address order. This means that large amounts of data is read from or written to a single address, which is then incremented for the next byte in the stream. The linear burst is one of the unique aspects of the PCI bus because it will perform both burst reads and burst writes. In short, it will transfer data on the bus every clock cycle—this doubles the PCI throughput compared to buses without linear burst capabilities. The devices designed to support PCI have low access latency, reducing the time required for a peripheral to be granted control of the bus after requesting access. For example, an Ethernet controller card connected to a LAN has large data files from the network coming into its buffer. Waiting for access to the bus, the Ethernet is unable to transfer the data to the CPU quickly enough to avoid a buffer overflow—forcing it to temporarily store the file’s contents in extra RAM. Because PCI-compliant devices support faster access times, the Ethernet card can promptly send data to the CPU.
TABLE 33-1 FEATURES OF A PCI BUS ARCHITECTURE

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SYSTEM DATA AND TROUBLESHOOTING

Performance features include: s Data bursting as normal operating mode—both read and write s Linear burst ordering s Concurrency support (deadlock, buffering solutions) s Low latency guarantees for real-time devices s Access-oriented arbitration (not time slice) s Supports multiple loads (PCI boards) at 33MHz s Error detection and reporting s Multimaster; peer-to-peer communication s 32-bit multiplexed, processor independent s Synchronous, 8–33MHz (132MB/sec) operation s Variable length, linear bursting (both read and write) s Parity on address, data, command signals s Concurrency/pipelining support s Initialization hooks for auto-configuration s Arbitration supported s 64-bit extension transparently compatible with 32-bit s CMOS drivers; TTL voltage levels s 5-V and 3.3-V compatible

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The PCI bus supports bus mastering, which allows one of a number of intelligent peripherals to take control of the bus to accelerate a high-throughput, high-priority task. PCI architecture also supports concurrency—a technique that ensures that the microprocessor operates simultaneously with these masters, instead of waiting for them. As one example, concurrency allows the CPU to perform floating-point calculations on a spreadsheet while an Ethernet card and the LAN have control of the bus. Finally, PCI was developed as a dual-voltage architecture. Normally, the bus is a +5-Vdc system, like other busses. However, the bus can also operate in a +3.3-Vdc (low-voltage) mode.

PCI BUS LAYOUT
The layout for a PCI bus slot is shown in Fig. 33-1. Notice that there are two major segments to the +5-Vdc connector. A +3.3-Vdc connector adds a key in the 12/13 positions to prevent accidental insertion of a +5-Vdc PCI board into a +3.3-Vdc slot. Similarly, the +5-Vdc slot is keyed in the 50/51 position to prevent placing a +3.3-Vdc board into a +5-Vdc slot. The pinout for a PCI bus is shown in Table 33-2.
A1 A49 A52 A62 A63 A94 5 volt B1 A1 A11 A14 B49 B52 B62 B63 A62 A63 B94 A94 3.3 volt B1 B11 B14 PCI local bus diagrams. B62 B63 B94

FIGURE 33-1

TABLE 33-2 PCI BUS PINOUT—5 VOLT AND 3.3 VOLT (REV. 2.0) 5 VOLT –12 Vdc TCK Ground TDO +5 Vdc +5 Vdc –INTB –INTD –PRSNT1 Reserved –PRSNT2 Ground Ground 3.3 VOLT –12 Vdc TCK Ground TDO +5 Vdc +5 Vdc –INTB –INTD –PRSNT1 Reserved –PRSNT2 Key Key PIN B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 3.3 VOLT –TRST +12 Vdc TMS TDI +5 Vdc –INTA –INTC +5 Vdc Reserved +3.3 Vdc (I/O) Reserved Key Key 5 VOLT –TRST +12 Vdc TMS TDI +5 Vdc –INTA –INTC +5 Vdc Reserved +5 Vdc Reserved Ground Ground

PCI BUS CONFIGURATION AND SIGNALS

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TABLE 33-2 PCI BUS PINOUT—5 VOLT AND 3.3 VOLT (REV. 2.0) (CONTINUED) 5 VOLT Reserved Ground Clock Ground –REQ +5 Vdc Adr/Dat 31 Adr/Dat 29 Ground Adr/Dat 27 Adr/Dat 25 +5 Vdc C/ –BE3 Adr/Dat 23 Ground Adr/Dat 21 Adr/Dat 19 +5 Vdc Adr/Dat 17 C/ –BE2 Ground –IRDY +5 Vdc –DEVSEL Ground –LOCK –PERR +5 Vdc –SERR +5 Vdc C/ –BE1 Adr/Dat 14 Ground Adr/Dat 12 Adr/Dat 10 Ground Key Key Adr/Dat 8 Adr/Dat 7 +5 Vdc Adr/Dat 5 3.3 VOLT Reserved Ground Clock Ground –REQ +3.3 Vdc Adr/Dat 31 Adr/Dat 29 Ground Adr/Dat 27 Adr/Dat 25 +3.3 Vdc C/ –BE3 Adr/Dat 23 Ground Adr/Dat 21 Adr/Dat 19 +3.3 Vdc Adr/Dat 17 C/ –BE2 Ground –IRDY +3.3 Vdc –DEVSEL Ground –LOCK –PERR +3.3 Vdc –SERR +3.3 Vdc C/ –BE1 Adr/Dat 14 Ground Adr/Dat 12 Adr/Dat 10 Ground Ground Ground Adr/Dat 8 Adr/Dat 7 +3.3 Vdc Adr/Dat 5 PIN B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 PIN A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 3.3 VOLT Reserved –RST +3.3 Vdc –GNT Ground Reserved Adr/Dat 30 +3.3 Vdc Adr/Dat 28 Adr/Dat 26 Ground Adr/Dat 24 IDSEL +3.3 Vdc Adr/Dat 22 Adr/Dat 20 Ground Adr/Dat 18 Adr/Dat 16 +3.3 Vdc –FRAME Ground –TRDY Ground –STOP +3.3 Vdc SDONE –SBO Ground PAR Adr/Dat 15 +3.3 Vdc Adr/Dat 13 Adr/Dat 11 Ground Adr/Dat 9 Ground Ground C/ –BE0 +3.3 Vdc Adr/Dat 6 Adr/Dat 4 5 VOLT Reserved –RST +5 Vdc –GNT Ground Reserved Adr/Dat 30 +5 Vdc Adr/Dat 28 Adr/Dat 26 Ground Adr/Dat 24 IDSEL +5 Vdc Adr/Dat 22 Adr/Dat 20 Ground Adr/Dat 18 Adr/Dat 16 +5 Vdc –FRAME Ground –TRDY Ground –STOP +5 Vdc SDONE –SBO Ground PAR Adr/Dat 15 +5 Vdc Adr/Dat 13 Adr/Dat 11 Ground Adr/Dat 9 Key Key C/ –BE0 +5 Vdc Adr/Dat 6 Adr/Dat 4

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TABLE 33-2 PCI BUS PINOUT—5 VOLT AND 3.3 VOLT (REV. 2.0) (CONTINUED) 5 VOLT Adr/Dat 3 Ground Adr/Dat 1 +5 Vdc –ACK64 +5 Vdc +5 Vdc Key Key Reserved Ground C/ –BE6 C/ –BE4 Ground Adr/Dat 63 Adr/Dat 61 +5 Vdc Adr/Dat 59 Adr/Dat 57 Ground Adr/Dat 55 Adr/Dat 53 Ground Adr/Dat 51 Adr/Dat 49 +5 Vdc Adr/Dat 47 Adr/Dat 45 Ground Adr/Dat 43 Adr/Dat 41 Ground Adr/Dat 39 Adr/Dat 37 +5 Vdc Adr/Dat 35 Adr/Dat 33 Ground Reserved Reserved Ground 3.3 VOLT Adr/Dat 3 Ground Adr/Dat 1 +3.3 Vdc –ACK64 +5 Vdc +5 Vdc Key Key Reserved Ground C/ –BE6 C/ –BE4 Ground Adr/Dat 63 Adr/Dat 61 +3.3 Vdc Adr/Dat 59 Adr/Dat 57 Ground Adr/Dat 55 Adr/Dat 53 Ground Adr/Dat 51 Adr/Dat 49 +3.3 Vdc Adr/Dat 47 Adr/Dat 45 Ground Adr/Dat 43 Adr/Dat 41 Ground Adr/Dat 39 Adr/Dat 37 +3.3 Vdc Adr/Dat 35 Adr/Dat 33 Ground Reserved Reserved Ground PIN B56 B57 B58 B59 B60 B61 B62 Key Key B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93 B94 PIN A56 A57 A58 A59 A60 A61 A62 Key Key A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94 3.3 VOLT Ground Adr/Dat 2 Adr/Dat 0 +3.3 Vdc –REQ64 +5 Vdc +5 Vdc Key Key Ground C/ –BE7 C/ –BE5 +3.3 Vdc PAR64 Adr/Dat 62 Ground Adr/Dat 60 Adr/Dat 58 Ground Adr/Dat 56 Adr/Dat 54 +3.3 Vdc Adr/Dat 52 Adr/Dat 50 Ground Adr/Dat 48 Adr/Dat 46 Ground Adr/Dat 44 Adr/Dat 42 +3.3 Vdc Adr/Dat 40 Adr/Dat 38 Ground Adr/Dat 36 Adr/Dat 34 Ground Adr/Dat 32 Reserved Ground Reserved 5 VOLT Ground Adr/Dat 2 Adr/Dat 0 +5 Vdc –REQ64 +5 Vdc +5 Vdc Key Key Ground C/ –BE7 C/ –BE5 +5 Vdc PAR64 Adr/Dat 62 Ground Adr/Dat 60 Adr/Dat 58 Ground Adr/Dat 56 Adr/Dat 54 +5 Vdc Adr/Dat 52 Adr/Dat 50 Ground Adr/Dat 48 Adr/Dat 46 Ground Adr/Dat 44 Adr/Dat 42 +5 Vdc Adr/Dat 40 Adr/Dat 38 Ground Adr/Dat 36 Adr/Dat 34 Ground Adr/Dat 32 Reserved Ground Reserved

GENERAL BUS TROUBLESHOOTING

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KNOWING THE PCI SIGNALS
To reduce the number of pins needed in the PCI bus, data and address lines are multiplexed together (Adr./Dat 0 to Adr./Dat 63). It is also interesting to note that PCI is the first bus standard designed to support a low-voltage (+3.3 Vdc) logic implementation. On inspection, you will see that +5-Vdc and +3.3-Vdc implementations of the PCI bus place their physical key slots in different places so that the two implementations are not interchangeable. The Clock (CLOCK) signal provides timing for the PCI bus only, and can be adjusted from dc (0Hz) to 33MHz. Asserting the –Reset (–RST) signal will reset all PCI devices. Because the 64-bit data path uses eight bytes, the Command/ –Byte Enable (C/ –BE0 to C/ –BE7) signals define which bytes are transferred. Parity across the Address/Data and Byte Enable lines is represented with a Parity (PAR) or 64-Bit Parity (PAR64) signal. Bus mastering is initiated by the –Request (–REQ) line and granted after approval using the –Grant (–GNT) line. When a valid PCI bus cycle is in progress, the –Frame (–FRAME) signal is true. If the PCI bus cycle is in its final phase, –Frame will be released. The –Target Ready (–TRDY) line is true when an addressed device is able to complete the data phase of its bus cycle. An –Initiator Ready (–IRDY) signal indicates that valid data is present on the bus (or the bus is ready to accept data). The –FRAME, –TARGET READY, and –INITIATOR READY signals are all used together. A –Stop (–STOP) signal is asserted by a target asking a master to halt the current data transfer. The ID Select (IDSEL) signal is used as a chip-select signal during board configuration read and write cycles. The –Device Select (–DEVSEL) line is both an input and an output. As an input, –DEVSEL indicates if a device has assumed control of the current bus transfer. As an output, –DEVSEL shows that a device has identified itself as the target for the current bus transfer. The four interrupt lines are labeled –INTA to –INTD. When the full 64-bit data mode is being used, an expansion device will initiate a –64-Bit Bus Request (–REQ 64) and await a –64-Bit Bus Acknowledge (–ACK64) signal from the bus controller. The –Bus Lock (–LOCK) signal is an interface control used to ensure use of the bus by a selected expansion device. Error reporting is performed by –Primary Error (–PERR) and –Secondary Error (–SERR) lines. Cache memory and JTAG support are also provided on the PCI bus.

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SYSTEM DATA AND TROUBLESHOOTING

General Bus Troubleshooting
In most cases, you will not be troubleshooting a bus—after all, the bus is little more than a passive connector. However, the major signals that exist on an PCI bus can provide you with important clues about the system’s operation. The most effective bus troubleshooting tool available to you is a POST board (such as the ones covered in Chapter 15). Many POST boards are equipped with a number of LEDs that display power status, along with important timing and control signals. If one or more of those LEDs is missing, a fault has likely occurred somewhere on the motherboard. Remember that the vast majority of POST boards are designed for the ISA bus. You can plug a POST board (with a built-in logic probe capable of 33MHz operation) into an ISA connector, then use the logic probe to test key signals. Because the signals on a PCI bus are quite different than those on an ISA bus, try the following signals:
s Voltage Use your multimeter and check each voltage level on the PCI bus. You should be

able to find –12 Vdc and +5 Vdc, regardless of whether the bus is standard or low-voltage.

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For a low-voltage bus, you should also be able to find a +3.3-Vdc supply. If any of these supply levels are low or are absent, troubleshoot or replace the power supply. s CLOCK (pin B16) The Clock signal provides timing signals for the expansion device. It can be adjusted between DC (0Hz) and 33MHz. If this signal is absent, the expansion board will probably not run. Check the clock-generating circuitry on the motherboard or replace the motherboard outright. s RST (pin B18) The Reset line can be used to re-initialize the PCI expansion device. This line should not be active for more than a few moments after power is applied or after a warm reset is initiated.
PCI busses are highly dependent on a myriad of settings in the CMOS setup. Always check for proper CMOS configuration whenever you encounter trouble with PCI devices or bus performance.

Another point to consider is that bus connectors are mechanical devices. As a result, they do not last forever. If you or your customer are in the habit of removing and inserting boards frequently, it is likely that the metal “fingers” providing contact will wear, resulting in unreliable connections. Similarly, inserting a board improperly (or with excessive force) can break the connector. In extreme cases, even the motherboard can be damaged. The first rule of board replacement is: always remove and re-insert the suspect board. It is not uncommon for oxides to develop on board and slot contacts that may eventually degrade signal quality. By removing the board and re-inserting it, you can wipe off any oxides or dust and possibly improve the connections. The second rule of board replacement is: always try a board in another expansion slot before replacing it. This way, a faulty bus slot can be ruled out before suffering the expense of a new board. Keep in mind that many current PCI motherboards have only one or two PCI slots—the remainder are ISA slots. If a bus slot is defective, a technician can do little, except: 1 Block the slot and inform the customer that it is damaged and should not be used. 2 Replace the damaged bus slot connector (a tedious and time-consuming task) and pass the labor expense on to the customer. 3 Replace the motherboard outright (also a rather expensive option).

Further Study
That’s it for Chapter 33. Be sure to review the glossary and chapter questions on the accompanying CD. If you have access to the Internet, take a look at some of these various PCI resources: PCI Special Interest Group Home Page: http://www.pcisig.com/ PC2 Consulting: http://www.pc2.com/ CompactPCI Home Page: http://www.compactpci.com/ Small PCI: http://www.pcisig.com/current/smallpci/