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VL BUS OPERATIONS

CONTENTS AT A GLANCE VL Bus Configuraton and Signals
VL bus layout Knowing the VL signals

General Bus Troubleshooting
VL-specific issues

Further Study

The demands of data transfer across the expansion bus have continued to evolve
faster than the throughput of classic ISA/EISA bus architectures allow. The volumes of data required by graphic user interfaces (such as Microsoft’s Windows) present serious challenges to conventional video adapter and memory design. Early in 1992, the Video Electronics Standards Association (VESA) proposed a new local bus standard called the VESA Local bus (VL bus, also dubbed the Video Local bus) intended to improve the performance of graphics and video sub-systems. In general terms, a “local bus” is a pathway that allows peripherals to access the system’s main memory quickly. For the VL bus, such improved access means higher data throughput and performance for video information at the speed of the CPU itself. By using a stand-alone bus for video, ISA or EISA busses can be implemented for backward system compatibility. That is, users can upgrade to a new motherboard and graphics card, but all other peripherals and software remain compatible.

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Of course, the path to a “standard” local bus was not an easy one. In 1991 and 1992, a few chip set suppliers and manufacturers implemented non-standard high-performance I/O buses. For example, some OPTi chip sets were designed to support an OPTi local bus. Unfortunately, the OPTi local bus was supported by only a small handful of manufacturers, and because the OPTi approach was specific to their chip sets, few (if any) I/O cards were ever actually developed for these buses and few manufacturers provided them. Thus, OPTi and other proprietary buses met the same fate as all other non-standardized approaches in the PC industry—they disappeared. However, the failure of proprietary local bus designs did not prevent industry acceptance of a “standard” VL bus design developed by VESA (Video Electronics Standards Association) in late 1992. By placing the VL extension connectors in-line with standard ISA connectors, the VL board can also serve as an ISA board—only with far higher data throughput. The essential advantage of a VL bus is direct access to the CPU’s main busses. This allows a VL device to rapidly transfer the large quantities of data that are vital for high-performance video under Windows (and now Windows 95). Further, the VL bus operates at the motherboard’s bus speed, rather than a fixed 8.3MHz, like the ISA bus. As a result, faster CPU speed will result in faster bus speed. Unfortunately, this is where the advantages end. Although virtually direct connection to the CPU might seem like a real asset, you should understand the serious drawbacks. Processor dependence can ultimately become a disadvantage for the VL bus. Because higher processor speed results in higher bus capacitance, VL signals can lose reliability at high CPU clock frequencies. Further, the processor signals were intended to attach to only a few chips (such as the RAM controller) and have very precise timing rules. In fact, each type of Intel i486 chip (i.e., i486SX, i486DX, and i486DX/2) has slightly different timing requirements. When additional capacitance loads are added by adding multiple connectors and multiple local-bus chips, all sorts of undesirable things can happen. The two most likely problems are: data “glitches” caused by slowed processor bus signals and out-of-spec timing for different I/O cards with different loading characteristics.
i486-type CPUs are listed in this paragraph because the VL bus had largely fallen into disuse by the time Pentium processors arrived. You will only rarely (if ever) find a Pentium motherboard fitted with VL bus slots.

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Although the VL specification does not list an upper frequency limit, the potential load problems dictate a practical limit. With a clock speed of 33MHz, a VL motherboard should be able to support two VL devices reliably. At 40MHz, only one VL device should be used. Above 40MHz, the chances of unreliable operation with even one VL device become substantial. If you find yourself working on a fast VL system with random system errors, see if the problem goes away when the VL device(s) are removed (and replaced with ISA equivalents, if necessary). Another problem is the lack of concurrency. For a PCI bus, the CPU can continue operating when a PCI device takes control of the system busses. VL architecture also allows

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for bus-mastering operation, but when a VL device takes control of the bus, the CPU must be stopped. Although this is technically not a defect, it clearly limits the performance of high-end devices (e.g., SCSI controllers) that might attempt to use a VL architecture. Finally, the VL bus has several other disadvantages. It is a +5-Vdc architecture (where PCI can support +3.3-Vdc). Unlike PCI, no “auto-configuration” capability is in the VL bus (jumpers and DIP switches are required), so Plug-and-Play operation is not supported.

VL BUS LAYOUT
The VL bus uses a 116-pin card edge connector with small contacts (similar in appearance to MicroChannel contacts), as shown in Fig. 46-1. The most recent VL bus release (2.0) offers a 32-bit data path with a maximum data throughput of about 130MB/sec. The pinout for a VL bus is illustrated in Table 46-1. Interestingly, the VL bus has an extension to the standard ISA/EISA bus. The two right connectors are standard 16-bit ISA bus connectors. The two right-most connectors provide the VL compatibility. The long VL connector portion provides the 32-bit VL support. This is different than the PCI bus, which does not use any part of the ISA bus.
32-bit area 64-bit area

1 ISA segment FIGURE 46-1

45 48 VL segment

58

A simplified drawing of a VL card and bus.

TABLE 46-1 VL BUS PINOUT (REV. 2.0) PIN A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 DESCRIPTION Data 00 Data 02 Data 04 Data 06 Data 08 Ground Data 10 Data 12 +VCC Data 14 Data 16 Data 18 Data 20 Ground PIN B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 DESCRIPTION Data 01 Data 03 Ground Data 05 Data 07 Data 09 Data 11 Data 13 Data 15 Ground Data 17 +VCC Data 19 Data 21

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TABLE 46-1 VL BUS PINOUT (REV. 2.0) (CONTINUED) PIN A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 Key Key A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 DESCRIPTION Data 22 Data 24 Data 26 Data 28 Data 30 +VCC Address 31 Ground Address 29 Address 27 Address 25 Address 23 Address 21 Address 19 Ground Address 17 Address 15 +VCC Address 13 Address 11 Address 9 Address 7 Address 5 Ground Address 3 Address 2 n/c –RESET D/ –C M/ –I/O W/ –R PIN B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 Key Key B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 DESCRIPTION Data 23 Data 25 Ground Data 27 Data 29 Data 31 Address 30 Address 28 Address 26 Ground Address 24 Address 22 +VCC Address 20 Address 18 Address 16 Address 14 Address 12 Address 10 Address 8 Ground Address 6 Address 4 –WBAK –BE 0 +VCC –BE 1 –BE 2 Ground –BE 3 –ADS

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–RDYRTN Ground IRQ 9 –BRDY –BLAST ID 0 ID 1 Ground LCLK +VCC –LBS16

–LRDY –LDEV –LREQ Ground –LGNT +VCC ID 2 ID 3 ID 4 n/c –LEADS

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KNOWING THE VL SIGNALS
The Data/-Command (D/–C) signal tells whether information on the bus is data or a command. Clock signals from the CPU are provided through the Local Bus Clock (LCLK) line. Memory/–I/O (M/–I/O) distinguishes between memory and I/O access, while the Write/–Read (W/–R) signal differentiates between read or write operations. The –Byte Enable lines (–BE0 to –BE7) indicate which eight bit bytes of the data bus are being transferred. A –Reset signal (–RESET) will initialize the VL device. The –Ready Return (–RDYRTN) line indicates that the VL bus is free for access. Data bus width is determined by the –Local Bus Size 16 (–LBS16) signal. Accessing the VL bus is a process of arbitration—much like the arbitration that takes place on an MCA or EISA bus. Each VL device is defined by its own ID number (ID0 to ID4). The -Local Bus Ready (–LRDY), –Local Bus Device (–LDEV), –Local Bus Request (–LREQ), and –Local Bus Grant (–LGNT) lines are used to negotiate for control of the VL bus. In most cases, only one VL device is on the bus, but arbitration must be performed to ensure proper access to memory.

General Bus Troubleshooting
In most cases, you will not be troubleshooting a bus. After all, the bus is little more than a passive connector. However, the major signals that exist on a VL bus can provide you with important clues about the system’s operation. The most effective bus troubleshooting tool available to you is a POST board (such as the ones covered in Chapter 15). Many POST boards are equipped with a number of LEDs that display power status, along with important timing and control signals. If one or more of those LEDs is missing, a fault has likely occurred somewhere on the motherboard. Keep in mind that the vast majority of POST boards are designed for the ISA bus. You can plug a POST board (with a built-in logic probe capable of 33MHz operation) into an ISA connector (which will check the ISA portion of the VL connector arrangement), then use the logic probe to test key signals on the VL extension. Because the signals on a VL extension are quite different than those on an ISA bus, try the following signals:
s Voltage Use your multimeter and check each voltage level on the VL bus. You should

be able to find +5 Vdc. If any of these supply levels are low or absent, troubleshoot or replace the power supply. s LCLK (pin A56) The Local Bus Clock signal provides timing signals for the expansion device. It will typically be at the processor frequency. If this signal is absent, the expansion board will probably not run. Check the clock-generating circuitry on the motherboard, or replace the motherboard outright. s –RESET (pin A42) The Reset line can be used to re-initialize the VL expansion device. This line should not be active for more than a few moments after power is applied or after a warm reset is initiated. s M/–I/O (pin A44) The Memory/–I/O line indicates whether memory or I/O locations are being accessed. You can expect this signal to flicker or remain dim because it should switch modes very regularly. A problem here usually indicates trouble with the CPU or intervening logic. Try replacing the motherboard.

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s W/–R (pin A45) The Write/–Read line defines whether data is being read or written

across the bus. This signal should also flicker or remain dim because it should switch modes regularly. Problems with this signal usually indicate trouble with the CPU or intervening logic. Try replacing the motherboard. s –LRDY (pin B48)—the Local Bus Ready signal tells VL devices that the bus is ready for use. If this signal is frozen at logic 1, the VL device might not be releasing the bus or a problem with motherboard logic might be disabling the bus. Try removing the VL device or moving it to another slot. If that fails, try replacing the motherboard. Another point to consider is that bus connectors are mechanical devices—as a result, they do not last forever. If you or your customer are in the habit of removing and inserting boards frequently, it is likely that the metal “fingers” providing contact will wear and result in unreliable connections. Similarly, inserting a board improperly (or with excessive force) can break the connector. In extreme cases, even the motherboard can be damaged. The first rule of board replacement is: Always try removing and re-inserting the suspect board. It is not uncommon for oxides to develop on board and slot contacts that might eventually degrade signal quality. By removing the board and re-inserting it, you can wipe off any oxides or dust and possible improve the connections. The second rule of board replacement is: Always try a board in another expansion slot before replacing it. This way, a faulty bus slot can be ruled out before suffering the expense of a new board. Remember that many current VL motherboards have only one or two VL slots—the remainder are ISA slots. If a bus slot is defective, a technician can do little, except:
1 Block the slot and inform the customer that it is damaged and should not be used. 2 Replace the damaged bus slot connector (a tedious and time-consuming task) and pass

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the labor expense on to the customer.
3 Replace the motherboard outright (also a rather expensive option).

VL-SPECIFIC ISSUES
Although the VL-bus is generally considered to be a sound (but dated) bus architecture, some perplexing issues sometimes crop up on the workbench. The two major issues to contend with are bus speed and VL device types.
s Bus speed The VL bus is linked to the CPU clock speed. This was fine when CPUs ran

at 33MHz or less, but the VL bus wasn’t intended to support higher clock speeds. Clock speeds higher than 33MHz (often activated when a late-model i486 motherboard was upgraded with an OverDrive processor), could cause signal degradation—the VL device(s) would malfunction. Whenever you encounter difficulty on a VL motherboard, always verify that the bus speed is 33MHz or less. Notice that a single well-designed VL board can often run up to 40MHz (sometimes 50MHz), but this is extremely rare and should never be expected. s Multiple VL devices The VL bus was originally intended as a single-slot architecture (primarily for high-performance graphic accelerators of the day). When designers expanded the role of VL and added more VL slots, the potential for signal degradation increased. More than two VL devices often cause problems on VL motherboards (especially at clock speeds over 33MHz).

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Further Study
That’s it for Chapter 46. Be sure to review the glossary and chapter questions on the accompanying CD. If you have access to the Internet, take some time to review this VL bus resource: VESA (Video Electronics Standards Organization): http://www.vesa.org