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# Lebanese International University Bekaa CamPus

## Final Bxam: Logic Design (CENG300)

Fall 20L0

Duration: 2 hours

Answer All Questions" Calculators are allowed. Your handwriting gg.! be clear and readable. write your solutions ONLY on this exam booklet and show all work. Scratch papers are not allowed. Make sure all exam pages are included.

StudentName:
Student ID#
:

Question Number

Weight
20
15

i
2 J

10

4
5

20
10

25

Total 100

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Question

## Gir.r th. f"llowing

a)

Boolean functions F together with the don't care condition function d: F(A,B,C,D) : !m(2,3,4,6,8,9,I2,I 4) d(A,B,C,D) lm(7, i0,13) (10 points). Simplify using amap, then implement with NAND gates only

l:

(20 points)

CD

t\.? s.:\A'[.'.*rt

;*'^

g-{l-FtJ \$-.'c;

tr (4,6.c.b)

Fe-

.-r,'F,, M AN\

_q:.Lr--:tt

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(b) Implement using 4-1 MUX and some external logic gates

(10 points).

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0 t

Select

e 5

? Itrpurr
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4

to t n'lll-jt

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Ouestion

A s.qrential circuit has two D-latches, one input X, described by the following equations: r ._

2:

and

Da=

Dn:x@S

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N*o.b
fu=gh
I

fncr-l t}.i<-

f,f/f
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d)

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## (c) Derive the state diagram (5 points).

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Question 3: For the following sequential circuit: (a) Write the inPut and outPut equations. (b) Derive the state table.

(10 points)

I
b)

ry.*'rIl^o-{w*

Da= c f Y + kc.y\z
7"*'"L)"^
l

flrt4

\$= x@YG)Z
tfe{v efut"z
c)

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Qo Points) Question 4: circuit that produces three outputs: majority, minority, and It tr *q"tr.d to design a combinational
equal.

Majority output is equal to 1 if the input variables have more 1's than 0's. The output is 0 otherwise. Minority output is equal to 1 if the input variables have less 1's than 0's. The output is 0 otherwise. Equal o.rtp.riir.quuito 1 if the input variables have equal 1's and 0's. The output is 0 otherwise.
(a) Design a 4-bitcircuit for input majority, minority, and equal functions. (b) Implement the circuit with one decoder and External OR gates. .J , *4-f\

1.,b8-.

r"- T-fk

A,g,c, )
g*\$'o''
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Question

(")

(10 Points) The inputs for a negative edge triggered JK flip-flop are shown below. Assume that Q is initially zero, determine the Q output relative to the clock, and state in each case the state (5 points) change, Set, Reset, or

5:

Q.{o

Complement)

Clock

Jrl

## I t'l ' I ',! | ,*l I I

r-----------

r----T---l

{_'

;Li

ll

(b)

flip-flop are shown below. Assume that Q is relative to the clock, and state in each case the state initially zero, determine the Q output (5 points) (No change,'S@ or Complement)
The inputs for a negative edge triggered T

CLK

r] a

{1 = n:

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Question

6:
has two

(25 Points)

A r.q*ntial circuit

## The state diagram is

shown below" (a) Is the circuit a Mealy or a Moore? Justiff. (b) Derive the state table. (c) Design and implement the circuit using T flip-flops'

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01.

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tf

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