Freescale Semiconductor Application Note

Document Number: AN3063 Rev. 0, 02/2006

MSC8122/26 Ethernet MII Quick Start
by Dejan Minic DSD Applications Freescale Semiconductor, Inc. Austin, TX

This application note presents a detailed code example that illustrates how to program the MSC8122/26 Ethernet controller in media-independent interface (MII) mode. The application note reviews the basics of the MSC8122/26 Ethernet controller, describes the MSC8122ADS board configuration, and takes a close look at the code. The MSC8122/6 Ethernet controller supports MII, reduced MII (RMII), and serial MII (SMII) for the 10/100 Ethernet rate.

Contents 1 Ethernet Controller Basics . . . . . . . . . . . . . . . . . . . . . .1 2 MSC8122ADS Board Configuration . . . . . . . . . . . . . .2 3 MII MAC2MAC Exercise . . . . . . . . . . . . . . . . . . . . . .3 3.1 MSC8103 Code (Host) . . . . . . . . . . . . . . . . . . . . . .3 3.2 MSC8122 Code (Slave) . . . . . . . . . . . . . . . . . . . . .4 3.3 Ethernet_Setup() . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 MII MAC2MAC External Exercise . . . . . . . . . . . . . .27

1

Ethernet Controller Basics

The MSC8122/26 Ethernet controller complies with IEEE® Std. 802.3™. It works with minimal SC140 core intervention and operates in ether full duplex mode for connecting the Ethernet to an on-board Ethernet switch or half-duplex mode for connecting the Ethernet to an on-board physical layer–PHY. On the receive side, the SC140 core prepares empty buffers and points to these buffers through up to four rings residing in memory. The Ethernet controller reads the descriptors, fills their associated buffers with the received buffers, and interrupts the SC140 core. On the transmit side, the SC140 core prepares buffers in memory and a descriptor ring that points to those buffers. The Ethernet controller reads these descriptors, reads the data from the buffers, and sends the data over the Ethernet. Enhanced pattern matching enables the received frames to be processed with a wide variety of
© Freescale Semiconductor, Inc., 2006. All rights reserved.

MSC8122ADS Board Configuration

tools to assist in network applications. Features such as extraction of data and filing of frames in queues based on a pattern hit can accelerate post processing of data. Pattern matching can further enhance address recognition by applying additional filtering to frames that pass the destination address check. Flexibility is built into pattern matching architecture to increase control in manipulating receive frames. When the receiver detects the first bytes of a frame, the Ethernet controller begins to perform the frame recognition functions. It first attempts to filter the frames by matching a pattern in the frame. If it fails, it filters according to the MAC address. Pattern matching is performed using user-selected patterns of flexible length, up to 256 bytes into the frame. For example, if four patterns of 16 bytes are used, incoming frames can be filtered to four destination queues, each dedicated to one DSP subsystem. Frames can be filtered not only by their MAC address but also by their IPv4 or IPv6 address and even their UDP port number. Based on these matches, the frame is accepted or rejected. When a frame is accepted, the Ethernet controller processes it on the basis of user-defined attributes. The receiver can also receive physical (individual), group (multicast), and broadcast addresses. The Ethernet transmitter requires very little SC140 core intervention. The transmitter takes data from the Tx FIFO and transmits data to the MAC. The MAC transmits the data through the MII/RMII/SMII interface to the physical media. The transmitter runs until the end-of-frame (EOF) condition is detected, unless there is a collision within the collision window (half-duplex mode) or an abort condition is encountered. In SMII mode, the Ethernet controller supports a MAC-to-MAC interface. In all three modes, the Ethernet controller can automatically gather network statistics required for RMON without the need to receive all addresses using promiscuous mode. For details, see the chapter on the Ethernet controller in the MSC8122 or MSC8126 reference manual.

2

MSC8122ADS Board Configuration

The MSC8122ADS board must be properly configured for the Ethernet exercises to work properly. Refer to Figure 1 for configuration and location of the switches and jumpers on the MSC8122ADS board. For the MII MAC2MAC Ethernet exercise mode, the JP8 jumper must be connected.

JP8

Must Be Connected in MII MAC2MAC Mode

JP6 MSC8103 MSC8122

SW7

All Jumpers Must Be Connected when ETH_SEL = 1 ETH_ON Must Be Selected

Figure 1. MSC8122ADS Switch and Jumper Configuration
MSC8122/26 Ethernet MII Quick Start, Rev. 0 2 Freescale Semiconductor

and the MAC2MAC exercise completed. the MSC8103 host configures the BCSRn as shown in Table 1. Run the host project. 0x15000000). For this exercise. 2. 3. 0xC0000000) Write(BCSR7. Run the slave project. Rev. 0x07000000). 0 Freescale Semiconductor 3 . During the debug session. you can run the MSC8122 Ethernet exercise as follows: 1. 0xD0000000) MII MAC TO MAC DSI MSC8122/26 Ethernet MII Quick Start.1 MSC8103 Code (Host) The MSC8103 serves as a host to configure the board control and status registers (BCSRn). an STDIO window appears and displays the following message to indicate that the MSC8101/3 configuration of the MSC8122ADS board has successfully completed: BCSR Init completed 4. • DTEST_TYPE=MII_M2M_TP • DTEST_SPEED=SPEED_100_MBPS This exercise for both host and slave CodeWarrior™ projects is available in the AN3063SW zip file in the directory named MII_MAC2MAC_internal_loopback\projects\feth_all_tests_fulld_gpio_and_dsi. Three messages indicate that the test ran. Table 1. NOP(100) Write(BCSR7.MII MAC2MAC Exercise 3 MII MAC2MAC Exercise When the MSC8122ADS board is properly set up. Download and run the MSC8122 project. Write(BCSR9. Download and run the host (MSC8101/3) project. BCSR Configuration for the MAC2MAC Exercise Mode MII MAC TO MAC Port GPIO BCSR Configuration Write(BCSR7.Core number 1 MIIGSK_ENR=3 Frame Was Received MII mode requires the following preprocessor macros to be added in the project settings under the I/O and Preprocessors panel for both host and slave projects. NOP(100) Write(BCSR7. 0x07000000). the Ethernet frame was successfully received. 0x15000000). Write(BCSR9. 3. Welcome to ENET MII test .

Core number %d\n". Write((currDataAddress+0x14). No configuration is necessary for the MAC2MAC mode described in this document.MII MAC2MAC Exercise 3. Write((currDataAddress+0x10).0xFFFFFFFF).0xF0FCDA00).0x00006364). The transmit buffer descriptors are initialized for 1000 frames: initTXBDs(NUM_OF_FRAMES). Write((currDataAddress+0x38). Write((currDataAddress+0x0C). MSC8122/26 Ethernet MII Quick Start. Write((currDataAddress+0x34).core_id). Write((currDataAddress+0x18). Write(MACCFG1.0x42130000).0x63640000). Read(CIDR. Write((currDataAddress+0x1C). Write((currDataAddress+0x28).0xFFFFFFFF).0xFFFFFFFF). configPhyForTest().0x002EAAAA). Write((currDataAddress+0x0C). the MSC8122 code can run.0xFFFFFFFF).0x00006364). Write(currDataAddress. Following are the values to which the data patterns are initialized.0xAAAAAAAA). Write((currDataAddress+0x20). The following lines simply read and display the core ID. // DATA Buffer 1 // data: 0xAAAAAAAA currDataAddress += 0x100.2 MSC8122 Code (Slave) When the MSC8101/03 host is running. initDataPatterns().0xFFFFFFFF). The code starts with the variable and vector initialization. The following function configures the MSC8122 PHY for the selected Ethernet operating mode.0xFFFFFFFF). Write((currDataAddress+0x14).0xFFFFFFFF). Write((currDataAddress+0x30). Write((currDataAddress+0x08). indicating the beginning of the MSC8122 Ethernet exercise. Rev. The following lines perform a soft reset on all MAC modules. 0 4 Freescale Semiconductor . Write(MACCFG1. Write((currDataAddress+0x24). Write((currDataAddress+0x10). MACCFG1_SOFT_RESET).0xAAAAAAAA). The following function initializes the data patterns for use in transmitting the Ethernet frame. Write((currDataAddress+0x2C). // DATA Buffer 0 // data: 0xFFFFFFFF Write(currDataAddress.0xFFFFFFFF).0x002EFFFF).0xFFFFFFFF). Write((currDataAddress+0x04).&core_id). NOP(10000).0xFFFFFFFF). printf("Welcome to ENET MII test . TYPE32BIT currDataAddress = FIRST_TX_DATA_ADDRESS.0x00000000). 0x0). Write((currDataAddress+0x04). Write((currDataAddress+0x08).0xFFFFFFFF).

0x00000000).0x00000000). Write((currDataAddress+0x1C).0x55555555). configEthernetRegisters().0xAAAAAAAA).0x55555555).0x55555555). MSC8122/26 Ethernet MII Quick Start. the receive buffer descriptors are initialized for the 1000 frames. Write((currDataAddress+0x20). enableTXBDs(NUM_OF_FRAMES).0x42130000).0x002E0000). Write((currDataAddress+0x24).0x00000000). Once the Ethernet Controller is configured the transmit buffer descriptors are enabled. Write((currDataAddress+0x30). initRXBDs(NUM_OF_FRAMES).0x55555555).0x00000000).0xAAAAAAAA).0x55555555). // DATA Buffer 3 // data: 0x00000000 currDataAddress += 0x100.0xAAAAAAAA). Write((currDataAddress+0x14).0xAAAAAAAA).0xF0FCDA00). Write((currDataAddress+0x08). Write((currDataAddress+0x2C). Write((currDataAddress+0x18). // DATA Buffer 2 // data: 0x55555555 currDataAddress += 0x100. Write((currDataAddress+0x14). Write((currDataAddress+0x20). Write((currDataAddress+0x0C). The configEthernetRegisters() function is used to configure the MSC8122 Ethernet controller registers.0x55555555). Write((currDataAddress+0x28).MII MAC2MAC Exercise Write((currDataAddress+0x18). Write((currDataAddress+0x24). Write((currDataAddress+0x28). Next. Write((currDataAddress+0x34). Write((currDataAddress+0x04).0x002E5555). Rev. Write((currDataAddress+0x28). Write(currDataAddress.0xAAAAAAAA). Write((currDataAddress+0x0C).0x00000000). Write((currDataAddress+0x18).0xAAAAAAAA). Write((currDataAddress+0x20). Write((currDataAddress+0x10).0x00000000). Write((currDataAddress+0x2C).0x00000000). Write((currDataAddress+0x1C). Write((currDataAddress+0x30). Write((currDataAddress+0x34).0x00000000). Write((currDataAddress+0x04). Write((currDataAddress+0x2C).0xAAAAAAAA). 0 Freescale Semiconductor 5 .0x00006364).0x55555555).0xF0FCDA00). Write((currDataAddress+0x38).0x00000000). Write((currDataAddress+0x34). Write((currDataAddress+0x10). Write((currDataAddress+0x08). Write((currDataAddress+0x38).0xAAAAAAAA).0x00000000).0x55555555). Write((currDataAddress+0x1C).0x55555555).0xAAAAAAAA).0x00000000).0x55555555).0x42130000). Write((currDataAddress+0x30). Write(currDataAddress.0x55555555).0x00006364). Write((currDataAddress+0x38). Write((currDataAddress+0x24).

NOP(100000). Bit Type Value Bit Type Value 0 1 2 3 4 5 6 — 7 R 0 23 MIILB R/W 1 8 9 10 11 12 RRXM 13 14 15 SRESET R/W 0 0 16 17 0 18 0 19 — R 0 0 20 0 21 0 22 0 24 — R 0 0 25 0 26 0 27 0 28 RTXM RRXF RTXF R/W 0 0 0 29 30 31 0 0 0 0 0 0 0 RXFL TXFL SYRXEN RXEN SYTXEN TXEN R/W R R/W R R/W 0 0 0 1 0 1 Figure 2. 0 6 Freescale Semiconductor . Reset Tx MAC. printf("READY=%x\n". Write(MIIGSK_ENR. Write to zero for future compatibility. The MIIGSK_ENR[READY] bit is polled until the Ethernet controller is ready for use. NOP(100). Reset Rx MAC. the MIIGSK[EN] bit is set. MAC Configuration 1 Register (MACCFG1R) Table 2 describes the functions of the MACCFG1R bits and states the values assigned to these bits for this exercise. which is shown in Figure 2. The following code ensures that the Ethernet controller is ready for use. The following lines configure the MAC configuration register 1 (MACCFG1R).&ready). Reserved. } printf("MIIGSK_ENR=%x\n". This 0 block multiplexes data and control frame transfers.ready). while(ready != 0x3) { NOP(10).ready). Read(MIIGSK_ENR. Read(MIIGSK_ENR. MACCFG1R Field Descriptions Bit SRESET 0 — 2–11 RRXM 12 RTXM 13 Description Soft Reset. 0 Value for This Exercise Normal operation.&ready). MSC8122/26 Ethernet MII Quick Start. 0 Normal operation. Table 2. This block detects control frames and contains the pause timers. It also responds to XOFF pause control frames.MII MAC2MAC Exercise Next.0x00000105). Write(MACCFG1. Puts all MAC modules into reset. which enables the Ethernet controller to transmit/receive Ethernet frames.0x1). Normal operation. Puts the PETMC transmit MAC control block into reset. Puts the receive MAC control block into reset. Rev.

0 0 Value for This Exercise Normal operation. Frame transmission is not enabled. No transmit pause flow control frames. MIIGSK Configuration Register (MIIGSK_CFGR) to set up certain overall modes and features of the Ethernet controller. Allows the MAC to transmit frames from the system. Transmit Enable. Reserved. Reset Tx Function. Causes the MII MAC transmit outputs to be looped back to the 1 MAC receive inputs.&ready). Read(0x02009000. Puts the receive function block into reset. 0 1 0 1 The following polling code detects when the frame transmission is complete. Write to zero for future compatibility. MACCFG1R Field Descriptions (continued) Bit RRXF 14 RTXF 15 — 16–22 MIILB 23 — 24–25 RXFL 26 TXFL 27 SYRXEN 28 RXEN 29 SYTXEN 30 TXEN 31 Description Reset Rx Function. Receive Enable. This block performs the frame transmission protocol. 0 Ignore receive pause flow control frames. Allows the transmit MAC control to send pause flow control frames if 0 the system requests them. Receive enable synchronized to the receive stream. Clearing this bit prevents the transmit MAC control from sending flow control frames. This block performs the receive frame protocol. MIIGSK Enable Register (MIIGSK_ENR) to enable Ethernet operation. Synchronized TX Enable. 0 Freescale Semiconductor 7 . Causes the receive MAC control to detect and act on pause flow control frames. and code execution stops at the debug statement.&ready).0xdc00003c). Puts the transmit function block into reset. Clearing this bit prevents the reception of frames. Write to zero for future compatibility. MII Loopback mode.3 Ethernet_Setup() The Ethernet_Setup() function is used to configure the Ethernet controller registers. Frame reception is not enabled. Transmit Enable synchronized to the transmit stream. asm(" debug"). Tx Flow. MAC can receive frames. Clearing this bit prevents the transmission of frames. Rev. Normal operation. printf("Frame Was Received\n"). } The following lines execute when the frame is received. Synchronized Rx Enable. Allows the MAC to receive frames from the PHY. Write(0x02001000. This section describes the process of using this function to configure the following registers in the order listed: 1. Reserved. while(ready!=0x0c000040) { Read(0x02009000. MSC8122/26 Ethernet MII Quick Start. Rx Flow.MII MAC2MAC Exercise Table 2. 2. 3. MAC can transmit frames. MII Loopback.

the following registers are configured: Write(MIIGSK_CFGR. the clock source (ETHCLOCK) is 125 MHz to support 100 Mbps operation. 0 8 Freescale Semiconductor . 0 Frequency Control. MAC configuration 2 register (MACCFG2R). This field has no effect in MII mode. 6. 0x00000000). Description Values for This Exercise MSC8122/26 Ethernet MII Quick Start. stIPBus1Regs->stEnet. 10. MAC station address registers. Interrupt Mask Register (IMASK) to enable the events specified in IEVENT. Maximum receive buffer length R0R1 Register (MRBLR0R1) to define the maximum number of bytes that can be written to a receive buffer descriptor ring before moving to the next buffer.vuliMIIMCFGR = 0x00000000. In SMII mode. DMA maintenance and control registers and an Ethernet control register. For this example. ETHCLOCK. MIIGSK_CFGR Bit Descriptions Bit — 0–24 FRCONT 25 Reserved. These two user-programmable registers hold the physical address that the Ethernet controller compares with the destination address field of the received frame. Rev. 5. Interrupt Event Register (IEVENT) to set up and specify interrupt events. ETHREF_CLK. 4. 9. 7. (In SMII mode. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 8 — R 0 16 0 17 0 18 0 19 0 20 — R 0 0 21 0 22 0 23 0 24 0 25 FRCONT R/W 0 0 26 — R 0 0 27 0 28 0 29 — R 0 0 30 0 31 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 LBMODE EMODE R/W 0 0 IFMODE R/W 0 0 Figure 3. MIIGSK_CFGR is a user-programmable register with configuration bits for different modes and features of the MSC8122 Ethernet controller. Group Address Registers 0–7 (GADDR[0–7]) and Individual Address Registers 0–7 (IADDR[0–7]) for hash functionality. MIIGSK Configuration Register (MIIGSK_CFGR) Table 3 describes the functions of the MIIGSK_CFGR bits and states the values assigned to these bits for this exercise. the clock source (ETHREF_CLK) is 50 MHz to support 100 Mbps operation. For MAC-to-MAC operation. A set of pattern matching control and attribute registers. 8.MII MAC2MAC Exercise 3. MACSTADDR1R and MACSTNADDR2R. and in RMII mode. In RMII mode.). this register is configured as shown in Figure 3. Determines the frequency of the clock source to the Ethernet controller to support 10/100 Mbps operations in RMII/SMII modes of operation. Table 3. which is the second of two user-programmable registers to configure MAC functionality.

Reserved. Description Values for This Exercise 0 Normal operation (the default). Causes the Ethernet controller RMII/SMII transmit outputs to be looped back to the Ethernet controller RMII/SMII receive inputs. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 — R 0 16 0 17 0 18 0 19 0 20 0 21 0 22 — 0 0 0 0 0 0 0 R 0 0 0 0 0 0 0 0 23 0 24 0 25 0 26 0 27 0 28 0 29 0 30 READY 1 0 31 EN R/W 1 8 9 10 11 12 13 14 15 Figure 4.0x1). Enables/disables Ethernet controller operation. For this example. 0 Normal operation. Causes the Ethernet controller MII receive inputs from the MII PHY to be looped back to the Ethernet controller transmit outputs to the MII PHY. RMII/SMII Sync Out . MIIGSK_CFGR Bit Descriptions (continued) Bit — 26 LBMODE 27 EMODE 28 — 29 IFMODE 30–31 Reserved. Enable.Internal Loopback Mode. Specifies the type of interface to which the Ethernet controller is connected. 1 The Ethernet controller can transmit/receive frames. This bit is read-only. The MIIGSK_ENR register enables or disables Ethernet controller operation and indicates when the Ethernet controller is ready for use. When MIIGSK_CFGR is configured. Table 4. 00 MII mode. this register is configured as shown in Figure 4. Description Values for this Exercise MSC8122/26 Ethernet MII Quick Start. Interface Mode. Echo Mode. Rev. the Ethernet controller must be enabled for operation. MIIGSK_ENR Bit Descriptions Bit — 0–29 READY 30 EN 31 Reserved. as follows: Write(MIIGSK_ENR. Ready.MII MAC2MAC Exercise Table 3. This bit is set when the Ethernet controller is ready for use. MIIGSK Enable Register (MIIGSK_ENR) Table 4 describes the functions of the MIIGSK_ENR bits and states the values assigned to these bits for this exercise. 0 Freescale Semiconductor 9 .

Rev. Preamble Length. Enables MAC CRC checking. 0 10 Freescale Semiconductor . This register is configured as follows (see Figure 5): Write(MACCFG2R. MAC Configuration 2 Register (MACCFG2R) Table 5 describes the functions of the MACCFG2R bits and states the values assigned to these bits for this exercise. Indicates padding and CRC status. Causes the MAC to check the frame length field to ensure that it matches the actual data field length. Reserved. Write to zero for future compatibility. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 8 — R 0 24 R 9 10 11 12 13 14 15 0 16 0 17 0 18 0 19 0 20 R 0 21 0 22 — R/W 0 23 0 25 0 26 — R 0 0 27 LENC R/W 1 0 28 — R 0 0 29 0 30 0 31 0 PREAL R/W 1 1 1 0 0 0 1 0 0 PADCRC CRCEN FDUP R/W 0 0 1 Figure 5. Values for This Exercise MSC8122/26 Ethernet MII Quick Start. A preamble length of 0 is not supported. Selects half-duplex or full-duplex mode. Write to zero for future compatibility. Table 5. PAD/CRC. which is the second of two user-programmable registers to configure MAC functionality. we set up the MAC configuration 2 register (MACCFG2R). The maximum value is 0x7. Full-duplex mode. Reserved. Reserved. Determines the length in bytes of the preamble field in the 0b0111 packet. Write to 0b000100 for future compatibility. Frame valid with valid CRC. Full Duplex. which is the default value. 1 The MAC checks the frame length field. Write to zero for future compatibility. 0 0 1 No padding and no CRC. CRC Enable.0x00007115). Description Reserved. MACCFG2R Field Descriptions Bit — 0–15 PREAL 16–19 — 20–25 26 LENC 27 — 28 PADCRC 29 CRCEN 30 FDUP 31 Length Check.MII MAC2MAC Exercise Next.

The fifth octet (SA5) holds a value of 0x63. Write(MACSTNADDR2R. These two user-programmable registers hold the physical address that the Ethernet controller compares with the destination address field of the received frame. we configure the MAC station address registers. MAC Station Address Part 2 Register (MACSTADDR2R) Next. Both registers are configured as follows. Rev. and bits 24–31 (SA4) hold the fourth octet of the station address. Write(MACSTNADDR1R. bits 8–15 (SA2) hold the second.0x63640000). we configure the Interrupt Event Register (IEVENT) as follows: Write(IEVENT.0x0). MSC8122/26 Ethernet MII Quick Start. bits 0–7 (SA1) hold the first octet of the station address. MACSTADDR1R and MACSTNADDR2R. Bit Type Value Bit Type Value 0 1 2 3 SA5 R/W 0 16 1 17 1 18 0 19 0 20 0 21 1 22 1 23 — R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 1 25 1 26 0 27 0 28 1 29 0 30 0 31 4 5 6 7 8 9 10 11 SA6 12 13 14 15 Figure 7. All four octets of the MACSTNADDR1R are configured to the default value of 0x00. 0 Freescale Semiconductor 11 . Bit Type Value Bit Type Value 0 1 2 3 SA1 R/W 0 16 0 17 0 18 0 19 SA3 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 0 21 0 22 0 23 0 24 0 25 0 26 0 27 SA4 0 28 0 29 0 30 0 31 4 5 6 7 8 9 10 11 SA2 12 13 14 15 Figure 6. and the sixth octet (SA6) holds a value of 0x64.0x0). MAC Station Address Part 1 Register (MACSTADDR1R) Bits 0–7 (SA5) and bits 7–15 (SA6) of the MACSTNADDR2R contain the remaining two octets (fifth and sixth octets).MII MAC2MAC Exercise Next. As shown in Figure 6. bits 16–23 (SA3) hold the third.

Transmit Control Interrupt. No interrupt. Write to zero for future compatibility. During a graceful stop. 0 12 Freescale Semiconductor . the DMA controller discards the frame. No system bus error. a pause operation is performed. • Completion of a graceful stop initiated by setting DMACTRL[GTS]. Busy Condition Interrupt. Interrupt Event Register (IEVENT) Table 6 describes the functions of the IEVENT bits and states the values assigned to these bits for this exercise. This bit is set when any transmit error causes the transmitter to halt (EBERR. MSC8122/26 Ethernet MII Quick Start. 0 No control frame. • Completion of a graceful stop initiated by setting TCTRL[TFCP]. If EBERR is set while a frame is being received. which eventually causes an underrun error (XFUN). Transmit Error. LC. Graceful Transmit Stop Complete. Write to zero for future compatibility. Generates an interrupt for one of two reasons. MSTAT Register Overflow. Frame truncation occurs when this condition occurs. Babbling Transmit Error. As soon as the transmitter finishes sending the current frame. A control frame was transmitted.MII MAC2MAC Exercise Bit Type Value Bit Type Value 0 — 0 16 1 2 3 4 — R 0 20 5 6 7 8 TXC 0 24 9 TXE 0 25 10 11 12 IE 0 28 13 LC 0 29 — R 14 15 RXC BSY EBERR R/W 0 0 0 17 18 19 MSRO GTSC BABT R 0 0 0 21 — R 0 22 23 TXB TXF R/W 0 0 26 27 CRL XFUN 0 30 0 31 RXB0 RXB1 RXB2 RXB3 R/W 0 0 0 0 0 0 GRSC RXF0 RXF1 RXF2 RXF3 R/W 0 0 0 0 0 0 0 0 0 Figure 8. CRL. 0 — 4 MSRO 5 GTSC 6 No MSTAT Register overflow. BABT 7 TXC 8 TXE 9 0 Normal Operation. No transmit error. A system bus error occurred during a DMA transaction. 0 If EBERR is set while a transmission is in progress. XFUN). Table 6. Reserved. Rev. the transmitter is put into a pause state after completion of the frame being transmitted. the DMA controller stops sending data to the Tx FIFO. IEVENT Bit Descriptions Name 0 RXC 1 BSY 2 EBERR 3 Description Reserved. Ethernet Bus Error. A control frame was received (MACCFG1R[RFCE] must be set). Generates an interrupt if the count for one of the 0 MSTAT registers exceeds the size of the register. The transmitted frame length has exceeded the value in the MACs Maximum Frame Length register. Values for This Exercise 0 No frame discarded. Set if a frame is received and discarded due to a lack of buffers. An error on the transmitted channel that caused the Ethernet 0 controller to set TSTAT[THLT]. Receive Control Interrupt. 0 No control frame.

and the remainder of the frame is discarded. Write to zero for future compatibility. This occurs only in Half-Duplex mode. A frame was received in queue 1 and the last RxBD in that frame was updated. 0 Values for This Exercise Normal operation. Normal operation. A TxBD whose Interrupt (I) bit was set in its status word was 0 updated but was not the last BD of the frame. Normal operation. No receive frame interrupt. An RxBD from queue 1 with the Interrupt (I) bit in its status 0 word was updated but was not the last BD of the frame. Reserved. No frame transmitted. The frame is truncated with a bad CRC. An RxBD from queue 3 with the Interrupt (I) bit in its status 0 word was updated but was not the last BD of the frame. An RxBD from queue 2 with the Interrupt (I) bit in its status 0 word was updated but was not the last BD of the frame. A frame was received in queue 0 and the last RxBD in that frame was updated. RXF0 24 RXF1 25 RXF2 26 0 Receive Frame Interrupt 0. It indicates that it is safe to write to the receive registers (status. XFUN 15 RXB0 16 RXB1 17 RXB2 18 RXB3 19 — 20–22 GRSC 23 No underrun. The transmit FIFO emptied before the complete frame was transmitted. Collision Retry Limit. 0 No graceful stop completed. Late Collision. The number of successive transmission collisions has 0 exceeded the MAC Half-Duplex Register retransmission maximum count. No insertion error. Rev. Insertion Error.MII MAC2MAC Exercise Table 6. No receive frame interrupt. An insertion error occurred during an attempt to insert data during transmission of a frame. Normal operation. This occurs only if the Interrupt (I) bit in the BD status word is set. Graceful Receive Stop Complete. This occurs only if the Interrupt (I) bit in the BD status word is set. Receive Buffer 3. and transmission of the next frame commences. An RxBD from queue 0 with the Interrupt (I) bit in its status 0 word was updated but was not the last BD of the frame. Receive Buffer 2. 0 Transmit Frame Interrupt. Transmit FIFO Underrun. 0 Receive Frame Interrupt 2. No collision. Receive Buffer 0. Generates an interrupt when a graceful receive stop is completed. A frame was received in queue 2 and the last RxBD in that frame was updated. MSC8122/26 Ethernet MII Quick Start. Receive Buffer 1. IEVENT Bit Descriptions (continued) Name TXB 10 TXF 11 IE 12 LC 13 CRL 14 Description Transmit Buffer. The frame is discarded without being transmitted. 0 Receive Frame Interrupt 1. 0 No excessive transmission collisions. Normal operation. No receive frame interrupt. control or configuration registers) in use by the system during normal operation. A frame was transmitted and the last corresponding TxBD is updated. A collision occurred beyond the collision window (slot time) in 0 Half-Duplex mode. This occurs only if the Interrupt (I) bit in the BD status word is set. This occurs only if the Interrupt (I) bit in the status word of the BD is set. 0 Freescale Semiconductor 13 .

This occurs only if the Interrupt (I) bit in the BD status word is set. Rev.0xffffffff). 0 RXCEN 1 BSYEN 2 Receive Control Interrupt Enable Busy Interrupt Enable 1 1 1 RCI enabled. Values for This Exercise No receive frame interrupt. Write to zero for future compatibility. Write to zero for future compatibility.MII MAC2MAC Exercise Table 6. EBERR enabled. Table 7. Bit Type Value Bit Type Value 0 — 1 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RXCEN BSYEN EBERREN — MSROEN GTSCEN BTEN TXCEN TXEEN TXBEN TXFEN IEEN LCEN CRLEN XFUNEN R/W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17 18 19 20 21 — 1 1 1 22 23 24 25 26 27 28 29 30 — 1 1 1 1 31 GRSCEN RXFEN0 RXFEN1 RXFEN2 RXFEN3 R/W 1 1 1 1 1 RXBEN0 RXBEN1 RXBEN2 RXBEN3 1 1 1 1 Figure 9. IMASK Bit Descriptions Bit Description Reserved. A frame was received in queue 3 and the last 0 RxBD in that frame was updated. 0 14 Freescale Semiconductor . IEVENT Bit Descriptions (continued) Name RXF3 27 — 28–31 Description Receive Frame Interrupt 3. MSC8122/26 Ethernet MII Quick Start. In connection with Interrupt Event Register. Settings EBERREN Ethernet Controller Bus Error Enable 3 — 4 MSROEN 5 GTSCEN 6 Reserved. BI enabled. Reserved. GTSCI enabled. MSTAT Register Overflow Interrupt Enable Graceful Transmit Stop Complete Interrupt Enable 1 1 MSROI enabled. the Interrupt Mask Register (IMASK) is configured as follows (see Figure 9): Write(IMASK. Write to zero for future compatibility. Interrupt Mask Register (IMASK) Table 7 describes the functions of the IMASK bits and states the values assigned to these bits for this exercise.

RFQ0I enabled. TBI enabled. 1 1 1 1 RBQ0I enabled. MSC8122/26 Ethernet MII Quick Start.MII MAC2MAC Exercise Table 7. RBQ1I enabled. TFI enabled. Transmit FIFO Underrun Enable 1 TFU enabled. TCI enabled. TEI enabled. Write to zero for future compatibility. RFQ2I enabled. Insertion Error Interrupt Enable 1 IEI enabled. Late Collision Enable 1 LC enabled. Graceful Receive Stop Complete Interrupt Enable Receive Frame Queue 0 Interrupt Enable Receive Frame Queue 1 Interrupt Enable Receive Frame Queue 2 Interrupt Enable Receive Frame Queue 3 Interrupt Enable Reserved. 1 1 1 1 1 GRSCI enabled. RBQ3I enabled. Receive Buffer Queue 0 Interrupt Enable Receive Buffer Queue 1 Interrupt Enable Receive Buffer Queue 2 Interrupt Enable Receive Buffer Queue 3 Interrupt Enable Reserved. RFQ1I enabled. 0 Freescale Semiconductor 15 . RBQ2I enabled. Collision Retry Limit Enable 1 CRL enabled. RFQ3I enabled. Write to zero for future compatibility. Rev. IMASK Bit Descriptions (continued) Bit BTEN 7 TXCEN 8 TXEEN 9 TXBEN 10 TXFEN 11 IEEN 12 LCEN 13 CRLEN 14 XFUNEN 15 RXBEN0 16 RXBEN1 17 RXBEN2 18 RXBEN3 19 — 20–22 GRSCEN 23 RXFEN0 24 RXFEN1 25 RXFEN2 26 RXFEN3 27 — 28–31 Description Babbling Transmitter Interrupt Enable Transmit Control Interrupt Enable Transmit Error Interrupt Enable Transmit Buffer Interrupt Enable Transmit Frame Interrupt Enable 1 1 1 1 1 Settings BTI enabled.

the group address registers 0–7 are configured. Write(GADDR1. Write(IADDR6. Write(IADDR2.0x0). Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 16 0 17 0 18 0 19 0 20 0 21 0 22 GADDRn R/W 0 0 23 24 GADDRn R/W 0 0 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 10.0x0). Write(IADDR7.0x0). Write(IADDR3. Write(GADDR2. the GADDR0 contains the high-order 32 bits and the GADDR7 contains the low-order 32 bits of the 256-entry hash table. Write(IADDR5. The IAADR0 contains the high-order 32 bits and the IAADR7 contains the low-order 32 bits of the 256 entry hash table. These registers are used for hash functionality and each register represents the 32-bit value associated with the corresponding register. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 R/W 8 9 10 11 12 13 14 15 IADDRn 0 16 0 17 0 18 0 19 0 20 0 21 0 22 0 23 R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 IADDRn Figure 11. 0 16 Freescale Semiconductor . For example.0x0).0x0).0x0). Write(IADDR1. all registers are initialized to their default value of 0x0 Write(IADDR0. Write(GADDR4. Write(GADDR7.0x0). These registers are used for hash functionality.0x0).MII MAC2MAC Exercise Next. all registers are initialized to their default value of 0x0. Rev.0x0). Write(GADDR3.0x0). Group Address Registers 0–7 (GADDR[0–7]) Next the individual address registers 0–7 are configured. For this exercise.0x0). For this exercise. Write(GADDR5.0x0). Individual Address Registers 0–7 (IADDR[0–7]) MSC8122/26 Ethernet MII Quick Start.0x0).0x0). Write(GADDR6.0x0).0x0). Write(IADDR4. Write(GADDR0.

When the data bit is unmasked. and PATTRBn registers are used in conjunction to configure pattern matching functionality. allowing for contiguous or non-contiguous patterns. Rev. Bit Type Reset Bit Type Reset 0 1 2 3 4 5 6 7 — R 8 9 10 11 12 13 14 15 0 16 — R 0 0 17 0 18 0 19 0 20 MI 0 21 R/W 0 22 0 23 0 24 CSE 0 25 CP 1 0 26 0 27 — R 0 28 0 29 0 30 PMC 0 31 0 0 0 0 0 0 0 1 0 0 0 0 1 0 Figure 12. Write to zero for future compatibility. There are sixteen pattern matching registers for detecting the same number of different 32-bit data patterns. PMASKn. Next the pattern mask data register 0 (PMASK0) is configured. The MI value for each 4-byte pattern is always honored (regardless of PCNTRLn[CP]). Table 8. MI as cleared corresponds to the first 4-bytes of the destination address. If a bit is masked. The pattern mask register specifies the 32-bit mask for pattern matching. The PMDn. from the 18–23 start of the receive frame (from the DA field to FCS inclusive) to perform the pattern matching. The maximum programmed value for MI is 63 (252-byte offset). Write(PMD0. in multiples of 4 bytes. all bits are unmasked to enable corresponding PDMn bits for pattern match compares. it is considered a match.0x00000000). Pattern Match Control Register 0 (PCNTRL0) Table 8 describes the functions of the PCNTRL0 bits and states the values assigned to these bits for this exercise.MII MAC2MAC Exercise Next the pattern matching registers are configured. Specifies the index. 0 Freescale Semiconductor 17 . the corresponding PMDn bit is enabled for pattern match compares (with frame data). For example. Values for This Exercise 0b000000 MI Matching Index. PCNTRLn. Next pattern match control register 0 (PCNTRL0) is configured as follows (see Figure 12): Write(PCNTRL0. PCNTRL0 Bit Descriptions Bits 0–17 Description Reserved. which represents the 32 bits of data to compare against the frame data.0x000000c2). In this example.0xffffffff). as follows: Write(PMASK0. First the pattern matching data register 0 (PMD0) is configured with the value of 0x0. MSC8122/26 Ethernet MII Quick Start. These user-programmable registers contain 32-bit data used to compare against the data of the received frames.

Rev. continue searching for other patterns up unto the 256-byte maximum. 0 18 Freescale Semiconductor . Write to zero for future compatibility. the PATTRB[QC] field is used to determine where the frame is filed. PCNTRL0 Bit Descriptions (continued) Bits CSE 24 Description Continue Search Enable. CSE is ignored (the frame is rejected and searching is discontinued). For each concatenated pattern. PCNTRL0[CP] as set means pattern 0 and pattern 1 are joined together as one pattern.MII MAC2MAC Exercise Table 8. Pattern Match Attributes Register 0 (PATTRB0) Table 9 describes the functions of the PATTRB0 bits and states the values assigned to these bits for this exercise. 26–29 PMC Pattern Match Control. Otherwise. the pattern matching should continue. Controls the filtering of frames based on pattern 10 Pattern Match Accept. Concatenated Pattern. The lowest numerical PCNTRLn register in which CP is set contains the pattern matching control and attribute information (except MI) that is used for concatenated patterns. If a pattern match reject occurs. — Reserved. PATTRB0 Field Descriptions Bits — 0–21 PMF 22 Description Reserved. CP 25 The immediate pattern that follows is concatenated to the current one. Values for This Exercise MSC8122/26 Ethernet MII Quick Start. Specifies which field is used to determine where the frame is filled. regardless. The immediate pattern registers that follow are 1 regarded as a continuation of this pattern. The frame is 30–31 matching. CP as set is always honored and PCNTRL15[CP] is always regarded as cleared. the attributes corresponding to the last matched entry are used. Table 9. Write to zero for future compatibility. 1 If a match occurs. For example. If no other matches are encountered. accepted (subject to the CSE bit). Indicates that if a match occurs on an entry in 1 which the CSE bit is set. Values for This Exercise If the pattern matched. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 — R 0 16 R 0 0 17 0 18 — R/W 0 0 R 0 R/W 0 0 1 0 0 19 0 20 0 21 0 22 PMF 0 23 — 0 24 0 25 0 26 0 27 — R 0 0 0 0 0 0 28 0 29 0 30 QC R/W 0 0 31 8 9 10 11 12 13 14 15 RDSEN RBDSEN R/W 0 0 Figure 13. all the patterns attempt to match to the first 4-bytes of the DA (if MI is left cleared). the MI field must be set to the appropriate 4-byte multiple.0x00000200). Pattern Match File. Next pattern match attribute register 0 (PATTRB0) is configured as follows (see Figure 13): Write(PATTRB0.

Write to zero for future compatibility. Pattern Match Control Register 1 (PCNTRL1) Table 11 describes the functions of the PCNTRL1 bits and states the values assigned to these bits for this exercise.MII MAC2MAC Exercise Table 9. 0 0 Disables snooping of all receive frame data to memory. 00 0 queue. 0 Freescale Semiconductor 19 .0x00000102). Reserved. Disables snooping of all receive BD memory accesses. Enables/disables snooping of all RxBD memory accesses. pattern match control register 1 (PCNTRL1) is configured as follows: Write(PCNTRL1. PATTRB0 Field Descriptions (continued) Bits — 23 RDSEN 24 RBDSEN 25 — 26–29 QC 30–31 Description Reserved. RxBD Snoop Enable. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 — R 8 9 10 11 12 13 14 15 0 16 — R 0 0 17 0 18 0 19 0 20 MI 0 21 R/W 0 22 0 23 0 24 CSE 0 25 CP 0 0 26 0 27 — R 0 28 0 29 0 30 PMC 0 31 0 0 0 0 0 0 1 0 0 0 0 0 1 0 Table 10. MSC8122/26 Ethernet MII Quick Start. Specifies the receive queue classification in which to file an incoming frame if the PATTRBn[PMF] field is set and a corresponding pattern match occurs. Values for This Exercise Similarly. Rev. Rx Data Snoop Enable. the pattern mask data register 1 (PMASK1) is configured as follows: Write(PMASK1. In the case of concatenated pattern configurations the QC used is from the first 4-byte pattern.0xffff0000). Next. the pattern matching registers are configured for the second register set. Next.0x63640000). Write to zero for future compatibility. Queue Classification. Enables/disables snooping of all receive frame data to memory. Pattern matching data register 1 (PMD1) is configured as follows: Write(PMD1.

The immediate pattern registers that follow are 0 regarded as a continuation of this pattern. MSC8122/26 Ethernet MII Quick Start. the pattern matching should continue. pattern match attribute register 1 is configured as follows (see Figure 14): Write(PATTRB1. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 — R 0 16 R 0 0 17 0 18 — R/W 0 0 R 0 R/W 0 0 1 0 0 19 0 20 0 21 0 22 PMF 0 23 — 0 24 0 25 0 26 0 27 — R 0 0 0 0 0 0 28 0 29 0 30 QC R/W 0 0 31 8 9 10 11 12 13 14 15 RDSEN RBDSEN R/W 0 0 Figure 14. For example. Indicates that if a match occurs on an entry in 0 which the CSE bit is set. accepted (subject to the CSE bit). PCNTRL1 Bit Descriptions Bits 0–17 Description Reserved. If no other matches are encountered. in multiples of 4 bytes. Values for This Exercise 000001 MI Matching Index. Pattern Match Attributes Register 1 (PATTRB1) Table 12 describes the functions of the PATTRB1 bits and states the values assigned to these bits for this exercise. For example. from the 18–23 start of the receive frame (from the DA field to FCS inclusive) to perform the pattern matching. CP 25 No pattern concatenation with the following pattern is performed. MI as cleared corresponds to the first 4-bytes of the destination address.0x00000200). — Reserved. Write to zero for future compatibility. regardless. Specifies the index. Controls the filtering of frames based on pattern 10 Pattern Match Accept. CP as set is always honored and PCNTRL15[CP] is always regarded as cleared. PCNTRL0[CP] as set means pattern 0 and pattern 1 are joined together as one pattern.MII MAC2MAC Exercise Table 11. Otherwise. If the pattern matched. 26–29 PMC Pattern Match Control. 0 20 Freescale Semiconductor . Write to zero for future compatibility. discontinue the search for all other patterns. the MI field must be set to the appropriate 4-byte multiple. all the patterns attempt to match to the first 4-bytes of the DA (if MI is left cleared). The frame is 30–31 matching. Rev. Next. allowing for contiguous or non-contiguous patterns. CSE is ignored (the frame is rejected and searching is discontinued). If a pattern match reject occurs. For each concatenated pattern. The lowest numerical PCNTRLn register in which CP is set contains the pattern matching control and attribute information (except MI) that is used for concatenated patterns. The maximum programmed value for MI is 63 (252-byte offset). CSE 24 Continue Search Enable. The MI value for each 4-byte pattern is always honored (regardless of PCNTRLn[CP]). the attributes corresponding to the last matched entry are used. Concatenated Pattern.

Enables/disables snooping of all RxBD memory accesses. 0 0 Disables snooping of all receive frame data to memory. In the case of concatenated pattern configurations the QC used is from the first 4-byte pattern. Pattern Match File. Write to zero for future compatibility. RxBD Snoop Enable. Write to zero for future compatibility. 1 If a match occurs. Values for This Exercise Next the receive control register (RCTRL) is configured for pattern matching mode by writing 0x42. Reserved. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 16 0 17 — R 0 18 0 19 0 20 CRCLSEL R/W 0 0 21 0 22 — R — R/W 0 0 23 24 0 25 PMEN R/W 1 0 26 — R 0 0 27 0 28 0 29 0 30 RA 1 0 31 — R 0 0 0 0 0 0 0 0 0 BCREJ PROM RSF R/W 0 0 0 Figure 15. Rx Data Snoop Enable. Note that promiscuous mode can be programmed by writing 0x48. 00 0 queue. Reserved. This register controls the operation of the receive block and it must be written only after system reset at initialization or when the DMACTRL[GRS] bit is cleared. The RCTRL register is configured as follows (see Figure 15): Write(RCTRL. MSC8122/26 Ethernet MII Quick Start. Queue Classification. 0 Freescale Semiconductor 21 . Receive Control Register (RCTRL) Table 13 describes the functions of the RCTRL bits and states the values assigned to these bits for this exercise. the PATTRB[QC] field is used to determine where the frame is filed. Specifies which field is used to determine where the frame is filled. Rev.0x00000042). Specifies the receive queue classification in which to file an incoming frame if the PATTRBn[PMF] field is set and a corresponding pattern match occurs. Enables/disables snooping of all receive frame data to memory. PATTRB1 Field Descriptions Bits — 0–21 PMF 22 — 23 RDSEN 24 RBDSEN 25 — 26–29 QC 30–31 Description Reserved. Write to zero for future compatibility.MII MAC2MAC Exercise Table 12. Disables snooping of all receive BD memory accesses.

Specifies whether the eight most significant bits of the 20 CRC remainder are to be used to map the destination address to the hash table entry. Rev. Reserved. 0 Use the eight most significant bits of the CRC remainder to map the DA to the hash table entry. A pattern match reject hit or the setting of RA prevents a frame from being accepted even if RCTRL[PROM] is set. When RSF=0. Write to zero for future compatibility. Broadcast Frame Reject. RCTRL Bit Descriptions Bit — 0–19 Description Reserved. are accepted unless there is a pattern match reject hit or RA is set. 0 22 Freescale Semiconductor . Next the maximum receive buffer length R0R1 Register (MRBLR0R1) is configured as follows (see Figure 16): Write(MRBLR0R1. Write to zero for future compatibility. Reject All Mode. For short frames to be received when RSF=1. 0 No effect.MII MAC2MAC Exercise Table 13. Pattern Match Enabled. Receive Short Frame Mode. No effect. Values for This Exercise CRCLSEL CRC LSB Select. Reserved. Only frames with pattern match accept hits are received. 1 RA 30 — 31 No frames accepted on the basis of a DA hit. Do not accept any frames on the basis of a DA hit. Enables the reception of frames shorter than 0 MINFLR bytes. 1 Pattern match is enabled PROM 28 RSF 29 No effect. Enables/disables pattern matching. Promiscuous Mode. Rejects frames with a destination address (DA) = 0 FFFF_FFFF_FFFF unless RCTRL[PROM] is set.0x00001200). Write to zero for future compatibility. all frames shorter than MINFLR are automatically rejected. All frames. regardless of the addresses. MSC8122/26 Ethernet MII Quick Start. a DA hit or a pattern match hit accept needs to occur. If both BCREJ and RCTRL[PROM] are set. This bit is ignored if PMEN is cleared. then frames with broadcast DA are accepted and the MISS (M) bit is set in the receive BD. Write to zero for future compatibility. — 21–24 PMEN 25 — 26 BCREJ 27 Reserved.

You write to MRBLR1 with a multiple of 64 for all modes. Therefore. Change MRBLRn only when the Ethernet controller receive function is disabled. user-supplied buffers must be at least as large as the MRBLR0. You write to MRBLR0 register with a multiple of 64 for all modes. To ensure that MRBL1 and MRBLR0 are multiples of 64. these 000000 bits are reserved and should be cleared. Table 14. Note that you can assign transmit buffers varying lengths by programming TxBD[DL] as needed. MRBLRn is not to be changed dynamically while the Ethernet controller is operating. Maximum Receive Buffer Length R0R1 Register (MRBLR0R1) Table 14 describes the functions of the MRBLR0R1 bits and states the values assigned to these bits for this exercise. Specifies the number of bytes that the Ethernet controller receiver writes to receive buffer ring 1 before moving to the next buffer. The Ethernet controller can write fewer bytes to the buffer than the value set in MRBLR0 if a condition such as an error or end-of-frame occurs. — 10–15 MRBLR0 16–25 — 26–31 MSC8122/26 Ethernet MII Quick Start. and they are not affected by the value in MRBLRn. The Ethernet controller can write fewer bytes to the buffer than the value set in MRBLR1 if a condition such as an error or end-of-frame occurs. Therefore.MII MAC2MAC Exercise Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 — R 13 14 15 MRBLR1 Type Value Bit 0 16 0 17 0 18 0 19 0 20 R/W 0 21 0 22 0 23 0 24 0 25 0 26 0 27 0 28 0 29 — R 0 30 0 31 MRBLR0 Type Value 0 0 0 1 0 R/W 0 1 0 0 0 0 0 0 0 0 0 Figure 16. Rev. To ensure that MRBLR1 and MRBLR0 are multiples of 64. 0 Freescale Semiconductor 23 . 0001 0010 00 (72 bytes) Maximum Receive Buffer Length for Ring 0. these 000000 bits are reserved and must be cleared. Specifies the number of bytes that the Ethernet controller receiver writes to receive buffer ring 0 before moving to the next buffer. MRBLR0R1 Field Descriptions Bit MRBLR1 10–9 Description Values for This Exercise 0000 0000 00 Maximum Receive Buffer Length for Ring 1. but it never exceeds the MRBLR0 value. but it never exceeds the MRBLR1 value. user-supplied buffers must be at least as large as MRBLR1.

Rev. both reads and writes of TxBDs/RxBDs have a priority set to the APR value. Always write a 0 to this bit after any reset or configuration. Sets the transmit/receive transaction priority. Always write a 0 to this bit after any reset or configuration. Polling Count.5. Disable Out-of-Sequence Buffer Descriptor 0 Out-of-Sequence buffer descriptor polling is enabled 00 512 clocks Values for This Exercise Reserved. DMAMR Field Descriptions Bit — 1–3 PCNT 4–5 — 6 DOOS 7 — 8 — 9 — 10–11 APR 12–13 Description Reserved. Table 15. Sets the transmit/receive transaction priority if the Ethernet controller is in alarm mode. Buffer Descriptor Fetches Priority prior to Alarm Mode. Alarm Mode Priority.MII MAC2MAC Exercise Next. 11 High priority BDPR 14–15 — 16–31 01 Mid priority MSC8122/26 Ethernet MII Quick Start. Always write a 0 to this bit after any reset or configuration. In alarm mode (used to help prevent potential underrun/overrun conditions). Always write a 1 to this bit after any reset or reconfiguration. Reserved. Always write a 0 to this bit after any reset or configuration. This field sets the polling frequency of the transmitter.0x004d0000). Reserved. the DMA maintenance register (DMAMR) is configured as follows (see Figure 17): Write(DMAMR. The polling frequency is proportional to the Ethernet MII clock speed (2. Bit Type Reset 0 1 — R 2 3 4 PCNT R/W 5 6 — R 0 7 8 9 — R/W 1 10 R/W 0 11 R 0 12 APR R/W 1 13 14 15 0 0 0 0 0 0 DOOS R/W R/W 0 0 1 BDPR R/W 0 1 Bit Type Value 16 17 18 19 20 21 22 23 — R 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 17. Reserved. 0 24 Freescale Semiconductor . DMA Maintenance Register (DMAMR) Table 15 describes the functions of the DMAMR bits and states the values assigned to these bits for this exercise. Always write a 0 to this bit after any reset or configuration. 25 MHz) Reserved.

Specifies whether a value of zero is automatically written to the addressed counter after a host read or whether you must explicitly write the value of zero. This bit is self-resetting. Write to zero for future compatibility. It must not be changed without proper care. The values of the internal counters are input to the MSTAT module Reserved.0x00001080). Values for This Exercise 0 Automatically Zero-Addressed Statistical Counter Values. This bit must be set must be set before the Ethernet controller is enabled. Table 16. — 25–31 MSC8122/26 Ethernet MII Quick Start. STEN 19 Statistics are enabled so that internal counters can update. Statistics Enabled. Specifies whether the BD size is 8 bytes or 32 1 bytes. Rev. ECNTRL Bit Descriptions Bit — 0–16 CLRCNT 17 AUTOZ 18 Description Reserved. User must write a value of zero to the addressed counter after a host read. Reserved. It must not be changed without proper care. This is a steady state signal and must be set before the Ethernet controller is enabled. It must not be changed without proper care. — 20–23 DBDS 24 32-byte BD format. Ethernet Control Register (ECNTRL) Table 16 describes the functions of the ECNTRL bits and states the values assigned to these bits for this exercise. The addressed counter values are input to the MSTAT module. Specifies whether statistics are enabled so that internal 1 counters can update.MII MAC2MAC Exercise Next the Ethernet control register (ECNTRL) is configured as follows (see Figure 18): Write(ECNTRL. This is a steady state signal and must be set before the Ethernet controller is enabled. Specifies whether MSTAT counters continue to increment or are all reset. Write to zero for future compatibility. 0 Freescale Semiconductor 25 . Clear All Statistics Counters. Data Buffer Descriptor Size. Write to zero for future compatibility. Bit Type Value Bit Type Value 0 1 2 3 4 5 6 7 — 8 R 9 10 11 12 13 14 15 0 16 — 0 17 0 18 R/W 0 0 19 0 20 0 21 — 0 22 R 0 23 0 24 DBDS 0 25 — 0 26 — 0 27 — 0 28 — 0 29 — 0 30 — 0 31 — CLRCNT AUTOZ STEN R 0 0 1 0 0 0 0 R/W 1 0 0 0 R 0 0 0 0 Figure 18. 0 MSTAT counters continue to increment.

Causes the Ethernet controller to stop 0 receiving frames after receiving the current frame—that is. If frame transmission is not currently underway. When GRS is cleared. the Ethernet controller scans the input data stream for the start of a new frame (preamble sequence and start of frame delimiter) and the first valid frame received uses the next RxBD. Rev. but the Ethernet controller ignores the receive data until GRS is cleared. Because the receive enable bit of the MAC may still be set.MII MAC2MAC Exercise Finally the DMA control Register is configured as follows (see Figure 19). Settings GTS 28 0 Ethernet controller resumes transmitting frames. Write(DMACTRL. the GTSC interrupt is generated immediately. Once transmission completes. MSC8122/26 Ethernet MII Quick Start. the MAC may continue to receive. — 29 0 Reserved. clearing GTS causes a “restart. Causes the Ethernet controller to stop 0 transmitting frames after transmitting the current frame. The buffer of the receive frame associated with the EOF is closed and the IEVENT[GRSC] bit is set to generate an interrupt. DMA Control Register (DMACTRL) Table 17 describes the functions of the DMACTRL bits and states the values assigned to these bits for this exercise. Write to zero for future compatibility. after a valid end of frame is received.0x00000002). Always write a 0 to this bit after any reset or configuration. and the IEVENT[GTSC] is set to generate an interrupt. Graceful Transmit Stop.” Ethernet controller stops receiving frames after processing the current frame. Graceful Receive Stop. Bit Type Reset Bit Type Reset 0 1 2 3 4 5 6 7 8 — R 0 24 R/W 9 10 11 12 13 14 15 0 16 0 17 0 18 0 19 R 0 20 0 21 — 0 22 0 23 0 25 0 26 R 0 0 27 GRS 0 28 GTS 0 0 29 — R/W 0 0 30 — 0 0 31 WOP 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19. Table 17. DMACTRL Bit Descriptions Bit — 0–26 GRS 27 Reset 0 0 Description Reserved. 0 26 Freescale Semiconductor .

Rev. which is cleared to disable MII loopback mode. Next. Also. First download and run the host (MSC8101/3) project in AN3063SW. Provides the option for the Ethernet controller to 0 poll a TxBD periodically or to wait for software to tell it to fetch a BD. • For the external loopback. To resume transmission. Poll TxBD based on the setting of DMAMR[PCNT]. Settings 4 MII MAC2MAC External Exercise As long as the MSC8122ADS board is properly set up. the Ethernet controller allows two additional reads of a descriptor that is not ready before it enters a halt state. Wait or Poll. Always write a 1 to this bit after any reset or configuration. the MAC2MAC exercise ran and completed successfully. Test mode requires the following preprocessor macro to be added into the project settings under the I/O and Preprocessors panel for both the host and slave projects. There are only two differences between the MAC2MAC external and MAC2MAC internal loopback exercises: • The register configuration for the MACCFG1 (MAC configuration register 1. everything is ready to run the MSC8122 Ethernet exercise. DMACTRL Bit Descriptions (continued) Bit — 30 WOP 31 Reset 0 0 Description Reserved. download and run the MSC8122 project. software must clear TSTAT[THLT]. all JP6 jumpers must be removed. specifically in the MIILB (bit 23). This I/O messages indicate that the test ran successfully and that the Ethernet frames were successfully exchanged. Welcome to ENET MII test . During the debug session a STDIO window appears and displays the following message. a zip file that accompanies this application note. No interrupt is driven. MSC8122/26 Ethernet MII Quick Start.Core number 1 MIIGSK_ENR=3 Check 8122 TXBDs 8122: 1000 TXBDs were updated successfully Check 8103 TXBDs 1000 Frames Were transmitted successfully From 8103 Check 8103 RXBDs 8103 : 1000 RXBDs were updated successfully Check 8122 Receive RXBDs Checking 1000 8122 RXBDs 8122 1000 RXBDs were updated successfully Check 8103 TX data to 8122 Receive Buffers ALL FRAMES FROM 8103 WERE ACCEPTED Check 8103 RX data from 8122 Transmit Buffers ALL FRAMES FROM 8122 WERE ACCEPTED.MII MAC2MAC External Exercise Table 17. DTEST_TYPE=MII_M2M_TP DTEST_SPEED=SPEED_100_MBPS This exercise with both the host and slave CodeWarrior projects is available in the directory named MII_MAC2MAC_external\projects\feth_all_tests_fulld_gpio_and_dsi directory of AN3063SW. In the “Wait” mode. 0 Freescale Semiconductor 27 .

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