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Introduction to FPGA Design

Getting Started with Xilinx FPGAs Version 2. 1i

© 1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-1
No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

Outl ine
Hier chical Des ar ign Sy nchronous Design f Xil or inxFPGAs Summar y

© 1999 Xilinx, Inc. All Right Res v s er ed

Intro to FPGA Design 6-9
No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx

ic e. inx W hy Synchronous Design? Sy nchronous circuits are m ore rel e iabl — Events are triggered by clock edges which occur at welldef ined intervals — Outputs f rom one logic stage have a f clock cycle to ull propagate to the nex stage t – Sk bet ew ween dat ariv t a r al imesist at wit t s oler ed hin he ame clockper iod Asynchronous circuits are l rel e ess iabl — A delay may need to be a specif amount ( g.Synchronous Design W hy Synchronous Design? Xil FPGA Design Tips inx © 1999 Xilinx. Inc. Inc. 12ns) — Multiple delays may need to hold a specif relationship ( g. All Right Res v s er ed Intro to FPGA Design 6-10 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. DATA arrives 5ns bef SELECT) ore © 1999 Xilinx. All Right Res v s er ed Intro to FPGA Design 6-11 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx . ic e.

inx Design Tips Xil FPGA Design inx Reduce cl ock skew Cl ock dividers Avoid gl itches on cl ocks and asynchronous set/ reset signal s The Gl obalSet/ Reset network Sel a state m achine encoding schem e ect Access carry l ogic Buil eficient counters d f © 1999 Xilinx.W hat is happening? ail — Logic pl acement has changed.W hat did Xil change in their FPGAs? inx — SRAM process improvements and geometry shrinks increase speed — Normal variations between waf l er ots My design was working. All Right Res v s er ed Intro to FPGA Design 6-12 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. All Right Res v s er ed Intro to FPGA Design 6-13 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education.but I re-routed m y FPGA and now m y design f s.the simul ation is accurate — Timing simul ation uses worstcase del ays — Actual board-evel l conditions are usual better l y © 1999 Xilinx.which af f ects internal routing del ays My design passes a back-annotated tim ing sim ul ation but f s in circuit. Inc.Is the tim ing sim ul ail ation accurate? — Yes. inx .Case Studies The design I did two y ears ago no l onger works. Inc.

Inc. All Right Res v s er ed Intro to FPGA Design 6-15 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. inx . inx Use Gl obalBufers to Reduce f Cl ock Skew Gl obalbufers are connected to dedicated routing f — This routing network is balanced to minimize skew Al Xil FPGAs have gl l inx obalbufers f Diferent types ofgl f obalbufers f — XC4000E/ and Spartan hav 4 BUFGPs and 4 BUFGSs L e — XC4000EX/ XV hav 8 BUFGLSs XL/ e — Virtexhas 4 BUFGs or BUFGDLLs You can al s use a BUFG sy boland the sof way m tware wil choose an appropriate bufer type l f — Most sy nthesis tools can inf global buf onto clock er f ers signals © 1999 Xilinx. 0 A 12. 1 D Q_A 3. Inc. D Q_B 1 3.Cl ock Skew INPUT 3. 5 This shif register wil not work because ofcl t l ock skew! 2 cy cles 3 cy cles Clock Q_A Q_B Q_C A&C Clock B Clock Expect oper ion ed at Q_A Q_B Q_C Clocks ewed v s k er ion © 1999 Xilinx. 0 B C CLOCK 3. All Right Res v s er ed Intro to FPGA Design 6-14 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. D Q_C 3 3.

inx . Inc. inx Recom m ended Cl ock Divider No cl ock skew between fip-fops l l CLK2 CE _ D Q D CE Q CLK1 BUFG © 1999 Xilinx. All Right Res v s er ed Intro to FPGA Design 6-17 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. Inc.TraditionalCl ock Divider Introduces cl ock skew between CLK1 and CLK2 Uses an extra BUFG to reduce skew on CLK2 D Q D Q CLK2 BUFG CLK1 BUFG © 1999 Xilinx. All Right Res v s er ed Intro to FPGA Design 6-16 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education.

Inc.they can respond to very narrow cl ock pul ses Never source a cl ock signalf rom com binatoriall ogic — Also known as “gating the clock” MSB 0111 0111 1111 1000 tans ion can become r it 1000 due t f t MSB o aser MSB Shorter routing FF LSB Gl h ma oc ur here itc y c Bina ry Counter © 1999 Xilinx. All Right Res v s er ed Intro to FPGA Design 6-18 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. but without gl itches on the cl ock D I NPUT D Q3 Q2 Q1 Q0 CE Q FF CLOCK Co n e u tr © 1999 Xilinx. All Right Res v s er ed Intro to FPGA Design 6-21 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education. Inc.Avoid Cl ock Gl itches Because fip-fops in today’ FPGAs are very f l l s ast. inx Avoid Cl ock Gl itches:Answer Com pl in the circuit to create the sam e f ete unction. inx .

inx Avoid Set/ Reset Gl itches Convert to synchronous set or reset when possibl e FF Sy nchronous Reset I NPUT D Q Bi a y nr Co n e u tr Q[ ] x Q[ ] 0 R RES ET CLOCK © 1999 Xilinx. Inc. Inc. All Right Res v s er ed Intro to FPGA Design 6-23 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education.Avoid Set/ Reset Gl itches Gl itches on asynchronous cl or preset inputs can ear l ead to incorrect circuit behavior FF Asy nchronous Cl ear I NPUT D Q Bi a y nr Co n e u tr Q[ ] x Q[ ] 0 CLR RES ET CLOCK © 1999 Xilinx. inx . All Right Res v s er ed Intro to FPGA Design 6-22 No part of this document may be reproduced or transmitted without the ex press written permission of the Director of Xil Customer Education.