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5.1

DIGITAL SYSTEM DESIGN

5.2

5.2 Multipliers

**§5 - MULTIPLIER CIRCUITS
**

5.2.1 Unsigned Multiplication 5.1 Introduction Unsigned multiplication can be done using serial addition as shown below: Arithmetic circuits form an important class of circuits in digital systems. In this section, we will examine simple complementers, different types of adder/subtractor circuits and their trade-off between speed and complexity, multiplier circuits and floating point circuits. Arithmetic circuits alone could form a 3rd year course on its own, therefore the treatment here will be selective (but at a reasonably detail level). However, circuits will be treated at gate levels or above, but not at transistor level. Emphasis will be placed in the techniques, algorithms and ideas, not circuit tricks. In this chapter, I assume that you known two's complement representation of numbers and the basic ideas behind binary addition and subtraction. If you have forgotten, consult 1st or 2nd year notes. Perhaps the best book on this subject is "Computer Arithmetics - Principles, Architecture and Design" by K Kwang. This book covers all the materials discussed in this section and beyond. Another recently published book in this topic is “Computer Arithmetic – Algorithms and Hardware Designs” by Behrooz Parhami. This book covers almost all aspects of computer arithmetics and circuits.

Multiplicant Multiplier zero extended

1010 0111 01010 1010 01111 1010 10001 0000 01000 01000110

Yu = y3:y2:x1:y0 Xu = x3:x2:x1:x0 x0 * Yu 2 x1 * Yu 4 x2 * Yu 8 x3 * Yu

10 7 10 20 =30 40 =70 0 =70

carry out

At each stage, starting from the LSB of the multiplier, a one-bit multiplier is perform to give a partial product. This is shifted right by one bit before adding to the next bit multiplication. Note that we need 4-bit adder at each stage, yielding 5 bit results. The carry out is used to provide the fifth bit. At each stage, the LSB of the addition becomes one bit of the answer.

XBIT y3 y2 y1 y0 & & & & Z7 Z6 Z5 Z4 3 2 1 0 A+B 3 2 1 0 B A 3 2 1 0 Z3 Z2 Z1 RESET CLOCK R C1 1D S3 S2 S1 S0 Z3 Z2 Z1 Z0 Z7 Z6 Z5 Z4

x3:x2:x1:x0

Σ

Cout

S4

Figure 5.16 4-bit Unsigned Serial-add Multiplier

pykc

pykc

4-bit Unsigned Adder 4-bit Signed Adder A3 Cout S4 A3:0 sign extension signed subtract 11010 11010110 The procedure here is similar to that for unsigned multiply except that: • • Each input to the 4-bit sign adder must be sign extended by 1 bit The last operation must be a subtraction. CLOCK pykc pykc .1 Unsigned and Signed Addition Z5 Z4 Similar to unsigned multiply.2 Signed Multiplication Before considering signed multiplication. let us first examine 4-bit signed addition. Therefore the circuit need to use a 4-bit signed adder/subtractor as shown in figure 5. CLOCK XBIT = x3. Adding two 4 bit numbers gives a 5-bit sum.DIGITAL SYSTEM DESIGN 5.2. SUBTRACT=0. not an add. For an unsigned adder. S0 becomes part of the final answer. CLOCK XBIT = x2.3 DIGITAL SYSTEM DESIGN 5. signed multiplication can be done using serial addition as shown below: Figure 5. to ensure that a 4-bit signed addition gives the correct 5 bit result. we actually need a 5-bit adder as shown in figure 5. CLOCK Answer: Z7:0 = Xu * Yu signed addition At each stage.1. Unfortunately. this bit is wrong for signed addition if the sign of the two numbers are different. SUBTRACT x3:x2:x1:x0 y3 XBIT & & & & Z7 Z6 3 2 1 0 A+B 3 2 1 0 B A 3 2 1 0 Z3 Z2 Z1 +/1 SUB RESET CLOCK Σ A3:0 4 4 3 0 Σ A Cout not used R C1 1D Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Σ 4 R4 R3 R2 R1 R0 y2 y1 y0 B3 A+B B3:0 4 4 S3:0 B3:0 4 3 B 0 A+B 5 S4:0 Figure 5.2. Therefore.2 4-bit Signed Serial-add Multiplier The operation of this circuit is: • Reset the Flip-flops • XBIT = x0. 5. The input numbers must first be sign extended to form a 5-bit signed number before the addition. CLOCK • XBIT = x1. the carry out provides the fifth bit. CLOCK XBIT = x1.4 Multiplicant The operation of this circuit is: • • • • • • Multiplier sign extended 1010 0111 00000 11010 111010 11010 110111 11010 110101 00000 Ys = y3:y2:x1:y0 Xs = x3:x2:x1:x0 x0 * Ys 2 x1 * Ys 4 x2 * Ys . most significant 4 bits S4:1 are saved and fed back to adder as Z7:4. SUBTRACT=0.8 x3 * Ys -6 7 -6 -12 = -18 -24 = -42 0 = -42 Reset the Flip-flops XBIT = x0.

It is very similar to the previous implementation. CLOCK Answer: Z7:0 = Xs * Ys ∑ 2 (−x + x i i i −1 ) =− =− ∑2 x + ∑2 x i i i i =0 i =0 N −1 N −1 i −1 5. It is initialized to 0 (with RESET). The table above shows how the Booth algorithm work: • At each stage.3. SUBTRACT=0. Booth Algorithm is one of many algorithms that group together a number of bits in the multiplier and perform a recoding of the binary bits before the actual addition/subtraction. An extra register is need to store PREVBIT.DIGITAL SYSTEM DESIGN 5.Booth Algorithm ∑2 x + ∑2 i i i =0 i =−1 N −2 i=0 N −2 i= 0 N −1 N −2 i +1 xi N −2 i =0 i +1 1010 0111 Operation Ys = y3:y2:x1:y0 Xs = x3:x2:x1:x0 Ys * ( +2Ys * ( +4Ys * ( -x0) -x1+x0) =0 -6 7 = -Ys = −2 N −1 x N −1 − = −2 N −1 x N −1 + = −2 N −1 x N −1 + ∑2 x + ∑2 i i xi + 20 x−1 0 0 00000 00110 000110 00000 000011 00000 000001 11010 ∑ ( −2 + 2 i i +1 ) xi N −2 i= 0 ∑2 x i i xi xi-1 0 1 0 1 (-xi+xi-1) 0 +1 -1 0 Comments Do nothing Add Ys Subtract Ys Do nothing -x2+x1 ) =0 0 0 1 1 + +8Ys * (-x3+x2 ) = +8Ys 11010110 Ys * (-8x3+4x2+2x1+x0 ) Instead of treating the MSB differently from all other bits.3 Booth Serial Multiplier pykc pykc .3 Recoded Multipliers . The XOR gate and the AND gates are used to implement the above coding table. it is possible to rearrange the binary bits and code them differently.6 • • • XBIT = x2.5 DIGITAL SYSTEM DESIGN N −1 i=0 5. CLOCK XBIT = x3. we add Ys * 2i * (-xi + xi-1) • • The implementation of the Booth Algorithm is shown in figure 5. but we now remove the need to treat the last cycle as special. SUBTRACT=1. XBIT x3:x2:x1:x0 PREVBIT y3 y2 y1 y0 =1 & & & & Z7 Z6 Z5 Z4 3 2 1 0 A+B 3 2 1 0 B A 3 2 1 0 Z3 Z2 Z1 XBIT SUB +/1 RESET CLOCK R C1 1D Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 PREVBIT We assume that x-1 = 0 The algorithm is defined by the following equation: Σ 4 R4 R3 R2 R1 R0 Figure 5.2.

the same as kY. : x2 : x0 Xodd = x2k-1 : . Shown in figure 5..4 is a 2-bit serial multiplier for unsigned numbers: Xeven = x2k-2 : .DIGITAL SYSTEM DESIGN 5....8 5.. We need 6 bit adder output to accommodate the answer without overflow.5 Modified Booth Algorithm We can combine the multi-bit idea with the original Booth algorithm as shown below: Booth Algorithm: bit i bit i+1 Modified Booth: bit i & i+1 i X3 X2 X1 X0 Figure 5. There are no reasons why we could not deal with two (or more) bits at a time.5 Scaling Add/Subtract Circuit 2i ( − xi + xi −1 ) 2i +1 ( − xi +1 + xi ) 2 ( − xi + xi −1 ) + 2i +1 ( − xi+1 + xi ) = 2i ( −2 xi +1 + xi + xi −1 ) xi+1 0 0 0 0 1 1 1 1 xi 0 0 1 1 0 0 1 1 xi-1 0 1 0 1 0 1 0 1 -2xi+1+xi+xi-1 Comments Therefore we need a circuit that can add/subtract either 0.k SUB SUB SUB SUB DOUBLE Y3 5 MUX G1 1 1 1 1 1 1 +/- n+1 A B Sum n+1 Carry Save Adder Cout n+1 P Carry P+Q Propage n+2 Adder Q n+1 n+1 C L A T C H DOUBLE Zn+1:0 n+2 4 Q 5 0 4 P+Q 0 P 0 R5 R4 R3 R2 R1 R0 k=2 3 Q 0 3 P 0 0 P+kQ R5 R4 R3 R2 R1 R0 Y2 Y1 Y0 0 Y3 Y2 Y1 Y0 X3 X2 X1 X0 1 1 Figure 5. Such a circuit can be implemented as shown in figure 5.4 Multi-bit Multiplier All the circuits considered so far handle only one bit multiplication at each clock cycle. Xeven Xodd Yu n+1 2*Yu n+1 & & +/.. Ys or 2*Ys. where k=1 or 2.. : x3 : x1 n = 2k where n = no of data bits • • • • The multiplex chooses either to double Y3:0 or not.4 2-bit serial multiplier 5. pykc pykc .5.7 DIGITAL SYSTEM DESIGN 5. X3:0 is sign-extended to make it 5 bits.2...2.. R5:0 = X3:0 ± k * Y3:0...

First.10 The circuit to implement the modified Booth algorithm is shown in figure 5.6 Array Multiplier pykc pykc .k Next. an array of 1-bit multipliers (AND gate) and full-adders can be used.6 Modified Booth Multiplier Circuit The functional sequence for this circuit is: • • • RESET XBIT1:0 = X1:0. let us design a 1-bit multiply cell as shown below (figure 5.9 DIGITAL SYSTEM DESIGN 5. Each cell has a full-adder and an AND gate.7). let us examine a 4x4 unsigned product:- We can derive the following equations from the above table: SUB = XBIT 1 DOUBLE = XBIT 0 ⊕ PREVBIT ZERO = ( XBIT 1 = XBIT 0 = PREVBIT ) = XBIT 1 ⊕ XBIT 0 • DOUBLE XBIT1 XBIT0 PREVBIT =1 SUB & =1 k=2 5 Y3 Y2 Y1 Y0 & & & & Z7 Z6 Z5 Z4 0 3 P 0 Q 0 3 P+kQ RESET CLOCK R5 R4 R3 R2 R1 R0 Z3 Z2 XBIT1 R C1 1D Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 PREVBIT +/. CLOCK Figure 5.6.DIGITAL SYSTEM DESIGN 5. The signal feed through shown here helps to build a multiplier as a 2-D array:d a d a b' & b b' b = A c' B C FA Co Σ c c' Σ c a' d' a' d' a' = a b' = b c' = a ⋅ b ⋅ d + a ⋅ b ⋅ c + c ⋅ d d'= (a ⋅ b ⊕ d ) ⊕ c Figure 5. factor a3 b3 a3b0 a2b1 a1b2 a0b3 p3 p2 p1 p0 P=AxB a2 b2 a2b0 a1b1 a0b2 a1 b1 a1b0 a0b1 a0 b0 a0b0 =A =B For fast multiplication.2.7 One bit Multiply Cell 5. This circuit basically implement the following function: XBIT1 0 0 0 0 1 1 1 1 XBIT0 0 0 1 1 0 0 1 1 PREVBI T 0 1 0 1 0 1 0 1 0 +1 +1 +2 -2 -1 -1 0 p7 + a3b3 p6 a3b2 a2b3 p5 a3b1 a2b2 a1b3 p4 X Mult. CLOCK XBIT1:0 = X3:2.

∆ which is much better than (3n-2)∆ (especially when n is large). Instead of propagating the carry length-wise. This array could be modified to work much faster by apply the carry-save principle. the total worst case delay of the array is 10∆.10. However. Assuming ∆ is the worst case delay per cell. For a n x n bit array. (Why? Work it out yourself!) Note also that the shaded cells are simpler . Now the worst-case delay is only 2n. the worst case delay can be shown to be (3n-2)∆.9 Carry-save 4x4 unsigned multiplier array a3 d a a2 a1 a0 b & & & & b0 Σ c' c & a' d' b1 b2 & b3 & This circuit can further be simplified (hence making it works faster) by replacing the shaded cells with simpler circuits as shown in figure 5.8 4 x 4 bit unsigned multiplier array p7 p6 p5 p4 p3 p2 p1 p0 We can map the tabulated form of the 4x4 multiplication almost directly into the 2-D array shown in figure 5. this array is slow.8. This results in a better circuit as shown in figure 5. FA FA HA p7 p6 p5 p4 p3 p2 p1 p0 Figure 5.11 DIGITAL SYSTEM DESIGN 5.DIGITAL SYSTEM DESIGN 5.12 a3 d a a2 a1 a0 d a a3 a2 a1 a0 b0 b' b b' b b0 Σ c' c Σ b1 c' c b1 a' d' a' d' b2 b2 b3 b3 p7 p6 p5 p4 p3 p2 p1 p0 HA FA FA HA Figure 5.they only need a half adder instead of a full adder circuit. b' Figure 5.10 Simplied carry-save unsigned multiplier array pykc pykc . we could feed it forward diagonally as in the carry-save adder circuit.9.

The bits with negative weighting are enclosed in parenthesis. (a3) X (b3) a2b1 + a3b3 0 (a3b2) + (p7) p6 (a2b3) p5 a2b2 (a3b1) (a1b3) p4 a1b2 (a3b0) (a0b3) p3 p2 p1 p0 P=AxB a2 b2 a2b0 a1b1 a0b2 a1 b1 a1b0 a0b1 a0 b0 a0b0 =A =B Therefore. In order to build an array for this multiplication. The lower 3 bits are multiplied as in the unsigned case. As before.11.11 One bit subtractor with borrow pykc pykc .DIGITAL SYSTEM DESIGN 5. The truth table of a subtract cell is:X 0 0 1 1 0 0 1 1 Y 0 1 0 1 0 1 0 1 Bin 0 0 0 0 1 1 1 1 D 0 1 1 0 1 0 0 1 Bout 0 1 0 0 1 1 0 1 A subtract cell can be built from a full adder cell as shown in figure 5. They are subtracted instead of added.7 2's Complement Multiplier Array To handle 2's complement signed multiplication. we need subtract cells.13 DIGITAL SYSTEM DESIGN 5.2. one of many algorithms is depicted in the table below. let us consider 4 bit numbers. X Y Bin A B Cin Σ FA S Cout D Bout D = ( x ⊕ y ) ⊕ B in B out = x ⋅ y + x ⋅ Bin + y ⋅ B in Figure 5.14 5.12 Multiplier cell with subtraction The detail arrangement of the array is left as an exercise for you. the subtract cells in the bottom two rows of the multipliers become (figure 5.12):d a d a b' & b b' + - b = A c' B C FA Co Σ c c' Σ c a' d' a' d' Figure 5. The sign bits are handled separately.

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