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April 2011 Doc ID 15081 Rev 5 1/97

1
STM32F100xC
STM32F100xD STM32F100xE
High-density value line, advanced ARM-based 32-bit MCU with
256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces
Features
■ Core: ARM 32-bit Cortex™-M3

CPU
– 24 MHz maximum frequency, 1.25 DMIPS
/MHz (Dhrystone 2.1) performance
– Single-cycle multiplication and hardware
division
■ Memories
– 256 to 512 Kbytes of Flash memory
– 24 to 32 Kbytes of SRAM
– Flexible static memory controller with 4
Chip Selects. Supports SRAM, PSRAM
and NOR memories
– LCD parallel interface, 8080/6800 modes
■ Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-24 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
■ Low power
– Sleep, Stop and Standby modes
– V
BAT
supply for RTC and backup registers
■ Serial wire debug (SWD) and JTAG I/F
■ DMA
– 12-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I
2
Cs, USARTs and DACs
■ 1 × 12-bit, 1.2 µs A/D converter (up to 16 ch.)
– Conversion range: 0 to 3.6 V
– Temperature sensor
■ 2 × 12-bit D/A converters
■ Up to 112 fast I/O ports
– 51/80/112 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
■ Up to 16 timers
– Up to seven 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– One 16-bit, 6-channel advanced-control
timer: up to 6 channels for PWM output,
dead time generation and emergency stop
– One 16-bit timer, with 2 IC/OC, 1
OCN/PWM, dead-time generation and
emergency stop
– Two 16-bit timers, each with
IC/OC/OCN/PWM, dead-time generation
and emergency stop
– Two watchdog timers
– SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
■ Up to 11 communications interfaces
– Up to two I
2
C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 UARTs
– Up to 3 SPIs (12 Mbit/s)
– Consumer electronics control (CEC) I/F
■ CRC calculation unit, 96-bit unique ID

Table 1. Device summary
Reference Part number
STM32F100xC
STM32F100RC, STM32F100VC,
STM32F100ZC
STM32F100xD
STM32F100RD, STM32F100VD,
STM32F100ZD
STM32F100xE
STM32F100RE, STM32F100VE,
STM32F100ZE
LQFP144
20 × 20 mm
LQFP100
14 × 14 mm
LQFP64
10 × 10 mm
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Contents STM32F100xC, STM32F100xD, STM32F100xE
2/97 Doc ID 15081 Rev 5
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 13
2.2.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13
2.2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14
2.2.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16
2.2.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.18 I
²
C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.19 Universal synchronous/asynchronous receiver transmitter (USART) . . 19
2.2.20 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . 19
2.2.21 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.22 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.23 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.24 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.25 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.26 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.27 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM32F100xC, STM32F100xD, STM32F100xE Contents
Doc ID 15081 Rev 5 3/97
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 39
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 67
5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.16 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Contents STM32F100xC, STM32F100xD, STM32F100xE
4/97 Doc ID 15081 Rev 5
6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93
7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
STM32F100xC, STM32F100xD, STM32F100xE List of tables
Doc ID 15081 Rev 5 5/97
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F100xx features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. High-density STM32F100xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 12. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 13. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15. STM32F100xxB maximum current consumption in Sleep mode, code
running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 43
Table 17. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 45
Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 22. HSE 4-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 23. LSE oscillator characteristics (f
LSE
= 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 24. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 27. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 29. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 56
Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 57
Table 32. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 33. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 34. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 35. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 36. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 37. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 38. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 39. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 40. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 41. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 42. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 43. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 44. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
List of tables STM32F100xC, STM32F100xD, STM32F100xE
6/97 Doc ID 15081 Rev 5
Table 45. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 46. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 47. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 48. I
2
C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 49. SCL frequency (f
PCLK1
= 24 MHz, V
DD
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 50. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 51. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 52. R
AIN
max for f
ADC
= 12 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 53. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 54. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 55. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 56. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 57. LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data . . . . . . . . . . . . . 89
Table 58. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 90
Table 59. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . . 91
Table 60. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 61. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 62. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
STM32F100xC, STM32F100xD, STM32F100xE List of figures
Doc ID 15081 Rev 5 7/97
List of figures
Figure 1. STM32F100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3. STM32F100xx value line LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. STM32F100xx value line in LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 7. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 13. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 15. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 55
Figure 16. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 57
Figure 17. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 19. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 20. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 21. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 22. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 23. Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 24. Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 25. 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 26. 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 27. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 29. I
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 30. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 31. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 32. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 33. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 34. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 35. Power supply and reference decoupling (V
REF+
not connected to V
DDA
). . . . . . . . . . . . . . 84
Figure 36. Power supply and reference decoupling (V
REF+
connected to V
DDA
). . . . . . . . . . . . . . . . . 84
Figure 37. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 38. LQFP144, 20 x 20 mm, 144-pin thin quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 39. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 40. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 90
Figure 41. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 42. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 91
Figure 43. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 44. LQFP100 P
D
max vs. T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Introduction STM32F100xC, STM32F100xD, STM32F100xE
8/97 Doc ID 15081 Rev 5
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F100xC, STM32F100xD and STM32F100xE value line microcontrollers. In the
rest of the document, the STM32F100xC, STM32F100xD and STM32F100xE are referred
to as high-density value line devices.
This STM32F100xC, STM32F100xD and STM32F100xE datasheet should be read in
conjunction with the STM32F100xx high-density ARM-based 32-bit MCUs reference manual
(RM0059). For information on programming, erasing and protection of the internal Flash
memory please refer to the STM32F100xx high-density value line Flash programming
manual (PM0072). The reference and Flash programming manuals are both available from
the STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.


STM32F100xC, STM32F100xD, STM32F100xE Description
Doc ID 15081 Rev 5 9/97
2 Description
The STM32F100xx value line family incorporates the high-performance ARM Cortex™-M3
32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash
memory up to 512 Kbytes and SRAM up to 32 Kbytes), a flexible static memory control
(FSMC) interface (for devices offered in packages of 100 pins and more) and an extensive
range of enhanced peripherals and I/Os connected to two APB buses. All devices offer
standard communication interfaces (up to two I
2
Cs, three SPIs, one HDMI CEC, up to three
USARTs and 2 UARTS), one 12-bit ADC, two 12-bit DACs, up to 9 general-purpose 16-bit
timers and an advanced-control PWM timer.
The STM32F100xx high-density value line family operates in the –40 to +85 °C and –40 to
+105 °C temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving mode allows the design of low-power applications.
The STM32F100xx value line family includes devices in three different packages ranging
from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are
included, the description below gives an overview of the complete range of peripherals
proposed in this family.
These features make the STM32F100xx value line microcontroller family suitable for a wide
range of applications such as motor drives, application control, medical and handheld
equipment, PC and gaming peripherals, GPS platforms, industrial applications, PLCs,
inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Description STM32F100xC, STM32F100xD, STM32F100xE
10/97 Doc ID 15081 Rev 5
2.1 Device overview

Table 2. STM32F100xx features and peripheral counts
Peripheral STM32F100Rx STM32F100Vx STM32F100Zx
Flash - Kbytes 256 384 512 256 384 512 256 384 512
SRAM - Kbytes 24 32 32 24 32 32 24 32 32
FSMC No Yes
(1)
Yes
Timers
Advanced-control 1 1 1
General-purpose 10 10 10
Communication
interfaces
SPI 3 3 3
I
2
C 2 2 2
USART 3 3 3
UART 2 2 2
CEC 1 1 1
12-bit synchronized ADC
number of channels
1
16 channels
1
16 channels
1
16 channels
GPIOs 51 80 112
12-bit DAC
Number of channels
2
2
2
2
2
2
CPU frequency 24 MHz
Operating voltage 2.0 to 3.6 V
Operating temperatures
Ambient operating temperature: –40 to +85 °C /–40 to +105 °C
Junction temperature: –40 to +125 °C
Packages LQFP64 LQFP100 LQFP144
1. For the LQFP100 package, only FSMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory.
STM32F100xC, STM32F100xD, STM32F100xE Description
Doc ID 15081 Rev 5 11/97
Figure 1. STM32F100xx value line block diagram
1. AF = alternate function on I/O port pin.
2. T
A
= –40 °C to +85 °C (junction temperature up to 105 °C) or T
A
= –40 °C to +105 °C (junction temperature up to 125 °C).
PA[15:0]
EXT.I T
WWDG
12-bit ADC1
16 ADC channels
(ADC_INx)
JTDI
JTCK/SWCLK
JTMS/SWDIO
NJTRST
JTDO
NRST
V
DD
= 2.0 V to 3.6 V
80 AF
PB[15:0]
PC[15:0]
AHB2
WKUP
GPIO port A
GPIO port B
GPIO port C
F
max
: 24 MHz
V
SS
V
REF+
GP DMA
TIM2
TIM3
XTAL OSC
4-24 MHz
XTAL 32 kHz
OSC_IN
OSC_OUT
OSC32_OUT
OSC32_IN
A
P
B
1
:

F
m
a
x

=

2
4

M
H
z
HCLK
PCLK1
Flash 512 KB
Voltage reg.
3.3 V to 1.8 V
V
DD18
Power
Backup interface
as AF
TIM4
32 bit
RTC
AWU
RC HS
Cortex-M3 CPU
Ibus
Dbus
o
b
l
USART1
USART2
SPI2
12 channels
Backup
register
TIM15
I2C1
RX,TX, CTS, RTS,
USART3
Temp sensor
PD[15:0] GPIO port D
PE[15:0]
GPIO port E
FCLK
RC LS
Standby
IWDG
@VDD33
@V
BAT
POR / PDR
Supply
supervision

@VDDA
VDDA
VSSA
@VDDA
V
BAT
= 1.8 V to 3.6 V .
CK as AF
RX, TX, CTS, RTS, CK
as AF
RX,TX, CTS, RTS,
CK as AF
SPI1
IF
interface
@VDDA
PVD
Reset
Int
@VDD
AHB2
APB2 APB1
POR
TAMPER-RTC
System
TIM16
Reset &
clock
control

PCLK2
PLL
12-bit DAC1
IF
12-bit DAC2
@VDDA
DAC1_OUT as AF
DAC2_OUT as AF
SRAM
32 KB
TIM6
TIM7
(ALARM OUT)
NVIC
TRACECLK
TRACED[0:3]
as AF
TIM17
JTAG & SW pbus
Trace
controller
A
H
B

:

F
m
a
x
=
I2C2
HDMI CEC HDMI CEC as AF
4 channels
as AF
4 channels
as AF
4 channels
as AF
MOSI, MISO,
SCK, NSS as AF
MOSI, MISO, SCK, NSS
as AF
V
REF–
2 channels, 1 compl. channel
and BKIN as AF
F
l
a
s
h
i
n
t
e
r
f
a
c
e
B
u
s

m
a
t
r
i
x
SCL, SDA, SMBA as AF
SCL, SDA, SMBA as AF
ai17515b
TIM1
4 channels, 3 compl. channels,
ETR and BKIN as AF
2
4

M
H
z
1 channel, 1 compl. channel
and BKIN as AF
1 channel, 1 compl. channel
and BKIN as AF
TIM12
TIM13
TIM14
2 channels
as AF
1 channel
as AF
1 channel
as AF
TIM5
4 channels
as AF
UART4
RX,TX, CTS, RTS,
CK as AF
UART5
RX,TX, CTS, R
CK as AF
SPI3
MOSI, MISO,
SCK, NSS as AF
A
P
B
2
:

F
m
a
x

=

2
4

M
H
z
FSMC
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[3:0]
NBL[1:0]
NWAIT
NADV
as AF
GPIO port F
GPIO port G
PF[15:0]
PG[15:0]
Description STM32F100xC, STM32F100xD, STM32F100xE
12/97 Doc ID 15081 Rev 5
Figure 2. Clock tree
1. To obtain an ADC conversion time of 1.2 µs, APB2 must be at 24 MHz.
HSE OSC
4-24 MHz
OSC_ÌN
OSC_OUT
OSC32_ÌN
OSC32_OUT
LSE OSC
32.768 kHz
HSÌ RC
8 MHz
LSÌ RC
40 kHz
to independent watchdog (ÌWDG)
PLL
x2, x3, x4
PLLMUL
HSE = High-speed external clock signal
LSE = Low -speed external clock signal
LSÌ = Low-speed internal clock signal
HSÌ = High-speed internal clock signal
Legend:
MCO
cloc k out put
Main
..., x16
AHB
Prescaler
/1, 2..512
/2 PLLCLK
HSÌ
HSE
APB1
Prescaler
/1, 2, 4, 8, 16
ADC
Prescaler
/2, 4, 6, 8
ADCCLK 12 MHz max
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
to ADC1
LSE
LSÌ
HSÌ
/128
/2
HSÌ
HSE
peripherals
to APB1
Peripheral Clock
Enable
Enable
Peripheral Clock
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
TÌM1/15/16/17 timers
to TÌM1, TÌM15,
TÌM16 and TÌM17
peripherals to APB2
Peripheral Clock
Enable
Enable
Peripheral Clock
24 MHz max
24 MHz
24 MHz max
24 MHz max
to RTC
PLLSRC
SW
MCO
CSS
to Cortex System timer /8
Clock
Enable
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TÌMxCLK
TÌMxCLK
ÌWDGCLK
SYSCLK
FCLK Cortex
free running clock
ai18302
Ìf (APB1 prescaler =1) x1
else x2
Ìf (APB2 prescaler =1) x1
else x2
PREDÌV1
/1/2/3.../
.../15/16
Enable
FSMCLK
to FSMC Peripheral clock
TÌM2,3,4,5,6,7,12,13,14
to TÌM2,3,4,5,6,7,12,13,14
to Flash programming interface
FLÌTFCLK
STM32F100xC, STM32F100xD, STM32F100xE Description
Doc ID 15081 Rev 5 13/97
2.2 Overview
2.2.1 ARM
®
Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F100xx value line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
2.2.2 Embedded Flash memory
Up to 512 Kbytes of embedded Flash memory is available for storing programs and data.
2.2.3 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.2.4 Embedded SRAM
Up to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.2.5 FSMC (flexible static memory controller)
The FSMC is embedded in the high-density value line family. It has four Chip Select outputs
supporting the following modes: SRAM, PSRAM, and NOR.
Functionality overview:
● The three FSMC interrupt lines are ORed in order to be connected to the NVIC
● No read FIFO
● Code execution from external memory
● No boot capability
● The targeted frequency is HCLK/2, so external access is at 12 MHz when HCLK is at
24 MHz
2.2.6 LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
Description STM32F100xC, STM32F100xD, STM32F100xE
14/97 Doc ID 15081 Rev 5
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high-
performance solutions using external controllers with dedicated acceleration.
2.2.7 Nested vectored interrupt controller (NVIC)
The STM32F100xx value line embeds a nested vectored interrupt controller able to handle
up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3)
and 16 priority levels.
● Closely coupled NVIC gives low latency interrupt processing
● Interrupt entry vector table address passed directly to the core
● Closely coupled NVIC core interface
● Allows early processing of interrupts
● Processing of late arriving higher priority interrupts
● Support for tail-chaining
● Processor state automatically saved
● Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.2.8 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 18 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected
to the 16 external interrupt lines.
2.2.9 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-24 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 24 MHz.
2.2.10 Boot modes
At startup, boot pins are used to select one of three boot options:
● Boot from user Flash
● Boot from system memory
● Boot from embedded SRAM
STM32F100xC, STM32F100xD, STM32F100xE Description
Doc ID 15081 Rev 5 15/97
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.2.11 Power supply schemes
● V
DD
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through V
DD
pins.
● V
SSA
, V
DDA
= 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to V
DDA
is 2.4 V when the ADC or DAC is
used).
V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
● V
BAT
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when V
DD
is not present.
2.2.12 Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
DD
is below a specified threshold, V
POR/PDR
, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold. An interrupt can be
generated when V
DD
/V
DDA
drops below the V
PVD
threshold and/or when V
DD
/V
DDA
is higher
than the V
PVD
threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.2.13 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
● MR is used in the nominal regulation mode (Run)
● LPR is used in the Stop mode
● Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.2.14 Low-power modes
The STM32F100xx value line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
● Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
● Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
Description STM32F100xC, STM32F100xD, STM32F100xE
16/97 Doc ID 15081 Rev 5
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
● Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
2.2.15 DMA
The flexible 12-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The two DMA controllers
support circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, DAC, I
2
C, USART, all timers and
ADC.
2.2.16 RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
DD
supply when present or through the V
BAT
pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when V
DD
power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.2.17 Timers and watchdogs
The STM32F100xx devices include an advanced-control timer, nine general-purpose timers,
two basic timers and two watchdog timers.
Table 3 compares the features of the advanced-control, general-purpose and basic timers.
STM32F100xC, STM32F100xD, STM32F100xE Description
Doc ID 15081 Rev 5 17/97

Warning: Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for:
● Input capture
● Output compare
● PWM generation (edge or center-aligned modes)
● One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard TIM timers which have the same
architecture. The advanced control timer can therefore work together with the TIM timers via
the Timer Link feature for synchronization or event chaining.
Table 3. Timer feature comparison
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Capture/compare
channels
Complementary
outputs
TIM1 16-bit
Up,
down,
up/down
16 bits Yes 4 Yes
TIM2,
TIM3,
TIM4,
TIM5
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes 4 No
TIM12 16-bit Up
Any integer
between 1
and 65536
No 2 No
TIM13,
TIM14
16-bit Up
Any integer
between 1
and 65536
No 1 No
TIM15 16-bit Up
Any integer
between 1
and 65536
Yes 2 Yes
TIM16,
TIM17
16-bit Up
Any integer
between 1
and 65536
Yes 1 Yes
TIM6,
TIM7
16-bit Up
Any integer
between 1
and 65536
Yes 0 No
Description STM32F100xC, STM32F100xD, STM32F100xE
18/97 Doc ID 15081 Rev 5
General-purpose timers (TIM2..5, TIM12..17)
There are ten synchronizable general-purpose timers embedded in the STM32F100xx
devices (see Table 3 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3, TIM4, TIM5
STM32F100xx devices feature four synchronizable 4-channel general-purpose timers.
These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
They feature 4 independent channels each for input capture/output compare, PWM or one-
pulse mode output. This gives up to 12 input captures/output compares/PWMs on the
largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM1
advanced-control timer via the Timer Link feature for synchronization or event chaining.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM12 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
Their counters can be frozen in debug mode.
TIM15, TIM16 and TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate with
TIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16, and TIM17 have a complementary output with dead-time generation and
independent DMA request generation
Their counters can be frozen in debug mode.
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
STM32F100xC, STM32F100xD, STM32F100xE Description
Doc ID 15081 Rev 5 19/97
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
● A 24-bit down counter
● Autoreload capability
● Maskable system interrupt generation when the counter reaches 0.
● Programmable clock source
2.2.18 I
²
C bus
The I²C bus interface can operate in multimaster and slave modes. It can support standard
and fast modes.
It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.
A hardware CRC generation/verification is embedded.
The interface can be served by DMA and it supports SM Bus 2.0/PM Bus.
2.2.19 Universal synchronous/asynchronous receiver transmitter (USART)
The STM32F100xx value line embeds three universal synchronous/asynchronous receiver
transmitters (USART1, USART2 and USART3).
The available USART interfaces communicate at up to 3 Mbit/s. They provide hardware
management of the CTS and RTS signals, they support IrDA SIR ENDEC, the
multiprocessor communication mode, the single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
2.2.20 Universal asynchronous receiver transmitter (UART)
The STM32F100xx value line embeds 2 universal asynchronous receiver transmitters
(UART4, and UART5).
The available UART interfaces support IrDA SIR ENDEC, the multiprocessor communication
mode, the single-wire half-duplex communication mode and have LIN Master/Slave
capability.
The UART interfaces can be served by the DMA controller.
Description STM32F100xC, STM32F100xD, STM32F100xE
20/97 Doc ID 15081 Rev 5
2.2.21 Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 12 Mbit/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits.
The SPIs can be served by the DMA controller.
HDMI (high-definition multimedia interface) consumer
electronics control (CEC)
The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware
support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI
standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead.
2.2.22 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
2.2.23 Remap capability
This feature allows the use of a maximum number of peripherals in a given application.
Indeed, alternate functions are available not only on the default pins but also on other
specific pins onto which they are remappable. This has the advantage of making board
design and port usage much more flexible.
For details refer to Table 4: High-density STM32F100xx pin definitions; it shows the list of
remappable alternate functions and the pins onto which they can be remapped. See the
STM32F100xx reference manual for software considerations.
2.2.24 ADC (analog-to-digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
STM32F100xC, STM32F100xD, STM32F100xE Description
Doc ID 15081 Rev 5 21/97
2.2.25 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in noninverting configuration.
This dual digital Interface supports the following features:
● two DAC converters: one for each output channel
● up to 10-bit output
● left or right data alignment in 12-bit mode
● synchronized update capability
● noise-wave generation
● triangular-wave generation
● dual DAC channels’ independent or simultaneous conversions
● DMA capability for each channel
● external triggers for conversion
● input voltage reference V
REF+
Eight DAC trigger inputs are used in the STM32F100xx. The DAC channels are triggered
through the timer update outputs that are also connected to different DMA channels.
2.2.26 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < V
DDA
< 3.6 V. The temperature sensor is internally
connected to the ADC1_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.2.27 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE
22/97 Doc ID 15081 Rev 5
3 Pinouts and pin descriptions
Figure 3. STM32F100xx value line LQFP144 pinout
V
D
D
_
3
V
S
S
_
3
P
E
1
P
E
0
P
B
9
P
B
8
B
O
O
T
0
P
B
7
P
B
6
P
B
5
P
B
4
P
B
3
P
G
1
5
V
D
D
_
1
1
V
S
S
_
1
1
P
G
1
4
P
G
1
3
P
G
1
2
P
G
1
1
P
G
1
0
P
G
9
P
D
7
P
D
6
V
D
D
_
1
0
V
S
S
_
1
0
P
D
5
P
D
4
P
D
3
P
D
2
P
D
1
P
D
0
P
C
1
2
P
C
1
1
P
C
1
0
P
A
1
5
P
A
1
4
PE2
V
DD_2
PE3
V
SS_2
PE4
NC
PE5
PA13
PE6
PA12
VBAT
PA11
PC13-TAMPER-RTC
PA10
PC14-OSC32_IN
PA9
PC15-OSC32_OUT
PA8
PF0
PC9
PF1
PC8
PF2
PC7
PF3
PC6
PF4
V
DD_9
PF5
V
SS_9
V
SS_5 PG8
V
DD_5 PG7
PF6
PG6
PF7
PG5
PF8
PG4
PF9
PG3
PF10
PG2
OSC_IN
PD15
OSC_OUT
PD14
NRST
V
DD_8
PC0
V
SS_8
PC1
PD13
PC2
PD12
PC3
PD11
V
SSA PD10
V
REF- PD9
V
REF+ PD8
V
DDA PB15
PA0-WKUP
PB14
PA1
PB13
PA2
PB12
P
A
3
V
S
S
_
4
V
D
D
_
4
P
A
4
P
A
5
P
A
6
P
A
7
P
C
4
P
C
5
P
B
0
P
B
1
P
B
2
P
F
1
1
P
F
1
2
V
S
S
_
6
V
D
D
_
6
P
F
1
3
P
F
1
4
P
F
1
5
P
G
0
P
G
1
P
E
7
P
E
8
P
E
9
V
S
S
_
7
V
D
D
_
7
P
E
1
0
P
E
1
1
P
E
1
2
P
E
1
3
P
E
1
4
P
E
1
5
P
B
1
0
P
B
1
1
V
S
S
_
1
V
D
D
_
1
1
4
4
1
4
3
1
4
2
1
4
1
1
4
0
1
3
9
1
3
8
1
3
7
1
3
6
1
3
5
1
3
4
1
3
3
1
3
2
1
3
1
1
3
0
1
2
9
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
0
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
7
2
LQFP144
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
26
27
28
29
30
31
32
33
34
35
36
83
82
81
80
79
78
77
76
75
74
73
ai14667
STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions
Doc ID 15081 Rev 5 23/97
Figure 4. STM32F100xx value line LQFP100 pinout
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
8
0
7
9
7
8
7
7
7
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
P
A
3
V
S
S
_
4
V
D
D
_
4
P
A
4
P
A
5
P
A
6
P
A
7
P
C
4
P
C
5
P
B
0
P
B
1
P
B
2
P
E
7
P
E
8
P
E
9
P
E
1
0
P
E
1
1
P
E
1
2
P
E
1
3
P
E
1
4
P
E
1
5
P
B
1
0
P
B
1
1
V
S
S
_
1
V
D
D
_
1
V
D
D
_
3


V
S
S
_
3


P
E
1


P
E
0


P
B
9


P
B
8


B
O
O
T
0


P
B
7


P
B
6


P
B
5


P
B
4


P
B
3


P
D
7


P
D
6


P
D
5


P
D
4


P
D
3


P
D
2


P
D
1


P
D
0


P
C
1
2


P
C
1
1


P
C
1
0


P
A
1
5


P
A
1
4

2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA0-WKUP
PA1
PA2
ai14391
LQFP100
Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE
24/97 Doc ID 15081 Rev 5
Figure 5. STM32F100xx value line in LQFP64 pinout
Table 4. High-density STM32F100xx pin definitions
Pins
Pin name
T
y
p
e
(
1
)
I

/

O

L
e
v
e
l
(
2
)
Main
function
(3)

(after reset)
Alternate functions
(4)
L
Q
F
P
1
4
4
L
Q
F
P
1
0
0
L
Q
F
P
6
4
Default Remap
1 1 - PE2 I/O FT PE2 TRACECK/ FSMC_A23
2 2 - PE3 I/O FT PE3 TRACED0/FSMC_A19
3 3 - PE4 I/O FT PE4 TRACED1/FSMC_A20
4 4 - PE5 I/O FT PE5 TRACED2/FSMC_A21
5 5 - PE6 I/O FT PE6 TRACED3/FSMC_A22
6 6 1 V
BAT
S V
BAT
7 7 2
PC13-TAMPER-
RTC
(5)
I/O PC13
(6)
TAMPER-RTC
8 8 3
PC14-
OSC32_IN
(5)
I/O PC14
(6)
OSC32_IN
9 9 4
PC15-
OSC32_OUT
(5)
I/O PC15
(6)
OSC32_OUT
10 - - PF0 I/O FT PF0 FSMC_A0
11 - - PF1 I/O FT PF1 FSMC_A1
12 - - PF2 I/O FT PF2 FSMC_A2
13 - - PF3 I/O FT PF3 FSMC_A3
14 - - PF4 I/O FT PF4 FSMC_A4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
V
D
D
_
3


V
S
S
_
3


P
B
9


P
B
8


B
O
O
T
0


P
B
7


P
B
6


P
B
5


P
B
4


P
B
3


P
D
2


P
C
1
2


P
C
1
1


P
C
1
0


P
A
1
5


P
A
1
4

VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
P
A
3
V
S
S
_
4
V
D
D
_
4
P
A
4
P
A
5
P
A
6
P
A
7
P
C
4
P
C
5
P
B
0
P
B
1
P
B
2
P
B
1
0
P
B
1
1
V
S
S
_
1
V
D
D
_
1
LQFP64
ai14392
STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions
Doc ID 15081 Rev 5 25/97
15 - - PF5 I/O FT PF5 FSMC_A5
16 10 - V
SS_5
S V
SS_5
17 11 - V
DD_5
S V
DD_5
18 - - PF6 I/O PF6 FSMC_NIORD
19 - - PF7 I/O PF7 FSMC_NREG
20 - - PF8 I/O PF8 FSMC_NIOWR
21 - - PF9 I/O PF9 FSMC_CD
22 - - PF10 I/O PF10 FSMC_INTR
23 12 5 OSC_IN I OSC_IN
24 13 6 OSC_OUT O OSC_OUT
25 14 7 NRST I/O NRST
26 15 8 PC0 I/O PC0 ADC1_IN10
27 16 9 PC1 I/O PC1 ADC1_IN11
28 17 10 PC2 I/O PC2 ADC1_IN12
29 18 11 PC3 I/O PC3 ADC1_IN13
30 19 12 V
SSA
S V
SSA
31 20 - V
REF-
S V
REF-
32 21 - V
REF+
S V
REF+
33 22 13 V
DDA
S V
DDA
34 23 14 PA0-WKUP I/O PA0
WKUP/USART2_CTS
(7)
ADC1_IN0
TIM2_CH1_ETR
TIM5_CH1
35 24 15 PA1 I/O PA1
USART2_RTS
(7)
ADC1_IN1/
TIM5_CH2/TIM2_CH2
(7)
36 25 16 PA2 I/O PA2
USART2_TX
(7)
/TIM5_CH3
ADC1_IN2/ TIM15_CH1
TIM2_CH3
(7)
37 26 17 PA3 I/O PA3
USART2_RX
(7)
/TIM5_CH4
ADC1_IN3/TIM2_CH4
(7)
/
TIM15_CH2
38 27 18 V
SS_4
S V
SS_4
39 28 19 V
DD_4
S V
DD_4
Table 4. High-density STM32F100xx pin definitions (continued)
Pins
Pin name
T
y
p
e
(
1
)
I

/

O

L
e
v
e
l
(
2
)
Main
function
(3)

(after reset)
Alternate functions
(4)
L
Q
F
P
1
4
4
L
Q
F
P
1
0
0
L
Q
F
P
6
4
Default Remap
Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE
26/97 Doc ID 15081 Rev 5
40 29 20 PA4 I/O PA4
SPI1_NSS
(7)
/
USART2_CK
(7)

DAC_OUT1/ADC1_IN4
41 30 21 PA5 I/O PA5
SPI1_SCK
(7)
DAC_OUT2/ADC2_IN5
42 31 22 PA6 I/O PA6
SPI1_MISO
(7)
/
ADC1_IN6 /
TIM3_CH1
(7)

TIM1_BKIN /
TIM16_CH1
43 32 23 PA7 I/O PA7
SPI1_MOSI
(7)
/
ADC1_IN7 /
TIM3_CH2
(7)

TIM1_CH1N/
TIM17_CH1
44 33 24 PC4 I/O PC4 ADC1_IN14 / TIM12_CH1
45 34 25 PC5 I/O PC5 ADC1_IN15 / TIM12_CH2
46 35 26 PB0 I/O PB0
ADC1_IN8/TIM3_CH3 TIM1_CH2N /
TIM13_CH1
47 36 27 PB1 I/O PB1 ADC1_IN9/TIM3_CH4
(7)
TIM1_CH3N /
TIM14_CH1
48 37 28 PB2 I/O FT PB2/BOOT1
49 - - PF11 I/O FT PF11
50 - - PF12 I/O FT PF12 FSMC_A6
51 - - V
SS_6
S V
SS_6
52 - - V
DD_6
S V
DD_6
53 - - PF13 I/O FT PF13 FSMC_A7
54 - - PF14 I/O FT PF14 FSMC_A8
55 - - PF15 I/O FT PF15 FSMC_A9
56 - - PG0 I/O FT PG0 FSMC_A10
57 - - PG1 I/O FT PG1 FSMC_A11
58 38 - PE7 I/O FT PE7 FSMC_D4 TIM1_ETR
59 39 - PE8 I/O FT PE8 FSMC_D5 TIM1_CH1N
60 40 - PE9 I/O FT PE9 FSMC_D6 TIM1_CH1
61 - - V
SS_7
S V
SS_7
62 - - V
DD_7
S V
DD_7
63 41 - PE10 I/O FT PE10 FSMC_D7 TIM1_CH2N
64 42 - PE11 I/O FT PE11 FSMC_D8 TIM1_CH2
65 43 - PE12 I/O FT PE12 FSMC_D9 TIM1_CH3N
66 44 - PE13 I/O FT PE13 FSMC_D10 TIM1_CH3
Table 4. High-density STM32F100xx pin definitions (continued)
Pins
Pin name
T
y
p
e
(
1
)
I

/

O

L
e
v
e
l
(
2
)
Main
function
(3)

(after reset)
Alternate functions
(4)
L
Q
F
P
1
4
4
L
Q
F
P
1
0
0
L
Q
F
P
6
4
Default Remap
STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions
Doc ID 15081 Rev 5 27/97
67 45 - PE14 I/O FT PE14 FSMC_D11 TIM1_CH4
68 46 - PE15 I/O FT PE15 FSMC_D12 TIM1_BKIN
69 47 29 PB10 I/O FT PB10 I2C2_SCL/USART3_TX
(7)
TIM2_CH3 /
HDMI_CEC
70 48 30 PB11 I/O FT PB11 I2C2_SDA/USART3_RX
(7)
TIM2_CH4
71 49 31 V
SS_1
S V
SS_1
72 50 32 V
DD_1
S V
DD_1
73 51 33 PB12 I/O FT PB12
SPI2_NSS/
I2C2_SMBA/
USART3_CK
(7)
/
TIM1_BKIN
(7)
TIM12_CH1
74 52 34 PB13 I/O FT PB13
SPI2_SCK/
USART3_CTS
(7)
/
TIM1_CH1N
TIM12_CH2
75 53 35 PB14 I/O FT PB14
SPI2_MISO/TIM1_CH2N
USART3_RTS
(7)
/
TIM15_CH1
76 54 36 PB15 I/O FT PB15
SPI2_MOSI/
TIM1_CH3N
(7)
/
TIM15_CH2
77 55 - PD8 I/O FT PD8 FSMC_D13 USART3_TX
78 56 - PD9 I/O FT PD9 FSMC_D14 USART3_RX
79 57 - PD10 I/O FT PD10 FSMC_D15 USART3_CK
80 58 - PD11 I/O FT PD11 FSMC_A16 USART3_CTS
81 59 - PD12 I/O FT PD12 FSMC_A17
TIM4_CH1 /
USART3_RTS
82 60 - PD13 I/O FT PD13 FSMC_A18 TIM4_CH2
83 - - V
SS_8
S V
SS_8
84 - - V
DD_8
S V
DD_8
85 61 - PD14 I/O FT PD14 FSMC_D0 TIM4_CH3
86 62 - PD15 I/O FT PD15 FSMC_D1 TIM4_CH4
87 - - PG2 I/O FT PG2 FSMC_A12
88 - - PG3 I/O FT PG3 FSMC_A13
89 - - PG4 I/O FT PG4 FSMC_A14
90 - - PG5 I/O FT PG5 FSMC_A15
91 - - PG6 I/O FT PG6
92 - - PG7 I/O FT PG7
93 - - PG8 I/O FT PG8
Table 4. High-density STM32F100xx pin definitions (continued)
Pins
Pin name
T
y
p
e
(
1
)
I

/

O

L
e
v
e
l
(
2
)
Main
function
(3)

(after reset)
Alternate functions
(4)
L
Q
F
P
1
4
4
L
Q
F
P
1
0
0
L
Q
F
P
6
4
Default Remap
Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE
28/97 Doc ID 15081 Rev 5
94 - - V
SS_9
S V
SS_9
95 - - V
DD_9
S V
DD_9
96 63 37 PC6 I/O FT PC6 TIM3_CH1
97 64 38 PC7 I/O FT PC7 TIM3_CH2
98 65 39 PC8 I/O FT PC8 TIM13_CH1 TIM3_CH3
99 66 40 PC9 I/O FT PC9 TIM14_CH1 TIM3_CH4
100 67 41 PA8 I/O FT PA8
USART1_CK/
TIM1_CH1
(7)
/MCO
101 68 42 PA9 I/O FT PA9
USART1_TX
(7)
/
TIM1_CH2
(7)
/
TIM15_BKIN
102 69 43 PA10 I/O FT PA10
USART1_RX
(7)
/
TIM1_CH3
(7)
/
TIM17_BKIN
103 70 44 PA11 I/O FT PA11
USART1_CTS /
TIM1_CH4
(7)

104 71 45 PA12 I/O FT PA12
USART1_RTS /
TIM1_ETR
(7)
105 72 46 PA13 I/O FT
JTMS-
SWDIO
106 73 - Not connected
107 74 47 V
SS_2
S V
SS_2
108 75 48 V
DD_2
S V
DD_2
109 76 49 PA14 I/O FT
JTCK-
SWCLK
110 77 50 PA15 I/O FT JTDI SPI3_NSS
TIM2_CH1_ETR /
SPI1_NSS
111 78 51 PC10 I/O FT PC10 UART4_TX USART3_TX
112 79 52 PC11 I/O FT PC11 UART4_RX USART3_RX
113 80 53 PC12 I/O FT PC12 UART5_TX USART3_CK
114 81 5 PD0 I/O FT OSC_IN
(8)
FSMC_D2
(9)
115 82 6 PD1 I/O FT OSC_OUT
(8)
FSMC_D3
(9)
116 83 54 PD2 I/O FT PD2 TIM3_ETR/UART5_RX
117 84 - PD3 I/O FT PD3 FSMC_CLK USART2_CTS
118 85 - PD4 I/O FT PD4 FSMC_NOE USART2_RTS
119 86 - PD5 I/O FT PD5 FSMC_NWE USART2_TX
Table 4. High-density STM32F100xx pin definitions (continued)
Pins
Pin name
T
y
p
e
(
1
)
I

/

O

L
e
v
e
l
(
2
)
Main
function
(3)

(after reset)
Alternate functions
(4)
L
Q
F
P
1
4
4
L
Q
F
P
1
0
0
L
Q
F
P
6
4
Default Remap
STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions
Doc ID 15081 Rev 5 29/97
120 - - V
SS_10
S V
SS_10
121 - - V
DD_10
S V
DD_10
122 87 - PD6 I/O FT PD6 FSMC_NWAIT USART2_RX
123 88 - PD7 I/O FT PD7 FSMC_NE1 USART2_CK
124 - - PG9 I/O FT PG9 FSMC_NE2
125 - - PG10 I/O FT PG10 FSMC_NE3
126 - - PG11 I/O FT PG11
127 - - PG12 I/O FT PG12 FSMC_NE4
128 - - PG13 I/O FT PG13 FSMC_A24
129 - - PG14 I/O FT PG14 FSMC_A25
130 - - V
SS_11
S V
SS_11
131 - - V
DD_11
S V
DD_11
132 - - PG15 I/O FT PG15
133 89 55 PB3/ I/O FT JTDO SPI3_SCK
PB3/TRACESWO
TIM2_CH2 /
SPI1_SCK
134 90 56 PB4 I/O FT NJTRST SPI3_MISO
TIM3_CH1
SPI1_MISO
135 91 57 PB5 I/O PB5
I2C1_SMBA/ SPI3_MOSI
TIM16_BKIN
TIM3_CH2 /
SPI1_MOSI
136 92 58 PB6 I/O FT PB6
I2C1_SCL
(7)
/ TIM4_CH1
(7)

/ TIM16_CH1N
USART1_TX
137 93 59 PB7 I/O FT PB7
I2C1_SDA
(7)
/
FSMC_NADV /
TIM4_CH2
(7)
/
TIM17_CH1N
USART1_RX
138 94 60 BOOT0 I BOOT0
139 95 61 PB8 I/O FT PB8
TIM4_CH3
(7)
/TIM16_CH1 /
HDMI_CEC
I2C1_SCL/
CAN_RX
140 96 62 PB9 I/O FT PB9 TIM4_CH4
(7)
/ TIM17_CH1
I2C1_SDA /
CAN_TX
141 97 - PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0
142 98 - PE1 I/O FT PE1 FSMC_NBL1
143 99 63 V
SS_3
S V
SS_3
144 100 64 V
DD_3
S V
DD_3
1. I = input, O = output, S = supply.
Table 4. High-density STM32F100xx pin definitions (continued)
Pins
Pin name
T
y
p
e
(
1
)
I

/

O

L
e
v
e
l
(
2
)
Main
function
(3)

(after reset)
Alternate functions
(4)
L
Q
F
P
1
4
4
L
Q
F
P
1
0
0
L
Q
F
P
6
4
Default Remap
Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE
30/97 Doc ID 15081 Rev 5
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one
peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC
peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited
amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not
exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to
drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup
registers even after reset (because these registers are not reset by the main reset). For details on how to
manage these IOs, refer to the Battery backup domain and BKP register description sections in the
STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.
7. This alternate function can be remapped by software to some other port pins (if available on the used
package). For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F100xx reference manual, available from the STMicroelectronics website: www.st.com.
8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset,
however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100
and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For
more details, refer to Alternate function I/O and debug configuration section in the STM32F100xx
reference manual.
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
Table 5. FSMC pin definition
Pins
FSMC
LQFP100
(1)
NOR/PSRAM/SRAM NOR/PSRAM Mux
PE2 A23 A23 Yes
PE3 A19 A19 Yes
PE4 A20 A20 Yes
PE5 A21 A21 Yes
PE6 A22 A22 Yes
PF0 A0 -
PF1 A1 -
PF2 A2 -
PF3 A3 -
PF4 A4 -
PF5 A5 -
PF6 -
PF7 -
PF8 -
PF9 -
PF10 -
PF11 -
PF12 A6 -
PF13 A7 -
STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions
Doc ID 15081 Rev 5 31/97
PF14 A8 -
PF15 A9 -
PG0 A10 -
PG1 A11 -
PE7 D4 DA4 Yes
PE8 D5 DA5 Yes
PE9 D6 DA6 Yes
PE10 D7 DA7 Yes
PE11 D8 DA8 Yes
PE12 D9 DA9 Yes
PE13 D10 DA10 Yes
PE14 D11 DA11 Yes
PE15 D12 DA12 Yes
PD8 D13 DA13 Yes
PD9 D14 DA14 Yes
PD10 D15 DA15 Yes
PD11 A16 A16 Yes
PD12 A17 A17 Yes
PD13 A18 A18 Yes
PD14 D0 DA0 Yes
PD15 D1 DA1 Yes
PG2 A12 -
PG3 A13 -
PG4 A14 -
PG5 A15 -
PG6 -
PG7 -
PD0 D2 DA2 Yes
PD1 D3 DA3 Yes
PD3 CLK CLK Yes
PD4 NOE NOE Yes
PD5 NWE NWE Yes
PD6 NWAIT NWAIT Yes
Table 5. FSMC pin definition (continued)
Pins
FSMC
LQFP100
(1)
NOR/PSRAM/SRAM NOR/PSRAM Mux
Memory mapping STM32F100xC, STM32F100xD, STM32F100xE
32/97 Doc ID 15081 Rev 5
4 Memory mapping
The memory map is shown in Figure 6.
PD7 NE1 NE1 Yes
PG9 NE2 NE2 -
PG10 NE3 NE3 -
PG11 -
PG12 NE4 NE4 -
PG13 A24 A24 -
PG14 A25 A25 -
PB7 NADV NADV Yes
PE0 NBL0 NBL0 Yes
PE1 NBL1 NBL1 Yes
1. Ports F and G are not available in devices delivered in 100-pin packages.
Table 5. FSMC pin definition (continued)
Pins
FSMC
LQFP100
(1)
NOR/PSRAM/SRAM NOR/PSRAM Mux
STM32F100xC, STM32F100xD, STM32F100xE
Doc ID 15081 Rev 5 33/97
Figure 6. Memory map
APB memory space
DMA1
RTC
WWDG
IWDG
SPI2
USART2
USART3

ADC1
USART1

SPI1
EXTI
RCC

0
1
2
3
4
5
6
7
Peripherals
SRAM
reserved
reserved
Option Bytes
Reserved
0x4000 0000
0x4000 0400
0x4000 0800
0x4000 0C00
0x4000 2800
0x4000 2C00
0x4000 3000
0x4000 3400
0x4000 3800
0x4000 3C00
0x4000 4400
0x4000 4800
0x4000 4C00
0x4000 5400
0x4000 5800
0x4000 6C00
0x4000 7000
0x4000 7400
0x4001 0000
0x4001 0400
0x4001 0800
0x4001 0C00
0x4001 1000
0x4001 1400
0x4001 1800
0x4001 2400
0x4001 2800
0x4001 2C00
0x4001 3000
0x4001 3400
0x4001 3800
0x4001 3C00
0x4002 0000
0x4002 0400
0x4002 1000
0x4002 1400
0x4002 2000
0x4002 2400
0x4002 3000
0x4002 3400
0xFFFF FFFF
reserved
CRC
reserved
reserved
Flash interface
DMA2
reserved
reserved
TIM1
reserved
Port F
DAC
Port D
Port C
Port B
Port A
AFIO
PWR
BKP
I2C2
I2C1
reserved
TIM4
TIM3
TIM2
0xFFFF FFFF
0xE010 0000
0xE000 0000
0xC000 0000
0xA000 0000
0x8000 0000
0x6000 0000
0x4000 0000
0x2000 0000
0x0000 0000
0x1FFF FFFF
0x1FFF F80F
0x1FFF F800
0x1FFF F000
0x0801 FFFF
0x0800 0000
System memory
Flash memory
Cortex-M3 internal
peripherals
ai18400
0x0000 0000
Aliased to Flash or
system memory
depending on
BOOT pins
UART4
Port E
0x4001 1C00
0x4001 4C00
0x4001 4800
0x4001 4400
0x4001 4000
reserved
TIM17
TIM16
TIM15
0x4000 7C00
0x4000 7800
CEC
reserved
reserved
0x4000 5C00
TIM6
TIM7
TIM12
0x4000 1000
0x4000 1400
0x4000 1800
Port G
0x4001 2000
0x4000 5000
UART5
SPI3
TIM13
TIM14
0x4000 1C00
0x4000 2000
FSMC
external
memory
0x7000 0000
FSMC regs
TIM5
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
34/97 Doc ID 15081 Rev 5
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to V
SS
.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A
= 25 °C and T
A
= T
A
max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
5.1.2 Typical values
Unless otherwise specified, typical data are based on T
A
= 25 °C, V
DD
= 3.3 V (for the
2 V ≤ V
DD
≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 35/97

5.1.6 Power supply scheme
Figure 9. Power supply scheme
Caution: In Figure 9, the 4.7 µF capacitor must be connected to V
DD3
.
Figure 7. Pin loading conditions Figure 8. Pin input voltage
ai14123b
C = 50 pF
STM32F10xxx pin
ai14124b
STM32F10xxx pin
V
IN
ai14125e
V
DD
1/2/3/4/5
Analog:
RCs, PLL,
...
Power swi tch
V
BAT
GP I/Os
OUT
IN
Kernel logic
(CPU,
Digital
& Memories)
Backup circuitry
(OSC32K,RTC,
Backup registers)
Wake-up logic
5 × 100 nF
+ 1 × 4.7 μF
1.8-3.6V
Regulator
V
SS
1/2/3/4/5
V
DDA
V
REF+
V
REF-
V
SSA
ADC/DAC
L
e
v
e
l

s
h
i
f
t
e
r
IO
Logic
V
DD
10 nF
+ 1 μF
V
REF
10 nF
+ 1 μF
V
DD
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
36/97 Doc ID 15081 Rev 5
5.1.7 Current consumption measurement
Figure 10. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics,
Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.

ai14126
V
BAT
V
DD
V
DDA
I
DD
_V
BAT
I
DD
Table 6. Voltage characteristics
Symbol Ratings Min Max Unit
V
DD
− V
SS
External main supply voltage (including
V
DDA
and V
DD
)
(1)
1. All main power (V
DD
, V
DDA
) and ground (V
SS
, V
SSA
) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
V
IN
(2)
2. V
IN
maximum must always be respected. Refer to Table 7: Current characteristics for the maximum
allowed injected current values.
Input voltage on five volt tolerant pin V
SS
− 0.3 V
DD
+ 4.0
Input voltage on any other pin V
SS
− 0.3 4.0
|ΔV
DDx
| Variations between different V
DD
power pins 50
mV
|V
SSX
− V
SS
|
Variations between all the different ground
pins
50
V
ESD(HBM)
Electrostatic discharge voltage (human body
model)
see Section 5.3.12: Absolute
maximum ratings (electrical
sensitivity)
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 37/97


5.3 Operating conditions
5.3.1 General operating conditions

Table 7. Current characteristics
Symbol Ratings Max. Unit
I
VDD
Total current into V
DD
/V
DDA
power lines (source)
(1)
1. All main power (V
DD
, V
DDA
) and ground (V
SS
, V
SSA
) pins must always be connected to the external power
supply, in the permitted range.
150
mA
I
VSS
Total current out of V
SS
ground lines (sink)
(1)
150
I
IO
Output current sunk by any I/O and control pin 25
Output current source by any I/Os and control pin −25
I
INJ(PIN)
(2)
2. Negative injection disturbs the analog performance of the device. See Note: on page 82.
Injected current on five volt tolerant pins
(3)
3. Positive injection is not possible on these I/Os. A negative injection is induced by V
IN
<V
SS
. I
INJ(PIN)
must
never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage
values.
+5 / –0
Injected current on any other pin
(4)
4. A positive injection is induced by V
IN
>V
DD
while a negative injection is induced by V
IN
<V
SS
. I
INJ(PIN)
must
never be exceeded. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage
values.
± 5
ΣI
INJ(PIN)
Total injected current (sum of all I/O and control pins)
(5)
5. When several inputs are submitted to a current injection, the maximum ΣI
INJ(PIN)
is the absolute sum of the
positive and negative injected currents (instantaneous values).
± 25
Table 8. Thermal characteristics
Symbol Ratings Value Unit
T
STG
Storage temperature range –65 to +150 °C
T
J
Maximum junction temperature 150 °C
Table 9. General operating conditions
Symbol Parameter Conditions Min Max Unit
f
HCLK
Internal AHB clock frequency 0 24
MHz f
PCLK1
Internal APB1 clock frequency 0 24
f
PCLK2
Internal APB2 clock frequency 0 24
V
DD
Standard operating voltage 2 3.6 V
V
DDA
(1)
Analog operating voltage
(ADC not used)
Must be the same potential
as V
DD
2 3.6
V
Analog operating voltage
(ADC used)
2.4 3.6
V
BAT
Backup operating voltage 1.8 3.6 V
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
38/97 Doc ID 15081 Rev 5
5.3.2 Operating conditions at power-up / power-down
Subject to general operating conditions for T
A
.
Table 10. Operating conditions at power-up / power-down
P
D
Power dissipation at T
A
=
85 °C for suffix 6 or T
A
=
105 °C for suffix 7
(2)
LQFP144 TBD
mW LQFP100 TBD
LQFP64 TBD
TA
Ambient temperature for 6
suffix version
Maximum power dissipation –40 85
°C
Low power dissipation
(3)
–40 105
Ambient temperature for 7
suffix version
Maximum power dissipation –40 105
°C
Low power dissipation
(3)
–40 125
TJ Junction temperature range
6 suffix version –40 105
°C
7 suffix version –40 125
1. When the ADC is used, refer to Table 51: ADC characteristics.
2. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
J
max (see Section 6.2:
Thermal characteristics on page 92).
3. In low power dissipation state, T
A
can be extended to this range as long as T
J
does not exceed T
J
max (see
Section 6.2: Thermal characteristics on page 92).
Table 9. General operating conditions (continued)
Symbol Parameter Conditions Min Max Unit
Symbol Parameter Min Max Unit
t
VDD
V
DD
rise time rate 0 ∞
µs/V
V
DD
fall time rate 20 ∞
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 39/97
5.3.3 Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under the ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.
.
Table 11. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
PVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V
PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
V
PVDhyst
(2)
PVD hysteresis 100 mV
V
POR/PDR
Power on/power down
reset threshold
Falling edge
1.8
(1)
1. The product behavior is guaranteed by design down to the minimum V
POR/PDR
value.
1.88 1.96 V
Rising edge 1.84 1.92 2.0 V
V
PDRhyst
(2)
PDR hysteresis 40 mV
t
RSTTEMPO
(2)
2. Guaranteed by design, not tested in production.
Reset temporization 1.5 2.5 4.5 ms
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
40/97 Doc ID 15081 Rev 5
5.3.4 Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under the ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.

5.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
● All peripherals are disabled except if it is explicitly mentioned
● Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
● When the peripherals are enabled f
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
The parameters given in Table 13 are derived from tests performed under the ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.
Table 12. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
V
REFINT
Internal reference voltage
–40 °C < T
A
< +105 °C 1.16 1.20 1.26 V
–40 °C < T
A
< +85 °C 1.16 1.20 1.24 V
T
S_vrefint
(1)
1. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when
reading the internal
reference voltage
5.1
17.1
(2)
2. Guaranteed by design, not tested in production.
µs
V
RERINT
(2)
Internal reference voltage
spread over the temperature
range
V
DD
= 3 V ±10 mV 10 mV
T
Coeff
(2)
Temperature coefficient 100 ppm/°C
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 41/97


Table 13. Maximum current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions f
HCLK
Max
(1)
1. Based on characterization, not tested in production.
Unit
T
A
= 85 °C T
A
= 105 °C
I
DD
Supply
current in
Run mode
External clock
(2)
, all
peripherals enabled
2. External clock or HSI frequency is 8 MHz and PLL is on when f
HCLK
> 8 MHz.
24 MHz 19.7 20
mA
16 MHz 14.6 14.7
8 MHz 8.2 8.6
External clock
(2)
, all
peripherals disabled
24 MHz 11.3 11.6
16 MHz 8.7 8.9
8 MHz 5.6 6
HSI clock
(2)
, all peripherals
enabled
24 MHz 19 19
16 MHz 13.1 13.2
8 MHz 10.1 10.1
HSI clock
(2)
, all peripherals
disabled
24 MHz 9.4 9.6
16 MHz 6.7 7
8 MHz 5.4 5.6
Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM
Symbol Parameter Conditions f
HCLK
Max
(1)
1. Based on characterization, tested in production at V
DD
max, f
HCLK
max.
Unit
T
A
= 85 °C T
A
= 105 °C
I
DD
Supply current
in Run mode
External clock
(2)
, all
peripherals enabled
2. External clock or HSI frequency is 8 MHz and PLL is on when f
HCLK
> 8 MHz.
24 MHz 18.5 19
mA
16 MHz 13.1 13.5
8 MHz 7.3 7.6
External clock
(2)
all
peripherals disabled
24 MHz 8.4 8.5
16 MHz 7.3 7.7
8 MHz 4.8 5.2
HSI clock
(2)
, all
peripherals enabled
24 MHz 17.2 17.2
16 MHz 11.7 11.8
8 MHz 8.9 9
HSI clock
(2)
, all
peripherals disabled
24 MHz 8.1 8.3
16 MHz 5.6 5.8
8 MHz 4.3 4.5
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
42/97 Doc ID 15081 Rev 5

Table 15. STM32F100xxB maximum current consumption in Sleep mode, code
running from Flash or RAM
Symbol Parameter Conditions f
HCLK
Max
(1)
1. Based on characterization, tested in production at V
DD
max and f
HCLK
max with peripherals enabled.
Unit
T
A
= 85 °C T
A
= 105 °C
I
DD
Supply current
in Sleep mode
External clock
(2)
all
peripherals enabled
2. External clock or HSI frequency is 8 MHz and PLL is on when f
HCLK
> 8 MHz.
24 MHz 14.1 14.3
mA
16 MHz 9.7 10.3
8 MHz 5.9 6.2
External clock
(2)
, all
peripherals disabled
24 MHz 4.2 4.6
16 MHz 3.7 4.1
8 MHz 2.9 3.4
HSI clock
(2)
, all
peripherals enabled
24 MHz 12.5 12.7
16 MHz 8.2 8.5
8 MHz 6.4 6.6
HSI clock
(2)
, all
peripherals disabled
24 MHz 2.3 2.5
16 MHz 1.7 2
8 MHz 1.4 1.7
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 43/97

Typical current consumption
The MCU is placed under the following conditions:
● All I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
● All peripherals are disabled except if it is explicitly mentioned
● When the peripherals are enabled f
PCLK1
= f
HCLK
/4, f
PCLK2
= f
HCLK
/2, f
ADCCLK
=
f
PCLK2
/4
The parameters given in Table 17 are derived from tests performed under the ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.
Table 16. Typical and maximum current consumptions in Stop and Standby modes
Symbol Parameter Conditions
Typ
(1)
Max
Unit
V
DD
/V
BAT
= 2.0 V
V
DD
/ V
BAT
= 2.4 V
V
DD
/V
BAT
= 3.3 V
T
A
=
85 °C
T
A
=
105 °C
I
DD
Supply current
in Stop mode
Regulator in Run mode,
Low-speed and high-speed
internal RC oscillators and high-
speed oscillator OFF (no
independent watchdog)
31 320 670
µA
Regulator in Low-Power mode,
Low-speed and high-speed
internal RC oscillators and high-
speed oscillator OFF (no
independent watchdog)
24 305 650
Supply current
in Standby
mode
Low-speed internal RC oscillator
and independent watchdog ON
3.2
Low-speed internal RC oscillator
ON, independent watchdog OFF
3.1
Low-speed internal RC oscillator
and independent watchdog OFF,
low-speed oscillator and RTC
OFF
2.2 3.9 5.7
I
DD_VBAT
Backup
domain supply
current
Low-speed oscillator and RTC
ON
1.0 1.2 1.4 2 2.3
1. Typical values are measured at T
A
= 25 °C.
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
44/97 Doc ID 15081 Rev 5

Table 17. Typical current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions f
HCLK
Typical values
(1)
1. Typical values are measures at T
A
= 25 °C, V
DD
= 3.3 V.
Unit
All peripherals
enabled
(2)
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
I
DD
Supply
current in
Run mode
Running on high-speed
external clock with an
8 MHz crystal
(3)
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when f
HCLK
< 8 MHz, the PLL is used when f
HCLK
> 8 MHz.
24 MHz 14.1 9.5
mA
16 MHz 10 6.85
8 MHz 5.8 4.05
4 MHz 3.6 2.65
2 MHz 2.3 1.85
1 MHz 1.7 1.46
500 kHz 1.4 1.3
125 kHz 1.15 1.1
Running on high-speed
internal RC (HSI)
24 MHz 13.4 8.7
16 MHz 9.3 6.2
8 MHz 5.2 3.45
4 MHz 2.95 2.1
2 MHz 1.7 1.3
1 MHz 1.1 0.9
500 kHz 0.8 0.7
125 kHz 0.6 0.55
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 45/97

Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM
Symbol Parameter Conditions f
HCLK
Typical values
(1)
1. Typical values are measures at T
A
= 25 °C, V
DD
= 3.3 V.
Unit
All peripherals
enabled
(2)
2. Add an additional power consumption of 0.8 mA for the ADC and of 0.5 mA for the DAC analog part. In
applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
I
DD
Supply
current in
Sleep
mode
Running on high-speed
external clock with an
8 MHz crystal
(3)
3. An 8 MHz crystal is used as the external clock source. The AHB prescaler is used to reduce the frequency
when f
HCLK
> 8 MHz, the PLL is used when f
HCLK
> 8 MHz.
24 MHz 8.7 2.75
mA
16 MHz 6.1 2.1
8 MHz 3.3 1.3
4 MHz 2.25 1.2
2 MHz 1.65 1.15
1 MHz 1.35 1.1
500 kHz 1.2 1.07
125 kHz 1.1 1.05
Running on high-speed
internal RC (HSI)
24 MHz 8 2.15
16 MHz 5.5 1.5
8 MHz 2.7 0.75
4 MHz 1.65 0.6
2 MHz 1.1 0.55
1 MHz 0.8 0.5
500 kHz 0.65 0.49
125 kHz 0.53 0.47
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
46/97 Doc ID 15081 Rev 5
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed
under the following conditions:
● all I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
● all peripherals are disabled unless otherwise mentioned
● the given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
● ambient operating temperature and V
DD
supply voltage conditions summarized in
Table 6.

Table 19. Peripheral current consumption
Peripheral Typical consumption at 25 °C
(1)
Unit
APB1
TIM2 0.48
mA
TIM3 0.49
TIM4 0.48
TIM5 0.48
TIM6 0.2
TIM7 0.2
TIM12 0.32
TIM13 0.25
TIM14 0.25
DAC 1.06
(2)
WWDG 0.15
SPI2 0.2
SPI3 0.19
USART2 0.36
USART3 0.36
UART4 0.35
UART5 0.36
I2C1 0.34
I2C2 0.34
HDMI CEC 0.2
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 47/97
5.3.6 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 9.

APB2
GPIO A 0.26
mA
GPIO B 0.26
GPIO C 0.26
GPIO D 0.26
GPIO E 0.26
GPIO F 0.24
GPIO G 0.25
ADC1
(3)
1.28
SPI1 0.2
USART1 0.37
TIM1 0.63
TIM15 0.43
TIM16 0.34
TIM17 0.34
1. f
HCLK
= f
APB1
= f
APB2
= 24 MHz, default prescaler value for each peripheral.
2. Specific conditions for DAC: EN1 bit in DAC_CR register set to 1.
3. Specific conditions for ADC: f
HCLK
= 24 MHz, f
APB1
= f
APB2
= f
HCLK
, f
ADCCLK
= f
APB2
/2, ADON bit in the
ADC_CR2 register is set to 1.
Table 19. Peripheral current consumption (continued)
Peripheral Typical consumption at 25 °C
(1)
Unit
Table 20. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
HSE_ext
User external clock source
frequency
(1)
1 8 24 MHz
V
HSEH
OSC_IN input pin high level
voltage
(1)
0.7V
DD
V
DD
V
V
HSEL
OSC_IN input pin low level
voltage
(1)
V
SS
0.3V
DD
t
w(HSE)
t
w(HSE)
OSC_IN high or low time
(1)
5
ns
t
r(HSE)
t
f(HSE)
OSC_IN rise or fall time
(1)
20
C
in(HSE)
OSC_IN input capacitance
(1)
5 pF
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
48/97 Doc ID 15081 Rev 5
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed
external clock source, and under the ambient temperature and supply voltage conditions
summarized in Table 9.

DuCy
(HSE)
Duty cycle
(1)
45 55 %
I
L
OSC_IN Input leakage current V
SS
≤ V
IN
≤ V
DD
±1 µA
1. Guaranteed by design, not tested in production.
Table 21. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
LSE_ext
User external clock source
frequency
(1)
1. Guaranteed by design, not tested in production.
32.768 1000 kHz
V
LSEH
OSC32_IN input pin high level
voltage
(1)
0.7V
DD
V
DD
V
V
LSEL
OSC32_IN input pin low level
voltage
(1)
V
SS
0.3V
DD
t
w(LSE)
t
w(LSE)
OSC32_IN high or low time
(1)
450
ns
t
r(LSE)
t
f(LSE)
OSC32_IN rise or fall time
(1)
50
C
in(LSE)
OSC32_IN input capacitance
(1)
5 pF
DuCy
(LSE)
Duty cycle
(1)
30 70 %
I
L
OSC32_IN Input leakage current V
SS
≤ V
IN
≤ V
DD
±1 µA
Table 20. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 49/97
Figure 11. High-speed external clock source AC timing diagram
Figure 12. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 22. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
ai14127b
OSC_IN
External
STM32F10xxx
clock source
V
HSEH
t
f(HSE)
t
W(HSE)
I
L
90%
10%
T
HSE
t
t
r(HSE)
t
W(HSE)
f
HSE_ext
V
HSEL
ai14140c
OSC32_IN
External
STM32F10xxx
clock source
V
LSEH
t
f(LSE)
t
W(LSE)
I
L
90%
10%
T
LSE
t
t
r(LSE)
t
W(LSE)
f
LSE_ext
V
LSEL
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
50/97 Doc ID 15081 Rev 5

Figure 13. Typical application with an 8 MHz crystal
1. R
EXT
value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Table 23. In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 22. HSE 4-24 MHz oscillator characteristics
(1)(2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
f
OSC_IN
Oscillator frequency 4 8 24 MHz
R
F
Feedback resistor 200 kΩ
C
L1
C
L2
(3)
3. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. C
L1
and C
L2,
are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of C
L1
and C
L2
. PCB and MCU pin capacitance must be
included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
C
L1
and C
L2
.
Recommended load capacitance
versus equivalent serial
resistance of the crystal (R
S
)
(4)
4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
R
S
= 30 Ω 30 pF
i
2
HSE driving current
V
DD
= 3.3 V
V
IN
= V
SS
with 30 pF
load
1 mA
g
m
Oscillator transconductance Startup 25 mA/V
t
SU(HSE)
(5)
5. t
SU(HSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time V
DD
is stabilized 2 ms
ai14128b
OSC_OUT
OSC_IN
f
HSE
C
L1
R
F
STM32F10xxx
8 MHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
R
EXT
(1)

C
L2
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 51/97
Note: For C
L1
and C
L2
it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. C
L1
and C
L2,
are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of C
L1
and C
L2
.
Load capacitance C
L
has the following formula: C
L
= C
L1
x C
L2
/ (C
L1
+ C
L2
) + C
stray
where
C
stray
is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of C
L1
and C
L2
(15 pF) it is strongly recommended
to use a resonator with a load capacitance C
L
≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of C
L
= 6 pF, and C
stray
= 2 pF,
then C
L1
= C
L2
= 8 pF.

Table 23. LSE oscillator characteristics (f
LSE
= 32.768 kHz)
(1)
Symbol Parameter Conditions Min Typ Max Unit
R
F
Feedback resistor 5 MΩ
C
L1
C
L2
(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (R
S
)
(3)
R
S
= 30 KΩ 15 pF
I
2
LSE driving current
V
DD
= 3.3 V
V
IN
= V
SS
1.4 µA
g
m
Oscillator transconductance 5 µA/V
t
SU(LSE)
(4)
Startup time
V
DD
is
stabilized
T
A
= 50 °C 1.5
s
T
A
= 25 °C 2.5
T
A
= 10 °C 4
T
A
= 0 °C 6
T
A
= -10 °C 10
T
A
= -20 °C 17
T
A
= -30 °C 32
T
A
= -40 °C 60
1. Based on characterization, not tested in production.
2. Refer to the note and caution paragraphs above the table.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R
S
value for
example MSIV-TIN32.768 kHz. Refer to crystal manufacturer for more details
4. t
SU(LSE)
is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
52/97 Doc ID 15081 Rev 5
Figure 14. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under the ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.
High-speed internal (HSI) RC oscillator

Low-speed internal (LSI) RC oscillator

ai14129b
OSC32_OUT
OSC32_IN
f
LSE
C
L1
R
F
STM32F10xxx
32.768 KHz
resonator
Resonator with
integrated capacitors
Bias
controlled
gain
C
L2
Table 24. HSI oscillator characteristics
(1)
1. V
DD
= 3.3 V, T
A
= –40 to 105 °C °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
HSI
Frequency 8 MHz
ACC
HSI
Accuracy of HSI oscillator
T
A
= –40 to 105 °C
(2)
2. Based on characterization, not tested in production.
-2.4 2.5 %
T
A
= –10 to 85 °C
(2)
-2.2 1.3 %
T
A
= 0 to 70 °C
(2)
-1.9 1.3 %
T
A
= 25 °C -1 1 %
t
su(HSI)
(3)
3. Guaranteed by design. Not tested in production
HSI oscillator startup time 1 2 µs
I
DD(HSI)
(3)
HSI oscillator power consumption 80 100 µA
Table 25. LSI oscillator characteristics
(1)
1. V
DD
= 3 V, T
A
= –40 to 105 °C °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
f
LSI
Frequency 30 40 60 kHz
t
su(LSI)
(2)
2. Guaranteed by design, not tested in production.
LSI oscillator startup time 85 µs
I
DD(LSI)
(2)
LSI oscillator power consumption 0.65 1.2 µA
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 53/97
Wakeup time from low-power mode
The wakeup times given in Table 26 are measured on a wakeup phase with an 8-MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
● Stop or Standby mode: the clock source is the RC oscillator
● Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under the ambient temperature and V
DD
supply
voltage conditions summarized in Table 9.

5.3.8 PLL characteristics
The parameters given in Table 27 are derived from tests performed under the ambient
temperature and V
DD
supply voltage conditions summarized in Table 9.

Table 26. Low-power mode wakeup timings
Symbol Parameter Typ Unit
t
WUSLEEP
(1)
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
Wakeup from Sleep mode 1.8 µs
t
WUSTOP
(1)
Wakeup from Stop mode (regulator in run mode) 3.6
µs
Wakeup from Stop mode (regulator in low-power mode) 5.4
t
WUSTDBY
(1)
Wakeup from Standby mode 50 µs
Table 27. PLL characteristics
Symbol Parameter
Value
Unit
Min
(1)
Typ Max
(1)
1. Based on device characterization, not tested in production.
f
PLL_IN
PLL input clock
(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by f
PLL_OUT
.
1 8.0 24 MHz
PLL input clock duty cycle 40 60 %
f
PLL_OUT
PLL multiplier output clock 16 24 MHz
t
LOCK
PLL lock time 200 µs
Jitter Cycle-to-cycle jitter 300 ps
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
54/97 Doc ID 15081 Rev 5
5.3.9 Memory characteristics
Flash memory
The characteristics are given at T
A
= –40 to 105 °C unless otherwise specified.


5.3.10 FSMC characteristics
Asynchronous waveforms and timings
Figure 15 through Figure 18 represent asynchronous waveforms and Table 30 through
Table 33 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
● AddressSetupTime = 0
● AddressHoldTime = 1
● DataSetupTime = 1
Table 28. Flash memory characteristics
Symbol Parameter Conditions Min
(1)
1. Guaranteed by design, not tested in production.
Typ Max
(1)
Unit
t
prog
16-bit programming time T
A
= –40 to +105 °C 40 52.5 70 µs
t
ERASE
Page (2 KB) erase time T
A
= –40 to +105 °C 20 40 ms
t
ME
Mass erase time T
A
= –40 to +105 °C 20 40 ms
I
DD
Supply current
Read mode
f
HCLK
= 24 MHz, V
DD
= 3.3 V
20 mA
Write / Erase modes
f
HCLK
= 24 MHz, V
DD
= 3.3 V
5 mA
Power-down mode / Halt,
V
DD
= 3.0 to 3.6 V
50 µA
V
prog
Programming voltage 2 3.6 V
Table 29. Flash memory endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min
(1)
1. Based on characterization not tested in production.
Typ Max
N
END
Endurance
T
A
= –40 to +85 °C (6 suffix versions)
T
A
= –40 to +105 °C (7 suffix versions)
10 kcycles
t
RET
Data retention
1 kcycle
(2)
at T
A
= 85 °C
2. Cycling performed over the whole temperature range.
30
Years 1 kcycle
(2)
at T
A
= 105 °C 10
10 kcycles
(2)
at T
A
= 55 °C 20
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 55/97
Figure 15. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Data
FSMC_NE
FSMC_NBL[1:0]
FSMC_D[15:0]
t
v(BL_NE)
t
h(Data_NE)
FSMC_NOE
Address
FSMC_A[25:0]
t
v(A_NE)
FSMC_NWE
t
su(Data_NE)
MS18586V1
w(NOE)
t
t
v(NOE_NE)
t
h(NE_NOE)
t
h(Data_NOE)
t
h(A_NOE)
t
h(BL_NOE)
t
su(Data_NOE)
FSMC_NADV
(1)
t
v(NADV_NE)
t
w(NADV)
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
56/97 Doc ID 15081 Rev 5

Table 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
(1)

(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 5T
HCLK
– 1.5 5T
HCLK
+ 2 ns
t
v(NOE_NE)
FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns
t
w(NOE)
FSMC_NOE low time 5T
HCLK
– 1.5 5T
HCLK
+ 1.5 ns
t
h(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time –1.5 ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid 0 ns
t
h(A_NOE)
Address hold time after FSMC_NOE high 0.1 ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid 0 ns
t
h(BL_NOE)
FSMC_BL hold time after FSMC_NOE high 0 ns
t
su(Data_NE)
Data to FSMC_NEx high setup time 2T
HCLK
+ 25 ns
t
su(Data_NOE)
Data to FSMC_NOEx high setup time 2T
HCLK
+ 25 ns
t
h(Data_NOE)
Data hold time after FSMC_NOE high 0 ns
t
h(Data_NE)
Data hold time after FSMC_NEx high 0 ns
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 5 ns
t
w(NADV)
FSMC_NADV low time T
HCLK
+ 1.5 ns
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 57/97
Figure 16. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 3T
HCLK
– 1 3T
HCLK
+ 2 ns
t
v(NWE_NE)
FSMC_NEx low to FSMC_NWE low T
HCLK
– 0.5 T
HCLK
+ 1.5 ns
t
w(NWE)
FSMC_NWE low time T
HCLK
– 0.5 T
HCLK
+ 1.5 ns
t
h(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time T
HCLK
ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid 7.5 ns
t
h(A_NWE)
Address hold time after FSMC_NWE high T
HCLK
ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid 1.5 ns
t
h(BL_NWE)
FSMC_BL hold time after FSMC_NWE high T
HCLK
– 0.5 ns
t
v(Data_NE)
FSMC_NEx low to Data valid T
HCLK
+ 7 ns
t
h(Data_NWE)
Data hold time after FSMC_NWE high T
HCLK
ns
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 5.5 ns
t
w(NADV)
FSMC_NADV low time T
HCLK
+ 1.5 ns
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_D[15:0]
t
v(BL_NE)
t
h(Data_NWE)
FSMC_NOE
Address FSMC_A[25:0]
t
v(A_NE)
t
w(NWE)
FSMC_NWE
t
v(NWE_NE)
t
h(NE_NWE)
t
h(A_NWE)
t
h(BL_NWE)
t
v(Data_NE)
t
w(NE)
ai14990
FSMC_NADV
(1)
t
v(NADV_NE)
t
w(NADV)
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
58/97 Doc ID 15081 Rev 5
Figure 17. Asynchronous multiplexed PSRAM/NOR read waveforms

Table 32. Asynchronous multiplexed PSRAM/NOR read timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 7T
HCLK
– 2 7T
HCLK
+ 2 ns
t
v(NOE_NE)
FSMC_NEx low to FSMC_NOE low 3T
HCLK
– 0.5 3T
HCLK
+ 1.5 ns
t
w(NOE)
FSMC_NOE low time 4T
HCLK
– 1 4T
HCLK
+ 2 ns
t
h(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time –1 ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid 0 ns
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 3 5 ns
t
w(NADV)
FSMC_NADV low time T
HCLK
–1.5 T
HCLK
+ 1.5 ns
t
h(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
T
HCLK
ns
t
h(A_NOE)
Address hold time after FSMC_NOE high T
HCLK
ns
t
h(BL_NOE)
FSMC_BL hold time after FSMC_NOE high 0 ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid 0 ns
t
su(Data_NE)
Data to FSMC_NEx high setup time 2T
HCLK
+ 24 ns
t
su(Data_NOE)
Data to FSMC_NOE high setup time 2T
HCLK
+ 25 ns
t
h(Data_NE)
Data hold time after FSMC_NEx high 0 ns
t
h(Data_NOE)
Data hold time after FSMC_NOE high 0 ns
NBL
Data
FSMC_NBL[1:0]
FSMC_AD[15:0]
t
v(BL_NE)
t
h(Data_NE)
Address
FSMC_A[25:16]
t
v(A_NE)
FSMC_NWE
t
v(A_NE)
ai14892b
Address
FSMC_NADV
t
v(NADV_NE)
t
w(NADV)
t
su(Data_NE)
t
h(AD_NADV)
FSMC_NE
FSMC_NOE
t
w(NE)
t
w(NOE)
t
v(NOE_NE)
t
h(NE_NOE)
t
h(A_NOE)
t
h(BL_NOE)
t
su(Data_NOE)
t
h(Data_NOE)
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 59/97
Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms

Table 33. Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 5T
HCLK
– 1 5T
HCLK
+ 2 ns
t
v(NWE_NE)
FSMC_NEx low to FSMC_NWE low 2T
HCLK
2T
HCLK
+ 1 ns
t
w(NWE)
FSMC_NWE low time 2T
HCLK
– 1 2T
HCLK
+ 2 ns
t
h(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time T
HCLK
– 1 ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid 7 ns
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 3 5 ns
t
w(NADV)
FSMC_NADV low time T
HCLK
– 1 T
HCLK
+ 1 ns
t
h(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
T
HCLK
– 3 ns
t
h(A_NWE)
Address hold time after FSMC_NWE high 4T
HCLK
ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid 1.6 ns
t
h(BL_NWE)
FSMC_BL hold time after FSMC_NWE high T
HCLK
– 1.5 ns
t
v(Data_NADV)
FSMC_NADV high to Data valid T
HCLK
+ 1.5 ns
t
h(Data_NWE)
Data hold time after FSMC_NWE high T
HCLK
– 5 ns
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_AD[15:0]
t
v(BL_NE)
t
h(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:16]
t
v(A_NE)
t
w(NWE)
FSMC_NWE
t
v(NWE_NE)
t
h(NE_NWE)
t
h(A_NWE)
t
h(BL_NWE)
t
v(A_NE)
t
w(NE)
ai14891B
Address
FSMC_NADV
t
v(NADV_NE)
t
w(NADV)
t
v(Data_NADV)
t
h(AD_NADV)
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
60/97 Doc ID 15081 Rev 5
Synchronous waveforms and timings
Figure 19 through Figure 22 represent synchronous waveforms and Table 35 through
Table 37 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
● BurstAccessMode = FSMC_BurstAccessMode_Enable;
● MemoryType = FSMC_MemoryType_CRAM;
● WriteBurst = FSMC_WriteBurst_Enable;
● CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 19. Synchronous multiplexed NOR/PSRAM read timings
FSMC_CLK
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
FSMC_NOE
FSMC_AD[15:0] AD[15:0] D1 D2
FSMC_NWAÌT
(WAÌTCFG = 1b, WAÌTPOL + 0b)
FSMC_NWAÌT
(WAÌTCFG = 0b, WAÌTPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-AV)
t
d(CLKL-NADVH)
t
d(CLKL-AÌV)
t
d(CLKL-NOEL)
t
d(CLKL-NOEH)
t
d(CLKL-ADV)
t
d(CLKL-ADÌV)
t
su(ADV-CLKH)
t
h(CLKH-ADV)
t
su(ADV-CLKH) t
h(CLKH-ADV)
t
su(NWAÌTV-CLKH) t
h(CLKH-NWAÌTV)
t
su(NWAÌTV-CLKH) t
h(CLKH-NWAÌTV)
t
su(NWAÌTV-CLKH)
t
h(CLKH-NWAÌTV)
ai14893g
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 61/97

Table 34. Synchronous multiplexed NOR/PSRAM read timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 27.7 ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low 4 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 5 ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 ns
t
d(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low 1 ns
t
d(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high 0.5 ns
t
d(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid 12 ns
t
d(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid 0 ns
t
su(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK
high
6 ns
t
h(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high 0 ns
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 8 ns
t
h(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high 2 ns
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
62/97 Doc ID 15081 Rev 5
Figure 20. Synchronous multiplexed PSRAM write timings
FSMC_CLK
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
FSMC_NWE
FSMC_AD[15:0] AD[15:0] D1 D2
FSMC_NWAÌT
(WAÌTCFG = 0b, WAÌTPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL) t
d(CLKL-NExH)
t
d(CLKL-NADVL)
t
d(CLKL-AV)
t
d(CLKL-NADVH)
t
d(CLKL-AÌV)
t
d(CLKL-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-NBLH)
t
d(CLKL-ADV)
t
d(CLKL-ADÌV)
t
d(CLKL-Data)
t
su(NWAÌTV-CLKH)
t
h(CLKH-NWAÌTV)
ai14992f
t
d(CLKL-Data)
FSMC_NBL
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 63/97

Table 35. Synchronous multiplexed PSRAM write timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 27.7 ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_Nex low (x = 0...2) 2 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low 4 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 5 ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low 1 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 1 ns
t
d(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid 12 ns
t
d(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid 3 ns
t
d(CLKL-Data)
FSMC_A/D[15:0] valid after FSMC_CLK low 6 ns
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 7 ns
t
h(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high 2 ns
t
d(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high 1 ns
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
64/97 Doc ID 15081 Rev 5
Figure 21. Synchronous non-multiplexed NOR/PSRAM read timings

Table 36. Synchronous non-multiplexed NOR/PSRAM read timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 27.7 ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low 4 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 5 ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 0...25) 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 0...25) 4 ns
t
d(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low 1.5 ns
t
d(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high 1.5 ns
t
su(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK high 6.5 ns
t
h(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high 7 ns
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_SMCLK high 7 ns
t
h(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high 2 ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NOE
FSMC_D[15:0] D1 D2
FSMC_NWAÌT
(WAÌTCFG = 1b, WAÌTPOL + 0b)
FSMC_NWAÌT
(WAÌTCFG = 0b, WAÌTPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL)
t
d(CLKL-NExH)
t
d(CLKL-AV)
t
d(CLKL-AÌV)
t
d(CLKL-NOEL)
t
d(CLKL-NOEH)
t
su(DV-CLKH) t
h(CLKH-DV)
t
su(DV-CLKH)
t
h(CLKH-DV)
t
su(NWAÌTV-CLKH)
t
h(CLKH-NWAÌTV)
t
su(NWAÌTV-CLKH)
t
h(CLKH-NWAÌTV)
t
su(NWAÌTV-CLKH)
t
h(CLKH-NWAÌTV)
ai14894f
FSMC_NADV
t
d(CLKL-NADVL) t
d(CLKL-NADVH)
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 65/97
Figure 22. Synchronous non-multiplexed PSRAM write timings

Table 37. Synchronous non-multiplexed PSRAM write timings
(1)(2)
1. C
L
= 15 pF.
2. Preliminary values.
Symbol Parameter Min Max Unit
t
w(CLK)
FSMC_CLK period 27.7 ns
t
d(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2) 2 ns
t
d(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns
t
d(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low 4 ns
t
d(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high 5 ns
t
d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns
t
d(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 ns
t
d(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low 1 ns
t
d(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high 1 ns
t
d(CLKL-Data)
FSMC_D[15:0] valid data after FSMC_CLK low 6 ns
t
su(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high 7 ns
t
h(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high 2 ns
t
d(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high 1 ns
FSMC_CLK
FSMC_NEx
FSMC_A[25:0]
FSMC_NWE
FSMC_D[15:0] D1 D2
FSMC_NWAÌT
(WAÌTCFG = 0b, WAÌTPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
BUSTURN = 0
t
d(CLKL-NExL) t
d(CLKL-NExH)
t
d(CLKL-AV)
t
d(CLKL-AÌV)
t
d(CLKL-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-Data)
t
su(NWAÌTV-CLKH)
t
h(CLKH-NWAÌTV)
ai14993g
FSMC_NADV
t
d(CLKL-NADVL) t
d(CLKL-NADVH)
t
d(CLKL-Data)
FSMC_NBL
t
d(CLKL-NBLH)
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
66/97 Doc ID 15081 Rev 5
5.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
DD
and
V
SS
through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 38. They are based on the EMS levels and classes
defined in application note AN1709.

Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
● Corrupted program counter
● Unexpected reset
● Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 38. EMS characteristics
Symbol Parameter Conditions Level/Class
V
FESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
V
DD
= 3.3 V, T
A
= +25 °C,
f
HCLK
= 24 MHz, LQFP144
package, conforms to
IEC 61000-4-2
2B
V
EFTB
Fast transient voltage burst limits to be
applied through 100 pF on V
DD
and V
SS
pins
to induce a functional disturbance
V
DD
= 3.3 V, T
A
= +25 °C,
f
HCLK
= 24 MHz, LQFP144
package, conforms to
IEC 61000-4-4
4A
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 67/97
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

5.3.12 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage is applied to each power supply pin
● A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD78 IC latch-up standard.

Table 39. EMI characteristics
Symbol Parameter Conditions
Monitored
frequency band
Max vs. [f
HSE
/f
HCLK
]
Unit
8/24 MHz
S
EMI
Peak level
V
DD
= 3.6 V, T
A
= 25°C,
LQFP144 package
compliant with SAE
J1752/3
0.1 MHz to 30 MHz 16
dBµV 30 MHz to 130 MHz 25
130 MHz to 1GHz 25
SAE EMI Level 4 -
Table 40. ESD absolute maximum ratings
Symbol Ratings Conditions Class
Maximum
value
(1)
1. Based on characterization results, not tested in production.
Unit
V
ESD(HBM)
Electrostatic discharge
voltage (human body model)
T
A
= +25 °C
conforming to JESD22-A114
2 2000
V
V
ESD(CDM)
Electrostatic discharge
voltage (charge device model)
T
A
= +25 °C
conforming to JESD22-C101
II 500
Table 41. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class T
A
= +105 °C conforming to JESD78 II level A
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
68/97 Doc ID 15081 Rev 5
5.3.13 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below V
SS
or
above V
DD
(for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into the
I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 42

Table 42. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
I
INJ
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0 +0
mA
Injected current on all FT pins -5 +0
Injected current on any other pin -5 +5
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 69/97
5.3.14 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL
compliant.

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os, and
in Figure 25 and Figure 26 for 5 V tolerant I/Os.
Table 43. I/O static characteristics
Symbol Parameter Conditions Min Typ

Max Unit
V
IL
Standard I/O input
low level voltage
–0.3 0.28*(V
DD
–2 V)+0.8 V
V
I/O FT
(1)
input low
level voltage
–0.3 0.32*(V
DD
–2 V)+0.75 V
V
IH
Standard I/O input
high level voltage
0.41*(V
DD
–2 V) +1.3 V V
DD
+0.3
I/O FT
(1)
input high
level voltage
V
DD
> 2 V
0.42*(V
DD
–2)+1 V
5.5
V
DD
≤ 2 V 5.2
V
hys
Standard I/O Schmitt
trigger voltage
hysteresis
(2)
200 mV
I/O FT Schmitt trigger
voltage hysteresis
(2)
5% V
DD
(3)
mV
I
lkg
Input leakage
current
(4)

V
SS
≤ V
IN
≤ V
DD
Standard I/Os
±1
µA
V
IN
= 5 V
I/O FT
3
R
PU
Weak pull-up
equivalent resistor
(5)
V
IN
= V
SS
30 40 50 kΩ
R
PD
Weak pull-down
equivalent resistor
(5)
V
IN
= V
DD
30 40 50 kΩ
C
IO
I/O pin capacitance 5 pF
1. FT = 5V tolerant. To sustain a voltage higher than V
DD
+0.3 the internal pull-up/pull-down resistors must be disabled.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by design, not tested in production.
3. With a minimum of 100 mV.
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
70/97 Doc ID 15081 Rev 5
Figure 23. Standard I/O input characteristics - CMOS port
Figure 24. Standard I/O input characteristics - TTL port
ai17277b
V
DD
(V)
1.3
0.8
2 3.6
Ìnput range
not guaranteed
1.59
1
2.7
V
ÌH
=0.41(V
DD
-2)+1.3
3
0.7
CMOS standard requirement V
ÌH
=0.65V
DD

3.3
V
ÌH
/V
ÌL
(V)
CMOS standard requirement V
ÌL
=0.35V
DD
l.25
l.96
l.7l
l.7l
l.59
l
l.08
l.08
v
ÌLmax
v
ÌHmin
V
DD
-2)+0.8
=0.28(V
ÌL
ai17278
2 3.6
Ìnput range
not guaranteed
V
ÌH
/V
ÌL
(V)
1.3
2.0
0.8
2.16
1.96
1.25
TTL requirements V
ÌH
=2V
V
ÌH
=0.41(V
DD
-2)+1.3
V
ÌL
=0.28(V
DD
-2)+0.8
TTL requirements V
ÌL
=0.8V
V
DD
(V)
v
ÌLmax
v
ÌHmin
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 71/97
Figure 25. 5 V tolerant I/O input characteristics - CMOS port
Figure 26. 5 V tolerant I/O input characteristics - TTL port
Output driving current
The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed V
OL
/V
OH
).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
● The sum of the currents sourced by all the I/Os on V
DD,
plus the maximum Run
consumption of the MCU sourced on V
DD,
cannot exceed the absolute maximum rating
I
VDD
(see Table 7).
● The sum of the currents sunk by all the I/Os on V
SS
plus the maximum Run
consumption of the MCU sunk on V
SS
cannot exceed the absolute maximum rating
I
VSS
(see Table 7).
VDD
1.3
2 3.6
CMOS standard requirements V
ÌH
=0.65V
DD

CMOS standard requirment V
ÌL
=0.35V
DD
1.67
1
2.7
0.7
3 3.3
1
0.75
1.295
0.975
1.42
1.07
1.55
1.16
V
ÌH
/V
ÌL
(V)
V
DD
(V)
Ìnput range
not guaranteed
ai17279b
V
ÌH
=0.42(V
DD
-2)+1
V
ÌL
=0.32(V
DD
-2)+0.75
2.0
0.8
2 3.6 2.16
not guaranteed
Ìnput range
1.67
1
0.75
TTL requirement V
ÌH
=2V
V
ÌH
=0.42*(V
DD
-2)+1
V
ÌL
=0.32*(V
DD
-2)+0.75
TTL requirements V
ÌL
=0.8V
V
ÌH
/V
ÌL
(V)
V
DD
(V)
v
ÌLmax
v
ÌHmin
ai17280
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
72/97 Doc ID 15081 Rev 5
Output voltage levels
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in Table 9. All I/Os are CMOS and TTL compliant.

Table 44. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
V
OL
(1)
1. The I
IO
current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
CMOS port
(2)
,
I
IO
= +8 mA,
2.7 V < V
DD
< 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
0.4
V
V
OH
(3)
3. The I
IO
current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD
.
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
V
DD
–0.4
V
OL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
TTL port
(2)
I
IO
= +8 mA
2.7 V < V
DD
< 3.6 V
0.4
V
V
OH
(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
2.4
V
OL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
I
IO
= +20 mA
(4)
2.7 V < V
DD
< 3.6 V
4. Based on characterization data, not tested in production.
1.3
V
V
OH
(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
V
DD
–1.3
V
OL
(1)
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
I
IO
= +6 mA
(4)
2 V < V
DD
< 2.7 V
0.4
V
V
OH
(3)
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
V
DD
–0.4
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 73/97
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 27 and
Table 45, respectively.
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in Table 9.

Table 45. I/O AC characteristics
(1)

1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F100xx reference manual for a
description of GPIO Port configuration register.
MODEx
[1:0] bit
value
(1)
Symbol Parameter Conditions Max Unit
10
f
max(IO)out
Maximum frequency
(2)
2. The maximum frequency is defined in Figure 27.
C
L
= 50 pF, V
DD
= 2 V to 3.6 V 2
(3)
MHz
t
f(IO)out
Output high to low level fall
time
C
L
= 50 pF, V
DD
= 2 V to 3.6 V
125
(3)
3. Guaranteed by design, not tested in production.
ns
t
r(IO)out
Output low to high level rise
time
125
(3)
01
f
max(IO)out
Maximum frequency
(2)
C
L
= 50 pF, V
DD
= 2 V to 3.6 V 10
(3)
MHz
t
f(IO)out
Output high to low level fall
time
C
L
= 50 pF, V
DD
= 2 V to 3.6 V
25
(3)
ns
t
r(IO)out
Output low to high level rise
time
25
(3)
11
f
max(IO)out
Maximum frequency
(2)
C
L
= 50 pF, V
DD
= 2 V to 3.6 V 24 MHz
t
f(IO)out
Output high to low level fall
time
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V 5
(3)
ns
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V 8
(3)
C
L
= 50 pF, V
DD
= 2 V to 2.7 V 12
(3)
t
r(IO)out
Output low to high level rise
time
C
L
= 30 pF, V
DD
= 2.7 V to 3.6 V 5
(3)
C
L
= 50 pF, V
DD
= 2.7 V to 3.6 V 8
(3)
C
L
= 50 pF, V
DD
= 2 V to 2.7 V 12
(3)
- t
EXTIpw
Pulse width of external
signals detected by the
EXTI controller
10
(3)
ns
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
74/97 Doc ID 15081 Rev 5
Figure 27. I/O AC characteristics definition
5.3.15 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Table 43).
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in Table 9.

Figure 28. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 46. Otherwise the reset will not be taken into account by the device.
ai14131
10%
90%
50%
t
r(I O)out
OUTPUT
EXTERNAL
ON 50pF
Maximum frequency is achieved if (t
r
+ t
f
) ≤ 2/3)T and if the duty cycle is (45-55%)

10%
50%
90%
when loaded by 50pF
T
t
r(I O)out
Table 46. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage –0.5 0.8
V
V
IH(NRST)
(1)
NRST Input high level voltage 2 V
DD
+0.5
V
hys(NRST)
NRST Schmitt trigger voltage
hysteresis
200 mV
R
PU
Weak pull-up equivalent resistor
(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance must be minimum (~10% order).
V
IN
= V
SS
30 40 50 kΩ
V
F(NRST)
(1)
NRST Input filtered pulse 100 ns
V
NF(NRST)
(1)
NRST Input not filtered pulse 300 ns
ai14132d
STM32F10x
R
PU
NRST
(2)
V
DD
Filter
Ìnternal reset
0.1 µF
External
reset circuit
(1)
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 75/97
5.3.16 TIMx characteristics
The parameters given in Table 47 are guaranteed by design.
Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output
alternate function characteristics (output compare, input capture, external clock, PWM
output).

5.3.17 Communications interfaces
I
2
C interface characteristics
Unless otherwise specified, the parameters given in Table 48 are preliminary values derived
from tests performed under the ambient temperature, f
PCLK1
frequency and V
DD
supply
voltage conditions summarized in Table 9.
The STM32F100xx value line I
2
C interface meets the requirements of the standard I
2
C
communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Table 48. Refer also to Section 5.3.13: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Table 47. TIMx characteristics
Symbol Parameter
Conditions
(1)
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM5, TIM15, TIM16 and TIM17
timers.
Min Max Unit
t
res(TIM)
Timer resolution time
1 t
TIMxCLK
f
TIMxCLK
= 24 MHz 41.7 ns
f
EXT
Timer external clock
frequency on CHx
(2)
2. CHx is used as a general term to refer to CH1 to CH4 for TIM1, TIM2, TIM3, TIM4 and TIM5, to the CH1 to
CH2 for TIM15, and to CH1 for TIM16 and TIM17.
0 f
TIMxCLK
/2 MHz
f
TIMxCLK
= 24 MHz 0 12 MHz
Res
TIM
Timer resolution 16 bit
t
COUNTER
16-bit counter clock period
when the internal clock is
selected
1 65536 t
TIMxCLK
f
TIMxCLK
= 24 MHz 2730 µs
t
MAX_COUNT
Maximum possible count
65536 × 65536 t
TIMxCLK
f
TIMxCLK
= 24 MHz 178 s
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
76/97 Doc ID 15081 Rev 5

Table 48. I
2
C characteristics
Symbol Parameter
Standard mode I
2
C
(1)
1. Guaranteed by design, not tested in production.
Fast mode I
2
C
(1)(2)
2. f
PCLK1
must be higher than 2 MHz to achieve standard mode I
2
C frequencies. It must be higher than
4 MHz to achieve fast mode I
2
C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz
maximum I2C fast mode clock.
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 1.3
µs
t
w(SCLH)
SCL clock high time 4.0 0.6
t
su(SDA)
SDA setup time 250 100
ns
t
h(SDA)
SDA data hold time 0
(3)
3. The maximum hold time of the Start condition only has to be met if the interface does not stretch the low
period of SCL signal.
0
(4)
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900
(3)
t
r(SDA)
t
r(SCL)
SDA and SCL rise time 1000 300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time 300 300
t
h(STA)
Start condition hold time 4.0 0.6
µs
t
su(STA)
Repeated Start condition setup
time
4.7 0.6
t
su(STO)
Stop condition setup time 4.0 0.6 µs
t
w(STO:STA)
Stop to Start condition time (bus
free)
4.7 1.3 µs
C
b
Capacitive load for each bus line 400 400 pF
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 77/97
Figure 29. I
2
C bus AC waveforms and measurement circuit
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.

Table 49. SCL frequency (f
PCLK1
= 24 MHz, V
DD
= 3.3 V)
(1)(2)
1. R
P
= External pull-up resistance, f
SCL
= I
2
C speed,
2. For speeds around 400 kHz, the tolerance on the achieved speed is of ±2%. For other speed ranges, the
tolerance on the achieved speed ±1%. These variations depend on the accuracy of the external
components used to design the application.
f
SCL
(kHz)
(3)
3. Guaranteed by design, not tested in production.
I2C_CCR value
R
P
= 4.7 kΩ
400 0x8011
300 0x8016
200 0x8021
100 0x0064
50 0x00C8
20 0x01F4
ai14133d
Start
SDA
100 Ω
4.7kΩ
̲C bus
4.7kΩ
100 Ω
V
DD
V
DD
STM32F10x
SDA
SCL
t
f(SDA)
t
r(SDA)
SCL
t
h(STA)
t
w(SCLH)
t
w(SCLL)
t
su(SDA)
t
r(SCL)
t
f(SCL)
t
h(SDA)
Start repeated
Start
t
su(STA)
t
su(STO)
Stop
t
su(STO:STA)
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
78/97 Doc ID 15081 Rev 5
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 50 are preliminary values derived
from tests performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply
voltage conditions summarized in Table 9.
Refer to Section 5.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 50. SPI characteristics
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode 12
MHz
Slave mode 12
t
r(SCK)
t
f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF 8 ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode 30 70 %
t
su(NSS)
(1)
1. Preliminary values.
NSS setup time Slave mode 4t
PCLK
ns
t
h(NSS)
(1)
NSS hold time Slave mode 2t
PCLK
t
w(SCKH)
(1)
t
w(SCKL)
(1)
SCK high and low time
Master mode, f
PCLK
= 24 MHz,
presc = 4
50 60
t
su(MI)
(1)
t
su(SI)
(1)
Data input setup time
Master mode 5
Slave mode 5
t
h(MI)
(1)
Data input hold time
Master mode 5
t
h(SI)
(1)
Slave mode 4
t
a(SO)
(1)(2)
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time Slave mode, f
PCLK
= 24 MHz 0 3t
PCLK
t
dis(SO)
(1)(3)
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time Slave mode 2 10
t
v(SO)
(1)
Data output valid time Slave mode (after enable edge) 25
t
v(MO)
(1)
Data output valid time
Master mode (after enable
edge)
5
t
h(SO)
(1)
Data output hold time
Slave mode (after enable edge) 15
t
h(MO)
(1)
Master mode (after enable
edge)
2
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 79/97
Figure 30. SPI timing diagram - slave mode and CPHA = 0
Figure 31. SPI timing diagram - slave mode and CPHA = 1
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
ai14134c
S
C
K

I
n
p
u
t CPHA=0
MOSI
I NPUT
MISO
OUT PUT
CPHA=0
MSB OUT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
NSS input
t
SU(NSS)
t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
ai14135
S
C
K

I
n
p
u
t CPHA=1
MOSI
I NPUT
MISO
OUT PUT
CPHA=1
MSB OUT
MSB IN
BI T6 OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
BI T1 IN
t
SU(NSS) t
c(SCK)
t
h(NSS)
t
a(SO)
t
w(SCKH)
t
w(SCKL)
t
v(SO)
t
h(SO)
t
r(SCK)
t
f(SCK)
t
dis(SO)
t
su(SI)
t
h(SI)
NSS input
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
80/97 Doc ID 15081 Rev 5
Figure 32. SPI timing diagram - master mode
1. Measurement points are done at CMOS levels: 0.3V
DD
and 0.7V
DD
.
HDMI consumer electronics control (CEC)
Refer to Section 5.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics.
5.3.18 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 51 are preliminary values derived
from tests performed under the ambient temperature, f
PCLK2
frequency and V
DDA
supply
voltage conditions summarized in Table 9.
Note: It is recommended to perform a calibration after each power-up.
ai14136
S
C
K

I
n
p
u
t CPHA=0
MOSI
OUTUT
MISO
INPUT
CPHA=0
MSBIN
MSB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
BI T1 OUT
NSS input
t
c(SCK)
t
w(SCKH)
t
w(SCKL)
t
r(SCK)
t
f(SCK)
t
h(MI)
High
S
C
K

I
n
p
u
t CPHA=1
CPHA=1
CPOL=0
CPOL=1
t
su(MI)
t
v(MO)
t
h(MO)
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 81/97

Equation 1: R
AIN
max formula:
The above formula (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 51. ADC characteristics
Symbol Parameter Conditions Min Typ

Max Unit
V
DDA
Power supply 2.4 3.6 V
V
REF+
Positive reference voltage 2.4 V
DDA
V
I
VREF
Current on the V
REF
input
pin
160
(1)
220
(1)
µA
f
ADC
ADC clock frequency 0.6 12 MHz
f
S
(2)
Sampling rate 0.05 1 MHz
f
TRIG
(2)
External trigger frequency
f
ADC
= 12 MHz 823 kHz
17 1/f
ADC
V
AIN
(3)
Conversion voltage range
0 (V
SSA
tied to
ground)
V
REF+
V
R
AIN
(2)
External input impedance
See Equation 1 and
Table 52 for details
50 kΩ
R
ADC
(2)
Sampling switch resistance 1 kΩ
C
ADC
(2)
Internal sample and hold
capacitor
8 pF
t
CAL
(2)
Calibration time
f
ADC
= 12 MHz 5.9 µs
83 1/f
ADC
t
lat
(2)
Injection trigger conversion
latency
f
ADC
= 12 MHz 0.214 µs
3
(4)
1/f
ADC
t
latr
(2)
Regular trigger conversion
latency
f
ADC
= 12 MHz 0.143 µs
2
(4)
1/f
ADC
t
S
(2)
Sampling time f
ADC
= 12 MHz
0.125 17.1 µs
1.5 239.5 1/f
ADC
t
STAB
(2)
Power-up time 0 0 1 µs
t
CONV
(2)
Total conversion time
(including sampling time)
f
ADC
= 12 MHz 1.17 21 µs
14 to 252 (t
S
for sampling +12.5 for
successive approximation)
1/f
ADC
1. Preliminary values.
2. Guaranteed by design, not tested in production.
3. V
REF+
is internally connected to V
DDA
4. For external triggers, a delay of 1/f
PCLK2
must be added to the latency specified in Table 51.
R
AIN
T
S
f
ADC
C
ADC
2
N 2 +
( ) ln × ×
-------------------------------------------------------------- R
ADC
– <
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
82/97 Doc ID 15081 Rev 5



Note: ADC accuracy vs. negative injection current: Injecting a negative current on any of the
standard (non-robust) analog input pins should be avoided as this significantly reduces the
accuracy of the conversion being performed on another analog input. It is recommended to
add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative currents.
Table 52. R
AIN
max for f
ADC
= 12 MHz
(1)
1. Guaranteed by design, not tested in production.
T
s
(cycles) t
S
(µs) R
AIN
max (kΩ)
1.5 0.125 0.4
7.5 0.625 5.9
13.5 1.125 11.4
28.5 2.375 25.2
41.5 3.45 37.2
55.5 4.625 50
71.5 5.96 NA
239.5 20 NA
Table 53. ADC accuracy - limited test conditions
(1)(2)
1. ADC DC accuracy values are measured after internal calibration.
2. Preliminary values.
Symbol Parameter Test conditions Typ Max Unit
ET Total unadjusted error f
PCLK2
= 24 MHz,
f
ADC
= 12 MHz, R
AIN
< 10 kΩ,
V
DDA
= 3 V to 3.6 V
V
REF+
= V
DDA
T
A
= 25 °C
Measurements made after
ADC calibration
±1.5 ±2.5
LSB
EO Offset error ±1 ±2
EG Gain error ±0.5 ±1.5
ED Differential linearity error ±1.5 ±2
EL Integral linearity error ±1.5 ±2
Table 54. ADC accuracy
(1)

(2) (3)
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted V
DD
, frequency, V
REF
and temperature ranges.
3. Preliminary values.
Symbol Parameter Test conditions Typ Max Unit
ET Total unadjusted error
f
PCLK2
= 24 MHz,
f
ADC
= 12 MHz, R
AIN
< 10 kΩ,
V
DDA
= 2.4 V to 3.6 V
T
A
= Full operating range
Measurements made after
ADC calibration
±2 ±5
LSB
EO Offset error ±1.5 ±2.5
EG Gain error ±1.5 ±3
ED Differential linearity error ±1.5 ±2.5
EL Integral linearity error ±1.5 ±4.5
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 83/97
Any positive injection current within the limits specified for I
INJ(PIN)
and ΣI
INJ(PIN)
in
Section 5.3.13 does not affect the ADC accuracy.
Figure 33. ADC accuracy characteristics
Figure 34. Typical connection diagram using the ADC
1. Refer to Table 51 for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 35 or Figure 36,
depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
E
O
E
G
1 LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
T
=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual
transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal
transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 4093 4094 4095 4096
(1)
(2)
E
T
E
D
E
L
(3)
V
DDA
V
SSA ai14395b
V
REF+
4096
(or depending on package)]
V
DDA
4096
[1LSB
IDEAL
=

ai14139d
STM32F10xxx
V
DD
AINx
I
L
±1 µA
0.6 V
V
T
R
AIN
(1)
Cparasitic
V
AIN
0.6 V
V
T
R
ADC
(1)
C
ADC
(1)
12-bit
converter
Sample and hold ADC
converter
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
84/97 Doc ID 15081 Rev 5
Figure 35. Power supply and reference decoupling (V
REF+
not connected to V
DDA
)
1. V
REF+
is available on 100-pin packages and on TFBGA64 packages. V
REF-
is available on 100-pin
packages only.
Figure 36. Power supply and reference decoupling (V
REF+
connected to V
DDA
)
1. V
REF+
and V
REF-
inputs are available only on 100-pin packages.
V
REF+
STM32F10xxx
V
DDA
V
SSA
/V
REF-
1 µF // 10 nF
1 µF // 10 nF
ai14380b
V
REF+
/V
DDA
STM32F10xxx
1 µF // 10 nF
V
REF–
/V
SSA
ai14381b
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 85/97
5.3.19 DAC electrical specifications

Table 55. DAC characteristics
Symbol Parameter Min Typ Max
(1)
Unit Comments
V
DDA
Analog supply voltage 2.4 3.6 V
V
REF+
Reference supply voltage 2.4 3.6 V
V
REF+
must always be below
V
DDA
V
SSA
Ground 0 0 V
R
LOAD
(1)
Resistive load with buffer ON 5 kΩ
R
O
(1)
Impedance output with buffer OFF 15 kΩ
When the buffer is OFF, the
Minimum resistive load
between DAC_OUT and V
SS
to
have a 1% accuracy is 1.5 MΩ
C
LOAD
(1)
Capacitive load 50 pF
Maximum capacitive load at
DAC_OUT pin (when the buffer
is ON).
DAC_OUT
min
(1)
Lower DAC_OUT voltage with buffer
ON
0.2 V
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
V
REF+
= 3.6 V and (0x155) and
(0xEAB) at V
REF+
= 2.4 V
DAC_OUT
max
(1)
Higher DAC_OUT voltage with buffer
ON
V
DDA

0.2
V
DAC_OUT
min
(1)
Lower DAC_OUT voltage with buffer
OFF
0.5 mV
It gives the maximum output
excursion of the DAC.
DAC_OUT
max
(1)
Higher DAC_OUT voltage with buffer
OFF
V
REF+

– 1LSB
V
I
DDVREF+
DAC DC current consumption in
quiescent mode (Standby mode)
220 µA
With no load, worst code
(0xF1C) at V
REF+
= 3.6 V in
terms of DC consumption on
the inputs
I
DDA
DAC DC current consumption in
quiescent mode (Standby mode)
380 µA
With no load, middle code
(0x800) on the inputs
480 µA
With no load, worst code
(0xF1C) at V
REF+
= 3.6 V in
terms of DC consumption on
the inputs
DNL
(1)
Differential non linearity Difference
between two consecutive code-1LSB)
±0.5 LSB
Given for the DAC in 10-bit
configuration
±2 LSB
Given for the DAC in 12-bit
configuration
INL
(1)
Integral non linearity (difference
between measured value at Code i
and the value at Code i on a line
drawn between Code 0 and last Code
1023)
±1 LSB
Given for the DAC in 10-bit
configuration
±4 LSB
Given for the DAC in 12-bit
configuration
Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE
86/97 Doc ID 15081 Rev 5
Figure 37. 12-bit buffered /non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
Offset
(1)
Offset error
(difference between measured value
at Code (0x800) and the ideal value =
V
REF+
/2)
±10 mV
Given for the DAC in 12-bit
configuration
±3 LSB
Given for the DAC in 10-bit at
V
REF+
= 3.6 V
±12 LSB
Given for the DAC in 12-bit at
V
REF+
= 3.6 V
Gain
error
(1)
Gain error ±0.5 %
Given for the DAC in 12-bit
configuration
t
SETTLING
(1)
Settling time (full scale: for a 10-bit
input code transition between the
lowest and the highest input codes
when DAC_OUT reaches final value
±1LSB
3 4 µs C
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
Update
rate
(1)
Max frequency for a correct
DAC_OUT change when small
variation in the input code (from code i
to i+1LSB)
1 MS/s C
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
t
WAKEUP
(1)
Wakeup time from off state (Setting
the ENx bit in the DAC Control
register)
6.5 10 µs
C
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+
(1)
Power supply rejection ratio (to V
DDA
)
(static DC measurement
–67 –40 dB No R
LOAD
, C
LOAD
= 50 pF
1. Preliminary values.
Table 55. DAC characteristics (continued)
Symbol Parameter Min Typ Max
(1)
Unit Comments
R
LOAD
C
LOAD
Buffered/Non-buffered DAC
DACx_OUT
Buffer(1)
12-bit
digital to
analog
converter
ai17157
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics
Doc ID 15081 Rev 5 87/97
5.3.20 Temperature sensor characteristics

Table 56. TS characteristics
Symbol Parameter Min Typ Max Unit
T
L
(1)
V
SENSE
linearity with temperature ±1 ±2 °C
Avg_Slope
(1)
Average slope 4.0 4.3 4.6 mV/°C
V
25
(1)
Voltage at 25°C 1.32 1.41 1.50 V
t
START
(2)
Startup time 4 10 µs
T
S_temp
(3)(2)
ADC sampling time when reading the temperature 17.1 µs
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
Package characteristics STM32F100xC, STM32F100xD, STM32F100xE
88/97 Doc ID 15081 Rev 5
6 Package characteristics
6.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®

specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
STM32F100xC, STM32F100xD, STM32F100xE Package characteristics
Doc ID 15081 Rev 5 89/97

1. Drawing is not to scale.
2. Dimensions are in millimeters.

Figure 38. LQFP144, 20 x 20 mm, 144-pin thin quad flat
package outline
Figure 39. Recommended
footprint
D1
D3
D
E1
E3
E
e
Pin 1
identification
73
72
37
36
109
144
108
1
A A2 A1
b
c
A1
L
L1
k
Seating plane
C
ccc C
0.25 mm
gage plane
ME_1A
0.5
0.35
19.9
17.85
22.6
1.35
22.6
19.9
ai14
1 36
37
72
73 108
109
144
Table 57. LQFP144, 20 x 20 mm, 144-pin thin quad flat package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.20 0.0035 0.0079
D 21.80 22.00 22.20 0.8583 0.8661 0.874
D1 19.80 20.00 20.20 0.7795 0.7874 0.7953
D3 17.50 0.689
E 21.80 22.00 22.20 0.8583 0.8661 0.874
E1 19.80 20.00 20.20 0.7795 0.7874 0.7953
E3 17.50 0.689
e 0.50 0.0197
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
k 0° 3.5° 7° 0° 3.5° 7°
ccc 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F100xC, STM32F100xD, STM32F100xE
90/97 Doc ID 15081 Rev 5

1. Drawing is not to scale.
2. Dimensions are in millimeters.

Figure 40. LQFP100 – 14 x 14 mm, 100-pin low-profile
quad flat package outline
Figure 41. Recommended footprint
D
D1
D3
75 51
50 76
100 26
1 25
E3 E1 E
e
b
Pin 1
identification
SEATING PLANE
GAGE PLANE
C
A
A2
A1
C ccc
0.25 mm
0.10 inch
L
L1
k
C
1L_ME
75 51
50 76
0.5
0.3
16.7 14.3
100 26
12.3
25
1.2
16.7
1
ai14906b
Table 58. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.20 0.0035 0.0079
D 15.80 16.00 16.20 0.622 0.6299 0.6378
D1 13.80 14.00 14.20 0.5433 0.5512 0.5591
D3 12.00 0.4724
E 15.80 16.00 16.20 0.622 0.6299 0.6378
E1 13.80 14.00 14.20 0.5433 0.5512 0.5591
E3 12.00 0.4724
e 0.50 0.0197
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
k 0° 3.5° 7° 0° 3.5° 7°
ccc 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F100xC, STM32F100xD, STM32F100xE Package characteristics
Doc ID 15081 Rev 5 91/97

1. Drawing is not to scale.
2. Dimensions are in millimeters.

Figure 42. LQFP64 – 10 x 10 mm, 64 pin low-profile quad
flat package outline
Figure 43. Recommended
footprint
A
A2
A1
c
L1
L
E E1
D
D1
e
b
ai14398b
48
32 49
64 17
1 16
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909
Table 59. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data
Symbol
millimeters inches
(1)
Min Typ Max Min Typ Max
A 1.60 0.0630
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.20 0.0035 0.0079
D 12.00 0.4724
D1 10.00 0.3937
E 12.00 0.4724
E1 10.00 0.3937
e 0.50 0.0197
θ 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
N
Number of pins
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Package characteristics STM32F100xC, STM32F100xD, STM32F100xE
92/97 Doc ID 15081 Rev 5
6.2 Thermal characteristics
The maximum chip junction temperature (T
J
max) must never exceed the values given in
Table 9: General operating conditions on page 37.
The maximum chip-junction temperature, T
J
max, in degrees Celsius, may be calculated
using the following equation:
T
J
max = T
A
max + (P
D
max x Θ
JA
)
Where:
● T
A
max is the maximum ambient temperature in °C,
● Θ
JA
is the package junction-to-ambient thermal resistance, in °C/W,
● P
D
max is the sum of P
INT
max and P
I/O
max (P
D
max = P
INT
max + P
I/O
max),
● P
INT
max is the product of I
DD
and

V
DD
, expressed in Watts. This is the maximum chip
internal power.
P
I/O
max represents the maximum power dissipation on output pins where:
P
I/O
max = Σ (V
OL
× I
OL
) + Σ((V
DD
– V
OH
) × I
OH
),
taking into account the actual V
OL
/ I
OL
and V
OH
/ I
OH
of the I/Os at low and high level in the
application.

6.2.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 60. Package thermal characteristics
Symbol Parameter Value Unit
Θ
JA
Thermal resistance junction-ambient
LQFP 144 - 20 × 20 mm / 0.5 mm pitch
35
°C/W
Thermal resistance junction-ambient
LQFP 100 - 14 × 14 mm / 0.5 mm pitch
40
Thermal resistance junction-ambient
LQFP 64 - 10 × 10 mm / 0.5 mm pitch
49
STM32F100xC, STM32F100xD, STM32F100xE Package characteristics
Doc ID 15081 Rev 5 93/97
6.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 61: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F100xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example: high-performance application
Assuming the following application conditions:
Maximum ambient temperature T
Amax
= 82 °C (measured according to JESD51-2),
I
DDmax
= 50 mA, V
DD
= 3.5 V, maximum 20 I/Os used at the same time in output at low
level with I
OL
= 8 mA, V
OL
= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with I
OL
= 20 mA, V
OL
= 1.3 V
P
INTmax
=

50 mA × 3.5 V= 175 mW
P
IOmax
=

20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: P
INTmax
= 175 mW and P
IOmax
= 272 mW
P
Dmax
=

175

+

272 = 447 mW
Thus: P
Dmax
= 447 mW
Using the values obtained in Table 60 T
Jmax
is calculated as follows:
– For LQFP64, 49 °C/W
T
Jmax
= 82 °C + (49 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the range of the suffix 6 version parts (–40 < T
J
< 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 61: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature T
J
remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature T
Amax
= 115 °C (measured according to JESD51-2),
I
DDmax
= 20 mA, V
DD
= 3.5 V, maximum 20 I/Os used at the same time in output at low
level with I
OL
= 8 mA, V
OL
= 0.4 V
P
INTmax
=

20 mA × 3.5 V= 70 mW
P
IOmax
=

20 × 8 mA × 0.4 V = 64 mW
This gives: P
INTmax
= 70 mW and P
IOmax
= 64 mW:
P
Dmax
=

70

+

64 = 134 mW
Thus: P
Dmax
= 134 mW
Package characteristics STM32F100xC, STM32F100xD, STM32F100xE
94/97 Doc ID 15081 Rev 5
Using the values obtained in Table 60 T
Jmax
is calculated as follows:
– For LQFP100, 40 °C/W
T
Jmax
= 115 °C + (40 °C/W × 134 mW) = 115 °C + 5.4 °C = 120.4 °C
This is within the range of the suffix 7 version parts (–40 < T
J
< 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 61: Ordering information scheme).
Figure 44. LQFP100 P
D
max vs. T
A
0
100
200
300
400
500
600
700
65 75 85 95 105 115 125 135
T
A
(°C)
P
D

(
m
W
)
Suffix 6
Suffix 7
STM32F100xC, STM32F100xD, STM32F100xE Ordering information scheme
Doc ID 15081 Rev 5 95/97
7 Ordering information scheme

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 61. Ordering information scheme
Example: STM32 F 100 V C T 6 B xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
100 = value line
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Flash memory size
C = 256 Kbytes of Flash memory
D = 384 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Internal code
B
Options
xxx = programmed parts
TR = tape and real
Revision history STM32F100xC, STM32F100xD, STM32F100xE
96/97 Doc ID 15081 Rev 5
8 Revision history

Table 62. Document revision history
Date Revision Changes
09-Oct-2008 1 Initial release.
31-Mar-2009 2
I/O information clarified on page 1.
Table 5: High-density STM32F100xx pin definitions modified.
Figure 5: Memory map on page 26 modified.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Table 20: High-speed external user clock characteristics and Table
21: Low-speed user external clock characteristics modified. ACCHSI
max values modified in Table 24: HSI oscillator characteristics.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Table 15:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Figure 10, Figure 11 and Figure 12 show typical curves (titles
changed).
Small text changes.
01-Sep-2010 3
Major revision of whole document.
Added LQFP144 package and additional peripherals (SPI3, UART4,
UART, TIM5, 12, 14, 13, FSMC).
18-Oct-2010 4
Updated Power consumption data in Table 13 to Table 16
Updated Section 5.3.11: EMC characteristics on page 66
11-Apr-2011 5
Added Section 2.2.6: LCD parallel interface on page 13
In Table 4 on page 24 moved TIM15_BKIN and TIM17_BKIN from
remap to default column. Updated description of PA3, PA5 and PF6
to PF10.
Updated footnotes below Table 6: Voltage characteristics on page 36
and Table 7: Current characteristics on page 37
Added VBAT values in Table 16: Typical and maximum current
consumptions in Stop and Standby modes on page 43
Updated tw min in Table 20: High-speed external user clock
characteristics on page 47
Updated startup time in Table 23: LSE oscillator characteristics
(fLSE = 32.768 kHz) on page 51
Added HSI clock accuracy values in Table 24: HSI oscillator
characteristics on page 52
Updated FSMC Synchronous waveforms and timings on page 60
Updated Table 43: I/O static characteristics on page 69
Added Section 5.3.13: I/O current injection characteristics on
page 68
Corrected TTL and CMOS designations in Table 44: Output voltage
characteristics on page 72
STM32F100xC, STM32F100xD, STM32F100xE
Doc ID 15081 Rev 5 97/97


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Contents

STM32F100xC, STM32F100xD, STM32F100xE

Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 2.2.14 2.2.15 2.2.16 2.2.17 2.2.18 2.2.19 2.2.20 2.2.21 2.2.22 2.2.23 2.2.24 2.2.25 2.2.26 2.2.27 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 13 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 13 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 14 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Universal synchronous/asynchronous receiver transmitter (USART) . . 19 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . 19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 Remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21

3

Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/97

Doc ID 15081 Rev 5

STM32F100xC, STM32F100xD, STM32F100xE

Contents

4 5

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2 5.3

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 38 Embedded reset and power control block characteristics . . . . . . . . . . . 39 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 67 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Doc ID 15081 Rev 5 3/97

. . .2 STM32F100xC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Contents 6. . . . .1 6. . 95 Revision history . . . . . . . . . . . . . . . . . . . . . . . STM32F100xD. . . . . . . . . . . . . . .2. . . . . . . . . . . . STM32F100xE Reference document . . . . . . 93 7 8 Ordering information scheme .2. . . . . . 96 4/97 Doc ID 15081 Rev 5 . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 EMS characteristics . . Table 39. . . . . . . . . . . 53 PLL characteristics . . . . . . . . . . . . . . . . . . . . Table 34. . . . . . . . . . . . . . . . . . . . . . . Table 42. . . . . . . . . 54 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8. . . . . . . . . . . . . . STM32F100xD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 41. . 39 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . 72 Doc ID 15081 Rev 5 5/97 . . . . . . . . . . 43 Typical current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . Table 9. . . . . . . . . . . . . . . Table 36. . . . . . . . . . . . . . Table 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . Table 37. . . . . . . . . . 64 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F100xx features and peripheral counts . . . . . . . . . . . . . Table 31. . . . . . . . . . . . . . . . . code running from Flash or RAM. . code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . 54 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . Table 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Peripheral current consumption . . . . . . . . . . . . 67 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13. . . . . . Table 26. . . . . . . . . . 66 EMI characteristics . . . . 38 Embedded reset and power control block characteristics. . . . . . . 57 Asynchronous multiplexed PSRAM/NOR read timings. . . 52 Low-power mode wakeup timings . 41 Maximum current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 40. . . . . . . . . . 63 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . Table 43. . . . . . . . . . . . . . . . . . . . Table 44. . . . . Table 29. . . . . . 48 HSE 4-24 MHz oscillator characteristics. . . 36 Current characteristics . . . . . . . . 40 Maximum current consumption in Run mode. . . . . . . . . . . . . . . . . . . . code with data processing running from RAM. . 68 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 22. . . . . . . . . . . . . . . . . . . . code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage characteristics . . . 61 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LSE oscillator characteristics (fLSE = 32. . . . . . . . . . . . . Table 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F100xE List of tables List of tables Table 1. . . Table 17. 37 General operating conditions . . . . . . Table 14. . . . . . . . . 69 Output voltage characteristics . . . . . . . . . . . 17 High-density STM32F100xx pin definitions . . 47 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . .STM32F100xC. . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 32. . . . . . . . . . Table 2. . . . Device summary . . . 56 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . 52 LSI oscillator characteristics . . . 53 Flash memory characteristics . . . . . 41 STM32F100xxB maximum current consumption in Sleep mode. . . . . . .768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 24. . . . . . . . . . . . . . . . . . Table 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15. . . . . . 58 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . 24 FSMC pin definition . . . . . . . . . . . . code running from Flash or RAM . . . . . . . . . . . . Table 6. . . . . . . . . . . . . . . . 44 Typical current consumption in Sleep mode. . . . . . . . . . . 42 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . Table 19. . . . . . . . . Table 35. . . . . . . . . . Table 27. . . . . . . . . . . . . . . . . . . . . . . . . . Table 18. . . . . . . Table 16. . Table 5. . . . . . . 67 Electrical sensitivities . . . . . . . . . . . . . . . . Table 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21. . . . 67 I/O current injection susceptibility . . . . Table 38. . . . . . . . . . Table 11. . . . . . . . . . . . . Table 4. . . . . . . . . . . . 37 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . Table 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . 75 I2C characteristics. . . . Table 57. . . Table 61. . . . Table 54. . . . . STM32F100xC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 53. . . . . . . . . . . . . . 74 TIMx characteristics . . . . . . . . . . . . STM32F100xD. . . . . . . . . . . . . . . . . . . . . . . Table 59. . . . . . . . . . . . . . . . . . .3 V) . . . . . . . . . . . . Table 52. . . . . . . . . . . . . . . . . . . Table 46. . . . . . . 64 pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . 20 x 20 mm. . . . . . . . . 90 LQFP64 – 10 x 10 mm. . . . . Table 55. . . . . Table 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Ordering information scheme . . . . . . . . . . . . . . . 91 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . Table 58. . . . . . . . . . . . . . . . . . . . . . . . . Table 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 50. . . . . 87 LQFP144. . . . . . 77 SPI characteristics . . . . . . 82 ADC accuracy . . 78 ADC characteristics . . . . . . . . . . . . . . . . 144-pin thin quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 62. . . . 96 6/97 Doc ID 15081 Rev 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LQPF100 – 14 x 14 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 48. . . . . . Table 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F100xE I/O AC characteristics . . . . 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 95 Document revision history . . . . . . . . . . . . VDD = 3. . . . . . . . . . . . . . . . . Table 56.List of tables Table 45. . . . . . . . . . . . . . . . . . . 82 ADC accuracy . . . . . . . Table 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .limited test conditions . . . 73 NRST pin characteristics . . . . . . . . . . . . . . . . 85 TS characteristics . . . . . . . . 81 RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . 76 SCL frequency (fPCLK1= 24 MHz. . . . . . . . . . . . . .

. . . . . Figure 8. . . . . . . . . . . . . 33 Pin loading conditions . . . . . . . . . . . . . . . . 86 LQFP144. . . . . . . . Figure 21. . . . . . . . . . . . . . . . 71 5 V tolerant I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical application with a 32. . . . . . . . . . . . . . . . Figure 43. . . . 100-pin low-profile quad flat package outline . . . . . . . . 20 x 20 mm. . . . Figure 25. . . . . . . . . . . . . . . . Figure 24. . . . . . . . . . . . . . . . Figure 28. . . . . Figure 37. . . . . . . . . 90 LQFP64 – 10 x 10 mm. . . . . . . . . . . . . . . . . 84 12-bit buffered /non-buffered DAC . . . . . . . . . 90 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . 23 STM32F100xx value line in LQFP64 pinout . . . . . . . . . . . . . .CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29. . Figure 16. . . . . . . . . . . . . . . . . . . . . . . . . STM32F100xx value line block diagram . . . . . . . . . . . . . . . . . . . . . Figure 20. . . . . . . . . . 71 I/O AC characteristics definition . . . . . . . . Figure 13. . Figure 5. . . . . . . . . . . . 62 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Doc ID 15081 Rev 5 7/97 . . . . . . . . . . . . . . . . . . . 77 SPI timing diagram . . . . . . . . . . . . . . Figure 44. . . . . . Figure 40. . . . . . . . . . . . . Figure 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. . . . . . . . . . . Figure 33. . . STM32F100xE List of figures List of figures Figure 1. . . . . . . . . . . . . . . . . . . . . . . . Figure 35. . . . . . . . . Figure 17. 83 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . 59 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . .STM32F100xC. . . . . . . . . . . . . . . . . . . . . . . . . . . . TA . . . . . . . 74 Recommended NRST pin protection . . . . . . . 64 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . 12 STM32F100xx value line LQFP144 pinout . . Figure 4. . . . . . . . 35 Current consumption measurement scheme . . Figure 10. . . . . . . . 83 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . .768 kHz crystal . . . . . . . . . . . . . . Figure 41. . . . . . 70 Standard I/O input characteristics . . . . . . . . . . . . . . . . . Figure 22. . . . . . . . . . . . . . . . . . . . . . Figure 3. . . . . . . . . Figure 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . Figure 31. . 57 Asynchronous multiplexed PSRAM/NOR read waveforms. 65 Standard I/O input characteristics . . . . . . . . . . . . . . . . . . 24 Memory map . . . . . . . . . 35 Pin input voltage . . . . . . . . . . 49 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . .TTL port . . . . . 89 LQFP100 – 14 x 14 mm. . 89 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11. . . . .CMOS port . . . . . . Figure 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12. . . . . . . . . . . . .slave mode and CPHA = 1 . . . . 79 SPI timing diagram . . . . . . . . . . . . . . . . . Figure 36. . . .master mode . . Figure 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 V tolerant I/O input characteristics . . . . . . 55 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . 58 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . Figure 39. . . . . . . . . Figure 14. . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27. . .slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . 35 Power supply scheme. . . . . . . . . . . . . . . . . . . . STM32F100xD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26. . . . . . . . . . . . . . . . . . . 74 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . Figure 42. . . . . . . . . Figure 34. . . . . . . 91 Recommended footprint . . . . . . . . . . . . . . . . . . . 36 High-speed external clock source AC timing diagram . . . . Figure 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32F100xx value line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADC accuracy characteristics . . . . . . . . . Figure 38. . . . . . . . . . . . . . . . . . Figure 15. . . . . . . . . . . . . . . . . . . . . 144-pin thin quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LQFP100 PD max vs. . . 11 Clock tree . . . . . . . . . Figure 9. . . . . . .TTL port . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23. . . . .

STM32F100xE 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F100xC. the STM32F100xC. STM32F100xD and STM32F100xE datasheet should be read in conjunction with the STM32F100xx high-density ARM-based 32-bit MCUs reference manual (RM0059).com/help/index.com. For information on programming. STM32F100xD. STM32F100xD and STM32F100xE value line microcontrollers. In the rest of the document.doc.com website at the following address: http://infocenter. STM32F100xD and STM32F100xE are referred to as high-density value line devices.st.arm. available from the www. The reference and Flash programming manuals are both available from the STMicroelectronics website www.jsp?topic=/com. 8/97 Doc ID 15081 Rev 5 . For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual. This STM32F100xC.arm. erasing and protection of the internal Flash memory please refer to the STM32F100xx high-density value line Flash programming manual (PM0072).ddi0337e/.Introduction STM32F100xC.arm.

6 V power supply. STM32F100xD. and HVACs. up to three USARTs and 2 UARTS). Depending on the device chosen. GPS platforms. inverters. from a 2. different sets of peripherals are included. The STM32F100xx high-density value line family operates in the –40 to +85 °C and –40 to +105 °C temperature ranges. All devices offer standard communication interfaces (up to two I2Cs. one HDMI CEC. up to 9 general-purpose 16-bit timers and an advanced-control PWM timer. scanners. Doc ID 15081 Rev 5 9/97 . A comprehensive set of power-saving mode allows the design of low-power applications. a flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more) and an extensive range of enhanced peripherals and I/Os connected to two APB buses.STM32F100xC. industrial applications. alarm systems. two 12-bit DACs. video intercoms. medical and handheld equipment. printers. STM32F100xE Description 2 Description The STM32F100xx value line family incorporates the high-performance ARM Cortex™-M3 32-bit RISC core operating at a 24 MHz frequency. application control. The STM32F100xx value line family includes devices in three different packages ranging from 64 pins to 144 pins. the description below gives an overview of the complete range of peripherals proposed in this family. PC and gaming peripherals. These features make the STM32F100xx value line microcontroller family suitable for a wide range of applications such as motor drives. high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 32 Kbytes). three SPIs. one 12-bit ADC.0 to 3. PLCs.

Description STM32F100xC. For the LQFP100 package.Kbytes SRAM . 10/97 Doc ID 15081 Rev 5 .Kbytes FSMC Timers 384 32 No 1 10 3 2 3 2 1 1 16 channels 51 2 2 512 32 512 32 I C Communication USART interfaces UART CEC 12-bit synchronized ADC number of channels GPIOs 12-bit DAC Number of channels CPU frequency Operating voltage Operating temperatures Packages Ambient operating temperature: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to +125 °C LQFP64 LQFP100 LQFP144 1. only FSMC Bank1 is available.6 V (1) STM32F100Zx 256 24 384 32 Yes 1 10 3 2 3 2 1 1 16 channels 112 2 2 512 32 Flash .1 Table 2. STM32F100xD. Bank1 can only support a multiplexed NOR/PSRAM memory. Device overview STM32F100xx features and peripheral counts Peripheral STM32F100Rx 256 24 Advanced-control General-purpose SPI 2 STM32F100Vx 256 24 384 32 Yes 1 10 3 2 3 2 1 1 16 channels 80 2 2 24 MHz 2. STM32F100xE 2.0 to 3.

SCK. ETR and BKIN as AF MOSI. RTS. MISO. 1 compl. CTS. 2. NSS as AF RX. channel and BKIN as AF 1 channel.6 V VSS Ibus Cortex-M3 CPU Fmax : 24 MHz Dbus System AHB : F max = 24 MHz A[25:0] D[15:0] CLK NOE NWE NE[3:0] NBL[1:0] NWAIT NADV as AF 80 AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] 2 channels. MISO.8 V to 3. STM32F100xE Figure 1. 3. Doc ID 15081 Rev 5 11/97 . TA = –40 °C to +85 °C (junction temperature up to 105 °C) or TA = –40 °C to +105 °C (junction temperature up to 125 °C).TX. RTS. CK as AF RX. SCK. 1 compl.TX. SMBA as AF TIM15 TIM16 TIM17 TIM1 SPI1 APB1: Fmax = 24 MHz 16 ADC channels (ADC_INx) V SPI2 SPI3 V TIM6 @VDDA TIM7 HDMI CEC I2C1 I2C2 12-bit DAC1 IF 12-bit DAC2 DAC1_OUT as AF DAC2 _OUT as AF @VDDA ai17515b 1.STM32F100xC. CK as AF RX. CTS. MISO. R CK as AF MOSI. channels. TX. STM32F100xx value line block diagram Trace controller Flash obl interface Flash 512 KB 32 bit POR Reset @VDDA RC HS RC LS Int Description TRACECLK TRACED[0:3] as AF NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF JTAG & SW pbus VDD18 Power Voltage reg.TX. NSS as AF HDMI CEC as AF SCL.6 V . 1 compl.3 V to 1.TX.I T WKUP GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F AHB2 APB 2 PCLK1 PCLK2 HCLK FCLK VBA T = 1. channel and BKIN as AF 4 channels.8 V @VDD33 Supply supervision POR / PDR PVD @VDDA @VDD VDD= 2. OSC32_IN OSC32_OUT TAM PER-RTC (ALARM OUT) Backup interface TIM2 TIM3 TIM4 TIM5 GPIO port G APB2: Fmax = 24 MHz TIM12 TIM13 TIM14 USART2 USART3 UART4 USART1 UART5 Temp sensor WWDG 12-bit ADC1 IF REF+ REF– AHB2 APB1 4 channels as AF 4 channels as AF 4 channels as AF 4 channels as AF 2 channels as AF 1 channel as AF 1 channel as AF RX. NSS as AF MOSI. CTS. SDA.0 V to 3. CK as AF NVIC GP DMA 12 channels Bus matrix SRAM 32 KB NRST VDDA VSSA PLL XTAL OSC 4-24 MHz IWDG Standby interface @VBAT XTAL 32 kHz RTC AWU Backup register OSC_IN OSC_OUT FSMC Reset & clock control EXT. RTS. SDA. CK as AF RX. SMBA as AF SCL. channel and BKIN as AF 1 channel. SCK. CTS. RTS. CTS. STM32F100xD. AF = alternate function on I/O port pin. 3 compl.

Description Figure 2. STM32F100xE 1.2 µs. 12/97 Doc ID 15081 Rev 5 . STM32F100xD. APB2 must be at 24 MHz. Clock tree STM32F100xC. To obtain an ADC conversion time of 1.

In the scope of the EN/IEC 60335-1 standard.2 2.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency.2 Embedded Flash memory Up to 512 Kbytes of embedded Flash memory is available for storing programs and data.2. Among other applications. and NOR. and is flexible enough to adapt to Doc ID 15081 Rev 5 13/97 . while delivering outstanding computational performance and an advanced system response to interrupts.2. It supports the Intel 8080 and Motorola 6800 modes. 2.2. 2. delivering the high-performance expected from an ARM core in the memory size usually associated with 8.4 Embedded SRAM Up to 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. STM32F100xD.2. with a reduced pin count and low-power consumption. CRC-based techniques are used to verify data transmission or storage integrity. STM32F100xE Description 2. It has four Chip Select outputs supporting the following modes: SRAM.and 16-bit devices. 2. is therefore compatible with all ARM tools and software.2.1 Overview ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. Functionality overview: ● ● ● ● ● The three FSMC interrupt lines are ORed in order to be connected to the NVIC No read FIFO Code execution from external memory No boot capability The targeted frequency is HCLK/2. The CRC calculation unit helps compute a signature of the software during runtime.6 LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. PSRAM. they offer a means of verifying the Flash memory integrity.2. 2.5 FSMC (flexible static memory controller) The FSMC is embedded in the high-density value line family. to be compared with a reference signature generated at linktime and stored at a given memory location. It has been developed to provide a low-cost platform that meets the needs of MCU implementation. The STM32F100xx value line family having an embedded ARM core. so external access is at 12 MHz when HCLK is at 24 MHz 2.STM32F100xC.

2.2.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 18 edge detector lines used to generate interrupt/event requests.2. resonator or oscillator). Similarly. Each line can be independently configured to select the trigger event (rising edge. STM32F100xD. 2. 2. Several prescalers allow the configuration of the AHB frequency.10 Boot modes At startup. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. A software interrupt is generated if enabled. A pending register maintains the status of the interrupt requests. however the internal RC 8 MHz oscillator is selected as default CPU clock on reset.2.Description STM32F100xC. the system automatically switches back to the internal RC oscillator.2. in which case it is monitored for failure. the high-speed APB (APB2) and the low-speed APB (APB1) domains. STM32F100xE specific LCD interfaces. If failure is detected. falling edge. full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal. ● ● ● ● ● ● ● ● Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency.7 Nested vectored interrupt controller (NVIC) The STM32F100xx value line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. both) and can be masked independently.9 Clocks and startup System clock selection is performed on startup. An external 4-24 MHz clock can be selected. 2. boot pins are used to select one of three boot options: ● ● ● Boot from user Flash Boot from system memory Boot from embedded SRAM 14/97 Doc ID 15081 Rev 5 . This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. The maximum frequency of the AHB and the APB domains is 24 MHz. Up to 112 GPIOs can be connected to the 16 external interrupt lines.

The voltage regulator can also be put Doc ID 15081 Rev 5 15/97 . the PLL. The device remains in reset mode when VDD is below a specified threshold.2.12 Power supply supervisor The device has an integrated power on reset (POR)/power down reset (PDR) circuitry.4 V when the ADC or DAC is used).2. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. the HSI RC and the HSE crystal oscillators are disabled. short startup time and available wakeup sources: ● Sleep mode In Sleep mode. only the CPU is stopped. VDDA and VSSA must be connected to VDD and VSS.8 V domain are stopped. external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. VPOR/PDR. low power (LPR) and power down. STM32F100xE Description The boot loader is located in System Memory.6 V: External power supply for I/Os and the internal regulator. 2. STM32F100xD. It is disabled in Standby mode. without the need for an external reset circuit. VSSA.2. 2. inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. For further details please refer to AN2606. It is always active.0 to 3. It is used to reprogram the Flash memory by using USART1. ● ● ● MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down. Reset blocks. respectively.6 V: External analog power supplies for ADC. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. DAC. Provided externally through VDD pins. VBAT = 1. providing high impedance output.13 Voltage regulator The regulator has three operation modes: main (MR). ● Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. 2.2.6 V: Power supply for RTC. RCs and PLL (minimum voltage to be applied to VDDA is 2. and ensures proper operation starting from/down to 2 V. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. VDDA = 2. The PVD is enabled by software.11 Power supply schemes ● ● VDD = 2.0 to 3.14 Low-power modes The STM32F100xx value line supports three low-power modes to achieve the best compromise between low power consumption. ● 2.STM32F100xC. All clocks in the 1. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold.8 to 3.

16/97 Doc ID 15081 Rev 5 . the HSI RC and the HSE crystal oscillators are also switched off.2. The PLL. The device can be woken up from Stop mode by any of the EXTI line. and provides an alarm interrupt and a periodic interrupt. STM32F100xD. all timers and ADC. Configuration is made by software and transfer sizes between source and destination are independent. After entering Standby mode. 2. the internal low power RC oscillator or the high-speed external clock divided by 128. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The internal voltage regulator is switched off so that the entire 1. Each channel is connected to dedicated hardware DMA requests. The EXTI line source can be one of the 16 external lines.8 V domain is powered off. The internal low power RC has a typical frequency of 40 kHz. STM32F100xE either in normal or in low power mode. resonator or oscillator. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function. Note: The RTC. 2. a IWDG reset. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. the PVD output or the RTC alarm. two basic timers and two watchdog timers.17 Timers and watchdogs The STM32F100xx devices include an advanced-control timer.Description STM32F100xC.2. general-purpose and basic timers. peripheral-to-memory and memory-to-peripheral transfers. The DMA can be used with the main peripherals: SPI. The two DMA controllers support circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. DAC. ● Standby mode The Standby mode is used to achieve the lowest power consumption. the IWDG. I2C. a rising edge on the WKUP pin.2. The device exits Standby mode when an external reset (NRST pin). USART. with support for software trigger on each channel. 2. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. It is clocked by a 32. or an RTC alarm occurs. and the corresponding clock sources are not stopped by entering Stop or Standby mode.768 kHz external crystal.16 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin.768 kHz. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32. Table 3 compares the features of the advanced-control. nine general-purpose timers.15 DMA The flexible 12-channel general-purpose DMA is able to manage memory-to-memory.

TIM17 TIM6. It has complementary PWM outputs with programmable inserted dead times. If configured as the 16-bit PWM generator. TIM14 16-bit Up No 1 No TIM15 16-bit Up Yes 2 Yes TIM16. TIM4. down. The 4 independent channels can be used for: ● ● ● ● Input capture Output compare PWM generation (edge or center-aligned modes) One-pulse mode output If configured as a standard 16-bit timer. The counter can be frozen in debug mode. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. it has the same features as the TIMx timer. TIM5 TIM12 16-bit Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 Any integer between 1 and 65536 Yes 4 No 16-bit Up No 2 No TIM13. Many features are shared with those of the standard TIM timers which have the same architecture. down. Timer Description Timer feature comparison Counter resolution 16-bit Counter type Up.STM32F100xC. it has full modulation capability (0-100%). TIM3. TIM7 16-bit Up Yes 1 Yes 16-bit Up Yes 0 No Warning: Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It can also be seen as a complete general-purpose timer. up/down Prescaler factor 16 bits DMA request Capture/compare Complementary generation channels outputs Yes 4 Yes TIM1 TIM2. STM32F100xE Table 3. up/down Up. STM32F100xD. Doc ID 15081 Rev 5 17/97 .

TIM15. TIM4. The TIM15. STM32F100xD. TIM4. TIM15 has two independent channels. whereas TIM16 and TIM17 feature one single channel for input capture/output compare. This gives up to 12 input captures/output compares/PWMs on the largest packages.. Each general-purpose timer can be used to generate PWM outputs. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock. and TIM17 have a complementary output with dead-time generation and independent DMA request generation Their counters can be frozen in debug mode. TIM16. TIM16 and TIM17 timers can work together. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. Their counters can be frozen in debug mode. These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.5. TIM13 and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM2. TIM12. STM32F100xE General-purpose timers (TIM2. TIM12. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. TIM3. The TIM2. TIM5 all have independent DMA request generation. TIM16 and TIM17 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare.. They can also be used as a generic 16-bit time base. TIM3. TIM5 general-purpose timers can work together or with the TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. TIM3. PWM or one-pulse mode output. or as a free running timer for application timeout 18/97 Doc ID 15081 Rev 5 . TIM4. it can operate in Stop and Standby modes. and TIM15 can also operate with TIM1 via the Timer Link feature for synchronization or event chaining. TIM15. TIM5 STM32F100xx devices feature four synchronizable 4-channel general-purpose timers.17) There are ten synchronizable general-purpose timers embedded in the STM32F100xx devices (see Table 3 for differences). Their counters can be frozen in debug mode. PWM or one-pulse mode output. whereas TIM16 and TIM17 feature one single channel for input capture/output compare. It can be used as a watchdog to reset the device when a problem occurs.Description STM32F100xC. TIM15 can be synchronized with TIM16 and TIM17. TIM12 has two independent channels. or as simple time base. PWM or onepulse mode output. TIM2.

STM32F100xE Description management. and UART5). SysTick timer This timer is dedicated for OS. It is clocked from the main clock.20 Universal asynchronous receiver transmitter (UART) The STM32F100xx value line embeds 2 universal asynchronous receiver transmitters (UART4. the multiprocessor communication mode. Doc ID 15081 Rev 5 19/97 . It has an early warning interrupt capability and the counter can be frozen in debug mode.2.STM32F100xC. The available UART interfaces support IrDA SIR ENDEC. STM32F100xD. A hardware CRC generation/verification is embedded. The counter can be frozen in debug mode. The available USART interfaces communicate at up to 3 Mbit/s.2.2. the single-wire half-duplex communication mode and have LIN Master/Slave capability. Programmable clock source 2. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. They provide hardware management of the CTS and RTS signals.19 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F100xx value line embeds three universal synchronous/asynchronous receiver transmitters (USART1. It can support standard and fast modes.18 I²C bus The I²C bus interface can operate in multimaster and slave modes. It features: ● ● ● ● A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. 2. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. The interface can be served by DMA and it supports SM Bus 2.0/PM Bus. The UART interfaces can be served by the DMA controller. the multiprocessor communication mode. It can be used as a watchdog to reset the device when a problem occurs. the single-wire half-duplex communication mode and have LIN Master/Slave capability. 2. they support IrDA SIR ENDEC. but could also be used as a standard down counter. USART2 and USART3). It is hardware or software configurable through the option bytes. The USART interfaces can be served by the DMA controller.

This protocol provides high-level control functions between all audiovisual products in an environment. 2. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. See the STM32F100xx reference manual for software considerations. STM32F100xE 2. alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable.24 ADC (analog-to-digital converter) The 12-bit analog to digital converter has up to 16 external channels and performs conversions in single-shot or scan modes.2.2. In scan mode. automatic conversion is performed on a selected group of analog inputs. For details refer to Table 4: High-density STM32F100xx pin definitions. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2. The SPIs can be served by the DMA controller. An interrupt is generated when the converted voltage is outside the programmed thresholds. as input (with or without pull-up or pull-down) or as peripheral alternate function. An analog watchdog feature allows very precise monitoring of the converted voltage of one.2.21 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 12 Mbit/s in slave and master modes in fullduplex and simplex communication modes. It is specified to operate at low speeds with minimum processing and memory overhead. The ADC can be served by the DMA controller. Indeed.23 Remap capability This feature allows the use of a maximum number of peripherals in a given application. 2. some or all selected channels. Most of the GPIO pins are shared with digital or analog alternate functions.2. STM32F100xD. All GPIOs are high currentcapable except for analog inputs. This has the advantage of making board design and port usage much more flexible. 20/97 Doc ID 15081 Rev 5 . it shows the list of remappable alternate functions and the pins onto which they can be remapped.22 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain).Description STM32F100xC. HDMI (high-definition multimedia interface) consumer electronics control (CEC) The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard).

The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. STM32F100xE Description 2. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. STM32F100xD.2.2. The conversion range is between 2 V < VDDA < 3.STM32F100xC. This dual digital Interface supports the following features: ● ● ● ● ● ● ● ● ● ● two DAC converters: one for each output channel up to 10-bit output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual DAC channels’ independent or simultaneous conversions DMA capability for each channel external triggers for conversion input voltage reference VREF+ Eight DAC trigger inputs are used in the STM32F100xx.26 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.2.6 V.27 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. The chosen design structure is composed of integrated resistor strings and an amplifier in noninverting configuration. Doc ID 15081 Rev 5 21/97 .25 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. 2.

Pinouts and pin descriptions STM32F100xC. Pinouts and pin descriptions STM32F100xx value line LQFP144 pinout VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 LQFP144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD_2 VSS_2 NC PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD_9 VSS_9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD_8 VSS_8 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 VSS_6 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 ai14667 22/97 Doc ID 15081 Rev 5 . STM32F100xE 3 Figure 3. STM32F100xD.

STM32F100xD. STM32F100xx value line LQFP100 pinout Pinouts and pin descriptions PE2 PE3 PE4 PE5 PE6 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai14391 Doc ID 15081 Rev 5 23/97 . STM32F100xE Figure 4.STM32F100xC.

Pinouts and pin descriptions Figure 5. STM32F100xC. STM32F100xE STM32F100xx value line in LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14392 Table 4. Pins LQFP144 LQFP100 LQFP64 High-density STM32F100xx pin definitions I / O Level(2) Alternate functions(4) Main function(3) (after reset) PE2 PE3 PE4 PE5 PE6 VBAT PC13(6) PC14(6) PC15(6) PF0 PF1 PF2 PF3 PF4 TAMPER-RTC OSC32_IN OSC32_OUT FSMC_A0 FSMC_A1 FSMC_A2 FSMC_A3 FSMC_A4 Type(1) Pin name Default TRACECK/ FSMC_A23 TRACED0/FSMC_A19 TRACED1/FSMC_A20 TRACED2/FSMC_A21 TRACED3/FSMC_A22 Remap 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 - 1 2 3 4 - PE2 PE3 PE4 PE5 PE6 VBAT I/O I/O I/O I/O I/O S FT FT FT FT FT PC13-TAMPERI/O RTC(5) PC14OSC32_IN(5) I/O PC15I/O OSC32_OUT(5) PF0 PF1 PF2 PF3 PF4 I/O FT I/O FT I/O FT I/O FT I/O FT 24/97 Doc ID 15081 Rev 5 . STM32F100xD.

STM32F100xC. STM32F100xD. STM32F100xE Table 4. Pins LQFP144 LQFP100 LQFP64 Pin name Type(1) Pinouts and pin descriptions High-density STM32F100xx pin definitions (continued) I / O Level(2) Alternate functions(4) Main function(3) (after reset) PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA WKUP/USART2_CTS(7) ADC1_IN0 TIM2_CH1_ETR TIM5_CH1 USART2_RTS(7) ADC1_IN1/ TIM5_CH2/TIM2_CH2(7) USART2_TX(7)/TIM5_CH3 ADC1_IN2/ TIM15_CH1 TIM2_CH3 (7) USART2_RX(7)/TIM5_CH4 ADC1_IN3/TIM2_CH4(7) / TIM15_CH2 ADC1_IN10 ADC1_IN11 ADC1_IN12 ADC1_IN13 FSMC_NIORD FSMC_NREG FSMC_NIOWR FSMC_CD FSMC_INTR Default FSMC_A5 Remap 15 - 5 6 7 8 9 PF5 VSS_5 VDD_5 PF6 PF7 PF8 PF9 PF10 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA I/O FT S S I/O I/O I/O I/O I/O I O I/O I/O I/O I/O I/O S S S S 16 10 17 11 18 19 20 21 22 - 23 12 24 13 25 14 26 15 27 16 28 17 10 29 18 11 30 19 12 31 20 32 21 - 33 22 13 34 23 14 PA0-WKUP I/O PA0 35 24 15 PA1 I/O PA1 36 25 16 PA2 I/O PA2 37 26 17 38 27 18 39 28 19 PA3 VSS_4 VDD_4 I/O S S PA3 VSS_4 VDD_4 Doc ID 15081 Rev 5 25/97 .

STM32F100xD. STM32F100xE High-density STM32F100xx pin definitions (continued) I / O Level(2) Alternate functions(4) Main function(3) (after reset) Default SPI1_NSS(7)/ USART2_CK(7) DAC_OUT1/ADC1_IN4 SPI1_SCK(7) DAC_OUT2/ADC2_IN5 SPI1_MISO(7)/ ADC1_IN6 / TIM3_CH1(7) SPI1_MOSI(7)/ ADC1_IN7 / TIM3_CH2(7) ADC1_IN14 / TIM12_CH1 ADC1_IN15 / TIM12_CH2 ADC1_IN8/TIM3_CH3 Remap 40 29 20 PA4 I/O PA4 41 30 21 PA5 I/O PA5 42 31 22 PA6 I/O PA6 TIM1_BKIN / TIM16_CH1 TIM1_CH1N/ TIM17_CH1 43 32 23 44 33 24 45 34 25 46 35 26 47 36 27 48 37 28 49 50 51 52 53 54 55 56 57 - PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 I/O I/O I/O I/O I/O PA7 PC4 PC5 PB0 PB1 TIM1_CH2N / TIM13_CH1 TIM1_CH3N / TIM14_CH1 ADC1_IN9/TIM3_CH4(7) I/O FT PB2/BOOT1 I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS_7 VDD_7 PE10 PE11 PE12 PE13 FSMC_D7 FSMC_D8 FSMC_D9 FSMC_D10 TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 FSMC_A7 FSMC_A8 FSMC_A9 FSMC_A10 FSMC_A11 FSMC_D4 FSMC_D5 FSMC_D6 TIM1_ETR TIM1_CH1N TIM1_CH1 FSMC_A6 58 38 59 39 60 40 61 62 - 63 41 64 42 65 43 66 44 26/97 Doc ID 15081 Rev 5 . Pins LQFP144 LQFP100 LQFP64 Pin name Type(1) STM32F100xC.Pinouts and pin descriptions Table 4.

Pins LQFP144 LQFP100 LQFP64 Pin name Type(1) Pinouts and pin descriptions High-density STM32F100xx pin definitions (continued) I / O Level(2) Alternate functions(4) Main function(3) (after reset) PE14 PE15 PB10 PB11 VSS_1 VDD_1 SPI2_NSS/ I2C2_SMBA/ USART3_CK(7)/ TIM1_BKIN(7) SPI2_SCK/ USART3_CTS(7)/ TIM1_CH1N SPI2_MISO/TIM1_CH2N USART3_RTS(7)/ SPI2_MOSI/ TIM1_CH3N(7)/ FSMC_D13 FSMC_D14 FSMC_D15 FSMC_A16 FSMC_A17 FSMC_A18 Default FSMC_D11 FSMC_D12 I2C2_SCL/USART3_TX(7) I2C2_SDA/USART3_RX(7) Remap TIM1_CH4 TIM1_BKIN TIM2_CH3 / HDMI_CEC TIM2_CH4 67 45 68 46 - PE14 PE15 PB10 PB11 VSS_1 VDD_1 I/O FT I/O FT I/O FT I/O FT S S 69 47 29 70 48 30 71 49 31 72 50 32 73 51 33 PB12 I/O FT PB12 TIM12_CH1 74 52 34 PB13 I/O FT PB13 TIM12_CH2 75 53 35 76 54 36 77 55 78 56 79 57 80 58 81 59 82 60 83 84 - PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PB14 PB15 PD8 PD9 PD10 PD11 PD12 PD13 VSS_8 VDD_8 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PG8 TIM15_CH1 TIM15_CH2 USART3_TX USART3_RX USART3_CK USART3_CTS TIM4_CH1 / USART3_RTS TIM4_CH2 85 61 86 62 87 88 89 90 91 92 93 - FSMC_D0 FSMC_D1 FSMC_A12 FSMC_A13 FSMC_A14 FSMC_A15 TIM4_CH3 TIM4_CH4 Doc ID 15081 Rev 5 27/97 . STM32F100xD. STM32F100xE Table 4.STM32F100xC.

Pinouts and pin descriptions Table 4. STM32F100xD. Pins LQFP144 LQFP100 LQFP64 Pin name Type(1) STM32F100xC. STM32F100xE High-density STM32F100xx pin definitions (continued) I / O Level(2) Alternate functions(4) Main function(3) (after reset) VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 TIM13_CH1 TIM14_CH1 USART1_CK/ TIM1_CH1(7)/MCO USART1_TX(7)/ TIM1_CH2(7) / TIM15_BKIN USART1_RX(7)/ TIM1_CH3(7) / TIM17_BKIN USART1_CTS / TIM1_CH4(7) USART1_RTS / TIM1_ETR(7) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 Default Remap 94 95 - - VSS_9 VDD_9 PC6 PC7 PC8 PC9 PA8 S S I/O FT I/O FT I/O FT I/O FT I/O FT 96 63 37 97 64 38 98 65 39 99 66 40 100 67 41 101 68 42 PA9 I/O FT PA9 102 69 43 PA10 I/O FT PA10 103 70 44 104 71 45 105 72 46 106 73 - PA11 PA12 PA13 I/O FT I/O FT I/O FT PA11 PA12 JTMSSWDIO Not connected 107 74 47 108 75 48 109 76 49 110 77 50 111 78 51 112 79 52 113 80 53 114 81 115 82 5 6 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT VSS_2 VDD_2 JTCKSWCLK JTDI PC10 PC11 PC12 OSC_IN(8) SPI3_NSS UART4_TX UART4_RX UART5_TX FSMC_D2(9) FSMC_D3(9) TIM3_ETR/UART5_RX FSMC_CLK FSMC_NOE FSMC_NWE USART2_CTS USART2_RTS USART2_TX TIM2_CH1_ETR / SPI1_NSS USART3_TX USART3_RX USART3_CK I/O FT OSC_OUT(8) I/O FT I/O FT I/O FT I/O FT PD2 PD3 PD4 PD5 116 83 54 117 84 118 85 119 86 - 28/97 Doc ID 15081 Rev 5 .

I = input. S = supply. Doc ID 15081 Rev 5 29/97 . O = output.STM32F100xC. STM32F100xE Table 4. Pins LQFP144 LQFP100 LQFP64 Pin name Type(1) Pinouts and pin descriptions High-density STM32F100xx pin definitions (continued) I / O Level(2) Alternate functions(4) Main function(3) (after reset) VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 JTDO SPI3_SCK PB3/TRACESWO TIM2_CH2 / SPI1_SCK TIM3_CH1 SPI1_MISO TIM3_CH2 / SPI1_MOSI USART1_TX FSMC_NE4 FSMC_A24 FSMC_A25 FSMC_NWAIT FSMC_NE1 FSMC_NE2 FSMC_NE3 USART2_RX USART2_CK Default Remap 120 121 122 87 123 88 124 125 126 127 128 129 130 131 132 - - VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 PB3/ S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT S S I/O FT I/O FT 133 89 55 134 90 56 135 91 57 136 92 58 PB4 PB5 PB6 I/O FT I/O I/O FT NJTRST PB5 PB6 SPI3_MISO I2C1_SMBA/ SPI3_MOSI TIM16_BKIN I2C1_SCL(7)/ TIM4_CH1(7) / TIM16_CH1N I2C1_SDA(7) / FSMC_NADV / TIM4_CH2(7) / TIM17_CH1N 137 93 59 PB7 I/O FT PB7 USART1_RX 138 94 60 139 95 61 140 96 62 141 97 142 98 - BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 I I/O FT I/O FT I/O FT I/O FT S S BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 TIM4_CH3(7)/TIM16_CH1 / HDMI_CEC TIM4_CH4(7)/ TIM17_CH1 TIM4_ETR / FSMC_NBL0 FSMC_NBL1 I2C1_SCL/ CAN_RX I2C1_SDA / CAN_TX 143 99 63 144 100 64 1. STM32F100xD.

com. FT = 5 V tolerant. it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). Pins FSMC pin definition FSMC NOR/PSRAM/SRAM NOR/PSRAM Mux A23 A19 A20 A21 A22 Yes Yes Yes Yes Yes A6 A7 LQFP100(1) PE2 PE3 PE4 PE5 PE6 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PF8 PF9 PF10 PF11 PF12 PF13 A23 A19 A20 A21 A22 A0 A1 A2 A3 A4 A5 30/97 Doc ID 15081 Rev 5 . Table 5. 4. the FSMC function is not available. Later on. available from the STMicroelectronics website: www. refer to the Battery backup domain and BKP register description sections in the STM32F100xx reference manual. PD0 and PD1 are available by default. so there is no need for remapping. to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 6. 3. This alternate function can be remapped by software to some other port pins (if available on the used package). STM32F100xE 2. For the LQFP100 and LQFP144 packages. 5. For more details. however the functionality of PD0 and PD1 can be remapped by software on these pins.st.st. available from the STMicroelectronics website: www. refer to the Alternate function I/O and debug configuration section in the STM32F100xx reference manual. 7. Function availability depends on the chosen device. the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e. the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset. 8. For the LQFP64 package.Pinouts and pin descriptions STM32F100xC. For details on how to manage these IOs.com. PC13. If several peripherals share the same I/O pin. For more details. to drive an LED).g. Since the switch only sinks a limited amount of current (3 mA). 9. PC14 and PC15 are supplied through the power switch. For devices delivered in LQFP64 packages. Main function after the first backup domain power-up. refer to Alternate function I/O and debug configuration section in the STM32F100xx reference manual. STM32F100xD.

STM32F100xD. STM32F100xE Table 5. Pins NOR/PSRAM/SRAM PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PG2 PG3 PG4 PG5 PG6 PG7 PD0 PD1 PD3 PD4 PD5 PD6 D2 D3 CLK NOE NWE NWAIT DA2 DA3 CLK NOE NWE NWAIT A8 A9 A10 A11 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A16 A17 A18 D0 D1 A12 A13 A14 A15 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DA14 DA15 A16 A17 A18 DA0 DA1 Pinouts and pin descriptions FSMC pin definition (continued) FSMC NOR/PSRAM Mux Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes LQFP100(1) Doc ID 15081 Rev 5 31/97 .STM32F100xC.

32/97 Doc ID 15081 Rev 5 . STM32F100xD. Ports F and G are not available in devices delivered in 100-pin packages. STM32F100xE FSMC pin definition (continued) FSMC NOR/PSRAM Mux NE1 NE2 NE3 Yes NE4 A24 A25 NADV NBL0 NBL1 Yes Yes Yes LQFP100(1) 1. Pins NOR/PSRAM/SRAM PD7 PG9 PG10 PG11 PG12 PG13 PG14 PB7 PE0 PE1 NE4 A24 A25 NADV NBL0 NBL1 NE1 NE2 NE3 STM32F100xC.Memory mapping Table 5. 4 Memory mapping The memory map is shown in Figure 6.

STM32F100xC. STM32F100xD. Memory map APB memory space 0xFFFF FFFF 0x4002 3400 0x4002 3000 0x4002 2400 0xFFFF FFFF 0x4002 2000 0x4002 1400 0x4002 1000 7 0xE010 0000 Cortex-M3 internal peripherals 0xE000 0000 0x4002 0400 0x4002 0000 0x4001 4C00 0x4001 4800 6 0x4001 4400 0x4001 4000 0xC000 0000 0x4001 3C00 0x4001 3800 0x4001 3400 5 FSMC regs 0x4001 3000 0x4001 2C00 0xA000 0000 0x4001 2800 0x4001 2400 0x4001 2000 4 0x1FFF FFFF 0x1FFF F80F 0x8000 0000 0x1FFF F800 0x7000 0000 FSMC external memory 0x1FFF F000 System memory Option Bytes reserved 0x4001 1C00 0x4001 1800 0x4001 1400 0x4001 1000 0x4001 0C00 3 0x4001 0800 0x4001 0400 0x4001 0000 0x4000 7C00 0x4000 7800 2 Peripherals reserved 0x4000 7400 0x4000 7000 0x4000 6C00 0x4000 5C00 1 SRAM 0x0801 FFFF 0x4000 5800 0x4000 5400 0x4000 5000 0x4000 4C00 0x4000 4800 0 0x0800 0000 0x0000 0000 Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins Flash memory 0x4000 4400 0x4000 3C00 0x4000 3800 0x4000 3400 0x4000 3000 0x4000 2C00 0x4000 2800 0x4000 2000 0x4000 1C00 0x4000 1800 0x4000 1400 0x4000 1000 0x4000 0C00 0x4000 0800 0x4000 0400 0x4000 0000 USART1 reserved SPI1 TIM1 reserved ADC1 Port G Port F Port E Port D Port C Port B Port A EXTI AFIO reserved CEC DAC PWR BKP I2C2 reserved I2C1 UART5 UART4 USART3 USART2 SPI3 SPI2 reserved IWDG WWDG RTC TIM14 TIM13 TIM12 TIM7 TIM6 TIM5 TIM4 TIM3 TIM2 ai18400 reserved CRC reserved Flash interface reserved RCC DMA2 DMA1 reserved TIM17 TIM16 TIM15 reserved 0x6000 0000 0x4000 0000 0x2000 0000 Reserved Doc ID 15081 Rev 5 33/97 . STM32F100xE Figure 6.

VDD = 3. They are given only as design guidelines and are not tested.2 Typical values Unless otherwise specified.6 V voltage range). design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range.Electrical characteristics STM32F100xC. Data based on characterization results.1.1. 5. Based on characterization. all voltages are referenced to VSS. STM32F100xD.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature.1.1.3 Typical curves Unless otherwise specified.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8.3 V (for the 2 V ≤ VDD ≤ 3. 5. supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). STM32F100xE 5 5.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7. where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5. the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).1. all typical curves are given only as design guidelines and are not tested.1 Electrical characteristics Parameter conditions Unless otherwise specified. typical data are based on TA = 25 °C. 34/97 Doc ID 15081 Rev 5 . 5. 5.

Wake-up logic Backup registers) Level shifter OUT GP I/Os IN IO Logic Kernel logic (CPU. . Doc ID 15081 Rev 5 35/97 . Pin loading conditions Figure 8. STM32F100xD.STM32F100xC. Pin input voltage STM32F10xxx pin C = 50 pF VIN STM32F10xxx pin ai14123b ai14124b 5.RTC.1..8-3. Digital & Memories) VDD VDD 1/2/3/4/5 VSS Regulator 5 × 100 nF + 1 × 4.. STM32F100xE Electrical characteristics Figure 7. Power supply scheme VBAT 1. Caution: In Figure 9.6V Po wer swi tch Backup circuitry (OSC32K. the 4.7 µF capacitor must be connected to VDD3.6 Power supply scheme Figure 9. PLL.7 μF VDD VREF 1/2/3/4/5 VDDA VREF+ VREFVSSA 10 nF + 1 μF 10 nF + 1 μF Analog: RCs.

Electrical characteristics STM32F100xC. VSSA) pins must always be connected to the external power supply. VIN maximum must always be respected. These are stress ratings only and functional operation of the device at these conditions is not implied. All main power (VDD.0 50 mV 50 see Section 5. and Table 8: Thermal characteristics may cause permanent damage to the device.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.0 4.3 VSS − 0.0 VDD + 4. in the permitted range. STM32F100xE 5.1.3. Refer to Table 7: Current characteristics for the maximum allowed injected current values. STM32F100xD. Exposure to maximum rating conditions for extended periods may affect device reliability.12: Absolute maximum ratings (electrical sensitivity) V Unit VESD(HBM) 1.3 Max 4.3 VSS − 0. Table 7: Current characteristics. Symbol VDD − VSS VIN(2) |ΔVDDx| |VSSX − VSS| Voltage characteristics Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin Input voltage on any other pin Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min –0. 2. VDDA) and ground (VSS.7 Current consumption measurement Figure 10. 36/97 Doc ID 15081 Rev 5 . Table 6.

4. Symbol IVDD IVSS IIO IINJ(PIN)(2) ΣIINJ(PIN) Electrical characteristics Current characteristics Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink) (1) Max. in the permitted range. When several inputs are submitted to a current injection.STM32F100xC. Table 8. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. See Note: on page 82.6 V V MHz Unit VDDA (1) VBAT Doc ID 15081 Rev 5 37/97 .3. 5.6 V 3.3 5. 150 150 25 −25 +5 / –0 ±5 (5) Unit Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on five volt tolerant pins Injected current on any other pin (4) (3) mA Total injected current (sum of all I/O and control pins) ± 25 1. the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).8 Max 24 24 24 3.4 1.6 3.6 3. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. Thermal characteristics Ratings Storage temperature range Maximum junction temperature Value –65 to +150 150 Unit °C °C Symbol TSTG TJ 5. A negative injection is induced by VIN<VSS. Symbol fHCLK fPCLK1 fPCLK2 VDD General operating conditions Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage Conditions Min 0 0 0 2 2 Must be the same potential as VDD 2. All main power (VDD. STM32F100xE Table 7. IINJ(PIN) must never be exceeded. Positive injection is not possible on these I/Os.1 Operating conditions General operating conditions Table 9. Refer to Table 6: Voltage characteristics for the maximum allowed input voltage values. VSSA) pins must always be connected to the external power supply. 2. STM32F100xD. 3. IINJ(PIN) must never be exceeded. VDDA) and ground (VSS.

2: Thermal characteristics on page 92). STM32F100xE General operating conditions (continued) Parameter Power dissipation at TA = 85 °C for suffix 6 or TA = 105 °C for suffix 7(2) Ambient temperature for 6 suffix version Conditions LQFP144 LQFP100 LQFP64 Maximum power dissipation Low power dissipation (3) Min Max TBD TBD TBD Unit PD mW –40 –40 –40 –40 –40 –40 85 °C 105 105 °C 125 105 °C 125 TA Ambient temperature for 7 suffix version TJ Junction temperature range 7 suffix version 1.2: Thermal characteristics on page 92). If TA is lower. 3. When the ADC is used. 2. Symbol tVDD Operating conditions at power-up / power-down Parameter VDD rise time rate VDD fall time rate Min 0 20 Max Unit µs/V ∞ ∞ 38/97 Doc ID 15081 Rev 5 . refer to Table 51: ADC characteristics.Electrical characteristics Table 9. Maximum power dissipation Low power dissipation 6 suffix version (3) 5.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA. higher PD values are allowed as long as TJ does not exceed TJmax (see Section 6. In low power dissipation state. STM32F100xD. TA can be extended to this range as long as TJ does not exceed TJmax (see Section 6. Symbol STM32F100xC.3. Table 10.

STM32F100xC, STM32F100xD, STM32F100xE

Electrical characteristics

5.3.3

Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 11.
Symbol
.

Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.1 2 2.19 2.09 2.28 2.18 2.38 2.28 2.47 2.37 2.57 2.47 2.66 2.56 2.76 2.66 Typ 2.18 2.08 2.28 2.18 2.38 2.28 2.48 2.38 2.58 2.48 2.68 2.58 2.78 2.68 2.88 2.78 100 Falling edge Rising edge 1.8(1) 1.84 1.88 1.92 40 1.5 2.5 4.5 1.96 2.0 Max 2.26 2.16 2.37 2.27 2.48 2.38 2.58 2.48 2.69 2.59 2.79 2.69 2.9 2.8 3 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms

VPVD

Programmable voltage detector level selection

PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)

VPVDhyst(2) VPOR/PDR VPDRhyst
(2)

PVD hysteresis Power on/power down reset threshold PDR hysteresis Reset temporization

tRSTTEMPO(2)

1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. 2. Guaranteed by design, not tested in production.

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Electrical characteristics

STM32F100xC, STM32F100xD, STM32F100xE

5.3.4

Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12.
Symbol VREFINT

Embedded internal reference voltage
Parameter Internal reference voltage Conditions –40 °C < TA < +105 °C –40 °C < TA < +85 °C Min 1.16 1.16 Typ 1.20 1.20 5.1 Max 1.26 1.24 17.1(2) Unit V V µs

ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) Temperature coefficient VDD = 3 V ±10 mV

10 100

mV ppm/°C

1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production.

5.3.5

Supply current characteristics
The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 10: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code.

Maximum current consumption
The MCU is placed under the following conditions:
● ● ● ●

All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK

The parameters given in Table 13 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9.

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STM32F100xC, STM32F100xD, STM32F100xE Table 13.

Electrical characteristics

Maximum current consumption in Run mode, code with data processing running from Flash
Max(1) Parameter Conditions fHCLK TA = 85 °C 24 MHz External clock (2), all peripherals enabled 16 MHz 8 MHz 24 MHz External clock(2), all peripherals disabled 16 MHz 8 MHz 24 MHz HSI clock(2), all peripherals enabled 16 MHz 8 MHz 24 MHz HSI clock(2), all peripherals disabled 16 MHz 8 MHz 19.7 14.6 8.2 11.3 8.7 5.6 19 13.1 10.1 9.4 6.7 5.4 TA = 105 °C 20 14.7 8.6 11.6 8.9 6 mA 19 13.2 10.1 9.6 7 5.6 Unit

Symbol

IDD

Supply current in Run mode

1. Based on characterization, not tested in production. 2. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.

Table 14.

Maximum current consumption in Run mode, code with data processing running from RAM
Max(1) Parameter Conditions fHCLK TA = 85 °C 24 MHz External clock (2), all peripherals enabled 16 MHz 8 MHz 24 MHz External clock(2) all peripherals disabled 16 MHz 8 MHz 24 MHz HSI clock(2), all peripherals enabled 16 MHz 8 MHz 24 MHz HSI clock(2), all peripherals disabled 16 MHz 8 MHz 18.5 13.1 7.3 8.4 7.3 4.8 17.2 11.7 8.9 8.1 5.6 4.3 TA = 105 °C 19 13.5 7.6 8.5 7.7 5.2 mA 17.2 11.8 9 8.3 5.8 4.5 Unit

Symbol

IDD

Supply current in Run mode

1. Based on characterization, tested in production at VDD max, fHCLK max. 2. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.

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3 1.6 4.2 6.1 3.2 3. all peripherals disabled 16 MHz 8 MHz 14.3 10.9 12.7 1.3 6.1 9.4 2. STM32F100xC.7 5. tested in production at VDD max and fHCLK max with peripherals enabled. 2. Based on characterization.7 2. 42/97 Doc ID 15081 Rev 5 . code running from Flash or RAM Max(1) Parameter Conditions fHCLK TA = 85 °C 24 MHz External clock(2) all peripherals enabled 16 MHz 8 MHz 24 MHz External clock(2).5 2 1.5 8.9 4.6 2.Electrical characteristics Table 15. all peripherals disabled 16 MHz 8 MHz 24 MHz HSI clock(2).4 mA 12.2 4. External clock or HSI frequency is 8 MHz and PLL is on when fHCLK > 8 MHz.4 TA = 105 °C 14. STM32F100xD. STM32F100xE STM32F100xxB maximum current consumption in Sleep mode.7 8.5 6.7 Unit Symbol IDD Supply current in Sleep mode 1. all peripherals enabled 16 MHz 8 MHz 24 MHz HSI clock(2).

Symbol Electrical characteristics Typical and maximum current consumptions in Stop and Standby modes Typ(1) Parameter Conditions Max Unit VDD/VBAT VDD/ VBAT VDD/VBAT TA = TA = = 2.3 Typical current consumption The MCU is placed under the following conditions: ● ● ● All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned When the peripherals are enabled fPCLK1 = fHCLK/4.1 µA 2. fADCCLK = fPCLK2/4 The parameters given in Table 17 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9.4 V = 3. independent watchdog OFF in Standby mode Low-speed internal RC oscillator and independent watchdog OFF. STM32F100xD.0 V = 2. 31 320 670 24 305 650 IDD 3.2 3. Low-speed and high-speed internal RC oscillators and highspeed oscillator OFF (no Supply current independent watchdog) in Stop mode Regulator in Low-Power mode.3 V 85 °C 105 °C Regulator in Run mode. low-speed oscillator and RTC OFF Backup Low-speed oscillator and RTC IDD_VBAT domain supply ON current 1. Low-speed and high-speed internal RC oscillators and highspeed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator Supply current ON. Doc ID 15081 Rev 5 43/97 .4 2 2. Typical values are measured at TA = 25 °C.2 1. fPCLK2 = fHCLK/2.2 3.9 5.0 1. STM32F100xE Table 16.7 1.STM32F100xC.

3 5. An 8 MHz crystal is used as the external clock source.8 mA for the ADC and of 0. mA 8. STM32F100xE Typical current consumption in Run mode.1 24 MHz 16 MHz 8 MHz Running on high-speed external clock with an 8 MHz crystal(3) 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Run mode 125 kHz 24 MHz 16 MHz 8 MHz Running on high-speed internal RC (HSI) 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 1. the PLL is used when fHCLK > 8 MHz. 3.3 1.7 1.1 0.45 2.2 3. VDD = 3. STM32F100xD. code with data processing running from Flash Typical values(1) Conditions fHCLK Unit Symbol Parameter All peripherals All peripherals enabled(2) disabled 14.8 0. STM32F100xC.6 2.55 2.Electrical characteristics Table 17.5 mA for the DAC analog part. In applications.7 1.46 1.85 4.65 1.4 9. Add an additional power consumption of 0.85 1.7 0. this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).6 9.1 1. Typical values are measures at TA = 25 °C.3 V.4 1. 44/97 Doc ID 15081 Rev 5 .15 13.1 10 5.3 0. The AHB prescaler is used to reduce the frequency when fHCLK < 8 MHz.95 1.2 2.5 6.8 3.05 2.7 6.3 1.9 0.

Doc ID 15081 Rev 5 45/97 . mA 2.3 1.65 0.1 0.2 1.15 1. this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).75 0. An 8 MHz crystal is used as the external clock source. 3.1 1.3 2. Typical values are measures at TA = 25 °C.6 0. code running from Flash or RAM Typical values(1) Conditions fHCLK Unit Symbol Parameter All peripherals All peripherals enabled(2) disabled 8.1 1.1 3.8 mA for the ADC and of 0. Electrical characteristics Typical current consumption in Sleep mode.49 0.53 2. VDD = 3.7 6.07 1. Add an additional power consumption of 0.5 2.1 8 5.65 1.75 2.7 1.5 0.05 24 MHz 16 MHz 8 MHz Running on high-speed external clock with an 8 MHz crystal(3) 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Sleep mode 125 kHz 24 MHz 16 MHz 8 MHz Running on high-speed internal RC (HSI) 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 1.STM32F100xC.5 0. The AHB prescaler is used to reduce the frequency when fHCLK > 8 MHz.15 1.5 mA for the DAC analog part. STM32F100xE Table 18.25 1.47 2. the PLL is used when fHCLK > 8 MHz.8 0.35 1.2 1. STM32F100xD.65 1.55 0. In applications.3 V.

25 1.2 0.2 Unit Table 19.Electrical characteristics STM32F100xC.48 0.36 0.36 0.49 0.34 0.15 0.25 0.32 0.2 0. The MCU is placed under the following conditions: ● ● ● all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption – – with all peripherals clocked off with only one peripheral clocked on ● ambient operating temperature and VDD supply voltage conditions summarized in Table 6. STM32F100xD.48 0. STM32F100xE On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. Peripheral current consumption Peripheral TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 DAC Typical consumption at 25 °C(1) 0.19 0.36 0.06(2) mA WWDG SPI2 SPI3 USART2 USART3 UART4 UART5 I2C1 I2C2 HDMI CEC 0.35 0.48 0. APB1 46/97 Doc ID 15081 Rev 5 .2 0.34 0.

Table 20.26 0.43 0.25 Unit mA 1.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source. default prescaler value for each peripheral.34 1.26 0.7VDD VSS 5 ns 20 pF Typ 8 Max 24 VDD V 0.34 0.24 0.26 0.28 0.3VDD Unit MHz Doc ID 15081 Rev 5 47/97 .37 0. Specific conditions for ADC: fHCLK = 24 MHz.63 0. Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) High-speed external user clock characteristics Parameter User external clock source frequency(1) OSC_IN input pin high level voltage(1) OSC_IN input pin low level voltage(1) OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) 5 Conditions Min 1 0.3. and under the ambient temperature and supply voltage conditions summarized in Table 9. fADCCLK = fAPB2/2. STM32F100xE Table 19. STM32F100xD. ADON bit in the ADC_CR2 register is set to 1. Peripheral current consumption (continued) Peripheral GPIO A GPIO B GPIO C GPIO D GPIO E GPIO F GPIO G APB2 ADC1 SPI1 USART1 TIM1 TIM15 TIM16 TIM17 (3) Electrical characteristics Typical consumption at 25 °C(1) 0.2 0.26 0. 3.26 0. fAPB1 = fAPB2 = fHCLK. fHCLK = fAPB1 = fAPB2 = 24 MHz. Specific conditions for DAC: EN1 bit in DAC_CR register set to 1. 5.STM32F100xC. 2.

48/97 Doc ID 15081 Rev 5 . Guaranteed by design.Electrical characteristics Table 20. Symbol DuCy(HSE) Duty cycle IL STM32F100xC. Table 21. STM32F100xD. Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source. not tested in production. Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE) Low-speed external user clock characteristics Parameter User external clock source frequency(1) OSC32_IN input pin high level voltage(1) OSC32_IN input pin low level voltage(1) OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) 5 30 VSS ≤ VIN ≤ VDD 70 ±1 0. not tested in production. and under the ambient temperature and supply voltage conditions summarized in Table 9. Guaranteed by design. STM32F100xE High-speed external user clock characteristics Parameter (1) Conditions Min 45 Typ Max 55 ±1 Unit % µA OSC_IN Input leakage current VSS ≤ VIN ≤ VDD 1.7VDD VSS 450 ns 50 pF % µA Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz OSC32_IN input capacitance(1) DuCy(LSE) Duty cycle(1) IL OSC32_IN Input leakage current 1.

Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency. STM32F100xD. In the application. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t External clock source fLSE_ext OSC32_IN IL STM32F10xxx ai14140c High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator oscillator. Doc ID 15081 Rev 5 49/97 . the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t External clock source fHSE_ext OSC _IN IL STM32F10xxx ai14127b Figure 12. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. STM32F100xE Electrical characteristics Figure 11. accuracy). package.STM32F100xC.

it is recommended to take this point into account if the MCU is used in tough humidity conditions. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment. not tested in production.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. accuracy).3 V VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 24 Unit MHz kΩ pF 1 mA mA/V ms 1. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency. 5. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator CL2 REXT(1) OSC_OU T RF Bias controlled gain STM32F10xxx ai14128b fHSE 1. STM32F100xE HSE 4-24 MHz oscillator characteristics(1)(2) Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) HSE driving current Oscillator transconductance Startup time RS = 30 Ω VDD = 3. 50/97 Doc ID 15081 Rev 5 . tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. and selected to match the requirements of the crystal or resonator. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. REXT value depends on the crystal characteristics. 3. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. are usually the same size. package. 2. However. It is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ. the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 13.Electrical characteristics Table 22.). Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32. CL1 and CL2. STM32F100xD. 4. In the application. Based on characterization. Symbol fOSC_IN RF CL1 CL2(3) i2 gm tSU(HSE) (5) STM32F100xC. designed for high-frequency applications. due to the induced leakage and the bias condition change. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

3. CL1 and CL2. STM32F100xD.5 2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. it is between 2 pF and 7 pF.768 kHz)(1) Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator transconductance TA = 50 °C TA = 25 °C TA = 10 °C RS = 30 KΩ VDD = 3. Refer to crystal manufacturer for more details 4.4 µA µA/V tSU(LSE)(4) Startup time VDD is stabilized TA = 0 °C TA = -10 °C TA = -20 °C TA = -30 °C TA = -40 °C 1. Symbol RF CL1 CL2(2) I2 gm 1. 2. STM32F100xE Note: Electrical characteristics For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator.5 pF.768 kHz oscillation is reached. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.5 4 6 s 10 17 32 60 Conditions Min Typ 5 15 Max Unit MΩ pF Caution: Table 23. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer Doc ID 15081 Rev 5 51/97 . Refer to the note and caution paragraphs above the table. then CL1 = CL2 = 8 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF. are usually the same size. To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF.STM32F100xC.3 V VIN = VSS 5 1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32. Typically. Based on characterization. not tested in production. LSE oscillator characteristics (fLSE = 32. Never use a resonator with a load capacitance of 12. and Cstray = 2 pF.768 kHz. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.

TA = –40 to 105 °C °C unless otherwise specified. 52/97 Doc ID 15081 Rev 5 .3 1 2 100 Max Unit MHz % % % % µs µA 1.65 LSI oscillator characteristics (1) Parameter Min 30 Typ 40 Max 60 85 1.3. not tested in production. Typical application with a 32. Guaranteed by design. STM32F100xD.9 -1 1 80 HSI oscillator characteristics(1) Parameter Conditions Min Typ 8 2. VDD = 3 V.3 V. High-speed internal (HSI) RC oscillator Table 24.768 kHz crystal Resonator with integrated capacitors CL1 OSC32_IN 32.4 -2. Based on characterization. 2.2 -1. Guaranteed by design. TA = –40 to 105 °C °C unless otherwise specified. Symbol fLSI tsu(LSI)(2) IDD(LSI)(2) Frequency LSI oscillator startup time LSI oscillator power consumption 0. STM32F100xE Figure 14.Electrical characteristics STM32F100xC. VDD = 3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. 3.2 Unit kHz µs µA 1.3 1. Symbol fHSI Frequency TA = –40 to 105 °C(2) ACCHSI Accuracy of HSI oscillator TA = –10 to 85 TA = 0 to 70 TA = 25 °C tsu(HSI)(3) HSI oscillator startup time IDD(HSI)(3) HSI oscillator power consumption °C(2) °C(2) -2. not tested in production.5 1. 2.768 KH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F10xxx fLSE ai14129b 5. Not tested in production Low-speed internal (LSI) RC oscillator Table 25.

Symbol PLL characteristics Value Parameter PLL input clock(2) Min(1) 1 40 16 Typ 8. Table 26. The clock source used to wake up the device depends from the current operating mode: ● ● Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 2.0 Max(1) 24 60 24 200 300 Unit MHz % MHz µs ps fPLL_IN fPLL_OUT tLOCK Jitter PLL input clock duty cycle PLL multiplier output clock PLL lock time Cycle-to-cycle jitter 1. Based on device characterization. Table 27.STM32F100xC. Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Low-power mode wakeup timings Parameter Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) Wakeup from Stop mode (regulator in low-power mode) Wakeup from Standby mode Typ 1.6 µs 5. Doc ID 15081 Rev 5 53/97 . STM32F100xE Electrical characteristics Wakeup time from low-power mode The wakeup times given in Table 26 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. not tested in production. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction.4 50 µs Unit µs 1. All timings are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. STM32F100xD.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. 5.8 3.3.

Based on characterization not tested in production.6 V Vprog Programming voltage 1. VDD = 3. Table 29. Guaranteed by design.3. Symbol NEND Flash memory endurance and data retention Value Parameter Endurance Conditions TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 1 kcycle(2) at TA = 85 °C kcycle(2) at TA = 105 °C Min(1) 10 30 10 20 Years Unit Typ Max kcycles tRET Data retention 1 10 kcycles(2) at TA = 55 °C 1.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. Table 28. VDD = 3.6 Unit µs ms ms mA mA µA V IDD Supply current Write / Erase modes fHCLK = 24 MHz.10 FSMC characteristics Asynchronous waveforms and timings Figure 15 through Figure 18 represent asynchronous waveforms and Table 30 through Table 33 provide the corresponding timings.0 to 3. STM32F100xE 5.3 V Power-down mode / Halt.5 Max(1) 70 40 40 20 5 50 2 3. Symbol tprog tERASE tME Flash memory characteristics Parameter 16-bit programming time Page (2 KB) erase time Mass erase time Conditions TA = –40 to +105 °C TA = –40 to +105 °C TA = –40 to +105 °C Read mode fHCLK = 24 MHz.3. 5. not tested in production. Cycling performed over the whole temperature range.3 V Min(1) 40 20 20 Typ 52. The results shown in these tables are obtained with the following FSMC configuration: ● ● ● AddressSetupTime = 0 AddressHoldTime = 1 DataSetupTime = 1 54/97 Doc ID 15081 Rev 5 . STM32F100xD. 2. VDD = 3.Electrical characteristics STM32F100xC.

FSMC_NADV is not used. STM32F100xD. C and D only. STM32F100xE Electrical characteristics Figure 15. Doc ID 15081 Rev 5 55/97 .STM32F100xC. Mode 2/B. In Mode 1. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1.

5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns FSMC_NOE high to FSMC_NE high hold time –1.5 0.1 0 0 2THCLK + 25 2THCLK + 25 0 0 5 THCLK + 1. Preliminary values. STM32F100xE Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time Min 5THCLK – 1.5 5THCLK + 1.5 5THCLK – 1.Electrical characteristics Table 30. STM32F100xC. STM32F100xD. Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) th(A_NOE) tv(BL_NE) th(BL_NOE) tsu(Data_NE) th(Data_NOE) th(Data_NE) tv(NADV_NE) tw(NADV) 1.5 FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NOE high Data to FSMC_NEx high setup time tsu(Data_NOE) Data to FSMC_NOEx high setup time Data hold time after FSMC_NOE high Data hold time after FSMC_NEx high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time 56/97 Doc ID 15081 Rev 5 . CL = 15 pF.5 0 0. 2.5 Max 5THCLK + 2 1.

Preliminary values.5 THCLK + 1. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] Address th(A_NWE) tv(BL_NE) FSMC_NBL[1:0] tv(Data_NE) NBL th(BL_NWE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. FSMC_NADV is not used. Table 31. C and D only.5 THCLK 7. STM32F100xD.5 THCLK – 0.STM32F100xC. In Mode 1. CL = 15 pF. Mode 2/B.5 THCLK – 0.5 THCLK + 7 THCLK 1.5 THCLK + 1. STM32F100xE Electrical characteristics Figure 16.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2. Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) th(A_NWE) tv(BL_NE) th(BL_NWE) tv(Data_NE) th(Data_NWE) tv(NADV_NE) tw(NADV) 1.5 Min 3THCLK – 1 THCLK – 0. Doc ID 15081 Rev 5 57/97 .5 Max 3THCLK + 2 THCLK + 1. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high FSMC_NEx low to Data valid Data hold time after FSMC_NWE high FSMC_NEx low to FSMC_NADV low FSMC_NADV low time THCLK 5.

Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] Address t h(A_NOE) tv(BL_NE) FSMC_NBL[1:0] NBL th(BL_NOE) th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Data th(Data_NOE) FSMC_AD[15:0] Address t v(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NADV ai14892b Table 32.5 tsu(Data_NOE) Data to FSMC_NOE high setup time Data hold time after FSMC_NEx high Data hold time after FSMC_NOE high 2. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NOE low FSMC_NOE low time FSMC_NOE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high Address hold time after FSMC_NOE high FSMC_BL hold time after FSMC_NOE high FSMC_NEx low to FSMC_BL valid Data to FSMC_NEx high setup time 2THCLK + 24 2THCLK + 25 0 0 3 THCLK –1.5 Max 7THCLK + 2 4THCLK + 2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3THCLK – 0. STM32F100xD. 58/97 Doc ID 15081 Rev 5 . Preliminary values. Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) th(A_NOE) th(BL_NOE) tv(BL_NE) tsu(Data_NE) th(Data_NE) th(Data_NOE) 1.5 3THCLK + 1.5 THCLK THCLK 0 0 Min 7THCLK – 2 4THCLK – 1 –1 0 5 THCLK + 1. CL = 15 pF.Electrical characteristics STM32F100xC. STM32F100xE Figure 17.

5 THCLK – 5 3 THCLK – 1 THCLK – 3 4THCLK 1.6 Min 5THCLK – 1 2THCLK 2THCLK – 1 THCLK – 1 7 5 THCLK + 1 Max 5THCLK + 2 2THCLK + 1 2THCLK + 2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) 1. STM32F100xE Electrical characteristics Figure 18. Data hold time after FSMC_NWE high Doc ID 15081 Rev 5 59/97 . 2. Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) th(A_NWE) tv(BL_NE) th(BL_NWE) Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Parameter FSMC_NE low time FSMC_NEx low to FSMC_NWE low FSMC_NWE low time FSMC_NWE high to FSMC_NE high hold time FSMC_NEx low to FSMC_A valid FSMC_NEx low to FSMC_NADV low FSMC_NADV low time FSMC_AD (address) valid hold time after FSMC_NADV high Address hold time after FSMC_NWE high FSMC_NEx low to FSMC_BL valid FSMC_BL hold time after FSMC_NWE high THCLK – 1. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] Address th(A_NWE) tv(BL_NE) FSMC_NBL[1:0] t v(A_NE) NBL th(BL_NWE) t v(Data_NADV) Data th(Data_NWE) FSMC_AD[15:0] Address t v(NADV_NE) tw(NADV) th(AD_NADV) FSMC_NADV ai14891B Table 33.STM32F100xC. CL = 15 pF. Preliminary values. STM32F100xD.5 THCLK + 1.

STM32F100xD. see the STM32F10xxx reference manual) DataLatency = 1 for NOR Flash. CLKDivision = 1. Synchronous multiplexed NOR/PSRAM read timings 60/97 Doc ID 15081 Rev 5 . DataLatency = 0 for PSRAM Figure 19. WriteBurst = FSMC_WriteBurst_Enable. The results shown in these tables are obtained with the following FSMC configuration: ● ● ● ● ● BurstAccessMode = FSMC_BurstAccessMode_Enable. MemoryType = FSMC_MemoryType_CRAM. STM32F100xE Synchronous waveforms and timings Figure 19 through Figure 22 represent synchronous waveforms and Table 35 through Table 37 provide the corresponding timings.Electrical characteristics STM32F100xC. (0 is not supported.

25) FSMC_CLK low to FSMC_NOE low FSMC_CLK low to FSMC_NOE high FSMC_CLK low to FSMC_AD[15:0] valid FSMC_CLK low to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid data before FSMC_CLK high 0 6 2 5 2 Electrical characteristics Synchronous multiplexed NOR/PSRAM read timings(1)(2) Parameter Min 27. Symbol tw(CLK) td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0.2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16.. STM32F100xE Table 34.2) FSMC_CLK low to FSMC_NEx high (x = 0.5 Max Unit ns ns ns 4 ns ns 0 ns ns 1 0. Preliminary values...... 2.25) FSMC_CLK low to FSMC_Ax invalid (x = 16.. FSMC_NWAIT valid after FSMC_CLK high Doc ID 15081 Rev 5 61/97 .7 1. STM32F100xD.5 12 ns ns ns ns ns ns ns ns FSMC_A/D[15:0] valid data after FSMC_CLK high 0 8 2 tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) 1..STM32F100xC. CL = 15 pF.

Electrical characteristics STM32F100xC. Synchronous multiplexed PSRAM write timings 62/97 Doc ID 15081 Rev 5 . STM32F100xD. STM32F100xE Figure 20.

2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16...... Preliminary values Electrical characteristics Synchronous multiplexed PSRAM write timings(1)(2) Parameter FSMC_CLK period FSMC_CLK low to FSMC_Nex low (x = 0.STM32F100xC.25) FSMC_CLK low to FSMC_NWE low FSMC_CLK low to FSMC_NWE high FSMC_CLK low to FSMC_AD[15:0] valid FSMC_CLK low to FSMC_AD[15:0] invalid FSMC_A/D[15:0] valid after FSMC_CLK low FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high FSMC_CLK low to FSMC_NBL high 7 2 1 3 6 1 12 2 1 5 0 2 4 Min 27. Symbol tw(CLK) td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-ADV) td(CLKL-ADIV) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH) 1.. CL = 15 pF.7 2 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Doc ID 15081 Rev 5 63/97 ... 2.2) FSMC_CLK low to FSMC_NEx high (x = 0. STM32F100xE Table 35. STM32F100xD.25) FSMC_CLK low to FSMC_Ax invalid (x = 16.

5 5 0 2 4 Min 27.. FSMC_NWAIT valid after FSMC_CLK high 64/97 Doc ID 15081 Rev 5 .25) FSMC_CLK low to FSMC_Ax invalid (x = 0. Synchronous non-multiplexed NOR/PSRAM read timings Table 36.5 FSMC_D[15:0] valid data after FSMC_CLK high 7 7 2 tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high th(CLKH-NWAITV) 1.7 1. Preliminary values.2) FSMC_CLK low to FSMC_NEx high (x = 0.. STM32F100xD. CL = 15 pF.. STM32F100xE Figure 21.25) FSMC_CLK low to FSMC_NOE low FSMC_CLK low to FSMC_NOE high 1... 2.5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) tsu(DV-CLKH) th(CLKH-DV) FSMC_D[15:0] valid data before FSMC_CLK high 6... Symbol tw(CLK) td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0..5 4 1.Electrical characteristics STM32F100xC.2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 0.

. Synchronous non-multiplexed PSRAM write timings Table 37..25) FSMC_CLK low to FSMC_NWE low FSMC_CLK low to FSMC_NWE high FSMC_D[15:0] valid data after FSMC_CLK low FSMC_NWAIT valid before FSMC_CLK high FSMC_NWAIT valid after FSMC_CLK high FSMC_CLK low to FSMC_NBL high 7 2 1 1 6 2 1 5 0 2 4 Min 27.7 2 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKL-NBLH) 1.. STM32F100xE Electrical characteristics Figure 22. 2.2) FSMC_CLK low to FSMC_NEx high (x = 0. Preliminary values.2) FSMC_CLK low to FSMC_NADV low FSMC_CLK low to FSMC_NADV high FSMC_CLK low to FSMC_Ax valid (x = 16.. Doc ID 15081 Rev 5 65/97 .. CL = 15 pF.STM32F100xC.... Symbol tw(CLK) td(CLKL-NExL) td(CLKL-NExH) Synchronous non-multiplexed PSRAM write timings(1)(2) Parameter FSMC_CLK period FSMC_CLK low to FSMC_NEx low (x = 0. STM32F100xD.25) FSMC_CLK low to FSMC_Ax invalid (x = 16.

TA = +25 °C.. over the range of specification values.3. STM32F100xE 5. STM32F100xD. conforms to IEC 61000-4-2 Level/Class VFESD 2B VEFTB VDD = 3. Fast transient voltage burst limits to be fHCLK = 24 MHz. Symbol EMS characteristics Parameter Voltage limits to be applied on any I/O pin to induce a functional disturbance Conditions VDD = 3.. A device reset allows normal operations to be resumed. When unexpected behavior is detected. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor. Table 38. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. TA = +25 °C. fHCLK = 24 MHz. the device is stressed by two electromagnetic events until a failure occurs. conforms to to induce a functional disturbance IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. They are based on the EMS levels and classes defined in application note AN1709. Software recommendations The software flowchart must include the management of runaway conditions such as: ● ● ● Corrupted program counter Unexpected reset Critical Data corruption (control registers. This test is compliant with the IEC 61000-4-2 standard. the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. until a functional disturbance occurs.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. 66/97 Doc ID 15081 Rev 5 . To complete these trials. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports).3 V. The test results are given in Table 38. The failure is indicated by the LEDs: ● ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. LQFP144 package.Electrical characteristics STM32F100xC. LQFP144 applied through 100 pF on VDD and VSS pins package. ESD stress can be applied directly on the device.3 V. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. This test is compliant with the IEC 61000-4-4 standard.

The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). STM32F100xE Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). LQFP144 package compliant with SAE J1752/3 5. Table 39. STM32F100xD.STM32F100xC. LU) using specific measurement methods. This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. EMI characteristics Conditions Monitored frequency band 0. Table 41.3.6 V. Symbol LU Electrical sensitivities Parameter Static latch-up class Conditions TA = +105 °C conforming to JESD78 Class II level A Doc ID 15081 Rev 5 67/97 . output and configurable I/O pin These tests are compliant with EIA/JESD78 IC latch-up standard.12 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. Symbol VESD(HBM) VESD(CDM) ESD absolute maximum ratings Ratings Electrostatic discharge voltage (human body model) Conditions TA = +25 °C conforming to JESD22-A114 Class 2 II Maximum Unit value(1) 2000 V 500 Electrostatic discharge TA = +25 °C voltage (charge device model) conforming to JESD22-C101 1. This test conforms to the JESD22-A114/C101 standard.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1GHz SAE EMI Level Max vs. Table 40. the device is stressed in order to determine its performance in terms of electrical sensitivity. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● ● A supply overvoltage is applied to each power supply pin A current injection is applied to each input. Based on characterization results. [fHSE/fHCLK] Unit 8/24 MHz 16 25 25 4 dBµV Symbol Parameter SEMI Peak level VDD = 3. not tested in production. TA = 25°C.

oscillator frequency deviation). Symbol I/O current injection susceptibility Functional susceptibility Description Negative injection -0 -5 -5 Positive injection +0 +0 +5 mA Unit Injected current on OSC_IN32. However. in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens. PA5. one at a time. PC13 IINJ Injected current on all FT pins Injected current on any other pin 68/97 Doc ID 15081 Rev 5 .13 I/O current injection characteristics As a general rule. STM32F100xE 5. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE). PA4. current injection to the I/O pins. While current is injected into the I/O pin. OSC_OUT32. STM32F100xD. out of spec current injection on adjacent pins or other functional failure (for example reset.Electrical characteristics STM32F100xC. 3 V-capable I/O pins) should be avoided during normal product operation. due to external voltage below VSS or above VDD (for standard. Functional susceptibilty to I/O current injection While a simple application is executed on the device.3. the device is checked for functional failures. susceptibility tests are performed on a sample basis during device characterization. the device is stressed by injecting current into the I/O pins programmed in floating input mode. The test results are given in Table 42 Table 42.

With a minimum of 100 mV. not tested in production.5 5. FT = 5V tolerant.32*(VDD–2 V)+0. To sustain a voltage higher than VDD+0. The coverage of these requirements is shown in Figure 23 and Figure 24 for standard I/Os. Symbol I/O static characteristics Parameter Conditions Min –0.2 mV Unit Standard I/O input low level voltage VIL I/O FT(1) input low level voltage Standard I/O input high level voltage VIH I/O FT(1) input high level voltage Standard I/O Schmitt trigger voltage hysteresis(2) I/O FT Schmitt trigger voltage hysteresis(2) VSS ≤ VIN ≤ VDD Standard I/Os VIN = 5 V I/O FT VIN = VSS VIN = VDD 200 Vhys 5% VDD(3) ±1 mV Ilkg Input leakage current(4) µA 3 30 30 40 40 5 50 50 kΩ kΩ pF RPU RPD CIO Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor(5) I/O pin capacitance 1. Guaranteed by design. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.75 V V VDD+0.8 V 0. STM32F100xE Electrical characteristics 5.STM32F100xC. 4. 3. Hysteresis voltage between Schmitt trigger switching levels.28*(VDD–2 V)+0. 5.3 –0. All I/Os are CMOS and TTL compliant (no software configuration required).3 5. Doc ID 15081 Rev 5 69/97 .3 the internal pull-up/pull-down resistors must be disabled. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). Their characteristics cover more than the strict CMOS-technology or TTL parameters. if negative current is injected on adjacent pins. and in Figure 25 and Figure 26 for 5 V tolerant I/Os. Leakage could be higher than max. the parameters given in Table 43 are derived from tests performed under the conditions summarized in Table 9. 2.42*(VDD–2)+1 V Typ Max 0.3.3 0.3 V VDD > 2 V VDD ≤ 2 V 0.41*(VDD–2 V) +1.14 I/O port characteristics General input/output characteristics Unless otherwise specified. All I/Os are CMOS and TTL compliant. Table 43. STM32F100xD.

Standard I/O input characteristics .CMOS port Figure 24. Standard I/O input characteristics .Electrical characteristics STM32F100xC. STM32F100xD.TTL port 70/97 Doc ID 15081 Rev 5 . STM32F100xE Figure 23.

and sink or source up to ±20 mA (with a relaxed VOL/VOH). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.STM32F100xC. ● Doc ID 15081 Rev 5 71/97 . In the user application.TTL port Output driving current The GPIOs (general-purpose inputs/outputs) can sink or source up to ±8 mA. cannot exceed the absolute maximum rating IVDD (see Table 7).CMOS port Electrical characteristics Figure 26. plus the maximum Run consumption of the MCU sourced on VDD. STM32F100xD. STM32F100xE Figure 25.2: ● The sum of the currents sourced by all the I/Os on VDD. 5 V tolerant I/O input characteristics . 5 V tolerant I/O input characteristics .

7 V < VDD < 3.3 0.6 V TTL port(2) IIO = +8 mA 2.4 V VDD–0. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. STM32F100xE Output voltage levels Unless otherwise specified.4 0. Based on characterization data. 72/97 Doc ID 15081 Rev 5 . IIO = +8 mA.7 V < VDD < 3. 2.Electrical characteristics STM32F100xC.4 V VDD–0.6 V Min Max 0. Symbol VOL(1) VOH (3) Output voltage characteristics Parameter Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions CMOS port(2).7 V 1.4 1. not tested in production. Table 44.6 V VOL(1) VOH (3) IIO = +6 mA(4) 2 V < VDD < 2. STM32F100xD. 3. 4.4 V 2.3 V VDD–1.4 Unit VOL(1) VOH (3) VOL(1) VOH (3) IIO = +20 mA(4) 2. 2.7 V < VDD < 3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. All I/Os are CMOS and TTL compliant. the parameters given in Table 44 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9.

6 V CL = 50 pF. VDD = 2.6 V 125 CL= 50 pF. 2. the parameters given in Table 45 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9.7 V CL = 30 pF.6 V ns tr(IO)out Output low to high level rise time Pulse width of external signals detected by the EXTI controller CL = 50 pF. STM32F100xD. VDD = 2 V to 2. STM32F100xE Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 27 and Table 45. VDD = 2. Table 45. VDD = 2.6 V (3) Unit MHz fmax(IO)out Maximum frequency(2) 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time ns fmax(IO)out Maximum frequency(2) 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time 10(3) 25(3) MHz CL= 50 pF.6 V CL = 30 pF. VDD = 2 V to 3. Guaranteed by design. VDD = 2 V to 3.STM32F100xC.6 V 25(3) CL = 50 pF.7 V to 3.7 V - tEXTIpw ns 1. MODEx [1:0] bit value(1) I/O AC characteristics(1) Symbol Parameter Conditions CL = 50 pF. Doc ID 15081 Rev 5 73/97 .6 V CL = 50 pF. respectively. VDD = 2. 3. VDD = 2 V to 2. The maximum frequency is defined in Figure 27.7 V to 3. Refer to the STM32F100xx reference manual for a description of GPIO Port configuration register. Unless otherwise specified.7 V to 3. VDD = 2 V to 3. The I/O speed is configured using the MODEx[1:0] bits. VDD = 2 V to 3.7 V to 3. VDD = 2 V to 3.6 V Max 2(3) 125(3) CL = 50 pF.6 V 24 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) 10(3) ns fmax(IO)out Maximum frequency(2) Output high to low level fall time MHz tf(IO)out 11 CL = 50 pF. not tested in production.

The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 46. 74/97 Doc ID 15081 Rev 5 . RPU (see Table 43). The reset network protects the device against parasitic resets.8 V VDD+0.5 2 200 40 50 100 Typ Max 0. 2. It is connected to a permanent pull-up resistor. not tested in production.5 mV kΩ ns ns Unit Vhys(NRST) RPU VF(NRST)(1) VNF(NRST)(1) 1. I/O AC characteristics definition 90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out T 10% 50% 90% tr(I O)out Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5. STM32F100xE Figure 27. Guaranteed by design. The pull-up is designed with a true resistance in series with a switchable PMOS. Figure 28. 2.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. Unless otherwise specified. STM32F100xD. This PMOS contribution to the series resistance must be minimum (~10% order). Otherwise the reset will not be taken into account by the device. Table 46. Recommended NRST pin protection 1. Symbol VIL(NRST)(1) VIH(NRST) (1) NRST pin characteristics Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse 300 VIN = VSS 30 Conditions Min –0.3.Electrical characteristics STM32F100xC. the parameters given in Table 46 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9.

PWM output). TIM4. to the CH1 to CH2 for TIM15. TIM4 and TIM5.17 Communications interfaces I2C interface characteristics Unless otherwise specified. CHx is used as a general term to refer to CH1 to CH4 for TIM1. Doc ID 15081 Rev 5 75/97 .3.16 TIMx characteristics The parameters given in Table 47 are guaranteed by design. input capture. TIM15. and to CH1 for TIM16 and TIM17. fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9. When configured as open-drain. Table 47. STM32F100xD. external clock. TIM2. Symbol tres(TIM) TIMx characteristics Parameter Timer resolution time Timer external clock frequency on CHx(2) Timer resolution 16-bit counter clock period when the internal clock is selected 1 fTIMxCLK = 24 MHz Conditions(1) Min 1 fTIMxCLK = 24 MHz 41. TIM3. TIM3.3. the PMOS connected between the I/O pin and VDD is disabled. but is still present.3. STM32F100xE Electrical characteristics 5. 5. The STM32F100xx value line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Refer to Section 5. 2. TIMx is used as a general term to refer to the TIM1. Refer also to Section 5.7 0 fTIMxCLK = 24 MHz 0 fTIMxCLK/2 12 16 65536 2730 65536 × 65536 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK µs tTIMxCLK s fEXT ResTIM tCOUNTER tMAX_COUNT Maximum possible count fTIMxCLK = 24 MHz 178 1.STM32F100xC. TIM5. TIM16 and TIM17 timers. The I2C characteristics are described in Table 48. TIM2.3. the parameters given in Table 48 are preliminary values derived from tests performed under the ambient temperature.13: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare.

3. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies.7 4. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. STM32F100xE I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 250 0 (3) Unit Max Min 1.6 0.6 µs 0. It must be higher than 4 MHz to achieve fast mode I2C frequencies.0 4. The maximum hold time of the Start condition only has to be met if the interface does not stretch the low period of SCL signal. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.0 4.Electrical characteristics Table 48. 76/97 Doc ID 15081 Rev 5 . 2.3 µs 0.3 400 µs µs pF 900(3) 300 300 ns Max 1.7 400 4. Guaranteed by design. 4.6 1.6 100 0(4) 1000 300 0. not tested in production.7 4. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb STM32F100xC. STM32F100xD.

the tolerance on the achieved speed is of ±2%. Guaranteed by design. fSCL = I2C speed. RP = External pull-up resistance.STM32F100xC. SCL frequency (fPCLK1= 24 MHz. For speeds around 400 kHz. Measurement points are done at CMOS levels: 0. STM32F100xE Figure 29. VDD = 3.7VDD. For other speed ranges. Doc ID 15081 Rev 5 77/97 . Table 49. These variations depend on the accuracy of the external components used to design the application. STM32F100xD. the tolerance on the achieved speed ±1%.7 kΩ 0x8011 0x8016 0x8021 0x0064 0x00C8 0x01F4 1. 3.3VDD and 0. I2C bus AC waveforms and measurement circuit Electrical characteristics Ω Ω Ω Ω 1.3 V)(1)(2) fSCL (kHz)(3) 400 300 200 100 50 20 I2C_CCR value RP = 4. 2. not tested in production.

3. Refer to Section 5. SCK. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. Preliminary values. MISO). fPCLK = 24 MHz.Electrical characteristics STM32F100xC. STM32F100xE SPI interface characteristics Unless otherwise specified. fPCLK = 24 MHz 4 0 2 3tPCLK 10 25 5 15 2 ns 5 5 30 4tPCLK 2tPCLK 50 5 60 12 8 70 ns % Conditions Master mode Min Max 12 MHz Unit th(SI)(1) ta(SO) (1)(2) tdis(SO)(1)(3) Data output disable time Slave mode tv(SO) (1) Data output valid time Data output valid time Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) tv(MO)(1) th(SO)(1) th(MO)(1) Data output hold time Master mode (after enable edge) 1. the parameters given in Table 50 are preliminary values derived from tests performed under the ambient temperature.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS. presc = 4 Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Slave mode. fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. 3. MOSI. 2. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 78/97 Doc ID 15081 Rev 5 . Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) tsu(NSS)(1) th(NSS)(1) tw(SCKH)(1) tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) th(MI) (1) SPI characteristics Parameter SPI clock frequency Slave mode SPI clock rise and fall time SPI slave input clock duty cycle NSS setup time NSS hold time SCK high and low time Capacitive load: C = 30 pF Slave mode Slave mode Slave mode Master mode. STM32F100xD. Table 50.

SPI timing diagram . Doc ID 15081 Rev 5 79/97 .slave mode and CPHA = 0 NSS input tc(SCK) tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN th(SI) B I T1 IN Electrical characteristics th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) LSB OUT tv(SO) MS B O UT th(SO) BI T6 OUT tdis(SO) LSB IN ai14134c Figure 31. SPI timing diagram .slave mode and CPHA = 1 NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. STM32F100xD. Measurement points are done at CMOS levels: 0.7VDD. STM32F100xE Figure 30.3VDD and 0.STM32F100xC.

18 12-bit ADC characteristics Unless otherwise specified. Note: It is recommended to perform a calibration after each power-up.7VDD. STM32F100xD.13: I/O current injection characteristics for more details on the input/output alternate function characteristics.3VDD and 0. Measurement points are done at CMOS levels: 0.3. 80/97 Doc ID 15081 Rev 5 . 5. HDMI consumer electronics control (CEC) Refer to Section 5. fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9.Electrical characteristics Figure 32. STM32F100xE CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. the parameters given in Table 51 are preliminary values derived from tests performed under the ambient temperature. SPI timing diagram .master mode High NSS input tc(SCK) SCK Input STM32F100xC.3.

VREF+ is internally connected to VDDA 4. Symbol VDDA VREF+ IVREF fADC fS(2) fTRIG(2) VAIN(3) RAIN(2) RADC(2) CADC(2) tCAL(2) tlat(2) tlatr(2) tS(2) tSTAB(2) tCONV(2) Electrical characteristics ADC characteristics Parameter Power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate External trigger frequency fADC = 12 MHz 0.6 0.214 3 fADC = 12 MHz (4) Unit V V µA MHz MHz kHz 1/fADC V kΩ kΩ pF µs 1/fADC µs 1/fADC µs 1/fADC µs 1/fADC µs µs 1/fADC 0 (VSSA tied to ground) See Equation 1 and Table 52 for details VREF+ 50 1 8 0. Preliminary values.05 Conditions Min 2.STM32F100xC.143 2(4) 0.6 VDDA 220(1) 12 1 823 17 Conversion voltage range External input impedance Sampling switch resistance Internal sample and hold capacitor Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) fADC = 12 MHz fADC = 12 MHz 5.9 83 fADC = 12 MHz 0.1 239. Doc ID 15081 Rev 5 81/97 . Equation 1: RAIN max formula: TS R AIN < ------------------------------------------------------------. STM32F100xE Table 51. 3.4 160(1) Typ Max 3.5 for successive approximation) 1. a delay of 1/fPCLK2 must be added to the latency specified in Table 51.17 14 to 252 (tS for sampling +12. 2.125 17. Guaranteed by design. For external triggers. STM32F100xD.5 0 1. Here N = 12 (from 12-bit resolution).– R ADC N+2 f ADC × C ADC × ln ( 2 ) The above formula (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB.4 2. not tested in production.5 0 1 21 fADC = 12 MHz 1.

Table 54.5 71.6 V TA = Full operating range Measurements made after ADC calibration Typ ±2 ±1. STM32F100xD.5 ±1 ±0. Preliminary values.5 LSB Unit 1.5 ±1. Note: ADC accuracy vs. STM32F100xE RAIN max for fADC = 12 MHz(1) Ts (cycles) tS (µs) 0. 82/97 Doc ID 15081 Rev 5 .5 28.5 ±2 ±1.2 50 NA NA RAIN max (kΩ) 1.96 20 0.5 ±1.9 11. VDDA = 2.6 V VREF+ = VDDA TA = 25 °C Measurements made after ADC calibration Typ ±1. Preliminary values. fADC = 12 MHz. Guaranteed by design.limited test conditions(1)(2) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 24 MHz.5 ±1.5 1.5 41. frequency. RAIN < 10 kΩ.4 V to 3. fADC = 12 MHz.4 5. Symbol ET EO EG ED EL ADC accuracy .5 Max ±2.5 ±1.5 7.4 25.5 13.5 ±1.5 239. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. STM32F100xC. ADC DC accuracy values are measured after internal calibration. VREF and temperature ranges.125 0. ADC DC accuracy values are measured after internal calibration.5 ±2 ±2 LSB Unit 1. Table 53. not tested in production.Electrical characteristics Table 52.625 1.5 ±4.125 2. 2.5 ±3 ±2. negative injection current: Injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input.5 Max ±5 ±2. 2.375 3.5 55.2 37.625 5. 3. VDDA = 3 V to 3.45 4. Better performance could be achieved in restricted VDD. RAIN < 10 kΩ. Symbol ET EO EG ED EL ADC accuracy(1) (2) (3) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 24 MHz.

ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. fADC should be reduced. 2. A high Cparasitic value will downgrade conversion accuracy. RADC and CADC. Refer to Table 51 for the values of RAIN. Doc ID 15081 Rev 5 83/97 . Figure 33.3. STM32F100xD. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). Typical connection diagram using the ADC VDD VT 0. They should be placed them as close as possible to the chip. STM32F100xE Electrical characteristics Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5. To remedy this. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 35 or Figure 36. EO=Offset Error: deviation between the first actual transition and the first ideal one. depending on whether VREF+ is connected to VDDA or not.STM32F100xC. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.6 V AINx VT 0. The 10 nF capacitors should be ceramic (good quality).6 V IL±1 µA STM32F10xxx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) RAIN(1) VAIN Cparasitic ai14139d 1.13 does not affect the ADC accuracy. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 5 6 7 4093 4094 4095 4096 VDDA ai14395b Figure 34. EG=Gain Error: deviation between the last ideal transition and the last actual one.

84/97 Doc ID 15081 Rev 5 .is available on 100-pin packages only. Figure 36.Electrical characteristics STM32F100xC. VREF+ is available on 100-pin packages and on TFBGA64 packages.inputs are available only on 100-pin packages. STM32F100xD. STM32F100xE Figure 35. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F10xxx V REF+ 1 µF // 10 nF V DDA 1 µF // 10 nF V SSA/V REF- ai14380b 1. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA 1 µF // 10 nF VREF–/VSSA ai14381b 1. VREF+ and VREF. VREF.

2 V VDDA – V 0.6 V in terms of DC consumption on the inputs Given for the DAC in 10-bit configuration Given for the DAC in 12-bit configuration Given for the DAC in 10-bit configuration Given for the DAC in 12-bit configuration 380 IDDA DAC DC current consumption in quiescent mode (Standby mode) 480 µA µA ±0.STM32F100xC.6 0 Unit V V V kΩ When the buffer is OFF. STM32F100xE Electrical characteristics 5.5 MΩ Maximum capacitive load at DAC_OUT pin (when the buffer is ON).6 V and (0x155) and (0xEAB) at VREF+ = 2. Symbol VDDA VREF+ VSSA RLOAD RO(1) (1) DAC electrical specifications DAC characteristics Parameter Analog supply voltage Reference supply voltage Ground Resistive load with buffer ON Min 2. the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.3. STM32F100xD.4 2.4 V It gives the maximum output excursion of the DAC.6 V in terms of DC consumption on the inputs With no load.6 3.4 0 5 Typ Max(1) 3.2 0.5 DNL(1) Differential non linearity Difference between two consecutive code-1LSB) ±2 Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) ±1 ±4 LSB LSB LSB LSB INL(1) Doc ID 15081 Rev 5 85/97 .19 Table 55.5 mV VREF+ V – 1LSB IDDVREF+ 220 µA With no load. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3. worst code (0xF1C) at VREF+ = 3. worst code (0xF1C) at VREF+ = 3. VREF+ must always be below VDDA Comments Impedance output with buffer OFF 15 kΩ CLOAD(1) Capacitive load 50 pF DAC_OUT min(1) DAC_OUT max(1) DAC_OUT min(1) DAC_OUT max(1) Lower DAC_OUT voltage with buffer ON Higher DAC_OUT voltage with buffer ON Lower DAC_OUT voltage with buffer OFF Higher DAC_OUT voltage with buffer OFF DAC DC current consumption in quiescent mode (Standby mode) 0. It gives the maximum output excursion of the DAC. middle code (0x800) on the inputs With no load.

No RLOAD. Preliminary values. Symbol STM32F100xC. CLOAD = 50 pF tWAKEUP(1) PSRR+ (1) 6. RLOAD ≥ 5 kΩ CLOAD ≤ 50 pF. STM32F100xD.5 10 µs –67 –40 dB 1. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD 12-bit digital to analog converter DACx_OUT C LOAD ai17157 1.6 V Given for the DAC in 12-bit at VREF+ = 3. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. RLOAD ≥ 5 kΩ 1 MS/s CLOAD ≤ 50 pF. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.Electrical characteristics Table 55.5 Settling time (full scale: for a 10-bit input code transition between the tSETTLING(1) lowest and the highest input codes when DAC_OUT reaches final value ±1LSB Update rate(1) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) Wakeup time from off state (Setting the ENx bit in the DAC Control register) Power supply rejection ratio (to VDDA) (static DC measurement 3 4 µs CLOAD ≤ 50 pF. 86/97 Doc ID 15081 Rev 5 . STM32F100xE DAC characteristics (continued) Parameter Min Typ Max(1) ±10 Unit mV LSB LSB % Comments Given for the DAC in 12-bit configuration Given for the DAC in 10-bit at VREF+ = 3.6 V Given for the DAC in 12-bit configuration Offset(1) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) ±3 ±12 Gain error(1) Gain error ±0. Figure 37. RLOAD ≥ 5 kΩ input code between lowest and highest possible ones.

3 1. Doc ID 15081 Rev 5 87/97 .0 1. not tested in production. STM32F100xE Electrical characteristics 5. Shortest sampling time can be determined in the application by multiple iterations.20 Table 56. STM32F100xD.3.1 1. Symbol TL(1) Avg_Slope V25(1) tSTART(2) TS_temp(3)(2) (1) Temperature sensor characteristics TS characteristics Parameter VSENSE linearity with temperature Average slope Voltage at 25°C Startup time ADC sampling time when reading the temperature 4.50 10 17. Guaranteed by characterization. 2.6 1.32 4 Min Typ Max Unit °C mV/°C V µs µs ±1 4.41 ±2 4.STM32F100xC. not tested in production. Guaranteed by design. 3.

ECOPACK® is an ST trademark. grade definitions and product status are available at: www. STM32F100xE 6 6. STM32F100xD. depending on their level of environmental compliance. 88/97 Doc ID 15081 Rev 5 .com.1 Package characteristics Package mechanical data In order to meet environmental requirements.st. ST offers these devices in different grades of ECOPACK® packages. ECOPACK® specifications.Package characteristics STM32F100xC.

20 0. Dimensions are in millimeters.0031 7° 0.002 0.7874 0.45 0.80 19.0295 0.0197 0.7953 0.40 0.20 0.0035 0. 2.20 22.063 0.05 1.17 0.5° 0.9 22.6 109 E1 E3 E 144 37 1 19.60 1.9 22.85 19.7953 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1.0087 Min inches(1) Typ Max 0.45 0.50 21. Symbol LQFP144.09 21.689 0.00 17. Table 57.08 7° 0° 0.8661 0. Doc ID 15081 Rev 5 89/97 .8583 0.8583 0.35 0.7795 0.00 20. Recommended footprint A A2 A1 ccc C b c 0.50 0.0571 0.689 0.35 72 L L1 0.STM32F100xC.5° 0.6 36 ai14 144 37 1 36 Pin 1 identification e ME_1A 1. STM32F100xE Package characteristics Figure 38.80 22.0106 0.25 mm gage plane D D1 D3 A1 73 72 108 73 1.7795 1. 144-pin thin quad flat package outline Seating plane C Figure 39.80 19.80 22.0067 0.0236 0.0177 22. 20 x 20 mm.15 1.50 0.0079 0.7874 0. STM32F100xD.20 20. 20 x 20 mm.75 0. Values in inches are converted from mm and rounded to 4 decimal digits.0394 3. Drawing is not to scale.0551 0.8661 0. 144-pin thin quad flat package mechanical data millimeters Min Typ Max 1.27 0. LQFP144.00 0° 3.874 0.0531 0.60 0.0059 0.5 108 17.00 20.22 0.00 17.20 20.35 k 109 0.874 0.

0059 0.00 12.5591 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1.20 0.5433 0.17 0.0035 0.00 0° 3.0551 0.25 mm 0. Symbol LQPF100 – 14 x 14 mm.6378 0.22 0.80 16.3 50 16. 90/97 Doc ID 15081 Rev 5 .622 0.622 0.45 0.4724 0.05 1.60 1.35 0.80 16.0197 0.063 0.5433 1.45 0.7 14.50 0.00 14.3 b E3 E1 E 100 26 1.09 15.00 12.002 0.00 15.80 13. 100-pin low-profile Figure 41.5512 0.Package characteristics STM32F100xC. LQFP100 – 14 x 14 mm.0571 0. Dimensions are in millimeters.2 100 26 25 1 ccc C 25 12.0067 0.6299 0.0394 3.40 0.0177 16.15 1.00 14.27 0.60 0.0031 7° 0.5° 0.20 14.0236 0.10 inch GAGE PLANE k D D1 D3 75 76 51 75 51 L L1 C 76 0.08 7° 0° 0. Drawing is not to scale.20 16.7 Pin 1 1 identification e A1 ai14906b A2 A SEATING PLANE C 1L_ME 1. STM32F100xD.0079 0.3 16. 2. Values in inches are converted from mm and rounded to 4 decimal digits. STM32F100xE Figure 40. Table 58.6299 0. Recommended footprint quad flat package outline 0.5591 0.20 14.20 0.0295 0.6378 0.75 0.4724 0.80 13. 100-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.0087 Min inches(1) Typ Max 0.0106 0.5 50 0.5° 0.00 0.5512 0.0531 0.

Drawing is not to scale.STM32F100xC. 2.0551 0. Symbol LQFP64 – 10 x 10 mm.4724 0.40 0.3937 0.3 e 10.50 0° 0.60 0.0177 1.5 32 E E1 b 12.00 12. STM32F100xD.3937 0.0020 0. 64 pin low-profile quad Figure 43. LQFP64 – 10 x 10 mm.0531 0.2 1 7.0067 0. Values in inches are converted from mm and rounded to 4 decimal digits.00 10.0236 0.0295 0.35 0.0035 0. Table 59.45 0.45 3.0394 7° 0.27 0.05 1.22 0.0059 0.0106 0.15 1. 64 pin low-profile quad flat package mechanical data millimeters Min Typ Max 1. Dimensions are in millimeters.5° 0. Recommended flat package outline footprint A A2 A1 49 48 33 0.0571 0.00 Number of pins 7° 0.0630 0.60 1.0197 3.7 ai14909 ai14398b 1.00 10.17 0.3 0.5° 0.0087 Min inches(1) Typ Max 0. Doc ID 15081 Rev 5 91/97 .0079 A A1 A2 b c D D1 E E1 e θ L L1 N 64 1.75 0° 0.09 12.7 10.4724 0. STM32F100xE Package characteristics Figure 42.00 0.3 64 17 1.8 16 D1 D L1 L c 12.20 0.

expressed in Watts. Available from www.jedec.Natural Convection (Still Air). Table 60. may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: ● ● ● ● TA max is the maximum ambient temperature in °C. STM32F100xD.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions .org. Symbol Package thermal characteristics Parameter Thermal resistance junction-ambient LQFP 144 . in °C/W.5 mm pitch Value 35 40 49 °C/W Unit ΘJA Thermal resistance junction-ambient LQFP 100 .2 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 37. PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax).2.20 × 20 mm / 0. 92/97 Doc ID 15081 Rev 5 .5 mm pitch Thermal resistance junction-ambient LQFP 64 . PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. TJ max.10 × 10 mm / 0.14 × 14 mm / 0. ΘJA is the package junction-to-ambient thermal resistance. STM32F100xE 6. The maximum chip-junction temperature. This is the maximum chip internal power. in degrees Celsius. PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH). PINT max is the product of IDD and VDD.Package characteristics STM32F100xC.5 mm pitch 6.

IDDmax = 20 mA. it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. VOL= 1.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA.STM32F100xC.3 V PINTmax = 50 mA × 3. IDDmax = 50 mA.1 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C). STM32F100xE Package characteristics 6.5 V. to a specific maximum junction temperature.2 Selecting the product temperature range When ordering the microcontroller. maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA. VDD = 3.5 V= 70 mW PIOmax = 20 × 8 mA × 0. As applications do not commonly use the STM32F100xx at maximum dissipation. as long as junction temperature TJ remains within the specified range. 49 °C/W TJmax = 82 °C + (49 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.5 V. the temperature range is specified in the ordering information scheme shown in Table 61: Ordering information scheme. Example 2: High-temperature application Using the same rules. maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA. parts must be ordered at least with the temperature range suffix 6 (see Table 61: Ordering information scheme).2. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2). STM32F100xD.4 V + 8 × 20 mA × 1. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Doc ID 15081 Rev 5 93/97 .5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V PINTmax = 20 mA × 3. VOL= 0. In this case.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 60 TJmax is calculated as follows: – For LQFP64. The following examples show how to calculate the temperature range needed for a given application. it is possible to address applications that run at high ambient temperatures with a low dissipation. VOL= 0. Example: high-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2). VDD = 3.

Package characteristics

STM32F100xC, STM32F100xD, STM32F100xE

Using the values obtained in Table 60 TJmax is calculated as follows: – For LQFP100, 40 °C/W TJmax = 115 °C + (40 °C/W × 134 mW) = 115 °C + 5.4 °C = 120.4 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 61: Ordering information scheme). Figure 44. LQFP100 PD max vs. TA
700 600

PD (mW)

500 400 300 200 100 0 65 75 85 95 105 115 125 135 Suffix 6 Suffix 7

TA (°C)

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Doc ID 15081 Rev 5

STM32F100xC, STM32F100xD, STM32F100xE

Ordering information scheme

7

Ordering information scheme
Table 61.
Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Device subfamily 100 = value line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C 7 = Industrial temperature range, –40 to 105 °C Internal code B Options xxx = programmed parts TR = tape and real

Ordering information scheme
STM32 F 100 V C T 6 B xxx

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

Doc ID 15081 Rev 5

95/97

Revision history

STM32F100xC, STM32F100xD, STM32F100xE

8

Revision history
Table 62.
Date 09-Oct-2008

Document revision history
Revision 1 Initial release. I/O information clarified on page 1. Table 5: High-density STM32F100xx pin definitions modified. Figure 5: Memory map on page 26 modified. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Table 20: High-speed external user clock characteristics and Table 21: Low-speed user external clock characteristics modified. ACCHSI max values modified in Table 24: HSI oscillator characteristics. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 10, Figure 11 and Figure 12 show typical curves (titles changed). Small text changes. Major revision of whole document. Added LQFP144 package and additional peripherals (SPI3, UART4, UART, TIM5, 12, 14, 13, FSMC). Updated Power consumption data in Table 13 to Table 16 Updated Section 5.3.11: EMC characteristics on page 66 Added Section 2.2.6: LCD parallel interface on page 13 In Table 4 on page 24 moved TIM15_BKIN and TIM17_BKIN from remap to default column. Updated description of PA3, PA5 and PF6 to PF10. Updated footnotes below Table 6: Voltage characteristics on page 36 and Table 7: Current characteristics on page 37 Added VBAT values in Table 16: Typical and maximum current consumptions in Stop and Standby modes on page 43 Updated tw min in Table 20: High-speed external user clock characteristics on page 47 Updated startup time in Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 51 Added HSI clock accuracy values in Table 24: HSI oscillator characteristics on page 52 Updated FSMC Synchronous waveforms and timings on page 60 Updated Table 43: I/O static characteristics on page 69 Added Section 5.3.13: I/O current injection characteristics on page 68 Corrected TTL and CMOS designations in Table 44: Output voltage characteristics on page 72 Changes

31-Mar-2009

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18-Oct-2010

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11-Apr-2011

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Doc ID 15081 Rev 5

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