Digital Simulation Labs

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Table of Contents
General Notes Lab1: An Inverter Lab 2: A Buffer Lab 3:Flipflop Lab 4: ALU Lab 5: Clock gating enabled RTL Synthesis of the FlipFlop circuit 6 9 12 16 21

Lab 6: Synthesis and Automatic layout generation followed simulation of the ALU circuit . 26

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General Notes
There are a number of things to consider before beginning these lab exercises. Please read through this section completely, and perform any needed steps in order to ensure a successful workshop. These labs were designed for use with Incisive Unified Simulator. Before running any of these labs, ensure that you‘ve set up IUS correctly:
%> setenv IUSHOME <IUS-installation-home>

To setup the lab environment, please perform the following steps: 1. Ensure the software mentioned above is correctly setup. 2. Source the C-Shell related commands file i.e (csh). These labs were designed to be run using Root Simulator and the synthesis engine.

LINUX BASICS
Determining your working directory
To find out what directory you are currently working in, use the pwd (Print Working Directory) command.
root@cadence:~$ pwd

The pwd command displays the full name of the directory in which you are working. The name of a user's home directory is his or her username, so yours will be different from the example (root is the person's username and the path to her home directory is /home/root.)

What is in a directory?
To find out what's in a directory, you can use the ls command to list its contents. Typing the command by itself lists the contents of your current working directory, but you also can use the command to list the contents of any directory. For now, just type ls and press Enter.
root@cadence:~$ ls Desktop

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and the two dots. if you are working in your home directory. Double dot . you use the cd command to change your working directory.Single dot . Type the ls command. a space. "home" is the parent of "root" in /home/root/. Compare the output from entering the following variations of the ls command while working in the user's home directory: root@cadence:~$ ls . root@cadence:~$ ls . then press Enter. If you are working in /usr/lib/ then the single dot represents /usr/lib . This represents the directory immediately "above" (or which contains) the current directory. your "working directory"..Parent Directory the double dot (two dots) is an object that represents the relative parent directory. as shown. Cadence Confidential 4 . This will list the contents of the parent directory for your current working directory. the dot represents your home directory. In the example. Making a new directory Use the mkdir command to make a new directory using an unique name and then use ls to verify that your new directory was created. You can specify a directory change in several ways.Current Directory A single dot is an "object" that represents the current directory. Before: root@cadence:~$ ls Make your new directory: root@cadence:~$ mkdir file1 After: root@cadence:~$ ls file1 Change your working directory In Linux.

For example: root@cadence:~$ cd /home root@cadence:/home$ pwd /home Return back to previous directory : root@cadence : cd - Cadence Confidential 5 .Typing the cd command and pressing Enter will take you to your home directory from anywhere on the system. Full directory names begin with a leading forward slash. For example: root@cadence:cd file1 root@cadence:~$ pwd Typing cd and the full name of a directory will take you to that directory from anywhere on the system.

v –MESS The compiler places the inverter_test description in the INCA_libs library. You will need to copy each file present in solutions folder to Workarea/Inverter location by using the below mentioned command : 3.Lab1: An Inverter In this lab we will simulate the inverter code modeled using switch level by the help of Incisive unified simulator. Cadence Confidential 6 .In this lab we will see how to perform simulation in command mode using testbench without using GUI window. (ii) Compile the testbench description with the -MESS option: ncvlog inverter_test. Note: You can abbreviate options down to their shortest unique string and use upper or Lower case. View the Code of Inverter and also the testbench for the same. 4.v –messages The compiler places the inverter description in the INCA_libs library. Compile the source Descriptions : (i) Compile the Inverter description with the -messages option: ncvlog inverter. 1. Change directory to digitallabs/lab1/Inverter 2.

5. Elaborate the top level Design (i) Elaborate the testbench

ncelab inv_test -messages
The elaborator places the inv_test code and snapshot in the INCA_libs library.

6. Simulate the Top-Level Design (i) Simulate the testbench:

ncsim inv_test

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The simulator displays results similar to the following:

Lab Summary:
In this lab we saw how to compile, elaborate and simulate the tesbench for Inverter module.

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Lab 2: A Buffer
In this lab, you will simulate a design using the Incisive simulator. You will: Perform this lab in the Buffer directory. This directory contains the following files (which you should briefly examine) describing a simple Buffer and its testbench: File(s) Description Buffer.v Buffer_test.v Buffer code Testbench

1. Change directory to digitallabs/lab2/Buffer. 2. View the Code of Inverter and also the testbench for the same.

3 . Compile the Source Descriptions (i). Compile the buffer description with the -mess option:

ncvlog buffer.v –mess

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(ii). Compile the testbench description with the -MESS option:

ncvlog buffer_test.v -mess

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Elaborate the Top-Level Design 1.Note: You can abbreviate options down to their shortest unique string and use upper or lower case. Elaborate the testbench: ncelab buf_test Cadence Confidential 10 . 6.

you simulated a design using the Incisive simulator. elaborated. Simulate the Top-Level Design (i) Simulate the testbench: ncsim buf_test The simulator displays results similar to the following: Lab Summary In this lab. and simulated the design and testbench Cadence Confidential 11 .7. You: * Compiled.

v 1. and simulate the design and testbench using nclaunch command in single step mode. step. and start other graphical tools. reset. you will simulate a design using the Incisive simulator. or disconnect the simulation. b. show the value of objects. Cadence Confidential 12 .Lab 3: Flip-Flop In this lab. or next the simulation.View the Code of Flipflop and also the testbench for the same. interrupt. Change directory to lab3. You can use the Tool Bar to run. Perform this lab in the lab3 directory. elaborate. This directory contains the following files (which you should briefly examine) describing a Flipflops and its testbenches: File(s) Description: ff. Use the following command to invoke user friendly GUI: irun ff.v ff_t. You can use the Menu Bar to run or step the simulation. and shut down the interface or the simulation. set scopes and stops.v ff_t.v –access +rwc –gui Now the Console & Design Browser window opens Before proceeding to the next step analyze the messages in the terminal window a. You will: * Compile.

b. Open an existing Waveform window or select the Windows . Display the component instances of the scope (double-click the scope in the Scope Tree pane). 3. a. Waveform window appears as shown below Cadence Confidential 13 .New .The simulator creates a default SHM database and sets a probe on any selected signals and opens a Waveform window displaying the selected signals. In the Design Browser window select all signals at the testbench scope. a. Tour the Waveform window. b.Waveform menu item or the Waveform button. Examine the Design Browser window.Note: To add additional signals simply select them in any window and click the Waveform button again. Open an existing Design Browser window or select the Windows— new — Design Browser menu item or the Design Browser button. Display the objects of a scope and their value in the Objects List pane (Select any displayed scope in the Scope Tree pane).2. Add the selected signal(s) to the Waveform window (select the Waveform button or the Add Selected button or drag and drop the signals into the Waveform window).

Select ff_t and click on the wave form window button Waveform window appears as shown below: Run the testbech simulation by clicking the following icon Cadence Confidential 14 .

We will obtain the required output of Flip flop in the waveform window as shown below: Cadence Confidential 15 .

Testbench 1.v –messages (ii).v – alu code test_alu. 2. you will simulate a design using the Incisive simulator. and simulate the design and testbench Perform this lab in the lab4 directory.v -.: Compile the Source Descriptions (i). This directory contains the following files (which you should briefly examine) describing a simple Transmission gate and its testbench: File(s) Description alu. Change directory to lab4.v –mess Cadence Confidential 16 .Lab 4: ALU In this lab. You will: * Compile. Compile the testbench description with the -MESS option: ncvlog test_alu. Compile the alu design description with the -messages option: ncvlog alu. View the Code of alu and also the testbench for the same. elaborate.

4.3. Simulate the top level design: (i) Simulate the testbench: with –gui option: ncsim TESTGEN_ALU –gui The -gui option opens the Console and Design Browser windows. Examine the Console window. Elaborate the design: ncelab TESTGEN_ALU -access +rwc -mess . Cadence Confidential 17 . Tour the Graphical Interface 1.

b. reset. 2. Display the objects of a scope and their value in the Objects List pane (Select any displayed scope in the Scope Tree pane). Display the component instances of the scope (double-click the scope in the Scope Tree pane). Schematic Tracer and Waveform window. You can use the Menu Bar to run or step the simulation. You can use the command line interface to the simulation in the I/O Region. interrupt. Open an existing Design Browser window or select the Windows— new — Design Browser menu item or the Design Browser button. and start other graphical tools. show the value of objects. set scopes and stops. a. or disconnect the simulation. 18 Cadence Confidential . Examine the Design Browser window. and shut down the interface or the simulation. c. or next the simulation. b. Examine the Design and Testbench Hierarchy In this section of the lab you visit the Source Browser.a. You can use the Tool Bar to run. step.

Once the simulation is done you can see the following waveform window and console window with the outputs. As no such window yet exists. and makes it the default Waveform target window. Cadence Confidential 19 .Move primary cursor to previous edge of select signal. --. select the Design Browser tab toexpand the sidebar area and display the embedded Design Browser. In the Source Browser window ensure that just the top-level scope is selected and send it tothe target Waveform window. this opens a Source Browser window displaying the source of the Top-level unit. In the Design Browser window select the top-level (TESTGEN_ALU) scope and select the Source Browser button to send it to the target Source Browser window. In the Source Browser window ensure that just the top-level scope is selected (navigate up as needed and Select—This Scope) and send it to the target Schematic Tracer window. 3. and makes it the default Schematic Tracer target. In the left sidebar. and makes it the default Source Browser target window. a.1.Run the simulation --. this opens a Waveform window displaying the signals of the top-level unit. As no such window yet exists. 2. As no such window yet exists. this opens a Schematic Tracer window displaying the top-level unit.

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Please read through this section completely. It‘s a place to run Synthesis .v work rtl Cadence Confidential 21 . and perform any needed steps in order to ensure a successful workshop. There are a number of things to consider before beginning the lab exercises. Go to directory lab5 Lab directory details: lib Contains the lib files for mapping the code to specified rtl. Flip flop rtl code ff.Lab 5: Clock gating enabled RTL Synthesis of the Flipflopcircuit studied .

1. The below picture can be seen after typing the above command.Lets do the Synthesis first. Invoke RTL Compiler by typing ―rc -gui‖ on your terminal window. The tool window look like the below image: Cadence Confidential 22 .

.r.The terminal will look like the below image after the tool is invoked. Give the path of the library w./lib‖ 23 Cadence Confidential .t to the directory you are in using the command: ―set_attribute lib_search_path . 2.

v }. The RTL files are in the directory name ―rtl‖: ―read_hdl {ff.g‖.3 Give the path of the RTL files with respect to the directory you are in using the below command: ―set_attribute hdl_search_path .. 6 Now Elaborate the design using ―elaborate‖command./rtl‖ 4 Read the library from the directory specified in giving the path for the library files in step 2 using the command: ―set_attribute library slow.lib‖ is the name of the library file in the directory ―library‖. Cadence Confidential 24 .lib‖.Give the command ―gui_show‖ to see the circuit in Tool window: The terminal window after the step 7 will look like The Tool window looks like image on next page 8.lib‖ ―slow_normal. 5 Read the RTL files from the directory specified in the path in step 3. Give the standard delay constraints using: ―read_sdc . Any one of these two libraries could be used at a time. 7 . The terminal window looks like the image on next page./constraints_top. There is another library there in that directory with name ―slow_highvt.

Synthesize the circuit using the command: ―synthesize -to_mapped -effort medium‖.9. The terminal window and the synthesized circuit in tool window will appear to be as on next page: Cadence Confidential 25 .

? 10. Similarly for Gates ―report gates‖. 11.v‖ ―ff_synth. How much area do you observe ? …………………………… Cadence Confidential 26 . Write the hdl code in terms of library components for the synthesized circuit using the command: ―write_hdl >> ff_synth. Similarly write the constraint file using ―write_sdc >> ff_synth. 13. 12.sdc‖.v‖ is the name of file in which the code gets written.Now report power of design using ―report power‖ in terminal Note down from the report: Leakage : Dynamic : Total: Report timing to determine the critical path using ―report timing‖ command : How much slack do you observe ? ……………………ps If the slack is negative how would you optimize the design . Check area using ―report area‖.

Enabling Clock Gating Now re-synthesize design with clock gating . Synthesize the design script by below command rc –f setup.g file and see the added attribute.g Cadence Confidential 27 . set the following attribute: set_attr lp_insert_clock_gating true / Open setup. Circuit with Flip-Flops Circuit with Flip-Flops clock gated To ensure that clock-gating logic is inserted during synthesis.

............ Note down the values below..... Leakage : Dynamic: Total: How much percentage of improvement in dynamic power ?......... Cadence Confidential 28 .........% What is the impact on timing? Slack difference............After the Synthesis do ―report power‖..........

lib} set_attr library slow. set_attr lib_search_path .lib read_hdl alu../constraints.Then move to the work directory. Move to lab6 . Open setup.. Read the library from the directory specified in giving the path for the library files in step 2 using the command: ―set_attr library slow.g by typing below command nedit setup. Set the library directory path where library files are stored..g You will find the below code set_attr lib_search_path . In this lab we will do the Synthsesis and Physical Design of ALU Design for which Synthesis will be done using RTL Compiler and Physical Design will be done using Encounter Digital Implementation System.lib‖ is the name of the library file in the directory ―library‖./lib 2.lib‖.g synthesize -to_mapped report timing Let us understand the script. Do listing to see the directories ‗ls‘./rtl‖ 3.g file. cd work. 1.. Here you will find setup.v elaborate read_sdc . Give the path of the RTL files with respect to the local directory ―set_attr hdl_search_path ./lib set_attr hdl_search_path .lib‖ ―slow. There is another library there in that directory with name ―fast./rtl set_attr library {slow.Lab6: Synthesis and Automatic layout generation followed by simulation of the ALU circuit studied. The RTL files are in the directory name ―rtl‖: Cadence Confidential 29 . Any one of these two libraries could be used at a time. Lets do the Synthesis first. 4 Read the RTL files from the directory specified in the path in step 3.

g‖ on your terminal window as given below Type ― gui_show‖ in the terminal to see graphic window .―read_hdl alu. 6 Give the command to see the circuit in Tool window: The terminal window after the step 7 will look like The Tool window looks like image on next page 7. Synthesize the circuit using the command: ―synthesize -to_mapped‖.v 5 Elaborate the design using ―elaborate‖ command. 8. ―report timing‖ 10.g‖. Report the critical path of the design. Cadence Confidential 30 ./constraints. Give the standard delay constraints using: ―read_sdc . 9. Now synthesize the design by executing below command in the terminal/ Execute the script by typing ―rc –f setup.

Write the hdl code in terms of library components for the synthesized circuit using the command: ―write_hdl >> alu. Check Power dissipation using ―report power‖. Check area using ―report area‖.Physical Design can be done by invoking the tool ―Encounter Digital implementation‖. 15. Timing could be check using ―report timing‖. 17. Invoke the tool using ―encounter‖ . 16.v‖ is the name of file in which the code gets write. Similarly write the constraint file using ―write_sdc > > alu.v‖ ―alu.Report power by using below command in terminal ―report power‖ What do find for the below column 11.The tool starts as below image: Cadence Confidential 31 . 14. 18.sdc‖. After the Synthesis . Similarly for Gates ―report gates‖. 12.

The terminal window and tool window can be seen as similar to images on next page Cadence Confidential 32 .

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Go the Tool window and click on the File and select Import Design. A new window ―Netlist files‖ will open. 19. Cadence Confidential 34 . A new window will open. Select the verilog files using browse button.

For maximum timing libraries select all libraries with ―slow‖ in their name and for minimum timing libraries select all libraries with fast in their names. 21.lib‖ in space in front of Maximum Timing Libraries.lef‖ in the lef directory./lib/*fast*./lib/*slow*. 22. Similarly select the lef file by clicking the browse button and then add the lef file with name ―all.20. 23.sdc‖ for timing constraint file. instead of selecting all the libraries for Maximum timing libraries.v‖ and click the Add button and then click the close button. 24.lib‖. This will select all the slow libraries. Click on Auto assign after top cell. Alternatively. type ―.. Select the timing libraries. Similarly select ―alu. Click on the arrow button >> and select the verilog File ―alu_netlist.. The Design Import window will look like the image on next page 35 Cadence Confidential . Similarly in front of Minimum Timing Libraries write ―.

The screen shot is shown in the next page. In the Design Import window click on Advanced Tab. Select Power out of the list on the left side of window. Cadence Confidential 36 .25. Enter the power nets as VDD and Ground nets as VSS.

Cadence Confidential 37 .26. The tool window will look like image on next page. Select OK.

Cadence Confidential 38 .This is floorplan view of the design.

―Core to right‖. Click OK and the Tool window will be look like as below. ―Core to top‖. give 20 to each.27. Click on Floorplan and select ―Specify Floorplan‖. Select the Aspect Ratio as per the requirement. Set aspect ratio to 1. e. Cadence Confidential 39 .g. This is to create the space for Power rings which will be created in power planning. Give some dimension in ―Core to left‖.―Core to bottom‖.

Click on Power .28. Next step is to do global net connect .Connect Global Nets A browser opens as shown in the next page Cadence Confidential 40 .

then click on ―Add to in list‖ .so that it is added in Connection List column as shown next page . Cadence Confidential 41 .After crating global net connect for VSS . click Apply button close the Global Net Connection window. Similarly global net connect has to created to VSS as described above .In the ―To Global Net‖ Column type VDD Select ―Pin‖ button from Connect and in Pin Names(s) type VDD .

Click on Power. Cadence Confidential 42 . select power planning and click on Add Rings. Equivalent tcl command : globalNetConnect VDD -type pgpin -pin VDD -inst * -module {} globalNetConnect VSS -type pgpin -pin VSS -inst * -module {} Next step is power planning.29.

Set the width as per the requirement ex 5 and taking the space between core boundary and I/O pad considerations. Left and Right as Metal6. Cadence Confidential 43 .30. Select the option for offset as ―center in channel‖ and click OK. Select the top and bottom layer as Metal5. The power ring will get created in between the channel. The image on the next page is showing the power ring created.

32 Click OK on Place window and in physical view the blue coloured standard cells can be seen as a result of placement of standard cells. A new Window Place will appear. go to ―Place‖ and click Place Standard Cells. Cadence Confidential 44 .31 After the power planning.

33 Click OK with all default settings. Cadence Confidential 45 . This is done to provide power to standard cells. The horizontal blue coloured metal1 stripes created as a result of Special Route.

Cadence Confidential 46 .because we are doing Sroute for standard cells as shown in the next page.34 Now we power routing has to be done for the placed standard cells.For power routing .When the window opens unckeck the Block Pins Pad Pins and Pad Rings . click on Route and select Special Route .

Click on OK to power route for the standard cells. Cadence Confidential 47 .

and select Report Timing.35 Before CTS. Cadence Confidential 48 . A Timing analysis window will get open. Click on Timing. In the window select the ―Pre-CTS‖ as Design Stage and select the ―Setup‖ as Analysis Type. timing analysis has to be done for any setup violations.

The terminal will look as the image below and Tool window as on next page. Cadence Confidential 49 . check for any negative value under WNS(Worst Negative Slack) and TNS(Total Negative Slack).36 Click OK to complete the Timing analysis. The timing information will get display on terminal in tabular form. In the table displayed on the terminal under ―timeDesign Summary‖.

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If any part of this design is Zoom-in. Cadence Confidential 51 . click Optimize in Tool window and Select Optimize Design. Different colours show different metal 37 If there is any of the negative slack value under WNS or TNS. A new window ―Optimization‖ will get open.The multi-coloured lines visible in the tool window are the connections between standard cells using metal layers. The tool will optimize the design and the optimized timing results will be displayed over terminal again. Select ―Pre-CTS‖ as Design Stage and ―Setup‖ as optimization type and click OK. metal layers can be viewed easily.

a new window ―Synthesize Clock Tree‖ will get open. Cadence Confidential 52 . so this step is skipped here. 38 Go to Clock. click ―Synthesize Clock Tree‖.In this case we did not get any negative slack.

39 Click on Gen Spec and a new window ―Generate Clock Spec‖ will open. Cadence Confidential 53 .

Then specify a name for Results Directory. 41 Click OK. Select all clocks starting with ―CLK‖ and click on Add button to add them to the Selected Cells. Select a name for Output specification. and click OK. The tool window looks like the image below. Cadence Confidential 54 .40 From Cells List.

Cadence Confidential 55 .42 Again Perform the Timing by clicking on Timing and selecting Report Timing. Select ―Post-CTS‖ under Design Stage and do the select ―Set-up‖ as Analysis Type.

The timing information will be displayed over the terminal window. Cadence Confidential 56 . Again check for any negative slacks under WNS or TNS.43 Click Ok to perform the timing.

45 Timing Analysis for ―Setup‖ as Analysis Type is done.44 If there is any negative value found for either of WNS or TNS then perform the Optimization Technique to reduce the negative slack. Cadence Confidential 57 . No negative slack is found in the terminal image on previous page so this step is skipped here. Repeat Step 42 for performing timing for ―Post CTS‖ as Design Stage and ―Hold‖ as Analysis Type. The tool will show the timing results in the terminal window.

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Perform the Optimization. Select ―Post-CTS‖ and ―HOLD‖ as the Optimization Type. the timeDesign Summary is showing the negative slack values for both TNS and WNS. Cadence Confidential 59 . Go to Optimize and click on Optimize Design.46 After Timing Analysis is performed.

47 Click OK to perform the Optimization and Tool will perform the optimization and displays the optimized results in the terminal window under timeDesign Summary. As compare to the Timing Results performed for Hold mode in Step 46. The results of Optimization can be seen on the next page in tabular form for both Setup and Hold mode. Cadence Confidential 60 . the design has been optimized and tabular results shows that all slack values are now positive values and no more negative values for slack.

Now we have to connect all new cells to VDD/GND Type below commands in the terminal globalNetConnect VDD -type tiehi globalNetConnect VDD -type pgpin -pin VDD -override globalNetConnect VSS -type tielo globalNetConnect VSS -type pgpin -pin VSS -override 48 Perform Routing by clicking Route. Cadence Confidential 61 . and select NanoRoute and then click Route. A window NanoRoute will open.

Cadence Confidential 62 . The tool will Perform the Routing and the Routing statistics can be seen on terminal window including DRC violations.Equivalent tcl command # Run global Routing # utilizes the nano router globalDetailRoute 49 Click Ok to Perform Routing.

After routing tool window looks like the below image. Cadence Confidential 63 .

The timing results will be displayed in terminal window for Set up mode. Cadence Confidential 64 .50 Perform the timing again. Go to Timing. select Report Timing and a Timing Analysis window will get open. Select ―Post-Route‖ as the Design Stage and ―Setup‖ as Analysis Type. Click Ok.

Click OK.Since there is no negative value of slack so design does not require optimization for Setup mode in Post-Route stage. 51 Repeat step for ―Post-Route‖ as Design Stage and ―Hold‖ as the Analysis Type. The timing results can be seen in the terminal window for hold mode. Cadence Confidential 65 .

The final view of the circuit is as below: Write the final gds file Go to File – Save – GDS/OASIS Cadence Confidential 66 .As there is no negative value of slack. the optimization is not required to perform.

gds -mapFile streamOut.map -libName DesignLib -units 2000 -mode ALL Cadence Confidential 67 .Equivalent tcl command: streamOut final.

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