DS1643/DS1643P Nonvolatile Timekeeping RAMs



§ Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source § Clock Registers are Accessed Identically to the Static RAM. These Registers Reside in the Eight Top RAM Locations. § Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power § Access Times of 70ns and 100ns § BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Up to 2100 § Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance § Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time § DS1643 Only (DIP Module) Standard JEDEC Byte-Wide 8K x 8 RAM Pinout UL Recognized § DS1643P Only (PowerCap Module Board) Surface Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-Fail Output Pin-for-Pin Compatible with Other Densities of DS164XP Timekeeping RAM

TOP VIEW N.C. A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 28 27 2 DS1643 26 3 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 14 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3

Encapsulated DIP (700-mil Extended)


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17





34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18

N.C. N.C. N.C. N.C. A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

PowerCap Module Board (Uses DS9034PCX PowerCap)

PART DS1643-70+ DS1643-70 DS1643+100 DS1643-100 DS1643P-70+ DS1643P-70 DS1643P+100 DS1643P-100 VOLTAGE RANGE (V) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 TEMP RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C PIN-PACKAGE 28 EDIP (0.740a) 28 EDIP (0.740a) 28 EDIP (0.740a) 28 EDIP (0.740a) 34-PowerCap* 34-PowerCap* 34-PowerCap* 34-PowerCap* TOP MARK DS1643+70 DS1643-70 DS1643+100 DS1643-100 DS1643P+70 DS1643P-70 DS1643P+100 DS1643P-100

*DS9034-PCX, DS9034I-PCX, DS9034-PCX+ required (must be ordered separately).
A “+” indicates a lead-free product. The top mark will include a “+” symbol on lead-free devices.

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REV: 042705

X2. Ground Crystal Connection. A12 A7 A6 A5 A4 A3 A2 A1 A0 A10 A11 A9 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE OE CE2 WE VCC PFO GND X1.C. 2. 3. Battery Connection 2 of 16 . VBAT No Connection FUNCTION Address Inputs Data Input/Output Active-Low Chip-Enable Input Active-Low Output-Enable Input Chip-Enable 2 Input (Active High) Active-Low Write-Enable Input Power-Supply Input Active-Low Power-Fail Output.DS1643/DS1643P PIN DESCRIPTION PDIP 1 2 3 4 5 6 7 8 9 10 21 23 24 25 11 12 13 15 16 17 18 19 20 22 26 27 28 — 14 — PIN PowerCap 1. This open-drain pin requires a pullup resistor for proper operation. 31–34 30 25 24 23 22 21 20 19 18 28 29 27 26 16 15 14 13 12 11 10 9 8 7 — 6 5 4 17 NAME N.

minutes. day. However. This design allows the PowerCap to be mounted on top of the DS1643P after the completion of the surface mount process. EPROM and EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. lithium energy source. After a halt is issued. The 28pin DIP style module integrates the crystal. updating is halted. Updating is halted when a one is written into the read bit. halting the internal clock register updating process does not affect clock accuracy. However. All of the DS1643 registers are updated simultaneously after the clock status is reset. internal updates to the DS1643 clock registers should be halted before clock data is read to prevent reading of data in transition. CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data. that is day. Corrections for the day of the month and leap year are made automatically.DS1643/DS1643P DESCRIPTION The DS1643 is an 8K x 8 nonvolatile static RAM with a full function Real Time Clock (RTC) that are both accessible in a byte-wide format. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. hours. the registers reflect the count. 3 of 16 . Updating is within a second after the read bit is written to 0. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to high temperatures required for solder reflow. PowerCap is a registered trademark of Dallas Semiconductor. the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. The PowerCap is keyed to prevent reverse insertion. the seventh most significant bit in the control register. As long as a 1 remains in that position. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. and time that was current at the moment the halt command was issued. month. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The nonvolatile timekeeping RAM is functionally equivalent to any JEDEC standard 8K x 8 SRAM. PACKAGES The DS1643 is available in two packages: 28-pin DIP module and 34-pin PowerCap® module. The device can also be easily substituted in ROM. which deselects the device when the VCC supply is in an out of tolerance condition. The DS1643 also contains its own power-fail circuitry. The 34pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. The RTC registers contain year. and silicon all in one package. date. and seconds data in 24-hour BCD format. The part number for the PowerCap is DS9034PCX. The real time clock information resides in the eight uppermost RAM locations. date.

halts updates to the DS1643 registers. like the read bit. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. the LSB of the seconds register will toggle at 512Hz. 4 of 16 .DS1643/DS1643P Figure 1. date and time data in 24 hour BCD format. and address for seconds register remain valid and stable). OE low. Block Diagram DS1643/ DS1643P Table 1. Setting the write bit to a 1. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time.. To increase the shelf life.e. The user can then load them with the correct day. The OSC bit is the MSB for the seconds registers. When the seconds register is being read. the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid (i. CE2 high. Truth Table VCC 5V ±10% <4.5V > VBAT <VBAT CE VIH X VIL VIL VIL X X CE2 X VIL VIH VIH VIH X X OE WE X X X VIL VIH X X X X VIL VIH VIH X X MODE Deselect Deselect Write Read Read Deselect Deselect DQ High Z High Z Data In Data Out High-Z High-Z High-Z POWER Standby Standby Active Active Active CMOS Standby Data Retention Mode SETTING THE CLOCK The 8-bit of the control register is the write bit. Setting it to a 1 stops the oscillator. When the frequency test bit is set to logic 1 and the oscillator is running. the oscillator can be turned off to minimize current drain from the battery. CE low.

DS1643/DS1643P CLOCK ACCURACY (DIP MODULE) The DS1643 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable. If CE or OE access times are not met. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. The start of a write is referenced to the latter occurring transition of WE or CE . The state of the data input/output pins (DQ) is controlled by CE and OE . the OE signal will be high during a write cycle. The addresses must be held valid throughout the cycle. In a typical application. the module is guaranteed to keep time accuracy to within ±1. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. Register Map—Bank1 ADDRESS 1FFF 1FFE 1FFD 1FFC 1FFB 1FFA 1FF9 1FF8 OSC = STOP BIT W = WRITE BIT B7 — X X X X X OSC W B6 — X X Ft X — — R B5 — X — X — — — X DATA B4 B3 — — — — — — X X — — — — — — X X B2 — — — — — — — X B1 — — — — — — — X B0 — — — — — — — X FUNCTION Year Month Date Day Hour Minutes Seconds Control RANGE 00-99 01-12 01-31 01-07 00-23 00-59 00-59 A R = READ BIT X = UNUSED FT = FREQUENCY TEST Note: All indicated “X” bits are not used but must be set to “0” for proper clock operation. 5 of 16 . However. If the address inputs are changed while CE and OE remain valid. If the outputs are activated before tAA .53 minutes per month (35ppm) at 25°C. A low transition on WE will then disable the outputs tWEZ after WE goes active. providing that the CE and OE access times and states are satisfied. valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). RETRIEVING DATA FROM RAM OR CLOCK The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. OE can be active provided that care is taken with the data bus to avoid bus contention. output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1643 is in the write mode whenever WE and CE are in their active state. the data lines are driven to an intermediate state until tAA. Once mounted together. CLOCK ACCURACY (POWERCAP MODULE) The DS1643P and DS9034PCX are each individually tested for accuracy. Table 2.

and clock data are maintained from the battery until VCC is returned to nominal level. Actual life expectancy of the Ds1643 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. guaranteeing full energy capacity. At this time the power-on reset output signal ( RST ) will be driven active low and will remain active until VCC returns to nominal levels. 6 of 16 . This is accomplished internally by inhibiting access via the CE signal.5V) the DS1643 can be accessed as described above with read or write cycles. data. Except for the RST .DS1643/DS1643P DATA RETENTION MODE When VCC is within nominal limits (VCC > 4. RAM. power input is switched from the VCC pin to the internal battery and clock activity. all control. the life expectancy is 10 years at 25°C with the internal clock oscillator running in the absence of VCC power. The RST signal is an open drain output and requires a pull up. Each DS1643 is shipped from Dallas Semiconductor with its lithium energy source disconnected. and clock and RAM data retention when the VCC supply is not present. when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and RAM are blocked from access. BATTERY LONGEVITY The DS1643 has a lithium power source that is designed to provide energy for clock activity. For specification purposes. However. When VCC is first applied at a level greater than VPF. and address signals must be powered down when VCC is powered down. The capability of this internal power supply is sufficient to power the DS1643 continuously for the life of the equipment in which it is installed. When VCC falls below the level of the internal battery supply. the lithium energy source is enabled for battery backup operation.

RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER Supply Voltage Logic 1 Voltage All Inputs Logic 0 Voltage All Inputs SYMBOL VCC VIH VIL MIN 4.1mA) Write Protection Voltage SYMBOL ICC ICC1 ICC2 IIL IOL VOH VOL VPF 4. 3 2.) PARAMETER Active Supply Current TTL Standby Current ( CE = VIH.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.DS1643/DS1643P ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground…………………………………………….37 -1 -1 2.3V to +7.. CE2 = VIL) CMOS Standby Current ( CE = VCC .0. CE2 = GND + 0. Noncondensing Soldering Temperature………………………………See IPC/JEDEC J-STD-020A Specification (Note 7) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.5 VCC + 0.2V. TA = 0°C to +70°C.3 TYP 5.25 4.4 4.5 2. 3 2.0V Operating Temperature Range………………………………………………0°C to +70°C. 3 7 of 16 .0 MAX 5. Noncondensing Storage Temperature Range………………………………………………-40°C to +85°C.3 +0.2 -0.0V ±10%.-0.4 0.50 V MIN TYP 15 1 1 MAX 50 3 3 +1 +1 UNITS mA mA mA mA mA 1 1 1 NOTES 2. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.0mA) Output Logic 0 Voltage (IOUT = +2.8 UNITS V V V NOTES DC ELECTRICAL CHARACTERISTICS (VCC = 5.

0V ±10%.) PARAMETER Read Cycle Time Address Access Time CE and CE2 to DQ Low-Z CE Access Time SYMBOL tRC tAA tCEL tCEA tCE2A tCEZ tOEL tOEA tOEZ tOH CE2 Access Time CE and CE2 Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address 70ns ACCESS MIN MAX 70 70 5 70 80 25 5 35 25 5 100ns ACCESS MIN MAX 100 100 5 100 105 35 5 55 35 5 UNITS ns ns ns ns ns ns ns ns ns ns NOTES 4 4 4 4 4 4 4 4 4 4 READ CYCLE TIMING DIAGRAM 8 of 16 .DS1643/DS1643P AC CHARACTERISTICS—READ CYCLE (VCC = 5. TA = 0°C to +70°C.

TA = 0°C to +70°C.) PARAMETER Write Cycle Time Address Setup Time WE Pulse Width CE Pulse Width SYMBOL tWC tAS tWEW tCEW tCE2W tDS tDH tAH tWEZ tWR CE2 Pulse Width Data Setup Time Data Hold Time Address Hold Time WE Data Off Time Write Recovery Time 70ns ACCESS MIN MAX 70 0 50 60 65 30 0 5 25 5 100ns ACCESS MIN MAX 100 0 70 75 85 40 0 5 35 5 UNITS ns ns ns ns ns ns ns ns ns ns NOTES 4 4 4 4 4 4 4 4 4 4 9 of 16 .0V ±10%.DS1643/DS1643P AC CHARACTERISTICS—WRITE CYCLE (VCC = 5.


Before Power-down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Fall Time: VPF(MIN) to VBAT VCC Rise Time: VPF(MIN) to VPF(MAX) Power-Up Recover Time Expected Data Retention Time (Oscillator On) SYMBOL tPD tF tFB tR tREC tDR MIN 0 300 10 0 TYP MAX UNITS ms ms ms ms ms years NOTES 35 10 5.) PARAMETER CE or WE at VIH. CE2 at VIL.0V ±10%. TA = 0°C to +70°C.DS1643/DS1643P POWER-UP/DOWN AC CHARACTERISTICS (VCC = 5. 6 POWER-UP/POWER-DOWN TIMING CAPACITANCE (TA = +25°C) PARAMETER Capacitance on All Pins Capacitance on All Output Pins SYMBOL CIN CO MIN TYP MAX 7 10 UNITS pF pF NOTES 11 of 16 .

5V Output: 1. b. heat the lead frame pad and apply solder. heat the lead frame pad until the solder reflow and use a solder wick to remove solder. 4) The CE2 control signal functions exactly the same as the CE signal except that the logic levels for active and inactive levels are opposite. apply flux to the pad. 6) Each DS1643 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 2) Typical values are at +25°C and nominal supplies. Post-solder cleaning with water washing techniques is acceptable. 7) Real-Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. 5) Data retention time is at 25°C. provided that ultrasonic vibration is not used.0V Timing Measurement Reference Levels: Input: 1. for the PowerCap: a. apply flux.DS1643/DS1643P AC TEST CONDITIONS Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0 to 3. To remove the part. To solder. In addition. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds. 12 of 16 . 3) Outputs are open. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up (“live-bug”).5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltages are referenced to ground.

com/DallasPackInfo.67 0.675 0.025 0.38 0.91 2.25 0. MM H IN.018 0.105 1.00 0.DS1643/DS1643P PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications.470 1. MM D IN.56 4.630 14.80 0.140 0.490 37.34 37.58 13 of 16 .) DS1643 28-PIN PACKAGE PKG DIM A IN.015 0.180 3.79 0. MM E IN.02 0. MM K IN. MM 28-PIN MIN MAX 1. MM C IN.090 0.57 0. MM B IN.75 18.maxim-ic.030 0.51 9. go to www.43 0. For the latest package outline information.85 0.015 0.075 0.315 0.740 17.45 0.110 2.335 8.76 0.99 16. MM G IN.29 2.590 0. MM F IN.010 0. MM J IN.


055 0.020 0.930 0.960 0.955 0.025 MAX 0.058 0.050 0.048 0.030 15 of 16 .240 0.250 0.020 INCHES NOM 0.015 0.920 0.052 0.052 0.DS1643/DS1643P DS1643P WITH DS9034PCX ATTACHED PKG DIM A B C D E F G MIN 0.925 0.245 0.025 0.965 0.

030 0. . Maxim Integrated Products. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. 120 San Gabriel Drive. Sunnyvale. Inc. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. CA 94086 408-737-7600 © 2005 Maxim Integrated Products · Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products.050 0. No circuit patent licenses are implied.DS1643/DS1643P RECOMMENDED POWERCAP MODULE LAND PATTERN PKG DIM A B C D E INCHES NOM 1.050 0.112 MIN - MAX - 16 of 16 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.826 0.