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1. Institute of Microelectronic, Tsinghua University, Beijing, China
I
ma96588@umac. mo
2. Analog and Mixed Signal VLSI Laboratory, FST, University of Macau, Macau, China
2
TerySSW@umac.mo
3. On leave fom Instituto Superior Tecnico/TU of Lisbon, Portugal
AbstractThis paper presents a pipelined successive
approximation register analogtodigital converter (SAR ADC)
for biomedical applications based on ôb nm CMOS technology.
Without using opamp, the proposed 9bit pipelined SAR ADC
can reduce the capacitance from b12L to 64C. The pipelined
architecture can enhance the operation efciency of the ADC and
also save the digital power consumption in the SAR. The
simulation results show that the total power of the ADC is 1Ü.2ô
JW only, and the fgure of merit (FOM) of the ADC is 2ö.ò
fJ/conversionstep.
Keywords SAR ADC; pipelned; ultralow power; biomedical
applications.
I. I NTRODUCTION
With the development of the healthcare electronics system,
there is an increasing demand for portable and wearable
devices to continuously monitor vital biosignals such as ECG,
EMG and AAP, etc, whose fequencies span fom DC to a few
MHz [1]. The analogtodigital converter (ADC) with Mega
Hertz conversion rate is required to convert the vital signals to
the digital form which can be analyzed by the digital processor.
To maximize the battery life, energyefcient ADCs are
needed. The Successive Approximation Register (SAR) ADC
architecture is well suitable for largescale wireless sensor and
biomedical applications due to its moderate speed, resolution
and very lowpower consumption.
An Nbit charge redistribution SAR ADC consists of N+ 1
capacitors having a total capacitance of 2
N
Co, where Co is the
unit capacitance. Due to this large capacitance, the power is
proportional to the charge/discharge of the capacitor array by
the switch sequence. The conventional capacitor array
consumes more power in charging and discharging the
capacitor array. Meanwhile, the ADC uses the bottom plate of
the capacitor array to sample the input signal. To drive such
large capacitive load, a powerhungry buffer is demanded
before the ADC. All these consume signifcant power [2].
This paper proposes a lowpower 9bit IMS/s pipelined
SAR ADC without the use of any opamps. With the pipe lined
architecture, the conversion rate in each stage can be relaxed
thus reducing the digital power which is the domination in the
SAR ADC. In addition, the proposed ADC also reduces the
978142448157 6/1 0/$26.00 ©20 10 IEEE
sampling capacitance and save the power of the switch buffers,
as well as the input driver of the ADC.
II. PROPOSED ADC ARCHITECTURE
As shown in Fig. 1, the proposed 9bit pipelined SAR ADC
architecture consists of a 5bit coarse stage, a 5bit fne stage, a
clock generator and a digital error corection circuit. Each stage
is mainly composed by a set of binary weighted capacitor DAC
array, a comparator and 5bit successive approximation
registers, etc. The switch S1 connects the MSB DAC array in
coarse stage and the LSB DAC array in fne stage to share the
charge during pipe lined operation. The controlling phases are
generated fom the clock generator. To alleviate the error
induced by the comparators and DAC arrays, the digital error
correction is applied to combine the coarse 5bit and the fne å
bit digital code to the fnal 9bit output code. The circuit blocks
are explained in detail in the next section.
The timing diagam of the ADC is shown in Fig. 2. Firstly,
the MSB DAC array samples the input signal with the
*a
*:rì
¯*:rì
*.· r:
""� *:rn
vbtDgtaItodt
Fig.l. A proposed 9bit twostage pipelined AC architecture
5amglc_loarsclonvcrsion
5haring
¯
línclonvcrsíon
llcar ¯
5Irobc1
5Irobc2
Fig.2. Timing diagram of pipe lined SAR ADC
878 ICECS 2010
Fig.3. A IObit conventional SA ADC.
bootstrapped switch [3] by the "sample" clock phase. Afer
sampling, the "strobe 1" activates the coarse stage comparator
to perform the 5bit coarse conversion with the MSB DAC
aray. The residue signal is produced in the MSB DAC while
the coarse conversion is completed. Then, the switch S1 is
tured on in the "sharing" phase, and the MSB DAC share the
charge of residue to the LSB aray. Before the sharing, the
memory charge of the LSB DAC array is cleared by the "clear"
phase to avoid the nonlinearit effect. Afer sharing, the LSB
DAC array starts the 5bit fne conversion, where the fne stage
comparator is triggered by the "strobe2". Meanwhile, the
coarse stage samples the new input and starts the next coarse
conversion in pipe lining fashion.
I I I. SWITCHIG SCHEME OF PROPOSED PIPELED SAA DC
Same as the conventional SAR ADC, the proposed
pipe lined SAR follows the binary search algorithm to perform
the quantization, but the quantization is split as two steps and
operates as a pipe lined scheme. Fig. 3 shows a conventional
10bit SAR ADC, which consists of a comparator, SAR logic,
and a lObit binary weighted capacitive DAC array. ±VrefJ are
the reference voltages for the switching of the IObit DAC
array. By the binary search algorithm, the output voltage of the
DAC (the top plate of the capacitors) Vxcan be expressed as
` ]
I0
]
_
Y
¯Í ¬Y ±¬
_
Y ± ¨ ¨
�
IH
_'
_'¯` _`
(I)
where N¡¿ is the sampled input signal, Bi is the comparison
result in the ibit conversion cycle. Supposing there is another
reference voltage Vret, and the relationship between Vrefl and
Lo8räc hI8gc
� ...............
'.«
\
nn
\,,ç¡ �
bbíI ¾hU UAL
Vret is given as below:
Therefore, the eq. (1) can be expressed as
5 h 5 h
5
í\~ l ~ l ¬ _ �2í ¬ _ 2í
/
n
º!¡
/
~ ¡
_ ºÍ
¡
/
~ ¡ 2
/ º!!
(2)
(3)
Eq. (3) reveals that the single step IObit quantization of SAR
ADC can be equalized as a twostep scheme, where the IObit
DAC array should be split as two 5bit DAC arrays with
different reference voltages.
Fig. 4 shows the circuit diagram of the capacitive DAC
arrays of the proposed pipe lined SAR ADC in singleend
scheme, which are implemented differentially in transistor
level. The 5bit MSB and 5bit LSB DAC arrays are perfored
the switching with ±Vrefl and ±Vret, respectively. The 5bit
coarse code is quantized in the coarse stage, where the output
voltage VX1 of the MSB DAC can be derived as
(4)
Fig. 5 shows the switching of MSB and LSB DAC arrays in
sharing phase. Afer the switch S1 is tued on, the LSB DAC
can share a half of charge fom the MSB, since the identical
capacitance of the 5bit DAC arrays. The sharing charges
contain the residue information which is the both input signal
and coarse code, where the coarse code is ' 110 11' as an
example in Fig. 5. Supposing that the LSB DAC is cleared
before S1 is on and the bottom plate of the LSB DAC connects
to Vy during the charge sharing, the LSB array's output VX2
can be calculated as
Ì Ì Ì
·
D¸ Ì
·
¯ ~
· 
,
·
~
,
,
''
,
.
,
,
.
,
Afer sharing, the switch S1 is tured off and the fne
conversion starts in the LSB array. The top plate voltage
on the LSB array, VX2 becomes as
(5)
Ì
·
D¸ � D
_
·
,
·.,
·,
¯
"(Vn ·.
�¸
,
·.
·
,
·.,
,
�
(6)
Since the output voltage of the LSB DAC array must be
equivalent to eq. (3) dividing by half during the fne
línchI8gc

I
�
'
¸,_
������� �'.·
bbíI lhU UAL
8
8
8
8
8
¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬¬4
Fig.4. Capacitive DAC arrays of the proposed pipeline SA ADC
879
Fig.5. Circuit diagram of MSB and L SB DAC arrays in shaing phase for
equation (5)
S¡
¯
¾hHArruy g
Fig.6. Precharging of L SB DAC arrays in clea phase
Fig.7. Circuit diagram of MSB and L SB DAC arrays in shaing phase with
determined L SB reference voltage
conversion, Vy can be derived fom eq. (3) and eq. (6) as
(7)
Eq. (7) means that, in order to implement the correct binary
search algorithm during the fme conversion, the bottom plates
of the LSB DAC array should be connected with 2Vref at the
sharing phase. However, if te dynamic range of the ADC
approaches to the supply voltage, which is 1 Vp.p in 65 CMOS
process, the required reference voltages 12Vref1 will be higher
than the supply voltage. Therefore, the realizable switching of 
2Vref is accomplished in two phases. The LSB DAC array is
prechaged to Vref in the clear phase as shown in Fig. 6, ad
then the bottom plate of LSB DAC stays connected with Vref
in the sharing phase as shown in Fig. 7.
For the 5bit binary weighted capacitor array, the total
capacitance is 32C, where C is the unit capacitance. Compaing
to a 9bit conventional SAR ADC, the total capacitance in the
proposed pipeline SAR can reduce the capacitance fom 5I2C
to 2*32C. It can save the power consumption during the
charging of DAC, as well as the switching power dissipated on
the switch buffers. The energy dissipation of charging the
capacitor can be given as
(8)
where � V is the voltage difference between the capacitor. As
� V reduces to 1/32 for the switching of LSB DAC aray, it can
save the power drastically in the fne conversion [4].
880
IV. CIRCUIT I MPLEMENTATION
A. Comparator
The comparator circuit is employed by the dynamic latch
[5]. The autozeroed preamplifer is preceded to the dynamic
latch alleviating the comparator offset, with the gain of about
16. To improve the noise performance of the comparator, two
capacitors with IOf are connected to the output of the
comparator. Although the comparator' s settling time is
enlarged by the loading capacitors, it' s still short enough for
conversion in this design.
For the 9bit traditional SAR ADC with conversion rate of
fs, the speed of the comparator is requied as 1Ofs. Although m
this 1 MS/s ADC includes two comparators, the speeds of the
comparators are about 5 MS/s, only a half of the one in the
traditional SAR ADC. The power of two dynamic latches in
the proposed ADC will not consume more power compared to
the one in traditional SAR ADC, as it is proportional to the
conversion rate.
D. Digital Error Correction
The digital error correction is employed here to eliminate
the nonlinearity fom the comparator offsets in coarse and fne
stages. The IObit codes are processed in the digital error
correction with Ibit overlapping, where the last bit of the
coarse code and the frst bit of the fne code is combined into
one bit with digital addition. Finally, a 9bit output code is
obtained.
C Successive Approximation Registers
The successive approximation registers requires the D Flip
Flops to provide the approximation clock cycles. For the
traditional SAR ADC, Nbit ADC needs N+ 1 DFFs. In the
proposed 9bit ADC, only 6 DFFs are utilized instead of 11 D
FFs, since both the coarse and fne stages contain only 5
conversion cycles and share the DFF. Therefore, the speed of
the digital logics almost reduces to half and the digital power is
optimized.
à2H
¹�q'¹,,µ ¹....'¹.,p ¹.,..·¹;p ¹,,·¹.,µ
J1H H H J1H JZH
Fig.8. Resistive ladder providing the reference voltages ¹':
º
n +¹':
º
L
D. Reference Ladder
The reference voltages ±VrefJ and ±Vref ae generated fom
the resistive ladder, where I 28tap resistors are demanded. The
resistive ladder is shown as in Fig. 8. In this design, the tap
resistor is 1. 6 ÞÍ for the unit capacitance of 16 f in the DAC
arrays.
V. SIMULATION RE SULT S
The proposed pipe lined SAR ADC has been verifed with
transistorlevel simulation based on the 65nm CMOS
technology with high threshold option.
The static performance is characterized through the
differential nonlinearity (DNL) and integral nonlinearity (INL).
As shown in Fig. 9, the simulated DNL and INL are +0.46/
0.66 LSB and +0.37/0.53 LSB, respectively. Fig. 10 shows a
fequency spectum simulation @fi 403.3 KHz and I 1
MS/s with the SNDR of 53.0 dB. The 50 times MonteCarlo
simulations in Fig. 11 show that the proposed 9bit pipelined
SAR ADC SNDR can achieve an average of 53. 3 dB. Fig. 12
and Fig. 13 illustrate the SNDR of the ADC versus the input
fequency and the sampling rate variation, respectively.
For the fgure of merit �OM) [6] of the ADC which is
defned as FOM Power/(2
E
O
B
*fs), this work can be achieve
the FOM as 28. 3 f/conversionstep. The ADC simulation
results are summarized in the Table I.
VI. CONCLU SION
A 9bit 1 MS/s SAR ADC with pipelined architecture is
presented. By the pipe lined operation, the proposed ADC
reduces the digital consumption as well as the total capacitance.
The ADC consumes power 10.26 fW and achieves the FOM
28. 3 f/conversionstep at the maximum sampling rate.
O¡!1ÀA¡ O¡À¡¡À tOOL
U4 ~~ ~~�~~�~~�~~�
U.2
=
� U
= U,2
Z
" U4
U,( ..� ..� ..� ..� ..
0 IUU 2UU JUU 4UU UU
O1!¡ÀA¡ O1À¡1À tOOL
Fig.9. Simulated DNL and INL of the proposed ADC
0
2U
=
¯ 4U
W
±
¸� (U
G
]öU
1UU
[,,=401.1 Kuz
SNuR=S1dBµ,,=484.4Kuz
IUU ZUU JUU
requeney(kMz)
4UU JUU
Fig.IO. FFT of the digital output@.fn=403.3 kHz andf =1 MS/s.
.�
7
_Jl
o
<
Mcan5J.JdB
Num50
0 �
´l ´J ´² ´² ´÷ ´´ ´¹
SNDR [dB)
Fig.ll. Histogram of SNR of proposed novel ADC @.fn =484.4 KHz
andf =1 MS/s.
881
1::1 
_
_
¬
_
���_� _¬_ _

__
�
__
nputrequency(KHz)
Fig.12. Simulated SNDR versus input frequency @f =1 MS/s.
;=1
�
(
_
_
Û.
_
.
(
_
.0
_
.S
Samping rcqucncy(MHz)
ÌÛ Ì.
Fig.13. Simulated SNDR versus sampling rate.
TABLE I . ILklOkVAXCLSUMMAkY
O
F T!L PROPOSED ADC
Technology 65 nm Power Supply I I N
Resolution 9 bit Power Dissipation
Sampling Rate I MS/s Analog 4.371 fW
Dynamic Range 1.0 N¡¡·n Digital 0.791 fW
SNDR(@n=484.4kHz) 53.0 dB
Reference
5.098!W
ladder
DNL (L SB) +0.46/0.66 Total Power 10.26 fW
INL (LSB) +0.37/0.53 FOM
28.3
fconvs
ACKNOWLE DGMENT
This work was fnancially supported by Research Grants of
University of Macau and Macao Science ò Technology
Development Fund (FDCT)
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B. Nauta, "A 10bit ChargeRedistribution ADC Consuming 1.9 uW at I
MS/s," ÍlllJ SoliJStatcCircuits,vol. 45, no.5, pp. I 007 � 1015, May
2010 .
[5] G. Y. Huang, C. C. Liu; Y. Z. Lin, S. i. Chang, "A 10bit 12MS/s
successive approximation AC with 1.2pF input capacitance," Irocs.
Ílll HSSCC, pp. 157  160, Dec. 2009.
[6] 1.Craninckx, G. van der Plas, "A 65 fconversionstep 0to50 MS/s 0
to0.7 mW 9 b chargesharing SAR AC in 90 nm digital CMOS,"
Ílll ÍSSCC Lig. Icch. Iaµcrs, pp. 246247, Feb. 2007.
.3. 1 2 2 f:: 2' 2 V"fl +" . (3) reveals that the single step IObit quantization of SAR ADC can be equalized as a twostep scheme. 5bit MSB DAC v"n v. The residue signal is produced in the MSB DAC while the coarse conversion is completed...""'\ 5bit LSB DAC = 5 B.. 5 shows the switching of MSB and LSB DAC arrays in sharing phase.. (3) dividing by half during the fine Fine Stage /�"§... After the switch S1 is turned on. I I I.. and the relationship between Vrefl and Coarse Stage Since the output voltage of the LSB DAC array must be equivalent to eq. VX2 becomes as (I) VX2 where Yin is the sampled input signal. Before the sharing. the LSB array's output VX2 can be calculated as SAADC Same as the conventional SAR ADC. 5 B }O B 2V After sharing. . ±VrefJ are the reference voltages for the switching of the IObit DAC array... the LSB DAC array starts the 5bit fine conversion.. the LSB DAC can share a half of charge from the MSB. 4 shows the circuit diagram of the capacitive DAC arrays of the proposed pipelined SAR ADC in singleend scheme.J .L2V i ref! i =] 2 (3) Fig..f. and the MSB DAC share the charge of residue to the LSB array. Then.. the coarse stage samples the new input and starts the next coarse conversion in pipelining fashion.444�'!++<:::J Vrtf2 . By the binary search algorithm. Fig. the memory charge of the LSB DAC array is cleared by the "clear" phase to avoid the nonlinearity effect. S WITCHING SCHEME O F PROPO SE D PIPELINE D Eq.n V"fl + �2f2V"flVy 2V"j2 +2 f:: 2' �) (6) Vi" o++t"t. A IObit conventional SAR A DC.. +t' o++¥f4f4fl D++�.. the switch S1 is turned off and the fine conversion starts in the LSB array..!.. l.. since the identical capacitance of the 5bit DAC arrays.v in ref] + i 5 R. 5.2V"fl /I:y 2 on (5) = V V In ' refl +" '2Vrefl +" 215 � ft 21 ft 25 . Fig. . Supposing there is another reference voltage Vret2..Vret2 is given as below: (2) Therefore. The sharing charges contain the residue information which is the both input signal and coarse code.. the eq. Meanwhile....!L�������+�VITn I Fig. which consists of a comparator. · · · · · _. (1) can be expressed as Vx = v .. The top plate voltage on the LSB array.J. the "strobe 1" activates the coarse stage comparator to perform the 5bit coarse conversion with the MSB DAC array. where the output voltage VX1 of the MSB DAC can be derived as (4) Fig. 3 shows a conventional 10bit SAR ADC. where the IObit DAC array should be split as two 5bit DAC arrays with different reference voltages. L �2V i ref] = ] + 5 R.. the switch S1 is turned on in the "sharing" phase. � B'+5 2V"f2 1 "2(V.. Supposing that the LSB DAC is cleared before S1 is on and the bottom plate of the LSB DAC connects to Vy during the charge sharing. where the coarse code is ' 11011' as an example in Fig. where the fine stage comparator is triggered by the "strobe2". bootstrapped switch [3] by the "sample" clock phase. The 5bit MSB and 5bit LSB DAC arrays are performed the switching with ±Vrefl and ±Vret2.. which are implemented differentially in transistor level.. Capacitive DAC arrays of the proposed pipeline SAR A DC 879 . but the quantization is split as two steps and operates as a pipelined scheme. The 5bit coarse code is quantized in the coarse stage.. After sampling. After sharing.!.. Bi is the comparison result in the ibit conversion cycle. the proposed pipelined SAR follows the binary search algorithm to perform the quantization.. respectively.4.. the output voltage of the DAC (the top plate of the capacitors) Vxcan be expressed as VX2 = 1 V 1 15 B. 5 L . SAR logic. and a lObit binary weighted capacitive DAC array.
Reference Ladder The reference voltages ±VrefJ and ±Vref2 are generated from the resistive ladder. 8. the total capacitance in the proposed pipeline SAR can reduce the capacitance from 5I2C to 2*32C.5.f2 VernVrrn Eq. Comparing to a 9bit conventional SAR ADC. 880 . the required reference voltages 12Vref21 will be higher than the supply voltage. the speed of the digital logics almost reduces to half and the digital power is optimized. Finally. To improve the noise performance of the comparator. conversion. Vy can be derived from eq.Precharging of L SB DAC arrays in clear phase Digital Error Correction Fig. in order to implement the correct binary search algorithm during the fme conversion. For the 9bit traditional SAR ADC with conversion rate of fs. Therefore. (7) means that. For the traditional SAR ADC. where C is the unit capacitance. the speed of the comparator is required as 1Ofs.. the realizable switching of 2Vref2 is accomplished in two phases.p in 65 CMOS process. only 6 DFFs are utilized instead of 11 D FFs. where the last bit of the coarse code and the first bit of the fine code is combined into one bit with digital addition. r C Fig. Although the comparator's settling time is enlarged by the loading capacitors. However. 7. Nbit ADC needs N+1 DFFs. it' s still short enough for conversion in this design. Circuit diagram of M SB and L SB DAC arrays in sharing phase for equation (5) S. The autozeroed preamplifier is preceded to the dynamic latch alleviating the comparator offset. Although in this 1 MS/s ADC includes two comparators. the speeds of the comparators are about 5 MS/s.6.8. SIMULATION RE SULT S The proposed pipelined SAR ADC has been verified with transistorlevel simulation based on the 65nm CMOS technology with high threshold option. it can save the power drastically in the fine conversion [4].IV. Circuit diagram of M SB and L SB DAC arrays in sharing phase with determined L SB reference voltage The digital error correction is employed here to eliminate the nonlinearity from the comparator offsets in coarse and fine stages. The power of two dynamic latches in the proposed ADC will not consume more power compared to the one in traditional SAR ADC.6 Kn for the unit capacitance of 16 fF in the DAC arrays. two capacitors with IOfF are connected to the output of the comparator.orf2 VCTIlV . the bottom plates of the LSB DAC array should be connected with 2Vref2 at the sharing phase. The LSB DAC array is precharged to Vref2 in the clear phase as shown in Fig. The resistive ladder is shown as in Fig. (6) as (7) C. the total capacitance is 32C. the tap resistor is 1. B. (3) and eq. Therefore.7. with the gain of about 16.. CIRCUIT I MPLEMENTATION A.. as well as the switching power dissipated on the switch buffers. In the proposed 9bit ADC. V�rn+Vrrn VcllI+V. which is 1Vp. In this design. Resistive ladder providing the reference voltage s ±Vr fl and ±Vr f2 e e D. It can save the power consumption during the charging of DAC. The energy dissipation of charging the capacitor can be given as (8) �V 32R 31R R R 31R 32R Fig. only a half of the one in the traditional SAR ADC. As reduces to 1/32 for the switching of LSB DAC array. For the 5bit binary weighted capacitor array. Comparator Fig. since both the coarse and fine stages contain only 5 conversion cycles and share the DFF. as it is proportional to the conversion rate. and then the bottom plate of LSB DAC stays connected with Vref2 in the sharing phase as shown in Fig. Successive Approximation Registers The successive approximation registers requires the D Flip Flops to provide the approximation clock cycles. where �V is the voltage difference between the capacitor. The IObit codes are processed in the digital error correction with Ibit overlapping. MSB Array The comparator circuit is employed by the dynamic latch [5]. if the dynamic range of the ADC approaches to the supply voltage. V. where I28tap resistors are demanded. 6. a 9bit output code is obtained.
the simulated DNL and INL are +0. 11 show that the proposed 9bit pipelined SAR ADC SNDR can achieve an average of 53.J/conversionstep. A pr. C.6 0.00 � 1 00 4 . Chang. P.. Simulated SN DR versus input frequency@fs =1 M S/s. S.3 fJ/conversionstep at the maximum sampling rate. no.... vol. As shown in Fig.9. � 40 0 02 0. The ADC simulation results are summarized in the Table I..=484. Feb. Gray. 2010.500 Input Frequency (KHz) .7 mW 9 b chargesharing SAR ADC in 90 nm digital CMOS. Nauta.5. respectively. The 50 times MonteCarlo simulations in Fig.3 fJlconvs DIGITAL OUTPUT CODE .3 f. A 9bit 1MS/s SAR ADC with pipelined architecture is presented. Zou. S. C." IEEE ISSCC Dig. Abo. 2009.4 KHz andfs =1 M S/s. pp. 45. 1. 599606..fin =484. Elzakker." IEEE J Solid State Circuits.4 0.26 flW and achieves the FOM 28. respectively. "A 65 fJlconversionstep 0to50 M S/s 0to0. FFT of the digital output@. L ian. 12 and Fig." IEEE J Solid State Circuits.0 Vp.4 KHz This work was financially supported by Research Grants of University of Macau and Macao Science & Technology Development Fund (FDCT) RE FERENCE S [ I] X. D. pp.5V. PERFORMANCE SUMMARY OF T HEPROPOSED A DC 65 nm 9 bit I M S/s 1.3 KHz and Is 1 MS/s with the SNDR of 53. The ADC consumes power 10." IEEE J Solid State Circuits.2 Z .:. Z. L iu.pdiff 53. G.2p F input capacitance.0 Sampling Frequency (MHz) 1.791 flW 5.46/0.. Klumperink.0. IEEE ASSCC.. Papers.0 dB +0. 14. "A 10bit ChargeRedistribution A DC Consuming 1. pp." Procs. Tech. van der Plas. pp. no. . Xu. J.3M S/s CMO S pipelined analogtodigital converter. "A 10bit 12M S/s successive a pproximation ADC with 1. vol. B. I007 � 1015.9 uW at I M S/s.. R.160.46/0.IO.2 0 ' 0. P.. 157 . "A 1. May 2010 . Dec. vol.���� = � 0.3 KHz SNDR=53 dB@(. G. vol. 10bit. Fig. Yi.4. A pr. L iu.2 VI. TABLE I . 2007. E. 881 . E.� " c 20 /. Chang. 10 shows a frequency spectrum simulation @fin 403.37/0. 9. x. 40 60 80 E 100 [2] 100 Frequency (KHz) 200 300 400 500 [3] Fig. 44. Huang." IEEE J Solid State Circuits. L. = 1::1 .=403.66 LSB and +0.66 +0.. Y.53 Power Supply T echnology Resolution Sampling Rate Dynamic Range SN DR (@fin=484. M.4kHz) DNL (L SB) INL (LSB) I I V Po wer Dissipation Analog Digital Reference ladder Total Po wer FOM 4. " A IV 450nW Fully I ntegrated Programmable Biomedical Sensor I nterface Chip.The static performance is characterized through the differential nonlinearity (DNL) and integral nonlinearity (INL). 1067 . the proposed ADC reduces the digital consumption as well as the total capacitance.8 0. Huang. pp.371 flW 0.4." . 5.53 LSB.__ ___ 50 51 52 53 54 SNDR (dB) 55 56 [6] Fig. 0. Geraedts.3 dB Num=50 [ 4] [5] ____ ______ _ � __ o . 2009.3 dB. 45. May 1999. pp.':' o 100 200 300 400 500 DIGITAL OUTPUT CODE ACKNOWLE DGMENT Fig. = = Fig.12. G. Simulated DNL and INL of the proposed A DC o . :c '010 . CONCLU SION Fig.3 kHz andfs =1 M S/s. Histogram of SNDR of proposed novel A DC @.098!IW 10. Craninckx. C...13. Y.ll.4 1.=1 40 0 L���2 0�03 00.26 flW 28. no.4 r. this work can be achieve the FOM as 28.0 dB.� Mean=53.� = . A. M.1077. no...37/0. V. 13 illustrate the SNDR of the ADC versus the input frequency and the sampling rate variation. Schinkel. L in. Y. By the pipelined operation. 246247. 731 � 740. For the figure of merit � OM) [6] of the ADC which is defined as FOM Power/(2E OB*fs). Yao. Simulated SN DR versus sampling rate.Z . Tuijl . :.fin=403..6 L__�__�__�__�__. V. L in. Fig. "A 10bit 50M S/s SAR A DC With a Monotonic Capacitor Switching Procedure. 34.
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