Carbon Nanotube Imperfection-Immune Digital VLSI

Subhasish Mitra
Robust Systems Group Department of EE & Department of CS Stanford University
H. Chen, J. Deng, A. Hazeghi, A. Lin, N. Patil, M. Shulaker, L. Wei, H. Wei, Prof. H.-S. P. Wong, J. Zhang

Carbon Nanotube FET (CNFET)

D

Carbon Nanotube (CNT) Diameter (D) : 0.5 - 3 nm

S. Iijima

Ideal CNFET Inverter

P+ doped Semiconducting CNTs

Vdd
Lithographic pitch
4nm

Input
Gates

Output

Sub-lithographic pitch

Gnd

N+ doped Semiconducting CNTs

3

CNFET Technology Milestones

1998 First CNFET demonstration [Delft, IBM] 2004 Best single-CNT CNFET [Stanford]

2001 Single-CNT logic gates [IBM]

2006 Single-CNT ring osc. [IBM]

CNFETs: BIG Promise, BUT

Major barriers for a decade Mis-positioned nanotubes Metallic nanotubes Processing alone inadequate Imperfection-immune design essential

Mis-positioned CNTs
Vdd A C

Incorrect Logic
B D Out

Wanted: AC + BD Got: AC + BD + AD

B Gnd

D
Wanted: (A+C) (B+D) Got : B+D
6

Metallic CNTs
Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)

CNFET with s-CNT

Current Current

CNFET with m-CNT

Transistor
Vg

No gate control
Vg

Typical: 10 50% grown CNTs metallic

7

Results
Yesterday SSI single-CNT ring oscillator Today Imperfection-immune VLSI circuits

CNFET Technology Milestones

1998 First CNFET demonstration [Delft, IBM] 2004 Best single-CNT CNFET [Stanford] 2008 Mis-positionedCNT-immune VLSI logic gates [Stanford] 2009 Imperfectionimmune adders & latches [Stanford] 2009 Monolithic 3D CNT circuits [Stanford]

2001 Single-CNT logic gates [IBM]

2006 Single-CNT ring osc. [IBM]

2008 Flexible CNT circuits [UIUC]

2009 Defecttolerant logic gates [USC]

2010 Ultra-short channel CNFETs [IBM]

CNFET Technology Outlook

Problem CNT alignment & positioning Challenge Correct function Correct function Low leakage High current density Complementary CNFETs
10

Status

Metallic CNT

CNT density

CNT doping

Outline
Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

Patil, IEEE TCAD 2008, Symp. VLSI Tech. 2008

11

Mis-positioned-CNT-Immune NAND
1. Grow CNTs

12

Mis-positioned-CNT-Immune NAND
Vdd

1. Grow CNTs 2. Extended gate & contacts

A Out A B Gnd B

CRUCIAL

13

Mis-positioned-CNT-Immune NAND
Vdd

1. Grow CNTs 2. Extended gate & contacts 3. Etch gate & CNTs
A Out A B Gnd B

4. Chemically dope P & N regions

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Mis-positioned-CNT-Immune NAND
Vdd

1. Grow CNTs 2. Extended gate & contacts 3. Etch gate & CNTs
A Out A B Gnd B

4. Chemically dope P & N regions

Etched region ESSENTIAL

Graph algorithms All possible functions

15

Automated Algorithms
Given: Layout Determine Mis-positioned-CNT immune ?

16

Mis-positioned-CNT-Immune NAND
Contact Doped GA E GB Doped Contact A Contact Intended: A or B B Contact

1 Contact 1 A
Gate A Doped

0
Etched

B
Gate B

1 Doped 1 Contact
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Mis-positioned-CNT-Immune NAND
Contact Doped GA E GB Doped Contact A Contact Intended: A or B B C-D-A-D-C : A Contact

1 Contact 1 A
Gate A Doped

0
Etched

B
Gate B

1 Doped 1 Contact
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Mis-positioned-CNT-Immune NAND
Contact Doped GA E GB Doped Contact A Contact Intended: A or B B C-D-A-D-C : A C-D-B-D-C : B Contact

1 Contact 1 A
Gate A Doped

0
Etched

B
Gate B

1 Doped 1 Contact
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Mis-positioned-CNT-Immune NAND
Contact Doped GA E GB Doped Contact C-D-A-D-C : A C-D-B-D-C : B C-D-B-D-A-D-B-D-C : A & B Contact A Contact Intended: A or B B

1 Contact 1 A
Gate A Doped

0
Etched

B
Gate B

1 Doped 1 Contact
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Mis-positioned-CNT-Immune NAND
Contact Doped GA E GB Doped Contact C-D-A-D-C : A C-D-B-D-C : B C-D-B-D-A-D-B-D-C : A & B C-D-E-D-C : 0 Contact A Contact Intended: A or B B

1 Contact 1 A
Gate A Doped

0
Etched

B
Gate B

1 Doped 1 Contact
21

Mis-positioned-CNT-Immune NAND
Contact Doped GA E GB Doped Contact C-D-A-D-C : A C-D-B-D-C : B C-D-B-D-A-D-B-D-C : A & B C-D-E-D-C : 0 Contact A Contact Intended: A or B B

1 Contact 1 A
Gate A Doped

0
Etched

B
Gate B

Implemented: A or B or (A & B) or 0 == A or B

1 Doped 1 Contact

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Automated Algorithms
Given: Logic function Produce Mis-positioned-CNT immune layout

23

Mis-positioned-CNT-Immune Layout
Vdd / Gnd Contact CNTs Gates Intermediate Contact
B C A

Etched regions

Output Contact

Out = A + (B + C)(D + E)

Immune to LARGE number of mis-positioned CNTs Efficient

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Most Importantly
VLSI processing No die-specific customization VLSI design flow Immune library cells

25

CNT Growth on Silicon Substrates

Highly mis-positioned Not desirable for VLSI

10 m

4 m

26

First Wafer-Scale Aligned CNT Growth

Quartz wafer with catalyst

Aligned CNT growth SEM image (grown CNTs)

Quartz wafer 99.5% CNTs aligned

27

Wafer-Scale CNT Transfer

Silicon substrates for VLSI Low temperature (90oC 120oC) processing
Thermal Release Adhesive Tape Before transfer Source Substrate (Quartz) After transfer Target Substrate (SiO2/Si)

2 m

2 m
28

First VLSI Demonstration

Mis-positioned-CNT-immune logic gates NAND, NOR, AND-OR-INV, OR-AND-INV
Etched Region
10m

10m

NAND pullup Current ( A) Current ( A) 100 50 0 A off B off off on on off on on 1.5 0.75 0 A off B off

NOR pullup

off on

on off

on on
29

off = 2V, on = -2V

off = 5V, on = -5V

Outline
Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

Patil, IEDM 2009, Shulaker, Nanoletters 2011, Wei, IEDM 2009, Symp. VLSI Tech. 2010
30

Metallic CNTs
Semiconducting CNT (s-CNT) Metallic CNT (m-CNT)

CNFET with s-CNT

Current Current

CNFET with m-CNT

Transistor
Vg

No gate control
Vg

Typical: 10 50% grown CNTs metallic

31

m-CNT Processing Options

Grow 0% m-CNTs Open challenge Remove m-CNTs after growth 99.99% removal required

32

Existing m-CNT Removal

Sort CNTs Inadequate SDB Single Device electrical Breakdown Not scalable

33

SDB Technique
Current-induced m-CNT breakdown Single-device level

s-CNTs m-CNTs

Collins, Science 2001

34

SDB Technique
Current-induced m-CNT breakdown Single-device level

Gate off

s-CNTs m-CNTs

Collins, Science 2001

35

SDB Technique
Current-induced m-CNT breakdown Single-device level
High Voltage

Gate off Gnd

s-CNTs m-CNTs

Collins, Science 2001

36

SDB Technique
Current-induced m-CNT breakdown Single-device level
High Voltage

Gate off Gnd

s-CNTs m-CNTs m-CNT broken
Collins, Science 2001
37

SDB Technique
Current-induced m-CNT breakdown Single-device level
High Voltage
101 Current density (A / m) 102

Before SDB

After SDB

Gate off Gnd

s-CNTs m-CNTs m-CNT broken

100

10-1 100

102 Ion / Ioff

104

106

Collins, Science 2001

38

Major SDB Challenges

Incorrect logic m-CNT fragments Impractical for giga-scale ICs Internal node access

39

Incorrect Logic with SDB

Vdd Pull-up Network Output Contact High B off High

Wanted: (A + B) (C + D) Got: (C + D)

off

Intermediate Contact

Broken off Gnd

40

off

C Gnd Contact

Incorrect Logic !

VMR: m-CNT Immune Design

New approach: VLSI Metallic CNT Removal Sufficient All logic designs VLSI processing & design flows

41

VMR Example

Final intended design

VDD

GND

42

VMR Steps
1. Grow and transfer CNTs s-CNTs m-CNTs (no gate control)

Back-Gate Oxide Silicon Back-Gate

43

VMR Steps
1. Grow and transfer CNTs 2. Fabricate VMR electrodes

VMR Electrodes

Back-Gate Oxide Silicon Back-Gate Inter-digitated VMR electrodes Electrical breakdown friendly

44

VMR Steps
1. Grow and transfer CNTs 2. Fabricate VMR electrodes 3. Electrical breakdown (back-gate)

VMR Electrodes

Back-Gate Oxide Silicon Back-Gate

Inter-digitated VMR electrodes Electrical breakdown friendly

High voltage

Gnd

45

VMR Steps
1. Grow and transfer CNTs 2. Fabricate VMR electrodes 3. Electrical breakdown (back-gate) 4. Etch CNTs : predefined regions (mis-positioned-CNT-immune design) 5. Etch unneeded VMR electrodes

CNFET contacts not removed

46

VMR Steps
1. Grow and transfer CNTs 2. Fabricate VMR electrodes 3. Electrical breakdown (back-gate) 4. Etch CNTs : predefined regions (mis-positioned-CNT-immune design) 5. Etch unneeded VMR electrodes 6. Top-gates (mis-positioned-CNT-immune design), doping, wires

47

Theorem
VMR works for arbitrary logic design if Any two transistors in series Connected through contact Minimum pitch

Immune library cells: very small impact

48

First Experimental Demonstration

Imperfection-immune CNT VLSI circuits Arithmetic & storage elements

Half-adder Sum

D-latch

49

First Monolithic CNT 3D ICs

2-layer CNT XOR

Conventional via, NOT TSV

50

Outline
Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

Zhang, IEEE TCAD 2009, DAC 2009, DAC 2010

51

CNT Variations Challenging

Probabilistic modeling essential [Borkar 07]
CNFET Ion variations m-CNTs CNT density variations

Others

Channel length variations

CNT diameter variations

52

Probabilistic CNT Growth Model

Probability (m-CNT) = pm Probability (s-CNT) = ps = 1 - pm
s-CNT

m-CNT

2 = 0.3 3

1 2 3 = 0.44 3 3

2 1 3 = 0.22 3 3

1 = 0.04 3
53

m-CNT Removal Alone Inadequate

m-CNT

m-CNTs removed s-CNTs intact

No CNTs left !

prob. = (pm)3

Must be highly unlikely

= (33%)3 = 4%
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Probabilistic Design a MUST

Processing Design

% grown m-CNTs CNT density variations

Special layouts CNFET sizing

Processing & Design Co-Optimization Noise margin Leakage Delay variations

55

Special Layouts
high CNT variationagnostic

New technique Aligned-active layouts Engineered CNT correlations

1 Cost

design

low low

Upsize CNFETs

Yield

high

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Outline
Introduction Mis-positioned-CNT-immune logic Metallic-CNT-immune logic CNT variations Conclusion

57

Thanks to our Sponsors

Photo credits: H. Dai, ibm.com, Nanoletters, Nature, Science, Stanford, Wikipedia 58

CNFET Technology Outlook

Problem CNT alignment & positioning Challenge Correct function Correct function Low leakage High current density Complementary CNFETs
59

Status

Metallic CNT

CNT density

CNT doping

Conclusion
Imperfection-immune design essential New solutions: practical, elegantly simple

Next challenge: CNT variations CNT correlation unique layouts

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