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PROGRAMMING - I

5.1

INTRODUCTION: The key benefit from the application of computers is to be able to be

programmed to perform a specific task. The sequence of instructions to the CPU of a computer that causes it to solve a problem is called a program. The art of designing this sequence is called programming. A computer may be applied to solve a problem by designing the program and interfaces, the rest of the computer system remains the same. Since the main computer components are common, they can be mass produced with corresponding economies of scale. The changes are basically in the program which can be altered at a small cost. Designing the program is a major part of designing a microcomputer system. The primary task of a computer is to execute programs. The program is stored in the memory and it instructs the computer to perform a particular task. It consists of a sequence of instructions which the computer understands. The computer keeps fetching instructions from the memory and executing it in a sequential manner, unless an instruction causes it to change the execution sequence, or causes the computer to halt. The computer fetches and executes instructions. The complete set of instructions which of a computer can interpret and execute is known as the INSTRUCTION SET of that particular type of computer. The program is written using instructions from this instruction set. The next question is what are these instructions like? A computer can only understand binary numbers. Therefore, an instruction is simply a binary bit pattern, ie, a binary number. The computer interprets this binary bit pattern as an instruction to a particular task. For example, the bit pattern 0010 1111 instructs the 8085 microprocessor to complement the contents of register A. The entire program is a sequence of binary numbers. This is called machine language program or object program. But there are some basic difficulties in working with machine language. Such programs are not in a format which the humans, ie, the programmer can easily understand and debug. For a computer 01111010B may be easy to understand, but 1

not so for the programmer. They may find it tiresome and confusing. The situation is improved if the program is written in hexadecimal rather than binary numbers. For example 7AH is easier to understand and remember than 01111010B. Writing and debugging of programs becomes easier. It is for this reason programming is done with hexadecimal numbers. The program in hexadecimal is converted to binary through a program called the hexadecimal loader. The hexadecimal loader converts hexadecimal numbers and loads it into the computer. This is a common program and is usually a part of the monitor.

5.2

SOFTWARE MODEL OF 8085. The purpose of developing a software model is to aid the programmer in

understanding the operation of a microprocessor system from the software point of view. In order to program a microprocessor, we need not know all its hardware features. The functions of the various pins of the microprocessor and their electrical characteristics are not of importance to the programmer, nor is the knowledge of the working of its internal circuits needed. He is only interested in the software resources of the microprocessor system and how they are organized. A programmer must know the various internal registers and flags within the microprocessor, understand their purpose, capabilities and their limitations. In other words he must understand the programming model of the microprocessor. Furthermore, he must also know how the memory and the I/O are organized and how it is addressed by the microprocessor to obtain instructions and data.

5.2.1 Programming Model of 8085. The programming model is the diagram of the internal registers and the flags within the microprocessor, which are of importance to the programmer. The programming model of 8085 is shown in Figure 5.1. The 8085 contains several registers which can be used by the programmer. Some of these registers are general purpose and can be used by the programmer in any manner. Others are special purpose registers and are used for a specific purpose. The registers B, C, D, E, H, L are 8-bit general purpose registers. They can be used either individually as 8-bit registers or as 16-bit register pairs. The valid register 2

pairs are BC, DE, and HL. These register pairs are used to hold addresses or 16-bit numbers by some instructions. The register pair HL has a special significance. One is it can be used as a pointer to a memory location. Second, it acts as the accumulator for double byte addition. The register pair BC and DE can also be used as pointers by a very limited instructions. Amongst the special purpose registers, the Accumulator and the Flags together are known as the Processor Status Word. They give complete information of the result of a particular arithmetic or logical instruction. The Accumulator, also known as register A is the is an 8-bit special purpose register. It is the primary source and destination for arithmetic and logical instructions. Almost every arithmetic and boolean instructions take one of the operands from the accumulator and the result is placed in the accumulator. The other operand can be either in the memory or any of the other registers. Also all data transfers between CPU and I/O take place through the accumulator. The Flag register (F) contains five bits that are used as flags. Each of these record processor status information and may control the processor operation. On the execution of certain instructions the flags change. More over certain instructions such as conditional calls and jumps use these flags for their execution. The Sign Flag bit (S) indicates whether the results of an operation is positive or negative. If the most significant bit of the result of an operation is '1', then this flag is set, otherwise it is reset. The Zero Flag bit (Z) indicates whether the result of an operation is zero or non-zero. It is set if the result is zero, else it is reset. The Auxiliary Carry Flag bit (AC) holds the carry between the least significant and most significant halves (nibbles) of the result. If there is a carry from the 3rd bit to the fourth bit, AC is set, else it is reset. The Parity Flag bit (P) indicates the parity of the result. If the parity is even then P is set , otherwise it is reset. ( Parity is the number of '1' in the result expressed as even or odd.) The Carry Flag bit (C) indicates a carry out of the most significant bit of the result. If the instruction results in a carry (from addition) or a borrow (from subtraction or comparison) out of the most significant bit, this flag is set, otherwise it is reset.

The Program Counter (PC) keeps track of the address of the memory location containing the next instruction to be executed in the program memory. This is a 16-bit register.

Figure 5.1. The Programming Model Of 8085 Microprocessor.

Figure 5.2. Busses and Control Signals of 8085

The Stack Pointer (SP) keeps a track of the stack. The stack is a last-in, first out data structure the 8085 maintains in the memory. The stack pointer contains the address of (points to) the last memory location filled on the stack. The stack grows towards decreasing memory locations. With each addition to the stack the stack pointer is decreased by two and vice-versa. All stack operations are 16-bit.

5.2.2 Data and Address Busses of 8085 In order to understand how the memory and the I/O is organized, we shall review the bus organization of 8085. The 8085 has a 8-bit data bus. Therefore 8-bits of data can be transferred to and fro from the microprocessor in parallel. The 8085 has 16 address lines. The address lines are divided into two groups of 8 lines, ie, the Lower Address Bus and the Upper Address Bus. The Lower Address Bus and the Data Bus are multiplexed and they can be demultiplexed by using the ALE signal and a latch. The main control signals are RD 1, WR 2, IO/ M 3. The address lines address the memory when IO/ M 4 signal is '0'. It addresses the I/O when IO/ M 5 signal is '1'. These busses and control signals are shown in Figure 5.2.

5.2.3 Memory Addressing and Memory Map. When IO/ M 6 is low, the 16 address lines can address 216= 65,536 memory locations. This is also referred to as 64K, where 1K = 210= 1024. In other words the 16-bit address on the address bus selects one of the 64K memory locations which the 8085 microprocessor can address. Once the memory location is selected the data transfer between the selected memory location and microprocessor can take place. A memory location has therefore an address and a content. The memory address is the 16-bit address on the address bus which selects a memory location. The content is the data contained at that particular memory location. A memory location contains 8 bits of data. Therefore in short: i) ii) The memory can be considered to be an array of 64K memory locations, each with an unique address. Each memory location is 8-bit wide, ie, it can contain 8 bits of data.

A memory map can be drawn showing the memory organization of a computer system. Various functions assigned to these memory locations, eg, program storage, data storage, temporary storage, stacks etc can be depicted on it. Furthermore the type of memory interfaced and at what locations can also be shown on it. The latter will be dealt with in a separate module. A memory map is shown in Figure 5.3.

5.2.4 I/O Addressing and I/O Map. When IO/ M is high, the address on the address lines is for the I/O. Similar to memory addressing, the address on the address bus selects one unique I/O port location and then data transfers between the I/O port and the 8085 can take place. Each I/O port location is also 8 bits wide. But there is one difference. The address is duplicated on the Lower Address Bus A0-A7 and the Upper Address Bus A8-A15. Therefore there are 8 bits of unique address. Therefore the 8085 can address only 28= 256 I/O ports. An I/O map can be drawn showing the I/O organization of a computer system. The various functions assigned to the I/O can be depicted on it. An I/O map is shown in Figure 5.4

5.2.5 The Software Model of 8085. The software model of 8085 is shown in Figure 5.5. It shows the internal registers of 8085 as well as the memory and the I/O space. This model gives a clear indication of the various resources available to the programmer. In other words it becomes his play field. This is an invaluable conceptual aid in programming. It gives a clear picture of how instructions work and how they affect the registers, flags, memory and the I/O. The Interrupts are also shown in the figure. They can be disabled or enabled through software. The SID and SOD lines are also shown as they can be programmed through software.

Figure 5.3. The Memory Map

Figure 5.4. The Memory Map.

Figure 5.4. The I/O Map.

Figure 5.5. The Software Model of 8085

5.3

REVIEW OF THE INSTRUCTION SET. The instruction set of 8085 was introduced in module on the 8085 CPU. The

detailed instruction set is given the Appendix. In this section some of the aspects of the instruction set will be highlighted. It is recommended that the student goes thoroughly through the instruction set given in the Appendix. 5.3.1 Instruction Format. There are three different instruction formats ( Figure 5.6), namely, one byte, two byte and three byte instructions. The first byte of all instructions is the op-code (operation code). The op-code tells the 8085 CPU which operation is to be performed. The other bytes, if present, contain the operands to be used by the instruction. Multibyte instructions must be stored in successive memory locations. The address of the first byte is the address of the instruction. a) b) Single Byte Instructions: These instructions contain only the op-code.

Most of the instructions of 8085 are single byte instructions. Two Byte Instructions: In these instructions the first byte is the op-code and the second byte contains an 8-bit operand. This operand can be a 8-bit data or an I/O address. c) Three Byte Instructions: In these instructions the first byte is the op-code and the second and third bytes contain a 16-bit operand. This may be a 16-bit data or a memory address. The method of encoding this 16-bit operand in the instruction is a bit unusual. The second byte contains the least significant byte (LSB) and the third byte contains the most significant byte (MSB) of the two byte data or address. For example if the 16-bit data is 1234H it is coded as 34 12 in the 2nd and 3rd bytes respectively of the instruction. Always remember that a 16-bit data is coded as LSB first and then MSB. Op-codes and Mnemonics. The op-codes are basically binary numbers. For example, if register A is to be complemented the op-code is 0010 1111B or 2FH. A programmer will find it difficult to remember which op-code 2FH corresponds to. Therefore the op-codes are described in terms of MNEMONICS. Mnemonics are abbreviations of the instruction. In programmer. The mnemonics are usually written in upper case. 10 other words the op-codes are described in terms of mnemonics for the benefit of the

5.3.2 Addressing Modes of 8085. When 8085 executes an instruction it performs specified functions on data. These data are called its operands. These may be a part of the instruction, reside in one of the internal registers, stored in the memory or held in the I/O. The various methods the 8085 uses to access the operands are called its addressing modes. The 8085 has four addressing modes, namely direct addressing, register addressing, register indirect addressing and immediate addressing. Direct Addressing. In direct addressing the instruction contains the actual address of the operand in the memory. A 16-bit memory address follows the op-code of the instruction. Consider the instruction LDA 1234H. LDA is the mnemonic for the instruction Load Direct Accumulator and 1234H is the 16-bit address which contains the data to be loaded. Assume the data is 10H. The op-code for LDA is 3AH. Therefore the instruction which is 3 bytes long is 3A 34 12. Notice that the address is coded LSB first and then MSB, in the second and third bytes of the instruction. Register A 10 < Memory Location 1234 10

Register Addressing. In register addressing the instruction specifies the register or register pair in which the operand is located. They can be the registers B, C, D, E, H, L, or A, or the register pairs BC, DE, HL or SP. For example, consider MOV B,A instruction. This is a one byte instruction whose op-code is 47H. The mnemonic MOV stands for move. The instruction is read as move destination register B, source register A, or as move A to B. The instruction causes contents of register A to be copied to register B. Register Indirect Addressing. In the register indirect addressing, a register pair holds the address of the memory location containing the operand. Thus the memory is addressed indirectly by 11

the register pair. The register pair HL is a special register for register indirect addressing. It defines a register M in the memory at the location, whose address is contained in the register pair HL. Consider the instruction MOV A,M. It is a one byte instruction. It is a one byte instruction and the op-code for it is 7EH. Assume that at the time of execution of the instruction the register pair HL contains 1234H. This instruction moves content of M (located at memory address pointed by HL, namely 1234H) to register A. See Figure 5.7. Immediate Addressing. In this mode of addressing the data is encoded in the instruction. The data is placed immediately after the op-code. The data may be 8-bit or 16-bit, depending on the type of instruction. For example, consider the instruction MVI A,30H. The mnemonic MVI stands for move immediate. This is a two byte instruction whose opcode (the first byte) is 3EH. This is followed by the data to be moved to register A. The instruction is coded in machine language as 3E 30. Implicit Addressing. In certain instructions the operand is not specified, but is assumed to be in a register usually the accumulator. Consider the CMA instruction. CMA stands for complement the accumulator. Here the register A (the accumulator) is implied. This is a one byte instruction whose machine code is 2FH.

5.3.3 Classification of Instructions. In the previous sections we had encountered some of the instructions. Here we shall go through the various groups of instructions. It is useful to refer to the software model of 8085, while going through the instruction set. The 8085 microprocessor has 74 different instructions, which total to 246 different op-codes. These op-codes are different for different variations of the instructions. For example, the MOV reg1,reg2 has 63 variations and therefore 63 12

different op-codes.

Figure 5.6. Instruction Types. j

Figure 5.7. HL points to Reg. M in Memory.

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The instruction set of 8085 has been grouped under five different functional headings, as follows: 1. Data Transfer Group - These instructions move data between registers or between registers and memory. 2. Arithmetic Group - These instructions add, subtract, increment or decrement data in registers or memory. 3. Logical Group - These instruction perform logical operations of ANDing, ORing, XORing, comparing, rotating or complementing data in registers or between memory and a register. 4. Branch Group - These instructions modify the program flow by performing conditional or un-conditional jumps, calls or returns. 5. Stack, I/O, and Machine Control Group. These instructions perform stack operations, reading and writing to I/O ports and interrupt control and setting and clearing of flags. 5.3.4 Data Transfer Group. The instructions in this group are used to transfer data around the registers and the memory, as well as load them with immediate data specified in the instruction itself. In data transfer instructions, the flags are not affected, ie, the values of the flags remain the same before and after the data transfer instruction. In nearly all the data transfer instructions although the data is copied from one place to the other and not moved, as suggested by the mnemonics. The exception to this is the XCHG instruction, where exchange of data takes place. If one recalls the software model, these instructions transfer data between the registers B, C, D, E, H, L and A and the memory. Direct memory to memory transfer is not possible. These instructions can be subdivided into immediate, direct, indirect and register transfer instructions. The registers i) Immediate Data Transfer Instructions: These instructions load the registers or register pairs of 8085 or a memory location M addressed indirectly by the HL register with the immediate data supplied with the instruction itself. There are two forms of the 14

instruction. One form, the move immediate instruction is MVI r,8-bit data loads the 8-bit data into the register specified. The registers can be A, B, C, D, E, H, L or M. The other form is the load immediate register pair instruction is LXI rp,16-bit data LXI loads the specified register pair with the immediate 16-bit data supplied with the instruction. The register pairs can be BC, DE, HL or SP. A mnemonic containing X as a letter, usually refers to a register pair operation. ii) Direct Data Transfer Instructions: In these instructions the data is transferred to and from the memory. The address of the memory location is given in the instruction itself. There are two forms of these instructions one dealing with 8-bit data and the other with 16-bit data. In the first form, the data transfers takes place between the accumulator, ie, register A and the content of memory location specified. LDA STA memory address memory address ; (Load Direct Accumulator for memory) ; (Store Direct Accumulator to memory)

In the other form a 16-bit data, the data transfer takes place between the HL register pair and two consecutive address specified. LHLD memory address SHLD memory address ; (Load HL Direct), ; (Store HL Direct). memory locations, starting from the memory

The LHLD xxxx instruction loads the register L with the content of the memory address xxxx and register H with content of the memory location xxxx+1 as shown in Figure 5.8. In SHLD instruction the contents of the HL stored in the memory in a similay way. iii) Indirect Data Transfer: Although data can be transferred indirectly through the register M, there are other types of indirect data transfer instructions also. These are LDAX rp STAX rp ; (Load Accumulator Indirect), ; (Store Accumulator Indirect).

The rp can be the B (register pair BC) or D (register pair DE). These instructions load and store register A at a memory location whose address is contained in the specified register pair. The other method of defining a register M in memory does not have a particular 15

instruction. In this method the register M is like any other register of 8085.

Figure 5.8 The LHLD Instruction.

Figure 5.9 The XCHG Instruction.

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iv) Register Transfer Data Instructions: This is the largest group of data transfer instructions. These instructions transfer 8-bit data between the various registers. There 63 different MOV instructions. These have the form MOV reg1, reg2 (Move reg2 to reg1) where reg1 and reg2 are the registers A, B, C, D, E, H, L, A, M. XCHG is a 16-bit instruction. This exchanges contents of DE and HL register pairs. This is different from the other data transfer instructions as an exchange of data takes place instead of a simple move. There are no operands specified as DE and HL are implicitly addressed. See Figure 5.9.

5.3.5 Arithmetic Group. The arithmetic group includes instructions for 8-bit addition and subtraction, 16bit addition, instructions for incrementing and decrementing registers and register pairs. In all the arithmetic and logical instructions requiring two operands one of the operands is assumed to be in the accumulator (register A) and the result of the operation is also put in the accumulator. All arithmetic instructions affect the flags according to the rules indicated earlier (discussion on the software model), unless indicated otherwise. All subtraction operations are performed through the two's complement arithmetic and set the carry flag to indicate a borrow and clear it to indicate no borrow. i) 8-bit binary addition instructions: The register A is assumed to contain one operand. The second operand can be in any of the registers B, C, D, E, H, L, in the memory register M, or supplied as an immediate operand with the instruction. The result of the addition is put in the accumulator. The forms of instruction are ADD register ADD 8-bit data ; (A) <-- (A) + (register) ; (A) <-- (A) + 8-bit data)

The notation (A) <-- (A) + (register) implies that the content of register A is added to that of the specified register and the result is put in register A. As an example consider that A contains 40H and B contains EEH. The instruction ADD B will cause the addition and the result 2EH will be put in register A. 17

The flags will be set as under. S 0 Z 0 AC 0 P 1 CY 1

ii) 8-bit binary addition with carry instructions: These instructions are similar to the ADD instructions, except that the carry flag is also taken into account. If the carry flag is set prior to this instruction, 1 will be added to the result. This is helpful in multibyte addition, where the overflow from previous bytes has to be considered. The forms of instructions are: ADC register ADC 8-bit data ; (A) <-- (A) + (register) + (CY) ; (A) <-- (A) + 8-bit data + (CY)

where (CY) is the value (0 or 1) of the carry flag. iv) BCD addition: In BCD addition the operands are BCD numbers and binary addition is first done. Then the Decimal Adjust Accumulator instruction, DAA is executed. The correct BCD addition results will be available in the accumulator. v) Double byte addition instruction: The DAD instruction is a double byte addition instruction. The register pair HL acts as the double byte accumulator. One of the operands is in HL register pair and the other operand is in any of the register pairs, namely BC, DE, HL or SP. The result is put in HL. This instruction only affects the carry flag. The form of instruction is DAD register pair ; (HL) <-- (HL) + ( register pair)

vi) 8-bit binary subtraction: In the subtract instructions the accumulator contains one of the operands from which the other operand is subtracted. The result is put in the accumulator. In case a borrow is generated, the carry flag is set. The forms of instruction are SUB reg SUI 8-bit data ; (A) <-- (A) - (register) ; (A) <-- (A) - 8-bit data

Subtract instructions with borrow take care of the previous borrow generated. These are used for multi-byte subtractions. The value of the carry flag is subtracted from the result. The forms of the instructions are SBB SBI reg 8-bit data ; (A) <-- (A) - (register) - (CY) ; (A) <-- (A) - 8-bit data - (CY)

vii) Increment and decrement register instructions: These instructions increment 18

or decrement the specified register by one. These instructions affect all flags except the CY flag. These are very useful instructions when a register is being used as a counter, as we shall see later. The form of the instructions are INR register ; (register) <-- (register) + 1 ; (register) <-- (register) - 1 DCR register

The register can be a, B, C, D, E, H, L or M. viii) Increment and decrement register pair instructions: These instructions increment or decrement the specified register pairs. It effect none of the flags. The register pair which can be incremented or decremented are BC, DE, HL, SP. The form of instructions are INX register pair ; (reg. pair) <-- (reg. pair) + 1 ; (reg. pair) <-- (reg. pair) - 1 DCX register pair

5.3.6 Logical Group. The logical group contain instructions for Comparing, ANDing, XORing, ORing, Complementing and rotating the operands. The accumulator contains one of the operands and also contains the results of the operation.

i) The basic logic functions: The instructions for basic logic functions of AND, XOR and OR are given below. ANA register ANI 8-bit data ; (A) 7 (register) ; (A) 8 8-bit data

where 9 is the symbol for AND operation. In the ANDing instruction the CY flag is set and the AC flag is cleared. Other flags are set according to the result. XRA register XRI AC flags are 8-bit data ; (A) 10 (register) ; (A) 11 8-bit data

where 12 is the symbol for XOR operation. In the XORing instruction the CY and the cleared. Other flags are set according to the result. The XRA A instruction is frequently used to clear the flags as well as the accumulator. ORA register ORI 8-bit data ; (A) 13 (register) ; (A) 14 8-bit data

where 15 is the symbol for OR operation. In the ORing instruction the CY and the 19

AC flags are cleared. Other flags are set according to the result. ii) The compare instructions: These instructions are similar to the SUB instructions, except that the result in not put in the accumulator. Only the flags are set. The forms of the instructions are CMP register CPI 8-bit data ; Flags for (A) - (register) are set. ; Flags for (A) - 8-bit data are set.

If the Z flag is set then the two operands are equal. If the CY flag is set then the operand in the accumulator is smaller of the two. iii) The rotate instructions: There are a set of four instructions that allow the contents of the accumulator to be rotated left or right. Each rotate instruction affects the contents of the accumulator and the carry flag. These instructions are the Rotate Left Circular RLC, Rotate Right Circular RRC, Rotate A Left through Carry RAL, and Rotate A Right through Carry RAR. In all these instructions only the carry flag is affected. The details of these instructions are shown in Figure 5.10. iv) Misc. logical instructions. One of these instructions, the CMA, complements the accumulator. No flags are affected. The other two instructions, STC and CMC, set and complement the carry flag respectively. There is no instruction for resetting the carry flag. No other flag except the carry flag is affected. CMC ; it complements the CY flag. STC ; it sets the CY flag.

5.3.7 Branch Group. The 8085 has a variety of instructions which alter the normal sequence of program flow. These are known as the branching or program control instructions. There are two basic forms of these instruction, namely the jump and the call instructions. The jump instructions allow the program to jump to any location in the memory and continue the program execution. The call instructions transfers control temporarily to a sub-program. On encountering a return instruction in the sub-program the control returns to the main program. The jump, call and return instructions can be 20

unconditional or conditional. The conditional instructions branch only when a condition is met. The conditions are related to the state of a particular status flag. These instructions do not alter the flags.

Figure 5.10 The Rotate Instructions.


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i) The unconditional jump instructions: The jump instruction causes the next instruction to be executed from the address specified in the instruction. The form of the instruction is JMP memory address This instruction loads the program counter PC with the specified address, instead of next address in the program sequence. Therefore the instructions are now fetched sequentially from this new address. In other words the program jumps to the specified address. The other unconditional jump instruction is PCHL. This uses indirect register addressing. The HL register pair contains the address of the jump location. This instruction causes contents of HL register pair to be copied to PC. ii) The conditional jump instructions: In these instructions jump to the specified memory address occurs if the condition specified in the instruction is met, else the no operation occurs and the next instruction in sequence is executed. The format for the instruction is Jcondition memory address The various conditions based on the status of the flags is given below. The corresponding value of the flag as well as comments on the condition are given. For example JZ address implies jump if zero, ie, if the z flag is 1. Condition Z NZ C NC M P PE PO Condition flags Z=1 Z=0 CY = 1 CY = 0 S=1 S=0 P=1 P=0 if plus if parity even if parity odd Comment if zero if not zero if carry set if no carry if minus

iii) The call instructions: These instructions cause the program to branch to a subroutine whose memory address is specified in the instruction. But before the program jumps by loading the PC with the new address, this instruction causes the current value of PC to be saved on the stack. The forms of instructions are CALL Ccondition memory address memory address ; Unconditional call. ; Conditional call.

The conditions are the same as described for the conditional jump instructions. The 22

following steps are performed by this instruction. It is useful to recall that stack pointer SP points to the last filled memory location on the stack, and that the stack grows towards decreasing memory addresses. The stack pointer SP is decremented by 1 and MSB of PC is stored in the memory location pointed to by the SP. The SP is again decremented by 1 and the LSB of PC is stored in the memory location pointed to by SP. The PC is now loaded with the specified address. In the case of conditional call instruction, if the condition is not met, no action takes place and the next sequential instruction is executed. iv) The return instructions: This instruction are generally used together with the call instruction. If the 8085 is executing a subroutine because of a call instruction, it returns to the original program from this subroutine, when it encounters a return. This instruction does not require an address, as the address is already saved on the stack by the call instruction. The form of the instructions are RET Rcondition ; Unconditional return ; Conditional return

The conditions are the same as described for the conditional jump instructions. The following steps are performed by this instruction. The stack pointer SP is incremented by 1 and data in the memory location pointed to by the SP is copied into the MSB of PC. The SP is again incremented by 1 and the data in the memory location pointed to by SP is copied into the LSB of PC. The PC is therefore now loaded with the previously saved address on the stack by the call instruction. In the case of conditional return instruction, if the condition is not met, no action takes place and the next sequential instruction is executed. v) The restart instructions: These are special unconditional call instructions. In these instructions instead of an address, a number n between 0 and 7 is specified. The address is fixed and is equal to n * 8. The form of instruction is RST n ; where n lies between 0 and 7. Therefore RST 1 is the same as CALL 0008H. In all other aspects it is similar to a CALL instruction. The RST instruction is a single byte as compared to the three byte CALL instruction.

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5.3.8 Stack, I/O and Machine Control Group. This group is a miscellaneous group. These instructions deal with manipulation of the stack, the I/O, Interrupt control and serial I/O. Some of these instructions will be dealt in detail in the next module. i) The no operation instruction: This NOP instruction is a single byte instruction and does nothing. But being an instruction it takes some time to execute. It is useful in timing matching and providing delays. It can replace an instruction, if that instruction is not needed. A series of NOP instructions can be put in a program to make space for future additions to a program. ii) The halt instruction: The HLT instruction is used to stop program execution. The only way the microprocessor can restart is through a reset or an interrupt. Both these must come through external hardware. This is useful in waiting for external interrupts. iii) The stack manipulation instructions: These instructions are used manipulate the stack. The PUSH and the POP instructions save and restore the specified register pairs on the stack respectively. During programming, if the registers are to be saved,The format of the instructions are PUSH register pair POP register pair The register pairs are BC, DE, HL and the PSW. The PUSH B instruction works in the following manner. The SP is decremented to point to the next empty location on the stack and the higher order register B is copied to the stack. The SP is again decremented and the lower order register C is copied on to the stack. Figure 5.11 illustrates this instruction. The POP instruction works in the reverse way. The other stack related instructions are SPHL and XTHL. The SPHL is an instruction to load the stack pointer SP from the HL register pair. The content of HL is copied to SP. This is an indirect way of loading the SP in order to initialize the stack. The XTHL instruction exchanges the content of the HL register pair with the most recent data on the stack. In other words. The content of register L is exchanged with the content of memory location being pointed to by SP and the content of register H is exchanged with the content of the memory location following it.

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iv) The I/O instructions: There are only two instructions which are related to I/O

Figure 5.11. The PUSH Instruction.

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operations. In both these instructions data movement takes between the specified port and the accumulator. The form of these instructions is IN port address OUT port address The port address is an 8-bit number. In the IN instruction the data from the specified port is copied into the A register. In the OUT instruction the data present in the register A is sent to the specified output port. v) Interrupt control instructions: These are the EI, DI, RIM and SIM instructions. The DI instruction masks all the interrupts except the unmaskable TRAP interrupt. If the interrupts are masked they are not recognized. The EI instruction unmasks the interrupts. When an interrupt occurs, future interrupts are automatically disabled. The EI instruction is used to enable them. The DI instruction is very useful in programs which require that no interrupt should occur during a particular program segment. The interrupts are disabled by DI instruction in the beginning of the segment and then enabled by the EI instruction at the end of the section. Apart from the general masking of the interrupts individual interrupts can be masked or unmasked. This is done using SIM, the set interrupt mask instruction. The individual mask settings and whether there are any pending interrupts can be known from RIM, read interrupt mask instructions. The RIM and SIM instructions are also used for serial I/O on the SID and SOD pins of 8085. The RIM instruction is used to read the serial data on the SID line and the SIM instruction is used to send serial data on the SOD line. The SIM instruction: In order to use the SIM instruction register A has to be loaded with the data as indicated in Figure 5.12. The bits M5.5, M6.5, and M7.5 are set to 1 to disable them or 0 to enable them. Also the mask set enable is set to 1. This enables the mask to be set on executing SIM instruction. The R7.5 is used to reset the RST7.5 flip flop. If instead of masking the interrupts the serial data is to be sent the data 0 or 1 is put in SOD and sod enable SOE is made 1. This serial data is put on the SOD line on executing the SIM instruction. The RIM instruction: On execution of the RIM instruction the register A contains the data as given in Figure 5.13. The bit labelled M5.5, M6.5 and M7.5 indicate the individual masking of the interrupts RST5.5, RST6.5 and RST7.5, respectively. The interrupt enable flag IE indicates whether the interrupts are enabled or disabled. The bits I5.5, I6.5 and I7.5 indicate whether any of the RST5.5, RST6.5 and RST7.5 are 26

pending, ie, waiting to be processed. The SID bit gives the status of the SID serial line.

Figure 5.12. Register A prior to execution of SIM.

Figure 5.13. Register A after execution of RIM.

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5.3.9 Time and Space Requirements of Instructions. While writing a program the programmer has to know the space required by his program. This will depend on the number of instructions the program has, as well as the length of each instructions, ie, whether they are 1, 2 or 3 byte instructions. This is the Program memory. Moreover the memory requirements for storing the data has also to be considered. This is known as the Data Memory and is the amount of memory required by the data. The other consideration is the time that is required by the program. Each instruction takes a finite amount of time, even if it is a NOP. This because the instructions have to be fetched, decoded and executed. The execution time is referred to as states, where a state is the time required for one system clock. The total time a program required is the sum of all instruction execution times. A complete description of the Instruction Set is given in the Appendix. This also gives the number of bytes the instruction takes, as well as the time required for its execution.

5.4

SIMPLE PROGRAMMING EXAMPLES A few simple examples of programming are presented in this section. These

examples have been based on the various addressing modes covered in Section 5.3.2. The the method of writing assembly language programs has been introduced here informally.

5.4.1 Example of Direct Addressing. Transfer the contents of memory location 2345H to 2400H. This example requires the transfer of data from one memory location to another. Unfortunately there is no direct instruction to do this. Therefore data is first transferred to register A from memory location 2345H and then it is transferred from register A to memory location 2400H, as shown in Figure 5.14.

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On going through the data movement group of instructions, the following time instructions will do the needful. LDA STA 2345H ; 2400H ; Loads register A with contents of memory location 2345H Store register A at memory location 2400 H.

In the above program any thing after `;' is considered a comment. This is an aid to understanding the program, but is not a part of a program. This small program can also be written using symbolic addresses for these memory location. If SOURCE stands for memory location 2345 H and DESTN stands for memory location 2400, the above program can be written as LDA STA SOURCE ; DESTN ; SOURCE stands for memory location 2345 H. DESTN stands for memory location 2400 H.

SOURCE and DESTN are known as labels. These denote the symbolic address, i.e., stand for the address of a memory location. A program written using MNEMONICS, hexadecimal numbers and labels in an assembly language program. This cannot be understood by the computer. Therefore as an intermediate step this program can be written in machine code in the hexadecimal form. The op-codes corresponding to mnemonics, addresses and data are expressed as hexadecimal numbers. This is of the form: 3A 45 23 32 00 24 On further converting it to binary machine code as 0011 1010 0100 0101 0010 0011 0011 0010 0000 0000 0010 0100 This binary form is what the computer understands. But to a programmer this is practically impossible to work with. Therefore the machine codes are usually entered into the computer memory in Hexadecimal form. Programs can be developed more meaningfully in assembly language using mnemonics. But this has to be translated in actual machine code. This can be done in two ways: a) Through a computer program known as an Assembler. b) Manually using the instruction set. This is called hand assembly. 5.4.2 Example of Register Addressing 29

Registers D and E contain numbers which are to be added and the result is

Figure 5.14 Example of Direct Addressing.

Figure 5.15 Example of Indirect Register Addressing


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stored in register C. The assembly language program is given below: MOV E,A ADD D MOV C,A ; moves content of reg E to reg A ; reg D is added to Acc, result in Acc ; result is moved to C.

5.4.3 Example of Indirect Register addressing. Move the contents of memory location 2000 H to Register B. In the example a register M is defined in the memory location 2000 H by loading this address in the register pair HL, as shown in Figure 5.15. LXI H,2000 H ; load HL with address 2000H ; this defines register M in memory MOV B,M ; move contents of M to B.

5.4.4 Example of Immediate and Implicit addressing. To store the number A5H in register B and its complement in register A. The assembly program for this is given below. MVI CMA B,A5H ; store A5 in register B. ; copy B to A ; complement A and store it in A itself

MOV A,B

The first instruction is an example of immediate addressing. The 8-bit data (A5H) is specified within the instruction itself. The third instruction is an example of implicit addressing. Here CMA meaning `complement the accumulator' implies the register A. It is not specified separately as an operand.

5.5

DETAILED PROGRAMMING EXAMPLE. Problem: Three signed numbers P, Q and R are stored at memory locations

0800H, 0801H and 0802H. The expression (P + Q - R) is to be determined and the 31

result is to be put in register B. The result is also to be outputted to port address 02H, to which a 8 LEDs are connected. Any carry generated is neglected. In order to solve this example, we will first develop an algorithm in plain and simple language. An algorithm is a procedure or a formula used to solve a problem. We shall then write the program in assembly language using mnemonics and finally code it in machine language using hand assembly. Finally we will go through the program step by step and see what actions take place in the software model of 8085 during program execution. The algorithm can be described by stating the inputs, outputs and the method of solving the problem. The input, P, Q and R are available in memory locations 0800H, 0801H and 0802H. The required output is a single byte integer equal to (P + Q - R) to be stored in register B and also outputted to port address 02H. The following method is used to solve the problem. This problem can be in other possible ways also. The register pair HL is loaded with 0801H (the address of Q). This defines the register M at 0801H. The accumulator is then loaded with data (P) from 0800H. The register M is added to the accumulator. Again the register pair HL is loaded with 0802H (address of R). The register M is now subtracted from the accumulator. The result (P + Q - R) is now in register A. This is moved to register B. Register A is also outputted to the I/O port 02H. After outputting the system halts. The assembly language program for this can now easily be written using the instruction set. LXI LDA LXI H,0801H 0800H H,0802H ; HL is loaded with 0801H (address of Q). ; Acc is loaded with P from 0800H. ; M which contains Q is added to Acc. ; HL is loaded with 0802H (address of R). ; M which contains R is subtracted from Acc. ; data of A is copied to B. ; data in A is outputted to I/O port 02H. ; system is halted.

ADD M SUB M MOV B,A OUT 02H HLT

Once the program has been developed, the translation to machine language is 32

done. One of the decisions to be taken is about the location of the program in the memory. In this example the origin of the program is placed at 0803H, immediately following the data. The program consists of 8 instructions of varying lengths. The first instruction starts from 0803H and is three byte long. The op-code is 21H and it requires a 16 bit data, encoded as LSB first and then MSB. The machine code in hexadecimal is therefore 21 01 08. Therefore, 21H, 01H and 08H are placed at memory locations 0803H, 0804H and 0805H respectively. the Appendix. The next instruction therefore starts at 0806H. The op-codes are found from the instruction set given in The assembly level program, together with the address of the instruction and machine code is given below. The first three locations contain data. In order to indicate that they contain data, a pseudo-mnemonic DB is put against the address. Details of how to write an assembly level program will be taken up in the next lecture. Address 0800 0801 0802 0803 0806 0809 080A 080D 080E 080F 0811 M/c Code 09 FE 05 210108 3A0008 86 210208 96 47 D302 76 Label Mnemonic P: Q: R: START: DB DB DB LXI LDA ADD LXI SUB MOV OUT HLT Operands 09 0FEH 05 H,0801H 0800H M H,0802H M B,A 02H

Figure 5.16 shows the software model of 8085. Assume that data and program have been entered in the memory of the microprocessor system and is lying at address 0800H onwards. The program execution is to start from 0803H. The various registers and flags of 8085 could contain any data, and have been indicated by a '--'. In order to start the program execution, the program counter PC is loaded with 0803H the address of the first instruction. This step is done by the monitor of the system. This is shown in Figure 5.17. Figure 5.18 shows the software model after the execution of the first instruction. The PC now points to the second instruction at 0806H. The HL register pair is loaded 33

with the address specified in the first instruction, i.e. 0801H. No flags are affected. Figure 5.19 show the execution of the second instruction LDA 0800H. The contents of memory location specified in the LDA instruction, i.e., 0800H is copied to

Figure 5.16. Detailed Example -Step 1.

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Figure 5.17 Detailed Example - Step 2.

Figure 5.18. Detailed Example - Step 3.

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Figure 5.19. Detailed Example - Step 4.

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register A. affected.

The PC points to the next instruction to be executed.

No flags are

The next instruction to be executed is ADD M. The register M is defined in the memory and its address is given by the current content of the HL register pair, i.e., 0801H. The content of this memory location is added to the accumulator, and the result is put in the accumulator. Flags are set according to the rules given in Section 5.2.1. The addition operation is explained below: 09H FEH Addition = = 0000 1001 1111 1110 ____________ 1 0000 0111 Carry AC = 07H.

The C and AC flags are set and the other flags are reset. The software model after the execution of this instruction is shown in Figure 5.20. Figure 5.21 shows the execution of the LXI H,0802H. The HL register pair is loaded with the 16 bit data of the instruction. The PC points to the next instruction. Figure 5.22 shows the software model after the execution of the SUB M instruction. The register M is now located at 0802, which is the current content of HL register pair. The operation (A - M) is carried out and the result 02H is put in A. The status of flags are S = 0, Z = 0, AC = 1, P = 0 and C = 0. The PC points to the next instruction to be executed. Figure 5.23 depicts the results of the execution of MOV B,A instruction. The content of A is copied to B. The flags are unaffected. Figure 5.24 shows the execution of the OUT 02H instruction. The content of register A is copied to I/O port address 02 H. instruction. The flags are not affected. The PC now points to the HLT

5.6

ASSEMBLY LANGUAGE PROGRAMS AND ASSEMBLERS In the previous lectures of this module we have already encountered assembly 37

language programs and we are familiar with some of its features. Let us recapitulate some of the The level program sequence of features. assembly consists of a

Figure 5.20 Detailed Example - Step 6.

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Figure 5.21 Detailed Example - Step 6.

Figure 5.22. Detailed Example - Step 7.

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Figure 5.23. Detailed Example - Step 8.

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Figure 5.24. Detailed Example - Step 9.

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instructions using symbolic op-codes, i.e., mnemonics, and symbolic or numeric data and addresses, i.e., labels. This program cannot be executed directly and has to be translated into machine code by hand (hand assembly) or through a program called the assembler. It was also observed that some additional information is also required, such as the address of the origin of the program in the memory and the address of the data in the memory. This additional information is given to the assembler through assembler directives or pseudo-operations. The assembly language program thus is a sequence of assembler directives and instructions. These are written using mnemonics (symbolic op-codes) or The assembler pseudo-operations together with symbolic or numeric data and addresses. The assembler directives provide necessary information to the assembler. described. 5.6.1 The Assembly Language Statement Each instructions in an assembly language program has four fields, namely, the label, the mnemonic, the operand and the comment. These fields follow each other in the sequence specified. An example is shown below: Label START: Mnemonic LX1 Operand(s) H, 0345 H; Comment HL loaded with pointer assembler directives will be after the format for assembly language instruction is

Each of the fields is separated from the other by a special symbol known as a delimiter for instance the comment field starts with a semicolon. These fields are discussed below: The label field A label field is the first field in an assembly language instruction. It may contain a label, i.e., symbolic memory address that is used to refer to the address of the statement in the program. In above example the label start is the symbolic address of the LXI H,0345H instruction. Labels are optional. If it is present it is separated from the next field by a colon `:'. The labels are a string of alphanumeric characters, the first of which is an 42

alphabet.

The string usually contains five or six characters depending on the

assembler. The label should not contain space or other special characters. Some assemblers do permit some limited special characters in a label. The label should not be mnemonic, pseudo-instruction or name of a register. For instance SUB, ORG or PC should not be used as a label. The assembler will otherwise signal an error. The Mnemonic Field This field must always contain a valid 8085 mnemonic or an assembler pseudo operation. Any other entry in the field results in an error. The field is separated from the label, if present by a colon and from, the operand field by a space. The Operand Field The operand field contains the name of registers, data or labels. The operands are separated from the comment field by a semicolon `;'. If more than one operand is required, the operands are separated by comma `,'. The data may be expressed in binary, decimal or hexadecimal form. This is indicated by a B,D or H immediately following the data. If this is not indicated, the data is assumed to be decimal. Most assemblers expect a 0 to precede hexadecimal data if it starts with an alphabet. ASCII data may be given if it is surrounded by a apostrophises, e.g. `K'. Some assemblers permit limited arithmetic and logical operation on the operand data. For example, LABEL+1 would evaluate to the value of LABEL plus 1. These operations are usually of +, -, *, /, NOT, AND, OR, XOR and MOD. The manual of the assembler being used should be consulted for details. The Comment Field The comment field begins with a semicolon. Whenever the assembler

encounters a semicolon, it assumes the rest of the line is a comment. If the entire line is a comment, then it must start with a semicolon `;' or an asterisk *. In that case there are no other field on that line. Comments have no effect on the object code and are ignored by the assembler. But they are essential for understanding and documenting a program. It is a good programming practise use comments freely in a program. These comments should be brief and to the point and bring out what the program is doing. 43

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5.6.2 Assembler Directives The assembler directives also known as assembler pseudo operations. They may or may not lead to generation of machine code. For example, END does not lead to any machine code generation, but DB does. Other pseudo operations which we shall cover are DW, DS, ORG EQU, SET, TITLE, SPC. These pseudo operation are placed in the mnemonic field of a statement. End (END): This signals the end of the program. It is the last instruction in a program. Define Byte (DB): This is used to define an 8-bit data in the memory. X: Y: Z: P: DB DB DB 12H `D' `H1' ; ; ; ; 12H is put in memory location X ASCII code is put at memory location Y ASCII codes of H and I are put at two memory locations ; starting at Z. DB 1,2,19 1,2 and 19 are put in memory locations starting from P.

Define Word (DW): This is used to store a 16-bit number in the memory, e.g. K: DW 1234 ; Number 1234 is stored in the memory at K in the proper ; format, i.e. LSB first and then MSB. Define Storage (DS): This is used to reserve space in the program for data. DATA: DS 5 ; reserves 5 bytes of memory starting from memory ; location DATA Origin (ORG): This informs the assembler about the starting location of the program. When used in the middle of a program, the location of the start of segment of program which follow it is changed to the value indicated. ORG 1000 H START: LX1 H, 200H These directives are similar but not the same. The 45 ; informs assembler that the next statement ; starts from 1000 H.

Equate (EQU) and Set (SET):

EQU directive is used to equal a label to another label or value. A label can be equated only once during assembly. If the value of the label has to be changed later in the program SET is used. SET is used only for special cases in a program. SCORE: VALUE: EQU 20 SET 5 ; ; label SCORE has a value of 20 label VALUE has temporary value of 5.

Apart from these there are other assembler directives such as, IF and ENDIF for conditional assembly, TITLE and SPC for listing control, GLB and EXT for use with linker to link with other programs. Discussion on these is beyond the scope of the present discussion.

5.6.3 Assemblers As mentioned earlier an assembler converts the software written in assembly language into machine language in the hexadecimal form. The assembly language program is called a source program and the machine code is the object code. This code can be loaded into the microprocessor using loader. The object code is usually in a special object format, e.g. S-format or Intel Hex Format.

Apart from this object code, the assembler also generates a listing.

This

contains the source code and the errors encountered during assembly. If there are no errors it indicates the machine codes corresponding to each statement. It also gives a label or symbol listing at the end. This symbol listing gives the symbol value corrosponding to the symbol name. Most assemblers are two pass assemblers. It scans the source code twice. In the first pass it makes a table of labels found in the program. It also keeps track of address of the labels. In this pass it determines the address of all labels in the program. Some labels may have been referred in the operand field prior to its definition in the label field (forward referencing). In the second pass, the object code is determined using the generated label table. The single-pass or the one pass assembler scans the source code only once. These assemblers cannot handle 46

forward references automatically, and seme method has to be used to handle them. Macro assemblers are special types of assemblers. programmer to define new op-codes termed as macros. They permit the

They may be an often

repeated group of instructions which occur many times in a program. Whenever the macro name appears, it is replaced by this group of instructions during the assembly process. The other types of assemblers are the cross-assembler and the metaassembler. A cross assembler is an assembler that runs on a computer whose CPU is different than the one for which it assembles the program. For example, an assembler for generating code for 8085 may be run on a PC. A self assembler or a resident assembler on the other hand generates code for the same computer system on which it runs. A meta-assemblers an assembler which can handle many different instruction sets. It is left to the user to define the instruction set used.

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