Vector Floating Point Instruction Set Quick Reference Card

Key to Tables {cond} <S/D> <S/D/X> <VFPsysreg> See Table Condition Field S (single precision) or D (double precision). As above, or X (unspecified precision). FPSCR or FPSID. 2: VFPv2 and above. 3: VFPv3 and above. Fd, Fn, Fm {E} {Z} <VFPregs> <BinLoc> <type> Sd, Sn, Sm (single precision), or Dd, Dn, Dm (double precision). E : raise exception on any NaN. Without E : raise exception only on signaling NaNs. Round towards zero. Overrides FPSCR rounding mode. A comma separated list of consecutive VFP registers, enclosed in braces ( { and } ). Number of integer bits in fixed-point number, 0-16 or 0-31. SH, SL, UH, or UL, for Signed or Unsigned, Halfword (16-bit) or Longword (32-bit).

Operation Vector arithmetic Multiply and negate and accumulate negate and accumulate and subtract negate and subtract Add Subtract Divide Copy Absolute Negative Square root Scalar compare Scalar convert Two values Value with zero Single to double Double to single Unsigned integer to float Signed integer to float Fixed-point to float Float to unsigned integer Float to signed integer Float to fixed-point Insert constant Insert constant in register Single to ARM Two ARM to two singles Two singles to two ARM Two ARM to double Double to two ARM ARM to lower half of double Lower half of double to ARM ARM to upper half of double Upper half of double to ARM ARM to VFP system register VFP system register to ARM FPSCR flags to CPSR Transfer registers ARM to single

Assembler FMUL<S/D>{cond} Fd, Fn, Fm FNMUL<S/D>{cond} Fd, Fn, Fm FMAC<S/D>{cond} Fd, Fn, Fm FNMAC<S/D>{cond} Fd, Fn, Fm FMSC<S/D>{cond} Fd, Fn, Fm FNMSC<S/D>{cond} Fd, Fn, Fm FADD<S/D>{cond} Fd, Fn, Fm FSUB<S/D>{cond} Fd, Fn, Fm FDIV<S/D>{cond} Fd, Fn, Fm FCPY<S/D>{cond} Fd, Fm FABS<S/D>{cond} Fd, Fm FNEG<S/D>{cond} Fd, Fm FSQRT<S/D>{cond} Fd, Fm FCMP{E}<S/D>{cond} Fd, Fm FCMP{E}Z<S/D>{cond} Fd FCVTDS{cond} Dd, Sm FCVTSD{cond} Sd, Dm FUITO<S/D>{cond} Fd, Sm FSITO<S/D>{cond} Fd, Sm FTOUI{Z}<S/D>{cond} Sd, Fm FTOSI{Z}<S/D>{cond} Sd, Fm 3 FCONST{cond} Fd, #<imm8> MOV{cond} Sn, Rd MOV{cond} Rd, Sn 2 MOV{cond} {Sn,Sm}, Rd, Rn 2 MOV{cond} Rd, Rn, {Sn,Sm} 2 MOV{cond} Dn, Rd, Rn 2 MOV{cond} Rd, Rn, Dn MOV{cond} Dn[0], Rd MOV{cond} Rd, Dn[0] MOV{cond} Dn[1], Rd MOV{cond} Rd, Dn[1] MSR{cond} <VFPsysreg>, Rd MRS{cond} Rd, <VFPsysreg> MRS{cond} R15, FPSCR

Exceptions IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, UF, IX IO, OF, IX IO, OF, IX

Action Fd := Fn * Fm Fd := (Fn * Fm) Fd := Fd + (Fn * Fm) Fd := Fd (Fn * Fm) Fd := Fd + (Fn * Fm) Fd := Fd (Fn * Fm) Fd := Fn + Fm Fd := Fn Fm Fd := Fm Fd := abs(Fm) Fd := Fm

Notes

IO, DZ, OF, UF, IX Fd := Fn / Fm

IO, IX IO IO IO IO, OF, UF, IX IX IX IO, IX IO, IX

Fd := sqrt(Fm) Set FPSCR flags on Fd Fm Set FPSCR flags on Fd 0 Dd := convertStoD(Sm) Sd := convertDtoS(Dm) Fd := convertUItoF(Sm) Fd := convertSItoF(Sm) Fd := convert<type>toF(Fd) Sd := convertFtoUI(Fm) Sd := convertFtoSI(Fm) Fd := convertFto<type>(Fd) Fd := convertIMtoF(imm8) Sn := Rd Rd := Sn Sn := Rd, Sm := Rn Rd := Sn, Rn := Sm Dn[31:0] := Rd, Dn[63:32] := Rn Rd := Dn[31:0], Rn := Dn[63:32] Dn[31:0] := Rd Rd := Dn[31:0] Dn[63:32] := Rd Rd := Dn[63:32] VFPsysreg := Rd Rd := VFPsysreg CPSR flags := FPSCR flags Stalls ARM until all VFP ops complete. Stalls ARM until all VFP ops complete. Sm must be S(n+1) Sm must be S(n+1) Destination is bottom 16 or 32 bits of Fd. Source is in bottom 16 or 32 bits of Fd. Use FMSTAT to transfer flags. Use FMSTAT to transfer flags.

3 F<type>TO<S/D>{<cond>} Fd, #<BinLoc> IO, IX

3 FTO<type><S/D>{<cond>} Fd, #<BinLoc> IO, IX

Vector Floating Point Instruction Set Quick Reference Card

Operation Save VFP registers Single Multiple, unindexed / increment after decrement before Push onto stack Load VFP registers Single Multiple, unindexed / increment after decrement before Pop from stack Assembler STR{cond} Fd, [Rn{, #<immed>}] STM{cond} Rn{!}, <VFPregs> STMDB{cond} Rn!, <VFPregs> PUSH{cond} <VFPregs> LDR{cond} Fd, [Rn{, #<immed>}] LDM{cond} Rn{!}, <VFPregs> LDMDB{cond} Rn!, <VFPregs> POP{cond} <VFPregs> LDMIA, LDMFD LDMEA (empty ascending) LDM SP! STMIA, STMEA STMFD (full descending) STMFD SP! Fd := [address]. Immediate range 0-1020, multiple of 4. Loads list of VFP registers, starting at address in Rn. Synonyms Action [address] := Fd. Immediate range 0-1020, multiple of 4. Saves list of VFP registers, starting at address in Rn.

FPSCR format 31 N 30 Z 29 C 28 V 24 FZ

Rounding 23 22 RMODE

(Stride 1)*3 21 20 STRIDE

Vector length 1 18 17 LEN 16 12 IXE

Exception trap enable bits 11 UFE 10 OFE 9 DZE 8 IOE 4 IXC

Cumulative exception bits 3 UFC 2 OFC 1 DZC 0 IOC

FZ: 1 = flush to zero mode.

Rounding: 0 = round to nearest, 1 = towards +, 2 = towards , 3 = towards zero.

(Vector length * Stride) must not exceed 4 for double precision operands.

Register banks, and sector, scalar and mixed operations If Fd is S0-S7, D0-D3, or D16-D19, operation is Scalar (regardless of vector length). If Fd is S8-S31, D4-D15, or D20-D31, and Fm is S8-S31, D4-D15, or D20-D31, operation is Vector. If Fd is S8-S31, D4-D15, or D20-D31, and Fm is S0-S7, D0-D3, or D16-D31, operation is Mixed (Fm scalar, others vector). S0-S7 (or D0-D3), S8-S15 (D4-D7), S16-S23 (D8-D11), S24-S31 (D12-D15), D16-D19, D20-D23, D24-D27, D28-D31, each form a circulating bank of registers.

Exceptions IO OF UF IX DZ Invalid operation Overflow Underflow Inexact result Division by zero

Condition Field Mnemonic EQ NE CS / HS CC / LO MI PL VS VC Description (VFP) Equal Not equal, or unordered Greater than or equal, or unordered Less than Less than Greater than or equal, or unordered Unordered (at least one NaN operand) Not unordered Description (ARM or Thumb) Equal Not equal Carry Set / Unsigned higher or same Carry Clear / Unsigned lower Negative Positive or zero Overflow No overflow Mnemonic HI LS GE LT GT LE AL Description (VFP) Greater than, or unordered Less than or equal Greater than or equal Less than, or unordered Greater than Less than or equal, or unordered Always (normally omitted) Description (ARM or Thumb) Unsigned higher Unsigned lower or same Signed greater than or equal Signed less than Signed greater than Signed less than or equal Always (normally omitted)

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Document Number
ARM QRC 0007A Issue A B C Change Log Date November 2004 May 2005 March 2006 Change First Release Release for RVCT 2.2 SP1 Release for RVCT 3.0

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