Intro To SystemVerilog

SystemVerilog for Verification

Day One

Welcome to the “Intro to SystemVerilog for Verification” class Requirements
Some HDL programming experience Some Unix experience Familiarity with some Unix editor Unix account in Folsom, Chandler, Dupont, or Penang.

Assumes use of Modelsim.
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Advanced classes go into more details.Scope Of Course Introduction to SystemVerilog for verification Hands-on lab assignments Students will not be SystemVerilog experts at the end of this class. Class is an introduction only. Next Classes: Functional Coverage/Temporal language/Checkers How to write a SV Test How to write an SV BFM Length: 2 days Intel Confidential 4 .

command line keyboard input Screen output Placeholders for data user should input Intel Confidential Courier Regular Italic 5 .Typographic Conventions Regular Text Courier Bold Course Content Code examples.

Intel Confidential 6 . and temporal expressions to Verilog. constraints.What is SystemVerilog SystemVerilog is an IEEE extension to the Verilog language. SystemVerilog adds testbench features such as classes.

Getting More Information SystemVerilog LRM %20Lib/Forms/ Comprehensive information on SV: AVC Wiki Intel Confidential 7 .aspx Additional Information www.1a.

and create a work library: % mkdir svtraining. cd svtraining % vlib work % vmap work work Intel Confidential 8 . type the following at the unix prompt: % source <local site specific setup script> Next. create a training directory.Using SystemVerilog To setup your environment to use SystemVerilog.

end: hello endmodule: helloWorld Intel Confidential 9 . initial begin: hello $display("Hello World").Hello World module helloWorld().

To run your program.q -f" helloWorld Intel Confidential 10 .sv Note: If you do not name your file ending in . use the following command: % vsim -c -do "run -all. you must use the –sv option to vlog. type the following: % vlog SystemVerilog To compile your program.

Commenting Your Code Like C++. SystemVerilog supports two types of comments /* Block comments that can span * multiple lines */ // And single line comments $display(“hello”). // This is a comment Intel Confidential 11 .

Intel Confidential 12 .Lab 1: Hello World Create a module that prints “Hello World” using the $display command.

Basic Data Types .

x. 0). 32 bit signed 4-state. 64 bit signed 2-state.Integer Data Type shortint int longint byte bit logic reg integer time 2-state (1. 16 bit signed 2-state.0.z) user-def 4-state user-defined size 4-state. 64 bit unsigned Intel Confidential 14 . 8 bit signed 2-state. 32 bit signed 2-state. user-defined vector size 4-state (1.

// Creates 2 bit logic // vector Intel Confidential 15 . reg and logic defaults to unsigned To create vectors. use the following syntax: logic [1:0] L. int. shortint.Signed/Unsigned byte. bit. integer and longint defaults to signed Use unsigned to represent unsigned integer value Example: int unsigned ui.

… Strn} Str1[index] Equality Inequality Comparison Concatenation indexing – return 0 if out of range Intel Confidential 16 . >.Strings string – dynamic allocated array of bytes SV provides methods for working with strings Str1 == Str2 Str1 != Str2 <. Str2. <=. >= {Str1.

String Methods len putc getc toupper tolower compare icompare substr atoi. atoct. atohex. atobin atoreal itoa hextoa octtoa bintoa realtoa Intel Confidential 17 .

[x|X] 18 Intel Confidential . 32’hDEAD_BEEF. 1.4 Base Exponent ( E/e) Logic Value 0.Literal Values Integer Literal – Same as verilog value – unsized decimal value size’base value – sized integer in a specific radix Ex: 4’b0101. [z|Z]. 2’b1Z Real Literal value.value Ex: 2. 4’hC.

Lab 2: Data Types Write a top level module that displays the following output.toupper()). Hint: Output: # The integer i is 0x00000014 # The unsigned integer ui is 0xdeadbeef # The logic L is 1Z # string str1 is "Hello World" # string str2 is "Cruel World“ Intel Confidential 19 . $display(“%d %h”. $sformat(str. string str. h. logic 3. “%b”. string int i. int both signed and unsigned 2.str. Use of the following data types: 1. h). i. l) $display(“Logic value in upper case %s”.

Equivalent to: a = a + 3.Operators Logic Operators & + | ~ % ^ / ~& * ~| ~^ << >> Arithmetic Operators ** <<< >>> Assignment Operators = += -= *= /= %= &= |= ^= <<= >>= <<<= >>>= Example: a += 3. Intel Confidential 20 .

a now contains 2. b = 1'bZ. Intel Confidential 21 . Comparison Operators == != === !== =?= !?= > < <= >= Example: a = 1'bZ.Operators Auto-increment (++) Auto-decrement(--) Example: a = 1. if (a != b) $display(“Z != Z”). a++. if (a === b) $display(“Z === Z”).

v = {32’b1. “World”}. 32’b10}. c} = 3’b111. b. Example: s = {“Hello”. If LHS is smaller then assignment gets truncated. “ “.Concatenation The { } operator is used for concatenation. Intel Confidential 22 . // v = 64b vector Can also be used on left hand side: {a. Sizes of assignment have to match.

Lab 3: Operators Write a SystemVerilog module to calculate the following. Intel Confidential 23 . and print the result as an integer to the screen: (1101001 XOR 11111001) ÷ 5 Ignore remainder.

Flow Control Constructs How to go with the flow .

while.SystemVerilog additions Verilog includes: if-(else-(if)). for. repeat. forever. foreach Intel Confidential 25 . case.while. ?: (ternary) SystemVerilog: Enhances for Adds do..

if Verilog ‘if’ expressions Then branch taken for any nonzero known value of expr (no ‘x’ or ‘z’). equivalent to expr != ‘0’ Chain ‘if’ statements: if (expr) begin … end else if (expr) begin … end else begin … end Intel Confidential 26 .

with 3 operands. but conditional expr ? then_val : else_val Some call this the “ternary” operator. Ex: var_m = (x == 1) ? a : b.?: Operator. Intel Confidential 27 . in the same vein as “unary” and “binary”.

no 4-value exact matching. bit length of all expressions padded to same length case (expr) item: begin statement end item2. item3. runtime evaluation. item4: begin statement end default: statement endcase Intel Confidential 28 .

8’b01z10zx1: $display(“y”). 8’b11z01011: $display(“z”).casez. endcase Intel Confidential 29 . casex Handle wild cards with either casez or casex casez: ‘z’ bit in either item or expression will be treated as a match for that bit casex: ‘z’ or ‘x’ bits will both match casex (8’bx100z011 ^ reg_a) 8’b1x1001?1: $display(“x”).

Continuous execution, without end, of body statement(s) Used with timing controls Usually last statement in some block initial : clock_drive begin clk = 1’b0; forever #10 clk = ~clk; end : clock_drive
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Repeat a block ‘x’ times, no conditional test
repeat (expr) statement

What happens with expr = ‘x’ or ‘z’? Example
x = 0; repeat (16) begin $display(“%d”, x++); end
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Executes statement as long as expr evaluates to true

while (expr) statement

while (reg_i) begin something_happens(); reg_i = reg_i – 1; end

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step_assignment) statement Equivalent to begin initial_assignment. end end Intel Confidential 33 . step_assignment. condition.for ‘C’ inspired for loop for (initial_assignment. while (condition) begin statement.

arrb[i]--. i++) begin arr[i] += 200. i < arr.operators (Mentioned in operator section) for (int i.size().Enhanced for SystemVerilog adds: Loop variable declaration Multiple statements in init and step blocks (comma separated) ++ and -. end Intel Confidential 34 . j+=2.

end 2) do begin $display(“%d”. What’s the difference? x = 0. do statement while (expr). x--. end while (x). x). Intel Confidential 35 . x). 1) while (x) begin $display(“%d”.

Fn = Fn-1 + Fn-2 Hint: F1 = F2 = 1 Intel Confidential 36 .Lab 4: Flow control Write a SystemVerilog module to display the first 20 Fibonacci numbers.

User Defined Types and Enumerated Types .

yard = 36. 8-38 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . inch foot = 12.User Defined Types SystemVerilog supports a new keyword: typedef Syntax: typedef <base_data_type> <type_identifier> // inch becomes a new type // these are 2 new variables of type ‘inch’ typedef int inch .

// bool is NOT a SystemVerilog type bool myvar.Enumeration Syntax: enum [enum_base_type] { enum_name_declaration {. YES} bool. c} vars. // b=6.enum_name_declaration} } enum_base_type: default is int Enumeration is a useful way of defining abstract variables. green. // All medal members are 4-bits Define a new type typedef enum {NO. traf_lite2. c=7 Default assigned values start at zero 0 1 2 enum {red. gold} medal. b. yellow} traf_lite1. Values can be cast to integer types and auto-incremented enum { a=5. silver. green. // but it just became one “myvar” will now be checked for valid values in all assignments. NOTE: Define an enumeration with “ enum ” enum {red. arguments and relational operators 8-39 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . A sized constant can be used to set size of the type enum bit [3:0] { bronze=4’h3. yellow} lite.

next(). yellow. green. blue. always @(posedge clk) col_ps <= col_ns. To use enumerated types in numerical expressions the language provides the following functions: prev(). last(). white. Colors col_ps. num() and name(). Intel Confidential 40 . first(). black} Example typedef enum {red.Enumeration example Modelsim now allows viewing of enum types in waveforms similar to VHDL enum types. Colors col_ns. always @(col_ps) col_ns = col_ps.

Casting .

Casting A data type can be changed by using a cast (’) operation. Intel Confidential 42 . Syntax: <type>’(<value/expression>) Examples: int’(2.0)// real to int casting 7’(x-2)//number of bits to change size. signed(m)//changes m to signed inteltype’(2+3)//casting to a user defined type [inteltype].0 * 3.

Arrays .

Intel Confidential 44 . Ex: logic [3:0] m. // each element is only 1-bit deep Ex: logic [3:0] m [5:0] Arrays can have packed and unpacked dimensions.Packed/Unpacked Arrays In packed arrays [range is on the left side of the identifier] all elements are glued together and can be overwritten by zero/sign extension of a single literal. m = 4’b1100. In unpacked arrays [range is on the right side of the identifier] each individual element is considered by itself without any relation to other elements. Ex: logic m [5:0].

'{9. // All elements “5” For more control.11.2.'{3{4}}}.Array Literals and Default To help in assigning literal values to arrays SV introduces the default keyword: int k [1:1000] = '{default: 5}.2}.10.12}}.1.7. int k [1:3][1:4] = '{'{1.3.8}. // 3 groups of 4 int m [1:2][1:3] = '{'{0.6. // 2 groups of 3 8-45 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation .4}.'{5. consider the dimensions of the array and use { } to match those dimensions exactly.

// Dynamic array of 4-bit vectors // Dynamic array of integers // Declare a dynamic array // Create a 256-element array // Create a 100-element array // Create a 200-element array // preserving previous values in lower 100 addresses Copyright © 2005 Mentor Graphics Corporation 8-46 • SV for Verification Using Questa: Functional Coverage . integer mem[ ]. addr = new[200](addr). int data[ ].Dynamic Arrays Syntax: data_type array_name[] . not synthesizable Dynamic declaration of one index of an unpacked array Declares a dynamic array array_name of type data_type data_type array_name[] = new[ array_size ] [(array)] . Allocates a new array array_name of type data_type and size array_size Optionally assigns values of array to array_name If no value is assigned then element has default value of data_type Examples: bit [3:0] nibble[ ]. data = new[256]. 1st new array in SV. int addr = new[100].

int j = addr. // j = 256 function void delete() Empties array contents and zero-sizes it int addr[ ] = new[256].size(). Cannot delete selected elements 8-47 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation .delete(). addr.Dynamic Arrays – Methods function int size() Returns the current size of the array int addr[ ] = new[256].

size()).size()). $display("Size of array = %d". bit data1 []. data1. initial begin // create a 128 element array data1 = new [128]. data2 = new[256](data1). data1.size()). $display("Size of array = %d". end endmodule Intel Confidential 48 .delete(). data1. data2.Dynamic Array Example module dyn_arry (). $display("Size of array = %d".

// clear the q1 list Copyright © 2005 Mentor Graphics Corporation 8-49 • SV for Verification Using Questa: Functional Coverage . q1 = ‘{ q1. A list is basically a variable size array of any SV data type. item = q1[0]. // $ represents the ‘upper’ array boundary // uses concatenate syntax to write n to the left end of q1 // uses concatenate syntax to write n to the right end of q1 // read leftmost ( first ) item from list // read rightmost ( last ) item from list // determine number of items on q1 // delete leftmost ( first ) item of q1 // delete rightmost ( last ) item of q1 // step through a list using integers (NO POINTERS) for (int i=0. item.size. not synthesizable SV has a built-in list mechanism which is ideal for queues. q1 }. n = q1.size. q1 = q1[1:$]. n }. q1 = ‘{ n. int q1[$]. stacks. q1 = q1[0:$-1]. int n. i < q1. etc. item = q1[$]. i++) begin … end q1 = { }.Queues and Lists 3rd new array in SV.

Prototype: function void push_front (queue_type item). If the queue is empty.insert (i. e. Q = Q[0.delete (i) => Q = ‘{Q[0:i-1]. Prototype: function void push_back (queue_type item).$-1] push_front() Inserts the given element at the front of the queue. Prototype: function queue_type pop_front(). e = Q. it returns 0. Inserts the given item at the specified index position.pop_back () => e = Q[$].Queue Methods size() insert() Returns the number of items in the queue. e} 8-50 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . Q[i. Prototype: function void insert (int index.$]} pop_front() Removes and returns the first element of the queue. e = Q.pop_front () => e = Q[0]. queue_type item). Deletes the item at the specified index position. Q. Q. Prototype: function void delete (int index).$] pop_back() Removes and returns the last element of the queue. Prototype: function queue_type pop_back().$]} Prototype: function int size().push_back (e) => Q = ‘{Q. e) => delete() Q = ‘{Q[0:i-1]. Q[i+1. Q.push_front (e) => Q = ‘{e. Q = Q[1. Q. Q} push_back() Inserts the given element at the end of the queue.

i < q. q[i]).push_back(1). q. Delete the element of queue at index 1 q.push_front (0). i. // declare the q initial begin: store_disp Push elements into the queue q.Queue Example module queues (). i++) $display("q[%0d] = %0d". int q [$].size()). end: store_disp // // // // // endmodule: queues Intel Confidential 51 .push_back(0).delete(1). Display its contents $display("Size of queue = %0d". Display all the contents in the queue for (int i = 0. Push to front of the queue q.size(). q.

Lab 6: Queues Write a SystemVerilog program with specification as defined in lab6.lab6 # run –all # Size of queue = 3 # q[0] = 0 # q[1] = 1 # q[2] = 3 # q -f Intel Confidential 52 .sv The output will look as follows: # Loading work.

Syntax: data_type array_name [index_type].Associative Arrays Associative arrays are used when the size of the array is not known or the data is sparse. Intel Confidential 53 . Associative array do not have their storage allocated until it is used. Data type used as an index serves as lookup key and imposes an order. It implements a lookup table of the elements of its declared type. In other words value_type array_name [key_type].

Intel Confidential 54 . a[5] = 2’b11. Integer Index Types Ex: bit [1:0] a [int]. a[“joe”] = 21.Index Types String Index Types Ex: int a [string].

When specified used to delete given index else whole array. prev (<index>) Intel Confidential 55 . Returns 1 if element exists at index else 0 assigns to the given index variable the value of the first/last (smallest/largest) index in the associative array. finds the entry whose index is greater/smaller than the given index. and 1 otherwise.Associative Array Methods Function num() delete(<index>) Use Returns number of entries Index for delete optional. last (<index>) next (<index>). It returns 0 if the array is empty. exists (<index>) first (<index>).

next(s)). end: test endmodule: asoc_arry Intel Confidential 56 .first(s)) do begin $display("Name = %s -. end while (db. db. // store values at indexes of associative array db ["jill"] = 19.Example module asoc_arry ().num()). s.exists("jill")) // check if index exists and change value begin db["jill"] = 25. db[s]). if (db. end // print the contents of associative array if (db. db ["joe"] = 21. int db [string]. // Define an associative array initial begin: test string s.Age = %0d".Associative array methods . // Display the size of the associative array $display("Size of hash = %0d".

Print the contents of the associative array.Lab 7: Associative Arrays 1.Age 2.Name of person VALUE . 5. Make the following entries into assoc NAME AGE ---------------John 25 James 30 Jane 24 3. Display the size of the hash using $display statement Check if name Jane exists in the associative array and if it does change her age to 40. Intel Confidential 57 . Define an associate array named 'assoc' assoc has the following attributes: INDEX . 4.

Procedural Blocks .

Triggering sensitivity @(<signal>) waits for an edge on <signal> before executing the next statement Edge-sensitive signal detection @(posedge clk) – waits for a rising edge clock @(negedge rstb) – waits for a falling edge on rs wait(<signal>) waits for a condition to become true before executing the next statement. execution continues without stopping Intel Confidential 59 . Level-sensitive signal detection If the signal is already true.

end endmodule Intel Confidential 60 . #25 b = 1’b0. Multiple behavioral statements must be grouped. each block starts to execute concurrently at time 0. typically using begin and end. reg a. If there are multiple initial blocks. initial begin #5 a = 1’b1.Initial Block An initial block starts at time 0. executes exactly once during a simulation. Example module stimulus. and then does not execute again. Each block finishes execution independently of other blocks.b.

Always Block The always block statement starts evaluating sensitivity list at time 0 and executes statements in the always block continuously in a looping fashion. end endmodule 61 . Intel Confidential Example module clock_gen. bit clock. forever #10 clock = ~clock. initial begin clock = 1’b0. This statement is used to model a block of activity that is repeated continuously. end always @(posedge clk) begin <statements>.

$display("Final PC = %h".PC). A final block is typically used to display statistical information about the simulation.$time/period).Final Blocks The final block is like an initial block. except that it occurs at the end of simulation time and executes without delays. Example final begin $display("Number of cycles executed %d". end Intel Confidential 62 . defining a procedural block of statements.

Lab 8: Procedural Blocks Create a SystemVerilog module: 1. 2. Define a final block to print the size of 'q' at the end of simulation Hint: Use final blocks Output: # Size of q = 4 Intel Confidential 63 . Define an initial block such that it generates a clock clk time period = 10ns NOTE: Need to initialize clock even though the bit data type is automatically done. 3. Increment 'counter' when always block is triggered 4. When counter reaches 4 call $finish system call Hint: Use if statement 5. Create an always blocks that stores the value of signal 'clk' into queue 'q' at positive edge of the clock.

Types of Assignment Blocking Nonblocking .

b = 2. c = 5 65 . #10. c = x // at time 20 a = 5. Execution flow is blocked until a given blocking assignment is complete. end // at time 0 a = 30 //at time 10 a = 5. b = x. a = 5.Blocking Assignment The simulator completes a blocking assignment (=) in one pass [execution and assignment]. c = 5 // at time 20 a = 5. Intel Confidential Example initial begin a = 30. b = 2. c = #10 a. If there is a time delay on a statement then the next statement will not be executed until this delay is over. b = x.

b = 2. Example initial begin a = 30. c <= #10 a.Nonblocking Assignment The simulator completes a nonblocking assignment (<=) in two passes. b = 2. Assignment to the lefthand side is postponed until other evaluations in a given simulation time step are complete. c = 30 66 Intel Confidential . #10. a <= 5. b <= 2. Right-hand side of the assignment is sampled immediately. end // at time 0 a = 30 //at time 10 a = 5. c = x // at time 20 a = 5.

Tasks and Functions .

return. Default port direction is input ANSI style portlists Implied begin…end task automatic my_task( input int local_a.local_b+1). return keyword is supported and global_b = local_b. // end ‘this’ copy of task end global_a = local_a. if (local_a == local_b) Arguments can be ANY begin SV type. terminates task at that point endtask Full recursion is supported (automatic variables/arguments stored on stack) • Can do concurrent calls • Can do recursive calls 8-68 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . etc.Tasks SystemVerilog makes a number of extensions to basic Verilog syntax. my_task(local_a-1. automatic tasks allocate memory dynamically at call time. int local_b). even structs.

counter++. counter++. int counter = 0. endtask initial begin reentry(). $display("Value of counter = %0d". counter++. counter++. endtask initial begin reentry(). counter++.Task usage examples [1] Example of a static task module task_reentry(). reentry(). task automatic reentry(). reentry(). $display("Value of counter = %0d". counter++. counter++. reentry(). counter++. end endmodule: task_reentry What will be the value of counter for each call to reentry()? Intel Confidential What will be the value of counter for each call to reentry()? 69 . task reentry(). counter). counter++. counter++. end endmodule: task_reentry Example of an automatic task module task_reentry(). int counter = 0. reentry(). reentry(). reentry(). counter).

Task usage examples [2]
module task_function (); int i, j, z; initial begin i = 5; j = 3; end initial begin #10; tsk (i, z, j); $display("Z = %0d, J = %0d", z, j); // prints Z = 50, J = 4 end task tsk (input int t1, output int t2, inout int t3); t2 = 10 * t1; t3++; endtask: tsk endmodule
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automatic functions allocate memory dynamically at call time (full recursion). Default port direction is input (also supports output) ANSI style portlists Implied begin…end

function automatic int factorial (int n); if (n==0) return(1); // factorial 0 is 1 else return(factorial(n-1)*n); endfunction

Arguments and return type can be ANY SV type, even complex structs, etc.

return(value) is supported and terminates function at that point

function void inverta(); a = !a endfunction reg a;
Return type of void means no return value! Recommended style (instead of writing a task) to guarantee a task executes with 0 delay.

initial inverta(); // function called like a task
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Function usage examples
Example 1
function void show_packet(); $display("=================="); $display("Packet Type = %s", context_name); $display("Address = %h", addr); $display("Data = %h", data); $display("==================="); endfunction

Example 2
typedef enum {FALSE, TRUE} bool; bool cache_range; function bool is_cache_range (); if (addr > 0 & addr < 10) begin cache_range = TRUE; $display("addr in cache range = %d", addr); return TRUE; end else begin cache_range = FALSE; return FALSE; end endfunction

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Functions Function can enable other functions only. Functions should execute in zero simulation time. [Pass by reference not supported in Modelsim 6. By default arguments are passed by value.Task and Functions Usage .1] Intel Confidential 73 . Tasks may have zero or more arguments of type input. Task cannot be called from functions. output or inout types. output and inout. Functions have only one return value but SystemVerilog also allows functions to have input.Summary Tasks Tasks can enable other tasks and functions Tasks may execute in non-zero simulation time. Both tasks and functions support passing arguments by reference.

endfunction // a local copy of ‘m’ is // created when ‘val’ is // called. <function body>. each copy retains a local copy of argument. Example function int val (byte m [3:0]). When defined as automatic. Changes to arguments in subroutine are not visible outside.Task and function argument passing Passing by value is the default mechanism for passing arguments. Intel Confidential 74 . Copies arguments passed into subroutine area.

5. 5).Default argument values – Tasks/Functions SV allows a subroutine declaration to specify default value for each argument. When subroutine is called. Example task read (int j =0. endtask // task can be called using // following default arguments read (. arguments with default values can be omitted from the call and corresponding default values are used. 5). int k. 1) read (2. // equivalent: read (0. // equivalent: read (2. // error since k has no default // value Intel Confidential 75 . data = 1). BKM: Default arguments should be optional arguments and should be the final set of arguments. 1) read ().

returns the value of 1 indicating success. 3. Takes queue and index value as input 2. 4.Lab 9a Create a SystemVerilog module as described below: 1. Intel Confidential 76 . changes the value of str stored in queue at index 1 to "Intel Ireland" from "Intel Folsom“. 3. str = "Intel Folsom" Display the size of the queue. 5. index =1. str = "Intel Chandler" 2. Define a function named "change_str" which does the following: 1. 2. Define a queue 'q' of string type. index =0. Define a named initial block "store_info" Store the following values into the queue 1.

# # # # # # Takes queue and return value from "change_str" as inputs The default inital value [task input argument: ret_value] shall be set to 0. q[%0d] = %s" Notes: "change_str" and “show" are called from named initial block "store_info". 2.Lab 9b 6. Define a task named “show" which does the following: 1.lab9 run –all Size of storage q = 2 q[0] = Intel Chandler q[1] = Intel Ireland q -f Intel Confidential 77 . 7. When the return value from "change_str" function is 1. 3. prints the elements stored in the queue using the following format: Output: Loading work.

Hierarchy Who comes first .

Modules The basic hardware unit in Verilog. Hierarchy of design Ports represent communication Inout Inputs Module Outputs Intel Confidential 79 .

Examples: input bit[3:0] x. etc. z. inout Type – wire. input bit w[3:0]. bit. output. input int x. y.Ports Connections Direction – input. output reg r. Intel Confidential 80 . inout logic s. output logic q. user-defined. logic.

Module syntax module x (port_list).data(data). output logic w_or_rb ). data. . end : place_holder endmodule : cpu // Error prone cpu cpu_inst1(addr. . // Better cpu cpu_inst2(.* ). module_body endmodule : x Instantiation x x1 (port_binding_list).w_or_rb(w_or_rb) ). // Newer cpu cpu_inst3( . output logic[63:0] addr. initial begin : place_holder $display(“A NOTHING CPU”).addr(addr). Example module cpu (inout logic[63:0] data. Intel Confidential 81 . w_or_rb).

Generic parameters (ala VHDL generics) Elaboration time constants Separate “ports” on a module Example
module xyz #(parameter int width = 8) (input x[width-1:0], output y)); assign y[width-1:0] = x[width-1:0]^ 8’hAE; endmodule xyz #(.width(14)) xyz1 (.x(inp), .y(outp));

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Multiple drivers
Most nets have only one driver Nets with multiple drivers need to have a resolution function In SystemVerilog there is a wire type that includes a resolution function Example
wire x; dut dut1(.outp(x)); dut dut2(.outp(x));
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Great coding efficiency can be achieved by modeling the blocks of a system at different levels of abstraction, behavioral, rtl, gate, etc. In Verilog, the I/O between these blocks has always remained at the lowest “wire” level. High-performance system-level simulation requires the abstraction of inter-block communication.
module mmu(d, a, rw_, en); output [15:0] a; output rw_, en; inout [7:0] d; ... endmodule module mem(d, a, rw_, en); input [15:0] a; input rw_, en; inout [7:0] d; ... Traditional endmodule Verilog module system; wire [7:0] data; wire [15:0] addr; wire ena, rw_; mmu U1 (data, addr, rw_, ena); mem U2 (data, addr, rw_, ena); endmodule interface interf; logic [7:0] data; logic [15:0] addr; logic ena, rw_; endinterface module mmu(interf io); io.addr <= ad; ... endmodule module mem(interf io); adr = io.addr; ... endmodule SystemVerilog module system; interf i1; mmu U1 (i1); mem U2 (i1); endmodule
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addr rw_ ena




At it’s simplest an interface is like a module for ports/wires

8-84 • SV for Verification Using Questa: Functional Coverage

a = 0. Enhanced interface with methods • source/sink only call methods • source/sink don’t see low-level “details” like variables/structure. interface intf sink if (intf. sink a a a if ( a == 1) … Traditional Verilog approach • Simple netlist-level IO • source/sink can be abstracted but IO must stay at low level • IO operations are cumbersome Simple “bundle” interface • All accesses are through interface • Simplifies source/sink declarations source intf.wrt_a(0). source intf. etc.a = 0.IO Abstraction source reg a. • Easy to swap interface abstractions without any effect on source/sink Copyright © 2005 Mentor Graphics Corporation 8-85 • SV for Verification Using Questa: Functional Coverage . task rd_a().a == 1) … a reg a. task wrt_a().rd_a() == 1) a reg a. interface intf sink if ( intf.

Interface Characteristics • Interfaces bring abstraction-level enhancements to ports. etc. etc. • Interfaces are defined once and used widely. This includes tasks. pipelining. initial/always blocks. may be captured in an interface rather than the connecting modules. parameters. not just internals. functions. 8-86 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . e. • Interfaces are synthesizable. so it simplifies design. Changing a bus spec (add a new signal?) means editing the interface only. • An interface may contain any legal SystemVerilog code except module definitions and/or instances.g. • Bus timing.

Interface in hierarchy Interfaces appear as normal module instantiations in design hierarchy. At the moment. Interface instances interface name: bfm_interface Instantiated twice: bi1. bi2 Intel Confidential 87 . interfaces cannot be instantiated in VHDL blocks.

i(i. … endmodule: s module top(). b. … endmodule: m module s (i2. endmodule: top Intel Confidential Restrict access to internal interface signals Protect implementation signals from corruption 88 .modport Different users of interface need different views Master/Slave Example interface i2. d).master)). c. d). modport master (input a. modport slave (output a. endinterface : i2 module m (i2. input c.slave)). wire a. m u1(.master i). b.slave i). i2 i().i(i. d. b. s u2(. output c.

and an output named b modb has an input named b. and an output named a Use an interface to connect Intel Confidential 89 . moda has an input named a.Lab 10 Create modules moda and modb.

Clocking blocks Synchronous blocks can have race conditions when all trying to evaluate blocks in same time step Clocking blocks capture timing and synchronization requirements Intel Confidential 90 .

endclocking : block_name clocking bus @(posedge clock1). input data. output negedge ack. endclocking Intel Confidential 91 .Clocking block syntax clocking block_name clocking_event.enable. enable=top. default input #10ns output #2ns. ready. item list. input #1 addr.mem1.

Program Blocks A program block is similar to a module. end initial begin: there $display(“Hello There”). It is used for testbench code. program helloWorld(). end endprogram: helloWorld Intel Confidential 92 . initial begin: hello $display("Hello World").

modules. UDPs. Program blocks may contain one or more initial blocks. but not the other way around. or other programs. but may not contain always. Intel Confidential 93 . When all program blocks complete the simulation ends. Programs may be explicitly exited using the $exit task.Program Blocks Programs can be instantiated inside modules. interfaces.

Day Two .

Classes SystemVerilog and Object Oriented Programming Testbench Only .

etc. “Bob’s car”. “Sally’s truck”. Objects/Classes have: Data Operations/Methods Example: A class might be “Automobile”. etc. speed. Start. increaseSpeed. etc. turn.Object Oriented Primer A Class is a description of some group of things that have something in common. stop. Instances of the “Automobile” class might be “Joe’s car”. Intel Confidential 96 . Color. Objects are individual instances of “classes”. direction. Encapsulation: Encapsulate implementation details internal to the object/class.

Classes Inheritance: (is-a relationship) Allows users to extend existing classes. an “Automobile” class might have 4 instances of a “wheel” class. In these cases.e. When using inheritance. users might create subclasses for “sedan”. “van”. It is allowed to override them. a wheel is not an “Automobile”. a “sedan” is a “Automobile”. For example. In this case. i. Extending the “Automobile” class example. or use them as-is. etc. making minor modifications. so inheritance should not be used. Intel Confidential 97 . the subclass IS-A superclass. “truck”. The “van” class might also have a “minivan” subclass. Etc. the sub-class “inherits” all the parents public/protected data properties and methods. Composition: (has-a relationship) Composition is used for the case where one object HAS-A instance of another class.

SystemVerilog can only process objects differently depending on their class. Intel Confidential 98 .Classes Polymorphism: Most common definition of polymorphism is the ability of the language to process objects differently depending on their data type or class.

endclass: myPacket Intel Confidential 99 . property declarations.Class Format class classname [extends superclass]. constructor. methods.

function new(). endtask: myTask.2. virtual function integer myFunc(int b). endfunction: myFunc endclass: myPacket Intel Confidential 100 . // inheritance byte data[$]. #10. output byte b). b = a + 5. return(b – 3). data = ‘{1. command = IDLE. bit [3:0] command. endfunction: new virtual task myTask(input byte a.Example Class class myPacket extends BasePacket.3.4}.

c.property2 = 11. Intel Confidential 101 . c. c = new.task1().” operator.function1(). c.property1 = 10.Referencing Properties and Methods Instance data properties and methods may be referenced/called using the “. c.

… endfunction: new Only one constructor per class allowed. Constructors may take arguments. endfunction: new // Creating an instance invokes the constructor: myInstance = data = { command = IDLE. … endfunction: new When extending a class constructor. Intel Confidential 102 . bit[12:0] addr = 0). call super.Constructors Example constructor function new().4}.3. function new(). function new(int a = 0. super.

// Equivalent: this. int x.y + this. x = y + z. … virtual function integer myFunc().myOtherMethod(). class myPacket extends BasePacket.z. endfunction: myFunc endclass: myPacket Intel Confidential 103 . z. myOtherMethod(). since the current instance is assumed if no variable is specified.this The special variable this is a predefined object handle for the current object instance. // Equivalent to: this. It is optional. y.x = this.

If one instance changes the value. $display(“Current value: %d”. staticProperty = val. it changes the value for all instances.staticProperty). static int staticProperty = 0. endfunction: setStaticProperty endclass: StaticExample Intel Confidential 104 . endfunction: showStaticProperty virtual function void setStaticProperty(int val). This means that all instances share the same value of this variable. class StaticExample. virtual function void showStaticProperty().Static Properties Static properties/data members are “static” to all instances of the class.

… endfunction: staticMethod endclass: StaticExample StaticExample::staticMethod(). To invoke a static method. Static methods may only modify static properties. static function void staticMethod(). static int staticProperty = 0. Intel Confidential 105 . use Classname::methodName class StaticExample.Static Methods Static methods do not require an instance of the class to operate on.

the method defined in the class of the object instance is called.bc. // Returns an instance myFirstClass bc = getFirstClassInstance(). endfunction: myFunc endclass: mySecondClass BaseClass bc.myFunc(6)). return(b + 10). endfunction: myFunc endclass: myFirstClass class mySecondClass extends BaseClass. virtual function in myFunc(int b). // Returns an instance mySecondClass bc = getSecondClassInstance(). return(b – 3).myFunc(6)). $display(“What do I print? %d” . endfunction myFunc endclass: BaseClass class myFirstClass extends BaseClass. 106 Intel Confidential . If the subclass overrides a method specified in the superclass. $display(“What do I print? %d” .bc. return(b + 3). virtual function int myFunc(int b).Polymorphism Instances of subclasses may be assigned to variables declared of the superclass type. This is useful for cases where the general algorithm is the same for all the subclasses. but only a few details need to change. virtual function int myFunc(int b). class BaseClass.

class myPacket extends BasePacket. Intel Confidential 107 . protected int x. To make data members visible only to the class. use the local keyword. class myPacket extends BasePacket. or any subclasses. use the protected keyword. local int x.Data Hiding and Encapsulation To make data members visible only to the class.

// Assignment of constant value in // declaration makes it constant // to all instances. function new(int id). // Single assignment in // constructor OK … Intel Confidential 108 . const constants are different from ` define constants because the initial value may be determined at runtime.Constant Class Properties The const keyword may be used to make class properties unchangeable. size = id * 4096. class myPacket extends BasePacket. and may be different per class instance. const int size.

… Intel Confidential 109 . Users must subclass the abstract class to create instances of the class.Abstract Classes The virtual keyword may be used on a class to make the class “abstract”. An abstract class may not be instantiated. virtual class BasePacket.

C2 c2Instance. C1 c1Instance.Typedef Class and Forward References Sometimes it is necessary to use a class before it has been defined. … endclass: C2 Intel Confidential 110 . … endclass: C1 class C2. then later define the class. you can use a typedef forward reference. // Forward declaration of C2 class C1. To do this. Example: typedef class C2.

Using your new class.5. Hint: $sformat(str. DATA=0x%h".x. x. // Returns formatted representation of // xaction.setData(‘{1.length.2. setData(byte d[$]). The Xaction class should have the following Properties: byte int data[$].8}). x = new. Xaction x. // Length in bytes Methods: // Sets data to value passed and // length to the size of queue"Len=%d. Format should be: // Len=X. $display(“%s”. Data=0xXXXXXXXX string toString().6.Lab 11a: Classes Create an “Xaction” class.toString()).3. run the following test code.7. Intel Confidential 111 . // Queue of bytes length.

stall().8}). $display(“current time = %t”.Lab 11b: Classes Modify lab10a and create a subclass of the Xaction class that has the following property added: int iws. // Initiator wait states // Wait IWS time steps stall(). s = new. Intel Confidential 112 .x. s.7. x = s. Data=0xXXXXXXXX. IWS=X Execute the following testcode. Be sure to use super. x.setData(’{5.iws = 10. Add a task to the class that waits for the number of time steps specified in iws: Override the toString() method. add printing the iws value.toString. Xaction x. $display(“current time = %t”.6. and not reimplement the toString of the parent class: // Len=X.$time). SubXaction s.$time). s. $display(“%s”.toString()).

Intel Confidential 113 . Virtual interfaces let BFM models manipulate virtual set of signals instead of actual RTL signals. Syntax: virtual <interface name> <variable name>. need a specialized mechanism Virtual interfaces provide a mechanism for separating test programs/BFM models from the actual signals.Virtual Interfaces Classes cannot have modules or interfaces. Virtual interface is a variable that represents an interface instance.

@(posedge bus.req <= 1'b1. // class instance BFM mybfm = new (infc_b).req. clk). logic [7:0] data.Virtual Interfaces Example // interface // definition interface Bus (input logic clk). bus. bit req. $time). bus.clk). bit grant. // need to initialize virtual interface // in constructor bus = b. logic [7:0] addr. Xaction xaction. // dut instance dut dut1 (infc_b. endtask: req_bus endclass: BFM Intel Confidential 114 . virtual Bus bus. endfunction task req_bus(). function new (virtual Bus b). class BFM. endinterface: Bus // testbench // interface instance Bus infc_b (clk). xaction = new. $display("Req = %b @ %0t".

Random Constraints How to decide how random to be .

Random data sources Random exercise of stimulus allows easy cases to be done easily Ability to “tune” random stimulus usually gives more coverage with less work (be careful) Save the impossible cases until the Design Under Test (DUT) is healthier Works hand-in-hand with functional coverage Intel Confidential 116 .

thread stable.Simplest randomness $urandom system tasks $urandom() is SV. deterministic $urandom returns unsigned 32-bit integers Procedural call can be inserted wherever needed Intel Confidential 117 .

endclass : x x x_inst = new. initial begin : random_loop forever @(posedge clk) x_inst.randomize()” is called Example: class x.More sophisticated mechanisms Random variables (rand modifier – classes only) Must be properties of a class. rand int a. b. except for some explicit randomization Select new random value each time “. c. end : random_loop Intel Confidential 118 .randomize().

What’s ‘randc’ for? Exhaustive permutations of a variable ‘c’ is for “cyclic”. every value of the variable will be reached before any value is duplicated Caution… special solver ordering for randc Intel Confidential 119 .

} c_eq_10 {c == 10.} How many permutations are now possible? Intel Confidential 120 . b > 0. c > 0.} b_in_range { b >= 2 && b <= 8.Constraints Set of Boolean algebraic expressions Relationships between random variables and: Other random variables Non-random state variables Example: constraint constraint constraint constraint a_le_b { a <= b. } all_gt_0 {a > 0.

42. int z = ’hff.Constraints Restrict range of possible values Can use state variables to restrict range of random variables Example: int x[7] = ’{3.27.6. w = 10. constraint c_within_set_of_x { c inside x. } Intel Confidential 121 .1}. } constraint b_between_w_z { b <= z && b >= w.10.5.

} x. } z.randomize() begin … end -solvefaildebug Intel Confidential y.Conflicting constraints What happens when you impose constraints that conflict in some way? Example: constraint x_gt_y { x > constraint y_gt_z { y > constraint z_gt_x { z > … if ( x_inst. } == 0 ) // Solver error Modelsim cmdline setting 122 .

x < y+b-c*10>>20 Other constraint operations set membership implication iterative constraint variable ordering functions within -> or if…else… foreach solve … before … func_x() Intel Confidential 123 .Constraint operators Any Verilog boolean expression i.e.

Implication constraint Uses one boolean to decide if another constraint must hold (trans_size == SMALL) -> (length < 10) (trans_size == MED) -> (length >= 10 && length <= 100) (trans_size == LARGE) -> (length > 100) Advanced note: a -> b is equivalent to !a || b Intel Confidential 124 .

8. 4. 10}. including reference to other elements of array constraint foreach A[i] } constraint foreach (k < } c1 { ( A[i] ) inside {2.size-1) -> A[k+1] > A[k]. Intel Confidential 125 . 6.Loop/array constraints Constrain every element of an array in some fashion. c2 { ( A[k] ) A.

Arguments to . randomize class members according to declaration modifiers Optional arguments Specify the variables which are random Can make ‘rand’ override declaration type for this call Declares entire set of random variables for this run of Constraint Solver ‘null’ argument forces checking constraints only Cannot change ‘randc’ to ‘rand’ Intel Confidential 126 .randomize() Normal form of .randomize() No arguments.

}.randomize with {} Specify inline constraints that are added to constraint set to solve trans. z > buzz..randomize() with { x < 100. Intel Confidential 127 .

io_read := 1. [10:50] :/ 9 }. [3:9] :/ 1. io_write := 1. idle := 1 }. } Intel Confidential 128 . mem_read := 5. lrw := 1. } constraint distConstraint { cmd dist { mem_write := 10. lrrww := 1.Distribution Constraints Operators: := :/ dist Example: constraint twsConstraint { tws dist { [0:2] :/ 10.

} // Mem above 16-bit is write-only IO devices constraint c5 { (!wr_or_rd_b) -> (addr[19:16] != 0). LRG} trans_len. endfunction : toString endclass : transaction <CONTINUED> Intel Confidential 129 . class transaction { rand bit [19:0] addr. MED.} constraint c4 { (len == LRG) -> (byte_len > 8). rand trans_len len. } constraint c2 { (len == SM) -> (byte_len <= 4).Putting it all together module test_rand. addr. rand bit wr_or_rd_b. (wr_or_rd_b ? “WR” : “RD”). constraint c1 { wr_or_rd_b -> len != LRG. } virtual function string toString() return sformat(“%5H: %s %d bytes”. } constraint c3 { (len == MED) -> (byte_len > 4 && byte_len <= 8). byte_len). rand bit [3:0] byte_len. typedef enum {SM.

intial begin : test_body int counter = 0. counter++. repeat (20) begin : rand_gen if (trans. end $display(“%d: %s”. trans.randomize() == 0) begin $display(“ERROR: Random constraints conflict”).Putting it all together (cont) transaction trans = new().toString()). end : rand_gen end : test_body endmodule : test_rand Intel Confidential 130 . $finish.

Add a rand property named size. with the following enumerated values: SMALL. Add a distribution constraint that make the size: SMALL 70%. Intel Confidential 131 . 3. Write a loop that calls randomize() 40 times. MEDIUM 20%. Add a constraint that sets the length based on the size property: SMALL : (length <= 10) MEDIUM : (length >10) && (length <=20) LARGE : (length > 20) && (length < 100) (Note: Add a constraint saying the length must be > 0) 4. printing the Xaction after each randomize() call.Lab 12: Random Constraints Modify the Xaction class created in lab11 and make all properties rand. LARGE. 2. 1. MEDIUM. LARGE 10%.

tasks.Packages A mechanism for sharing parameters. types. sequences. functions. interfaces and programs Intel Confidential 132 . classes. and properties among modules. data.

y = FALSE. TRUE The importing identifiers become directly visible in the importing scope: -c Intel Confidential import p::*. FALSE. y = p::TRUE A qualified package identifier is visible in any scope All declarations inside package p become potentially directly visible in the importing scope: .c. endpackage u = p::c. typedef enum {FALSE. BOOL c = TRUE. import p::c if ( ! c ) … 133 . TRUE} BOOL.Package Search Order Rules package p. BOOL.

import p::*. int a. endclass typedef enum {FALSE. BOOL b = TRUE. endmodule Intel Confidential 134 . TRUE} BOOL. int b.Package Example keyword package … endpackage Example: package p. class Data. endmodule OR module top. endpackage : p module top. p::BOOL b = p::TRUE.

Write a top level module that print out both C value Intel Confidential 135 .Lab 13: Packages Create two packages which contains an int C and C is initialized with two different values.

System Tasks .

only one $monitor active Intel Confidential 137 . $write – printf-ish ($display w/out newline) $sformat – print formatted string (ala sprintf) $monitor – Implicit task to call $display any time arguments change. with “\n” implied $display (format_string.Display $display – printf-ish. arguments).

Time $time – Returns 64-bit time normalized to unit timescale. most common for error messages $realtime – floating point scaled to timescale $stime – least significant 32-bits of time Intel Confidential 138 .

Intel Confidential 139 . initial @(posedge all_bfms_done) $finish(). final blocks $stop – halt simulation $exit – quit execution of program block (SV-only) Example initial #10000 $finish().Simulation Control $finish – end simulation (quit simulator).

args). "%x %x". “w”). hexStartAddr. Example string buf_s. end if (2==$sscanf(buf_s. if (chars_read == 0) begin $display(“End of file”). “r”). $fgets(string str. string mode) $fgetc(int fd). $ungetc(char c. FORMAT. hexStartAddr. int fd). hexEndAddr). hexEndAddr) ) begin $display(“Address Range: %8x -> %8x”. int fd). args). out_fd = $fopen(“output_file”. $finish(). $fscanf(int fd. FORMAT. chars_read = $fgets(buf_s. in_fd = $fopen(“input_file”.File I/O integer char int integer integer integer fd c code code code code = = = = = = $fopen(string filename. end Intel Confidential 140 . in_fd). $sscanf(string str.

File I/O $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo $fgetc $fflush $fgets $fmonitor $fmonitorb $fmonitorh $fmonitoro $readmemb $swrite $swriteo $sformat $fscanf $fread $fseek $fopen $fstrobe $fstrobeb $fstrobeh $fstrobeo $ungetc $ferror $rewind $fwrite $fwriteb $fwriteh $fwriteo $readmemh $swriteb $swriteh $sdf_annotate $sscanf $ftell Intel Confidential 141 .

Random functions $random $dist_chi_square $dist_exponential $dist_poisson $dist_uniform $dist_erlang $dist_normal $dist_t Intel Confidential 142 .

if (CK) count = count + 1. Example … always @(CK or D) begin : latch_counter int count. By providing blocks with names provides the following advantages: Declaration of local variables. Named blocks are part of the design hierarchy. end end : latch_counter … Intel Confidential 143 .Named blocks Blocks can be provided names. begin O = D . Local variables declared can be accessed through hierarchical referencing.

Threads .

#5 a = 3.Sequential Blocks There is the difference between a sequential and a concurrent block: Simulator executes statements in a sequential block in sequence It finishes the current statement. then begins the next You always know the order in which it actually executes the statements The simulator exits the block after finishing the last statement Intel Confidential Example begin #5 a = 1. end 145 . #5 a = 2.

Example fork begin $display( "First Block\n" )..Concurrent Blocks The simulator executes statements in a concurrent block in parallel It starts executing all statements simultaneously You can not know the order in which it actually executes statements scheduled for the same simulation time The simulator exits the block after finishing the latest statement.join is illegal. @eventA. end begin $display( "Second Block\n" ). # 20ns. end join Intel Confidential 146 . A return statement in the context of fork.

end NOTE Child processes spawned by a fork…join_none do not start to execute until the parent process hits a blocking statement Copyright © 2005 Mentor Graphics Corporation 8-147 • SV for Verification Using Questa: Functional Coverage .Dynamic Processes Inspired by the need for software verification environments to dynamically start and stop threads. SystemVerilog defines 2 new special cases of fork…join with associated keywords join_any & join_none join_any join_none fork … other blocks continue … as dynamic threads … join_any // any block finished begin fork … join_none // no waiting at all @(sig1).

task2(). begin fork task1(). join_none wait fork. task4(). join_any fork task3().1 The wait fork statement is used to ensure that all child processes (spawned by the process where it is called) have completed execution. end // continue when either task completes // continue regardless // block until tasks 1-4 complete 8-148 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation .Process Control – Wait Fork With Dynamic processes SystemVerilog needed to provide more global detection that spawned processes have completed. Q 6.

fork simul_test1.Process Control – Disable Fork Q 6. join endtask task test_with_timeout. Termination is recursive. fork run_tests(). join_any disable fork. in other words it terminates child processes. etc. first to finish triggers join_any // Kills the slower task (including any grandchild processes and so on) 8-149 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . grandchild processes. endtask // 2 child tasks spawned in parallel. timeout( 1000 ).1 The disable fork statement terminates all active child processes of the process where it is called. task run_tests. simul_test2.

Events Trigger Types [1] Triggering an event Named events are triggered using -> operator. bit clk. forever #10 clk = !clk . Event can be visualized in wave window. end endmodule Intel Confidential 150 . always @(posedge clk) -> a. module event_testing (). These events are such that trigger state cannot be observed but only their effect. b. always @(negedge clk) -> b. initial begin clk = 1'b0. Triggering an event unblocks all processes currently waiting on the event. event a.

end initial begin forever @(a) $display("event a triggered @ %0t. The statement executes without blocking and it creates a nonblocking assign update event in the time in which the event occurs.Events Trigger Types [2] Nonblocking event trigger They are triggered using ->> operator. counter++. The effect of this event is felt during the nonblocking assignment region of a simulation cycle. Example always @(posedge clk) begin if (counter == 2) ->> a. end Intel Confidential 151 . $time).

Waiting for an event @ is used to wait for an event. forever #10 clk = !clk . c. end endmodule 152 Intel Confidential . initial begin clk = 1'b0. bit clk. always @(posedge clk) -> a. always @(negedge clk) -> b. The @ operator blocks the calling process until the given event is triggered. event a. b. always @(a or b) -> c. Example module event_testing ().

b. Intel Confidential Example bit success. // event must occur in the // following order // ->a ->b ->c if not it fails. else success = 0. If any events are triggered out of order then it causes a fail of the operation. wait_order (a.Event Sequencing: wait_order() wait_order construct suspends the calling process until all specified events are triggered in the given order [left to right]. c) success = 1. 153 .

Event Variables [1] Merging Events When one event variable is assigned to another. // also triggers a Intel Confidential 154 . a = b. Example event a. -> a. Executing -> on either one of the events affects processes waiting on either event variable. b. both merge into one event variable. // also triggers b -> b.

Event Variables [2] Reclaiming Events When an event variable is assigned the special null value. Intel Confidential 155 . the association between the event variable and the underlying synchronization queue is broken. Example event E1 = null.

Event Variables [3] Event Comparison Event variables can be compared against other event variables or the special value null. Intel Confidential 156 . Example event E1. Equality (==) with another event or with null. E2. if ( E1 == E2 ) $display( "E1 and E2 are the same event" ). if ( E1 ) // same as if ( E1 != null ) E1 = E2. Inequality (!=) with another event or with null.

Semaphores Can be described as counters used to control access to shared resources by multiple processes [threads]. Printer1 Printer1 [1] [0] Printer2 [1] 3 keys 2 keys Printer3 [1] Print manager Intel Confidential 157 .

Return one or more keys back. Intel Confidential 158 . Try to get one or more keys without blocking. Obtain one or more keys.Semaphore Methods Semaphore provides following built-in methods: Method new() put() get() try_get() Use Create a semaphore with specified number of keys.

#6 spr.get(1). $display("initial1 returns 1 key at %0t". end Output: # initial1 takes 1 key at 1 # initial1 returns 1 key at 7 # inital2 takes 2 keys at 7 # inital2 returns 1 key at 12 # initial1 takes 1 key at 12 # q -f Intel Confidential initial begin:init2 #5 spr. #5 spr.$time). #1 spr.put(1).put(1). $display(" inital2 takes 2 keys at %0t". $display("initial1 takes 1 key at %0t".$time). initial begin:init1 #1 spr. $time). end endmodule: semaphore_test 159 .$time).get(2). $display("initial1 takes 1 key at %0t".get(1). $time). semaphore spr = new(2). $display(" inital2 returns 1 key at %0t".Semaphore example module semaphore_test ().

Mailboxes Mailbox is a communication mechanism that allows messages to be exchanged between different processes. Process 1 Process 2 Intel Confidential 160 .

Bounded mailboxes Number of entries is determined when the mailbox is created. Ex: mailbox m = new (5).Mailbox Types Mailboxes can be classified as: Unbounded mailboxes No restrictions placed on size of mailbox. put() will never block. Bound value should be positive. put() will be blocked if the mailbox is full. Ex: mailbox m = new (). // mailbox of depth = 5 Intel Confidential 161 .

Mailbox Methods Messages are placed in strict FIFO order. Mailboxes provides following built-in methods: Method new() put() get() try_get()/ try_peek() try_put() Create a new mailbox. Place a message in a mailbox. Useful only for bounded mailboxes. Retrieve a message from mailbox. Copies a message from mailbox without actually removing it. Intel Confidential Use peek() 162 . Try to place a message in mailbox without blocking. Try to retrieve a message from the mailbox without blocking. This does not guarantee order of arrival but that the arrival order shall be preserved.

Mailbox example
module mailbox_ex (); class Xaction; rand bit [2:0] addr; endclass typedef mailbox #(Xaction) mbx; mbx mb = new (); initial begin: t Xaction xaction; int mb_size; for (int i=0; i<5; i++) begin xaction = new; xaction.addr = 3’b111; $display("BEFORE:: Addr = %h", xaction.addr); mb.put(xaction); end 163 mb_size = mb.num(); for (int i=0; i<mb_size; i++) begin: dis_l Xaction d_x; mb.get(d_x); $display("Addr = %h", d_x.addr); end: dis_l end: t endmodule: mailbox_ex

Intel Confidential


Intel Confidential


foreach (Not in ModelSim 6.1) {BACKUP}
Implicit loop variable(s), multiple dimensions, any array type
int arr_x[]; typedef int arr_joe[7:0][3:8] arr_joe arr_y[$]; int arr_z[0:3*width][8*num-1:0]; initial begin arr_x = foreach foreach foreach end

new[10]; (arr_x[i]) statement (arr_y[m,n,p]) statement (arr_z[i,j]) statement

Intel Confidential


no more than one branch may be true for each evaluation. an error is generated Intel Confidential 166 . and no branch is true. simulator errors if this happens ‘priority’ .order of evaluation is important Both modifiers require that if no fall-through else/default statement is available.‘unique’ and ‘priority’ modifiers {BACKUP} Modifiers on if and case/casex/casez selection expressions ‘unique’ .

Lab 5: CRC} Intel Confidential 167 .

The operators << (left shift) and ^ (xor) will be needed. Process the bitstream given in the lab file and report the CRC. Intel Confidential 168 .Lab 5: CRC (cont) {BACKUP} Implement the CRC algorithm shown in the previous foil.

x) Intel Confidential 169 .Constraint Guards {BACKUP} Guards prevent the application of constraints. but remove the constraint from consideration of the constraint solver Use the same implication operator.x > 10) -> (y < 100 && y > a. just using state variables (!global_reset_state && cmd) -> (cmd_type != IDLE) Can even test obj pointers for null (a != null && a. similar to implication.

randomize() cannot include variables outside scope of class Intel Confidential 170 .std::randomize() {BACKUP} Procedural invocation of constraint solver Any variables can be the random variables “with” block for constraints Normal .

Disabling rand/constraints {BACKUP} rand_mode – method to toggle the “rand” attribute off on a class variable constraint_mode – method to toggle the application of a named constraint Intel Confidential 171 .

Random Stability {BACKUP} SV has thread random stability Intel Confidential 172 .

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