Intro To SystemVerilog

SystemVerilog for Verification

Day One

Welcome to the “Intro to SystemVerilog for Verification” class Requirements
Some HDL programming experience Some Unix experience Familiarity with some Unix editor Unix account in Folsom, Chandler, Dupont, or Penang.

Assumes use of Modelsim.
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Advanced classes go into more details. Class is an introduction only.Scope Of Course Introduction to SystemVerilog for verification Hands-on lab assignments Students will not be SystemVerilog experts at the end of this class. Next Classes: Functional Coverage/Temporal language/Checkers How to write a SV Test How to write an SV BFM Length: 2 days Intel Confidential 4 .

command line keyboard input Screen output Placeholders for data user should input Intel Confidential Courier Regular Italic 5 .Typographic Conventions Regular Text Courier Bold Course Content Code examples.

Intel Confidential 6 . SystemVerilog adds testbench features such as classes.What is SystemVerilog SystemVerilog is an IEEE extension to the Verilog language. and temporal expressions to Verilog. constraints.

intel.Getting More Information SystemVerilog LRM Comprehensive information on SV: Intel Confidential 7 Additional Information %20Lib/Forms/AllItems.pdf AVC Wiki

cd svtraining % vlib work % vmap work work Intel Confidential 8 .Using SystemVerilog To setup your environment to use SystemVerilog. type the following at the unix prompt: % source <local site specific setup script> Next. and create a work library: % mkdir svtraining. create a training directory.

end: hello endmodule: helloWorld Intel Confidential 9 . initial begin: hello $display("Hello World").Hello World module helloWorld().

Compiling SystemVerilog To compile your program. use the following command: % vsim -c -do "run -all.q -f" helloWorld Intel Confidential 10 . you must use the –sv option to Note: If you do not name your file ending in .sv. type the following: % vlog hello. To run your program.

Commenting Your Code Like C++. SystemVerilog supports two types of comments /* Block comments that can span * multiple lines */ // And single line comments $display(“hello”). // This is a comment Intel Confidential 11 .

Lab 1: Hello World Create a module that prints “Hello World” using the $display command. Intel Confidential 12 .

Basic Data Types .

Integer Data Type shortint int longint byte bit logic reg integer time 2-state (1. 64 bit signed 2-state.x. 64 bit unsigned Intel Confidential 14 . 32 bit signed 4-state. user-defined vector size 4-state (1. 0).z) user-def 4-state user-defined size 4-state. 16 bit signed 2-state.0. 8 bit signed 2-state. 32 bit signed 2-state.

shortint. reg and logic defaults to unsigned To create vectors. int. bit. use the following syntax: logic [1:0] L.Signed/Unsigned byte. integer and longint defaults to signed Use unsigned to represent unsigned integer value Example: int unsigned ui. // Creates 2 bit logic // vector Intel Confidential 15 .

>= {Str1. <=.Strings string – dynamic allocated array of bytes SV provides methods for working with strings Str1 == Str2 Str1 != Str2 <. Str2. >. … Strn} Str1[index] Equality Inequality Comparison Concatenation indexing – return 0 if out of range Intel Confidential 16 .

atobin atoreal itoa hextoa octtoa bintoa realtoa Intel Confidential 17 . atohex.String Methods len putc getc toupper tolower compare icompare substr atoi. atoct.

1. 32’hDEAD_BEEF. 2’b1Z Real Literal value.value Ex: 2.Literal Values Integer Literal – Same as verilog value – unsized decimal value size’base value – sized integer in a specific radix Ex: 4’b0101. 4’hC. [z|Z].4 Base Exponent ( E/e) Logic Value 0. [x|X] 18 Intel Confidential .

toupper()). “%b”.Lab 2: Data Types Write a top level module that displays the following output. Hint: Output: # The integer i is 0x00000014 # The unsigned integer ui is 0xdeadbeef # The logic L is 1Z # string str1 is "Hello World" # string str2 is "Cruel World“ Intel Confidential 19 . h. logic 3. $sformat(str. h). $display(“%d %h”. Use of the following data types: 1. int both signed and unsigned 2. string str.str. string int i. i. l) $display(“Logic value in upper case %s”.

Equivalent to: a = a + 3. Intel Confidential 20 .Operators Logic Operators & + | ~ % ^ / ~& * ~| ~^ << >> Arithmetic Operators ** <<< >>> Assignment Operators = += -= *= /= %= &= |= ^= <<= >>= <<<= >>>= Example: a += 3.

a now contains 2. Intel Confidential 21 . a++. if (a === b) $display(“Z === Z”). Comparison Operators == != === !== =?= !?= > < <= >= Example: a = 1'bZ. if (a != b) $display(“Z != Z”). b = 1'bZ.Operators Auto-increment (++) Auto-decrement(--) Example: a = 1.

“World”}. Sizes of assignment have to match. If LHS is smaller then assignment gets truncated. “ “. b.Concatenation The { } operator is used for concatenation. // v = 64b vector Can also be used on left hand side: {a. 32’b10}. Example: s = {“Hello”. v = {32’b1. c} = 3’b111. Intel Confidential 22 .

Intel Confidential 23 .Lab 3: Operators Write a SystemVerilog module to calculate the following. and print the result as an integer to the screen: (1101001 XOR 11111001) ÷ 5 Ignore remainder.

Flow Control Constructs How to go with the flow .

SystemVerilog additions Verilog includes: if-(else-(if)). ?: (ternary) SystemVerilog: Enhances for Adds do. for. while. foreach Intel Confidential 25 . case.while.. repeat. forever.

equivalent to expr != ‘0’ Chain ‘if’ statements: if (expr) begin … end else if (expr) begin … end else begin … end Intel Confidential 26 .if Verilog ‘if’ expressions Then branch taken for any nonzero known value of expr (no ‘x’ or ‘z’).

?: Operator. but conditional expr ? then_val : else_val Some call this the “ternary” operator. Intel Confidential 27 . in the same vein as “unary” and “binary”. with 3 operands. Ex: var_m = (x == 1) ? a : b.

case 4-value exact matching. item3. runtime evaluation. item4: begin statement end default: statement endcase Intel Confidential 28 . bit length of all expressions padded to same length case (expr) item: begin statement end item2. no fallthrough.

8’b01z10zx1: $display(“y”). casex Handle wild cards with either casez or casex casez: ‘z’ bit in either item or expression will be treated as a match for that bit casex: ‘z’ or ‘x’ bits will both match casex (8’bx100z011 ^ reg_a) 8’b1x1001?1: $display(“x”). endcase Intel Confidential 29 . 8’b11z01011: $display(“z”).casez.

Continuous execution, without end, of body statement(s) Used with timing controls Usually last statement in some block initial : clock_drive begin clk = 1’b0; forever #10 clk = ~clk; end : clock_drive
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Repeat a block ‘x’ times, no conditional test
repeat (expr) statement

What happens with expr = ‘x’ or ‘z’? Example
x = 0; repeat (16) begin $display(“%d”, x++); end
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Executes statement as long as expr evaluates to true

while (expr) statement

while (reg_i) begin something_happens(); reg_i = reg_i – 1; end

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step_assignment. while (condition) begin statement.for ‘C’ inspired for loop for (initial_assignment. end end Intel Confidential 33 . step_assignment) statement Equivalent to begin initial_assignment. condition.

end Intel Confidential 34 .size().operators (Mentioned in operator section) for (int i.Enhanced for SystemVerilog adds: Loop variable declaration Multiple statements in init and step blocks (comma separated) ++ and -. arrb[i]--. i < arr. i++) begin arr[i] += 200. j+=2.

x).while do statement while (expr).do. end while (x). 1) while (x) begin $display(“%d”. x). What’s the difference? x = 0.. x--. end 2) do begin $display(“%d”. x--. Intel Confidential 35 .

Lab 4: Flow control Write a SystemVerilog module to display the first 20 Fibonacci numbers. Fn = Fn-1 + Fn-2 Hint: F1 = F2 = 1 Intel Confidential 36 .

User Defined Types and Enumerated Types .

inch foot = 12. yard = 36. 8-38 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation .User Defined Types SystemVerilog supports a new keyword: typedef Syntax: typedef <base_data_type> <type_identifier> // inch becomes a new type // these are 2 new variables of type ‘inch’ typedef int inch .

c=7 Default assigned values start at zero 0 1 2 enum {red. gold} medal. // bool is NOT a SystemVerilog type bool myvar.Enumeration Syntax: enum [enum_base_type] { enum_name_declaration {. traf_lite2. c} vars. silver. b.enum_name_declaration} } enum_base_type: default is int Enumeration is a useful way of defining abstract variables. A sized constant can be used to set size of the type enum bit [3:0] { bronze=4’h3. // but it just became one “myvar” will now be checked for valid values in all assignments. YES} bool. green. green. // b=6. NOTE: Define an enumeration with “ enum ” enum {red. yellow} traf_lite1. yellow} lite. Values can be cast to integer types and auto-incremented enum { a=5. // All medal members are 4-bits Define a new type typedef enum {NO. arguments and relational operators 8-39 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation .

Colors col_ps. next(). green.Enumeration example Modelsim now allows viewing of enum types in waveforms similar to VHDL enum types. Example typedef enum {red. Intel Confidential 40 . white. always @(col_ps) col_ns = col_ps. blue. first(). To use enumerated types in numerical expressions the language provides the following functions: prev(). num() and name(). Colors col_ns. yellow. black} Colors. always @(posedge clk) col_ps <= last().

Casting .

signed(m)//changes m to signed inteltype’(2+3)//casting to a user defined type [inteltype].Casting A data type can be changed by using a cast (’) operation. Intel Confidential 42 .0 * 3. Syntax: <type>’(<value/expression>) Examples: int’(2.0)// real to int casting 7’(x-2)//number of bits to change size.

Arrays .

// each element is only 1-bit deep Ex: logic [3:0] m [5:0] Arrays can have packed and unpacked dimensions. In unpacked arrays [range is on the right side of the identifier] each individual element is considered by itself without any relation to other elements. Ex: logic m [5:0]. Ex: logic [3:0] m. m = 4’b1100.Packed/Unpacked Arrays In packed arrays [range is on the left side of the identifier] all elements are glued together and can be overwritten by zero/sign extension of a single literal. Intel Confidential 44 .

7.4}.12}}.10.'{9. // 2 groups of 3 8-45 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation .3. // 3 groups of 4 int m [1:2][1:3] = '{'{0.'{3{4}}}.11.1.6. // All elements “5” For more control.Array Literals and Default To help in assigning literal values to arrays SV introduces the default keyword: int k [1:1000] = '{default: 5}. int k [1:3][1:4] = '{'{1. consider the dimensions of the array and use { } to match those dimensions exactly.2}.'{5.2.8}.

not synthesizable Dynamic declaration of one index of an unpacked array Declares a dynamic array array_name of type data_type data_type array_name[] = new[ array_size ] [(array)] . addr = new[200](addr). 1st new array in SV. integer mem[ ]. data = new[256]. Allocates a new array array_name of type data_type and size array_size Optionally assigns values of array to array_name If no value is assigned then element has default value of data_type Examples: bit [3:0] nibble[ ]. int data[ ]. // Dynamic array of 4-bit vectors // Dynamic array of integers // Declare a dynamic array // Create a 256-element array // Create a 100-element array // Create a 200-element array // preserving previous values in lower 100 addresses Copyright © 2005 Mentor Graphics Corporation 8-46 • SV for Verification Using Questa: Functional Coverage . int addr = new[100].Dynamic Arrays Syntax: data_type array_name[] .

Cannot delete selected elements 8-47 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . int j = addr. // j = 256 function void delete() Empties array contents and zero-sizes it int addr[ ] = new[256].Dynamic Arrays – Methods function int size() Returns the current size of the array int addr[ ] = new[256].size().delete(). addr.

data2 = new[256](data1). data2. bit data1 [].size()). initial begin // create a 128 element array data1 = new [128]. $display("Size of array = %d". $display("Size of array = %d".Dynamic Array Example module dyn_arry (). data1.delete().size()). $display("Size of array = %d".size()). data1. end endmodule Intel Confidential 48 . data1.

// $ represents the ‘upper’ array boundary // uses concatenate syntax to write n to the left end of q1 // uses concatenate syntax to write n to the right end of q1 // read leftmost ( first ) item from list // read rightmost ( last ) item from list // determine number of items on q1 // delete leftmost ( first ) item of q1 // delete rightmost ( last ) item of q1 // step through a list using integers (NO POINTERS) for (int i=0. not synthesizable SV has a built-in list mechanism which is ideal for queues. q1 = q1[1:$].Queues and Lists 3rd new array in SV. item. stacks. int n. int q1[$]. q1 = ‘{ q1. // clear the q1 list Copyright © 2005 Mentor Graphics Corporation 8-49 • SV for Verification Using Questa: Functional Coverage .size. q1 = q1[0:$-1]. item = q1[0]. item = q1[$]. i++) begin … end q1 = { }. A list is basically a variable size array of any SV data type. q1 }. n = q1. q1 = ‘{ n. i < q1. etc.size. n }.

pop_back () => e = Q[$]. Q = Q[0.$] pop_back() Removes and returns the last element of the queue. e) => delete() Q = ‘{Q[0:i-1].push_front (e) => Q = ‘{e.$]} Prototype: function int size().delete (i) => Q = ‘{Q[0:i-1]. Q. Q = Q[1. Deletes the item at the specified index position. it returns 0. e = Q. Inserts the given item at the specified index position. If the queue is empty. Q.pop_front () => e = Q[0].Queue Methods size() insert() Returns the number of items in the queue. Prototype: function void delete (int index). Q} push_back() Inserts the given element at the end of the queue. Prototype: function queue_type pop_back(). Prototype: function void insert (int index. e} 8-50 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation .push_back (e) => Q = ‘{Q. e. Prototype: function void push_front (queue_type item). queue_type item). Q[i+1. Q.$]} pop_front() Removes and returns the first element of the queue. Prototype: function void push_back (queue_type item).$-1] push_front() Inserts the given element at the front of the queue. e = Q. Q[i. Prototype: function queue_type pop_front().insert (i. Q.

delete(1).push_back(0). Push to front of the queue q. i. i < q. Display all the contents in the queue for (int i = 0. Delete the element of queue at index 1 q. end: store_disp // // // // // endmodule: queues Intel Confidential 51 .size().push_front (0). q.Queue Example module queues (). q. int q [$]. // declare the q initial begin: store_disp Push elements into the queue q. Display its contents $display("Size of queue = %0d". q[i]).size()).push_back(1). i++) $display("q[%0d] = %0d".

sv The output will look as follows: # Loading work.lab6 # run –all # Size of queue = 3 # q[0] = 0 # q[1] = 1 # q[2] = 3 # q -f Intel Confidential 52 .Lab 6: Queues Write a SystemVerilog program with specification as defined in lab6.

Data type used as an index serves as lookup key and imposes an order. Intel Confidential 53 . It implements a lookup table of the elements of its declared type.Associative Arrays Associative arrays are used when the size of the array is not known or the data is sparse. Associative array do not have their storage allocated until it is used. In other words value_type array_name [key_type]. Syntax: data_type array_name [index_type].

Intel Confidential 54 .Index Types String Index Types Ex: int a [string]. a[“joe”] = 21. a[5] = 2’b11. Integer Index Types Ex: bit [1:0] a [int].

exists (<index>) first (<index>). Returns 1 if element exists at index else 0 assigns to the given index variable the value of the first/last (smallest/largest) index in the associative array. It returns 0 if the array is empty. and 1 otherwise. prev (<index>) Intel Confidential 55 . finds the entry whose index is greater/smaller than the given index.Associative Array Methods Function num() delete(<index>) Use Returns number of entries Index for delete optional. last (<index>) next (<index>). When specified used to delete given index else whole array.

// Display the size of the associative array $display("Size of hash = %0d". // store values at indexes of associative array db ["jill"] = 19. end // print the contents of associative array if (db.exists("jill")) // check if index exists and change value begin db["jill"] = 25. db ["joe"] = 21. s.num()). // Define an associative array initial begin: test string s.Example module asoc_arry (). int db [string].Age = %0d". if (db. end while (db. db[s]).Associative array methods .first(s)) do begin $display("Name = %s -. end: test endmodule: asoc_arry Intel Confidential 56 .

Lab 7: Associative Arrays 1. Display the size of the hash using $display statement Check if name Jane exists in the associative array and if it does change her age to 40. Print the contents of the associative array. 4. Make the following entries into assoc NAME AGE ---------------John 25 James 30 Jane 24 3. Intel Confidential 57 . 5.Name of person VALUE .Age 2. Define an associate array named 'assoc' assoc has the following attributes: INDEX .

Procedural Blocks .

Level-sensitive signal detection If the signal is already true. execution continues without stopping Intel Confidential 59 .Triggering sensitivity @(<signal>) waits for an edge on <signal> before executing the next statement Edge-sensitive signal detection @(posedge clk) – waits for a rising edge clock @(negedge rstb) – waits for a falling edge on rs wait(<signal>) waits for a condition to become true before executing the next statement.

reg a. typically using begin and end. If there are multiple initial blocks. initial begin #5 a = 1’b1. executes exactly once during a simulation. and then does not execute again.Initial Block An initial block starts at time 0. end endmodule Intel Confidential 60 . Multiple behavioral statements must be grouped. Example module stimulus. each block starts to execute concurrently at time 0. Each block finishes execution independently of other blocks.b. #25 b = 1’b0.

Intel Confidential Example module clock_gen. initial begin clock = 1’b0. end endmodule 61 .Always Block The always block statement starts evaluating sensitivity list at time 0 and executes statements in the always block continuously in a looping fashion. end always @(posedge clk) begin <statements>. forever #10 clock = ~clock. bit clock. This statement is used to model a block of activity that is repeated continuously.

end Intel Confidential 62 .Final Blocks The final block is like an initial block.PC). except that it occurs at the end of simulation time and executes without delays. Example final begin $display("Number of cycles executed %d". A final block is typically used to display statistical information about the simulation.$time/period). $display("Final PC = %h". defining a procedural block of statements.

3. Define an initial block such that it generates a clock clk time period = 10ns NOTE: Need to initialize clock even though the bit data type is automatically done. When counter reaches 4 call $finish system call Hint: Use if statement 5. Increment 'counter' when always block is triggered 4. 2.Lab 8: Procedural Blocks Create a SystemVerilog module: 1. Define a final block to print the size of 'q' at the end of simulation Hint: Use final blocks Output: # Size of q = 4 Intel Confidential 63 . Create an always blocks that stores the value of signal 'clk' into queue 'q' at positive edge of the clock.

Types of Assignment Blocking Nonblocking .

#10. Execution flow is blocked until a given blocking assignment is complete. Intel Confidential Example initial begin a = 30. If there is a time delay on a statement then the next statement will not be executed until this delay is over. c = #10 a. end // at time 0 a = 30 //at time 10 a = 5. b = 2. c = 5 // at time 20 a = 5. c = 5 65 . c = x // at time 20 a = 5. b = 2. b = x.Blocking Assignment The simulator completes a blocking assignment (=) in one pass [execution and assignment]. b = x. a = 5.

a <= 5. c <= #10 a. b = 2. Right-hand side of the assignment is sampled immediately.Nonblocking Assignment The simulator completes a nonblocking assignment (<=) in two passes. b = 2. #10. Assignment to the lefthand side is postponed until other evaluations in a given simulation time step are complete. end // at time 0 a = 30 //at time 10 a = 5. b <= 2. c = x // at time 20 a = 5. c = 30 66 Intel Confidential . Example initial begin a = 30.

Tasks and Functions .

automatic tasks allocate memory dynamically at call time. etc.Tasks SystemVerilog makes a number of extensions to basic Verilog syntax. even structs. my_task(local_a-1. // end ‘this’ copy of task end global_a = local_a. if (local_a == local_b) Arguments can be ANY begin SV type. Default port direction is input ANSI style portlists Implied begin…end task automatic my_task( input int local_a.local_b+1). terminates task at that point endtask Full recursion is supported (automatic variables/arguments stored on stack) • Can do concurrent calls • Can do recursive calls 8-68 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . int local_b). return keyword is supported and global_b = local_b. return.

reentry(). counter++. endtask initial begin reentry(). counter). task reentry(). endtask initial begin reentry(). end endmodule: task_reentry Example of an automatic task module task_reentry(). reentry(). counter). counter++. end endmodule: task_reentry What will be the value of counter for each call to reentry()? Intel Confidential What will be the value of counter for each call to reentry()? 69 . counter++. counter++. $display("Value of counter = %0d". int counter = 0. $display("Value of counter = %0d". task automatic reentry().Task usage examples [1] Example of a static task module task_reentry(). counter++. counter++. reentry(). counter++. reentry(). int counter = 0. reentry(). reentry(). counter++. counter++. counter++.

Task usage examples [2]
module task_function (); int i, j, z; initial begin i = 5; j = 3; end initial begin #10; tsk (i, z, j); $display("Z = %0d, J = %0d", z, j); // prints Z = 50, J = 4 end task tsk (input int t1, output int t2, inout int t3); t2 = 10 * t1; t3++; endtask: tsk endmodule
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automatic functions allocate memory dynamically at call time (full recursion). Default port direction is input (also supports output) ANSI style portlists Implied begin…end

function automatic int factorial (int n); if (n==0) return(1); // factorial 0 is 1 else return(factorial(n-1)*n); endfunction

Arguments and return type can be ANY SV type, even complex structs, etc.

return(value) is supported and terminates function at that point

function void inverta(); a = !a endfunction reg a;
Return type of void means no return value! Recommended style (instead of writing a task) to guarantee a task executes with 0 delay.

initial inverta(); // function called like a task
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Function usage examples
Example 1
function void show_packet(); $display("=================="); $display("Packet Type = %s", context_name); $display("Address = %h", addr); $display("Data = %h", data); $display("==================="); endfunction

Example 2
typedef enum {FALSE, TRUE} bool; bool cache_range; function bool is_cache_range (); if (addr > 0 & addr < 10) begin cache_range = TRUE; $display("addr in cache range = %d", addr); return TRUE; end else begin cache_range = FALSE; return FALSE; end endfunction

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Functions Function can enable other functions only. By default arguments are passed by value. [Pass by reference not supported in Modelsim 6.Task and Functions Usage .1] Intel Confidential 73 .Summary Tasks Tasks can enable other tasks and functions Tasks may execute in non-zero simulation time. output or inout types. Functions should execute in zero simulation time. Task cannot be called from functions. Tasks may have zero or more arguments of type input. Both tasks and functions support passing arguments by reference. Functions have only one return value but SystemVerilog also allows functions to have input. output and inout.

<function body>. When defined as automatic. Changes to arguments in subroutine are not visible outside. Intel Confidential 74 .Task and function argument passing Passing by value is the default mechanism for passing arguments. each copy retains a local copy of argument. Copies arguments passed into subroutine area. Example function int val (byte m [3:0]). endfunction // a local copy of ‘m’ is // created when ‘val’ is // called.

When subroutine is called. int k. BKM: Default arguments should be optional arguments and should be the final set of arguments. 1) read (2. arguments with default values can be omitted from the call and corresponding default values are used. 5. Example task read (int j =0. 1) read (). // error since k has no default // value Intel Confidential 75 . // equivalent: read ( data = 1). 5. endtask // task can be called using // following default arguments read (.Default argument values – Tasks/Functions SV allows a subroutine declaration to specify default value for each argument. 5). // equivalent: read (0. 5).

changes the value of str stored in queue at index 1 to "Intel Ireland" from "Intel Folsom“. Intel Confidential 76 . 5. str = "Intel Folsom" Display the size of the queue. 4. 3. index =1.Lab 9a Create a SystemVerilog module as described below: 1. returns the value of 1 indicating success. Takes queue and index value as input 2. 3. 2. str = "Intel Chandler" 2. Define a queue 'q' of string type. Define a function named "change_str" which does the following: 1. index =0. Define a named initial block "store_info" Store the following values into the queue 1.

prints the elements stored in the queue using the following format: Output: Loading work.lab9 run –all Size of storage q = 2 q[0] = Intel Chandler q[1] = Intel Ireland q -f Intel Confidential 77 .Lab 9b 6. When the return value from "change_str" function is 1. 2. Define a task named “show" which does the following: 1. # # # # # # Takes queue and return value from "change_str" as inputs The default inital value [task input argument: ret_value] shall be set to 0. 3. 7. q[%0d] = %s" Notes: "change_str" and “show" are called from named initial block "store_info".

Hierarchy Who comes first .

Hierarchy of design Ports represent communication Inout Inputs Module Outputs Intel Confidential 79 .Modules The basic hardware unit in Verilog.

Intel Confidential 80 . bit. input bit w[3:0]. output reg r. user-defined. output logic q. Examples: input bit[3:0] x. etc. output.Ports Connections Direction – input. inout Type – wire. inout logic s. logic. input int x. y. z.

. // Newer cpu cpu_inst3( .w_or_rb(w_or_rb) ).addr(addr).Module syntax module x (port_list). . output logic[63:0] addr. w_or_rb). Example module cpu (inout logic[63:0] data. output logic w_or_rb ). module_body endmodule : x Instantiation x x1 (port_binding_list). data. // Better cpu cpu_inst2(. initial begin : place_holder $display(“A NOTHING CPU”).* ). end : place_holder endmodule : cpu // Error prone cpu cpu_inst1( Intel Confidential 81 .

Generic parameters (ala VHDL generics) Elaboration time constants Separate “ports” on a module Example
module xyz #(parameter int width = 8) (input x[width-1:0], output y)); assign y[width-1:0] = x[width-1:0]^ 8’hAE; endmodule xyz #(.width(14)) xyz1 (.x(inp), .y(outp));

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Multiple drivers
Most nets have only one driver Nets with multiple drivers need to have a resolution function In SystemVerilog there is a wire type that includes a resolution function Example
wire x; dut dut1(.outp(x)); dut dut2(.outp(x));
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Great coding efficiency can be achieved by modeling the blocks of a system at different levels of abstraction, behavioral, rtl, gate, etc. In Verilog, the I/O between these blocks has always remained at the lowest “wire” level. High-performance system-level simulation requires the abstraction of inter-block communication.
module mmu(d, a, rw_, en); output [15:0] a; output rw_, en; inout [7:0] d; ... endmodule module mem(d, a, rw_, en); input [15:0] a; input rw_, en; inout [7:0] d; ... Traditional endmodule Verilog module system; wire [7:0] data; wire [15:0] addr; wire ena, rw_; mmu U1 (data, addr, rw_, ena); mem U2 (data, addr, rw_, ena); endmodule interface interf; logic [7:0] data; logic [15:0] addr; logic ena, rw_; endinterface module mmu(interf io); io.addr <= ad; ... endmodule module mem(interf io); adr = io.addr; ... endmodule SystemVerilog module system; interf i1; mmu U1 (i1); mem U2 (i1); endmodule
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addr rw_ ena




At it’s simplest an interface is like a module for ports/wires

8-84 • SV for Verification Using Questa: Functional Coverage

etc. • Easy to swap interface abstractions without any effect on source/sink Copyright © 2005 Mentor Graphics Corporation 8-85 • SV for Verification Using Questa: Functional Coverage . a = 0.wrt_a(0). Enhanced interface with methods • source/sink only call methods • source/sink don’t see low-level “details” like variables/structure.IO Abstraction source reg a. task rd_a().rd_a() == 1) a reg a. interface intf sink if ( intf.a == 1) … a reg a.a = 0. sink a a a if ( a == 1) … Traditional Verilog approach • Simple netlist-level IO • source/sink can be abstracted but IO must stay at low level • IO operations are cumbersome Simple “bundle” interface • All accesses are through interface • Simplifies source/sink declarations source intf. source intf. task wrt_a(). interface intf sink if (intf.

initial/always blocks. not just internals. e. pipelining. functions. 8-86 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . • Interfaces are defined once and used widely. may be captured in an interface rather than the connecting modules.Interface Characteristics • Interfaces bring abstraction-level enhancements to ports. parameters. • Bus timing.g. • An interface may contain any legal SystemVerilog code except module definitions and/or instances. etc. etc. This includes tasks. Changing a bus spec (add a new signal?) means editing the interface only. • Interfaces are synthesizable. so it simplifies design.

interfaces cannot be instantiated in VHDL blocks. At the moment. Interface instances interface name: bfm_interface Instantiated twice: bi1. bi2 Intel Confidential 87 .Interface in hierarchy Interfaces appear as normal module instantiations in design hierarchy.

d. … endmodule: s module top(). c. output c. modport master (input a. wire a.slave)). modport slave (output a. endmodule: top Intel Confidential Restrict access to internal interface signals Protect implementation signals from corruption 88 . d). b.i(i.slave i). s u2(. d). endinterface : i2 module m (i2. i2 i(). b. b.master)). … endmodule: m module s (i2. m u1(.master i).modport Different users of interface need different views Master/Slave Example interface i2. input c.i(i.

Lab 10 Create modules moda and modb. and an output named b modb has an input named b. moda has an input named a. and an output named a Use an interface to connect Intel Confidential 89 .

Clocking blocks Synchronous blocks can have race conditions when all trying to evaluate blocks in same time step Clocking blocks capture timing and synchronization requirements Intel Confidential 90 .

Clocking block syntax clocking block_name clocking_event.enable.mem1. enable=top. input data. ready. endclocking Intel Confidential 91 . input #1 addr. item list. default input #10ns output #2ns. output negedge ack. endclocking : block_name clocking bus @(posedge clock1).

Program Blocks A program block is similar to a module. program helloWorld(). It is used for testbench code. initial begin: hello $display("Hello World"). end endprogram: helloWorld Intel Confidential 92 . end initial begin: there $display(“Hello There”).

Intel Confidential 93 . UDPs. or other programs. Programs may be explicitly exited using the $exit task. interfaces. modules. but may not contain always. but not the other way around. Program blocks may contain one or more initial blocks. When all program blocks complete the simulation ends.Program Blocks Programs can be instantiated inside modules.

Day Two .

Classes SystemVerilog and Object Oriented Programming Testbench Only .

turn. increaseSpeed. Objects are individual instances of “classes”. Encapsulation: Encapsulate implementation details internal to the object/class. speed. direction. Intel Confidential 96 . “Bob’s car”. Objects/Classes have: Data Operations/Methods Example: A class might be “Automobile”. etc. Instances of the “Automobile” class might be “Joe’s car”. Start. etc. etc. stop. “Sally’s truck”.Object Oriented Primer A Class is a description of some group of things that have something in common. Color.

“truck”. making minor modifications. Etc.e. In this case. It is allowed to override them. or use them as-is. the sub-class “inherits” all the parents public/protected data properties and methods.Classes Inheritance: (is-a relationship) Allows users to extend existing classes. The “van” class might also have a “minivan” subclass. an “Automobile” class might have 4 instances of a “wheel” class. Composition: (has-a relationship) Composition is used for the case where one object HAS-A instance of another class. Intel Confidential 97 . i. “van”. In these cases. etc. For example. a “sedan” is a “Automobile”. so inheritance should not be used. the subclass IS-A superclass. users might create subclasses for “sedan”. When using inheritance. a wheel is not an “Automobile”. Extending the “Automobile” class example.

Classes Polymorphism: Most common definition of polymorphism is the ability of the language to process objects differently depending on their data type or class. Intel Confidential 98 . SystemVerilog can only process objects differently depending on their class.

constructor. endclass: myPacket Intel Confidential 99 . methods. property declarations.Class Format class classname [extends superclass].

2.4}. command = IDLE.Example Class class myPacket extends BasePacket.3. endtask: myTask. endfunction: myFunc endclass: myPacket Intel Confidential 100 . return(b – 3). endfunction: new virtual task myTask(input byte a. data = ‘{1. b = a + 5. #10. // inheritance byte data[$]. output byte b). virtual function integer myFunc(int b). bit [3:0] command. function new().

task1().Referencing Properties and Methods Instance data properties and methods may be referenced/called using the “.property2 = 11. c. c = new. c. Intel Confidential 101 .” operator. c.function1().property1 = 10. c.

Constructors may take arguments.2. endfunction: new // Creating an instance invokes the constructor: myInstance = new. function new().3. command = IDLE.4}.new(). call super. data = {1. … endfunction: new When extending a class constructor. Intel Confidential 102 . bit[12:0] addr = 0).new(). function new(int a = 0. super.Constructors Example constructor function new(). … endfunction: new Only one constructor per class allowed.

int x. since the current instance is assumed if no variable is specified.y + this. myOtherMethod().this The special variable this is a predefined object handle for the current object instance.myOtherMethod().z. … virtual function integer myFunc(). // Equivalent to: this. endfunction: myFunc endclass: myPacket Intel Confidential 103 . y. class myPacket extends BasePacket. // Equivalent: this. x = y + z. z. It is optional.x = this.

Static Properties Static properties/data members are “static” to all instances of the class. This means that all instances share the same value of this variable. staticProperty = val. If one instance changes the value. endfunction: showStaticProperty virtual function void setStaticProperty(int val).staticProperty). virtual function void showStaticProperty(). $display(“Current value: %d”. static int staticProperty = 0. it changes the value for all instances. endfunction: setStaticProperty endclass: StaticExample Intel Confidential 104 . class StaticExample.

static function void staticMethod(). Static methods may only modify static properties. To invoke a static method. … endfunction: staticMethod endclass: StaticExample StaticExample::staticMethod(). Intel Confidential 105 .Static Methods Static methods do not require an instance of the class to operate on. use Classname::methodName class StaticExample. static int staticProperty = 0.

Polymorphism Instances of subclasses may be assigned to variables declared of the superclass type. This is useful for cases where the general algorithm is the same for all the subclasses. endfunction: myFunc endclass: mySecondClass BaseClass bc. If the subclass overrides a method specified in the superclass.bc. $display(“What do I print? %d” . virtual function in myFunc(int b). return(b – 3). return(b + 3). endfunction: myFunc endclass: myFirstClass class mySecondClass extends BaseClass. // Returns an instance mySecondClass bc = getSecondClassInstance(). class BaseClass. but only a few details need to change. $display(“What do I print? %d” . endfunction myFunc endclass: BaseClass class myFirstClass extends BaseClass.bc.myFunc(6)). 106 Intel Confidential . virtual function int myFunc(int b). // Returns an instance myFirstClass bc = getFirstClassInstance(). virtual function int myFunc(int b). the method defined in the class of the object instance is called.myFunc(6)). return(b + 10).

use the protected keyword. To make data members visible only to the class. use the local keyword. Intel Confidential 107 . local int x. protected int x. class myPacket extends BasePacket. class myPacket extends BasePacket.Data Hiding and Encapsulation To make data members visible only to the class. or any subclasses.

const constants are different from ` define constants because the initial value may be determined at runtime. const int size. // Single assignment in // constructor OK … Intel Confidential 108 . size = id * 4096. class myPacket extends BasePacket. function new(int id).Constant Class Properties The const keyword may be used to make class properties unchangeable. and may be different per class instance. // Assignment of constant value in // declaration makes it constant // to all instances.

… Intel Confidential 109 . An abstract class may not be instantiated.Abstract Classes The virtual keyword may be used on a class to make the class “abstract”. Users must subclass the abstract class to create instances of the class. virtual class BasePacket.

… endclass: C1 class C2. // Forward declaration of C2 class C1. then later define the class. … endclass: C2 Intel Confidential 110 . C2 c2Instance. you can use a typedef forward reference. Example: typedef class C2.Typedef Class and Forward References Sometimes it is necessary to use a class before it has been defined. To do this. C1 c1Instance.

Format should be: // Len=X.2.x.7.setData(‘{1.5. // Length in bytes Methods: // Sets data to value passed and // length to the size of queue passed. // Returns formatted representation of // xaction. Hint: $sformat(str. Intel Confidential 111 .length. x.Lab 11a: Classes Create an “Xaction” class. Using your new class. The Xaction class should have the following Properties: byte int data[$]. DATA=0x%h"."Len=%d. $display(“%s”. run the following test code.3.8}). x = new. Xaction // Queue of bytes length.4. setData(byte d[$]). Data=0xXXXXXXXX string toString().6.

add printing the iws value.iws = 10. Be sure to use super.$time).8}).setData(’{5. // Initiator wait states // Wait IWS time steps stall(). Intel Confidential 112 .stall(). $display(“%s”. $display(“current time = %t”. SubXaction s. IWS=X Execute the following testcode. Data=0xXXXXXXXX. $display(“current time = %t”. Add a task to the class that waits for the number of time steps specified in iws: Override the toString() method.toString. Xaction x. x = s.Lab 11b: Classes Modify lab10a and create a subclass of the Xaction class that has the following property added: int iws. x.x. s = new.6.7. and not reimplement the toString of the parent class: // Len=X.toString()). s. s.$time).

Virtual interface is a variable that represents an interface instance. need a specialized mechanism Virtual interfaces provide a mechanism for separating test programs/BFM models from the actual signals. Syntax: virtual <interface name> <variable name>. Virtual interfaces let BFM models manipulate virtual set of signals instead of actual RTL signals.Virtual Interfaces Classes cannot have modules or interfaces. Intel Confidential 113 .

bus. logic [7:0] data. endtask: req_bus endclass: BFM Intel Confidential 114 . Xaction xaction.clk). virtual Bus bus. $display("Req = %b @ %0t". endfunction task req_bus(). // dut instance dut dut1 (infc_b. bit req. endinterface: Bus // testbench // interface instance Bus infc_b (clk). bit grant. // class instance BFM mybfm = new (infc_b). class BFM. // need to initialize virtual interface // in constructor bus = b.Virtual Interfaces Example // interface // definition interface Bus (input logic clk). logic [7:0] addr. $time). function new (virtual Bus b). clk).req <= 1'b1.req. @(posedge bus. bus. xaction = new.

Random Constraints How to decide how random to be .

Random data sources Random exercise of stimulus allows easy cases to be done easily Ability to “tune” random stimulus usually gives more coverage with less work (be careful) Save the impossible cases until the Design Under Test (DUT) is healthier Works hand-in-hand with functional coverage Intel Confidential 116 .

Simplest randomness $urandom system tasks $urandom() is SV. deterministic $urandom returns unsigned 32-bit integers Procedural call can be inserted wherever needed Intel Confidential 117 . thread stable.

rand int a. initial begin : random_loop forever @(posedge clk) x_inst. except for some explicit randomization Select new random value each time “. end : random_loop Intel Confidential 118 . c.randomize(). b. endclass : x x x_inst = new.More sophisticated mechanisms Random variables (rand modifier – classes only) Must be properties of a class.randomize()” is called Example: class x.

every value of the variable will be reached before any value is duplicated Caution… special solver ordering for randc Intel Confidential 119 .What’s ‘randc’ for? Exhaustive permutations of a variable ‘c’ is for “cyclic”.

} c_eq_10 {c == 10.Constraints Set of Boolean algebraic expressions Relationships between random variables and: Other random variables Non-random state variables Example: constraint constraint constraint constraint a_le_b { a <= b. } all_gt_0 {a > 0. c > 0.} How many permutations are now possible? Intel Confidential 120 .} b_in_range { b >= 2 && b <= 8. b > 0.

1}.10.6.5. } constraint b_between_w_z { b <= z && b >= w. int z = ’hff.42. w = 10.27. } Intel Confidential 121 . constraint c_within_set_of_x { c inside x.Constraints Restrict range of possible values Can use state variables to restrict range of random variables Example: int x[7] = ’{3.

Conflicting constraints What happens when you impose constraints that conflict in some way? Example: constraint x_gt_y { x > constraint y_gt_z { y > constraint z_gt_x { z > … if ( x_inst. } z.randomize() begin … end -solvefaildebug Intel Confidential y. } x. } == 0 ) // Solver error Modelsim cmdline setting 122 .

Constraint operators Any Verilog boolean expression i. x < y+b-c*10>>20 Other constraint operations set membership implication iterative constraint variable ordering functions within -> or if…else… foreach solve … before … func_x() Intel Confidential 123 .e.

Implication constraint Uses one boolean to decide if another constraint must hold (trans_size == SMALL) -> (length < 10) (trans_size == MED) -> (length >= 10 && length <= 100) (trans_size == LARGE) -> (length > 100) Advanced note: a -> b is equivalent to !a || b Intel Confidential 124 .

8.size-1) -> A[k+1] > A[k].Loop/array constraints Constrain every element of an array in some fashion. including reference to other elements of array constraint foreach A[i] } constraint foreach (k < } c1 { ( A[i] ) inside {2. Intel Confidential 125 . 6. 4. c2 { ( A[k] ) A. 10}.

randomize class members according to declaration modifiers Optional arguments Specify the variables which are random Can make ‘rand’ override declaration type for this call Declares entire set of random variables for this run of Constraint Solver ‘null’ argument forces checking constraints only Cannot change ‘randc’ to ‘rand’ Intel Confidential 126 .randomize() No arguments.Arguments to .randomize() Normal form of .

z > buzz.randomize() with { x < 100.randomize with {} Specify inline constraints that are added to constraint set to solve trans. }.. Intel Confidential 127 .

lrrww := 1. } Intel Confidential 128 . idle := 1 }. io_read := 1. [3:9] :/ 1. lrw := 1.Distribution Constraints Operators: := :/ dist Example: constraint twsConstraint { tws dist { [0:2] :/ 10. [10:50] :/ 9 }. io_write := 1. mem_read := 5. } constraint distConstraint { cmd dist { mem_write := 10.

rand trans_len len. endfunction : toString endclass : transaction <CONTINUED> Intel Confidential 129 . byte_len). typedef enum {SM. constraint c1 { wr_or_rd_b -> len != LRG. } constraint c3 { (len == MED) -> (byte_len > 4 && byte_len <= 8). } // Mem above 16-bit is write-only IO devices constraint c5 { (!wr_or_rd_b) -> (addr[19:16] != 0). class transaction { rand bit [19:0] addr. rand bit [3:0] byte_len. rand bit wr_or_rd_b. MED.Putting it all together module test_rand. } constraint c2 { (len == SM) -> (byte_len <= 4). (wr_or_rd_b ? “WR” : “RD”). addr. } virtual function string toString() return sformat(“%5H: %s %d bytes”.} constraint c4 { (len == LRG) -> (byte_len > 8). LRG} trans_len.

toString()).Putting it all together (cont) transaction trans = new(). end $display(“%d: %s”. trans.randomize() == 0) begin $display(“ERROR: Random constraints conflict”). repeat (20) begin : rand_gen if (trans. counter++. $finish. end : rand_gen end : test_body endmodule : test_rand Intel Confidential 130 . intial begin : test_body int counter = 0.

3. 2. MEDIUM. Intel Confidential 131 . LARGE 10%. Add a constraint that sets the length based on the size property: SMALL : (length <= 10) MEDIUM : (length >10) && (length <=20) LARGE : (length > 20) && (length < 100) (Note: Add a constraint saying the length must be > 0) 4. printing the Xaction after each randomize() call. Add a distribution constraint that make the size: SMALL 70%.Lab 12: Random Constraints Modify the Xaction class created in lab11 and make all properties rand. Write a loop that calls randomize() 40 times. 1. Add a rand property named size. with the following enumerated values: SMALL. MEDIUM 20%. LARGE.

functions. interfaces and programs Intel Confidential 132 . data. types. classes.Packages A mechanism for sharing parameters. and properties among modules. tasks. sequences.

TRUE The importing identifiers become directly visible in the importing scope: -c Intel Confidential import p::*.Package Search Order Rules package p. FALSE.c. endpackage u = p::c. y = FALSE. BOOL. typedef enum {FALSE. TRUE} BOOL. import p::c if ( ! c ) … 133 . y = p::TRUE A qualified package identifier is visible in any scope All declarations inside package p become potentially directly visible in the importing scope: . BOOL c = TRUE.

int b. endmodule Intel Confidential 134 .Package Example keyword package … endpackage Example: package p. endmodule OR module top. p::BOOL b = p::TRUE. endclass typedef enum {FALSE. int a. class Data. BOOL b = TRUE. TRUE} BOOL. endpackage : p module top. import p::*.

Lab 13: Packages Create two packages which contains an int C and C is initialized with two different values. Write a top level module that print out both C value Intel Confidential 135 .

System Tasks .

$write – printf-ish ($display w/out newline) $sformat – print formatted string (ala sprintf) $monitor – Implicit task to call $display any time arguments change. arguments). with “\n” implied $display (format_string.Display $display – printf-ish. only one $monitor active Intel Confidential 137 .

Time $time – Returns 64-bit time normalized to unit timescale. most common for error messages $realtime – floating point scaled to timescale $stime – least significant 32-bits of time Intel Confidential 138 .

final blocks $stop – halt simulation $exit – quit execution of program block (SV-only) Example initial #10000 $finish().Simulation Control $finish – end simulation (quit simulator). initial @(posedge all_bfms_done) $finish(). Intel Confidential 139 .

int fd). end if (2==$sscanf(buf_s. string mode) $fgetc(int fd). hexStartAddr. “r”). if (chars_read == 0) begin $display(“End of file”). chars_read = $fgets(buf_s. hexEndAddr). out_fd = $fopen(“output_file”. int fd). $fgets(string str. args). Example string buf_s. $ungetc(char c. in_fd). "%x %x". FORMAT. $sscanf(string str. hexStartAddr.File I/O integer char int integer integer integer fd c code code code code = = = = = = $fopen(string filename. hexEndAddr) ) begin $display(“Address Range: %8x -> %8x”. $finish(). “w”). $fscanf(int fd. FORMAT. args). in_fd = $fopen(“input_file”. end Intel Confidential 140 .

File I/O $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo $fgetc $fflush $fgets $fmonitor $fmonitorb $fmonitorh $fmonitoro $readmemb $swrite $swriteo $sformat $fscanf $fread $fseek $fopen $fstrobe $fstrobeb $fstrobeh $fstrobeo $ungetc $ferror $rewind $fwrite $fwriteb $fwriteh $fwriteo $readmemh $swriteb $swriteh $sdf_annotate $sscanf $ftell Intel Confidential 141 .

Random functions $random $dist_chi_square $dist_exponential $dist_poisson $dist_uniform $dist_erlang $dist_normal $dist_t Intel Confidential 142 .

Named blocks are part of the design hierarchy. Local variables declared can be accessed through hierarchical referencing. Example … always @(CK or D) begin : latch_counter int count. if (CK) count = count + 1.Named blocks Blocks can be provided names. By providing blocks with names provides the following advantages: Declaration of local variables. end end : latch_counter … Intel Confidential 143 . begin O = D .

Threads .

Sequential Blocks There is the difference between a sequential and a concurrent block: Simulator executes statements in a sequential block in sequence It finishes the current statement. end 145 . #5 a = 2. then begins the next You always know the order in which it actually executes the statements The simulator exits the block after finishing the last statement Intel Confidential Example begin #5 a = 1. #5 a = 3.

join is illegal. end join Intel Confidential 146 . end begin $display( "Second Block\n" ). A return statement in the context of fork..Concurrent Blocks The simulator executes statements in a concurrent block in parallel It starts executing all statements simultaneously You can not know the order in which it actually executes statements scheduled for the same simulation time The simulator exits the block after finishing the latest statement. Example fork begin $display( "First Block\n" ). @eventA. # 20ns.

Dynamic Processes Inspired by the need for software verification environments to dynamically start and stop threads. SystemVerilog defines 2 new special cases of fork…join with associated keywords join_any & join_none join_any join_none fork … other blocks continue … as dynamic threads … join_any // any block finished begin fork … join_none // no waiting at all @(sig1). end NOTE Child processes spawned by a fork…join_none do not start to execute until the parent process hits a blocking statement Copyright © 2005 Mentor Graphics Corporation 8-147 • SV for Verification Using Questa: Functional Coverage .

1 The wait fork statement is used to ensure that all child processes (spawned by the process where it is called) have completed execution. Q 6. begin fork task1(). task2(). end // continue when either task completes // continue regardless // block until tasks 1-4 complete 8-148 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . join_none wait fork. join_any fork task3(). task4().Process Control – Wait Fork With Dynamic processes SystemVerilog needed to provide more global detection that spawned processes have completed.

Process Control – Disable Fork Q 6. etc. in other words it terminates child processes. simul_test2. fork run_tests(). Termination is recursive.1 The disable fork statement terminates all active child processes of the process where it is called. endtask // 2 child tasks spawned in parallel. grandchild processes. task run_tests. first to finish triggers join_any // Kills the slower task (including any grandchild processes and so on) 8-149 • SV for Verification Using Questa: Functional Coverage Copyright © 2005 Mentor Graphics Corporation . fork simul_test1. join endtask task test_with_timeout. join_any disable fork. timeout( 1000 ).

module event_testing (). always @(negedge clk) -> b. Event can be visualized in wave window. forever #10 clk = !clk . always @(posedge clk) -> a. Triggering an event unblocks all processes currently waiting on the event. b. end endmodule Intel Confidential 150 .Events Trigger Types [1] Triggering an event Named events are triggered using -> operator. bit clk. These events are such that trigger state cannot be observed but only their effect. initial begin clk = 1'b0. event a.

end Intel Confidential 151 .Events Trigger Types [2] Nonblocking event trigger They are triggered using ->> operator. The statement executes without blocking and it creates a nonblocking assign update event in the time in which the event occurs. The effect of this event is felt during the nonblocking assignment region of a simulation cycle. end initial begin forever @(a) $display("event a triggered @ %0t. $time). counter++. Example always @(posedge clk) begin if (counter == 2) ->> a.

always @(posedge clk) -> a. c. Example module event_testing (). always @(a or b) -> c. forever #10 clk = !clk . b. event a.Waiting for an event @ is used to wait for an event. bit clk. The @ operator blocks the calling process until the given event is triggered. initial begin clk = 1'b0. always @(negedge clk) -> b. end endmodule 152 Intel Confidential .

Intel Confidential Example bit success. // event must occur in the // following order // ->a ->b ->c if not it fails. c) success = 1. If any events are triggered out of order then it causes a fail of the operation. else success = 0. wait_order (a. 153 . b.Event Sequencing: wait_order() wait_order construct suspends the calling process until all specified events are triggered in the given order [left to right].

-> a. a = b. // also triggers b -> b.Event Variables [1] Merging Events When one event variable is assigned to another. both merge into one event variable. Executing -> on either one of the events affects processes waiting on either event variable. b. Example event a. // also triggers a Intel Confidential 154 .

Example event E1 = null.Event Variables [2] Reclaiming Events When an event variable is assigned the special null value. Intel Confidential 155 . the association between the event variable and the underlying synchronization queue is broken.

Example event E1. Inequality (!=) with another event or with null.Event Variables [3] Event Comparison Event variables can be compared against other event variables or the special value null. Intel Confidential 156 . Equality (==) with another event or with null. if ( E1 == E2 ) $display( "E1 and E2 are the same event" ). if ( E1 ) // same as if ( E1 != null ) E1 = E2. E2.

Semaphores Can be described as counters used to control access to shared resources by multiple processes [threads]. Printer1 Printer1 [1] [0] Printer2 [1] 3 keys 2 keys Printer3 [1] Print manager Intel Confidential 157 .

Return one or more keys back. Obtain one or more keys. Try to get one or more keys without blocking.Semaphore Methods Semaphore provides following built-in methods: Method new() put() get() try_get() Use Create a semaphore with specified number of keys. Intel Confidential 158 .

#6 spr. end endmodule: semaphore_test 159 . $display("initial1 takes 1 key at %0t". $display(" inital2 returns 1 key at %0t".get(1).Semaphore example module semaphore_test ().$time).$time). end Output: # initial1 takes 1 key at 1 # initial1 returns 1 key at 7 # inital2 takes 2 keys at 7 # inital2 returns 1 key at 12 # initial1 takes 1 key at 12 # q -f Intel Confidential initial begin:init2 #5 spr. initial begin:init1 #1 spr. semaphore spr = new(2). $time). $display("initial1 returns 1 key at %0t".put(1).put(1). $display("initial1 takes 1 key at %0t". $time).get(1). $display(" inital2 takes 2 keys at %0t".$time). #5 spr. #1 spr.get(2).

Process 1 Process 2 Intel Confidential 160 .Mailboxes Mailbox is a communication mechanism that allows messages to be exchanged between different processes.

put() will be blocked if the mailbox is full. // mailbox of depth = 5 Intel Confidential 161 .Mailbox Types Mailboxes can be classified as: Unbounded mailboxes No restrictions placed on size of mailbox. Bounded mailboxes Number of entries is determined when the mailbox is created. Ex: mailbox m = new (5). Bound value should be positive. Ex: mailbox m = new (). put() will never block.

Useful only for bounded mailboxes. Place a message in a mailbox. Try to retrieve a message from the mailbox without blocking. Intel Confidential Use peek() 162 . This does not guarantee order of arrival but that the arrival order shall be preserved. Try to place a message in mailbox without blocking.Mailbox Methods Messages are placed in strict FIFO order. Copies a message from mailbox without actually removing it. Retrieve a message from mailbox. Mailboxes provides following built-in methods: Method new() put() get() try_get()/ try_peek() try_put() Create a new mailbox.

Mailbox example
module mailbox_ex (); class Xaction; rand bit [2:0] addr; endclass typedef mailbox #(Xaction) mbx; mbx mb = new (); initial begin: t Xaction xaction; int mb_size; for (int i=0; i<5; i++) begin xaction = new; xaction.addr = 3’b111; $display("BEFORE:: Addr = %h", xaction.addr); mb.put(xaction); end 163 mb_size = mb.num(); for (int i=0; i<mb_size; i++) begin: dis_l Xaction d_x; mb.get(d_x); $display("Addr = %h", d_x.addr); end: dis_l end: t endmodule: mailbox_ex

Intel Confidential


Intel Confidential


foreach (Not in ModelSim 6.1) {BACKUP}
Implicit loop variable(s), multiple dimensions, any array type
int arr_x[]; typedef int arr_joe[7:0][3:8] arr_joe arr_y[$]; int arr_z[0:3*width][8*num-1:0]; initial begin arr_x = foreach foreach foreach end

new[10]; (arr_x[i]) statement (arr_y[m,n,p]) statement (arr_z[i,j]) statement

Intel Confidential


simulator errors if this happens ‘priority’ .‘unique’ and ‘priority’ modifiers {BACKUP} Modifiers on if and case/casex/casez selection expressions ‘unique’ .order of evaluation is important Both modifiers require that if no fall-through else/default statement is more than one branch may be true for each evaluation. and no branch is true. an error is generated Intel Confidential 166 .

Lab 5: CRC} Intel Confidential 167 .

Process the bitstream given in the lab file and report the CRC. Intel Confidential 168 .Lab 5: CRC (cont) {BACKUP} Implement the CRC algorithm shown in the previous foil. The operators << (left shift) and ^ (xor) will be needed.

but remove the constraint from consideration of the constraint solver Use the same implication operator.x > 10) -> (y < 100 && y > a.Constraint Guards {BACKUP} Guards prevent the application of constraints.x) Intel Confidential 169 . similar to implication. just using state variables (!global_reset_state && cmd) -> (cmd_type != IDLE) Can even test obj pointers for null (a != null && a.

std::randomize() {BACKUP} Procedural invocation of constraint solver Any variables can be the random variables “with” block for constraints Normal .randomize() cannot include variables outside scope of class Intel Confidential 170 .

Disabling rand/constraints {BACKUP} rand_mode – method to toggle the “rand” attribute off on a class variable constraint_mode – method to toggle the application of a named constraint Intel Confidential 171 .

Random Stability {BACKUP} SV has thread random stability Intel Confidential 172 .

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