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# Lecture 14

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Logistics
s s s

## Door combination lock

s s s s s s s s

Midterm 1: Average 90/100. Well done! Midterm solutions online HW5 due date delayed until this Friday Finished combinational logic Introduction to sequential logic and systems Memory storage elements
Latches Flip-flops

Last lecture
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Today
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Enter three numbers in sequence and the door opens As each number is entered, press new If there is an error the lock must be reset After the door opens the lock must be reset Inputs: Sequence of numbers, reset, new Outputs: Door open/close Memory: Must remember the combination Memory: Must remember which state we are in

State Diagrams

CSE370, Lecture 14

CSE370, Lecture 14

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x

Feedback

s

s

## As long as power is applied

"1" "0" "stored bit"

In order to do fun problems like the door combination lock, we must know the building blocks (like how you had to learn AND and OR before you could do functional things). Be patient --- once you know these elements, you can build a lot of meaningful functions For combinational logic, truth table was an invaluable visualization tool for a function. For sequential logic, state diagram serves as a way to visualize a function.

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State diagrams
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## Temporarily break the feedback path

"data"
CSE370, Lecture 14 CSE370, Lecture 14

The SR latch
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SR latch behavior
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## Truth table and timing

R Q Q' S 0 0 1 1 R 0 1 0 1 Q hold 0 1 disallow

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Reset Set

R S

Q Q

S 0 0 1 1

R 0 1 0 1

## Q hold 0 1 disallow R S Q Q'

S Reset Hold

Set

Reset Set

100

Race

CSE370, Lecture 14

CSE370, Lecture 14

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State diagrams
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s s

## How do we characterize logic circuits?

s s

Combinational circuits: Truth tables Sequential circuits: State diagrams States Unique circuit configurations Transitions Changes in state caused by inputs

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## Second draw the transitions between states

s

R S

Q Q'

CSE370, Lecture 14

CSE370, Lecture 14

Example: SR latch
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## Observed SR latch behavior

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SR=10 Q Q' 0 1 SR=01 SR=10 SR=01 SR=11 Q Q' 0 0 Q Q' 1 0 SR=00 SR=10

Begin by drawing the states s States Unique circuit configurations s Possible values for feedback (Q, Q') S 0 0 1 1 R R 0 1 0 1 Q hold 0 1 disallow SR=00 SR=01

## The 11 state is transitory

s s s

Either R or S gets ahead Latch settles to 01 or 10 state ambiguously Race condition non-deterministic transition
Disallow (R,S) = (1,1)

Q Q'

## SR=11 SR=00 SR=01

CSE370, Lecture 14

## possible oscillation between states 00 and 11 (when SR=00)

Q Q' 1 1
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## The D latch: store it and look it up

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The D flip-flop
Q Q CLK Output Output

## Output depends on clock

s s

Clock high: Input passes to output Clock low: Latch holds its output

Input

## Input sampled at clock edge

s s

Rising edge: Input passes to output Otherwise: Flip-flop holds its output

Input

Q Q CLK

Output Output

CLK D Qlatch

## Flip-flops can be rising-edge triggered or falling-edge triggered

CLK D Qff

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CSE370, Lecture 14

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The D flip-flop
Input D Q Q CLK Output Output

The D latch
Input D Q Q CLK Output Output

CLK D Qff
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CLK D Qlatch

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## How do we make a D flip flop?

Falling edge-triggered flip-flop
If Clk=1 then X=Y=0 and SR-latch block holds previous values of Q,Q also Z=D and W=Z=D Q When Clk0 then Y (set for SR-latch block) becomes Z=D Clk and X (reset for SR-latch block) becomes W=D so Q becomes D This is stable until D or the Clk switches D While Clk=0, if D switches then Z becomes 0 and X and W hold their previous values and Y=X=D as before.

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W X Clk Y D Z

W X Q Q Y Z

## You can do this at home:

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## Terminology & notation

Rising-edge triggered D flip-flop
Input D Q Q CLK Output Output CLK

## Latches versus flip-flops

Positive D latch
Input D Q Q Output Output CLK D Q Q D Q Q

## Falling-edge triggered D flip-flop

Input D Q Q CLK
CSE370, Lecture 14

Negative D latch
Input D Q Q CLK
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Output Output

Output Output

CLK behavior is the same unless input changes while the clock is high

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The master-slave D
Master D latch
X Input D Q D Q Output

T flip-flop
x Slave D latch x

s s

## CLK Input Q Input(t) 0 0 1 1 Q(t) 0 1 0 1 Q(t + t) 0 1 1 0

T Q >

CLK

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x x

## Clear and Preset set flip-flop to a known state

s

Used at startup, reset Synchronous: Q=0 when next clock edge arrives Asynchronous: Q=0 when reset is asserted
Doesn't wait for clock Quick but dangerous

s s

## Preset or Set the state to logic 1

s s

Synchronous: Q=1 when next clock edge arrives Asynchronous: Q=1 when reset is asserted
Doesn't wait for clock Quick but dangerous

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