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Un de r t h e Gu idan c e of Dr. Man is h a Pat t an aik

Designed by - Basanta Bhowmik


Jayveer Singh Bhadauriya

Co n t e n t s :
S ch em a t ic d es ign ..0 3 -1 9 Pr e la you t s im u la t ion ..2 0 -2 6 La you t d es ign .2 7 -5 0 Des ign r u le ch eck (DRC).5 1 -5 3 E xt r a ct ion 5 4 -5 6 La you t Vs s ch em a t ic(LVS ).5 7 -6 2 Pos t la you t s im u la t ion 6 3 -6 5 Gen er a t ion of GDS II file(MAS K)..6 6 -7 2 Ap p en d ix .7 3 -7 6 MOS IS Des ign r u le .7 3 E xt r a ct ed file/ La you t Net lis t 7 4 GDS II E xp or t file.....................7 5 GDS II Im p or t file..7 6

S c h e m at ic de s ign o f In v e rt e r
What is schematic Design: There are many phases or progressions of a design. A common term you will hear when working with a Designer is Schematic Design. This phase is early in the design process. Schematic Design establishes the general scope, conceptual ideas, the scale and relationship of the various program elements. The primary objective of schematic design is to arrive at a clearly defined feasible concept based on the most promising design solutions.

Op en in g S -ed it p la t for m : Fir s t of a ll d ou b le click on t h e icon of s -ed it on t h e d es k t op or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> S-Edit v 13.0

A new window will open:

Go to >>file >> New >> New Design Select New Design

One dialog box will appear Design Name : Give the name your design as you wish Create a Folder : Give the path where you want to save the S-Edit Files. Then Click on OK

Now to add libraries in your work click on Add , left on the library window. Give the path where Libraries are stored . As for example C:\Documents and Settings\Bhowmik.IIIT-3AC288AD0A\My Documents\Tanner EDA\Tanner Tools v13.0\Libraries\All\All.tanner

Now to create new cell Go to cell menu >> New view -Select New view

The new cell will appear like below: Design = your design name Cell = cell no. ( cell no you can change but your design name inv will be same for different cell. Design name should be changed only when you are going to design another circuit) View type = schematic Interface name = by default View name = by default Then press OK.

Then a cell will be appeared where we can draw the schematic of any circuit. In the black window you have seen some white bubble arranged in specific order. This is called grid. You can change grid distance by clicking on black screen and then scroll the mouse. If you want your screen big enough for design space , then you can close the Find & command window. You can again bring these window from view menu bar.

To make any circuit schematic . for example inverter a) Go to >>libraries & click on device then all device will be open.

b) Select any device e.g. :- NMOS Device, then click on , instance (then the dailog box instance cell will appear.)

In instance cell You can change the values of various device parameters according to your requirements. Go to properties >> change the parameter values as your requirement. Now before clicking DONE you have to DRAG the selected device into the cell and drop it where you want it to FIX . Then click DONE or press ESC.

Similarly you can DRAG & DROP any device into the cell for draw your schematic circuit. For inverter we need another Pmos.

Now connect two device with wire. Go to tool bar and select wire.

Similarly to give input & output port in the circuit , select input port that shown by red ellipse.

Now you can give Port name as you wish in the dailog box. Then click OK

Similarly give Output Port name. NOTE : you can rotate the port (short cut key R).

Now, after completed these steps, you should give the supply (VDD) & ground (GND). For that Go to liberaries >> MISC >>Select VDD or GND

Now you have to create a source of VDD. For that go to libraries >>spice_element >> and then select voltage source of type DC . you can give any value in vdd .lets take vdd =5v.

By doing all the above steps you have completed schematic of Inverter

Pre lay o u t s im u lat io n

After schematic design you have to check whether your design match with the specification required or not . Thats why you need to simulate the design which is called Pr e la you t s im u la t ion . For s im u la t ion go t o>> t ools >> T-s p ice>> ok

A T-spice window will open. Then click on the bar shown by red ellipse

A T-spice command Tool dialog box will open as shown beow.

On the T-spice command you can see in the left hand side Analysis, Current source Files Initialization, Output Settings Table Voltage source Optimization

Lets start doing transient analysis of Inverter. Step 1 : You have to include TSMC 0.18 m Technology file . For that Go to >> T-spice command tool >> Files >> Include >> browse TSMC .18m files >> Insert command. C:\Documents and Settings\Bhowmik.IIIT-3AC288AD0A\Desktop\TSMC 0.18um\

File is included shown by highlight.

Step2 : Then to give Input T-spice command tool >> Voltage source >> select type of input you want to give(lets take bit) >> Insert command Step 3: Analysis T-spice command tool >> Analysis >> select type of analysis you want to give(lets take transient) >> Insert command step 4: Output T-spice command tool >> Output >> which output you want to see >> Insert Command

The total spice netlist will come like this.

Now save it . Then Run by clicking red ellipse shown on left above corner.

Output of Pre layout simulation of Inverter

Layout Design
What is Layout Design: A layout-design of an IC refers essentially to the 3-dimensional character of the elements and interconnections of an IC. There is a continuing need for the creation of new layoutdesigns which reduce the dimensions of existing integrated circuits and simultaneously increase their functions.

Pro c e du re o f Lay o u t De s ign in 0 .1 8 m CMOS Te c h n o lo gy (MOS IS >> Mam in 0 8 ) Op en in g L-ed it p la t for m : Fir s t of a ll d ou b le click on t h e icon of L-ed it on t h e d es k t op or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> L-Edit v 13.0

A window will come like below.

We will start the layout of Inverter with


w= 1.5 m L =2.75 m w= 1.5 m L= 3.50 m

For inverter layout Go to file>> new.>> select A dialog box will come as shown in fig

Select layout and then press ok.

A new layout window will open

Carefully observe the Red ellipse which will be frequently used for your Design.

Before starting layout design you have to set the Technology you want to used. In TSMC .18 m Technology, available Technology are Charterd China_hj Generic0_25 m Mosis Orbit So to set the Technology Go to >> File >> Replace setup and then select

A dialog box will come. Click on browse >> Tanner EDA >> Tanner Tools v13.0 >>L-edit and LVS >> TECH >> Mosis >> mamin08 or mamin12 or or >> press ok

After pressing ok ,A small dialog box will come and it tells you ,Technology are going to be changes. In that stage press ok. Lets take in the above set up you set Mosis ->Mamin08 Technology. That means you have to follow Mosis design rule in your entire design. Mosis design rule are given in appendix.

Now lets recheck your technology set up. For that Go to >> set up >> Design >> then select

In the Set up design layout2 dialog box you have seen there are many technology can choose any one of them for your design. I have choosen Lambda rule for convenience. Also for Technology to micron mapping I have taken 1 lambda=0.5 micron . You can choose your own for better understandig and drawing the design.

In the same way select grid For design convenience and properly maintain the DRC , I have taken Major diplayed grid=10 lambda Minor diplayed grid=1 lambda (You put according to your calculation) Like that many other parameter you can change thats depends upto you.

Atlast press ok . Now you properly create the environment for design.

You have two option for any Design .Lets take example of Inverter First: For inverter design first of all you have to create a PMOS and a NMOS in the same window. Or Second:You can bring a PMOS and NMOS from the Library ,which is already available. For that Go to Cell >> Instance >> browse the Technology what you are using (e.g mamin08) >> press ok >> a series of devices which are available in the library will come >> seect EXT_NMOS or EXT_PMOS >> press ok . The device will come in cell window. But In the library some standard devices available which are not enough for your requirement all the time .This is a bad practice.Thats why you need a good practice to Design all the way from start to end of the Design. We will follow first procedure. So first of all design a PMOS. For PMOS you need a N type substrate ,source and drain will be P-type and pollysilicon Gate. BY default The cell window is P-type. So for design Pmos you need N-substrate that means Select N-well >> select switch to draging box (left upper corner of the window) >> draw

Then Select P-select >> select switch to draging box (left upper corner of the window) >> draw

Now Select Active >> select switch to draging box (left upper corner of the window) >> draw

Now Select Active >> select switch to draging box (left upper corner of the window) >> draw

In the same way draw Nmos .Here not required p-well because the window is already p-type. So the procedure is first draw a n-select then then draw the active area and then polysilicon gate.

After designing Nmos and Pmos you have to connect them . e.g PMOS source and substrate will be connected to VDD and Nmos source and substrate will be connected to Gnd. Pmos ,Nmos drain are connected to output and both gate are connected to Input. For source ,drain ,Vdd and Gnd you have to take Metal 1 layer. To connect Pmos substrare to Vdd you need N-select and Metal -1 layer

To connect Nmos substrare to Gnd you need P-select and Metal -1 layer

Now connect source and vdd of pMOS by Metal-1 layer

Put active contact of size 2m2 m

Now connect nMOS drain to pMOS drain and nMOS source to Gnd by metal-1 layer.shown by red ellipse.

Put active contact .

Now Connect both Gate as shown below,To make contact on Polysilicon, you need metal-1 (3m3 m)layer and Poly contact of size (2m2 m)

To give name to input output port, click to Switch to drawing ports as shown below:

After clicking on the Switch to drawing ports, click on that part of the layout where you want to give name of the port. As for example to give name Vdd you have to select the Metal-1 layer shown in figure.

After giving name to each port, your layout look like as shown below. Then save your design.


Design Rule Check (DRC) is the area of Electronic Design Automation (EDA) that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules. Design rule checking is a major step during Physical verification signoff on the design. Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of a mask set. Design rules are specific to a particular semiconductor manufacturing process.

Go to >>setup DRC >> select One dialog box will come as shown below, check out DRC Standard Rule Set then press OK.

Now run DRC shown by red ellipse.

After running DRC, if there is no error that means your design satisfies Design rule check.

To verify the functionality and timing of this inverter, you need to extract the spice netlist from the layout then simulate it. Unfortunately, the netlisting is not working at that moment, but we can still generate the extracted view from which a netlist can be generated (once we fix the installation). The extracted view also allows you to run LVS (Layout vs Schematic). This tool (which is also not working at the moment, probably for the same reason the netlisting is broken) allows you to compare a schematic and an extracted physical layout to verify that they are equivalent ( i.e. signals are connected the same way)

To extract, click on setup extract, then a setup extract dialog box will open, check extract standard rule set if it is not checked and then click on pencil icon as shown below.

After clicking on pencil icon, Setup Extract Standard Rule Set window will open, in that window give path of Extract Definition File. Browse >> My document >> Tanner EDA >> Tanner Tools v13.0 >> L edit and LVS >> Tech >> Mosis >> mamin08. Note: (check General -> open output file after extracting and all others are optional . Output-> Names,Write verbose spice statements,write .End statement .include file must be included in spice included Statement. All others are optional. Subcircuit-> optional. Then Press OK.

If you not give proper path of Extract definition file then a dialog box will come showing you I/O Error cannot open file.

To extract click on EXT toolbar shown by highlighting. Then warning will come like below.At this stage click on Ignore all.

A extracted file or netlist contaninig device details like connections,aspect ratio ,drain area,source area, perimeter,and juntion capacitances will come . Netlist or Extracted file of the inverter shown in appendix.

Lay o u t Vs s c h e m at ic (LVS )
The Layout Versus Schematic (LVS) is the class of EDA verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design. LVS checking software recognizes the drawn shapes of the layout that represent the electrical Components of the circuit, as well as the connections between them. This netlist is compared by the "LVS" software against a similar schematic or circuit diagram's netlist. LVS Checking involves : 1. Extraction: The software program takes a database file containing all the layers drawn to represent the circuit during layout. It then runs the database through many area based logic operations. Area based logical operations use polygon areas as inputs and generate output polygon areas from these operations. These operations are used to define the device recognition layers, the terminals of these devices, the wiring conductors and via structures, and the locations of pins (also known as hierarchical connection points). 2. Reduction: In the time of reduction the software combines the extracted components into series and parallel combinations if possible and generates a netlist representation of the layout database. A similar reduction is performed on the "source" Schematic netlist. 3. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic. If the two netlists match, then the circuit passes the LVS check and a message will come the circuit are equal. At this point it is said to be "LVS clean .

Op en in g LVS p la t for m : Fir s t of a ll d ou b le click on t h e icon of LVS V1 3 .0 on t h e d es k t op or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> LVS v 13.0

A new window will come as shown below.

Then go to >>file >> new >> LVS setup >> ok

Select input. In the input you have to import Layout netlist and Schematic netlist. Note: (dont forget to remove .include .md file from both netlist ). Select output, device parameter, merge device, paracitics,options,performance , the are basically optional. After checking click on run verification(shown by red ellipse)

A dialog box verification will come. In final report a message will shows The circuits are equal. That means your LVS checking is complete and your layout design perfectly same as schematic of your design.

Po s t lay o u t s im u lat io n
The parasitic capacitances extracted according to how your layout is designed might be critical in affecting the actual performance of your design. In order to get an idea of how the design would work from your layout, you should perform a post-layout simulation from the extracted view. The procedure is identical to that for simulating from the schematic view. The electrical performance of a full-custom design can be best analyzed by performing a postlayout simulation on the extracted circuit net-list. At this point, the designer should have a complete mask layout of the intended circuit/system, and should have passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics (such as parasitic capacitances and resistances), and any glitches that may occur due to signal delay mismatches. If the results of post-layout simulation are not satisfactory, you should modify some of the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics. This may require multiple iterations on the design, until the post-layout simulation results satisfy the original design requirements.

For post layout simulation Open layout netlist >> rest of the process is same as prelayout simulation.

Output of post layout simulation :

Ge n e rat io n o f GDS II file (MAS K)

GDS II stream format, common acronym GDSII, is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork between different tools, or creating photomasks. GDSII is like Gerber for PCBs. It is a format that ASIC Foundries accept for the manufacture of ASICs/VLSIs (mainly standard cells). Alike Gerber, GDSII contains Masks layers (as many as 24 to 30), including Metal top layer(s). The Term RTL-to-GDSII refers to a design methodology where already in the RTL stage, route problems, critical placements, Signal Integrity, Crosstalk, and other DRCs are taken under account to shorten up the "Timing Closure" cycle process. This is especially true for the new nanometer technologies (below 0.13um)

To generate GDS II file go to >> File >> Export Mask Data >> GDSII >> ok

A Export GDSII dialog box will come . click on the Export button. Shown by red ellipse If you want log file to save ,then first click on it and give a new name .This is basically optional.

After Exporting ,a GDSII Export file will come . It will tell you the details of Exporting. Last of the report something written . Like below. Summary: Export Successful. Elapsed Time: 0.00 seconds

Then close the layout cell(not layout window) and import GDSII (MASK) file. For that go to >> File >> Import Mask Data >> GDSII >>ok

Click on the Import.

Press ok

After Importing you will get MASK of your Design. As for example in the below shows a mask of Inverter

Appe n dix

MOS IS De s ign ru le
Rule number RI R2 R3 R4 R5 R6 R7 Description Active area rules Minimum active area width Minimum active area spacing Polysilicon rules Minimum poly width Minimum poly spacing Minimum gate extension of poly over active Minimum poly-active edge spacing (poly outside active area) Minimum poly-active edge spacing (poly inside active area) Metal rules Minimum metal width Minimum metal spacing Contact rules Poly contact size Minimum poly contact spacing Minimum poly contact to poly edge spacing Minimum poly contact to metal edge spacing Minimum poly contact to active edge spacing Active contact size Minimum active contact spacing (on the same active region) Minimum active contact to active edge spacing Minimum active contact to metal edge spacing Minimum active contact to poly edge spacing Minimum active contact spacing (on different active regions) Rule 3 3 2 2 2 1 3

R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20

3 3 2 2 1 1 3 2 2 1 1 3 6

Extracted file/Netlist of Layout

* Circuit Extracted by Tanner Research's L-Edit Version 13.01 / Extract Version 13.01 ; * TDB File: E:\layout\layout\Layout2.tdb * Cell: Cell0 Version 1.20 * Extract Definition File: C:\Documents and Settings\Bhowmik.IIIT-3AC288AD0A\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit and LVS\Tech\Mosis\mamin08.ext * Extract Date and Time: 08/28/2011 - 19:26 .include * Warning: Layers with Unassigned AREA Capacitance. * <PMOS Capacitor> * <NMOS Capacitor> * <PCAP Capacitor> * Warning: Layers with Unassigned FRINGE Capacitance. * <PMOS Capacitor> * <Pad Comment> * <NMOS Capacitor> * <PCAP Capacitor>

M1 Out In Gnd Gnd NMOS L=1.5u W=2.75u AD=12.375p PD=14.5u AS=11.6875p PS=14u $ (25 7 28 12.5) M2 Out In Vdd Vdd PMOS L=1.5u W=3.5u AD=14.875p PD=15.5u AS=15.75p PS=16u $ (25 27.5 28 34.5) * Total Nodes: 4 * Total Elements: 2 * Total Number of Shorted Elements not written to the SPICE file: 0 * Output Generation Elapsed Time: 0.000 sec * Total Extract Elapsed Time: 10.484 sec .END

GDSII Export File

GDSII Export... TDB File: E:\layout\layout\Layout2.tdb GDSII File: E:\layout\layout\Layout2.gds Option Settings: Do not export hidden objects: ON Overwrite data type on export: ON Calculate MOSIS checksum: OFF Check for self-intersecting polygons and wires: OFF Write XrefCells as links: OFF Preserve case of cell names: ON Restrict cell names to 32 characters. All cells are being exported Use custom GDSII units: 1 database unit = 0.0005 microns, 1 database unit = 0.001 user units. Fracture polygons: OFF Manufacturing grid for circle and curve approximation: 0.001 Lambda All ports with port boxes will be converted to point ports Checking XrefCell links ... Checking GDSII Numbers ... Checking for Hidden Layers and Objects ... Writing actual GDSII data ... Completed writing actual GDSII data ... Summary: Export Successful. Elapsed Time: 0.00 seconds

GDSII Import File

GDSII Import... GDSII File: E:\layout\layout\Layout2.gds SetupFile: C:\DOCUME~1\BHOWMI~1.III\LOCALS~1\Temp\tdb6C.tmp Option Settings: Treat unique GDS data types on a layer as different layers: ON Using original GDSII database resolution: 0.0005 microns Warning #33: Found unknown GDSII layer 47 (Action: Created a new layer GDS_47_DT_00 for GDSII number 47 and Data type 0) Warning #33: Found unknown GDSII layer 46 (Action: Created a new layer GDS_46_DT_00 for GDSII number 46 and Data type 0) Warning #33: Found unknown GDSII layer 43 (Action: Created a new layer GDS_43_DT_00 for GDSII number 43 and Data type 0) Warning #33: Found unknown GDSII layer 49 (Action: Created a new layer GDS_49_DT_00 for GDSII number 49 and Data type 0) Warning #33: Found unknown GDSII layer 42 (Action: Created a new layer GDS_42_DT_00 for GDSII number 42 and Data type 0) Warning #33: Found unknown GDSII layer 45 (Action: Created a new layer GDS_45_DT_00 for GDSII number 45 and Data type 0) Warning #33: Found unknown GDSII layer 44 (Action: Created a new layer GDS_44_DT_00 for GDSII number 44 and Data type 0) Warning #33: Found unknown GDSII layer 48 (Action: Created a new layer GDS_48_DT_00 for GDSII number 48 and Data type 0) Checking for Cell Name Conflicts... Resolving External Cell References... Summary: E:\layout\layout\Layout2.gds - 0 error(s), 8 warning(s) Import Successful Elapsed Time: 1.08 seconds