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Illustrate the structure of a MOS PNP transistor on a p-type substrate [3 marks]

Polysilicon SiO2 Source Gate Drain

p+ n - well


p - substrate

One mark should be deducted if the n-type well is not shown. 2. List the main steps in fabricating a PNP transistor as described in (1) [5 marks] Expect something similar to the following N-well formed by low-dose phosphorus implant driven-in by placing the wafer in a hightemperature furnace Oxide re-grown and active areas formed by etching away oxide in areas where transistors are to be made Polysilicon deposited where transistor gates and poly interconnections are required P-type doping of P-channel transistor sources and drains Oxide re-grown and etched so metal contacts can be diffused onto active areas and etched where not needed 3. If a MOS transistor is doubled in size, maintaining the same aspect ratio, how will this affect the switching time-constant? Explain why [3 marks] Gate capacitance will increase. C0 is proportional to WL/tox; if tox increases too, overall C0 would double. Channel resistance is proportional to L/Wtdiff. This would go down by x, but the change in the channel doping keeps it constant. Hence as C is increases and R stays constant, the switching speed is decreased by factor x. 4. Briefly describe the CMOS latchup problem and identify one way it can be avoided [2 marks] The p+ region of the p-transistor, the n-well and the p- substrate form a parasitic pnp transistor T1. The nwell, the p- substrate and the n+ source of the n-transistor forms another parasitic npn transistor T2. This parasitic structure forms pnpn device, which is a thyristor.

P+ T1




T2 p-substrate


(diagram is not required)

If Rw and/or Rs are not 0, and for some reason (power-up, current spike etc), T1 or T2 are forced to conduct, VDD will be shorted to Gnd through the small resistances and the transistors may fail. Once the circuit is 'fired', both transistors will remain conducting due to the voltage drop across Rw and Rs. The only way to get out of this mode is to turn the power off. This condition is known as latch-up and normally results in destruction of the chip.

To avoid latch-up, substrate-taps (tied to Gnd) and well-taps (tied to VDD) are inserted as frequently as possible. This has the effect of shorting out Rw and Rs. Other mechanisms such as Silicon on Insulator and Trench Isolation exist. 5. Draw a stick diagram for a CMOS inverter [3 marks]
VDD Need to include a Key Metal In VSS Out Poly pDiff nDiff C ontact Wells not usually shown Diff layers underneath Poly and Metal Poly underneath Metal

6. Define Logical Effort. What is the Logical Effort of a 3-input Nor gate? [4 marks] Logical Effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. To obtain the same pulldown drive as an inverter, pulldown transistors one unit wide are sufficient. To obtain the same pullup drive, transistors six units wide are required, since three of them in series must be equivalent to one transistor two units wide in the inverter.
VDD 2 Y A 1 VSS CIN =3 LE =1 (by definition) 1 C =7 IN LE =7/3 1 1 VSS C 6 Y

3NOR Gate
A B 6 6