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Architectures for Low Power Ultra-Wideband Radio Receivers in the 3.1-5GHz Band for Data Rates < 10Mbps
Marian Verhelst*, Wim Vereecken**, Michiel Steyaert and Wim Dehaene
Katholieke Universiteit Leuven Dept. Elektrotechniek, afd. ESAT-MICAS Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium
*M. Verhelst is Research Assistant of the Fund for Scientific Research - Flanders (Belgium)(FWO-Vlaanderen) **W. Vereecken is Research Assistant of the IWT Belgium

This paper compares different receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain requirements the partially analog receiver consumes 7 times less power per received bit than the fully digital one. Categories and Subject Descriptors: B.4.1 [INPUT/OUTPUT AND DATA COMMUNICATIONS]: Data Communications Devices – Receivers General Terms: Performance, Design. Keywords: Ultra-Wideband, Receiver, Architectures.

tems). In the past years a lot of research has been done on transceiver architectures in the lower frequency band. Almost always a fully digital architecture, which implies flexibility, scalability and (in this case) low power, was suggested for these frequencies [9] [15]. Only recently research started exploring the 3.1-10.6GHz band. The question is however whether the fully digital architecture, which seemed optimal for the lower frequency band, can be reused in the higher frequency band? The following paragraphs will prove that, unlike in the 0-960MHz band [9], it is not necessarily true that: “the more the operations are carried out in the digital domain, the less power will be consumed”. To be able to make a fair comparison between the different architectures, some parameters have to be fixed. In the following of this paper, we will assume a pulse rate of 100Mpulses/s, an ideal channel, components with ideal noise figures, 1 user and only AWG (additive white Gaussian) noise. These are first order parameters that allow us to do a quick, but reliable comparison between different architectures. The pulse rate of 100Mpulses/s reveals that this paper does not aim high speed UWB receivers. The focus is on low power and flexibility and data rates up to no more than 10Mbit/s are targeted. Because of the high interference by WLAN in the 5-6GHz band, the authors choose to use only the 3.1-5GHz frequency band. Figure 4 (left) shows the used pulse form in time and frequency domain. It is modeled by a raised cosine with roll-off factor α = 1. We will not utilize pulse position modulation (PPM) to encode the binary information onto the pulses. Instead pulse amplitude modulation (PAM) is used: The waveform plotted in figure 4 (left) represents a logical 1, the negative of this waveform represents a logical 0. A pseudo random sequence will be used for channelization and BER improvement purposes [14].



Wireless communication has never been so popular as it is now. The frequency spectrum is used intensively and bandwidth available for new wireless communication techniques becomes very scarce. The ultra-wideband (UWB) impulse radio technology [16], recently approved by the FCC [7], addresses this problem. This technology is based on transmitting ultrashort (< 1ns) pulses. The energy of these pulses is spread out over a large bandwidth (typically a few GHz) and can therefore be transmitted in already allocated frequency bands, below the noise floor of the other users and without disturbing them. UWB has many advantages compared to other, narrowband, communication techniques, such as robustness against jamming and multipath fading, low probability of detection and high user-capacity. The FCC allows the deployment of UWB in two separate frequency bands: the 0-960MHz band (for imaging applications) and the 3.1-10.6GHz (i.o. for communication sys-

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2. FULLY DIGITAL IMPULSE RADIO RECEIVER 2.1 Architecture and working principle
Figure 1 shows the main components of the fully digital architecture. This architecture resembles very much the baseband architecture, described in [9], with some adjustments to be able to use it in the 3.1-5GHz band.


3 MF and 3 PN correlators are always running in parallel. this component will still weigh heavily on the power budget of the receiver.1-5GHz band is it’s power consumption. Channelized ADC: 10GS/s ADCs are very hard to make and consume very much power. The graphs of figure 2 confirm these numbers. 1. Figure 2 shows the (in Simulink) simulated bit error rate E (BER) at the output of this receiver vs. 10 0 Figure 1: Architecture of the fully digital receiver. will increase the SNR by a factor Npn (cfr. As a result.g. the digital logic close to the ADC. a matched filter (MF) bank will correlate the data with the (5 bit) pulse form coefficients. the matched filter correlator bank. Secondly the PN correlation combines Npn pulses to recover one bit. With this information. The simulation uses 2-PAM to modulate the data on the pulses and a PN sequence length Npn = 15. This matched filter transforms every group of 100 input samples (one pulse period) into one correlation value. Only AWG-noise is considered. the result of the simulation without an ADC in front of the receiver follows this theoretical bound per- 3. Besides this. 2. This results in an extra processing gain by a factor Npn .2 Drawbacks of the fully digital architecture at 3. N0 √ = Q( 2SNRout Rout Wout ). and although it’s resolution can be very low (e. is filtered and afterwards sampled at the Nyquist rate. Paragraph 5 will treat the power consumption of this architecture more thoroughly. As a result the speed degrades by a factor 100 and the matched filter outputs a 100MHz (pulse rate) signal. The speed can be lowered at the expense of more parallelism.g. p (2) = Q( 2SNRin Npn Tpulse Win ).25dB for a 2 bit ADC and 2. Because UWB pulses are sent with very low power. Next paragraph will introduce some important adjustments to this architecture to get rid of the drawbacks discussed above. which implies very fast clocking registers. it is possible to compute the output Eb /N0 and from this the theoretical 2-PAM under bound for this architecture: r Eb BER = Q( 2 in ).3 Conclusions At a first glance this architecture does not seem to be ideal at all to be used in the 3. are detected by early/latetracking. The correlation operation itself has to be executed at 10GHz (sample rate) when the correlation is done fully serial. analytical computations determined the loss to be 1. simulated 5000 bits 2.3dB for a 1 bit ADC. Nevertheless this is a second source of huge power consumption. will also have to work at a very high frequency: Data enters this block at 10GHz. Figure 2 shows this bound. Theoretical analysis confirms these simulation results. stored locally. Npn = 15. In this way every pulse is replaced by a sequence of Npn pulses. Processing gain is achieved through two mechanisms: matched filtering and descrambling by PN correlation. in the receiver input and out the receiver output. due to clock offset. In the digital domain. Therefore an extra scrambling of the pulses with a pseudo noise (PN) sequence of length Npn is done at the transmitter side. From these. The ADC has to work at the Nyquist frequency. DSSS techniques [14]). This allows us to compare our choice of architecture with the fully digital architecture and see whether the changes result in an improvement. Placing an ADC in front of the receiver will add quantization noise. one solution will be chosen and worked out in more detail. Timing errors. with Tpulse the pulse repetition interval. ALTERNATIVE ARCHITECTURES This section will shortly introduce four possible alternatives for the fully digital architecture and select the most promising alternative among them. during normal operation. 10GHz. This power consumption will be dominated by the ADC and the matched filtering block in the digital domain. Under the assumption of a Gaussian input signal. (1) 10 −2 10 −3 10 −4 1 bit ADC 2 bit ADC no quantization theoretical 2−PAM: Q(sqrt(2Eb/N0)) −35 −30 −25 −20 −15 Epulse/N0 in −10 −5 Figure 2: Performance of the fully digital receiver with 2-PAM. A way to avoid 281 . The matched filter correlation takes advantage of the low duty cycle of the signal and provides a gain factor [14] 2 ∗ Tpulse ∗ Win = 2 ∗ 10e − 9 ∗ 5e9 = 100 = 20dB. As expected. the numbers above the correlator blocks are the input data rates of these blocks BER out 10 −1 During normal operation (data reception) data enters the receiver through the broadband antenna. the SNR at the outcome of these MF correlators is too low and needs further improvement. half of a sample) shifted versions of the pulse template. 1 bit). 10GHz. input pulse for N0 different ADCs at the entrance of the digital part.1-5GHz The major drawback when using this architecture in the 3. Descrambling these pulses in the receiver by correlating them with the same PN sequence.@ 10GHz low pass filter 0−5GHz ADC @10GHz MF correlator bank @100MHz PN correlator bank data recovery peak detector CONTROL TIMING fectly. This is done by correlating the data with slightly (e.1-5GHz band for UWB communication.

but with a windowed sine wave. but at first glance the decrease in speed and power of the ADC and MF block does not seem to compensate the extra power for the QVCO. [2]) abandons the down conversion and does only a bandpass filtering form 3 to 5GHz and a subsampling at 4GHz immediately afterwards. Besides this. Further research on this topic is still necessary. in paragraph 5. Down conversion before ADC: [6] suggests to do a quadrature down conversion in the analog domain before sampling the I and Q branch at Nyquist rate (Figure 3(b)). Next paragraphs reveal whether this architecture really offers a feasible solution. PARTIALLY ANALOG IMPULSE RADIO RECEIVER 4. both techniques suffer from large problems. with each ADC operating at a fraction of the effective sampling frequency. the two architectures of figure 1 and figure 3(d) will be compared against each other. These are parallel ADC architectures. while the ADC speed only degrades from 10GHz to 4GHz. the extra mixer and the extra ADC. Figure 4 compares the pulse template to the new analog matching form. a rather sharp analog bandpass filter is needed. This fourth adjustment (figure 3(d)) will try to move the MF correlation operation to the analog domain. Since the data rate after the MF operation is equal to the pulse rate.1-5GHz band to 0. @10GHz/M @10GHz MF correlator bank @100MHz PN correlator bank data recovery low pass filter band pass filter f2 band pass filter fM ADC peak detector . However. the complexity of the digital receiver part has grown intensively to be able deal with this subsampling (e. a totally different approach will have to be used. 4. This reduces the specifications of the ADC a lot. Figure 3(a) shows the resulting architecture when employing frequency domain channelization.. followed by a windowed integration.1 Architecture and working principle Moving the MF operation to the analog domain seems a stupid action. In this case it means converting the 3. the windowed sine wave (with a window length W L and frequency equal to the center frequency of the pulse). This solution however requires a QVCO and an extra mixer and ADC.this is to use a channelized ADC [13]. This operation will repeat the frequency contents of the 3-5GHz band and hence convert it to baseband. with a Hilbert transform). ADC . Paragraph 4 will handle it thoroughly. While the ADC speed is only reduced a little bit. this sine wave resembles the pulse form very much. Move operations to analog domain: The previous adjustments all tried to lower the ADC speed. Channelization can be employed in the time or frequency domain. 3. The generation of a sine wave in the analog domain is very straightforward. Most of the solutions given above do not seem to solve the problem of the high speed ADC and matched filter block completely. But they do not seem to be able to lower this speed drastically.1-2GHz and then sample at 4GS/s. CONTROL TIMING ADC (a) Channelized ADC @4GHz filter ADC filter filter ADC @4GHz QVCO @3GHz MF correlator bank @4GHz @100MHz PN correlator bank data recovery peak detector CONTROL TIMING (b) Down conversion before ADC @ 4GHz band pass filter 3−5GHz ADC @4GHz @100MHz PN correlator bank data recovery MF correlator bank peak detector CONTROL TIMING (c) Subsampling ADC @100MHz windowed integrator ADC @100MHz PN correlator bank data recovery peak detector VCO @4GHz CONTROL TIMING (d) Move operations to analog domain Figure 3: Four alternative architectures. To reach this. In [11] it is suggested not to match with the pulse template itself. The last one (figure 3(d)) however looks very promising. the ADC sampling rate will only be 100MS/s. the numbers above the correlator blocks are the input data rates of these blocks 4. Subsampling ADC: A third solution (figure 3(c).. Further research will have to point out whether these problems can be solved. Channelization in time still requires ADCs which are able to handle the full bandwidth (5GHz). which causes difficulties in the design of the sample/hold circuit. 282 . Finally. Moreover when windowed.g. This ADC technique is the subject of ongoing research [12]. Channelization in frequency on the other hand needs several broadband mixers and filters with sharp roll-offs in the analog domain. Generating the pulse template in this domain surely is very hard. So the correlation with the pulse template is now substituted by a multiplication with a sine. a very accurate clock is necessary to accommodate the different channels next to each other. This is a reduction with a factor 100! Of course this architecture also introduces some new problems.. 2. without touching the digital domain. And what’s more..

Form this graph an optimal WL of 1. A very small window is good for rejecting noise.0. the digital domain executes the PN decorrelation and takes care of data recovery and clock offset tracking. Figure 3(d) shows the new architecture. This effect becomes less apparent when the SNR decreases or the ADC resolution increases. It will be (Gaussian) distributed around the positive and negative correlation value.5dB. all signal energy will be captured. 5000 bits simulated The matched filtering template is designed aiming at a minimal effect of noise while maximizing the signal throughput.1 −4 0 −0. Figure 6 shows the simulated bit error rate (BER) at the E output of this receiver vs.5 4. which also results in a bad SNR.0 an integrator collects all energy captured in the window. The simulation uses 2PAM to modulate the data on the pulses. is less than in the fully digital receiver.05 −0. equal to the matching template in the fully digital receiver (left) and the analog matching form (right) in time and frequency domain Figure 6: Performance of the partially analog receiver with 2-PAM.2ns can be derived. the SNR at the entrance of this ADC is already fairly high (approximately 20dB above the input SNR). Of course this also brought along some new problems. Clock offset is measured by early/late-tracking. input pulse for different ADCs N0 at the entrance of the digital part. So.5 −2 0 2 4 −9 time [sec] x 10 −4 −2 0 2 4 −9 time [sec] x 10 BER out 10 −2 10 ampl [dB] 10 ampl [dB] 10 0 −3 ~1/WL 10 −2 10 −2 10 −4 1 bit ADC 2 bit ADC no quantization theoretical 2−PAM: Q(sqrt(2Eb/N0)) −35 −30 −25 −20 −15 Epulse/N0 in −10 −5 2 4 6 freq [Hz] 8 x 10 9 2 4 6 freq [Hz] 8 x 10 9 Figure 4: Comparison of the pulse form. Like in the fully digital receiver. As a result.5 3. during normal operation (data reception) the data is first mixed with a sine wave. As a result. Figure 5 shows the simulated processing gain of the analog matched filter in function of the integrator window length. The input signal of the ADC will hence not be uniform or Gaussian with zero mean at all. Noise will of course trouble this.2 Drawbacks of the partially analog architecture Most of the major drawbacks of the fully digital architecture have vanished by the transfer of the MF operation to the analog domain.05 ampl ampl 0 0.8dB (see figure 5 for W L = 1ns) due to imperfect matched filtering with the sine template. substituting this template by another will inevitably lead to a worse processing gain.0 3.3dB (see paragraph 2. a window length of 1ns and a PN sequence length Npn = 15. With this window the loss in processing gain compared to the real matched filtering is only approximately 0. With a too large window on the other hand.0 1. where the quantization loss for the ’1 bit ADC’-curve is less than the theoretical 2. the input of the ADC. Since only one sample per pulse period is taken. To this purpose a second matched filter correlation is necessary. ideally is a large positive or negative correlation value and no value in between.1) and figure 6 is an extra loss of approximately 0. Npn = 15. the 2 bit and certainly the 1 bit quantizer will introduce less quantization noise and the receiver will perform better. Only AWGnoise is considered. the ADC speed can be reduced to 100MS/s.1). The outcome of the analog correlator. but because of the filtering in the analog domain. The major difference between the curves of figure 2 (paragraph 2.5 2.5 too much noise energy captured MF with sine template partially analog receiver perfect MF fully digital receiver 1. but also a lot of noise goes through. This can also be seen in figure 6. The most important one is the lower Figure 5: Processing gain of the analog matched filtering operation (with sine template) in function of the window length (WL) of the windowed integrator 283 . processing gain [dB] WL of analog integrator [ns] 4. but will also reject a major part of the signal energy. The ADC samples the outcome of the integrator before the integrator resets again to be ready for the next pulse. The quantization loss on the other hand.5 0 10 0 10 WL −1 −1 −0.0 2.1 0. The window length of the analog integrator is an important parameter in this. The result of this operation is windowed and finally 20 19 18 too little signal energy captured 17 16 15 14 0.

The power consumption of the digital part can in a first order estimation be presumed equal to the power consumption of a 100MHz DSP processor. For this value of M one matched filter correlator consumes 273mW. 100MS/s) can from [4] be estimated at 15mW.18µm process) consumes 140mW when running at this speed [1]. some other degrees of freedom arise. control and PN correlation operations can all be assumed to be executed on this DSP. has to be exploited to reach a minimal power consumption for the block. The ARM926EJS (0. Table 1 shows the necessary Npn . The partially analog receiver clearly outperforms the fully digital one for the chosen parameters: Epulse = −10dB. it is possible to compute the power consumption for different values of the parameter M. A one bit ADC includes a high speed buffer.. As a result. Based on [8] (high speed M/S-flipflop) and Here 1.8 1. We can reach this goal by a fully digital architecture or with the partially analog architecture.3 Conclusions Together with a better power consumption. which is unacceptable. the power consumption is very high due to the high clocking speed (10GHz) in several components. M. Table 2 summarizes the power consumption in the different parts of these receivers. The input is -10dB. fully parallel. M = 20 seems to be optimal. 4. This trade-off is not possible in the fully digital architecture. since the number of pulses per bit (Npn ) is different The table shows that the digital receiver consumes much more power than the partially analog one. The power consumption of the broadband mixers and broadband windowed integrators are simulated in-house. fully serial implementation. 2 or more bit ADCs are all possible.2 0 20 40 60 80 100 speed = 10GHz M 5bit exors M 12bit adder speed = 10GHz/M 12bit register speed = 10GHz/M . For example the integration window length can be increased to achieve a faster acquisition at the expense of a slightly worse performance. Based on [5] a power consumption of 290mW can be derived for the ADC (100mW for the buffer. 110mW for a 10GHz S/H and 80mW for the comparator). BER = 1e−5. For every extra finger. and this for a lower data rate. Also in this architecture the power consumption of the digital part can be represented by the power consumption of the ARM processor. They both reach the same BER for the same input Epulse /N0 . a 10GS/s sample-andhold circuit and a fast comparator.2 1 0. Spice simulations (for adders and exors). We do not need separate matched filter correlators anymore. 2 and more bits ADCs at this high speed exist ([3]. Next paragraph will compare both of them and explore which one is to be used in which circumstances. 5bit exor + + + 5.6 1. Figure 7(top) shows the architecture of this block. [5]) but consume several Watts. The degree of parallelism in the implementation.. The power consumption of such ADC (2 bit.flexibility and scalability. Taking into account that M has to divide 100. The power consumption of every option can now be estimated. In this partially analog receiver architecture it is e. For M = 1. not possible anymore to choose the form of the matching template and implementing a RAKEreceiver structure with multiple fingers becomes costly. M Figure 7: The architecture of the matched filter block in the fully digital receiver (top) and it’s power consumption in function of the implemented parallelism M (under) Partially analog architecture Fully digital architecture We will only consider this receiver with a 1 bit ADC in front. A VCO for this architecture can be taken from [10] and consumes 11mW. not only some digital blocks (as in the fully digital receiver). Since both architectures encounter different losses. The matched filtering can however not run on this platform. the power will also be high because of the multiple exors and adders working in parallel and the large input buffer.8 0. The result can be seen in figure 7(under). since this operation is executed in the analog domain. Epulse N0 Table 1: Necessary Npn to reach BER 1e−5 with the different architectures Architecture fully digital 1 bit ADC fully digital 2 bit ADC partially analog 1 bit ADC partially analog 2 bit ADC Npn 170 122 174 137 degree of parallellism. (M−1)−bit shift register 5bit 5bit exor exor pulse coeff register file 100*5 bits speed = 10GHz/M power consumption MFblock [Watt] 1..g. since this would require a too high processor speed and hence power consumption. .6 0.. But is this also true for N0 other values of these parameters? 284 . COMPARISON OF THE TWO RECEIVERS IN TERMS OF POWER EFFICIENCY Suppose a bit error rate of 1e−5 is targeted. but with a different data rate. The matched filtering operation will be a kind of digital front-end. the last line of the table reveals an almost 7 times lower power consumption per received data bit. For the comparison a 2 bit ADC will be used. this architecture realizes a somewhat different flexibility than the fully digital architecture.4 0. On the other hand. that transforms the high speed data to 100MHz baseband signals and so lowers the DSP input speed. The timing. but also some of the analog components and the ADCs have to be copied. they need a different Npn to be able to compensate them and reach the confined goals. For M = 100.4 1.

[16] M.g. Finally. Chen. 285 . while in the second one the matched filtering is carried out in the analog volume 2. 6. In IEEE International Conference on Communications 2003. In International Solid-State Circuits Conference 1998. ”A 4-Gsample/s. Low-Power. September 2002. The power consumption of both receivers is very insensible to a change in Npn and for both receivers data rate 1 Npn Epulse N0 (3) E (for a constant BER. required pulse Previous computations and conclusions rely on the numbers given in table 2. 39:1433–1434. February 14. ”18 GHz low-power CMOS static frequency divider”. May 2003. where the pulse is located. paper 18. February 1998. The partially analog receiver turned out to perform remarkably better in terms of power consumption per received bit.35µm CMOS VCO for 5GHz Wireless applications”. February 1998. PhD thesis. CONCLUSIONS This paper focuses on two very different UWB receiver architectures for impulse radio communication in the 3. Blazquez et al. ”A Channelized Digital Ultrawideband Receiver”. Thiede. some new flexibility parameters arose. pages 449–454. IEEE Communications Letters. Win and R. University of Southern California. volume 1. Other implementations or more detailed calculations can change these power figures. Deschans et al. 2-bit SiGe Digitizers for the ALMA Project. ”A Fully Integrated 2. Kinget. These are rough power estimations based on one possible implementation of the two receivers. IEEE CAS Workshop on Wireless Communications and Networking. the superiority of the partially analog to the fully digital receiver in terms of power consumption per received bit is so huge that our conclusion will not change by assuming smarter implementations or more detailed calculations. The fully digital receiver can e. Data Rate Power cons. Digital communications. pages 2884–2888.18µm CMOS”. Orlando. [3] D. Proakis. ”Comparisons of Analog and Digital Impulse Radio for Wireless Multiple-Access Communications”.7V 0. BWRC Retreat. [12] W. S. [2] M. First Report and Order. In International Solid-State Circuits Conference 2003. ”Design and Analysis of Ultra-Wide Bandwidth Impulse Radio Receiver”. [9] I. [7] FCC. In IEEE International Conference on Communications: Towards the Knowledge Millennium. Figure 8 shows the power consumption per received bit for E different pulse (left).berkeley. New York. Advantages and drawbacks of both architectures are discussed and they are compared against each other. Scholtz. resp. October 2003. and is switched off otherwise. Hence the power consumption of this block and of the matched filter correlator bank following Table 2: Power consumption of the most consuming components of the fully digital and partially analog receiver Component VCO mixers 2GHz integrators ADC MF correlators other digital logic Total power cons. Poulton et al. [14] J.Changing the input pulse will not result in a different conN0 clusion. power consumption/bit [W/bit] power consumption/bit [W/bit] 7 6 5 4 3 2 1 −15 −10 −5 0 x 10 −6 fully digital receiver partially analog receiver 5 4 3 2 1 x 10 −6 fully digital receiver partially analog receiver 7.) As a result. but on the other hand. it is important to mention that our calculations do not take into account flexibility. Paper II”. [15] M. Ultra-Wideband Transceiver Architecture for Low-Rate. [8] Z. In the first one almost all operations are executed in the digital domain. Our future research will concentrate on solving the problems caused by this decrease in flexibility and at the same time explore the new degrees of freedom. ”An Integrated. FA.1. ”A Subsampling Radio Architecture for 3-10 GHz UWB”. ”A 20GS/s 8b ADC with a 1MB Memory in 0. In IEEE Transactions on Wireless Communications. volume 4. 2(2):36–38. resp. Namgoong. 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