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Fax: 781/326-8703 © Analog Devices, Inc., 2002
REV. PrF 10/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Act i ve and Appar ent Ener gy Met er i ng I C
wi t h di / dt sensor i nt er f ace
ADE7753*
FEATURES
High Accuracy, supports IEC 61036 and IEC61268
On-Chip Digital Integrator enables direct interface with
current sensors with di/ dt output
The ADE7753 supplies Active, Reactive and Apparent
Energy, Sampled Waveform, Current and Voltage RMS
Less than 0.1% error over a dynamic range of 1000 to 1
Positive only energy accumulation mode available
An On-Chip user Programmable threshold for line
voltage surge and SAG, and PSU supervisory
Digital Power, Phase & Input Offset Calibration
An On-Chip temperature sensor (±3°C typical)
A SPI compatible Serial Interface
A pulse output with programmable frequency
An Interrupt Request pin (IRQ) and Status register
Proprietary ADCs and DSP provide high accuracy data over
large variations in environmental conditions and time
Reference 2.4V±8% (20 ppm/ °C typical)
with external overdrive capability
Single 5V Supply, Low power (25mW typical)
FUNCTIONAL BLOCK DIAGRAM
* U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others Pending.
precise phase mat ching bet ween t he current and volt age
channels. The integrator can be switched on and off based on
the current sensor selected.
T he ADE7753 cont ains an Act ive Energy regist er. It is
capable of holding more than 200 seconds of accumulated
power at full load. Data is read from the ADE7753 via the
serial interface. The ADE7753 also provides a pulse output
(CF) wit h out put frequency is proport ional t o t he act ive
power .
In addition to rms calculation and active and apparent power
informat ion, t he ADE7753 also accumulat es t he signed
reactive energy. The ADE7753 also provides various system
calibrat ion feat ures, i. e. , channel offset correct ion, phase
calibration and power calibration. The part also incorporates
a det ect ion circuit for short durat ion low or high volt age
variat ions.
The ADE7753 has a positive only accumulation mode which
gives the option to accumulate energy only when positive
power is detected. An internal no-load threshold ensures that
the part does not exhibit any creep when there is no load.
A zero crossing output (ZX) produces an output which is
synchronized to the zero crossing point of the line voltage.
This information is used in the ADE7753 to measure the
line's period. The signal is also used internally to the chip in
t he line cycle Act ive and Apparent energy accumulat ion
mode. This enables a faster and more precise energy accumu-
lation and is useful during calibration. This signal is also
useful for synchronization of relay switching with a voltage
zero crossing.
The interrupt request output is an open drain, active low logic
output. The Interrupt Status Register indicates the nature of
t he int errupt , and t he Int errupt Enable Regist er cont rols
which event produces an output on the IRQ pin.
The ADE7753 is available in 20-lead SSOP package.
:

DVDD
HPF
LPF2
DGND
CLKOUT
V1P
V1N
+
-
+
-
V2P
V2N
2.4V
REFERENCE
ADC
AVDD
PGA
CLKIN
REF
IN/OUT
CF
RESET
AGND
4kΩ
Φ
PHCAL[5:0]
MULTIPLIER
Σ
APOS[15:0]
DIN DOUT SCLK CS
SAG
ZX
IRQ
ADE7753 REGISTERS &
SERIAL INTERFACE
ADE7753
TEMP
SENSOR
LPF1
INTEGRATOR
Ύdt
VRMSOS[11:0]
IRMSOS[11:0]
Σ
Σ
WGAIN[11:0]
WDIV[7:0]
CFNUM[11:0]
CFDEN[11:0]
DFC
VAGAIN[11:0]
VADIV[7:0]
:

PGA
ADC
PRELIMINARY TECHNICAL DATA
Pr el i mi nar y Techni cal Dat a
GENERAL DESCRIPTION
The ADE7753 is an accurat e act ive and apparent energy
measurements IC with a serial interface and a pulse output.
The ADE7753 incorporates two second order sigma delta
ADCs, a digit al int egrat or (on CH1), reference circuit ry,
temperature sensor, and all the signal processing required to
perform RMS calculation on the voltage and current, active,
reactive, and apparent energy measurement.
An on-chip digital integrator provides direct interface to di/
dt current sensors such as Rogowski coils. T he digit al
integrator eliminates the need for external analog integrator,
and this solution provides excellent long-term stability and
a
- 2-
(AV
DD
= DV
DD
= 5V ± 5% , AGND = DGND = 0V, On- Chi p Ref er enc e,
CLKI N = 3.579545MHz XTAL, TMI N t o TMAX = - 40°C t o + 85°C)
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE7753–SPECI FI CATI ONS
1,3
Parameter Spec Units Test Conditions/Comments
ENERGY MEASUREMENT ACCURACY
Measur ement Bandwidt h 1 4 k H z CLKI N = 3. 579545 MHz
Measurement Error
1
on Channel 1 Channel 2 = 300mV rms/60Hz, Gain = 2
Channel 1 Range = 0.5V full-scale
Gain = 1 0.1 % typ Over a dynamic range 1000 to 1
Gain = 2 0.1 % typ Over a dynamic range 1000 to 1
Gain = 4 0.1 % typ Over a dynamic range 1000 to 1
Gain = 8 0.1 % typ Over a dynamic range 1000 to 1
Gain = 16 0.2 % typ Over a dynamic range 1000 to 1
Channel 1 Range = 0.25V full-scale
Gain = 1 0.1 % typ Over a dynamic range 1000 to 1
Gain = 2 0.1 % typ Over a dynamic range 1000 to 1
Gain = 4 0.1 % typ Over a dynamic range 1000 to 1
Gain = 8 0.2 % typ Over a dynamic range 1000 to 1
Gain = 16 0.2 % typ Over a dynamic range 1000 to 1
Channel 1 Range = 0.125V full-scale
Gain = 1 0.1 % typ Over a dynamic range 1000 to 1
Gain = 2 0.1 % typ Over a dynamic range 1000 to 1
Gain = 4 0.2 % typ Over a dynamic range 1000 to 1
Gain = 8 0.2 % typ Over a dynamic range 1000 to 1
Gain = 16 0.4 % typ Over a dynamic range 1000 to 1
Phase Error
1
Between Channels ±0.05 ° max Line Frequency = 45Hz to 65Hz, HPF on
AC Power Supply Rejection
1
AV
DD
= DV
DD
= 5V+175mV rms/ 120Hz
Output Frequency Variation (CF) 0.2 % typ Channel 1 = 20mV rms, Gain = 16, Range = 0.5V
Channel 2 = 300mV rms/60Hz, Gain = 1
DC Power Supply Rejection
1
AV
DD
= DV
DD
= 5V ± 250mV dc
Output Frequency Variation (CF) ±0.3 % typ Channel 1 = 20mV rms/60Hz, Gain = 16, Range = 0.5V
Channel 2 = 300mV rms/60Hz, Gain = 1
ANALOG INPUTS See Analog Inputs Section
Maximum Signal Levels ±0.5 V max V1P, V1N, V2N and V2P to AGND
Input Impedance (dc) 390 kΩ min
Bandwidth 14 kHz CLKIN/256, CLKIN = 3.579545MHz
Gain Error
1,4
External 2.5V reference, Gain = 1 on Channel 1 & 2
Channel 1
Range = 0.5V full-scale ±4 % typ V1 = 0.5V dc
Range = 0.25V full-scale ±4 % typ V1 = 0.25V dc
Range = 0.125V full-scale ±4 % typ V1 = 0.125V dc
Channel 2 ±4 % typ V2 = 0.5V dc
Gain Error Match
1
External 2.5V reference
Channel 1
Range = 0.5V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16
Range = 0.25V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16
Range = 0.125V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16
Channel 2 ±0.3 % typ Gain = 1, 2, 4, 8, 16
Offset Error
1
Channel 1 ±10 mV max Channel 1 Range = 0.5V
Channel 2 ±10 mV max Channel 2 Range = 0.5V
WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545MHz/128 = 27.9kSPS
Channel 1 See Channel 1 Sampling
Signal-to-Noise plus distortion 62 dB typ 150mV rms/60Hz, Range = 0.5V, Gain = 2
Bandwidth (-3dB) 14 kHz CLKIN = 3.579545MHz
Channel 2 See Channel 2 Sampling
Signal-to-Noise plus distortion 52 dB typ 150mV rms/60Hz, Gain = 2
Bandwidth (-3dB) 140 Hz CLKIN = 3.579545MHz
ADE7753
–3–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Parameter Spec Units Test Conditions/Comments
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range 2.6 V max 2.4 V +8%
2.2 V min 2.4V -8%
Input Capacitance 10 pF max
ON-CHIP REFERENCE Nominal 2.4V at REF
IN/OUT
pin
Reference Error ±200 mV max
Current source 10 µA max
Output Impedance 4 kΩ min
Temperature Coefficient 20 ppm/°C typ
CLKIN Note all specifications CLKIN of 3.579545MHz
Input Clock Frequency 4 MHz max
1 MHz min
LOGIC INPUTS
RESET, DI N, SCLK, CLKI N and CS
Input High Voltage, V
INH
2.4 V min DV
DD
= 5 V ± 10%
Input Low Voltage, V
INL
0.8 V max DV
DD
= 5 V ± 10%
Input Current, I
IN
±3 µA max Typically 10nA, V
IN
= 0V to DV
DD
Input Capacitance, C
IN
10 pF max
LOGIC OUTPUTS
3
SAG & IRQ Open Drain out put s, 10kΩ pull up resist or
Output High Voltage, V
OH
4 V min I
SOURCE
= 5mA
Output Low Voltage, V
OL
0.4 V max I
SINK
= 0.8mA
ZX & DOUT
Output High Voltage, V
OH
4 V min I
SOURCE
= 5mA
Output Low Voltage, V
OL
0.4 V max I
SINK
= 0.8mA
CF
Output High Voltage, V
OH
4 V min I
SOURCE
= 5mA
Output Low Voltage, V
OL
1 V max I
SINK
= 7mA
POWER SUPPLY For specified Performance
AV
DD
4.75 V min 5V - 5%
5.25 V max 5V +5%
DV
DD
4.75 V min 5V - 5%
5.25 V max 5V + 5%
AI
DD
3 mA max Typically 2.0 mA
DI
DD
4 mA max Typically 3.0 mA
NOTES:
1
See Terminology Section for explanation of Specifications
2
See Plots in Typical Performance Graphs
3
Specifications subject to change without notice
4
See Analog Inputs Section
200 µA
1.6 mA
I
OH
I
OL
C
L
50pF
TO
OUTPUT
PIN
+2.1V
Load Circuit for Timing Specifications
ORDERING GUIDE
MOD EL Package Opt ion*
ADE7753ARS RS- 20
ADE7753ARSRL RS- 20
EVAL- ADE7753EB ADE7753 evaluat ion board
* RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small Outline
Package in reel.
ADE7753
–4– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
CS
SCLK
DIN
A4 A3 A2 A1 A0 DB7
Most Significant Byte
t
1
t
2
t
3
t
4
t
5
t
8
1 DB0 DB7
DB0
t
6
Least Significant Byte
t
7
t
7
0 0
Command Byte
CS
SCLK
DIN A4 A3 A2 A1 A0
t
1
t
11
t
11
t
9
DB7
DOUT
t
12
DB0 DB0 DB7
t
10
t
13
Most Significant Byte Least Significant Byte
0 0 0
Command Byte
Serial Write Timing
Serial Read Timing
ADE7753 TI MI NG CHARACTERI STI CS
1, 2
Parameter A,B Versions Units Test Conditions/Comments
Write timing
t
1
20 ns (min) CS falling edge to first SCLK falling edge
t
2
150 ns (min) SCLK logic high pulse width
t
3
150 ns (min) SCLK logic low pulse width
t
4
10 ns (min) Valid Data Set up time before falling edge of SCLK
t
5
5 ns (min) Data Hold time after SCLK falling edge
t
6
T BD ns (min) Minimum time between the end of data byte transfers.
t
7
T BD ns (min) Minimum time between byte transfers during a serial write.
t
8
100 ns (min) CS Hold time after SCLK falling edge.
Read timing
t
9
3. 1 us (min) Minimum time between read command (i.e. a write to Communication
Reigster) and data read.
t
10
T BD ns (min) Minimum time between data byte transfers during a multibyte read.
t
11
3
30 ns (min) Data access time after SCLK rising edge following a write to the
Communicat ions Regist er
t
12
4
100 ns (max) Bus relinquish time after falling edge of SCLK.
10 ns (min)
t
13
4
100 ns (max) Bus relinquish time after rising edge of CS.
10 ns (min)
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)
and timed from a voltage level of 1.6V.
2
See timing diagram below and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.
4
Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part
and is independent of t he bus loading.
(AV
DD
= DV
DD
= 5V ± 5% , AGND = DGND = 0V, On- Chi p Ref er enc e,
CLKI N = 3.579545MHz XTAL, TMI N t o TMAX = - 40°C t o + 85°C)
ADE7753
–5–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Ter minology
MEASUREMENT ERROR
The error associated with the energy measurement made by
the ADE7753 is defined by the following formula:
%
Energy True
Energy True ADE by registered Energy
Error Percentage
100
7753
×







 −
·
PHASE ERROR BETWEEN CHANNELS
The digit al int egrat or and t he HPF (High Pass Filt er) in
Channel 1 have non-ideal phase response. T o offset t his
phase response and equalize t he phase response bet ween
channels, two phase correction network is placed in Channel
1: one for the digital integrator and the other for the HPF.
Each phase correction network corrects the phase response of
t he corresponding component and ensures a phase mat ch
bet ween Channel 1 (current ) and Channel 2 (volt age) t o
within ±0.1° over a range of 45Hz to 65Hz and ±0.2° over
a range 40Hz to 1kHz.
POWER SUPPLY REJECTION
This quantifies the ADE7753 measurement error as a per-
cent age of reading when t he power supplies are varied.
For the AC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
input signal levels when an ac (175mV rms/120Hz) signal is
introduced onto the supplies. Any error introduced by this
AC signal is expressed as a percent age of reading—see
Measurement Error definit ion above.
For the DC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
toAV
DD
. . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND
V
1P
, V
1N
, V
2P
and V
2N
. . . . . . . . . . . . . . . . . . -6V to +6V
Reference Input Voltage to AGND . . . . –0.3 V to AV
DD
+
0. 3 V
Digital Input Voltage to DGND –0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND –0.3 V to DV
DD
+ 0.3 V
Operat ing T emperat ure Range
Indust rial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
St orage Temperat ure Range . . . . . . . . –65°C to +150°C
Junct ion T emperat ure . . . . . . . . . . . . . . . . . . . . . . . +150°C
20 Pin SSOP, Power Dissipation . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . 112°C/W
Lead T emperat ure, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
*
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTI ON
ESD (elect rost at ic discharge) sensit ive device. Elect rost at ic charges as high as 4000 V readily accumu-
late on the human body and test equipment and can discharge without detection. Although the ADE7753
feat ures propriet ary ESD prot ect ion circuit ry, permanent damage may occur on devices subject ed t o
high energy elect rost at ic discharges. Therefore, proper ESD precaut ions are recommended t o avoid
performance degradat ion or loss of funct ionalit y.
input signal levels when the supplies are varied ±5%. Any
er r or int r oduced is again expr essed as a per cent age of
r eading.
ADC OFFSET ERROR
This refers to the DC offset associated with the analog inputs
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see a dc analog input signal. The
magnitude of the offset depends on the gain and input range
selection - see characteristic curves. However, when HPF1 is
switched on the offset is removed from Channel 1 (current)
and the power calculation is not affected by this offset. The
offsets may be removed by performing an offset calibration -
see Analog Inputs.
GAIN ERROR
The gain error in t he ADE7753 ADCs is defined as t he
difference between the measured ADC output code (minus
the offset) and the ideal output code - see Channel 1 ADC &
Channel 2 ADC. It is measured for each of the input ranges
on Channel 1 (0.5V, 0.25V and 0.125V). The difference is
expressed as a percentage of the ideal code.
GAIN ERROR MATCH
The Gain Error Match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 (for each
of the input ranges) and a gain of 2, 4, 8, or 16. It is expressed
as a percentage of the output ADC code obtained under a gain
of 1. T his gives t he gain error observed when t he gain
selection is changed from 1 to 2, 4, 8 or 16.
WARNING!
ESD SENSITIVE DEVICE
ADE7753
–6– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTION
Pin No. MNEMONIC D ES CRIP TION
1 RESET Reset pin for the ADE7753. A logic low on this pin will hold the ADCs and digital
circuitry (including the Serial Interface) in a reset condition.
2 DV
DD
Digital power supply. This pin provides the supply voltage for the digital circuitry in
the ADE7753. The supply voltage should be maintained at 5V ± 5% for specified op-
eration. This pin should be decoupled to DGND with a 10µF capacitor in parallel with
a ceramic 100nF capacitor.
3 AV
DD
Analog power supply. This pin provides the supply voltage for the analog circuitry in
the ADE7753. The supply should be maintained at 5V ± 5% for specified operation.
Every effort should be made to minimize power supply ripple and noise at this pin by
the use of proper decoupling. The typical performance graphs in this data sheet show
the power supply rejection performance. This pin should be decoupled to AGND with a
10µF capacitor in parallel with a ceramic 100nF capacitor.
4, 5 V1P, V1N Analog inputs for Channel 1. This channel is intended for use with the di/dt current
transducer such as Rogowski coil or other current sensor such as shunt or current trans-
former (CT). These inputs are fully differential voltage inputs with maximum
differential input signal levels of ±0.5V, ±0.25V and ±0.125V, depending on the full
scale selection - See Analog Inputs. Channel 1 also has a PGA with gain selections of 1,
2, 4, 8 or 16. The maximum signal level at these pins with respect to AGND is ±0.5V.
Both inputs have internal ESD protection circuitry and in addition an overvoltage of
±6V can be sustained on these inputs without risk of permanent damage.
6, 7 V2N, V2P Analog inputs for Channel 2. This channel is intended for use with the voltage trans-
ducer. These inputs are fully differential voltage inputs with a maximum differential
signal level of ±0.5V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8 or
16. The maximum signal level at these pins with respect to AGND is ±0.5V. Both
inputs have internal ESD protection circuitry, and an overvoltage of ±6V can be sus-
tained on these inputs without risk of permanent damage.
8 AGN D This pin provides the ground reference for the analog circuitry in the ADE7753, i.e.
ADCs and reference. This pin should be tied to the analog ground plane or the quietest
ground reference in the system. This quiet ground reference should be used for all ana-
log circuitry, e.g. anti-aliasing filters, current and voltage transducers etc. In order to
keep ground noise around the ADE7753 to a minimum, the quiet ground plane should
only connected to the digital ground plane at one point. It is acceptable to place the
entire device on the analog ground plane - see Applications Information.
9 REF
IN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a
nominal value of 2.4V ± 8% and a typical temperature coefficient of 20ppm/°C. An
external reference source may also be connected at this pin. In either case this pin
should be decoupled to AGND with a 1µF ceramic capacitor.
10 D G N D This provides the ground reference for the digital circuitry in the ADE7753, i.e. multi-
plier, filters and digital-to-frequency converter. Because the digital return currents in
the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane
of the system - see Applications Information. However, high bus capacitance on the DOUT
pin may result in noisy digital current which could affect performance.
11 C F Calibration Frequency logic output. The CF logic output gives Active Power informa-
tion. This output is intended to be used for operational and calibration purposes. The
full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM
Register—see Energy To Frequency Conversion.
12 Z X Voltage waveform (Channel 2) zero crossing output. This output toggles logic high and
low at the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection.
13 SAG This open drain logic output goes active low when either no zero crossings are detected
or a low voltage threshold (Channel 2) is crossed for a specified duration. See Line Volt-
age Sag Detection.
14 I RQ Interrupt Request Output. This is an active low open drain logic output. Maskable
interrupts include: Active Energy Register roll-over, Active Energy Register at half
level, and arrivals of new waveform samples. See ADE7753 Interrupts.
ADE7753
–7–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION
SSOP Packages
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
DGND
CS
CLKOUT
CLKIN
ZX
CF
ADE7753
TOP VIEW
(Not to Scale)
AGND
IRQ
RESET
DVDD
V1P
V1N
V2N
V2P
SAG
REF
IN/OUT
11
12
AVDD
DIN
DOUT
SCLK
Pin No. MNEMONIC DESCRIPTION
15 CLKI N Master clock for ADCs and digital signal processing. An external clock can be pro-
vided at this logic input. Alternatively, a parallel resonant AT crystal can be connected
across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock
frequency for specified operation is 3.579545MHz. Ceramic load capacitors of between
22pF and 33pF should be used with the gate oscillator circuit. Refer to crystal manu-
facturers data sheet for load capacitance requirements.
16 C LKOU T A crystal can be connected across this pin and CLKIN as described above to provide a
clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when
either an external clock is supplied at CLKIN or a crystal is being used.
17 CS Chip Select. Part of the four wire SPI Serial Interface. This active low logic input al-
lows the ADE7753 to share the serial bus with several other devices. See ADE7753 Serial
Interface.
18 SC LK Serial Clock Input for the synchronous serial interface. All Serial data transfers are
synchronized to this clock—see ADE7753 Serial Interface. The SCLK has a schmitt-trigger
input for use with a clock source which has a slow edge transition time, e.g., opto-
isolat or out put s.
19 D O U T Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of
SCLK. This logic output is normally in a high impedance state unless it is driving data
onto the serial data bus—see ADE7753 Serial Interface..
20 D I N Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of
SCLK—see ADE7753 Serial Interface..
ADE7753
–8– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics-ADE7753
TBD
TPC 1— Error as a % of Reading (Gain=1)
TBD
TPC 2— Error as a % of Reading (Gain=4)
TBD
TPC 3— Error as a % of Reading (Gain=16)
TBD
TPC 4— Error as a % of Reading (Full-Scale input for Chan-
nel 1=0.25V, Gain=4)
TBD
TPC 5— Error as a % of Reading (Full-scale input for Chan-
nel 1=0.125V, Gain=8)
TBD
TPC 6— Test Circuits for Performance Curves
ADE7753
–9–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ANALOG INPUTS
The ADE7753 has two fully differential voltage input chan-
nels. The maximum differential input voltage for input pairs
V1P/V1N and V2P/V2N are ±0.5V. In addition, the maxi-
mum signal level on analog inputs for V1P/V1N and V2P/
V2N are ±0.5V with respect to AGND.
Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8 and 16.
The gain selections are made by writing to the Gain regis-
ter—see Figure 2. Bits 0 to 2 select the gain for the PGA in
Channel 1 and the gain selection for the PGA in Channel 2
is made via bits 5 to 7. Figure 1 shows how a gain selection
for Channel 1 is made using the Gain register.
V1P
V1N
V
in
k.V
in
+
-
Σ
+
GAIN[7:0]
Gain (k)
selection
Offset
Adjust
(±50mV)
CH1OS[7:0]
Bit 0 to 5: Sign magnitude coded offset correction
Bit 6: Not used
Bit 7: Digital Integrator (On=1, Off=0; default ON)
Figure 1— PGA in Channel 1
In addition to the PGA, Channel 1 also has a full scale input
range selection for the ADC. The ADC analog input range
selection is also made using the Gain register—see Figure 2.
As ment ioned previously t he maximum different ial input
voltage is 1V. However, by using bits 3 and 4 in the Gain
register, the maximum ADC input voltage can be set to 0.5V,
0.25V or 0.125V. This is achieved by adjusting the ADC
reference—see ADE7753 Reference Circuit. Table I below sum-
marizes t he maximum different ial input signal level on
Channel 1 for the various ADC range and gain selections.
GAIN REGISTER*
Channel 1 and Channel 2 PGA Control
ADDR: 0FH
0 1 2 3 4 5 6 7
PGA 2 Gain Select
000 = x1
001 = x2
010 = x4
011 = x8
100 = x16
0 0 0 0 0 0 0 0
*Register contents show power on defaults
PGA 1 Gain Select
000 = x1
001 = x2
010 = x4
011 = x8
100 = x16
Channel 1 Full Scale Select
00 = 0.5V
01 = 0.25V
10 = 0.125V
Figure 2— ADE7753 Analog Gain register
It is also possible to adjust offset errors on Channel 1 and
Channel 2 by writ ing t o t he Offset Correct ion Regist ers
(CH1OS and CH2OS respect ively). These regist ers allow
channel offsets in the range ±20mV to ±50mV (depending on
the gain setting) to be removed. Note that it is not necessary
to perform an offset correction in an Energy measurement
application if HPF in Channel 1 is switched on. Figure 3
shows the effect of offsets on the real power calculation. As
can be seen from Figure 3, an offset on Channel 1 and
Channel 2 will contribute a dc component after multiplica-
t ion. Since t his dc component is ext ract ed by LPF2 t o
generate the Active (Real) Power information, the offsets will
have contributed an error to the Active Power calculation.
This problem is easily avoided by enabling HPF in Channel
1. By removing the offset from at least one channel, no error
component is generated at dc by the multiplication. Error
terms at Cos(w.t) are removed by LPF2 and by integration of
the Active Power signal in the Active Energy register (AEN-
ERGY[23:0]) – see Energy Calculation.
V.I
2
frequency (rad/s)
ω 2ω 0
V
OS
.I
OS
V
OS
.I
I
OS
.V
DC component (including error term) is
extracted by the LPF for real power
calculation
Figure 3— Effect of channel offsets on the real power cal-
culation
The contents of the Offset Correction registers are 6-Bit, sign
and magnit ude coded. T he weight ing of t he LSB size
depends on the gain setting, i.e., 1, 2, 4, 8 or 16. Table II
below shows the correctable offset span for each of the gain
settings and the LSB weight (mV) for the Offset Correction
registers. The maximum value which can be written to the
offset correction registers is ±31 decimal —see Figure 4.
Figure 4 shows the relationship between the Offset Correc-
tion register contents and the offset (mV) on the analog inputs
for a gain set t ing of one. In order t o perform an offset
adjustment, The analog inputs should be first connected to
AGND, and there should be no signal on either Channel 1
or Channel 2. A read from Channel 1 or Channel 2 using the
Max Signal ADC Input Range Selection
Channel 1 0 . 5 V 0 . 2 5 V 0 . 1 2 5 V
0. 5V Gain = 1 — —
0. 25V Gain = 2 Gain = 1 —
0. 125V Gain = 4 Gain = 2 Gain = 1
0. 0625V Gain = 8 Gain = 4 Gain = 2
0. 0313V Gain = 16 Gain = 8 Gain = 4
0. 0156V — Gain = 16 Gain = 8
0. 00781V — — Gain = 16
Table I
Maximum input signal levels for Channel 1
ADE7753
–10– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Waveform register will give an indication of the offset in the
channel. This offset can be canceled by writing an equal and
opposite offset value to the relevant offset register. The offset
correct ion can be confirmed by performing anot her read.
Note when adjusting the offset of Channel 1, one should
disable the digital integrator and the HPF.
CH1OS[5:0]
00h
1Fh
3Fh
+50mV
-50mV
0mV
Offset
Adjust
01, 1111b
11, 1111b
Sign + 5 Bits
Sign + 5 Bits
Figure 4– Channel Offset Correction Range (Gain = 1)
Gai n Correctable Span LSB Size
1 ± 50mV 1. 61mV/LSB
2 ± 37mV 1. 19mV/LSB
4 ± 30mV 0. 97mV/LSB
8 ± 26mV 0. 84mV/LSB
16 ± 24mV 0. 77mV/LSB
Table II
Offset Correct ion range
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
di/dt sensor detects changes in magetic field caused by ac
current. Figure 5 shows the principle of a di/dt current
sensor.
+
-
EMF (electromotive force)
induced by changes in
magnetic flux density (d/dt)
Magnetic field created by current
(directly proportional to current)
Figure 5– Principle of a di/dt current sensor
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in t he magnet ic flux densit y passing t hrough a
conduct or loop generat es an elect romot ive force ( EMF)
between the two ends of the loop. The EMF is a voltage signal
which is proportional to the di/dt of the current. The voltage
output from the di/dt current sensor is determined by the
mutual inductance between the current carrying conductor
and the di/dt sensor.
The current signal needs to be recovered from the di/dt signal
before it can be used. An integrator is therefore necessary to
restore the signal to its original form. The ADE7753 has a
built-in digital integrator to recover the current signal from
t he di/dt sensor. T he digit al int egrat or on Channel 1 is
switched off by default when the ADE7753 is powered up.
Set t ing t he MSB of CH1OS r egist er will t ur n on t he
integrator. Figures 6 to 9 show the magnitude and phase
response of the digital integrator.
10
2
10
3
-50
-40
-30
-20
-10
0
10
FREQUENCY-Hz
G
A
I
N
-
d
B
Figure 6– Combined gain response of the digital integrator
and phase compensator
10
2
10
3
-90.5
-90
-89.5
-89
-88.5
-88
FREQUENCY-Hz
P
H
A
S
E
-
D
E
G
R
E
E
S
Figure 7– Combined phase response of the digital integra-
tor and phase compensator
40 45 50 55 60 65 70
-6
-5.5
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
FREQUENCY-Hz
G
A
IN
-
d
B
Figure 8– Combined gain response of the digital integrator
and phase compensator (40Hz to 70Hz)
ADE7753
–11–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ZERO CROSSING DETECTION
T he ADE7753 has a zero crossing det ect ion circuit on
Channel 2. This zero crossing is used to produce an external
zero cross signal (ZX) and it is also used in the calibration
mode - see Energy Calibration. The zero crossing signal is also
used to initiate a temperature measurement on the ADE7753
- see Temperature Measurement.
Figure 10 shows how the zero cross signal is generated from
the output of LPF1.
V2P
V2N
ADC 2
PGA2
1
x1, x2, x4,
x8, x16
REFERENCE
GAIN[7:5]
V2
TO
MULTIPLIER
-63% to + 63% FS
LPF1
f
-3dB
= 140Hz
ZERO
CROSS
ZX
V2 LPF1
ZX
23.2 8@ 60Hz
0.92
1.0
Figure 10– Zero cross detection on Channel 2
The ZX signal will go logic high on a positive going zero
crossing and logic low on a negative going zero crossing on
Channel 2. The zero crossing signal ZX is generated from the
output of LPF1. LPF1 has a single pole at 156Hz (at CLKIN
= 3. 579545MHz). As a result t here will be a phase lag
between the analog input signal V2 and the output of LPF1.
The phase response of this filter is shown in the Channel 2
Sampling section of this data sheet. The phase lag response of
LPF1 results in a time delay of approximately 0.97ms (@
60Hz) bet ween t he zero crossing on t he analog input s of
Channel 2 and the rising or falling edge of ZX.
The zero-crossing detection also drives one flag bit in the
interrupt status register. An active low in the IRQ output will
also appear if the corresponding bit in the Interrupt Enable
register is set to logic one.
The flag in the Interrupt status register as well as the IRQ
output are reset to their default value when the Interrupt
Status register with reset (RSTSTATUS) is read.
Zero Crossing Timeout
The zero crossing detection also has an associated time-out
r egist er ZXT OUT . T his u n sign ed , 12- bit r egist er is
decremented (1 LSB) every 128/CLKIN seconds. The reg-
ister is reset to its user programmed full scale value every time
a zero crossing on Channel 2 is detected. The default power
on value in this register is FFFh. If the register decrements
to zero before a zero crossing is detected and the DISSAG bit
in the Mode register is logic zero, the SAG pin will go active
low. The absence of a zero crossing is also indicated on the
IRQ pin if t he ZXTO enable bit in t he Int errupt Enable
regist er is set t o logic one. Irrespect ive of t he enable bit
set t ing, t he ZXTO flag in t he Int errupt St at us regist er is
always set when the ZXTOUT register is decremented to
zero - see ADE7753 Interrupts.
The Zerocross Time-out register can be written/read by the
user and has an address of 1Dh - see Serial Interface section. The
resolution of the register is 128/CLKIN seconds per LSB.
Thus the maximum delay for an interrupt is 0.15 second
(128/CLKIN × 2
12
).
Figure 11 shows the mechanism of the zero crossing time out
detection when the line voltage stays at a fixed DC level for
more than CLKIN/128 x ZXTOUT seconds.
Channel 2
ZXTO
detection bit
ZXTOUT
16-bit internal
register value
Figure 11 - Zero crossing Time out detection
PERIOD MEASUREMENT
The ADE7753 provides also the period measurement of the
line. The period register is an unsigned 15-bit register and is
updated every period.
T he r esolut ion of t his r egist er is 2. 2ms/LSB when
CLKIN=3.579545MHz, which represents 0.013% when the
line frequency is 60Hz. When the line frequency is 60Hz, the
value of t he Period regist er is approximat ely 7576d. The
lengt h of t he r egist er enables t he measur ement of line
frequencies as low as 13.9Hz.
40 45 50 55 60 65 70
-90.05
-90
-89.95
-89.9
-89.85
-89.8
-89.75
-89.7
FREQUENCY-Hz
P
H
A
S
E
-
D
E
G
R
E
E
S
Figure 9– Combined phase response of the digital integra-
tor and phase compensator (40Hz to 70Hz)
Not e t hat t he int egrat or has a -20dB/dec at t enuat ion and
approximately -90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be
a flat gain over the frequency band of interest. However, the
di/dt sensor has a 20dB/dec gain associat ed wit h it , and
generates significant high frequency noise, a more effective
anti-aliasing filter is needed to avoid noise due to aliasing—
see Antialias Filter.
When the digital integrator is switched off, the ADE7753 can
be used directly with a conventional current sensor such as
current transformer (CT) or a low resistance current shunt.
ADE7753
–12– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
POWER SUPPLY MONITOR
The ADE7753 also contains an on-chip power supply moni-
tor. The Analog Supply (AV
DD
) is continuously monitored
by the ADE7753. If the supply is less than 4V ± 5% then the
ADE7753 will go into an inactive state, i.e. no energy will be
accumulated when the supply voltage is below 4V. This is
useful to ensure correct device operation at power up and
during power down. The power supply monitor has built-in
hysteresis and filtering. This gives a high degree of immunity
to false triggering due to noisy supplies.
Time
AV
DD
0V
4V
5V
ADE7753
Power-on
Inactive
State
Inactive Active Inactive
SAG
Figure 12 - On-Chip power supply monitor
As can be seen from Figure 12 the trigger level is nominally
set at 4V. The tolerance on this trigger level is about ±5%.
The SAG pin can also be used as a power supply monitor
input to the MCU. The SAG pin will go logic low when the
ADE7753 is in it s inact ive st at e. T he power supply and
decoupling for the part should be such that the ripple at
AV
DD
does not exceed 5V±5% as specified for normal
operat ion.
LINE VOLTAGE SAG DETECTION
In addition to the detection of the loss of the line voltage
signal ( zer o cr ossing) , t he ADE7753 can also be pr o-
grammed to detect when the absolute value of the line voltage
drops below a certain peak value, for a number of line cycles.
This condition is illustrated in Figure 13 below.
SAGCYC[7:0] = 06H
6 half cycles
SAGLVL[7:0]
Full Scale
Channel 2
SAG
SAG reset high
when Channel 2
exceeds SAGLVL[7:0]
Figure 13– ADE7753 Sag detection
Figure 13 shows the line voltage fall below a threshold which
is set in the Sag Level register (SAGLVL[7:0]) for five line
cycles. Since t he Sag Cycle regist er (SAGCYC[7:0]) con-
tains 03h the SAG pin will go active low at the end of the fifth
line cycle for which the line voltage falls below the threshold,
if the DISSAG bit in the Mode register is logic zero. As is
the case when zero-crossings are no longer detected, the sag
event is also recorded by setting the SAG flag in the Interrupt
Status register. If the SAG enable bit is set to logic one, the
IRQ logic output will go active low - see ADE7753 Interrupts.
The SAG pin will go logic high again when the absolute value
of the signal on Channel 2 exceeds the sag level set in the Sag
Level register. This is shown in Figure 13 when the SAG pin
goes high during the tenth line cycle from the time when the
signal on Channel 2 first dropped below the threshold level.
Sag Level Set
The contents of the Sag Level register (1 byte) are compared
to the absolute value of the most significant byte output from
LPF1, after it is shifted left by one bit. Thus for example the
nominal maximum code from LPF1 with a full scale signal
on Channel 2 is 2518h—see Channel 2 sampling. Shifting one
bit left will give 4A30h. Therefore writing 4Ah to the SAG
Level register will put the sag detection level at full scale.
Writing 00h will put the sag detection level at zero. The Sag
Level register is compared to the most significant byte of a
waveform sample after the shift left and detection is made
when the contents of the sag level register are greater.
PEAK DETECTION
The ADE7753 can also be programmed to detect when the
absolute value of the voltage or the current channel of one
phase exceeds a certain peak value. Figure 14 illustrates the
behavior of the peak detection for the voltage channel.
VPKLVL[7:0]
V
2
PKV Interrupt Flag
(Bit 8 of STATUS register)
PKV reset low
when RSTSTATUS register
is read
Read RSTSTATUS register
Figure 14 - ADE7753 Peak detection
Both channel 1 and channel 2 are monitored at the same time.
Figure 14 shows a line voltage exceeding a threshold which
is set in t he Volt age peak regist er (VPKLVL[7:0]). T he
Voltage Peak event is recorded by setting the PKV flag in the
Interrupt Status register. If the PKV enable bit is set to logic
one in the Interrupt Mask register, the IRQ logic output will
go active low. Similarly, the Current Peak event is recorded
by setting the PKI flag in the Ineterrupt Status register—see
ADE7753 Interrupts.
Peak Level Set
T he cont ent s of t he VPKLVL and IPKLVL regist ers are
respectively compared to the absolute value of channel 1 and
channel 2, after they are multiplied by 2.
ADE7753
–13–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE7753 INTERRUPTS
ADE7753 Int errupt s are managed t hrough t he Int errupt
St at us regist er (STATUS[15:0]) and t he Int errupt Enable
register (IRQEN[15:0]). When an interrupt event occurs in
the ADE7753, the corresponding flag in the Status register
is set to a logic one - see Interrupt Status register. If the enable
bit for this interrupt in the Interrupt Enable register is logic
one, then the IRQ logic output goes active low. The flag bits
in the Status register are set irrespective of the state of the
enable bits.
In order to determine the source of the interrupt, the system
mast er ( MCU) should perform a read from t he St at us
regist er wit h reset (RSTSTATUS[15:0]). This is achieved
by carrying out a read from address 0Ch. The IRQ output will
go logic high on completion of the Interrupt Status register
Thus, for example, t he nominal maximum code from t he
channel 1 ADC with a full scale signal is 2851ECh —see
Channel 1 Sampling. Multiplying by 2 will give 50A3D8h.
Therefore, writing 50h to the IPKLVL register will put the
channel 1 peak detection level at full scale and set the current
peak detection to its least sensitive value.
Writing 00h will put the channel 1 detection level at zero.
T he det ect ion is done when t he cont ent of t he IPKLVL
register is smaller than the incoming channel 1 sample.
Peak Level Record
The ADE7753 records the maximum absolute value reached
by channel 1 and channel 2 in two different registers - IPEAK
and VPEAK respect ively. VPEAK and IPEAK are 24-bit
unsigned registers. These registers are updated each time the
absolute value of the Waveform sample from the correspond-
ing channel is above the value stored in the VPEAK or IPEAK
register. The contents of the VPEAK register corresponds to
2 times the maximum absolute value observed on the channel
2 input. The contents of IPEAK represents the max absolute
value obser ved on t he channel 1 input . Reading t he
RSTVPEAK and RSTIPEAK regist ers will clear t heir re-
spective contents after the read operation.
IRQ
t
1
Jump to
ISR
Global int.
Mask Set
Clear MCU
int. flag
Read
Status with
Reset (05h)
ISR Action
(Based on Status contents)
ISR Return
Global int. Mask
Reset
t
2
t
3
MCU
int. flag set
Jump to
ISR
MCU Program
Sequence
Figure 15– ADE7753 interrupt management
read command—see Interrupt timing. When carrying out a read
wit h reset , t he ADE7753 is designed t o ensure t hat no
interrupt events are missed. If an interrupt event occurs just
as the Status register is being read, the event will not be lost
and the IRQ logic output is guaranteed to go high for the
duration of the Interrupt Status register data transfer before
going logic low again to indicate the pending interrupt. See
the next section for a more detailed description.
Using the ADE7753 Interrupts with an MCU
Shown in Figure 15 is a t iming diagram which shows a
suggest ed implement at ion of ADE7753 int errupt manage-
ment using an MCU. At time t
1
the IRQ line will go active
low indicating that one or more interrupt events have oc-
curred in the ADE7753. The IRQ logic output should be tied
to a negative edge triggered external interrupt on the MCU.
On det ect ion of t he negat ive edge, t he MCU should be
configured to start executing its Interrupt Service Routine
(ISR). On entering the ISR, all interrupts should be disabled
using the global interrupt enable bit. At this point the MCU
ext ernal int errupt flag can be cleared in order t o capt ure
interrupt events which occur during the current ISR. When
the MCU interrupt flag is cleared a read from the Status
register with reset is carried out. This will cause the IRQ line
to be reset logic high (t
2
)—see Interrupt timing. The Status
regist er cont ent s are used t o det ermine t he source of t he
interrupt(s) and hence the appropriate action to be taken. If
a subsequent interrupt event occurs during the ISR, that event
will be recorded by the MCU external interrupt flag being set
again (t
3
). On returning from the ISR, the global interrupt
mask will be cleared (same instruction cycle) and the external
interrupt flag will cause the MCU to jump to its ISR once
again. This will ensure that the MCU does not miss any
ext ernal int errupt s.
Interrupt timing
The ADE7753 Serial Interface section should be reviewed first
before reviewing t he int errupt t iming. As previously de-
CS
SCLK
DIN
t
1
t
11
t
11
t
9
DB7
DOUT
DB0 DB0 DB7
0 0 0
Read Status Register Command
0
1
0
0 1
IRQ
Status Register Contents
Figure 16– ADE7753 interrupt timing
ADE7753
–14– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
TEMPERATURE MEASUREMENT
ADE7753 also includes an on-chip temperature sensor. A
temperature measurement can be made by setting bit 5 in the
Mode register. When bit 5 is set logic high in the Mode
register, the ADE7753 will initiate a temperature measure-
ment on the next zero crossing. When the zero crossing on
Channel 2 is detected the voltage output from the tempera-
ture sensing circuit is connected to ADC1 (Channel 1) for
digitizing. The resultant code is processed and placed in the
Temperature register (TEMP[7:0]) approximately 26µs later
( 24 CLKIN cycles) . If enabled in t he Int errupt Enable
register (bit 5), the IRQ output will go active low when the
temperature conversion is finished. Please note that tempera-
ture conversion will introduce a small amount of noise in the
energy calculation. If temperature conversion is performed
frequent ly (e. g. mult iple t imes per second), a not iceable
error will accumulate in the resulting energy calculation over
t ime.
The cont ent s of t he Temperat ure regist er are signed (2's
complement) with a resolution of approximately 1 LSB/°C.
The temperature register will produce a code of 00h when the
ambient temperature is approximately 70°C. The tempera-
ture measurement is uncalibrated in the ADE7753 and has an
offset tolerance that could be as high as ±20°C.
ADE7753 ANALOG TO DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7753 is carried
out using two second order sigma-delta ADCs. For simplic-
ity reason, the block diagram in Figure 17 shows a first order
sigma-delta ADC. The converter is made up of two parts: the
sigma-delta modulator and the digital low pass filter.
V
REF
+
-
....10100101......
Digital Low Pass Filter
Σ
e
MCLK/4
INTEGRATOR
1-Bit DAC
LATCHED
COMPARATOR +
-
R
C
Analog Low Pass Filter
24
Figure 17– First Order Sigma-Delta (Σ−∆) ADC
A sigma-delt a modulat or convert s t he input signal int o a
continuous serial stream of 1's and 0's at a rate determined by
the sampling clock. In the ADE7753 the sampling clock is
equal to CLKIN/4. The 1-bit DAC in the feedback loop is
driven by the serial data stream. The DAC output is sub-
tracted from the input signal. If the loop gain is high enough
the average value of the DAC output (and therefore the bit
stream) will approach that of the input signal level. For any
given input value in a single sampling interval, the data from
the 1-bit ADC is virtually meaningless. Only when a large
number of samples are averaged will a meaningful result be
obtained. This averaging is carried out in the second part of
the ADC, the digital low pass filter. By averaging a large
number of bits from the modulator the low pass filter can
produce 24-bit data words which are proportional to the input
signal level.
The sigma-delt a convert er uses t wo t echniques t o achieve
high resolution from what is essentially a 1-bit conversion
technique. The first is over-sampling. By over sampling we
mean that the signal is sampled at a rate (frequency) which is
many t imes higher t han t he bandwidt h of int erest . For
example t he sampling rat e in t he ADE7753 is CLKIN/4
(894kHz) and the band of interest is 40Hz to 2kHz. Over-
sampling has the effect of spreading the quantization noise
(noise due to sampling) over a wider bandwidth. With the
noise spread more t hinly over a wider bandwidt h, t he
quantization noise in the band of interest is lowered—see
Figure 18. However, oversampling alone is not an efficient
enough method to improve the signal to noise ratio (SNR) in
the band of interest. For example, an oversampling ratio of
4 is required just to increase the SNR by only 6dB (1-Bit). To
keep t he oversampling rat io at a reasonable level, it is
possible to shape the quantization noise so that the majority
of t he noise lies at t he higher frequencies. T his is what
happens in the sigma-delta modulator, the noise is shaped by
the integrator which has a high pass type response for the
quantization noise. The result is that most of the noise is at
the higher frequencies where it can be removed by the digital
low pass filter. This noise shaping is also shown in Figure 18.
Frequency (Hz)
0 447kHz 894kHz
2kHz
Sampling
Frequency
Shaped
Noise
Antialias filter (RC)
Digital filter
Noise
Signal
Frequency (Hz)
0 447kHz 894kHz
2kHz
Noise
Signal
High resolution
output from Digital
LPF
Figure 18– Noise reduction due to Oversampling & Noise
shaping in the analog modulator
scribed, when the IRQ output goes low the MCU ISR must
read the Interrupt Status register in order to determine the
source of t he int errupt . When reading t he St at us regist er
contents, the IRQ output is set high on the last falling edge
of SCLK of t he first byt e t ransfer (read Int errupt St at us
register command). The IRQ output is held high until the last
bit of the next 15-bit transfer is shifted out (Interrupt Status
register contents)— see Figure 16. If an interrupt is pending
at this time, the IRQ output will go low again. If no interrupt
is pending the IRQ output will stay high.
Antialias Filter
Figure 17 also shows an analog low pass filter (RC) on the
input t o t he modulat or. T his filt er is present t o prevent
aliasing. Aliasing is an art ifact of all sampled syst ems.
Basically it means that frequency components in the input
signal to the ADC which are higher than half the sampling
rat e of t he ADC will appear in t he sampled signal at a
ADE7753
–15–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
frequency below half the sampling rate. Figure 19 illustrates
the effect. Frequency components (arrows shown in black)
above half the sampling frequency (also know as the Nyquist
frequency, i.e., 447kHz) get imaged or folded back down
below 447kHz (arrows shown in grey). This will happen with
all ADCs regardless of t he archit ect ure. In t he example
shown, only frequencies near the sampling frequency, i.e.,
894kHz, will move into the band of interest for metering, i.e,
40Hz - 2kHz. This allows the usage of very simple LPF (Low
Pass Filter) to attenuate high frequency (near 900kHz) noise
and prevents distortion in the band of interest. For conven-
tional current sensor, a simple RC filter (single pole LPF)
with a corner frequency of 10kHz will produce an attenuation
of approximat ely 40dBs at 894kHz—see Figure 18. T he
20dB per decade attenuation is usually sufficient to eliminate
the effects of aliasing for conventional current sensor.
For di/dt sensor such as Rogowski coil, however, the sensor
has 20dB per decade gain. This will neutralize the -20dB per
decade attenuation produced by the simple LPF. Therefore,
when using a di/dt sensor, care should be taken to offset the
20dB per decade gain coming from the di/dt sensor. One
simple approach is to cascade two RC filters to produce the
-40dB per decade attenuation needed.
Frequency (Hz)
Aliasing Effects
0 447kHz 894kHz 2kHz
image
frequencies
Sampling Frequency
Figure 19 —ADC and signal processing in Channel 1
ADC transfer function
Below is an expression which relates the output of the LPF
in the sigma-delta ADC to the analog input signal level. Both
ADCs in the ADE7753 are designed to produce the same
output code for the same input signal level.
144 , 262 0492 . 3 ) ( × × ·
out
in
V
V
ADC Code
Therefore with a full scale signal on the input of 0.5V and an
internal reference of 2.42V, the ADC output code is nomi-
nally 165, 151 or 2851Fh. T he maximum code from t he
ADC is ±262,144, this is equivalent to an input signal level
of ±0. 794V. However for specified performance it is not
recommended that the full-scale input signal level of 0.5V be
exceeded.
ADE7753 Reference circuit
Shown below in Figure 20 is a simplified version of t he
reference output circuitry. The nominal reference voltage at
the REF
IN/OUT
pin is 2.42V. This is the reference voltage used
for the ADCs in the ADE7753. However, Channel 1 has
three input range selections which are selected by dividing
down the reference value used for the ADC in Channel 1. The
reference value used for Channel 1 is divided down to ½ and
¼ of the nominal value by using an internal resistor divider
as shown in Figure 20.
PTAT 60µA
1.7kΩ
12.5kΩ
12.5kΩ
12.5kΩ
12.5kΩ
2.5V
2.42V
REF
IN/OUT
Reference input to ADC
Channel 1 (Range Select)
2.42V, 1.21V, 0.6V
Maximum
Load = 10µA
Output
Impedance
6kΩ
Figure 20 —ADE7753 Reference Circuit Ouput
The REF
IN/OUT
pin can be overdriven by an external source,
e. g. , an ext ernal 2. 5V reference. Not e t hat t he nominal
reference value supplied to the ADCs is now 2.5V not 2.42V.
This has the effect of increasing the nominal analog input
signal range by 2. 5/2. 42×100% = 3% or from 0. 5V t o
0. 5165V.
T he volt age of ADE7753 r efer ence dr ift s slight ly wit h
temperature—see ADE7753 Specifications for the temperature
coefficient specificat ion (in ppm/°C) . T he value of t he
temperature drift varies from part to part. Since the reference
is used for the ADCs in both Channel 1 and 2, any x% drift
in the reference will result in 2x% deviation of the meter
accuracy. T he reference drift result ing from t emperat ure
changes is usually very small and it is typically much smaller
than the drift of other components on a meter. However, if
guaranteed temperature performance is needed, one needs to
use an external voltage reference. Alternatively, the meter can
be calibrated at multiple temperatures. Real time compensa-
tion can be easily achieved using the on the on-chip temperature
sensor.
CHANNEL 1 ADC
Figure 21 shows the ADC and signal processing chain for
Channel 1. In waveform sampling mode the ADC outputs a
signed 2’s Complement 24-bit data word at a maximum of
27.9kSPS (CLKIN/128). With the specified full scale ana-
log input signal of 0.5V (or 0.25V or 0.125V – see Analog
Inputs section) the ADC will produce an output code which is
approximat ely bet ween 2851ECh ( +2, 642, 412 Decimal)
and D7AE14h (-2,642,412 Decimal). This is illustrated in
Figure 21.
Channel 1 Sampling
The waveform samples may also be routed to the WAVE-
FORM regist er (MODE[14:13] = 1,0) t o be read by t he
syst em mast er (MCU). In waveform sampling mode t he
WSMP bit (bit 3) in the Interrupt Enable register must also
be set to logic one. The Active, Apparent Power and Energy
calculation will remain uninterrupted during waveform sam-
plin g.
When in waveform sample mode, one of four output sample
rates may be chosen by using bits 11 and 12 of the Mode
regist er (WAVSEL1, 0). T he out put sample rat e may be
27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—see Mode Register.
T he int errupt request out put IRQ signals a new sample
ADE7753
–16– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
availabilit y by going act ive low. T he t iming is shown in
Figure 22. T he 24-bit waveform samples are t ransferred
from the ADE7753 one byte (8-bits) at a time, with the most
significant byte shifted out first. The 24-bit data word is right
justified - see ADE7753 Serial Interface.

0 0 0 01 Hex
IRQ
DIN
DOUT
SCLK
Read from WAVEFORM
Channel 1 DATA - 24 bits
Sign
Figure 22 – Waveform sampling Channel 1
The interrupt request output IRQ stays low until the interrupt
routine reads the Reset Status register - see ADE7753 Interrupt.
Channel 1 RMS calculation
Root Mean Square (RMS) value of a continuous signal V(t)
is defined as:
( )

⋅ ·
T
rms
dt t V
T
V
0
2
1
(1)
For time sampling signals, rms calculation involves squaring
the signal, taking the average and obtaining the square root:

·
⋅ ·
N
i
rms
i V
N
V
1
2
) (
1
(2)
ADE7753 calculat es simult aneously t he RMS values for
Channel 1 and Channel 2 in different register. Figure 23
shows the detail of the signal processing chain for the RMS
calculat ion on channel 1. T he channel 1 RMS value is
processed from the samples used in the channel 1 waveform
sampling mode. The channel 1 RMS value is stored in an
unsigned 24-bit register (IRMS). One LSB of the channel 1
HPF V1P
V1N
ADC 1 PGA1
x1, x2, x4,
x8, x16
REFERENCE
2.42V, 1.21V, 0.6V
V1
0V
Analog
Input
Range
0.5V, 0.25V,
0.125V, 62.5mV,
31.3mV, 15.6mV,
V1
000000h
2851ECh
D7AE14h
ADC Output
word Range 000000h
2851ECh
D7AE14h
Channel 1 (Current Waveform)
Data Range
ACTIVE AND REACTIVE
POWER CALCULATION
WAVEFORM SAMPLE
REGISTER
GAIN[2:0]
GAIN[4:3]
000000h
1EF73Ch
E108C4h
Channel 1 (Current Waveform)
Data Range After integrator (50Hz)
DIGITAL
INTEGRATOR*
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED
DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE
FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.

000000h
19CE08h
E631F8h
Channel 1 (Current Waveform)
Data Range After Integrator (60Hz)
50Hz
60Hz
CURRENT RMS (IRMS)
CALCULATION
Figure 21 —ADC and signal processing in Channel 1
RMS regist er is equivalent t o one LSB of a channel 1
waveform sample. The update rate of the channel 1 RMS
measurement is CLKIN/4.
24
LPF3
Current Signal - i(t)
2851ECh
D7AE14h
00h
I
rms
(t)
1C82B3h
00h
IRMS Channel 1
Σ
+
SIGN 2
25
2
26
2
27
2
17
2
16
2
15
IRMSOS[11:0]
24
HPF
Figure 23 - Channel 1 RMS signal processing
With the specified full scale analog input signal of 0.5V, the
ADC will produce an output code which is approximately
±2,642,412d—see Channel 1 ADC. The equivalent RMS val-
ues of a full-scale AC signal is 1,868,467d (1C82B3h).
Channel 1 RMS offset compensation
The ADE7753 incorporates a channel 1 RMS offset compen-
sat ion regist er (IRMSOS). T his is 12-bit signed regist ers
which can be used to remove offset in the channel 1 RMS
calculation. An offset may exist in the RMS calculation due
to input noises that are integrated in the DC component of
V
2
(t). The offset calibration will allow the content of the
IRMS register to be maintained at zero when no input is
present on channel 1.
1 LSB of the Channel 1 RMS offset are equivalent to 32,768
LSB of the square of the Channel 1 RMS register. Assuming
that the maximum value from the Channel 1 RMS calcula-
tion is 1,868,467d with full scale AC inputs, then 1 LSB of
the channel 1 RMS offset represents 0.46% of measurement
error at -60dB down of full scale.
32768
2
0
× + · IRMSOS I I
rms rms
where I
rmso
is the RMS measurement without offset correc-
t ion.
ADE7753
–17–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
directly to the multiplier and is not filtered. A HPF is not
required to remove any DC offset since it is only required to
remove the offset from one channel to eliminate errors due to
offsets in the power calculation. When in waveform sample
mode, one of four output sample rates can be chosen by using
bits 11 and 12 of the Mode register. The available output
sample rates are 27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—
see Mode Register. The interrupt request output IRQ signals a
sample availability by going active low. The timing is the
same as that for Channel 1 and is shown in Figure 22.
Channel 2 RMS calculation
Figure 26 shows the details of the signal processing chain for
the RMS calculation on Channel 2. The channel 2 RMS
value is processed from the samples used in the channel 2
waveform sampling mode. The RMS value will be slightly
attenuated because of LPF1. Channel 2 RMS value is stored
in the unsigned 24-bit VRMS register. The update rate of the
channel 2 RMS measurement is CLKIN/4.
With the specified full scale AC analog input signal of 0.5V,
t he out put s from t he LPF1 swings bet ween 2518h and
DAE8h at 60 Hz- see Channel 2 ADC. The equivalent RMS
value of this full-scale AC signal is approximately 1,561,400
(17D338h) in the VRMS register.
LPF3
Voltage Signal - V(t)
2518h
0h
DAE8h
VRMS[23:0]
17D338h
00h
Channel 2
LPF1
S
+
SGN 2
9
2
8
2
2
2
1
2
0
VRMSOS[11:0]
+
Figure 26 - Channel 2 RMS signal processing
Channel 2 RMS offset compensation
The ADE7753 incorporates a channel 2 RMS offset compen-
sation register (VRMSOS). This is a 12-bit signed registers
which can be used to remove offset in the channel 2 RMS
calculation. An offset may exist in the RMS calculation due
to input noises and dc offset in the input samples. The offset
calibration allows the contents of the VRMS register to be
maintained at zero when no voltage is applied.
1 LSB of the channel 2 RMS offset are equivalent to 1 LSB
of the RMS register. Assuming that the maximum value from
the channel 2 RMS calculation is 1,561,400d with full scale
AC inputs, then 1 LSB of the channel 2 RMS offset represents
0.064% of measurement error at -60dB down of full scale.
VRMSOS V V
rmso rms
+ ·
where V
rmso
is the RMS measurement without offset correc-
t ion.
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel
1 and Channel 2 is zero from DC to 3.5kHz. When HPF is
enabled, Channel 1 has a phase response illust rat ed in
Figures 28 & 29. Also shown in Figure 30 is the magnitude
response of the filter. As can be seen from the plots, the phase
response is almost zero from 45Hz to 1kHz, This is all that
is required in t ypical energy measurement applicat ions.
CHANNEL 2 ADC
Channel 2 Sampling
In Channel 2 waveform sampling mode (MODE[14:13] =
1, 1 and WSMP = 1) t he ADC out put code scaling for
Channel 2 is not the same as Channel 1. Channel 2 waveform
sample is a 16-bit word and sign extended to 24 bits. For
normal operat ion, t he different ial volt age signal bet ween
V2P and V2N should not exceed 0. 5V. Wit h maximum
voltage input (±0.5V at PGA gain of 1), the outputs from the
ADC swings bet ween 2852h and D7AEh (±10,322 Deci-
mal). However, before being passed to the Waveform register,
the ADC output is passed through a single pole, low pass
filter with a cutoff frequency of 140Hz. The plots in Figure
24 shows the magnitude and phase response of this filter.
10
1
10
2
10
3
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
G
a
i
n

(
d
B
s
)
P
h
a
s
e

(
°
)
Frequency (Hz)
60 Hz, -0.73dB
50 Hz, -0.52dB
60 Hz, -23.2°
50 Hz, -19.7°
Figure 24 – Magnitude & Phase response of LPF1
T he LPF1 has t he effect of at t enuat ing t he signal. For
example if the line frequency is 60Hz, then the signal at the
output of LPF1 will be attenuated by about 8%.
( )
0.73dB 0.919
140Hz
60Hz
1
1
H(f)
2
− · ·
+
·
Note LPF1 does not affect the power calculation. The signal
processing chain in Channel 2 is illustrated in Figure 25.
V2P
V2N
ADC 2 PGA2
x1, x2, x4,
x8, x16
REFERENCE
GAIN[7:5]
V2
V1
0V
Analog
Input Range
ACTIVE AND REACTIVE
ENERGY CALCULATION
LPF1
0000h
2852h
D7AEh
LPF Output
word Range
VRMS CALCULATION
AND WAVEFORM
SAMPLING
(PEAK/SAG/ZX)
2518h
DAE8h
0.5V, 0.25V, 0.125V,
62.5mV, 31.25mV
2.42V
Figure 25 – ADC and Signal Processing in Channel 2
Unlike Channel 1, Channel 2 has only one analog input range
(1V differential). However like Channel 1, Channel 2 does
have a PGA with gain selections of 1, 2, 4, 8 and 16. For
energy measurement , t he out put of t he ADC is passed
ADE7753
–18– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
However, despit e being int ernally phase compensat ed t he
ADE7753 must work wit h t ransducers which may have
inherent phase errors. For example a phase error of 0.1° to
0.3° is not uncommon for a CT (Current Transformer).
These phase errors can vary from part to part and they must
be corrected in order to perform accurate power calculations.
The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE7753 provides a
means of digitally calibrating these small phase errors. The
ADE7753 allows a small time delay or time advance to be
int roduced int o t he signal processing chain in order t o
compensate for small phase errors. Because the compensa-
tion is in time, this technique should only be used for small
phase errors in the range of 0.1° to 0.5°. Correcting large
phase errors using a t ime shift t echnique can int roduce
significant phase errors at higher harmonics.
T he Phase Calibr at ion r egist er ( PHCAL[ 5:0] ) is a 2’s
complement signed single byt e regist er which has values
ranging from 21h (-31 in Decimal) to 1Fh (31 in Decimal).
The register is centered at 0Dh, so that writing 0Dh to the
register gives zero delay. By changing the PHCAL register,
the time delay in the Channel 2 signal path can change from
–100.8µs to +33.6µs (CLKIN = 3.579545MHz). One LSB
is equivalent to 2.22µs time delay or advance. With a line
frequency of 60Hz this gives a phase resolution of 0.048° at
t he fundament al (i.e., 360° × 2.22µs × 60Hz). Figure 27
illustrates how the phase compensation is used to remove a
0.1° phase lead in Channel 1 due to the external transducer.
In order to cancel the lead (0.1°) in Channel 1, a phase lead
must also be introduced into Channel 2. The resolution of the
phase adjustment allows the introduction of a phase lead in
increment of 0.048°. The phase lead is achieved by introduc-
ing a time advance into Channel 2. A time advance of 4.48µs
is made by writing -2 (0Bh) to the time delay block, thus
reducing the amount of time delay by 4.48µs, or equivalently,
a phase lead of approximately 0.1° at line frequency of 60Hz.
0Bh represents -2 because the register is centered with zero
at 0Dh.
0
0 0 1 1 0 1
5
V2P
V2N
ADC 2 PGA2
1
V2
24
LPF2
HPF V1P
V1N
ADC 1 PGA1 V1
24
PHCAL[5:0]
Delay Block
4.48µs / LSB
-100µs to +34µs
V1
V2
60Hz
Channel 2 delay
reduced by 4.48µs
(0.18lead at 60Hz)
0Bh in PHCAL[5:0]
V2
V1
0.18
60Hz
Figure 27 – Phase Calibration
10
2
10
3
10
4
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
FREQUENCY-Hz
P
H
A
S
E
-
D
E
G
R
E
E
S
Figure 28 – Combined Phase Response of the HPF & Phase
Compensation (10Hz to 1kHz)
40 45 50 55 60 65 70
-0.2
-0.15
-0.1
-0.05
0.05
0.1
0.15
0.2
FREQUENCY-Hz
P
H
A
S
E
-
D
E
G
R
E
E
S
Figure 29 – Combined Phase Response of the HPF & Phase
Compensation (40Hz to 70Hz)
40 45 50 55 60 65 70
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
FREQUENCY-Hz
G
A
IN
-
d
B
Figure 30 – Combined Gain Response of the
HPF & Phase Compensation
ACTIVE POWER CALCULATION
Power is defined as the rate of energy flow from source to
load. It is defined as the product of the voltage and current
waveforms. The resulting waveform is called the instanta-
neous power signal and it is equal to the rate of energy flow
at every instant of time. The unit of power is the watt or joules/
ADE7753
–19–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
sec. Equat ion 3 gives an expression for t he inst ant aneous
power signal in an ac system.
() ( )
t V t v ω sin 2 ·
(1)
() ( )
t I t i ω sin 2 ·
(2)
where V = rms voltage,
I = rms current.
() () ()
() ( )
t t p
t i t v t p
ω cos VI VI − ·
× ·
(3)
The average power over an integral number of line cycles (n)
is given by the expression in Equation 4.
( )
0
1 nT
P p t dt VI
nT
· ·

(4)
where T is the line cycle period.
P is referred to as the Active or Real Power. Note that the
active power is equal to the dc component of the instanta-
neous power signal p( t) in Equation 3 , i.e., VI. This is the
relationship used to calculate active power in the ADE7753.
The instantaneous power signal p( t) is generated by multiply-
ing the current and voltage signals. The dc component of the
instantaneous power signal is then extracted by LPF2 (Low
Pass Filt er) t o obt ain t he act ive power informat ion. This
process is illustrated graphically in Figure 31.
Voltage
Current
Instantaneous
Power Signal
Active Real Power
Signal = V x I
V. I.
00000h
19999Ah
CCCCDh
v(t) = √2×V×sin(ωt)
i(t) = √2×I×sin(ωt)
p(t) = V×I-V×I×cos(2ωt)
Figure 31– Active Power Calculation
Since LPF2 does not have an ideal “brick wall” frequency
response—see Figure 32, the Active Power signal will have
some ripple due t o t he inst ant aneous power signal. T his
ripple is sinusoidal and has a frequency equal to twice the line
frequency. Since the ripple is sinusoidal in nature it will be
removed when t he Act ive Power signal is int egrat ed t o
calculate Energy – see Energy Calculation.
Frequency
1.0Hz 3.0Hz 10Hz 30Hz 100Hz
-24
-20
-16
-12
-8
-4
0
d
B
s
Figure 32 —Frequency Response of LPF2
F igur e 33 shows t he signal pr ocessing chain for t he
ActivePower calculation in the ADE7753. As explained, the
Active Power is calculated by low pass filtering the instanta-
neous power signal. Note that for when reading the waveform
samples from the output of LPF2,
The gain of the Active Energy can be adjusted by using the
mult iplier and Wat t Gain regist er ( WGAIN[11:0]) . T he
gain is adjusted by writing a 2’s complement 12-bit word to
the Watt Gain register. Below is the expression that shows
how the gain adjustment is related to the contents of the Watt
Gain regist er.

,
_

¸
¸
¹
;
¹
¹
'
¹
+ × ·
12
2
1
WGAIN
Power Active WGAIN Output
For example when 7FFh is written to the Watt Gain register
t he Power out put is scaled up by 50%. 7FFh = 2047d,
2047/2
12
= 0.5. Similarly, 800h = -2048 Dec (signed 2’s
Complement) and power output is scaled by –50%.
Shown in Figure 34 is the maximum code (in hex) output
range for t he Act ive Power signal (LPF2). Not e t hat t he
output range changes depending on the contents of the Watt
Gain register. The minimum output range is given when the
Wat t Gain regist er cont ent s are equal t o 800h, and t he
HPF
LPF2
Current Signal - i(t)
Voltage Signal - v(t)
Instantaneous
Power Signal - p(t)
MULTIPLIER
Active Power
Signal - P
CCCCDh
I
V
19999Ah
000000h
WGAIN[11:0]
Σ
+
2
-6
2
-7
APOS[15:0]
sgn
2
-8
2
6
2
5
32 24
+ For Energy
Accumulation
For Waveform
Sampling
19999h
24
Figure 33– Active Power Signal Processing
ADE7753
–20– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ENERGY CALCULATION
As stated earlier, power is defined as the rate of energy flow.
T his r elat ionship can be expr essed mat hemat ically as
Equation 5.
P =
dE
dt
(5)
Where P = Power and E = Energy.
Conversely Energy is given as the integral of Power.

· Pdt E ( 6)
The ADE7753 achieves the integration of the Active Power
signal by continuously accumulating the Active Power signal
in an int ernal non-readable 56-bit Energy regist er. T he
Act ive Energy regist er (AENERGY[23:0]) represent s t he
upper 24 bit s of t his int ernal regist er. This discret e t ime
accumulation or summation is equivalent to integration in
continuous time. Equation 7 below expresses the relationship
¹
;
¹
¹
'
¹
× · ·



· →
1 0
) ( ) (
n t
T nT p dt t p E
Lim ( 7)
Where n is the discrete time sample number and T is the
sample period.
4
CLKIN
time (nT)
WAVEFORM
REGISTER
VALUES
O
U
T
P
U
T
L
P
F
2
T
LPF2
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL ACTIVE ENERGY REGISTER
+
+
Σ
Active Power
Signal - P*
Current Channel
Voltage Channel
APOS [15:0]
46 0
AENERGY[23:0]
WDIV[7:0]
23 0
WGAIN[11:0]
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
AENERGY[23:0] REGISTER
Figure 35 – ADE7753 Active Energy Calculation
The discrete time sample period (T) for the accumulation
regist er in t he ADE7753 is 1.1µs (4/CLKIN). As well as
calculating the Energy this integration removes any sinusoi-
dal components which may be in the Active Power signal.
Figure 35 shows a graphical representation of this discrete
time integration or accumulation. The Active Power signal
in the Waveform register is continuously added to the internal
Active Energy register. This addition is a signed addition,
therefore negative energy will be subtracted from the Active
Energy cont ent s.
The output of the multiplier is divided by WDIV. If the value
in the WDIV register is equal to 0 then the internal Active
Energy register is divided by 1. WDIV is an 8-bit unsigned
r egist er . Aft er dividing by WDI V, t he act ive ener gy is
accumulated in a 48-bit internal energy accumulation regis-
ter. The upper 24 bit of this register is accessible through a
read t o t he Act ive Energy regist er (AENERGY[23:0]). A
read to the RAENERGY register will return the content of
the AENERGY register and the upper 24-bit of the internal
register is clear after a read to AENERGY register.
As shown in Figure 35, the Active Power signal is accumu-
lat ed in an int er nal 48- bit signed r egist er .
The Active Power signal can be read from the Waveform
regist er by set t ing MODE[14:13] = 0, 0 and set t ing t he
WSMP bit (bit 3) in the Interrupt Enable register to 1. Like
the Channel 1 and Channel 2 waveform sampling modes the
waveform dat e is available at sample rat es of 27. 9kSPS,
14kSPS, 7kSPS or 3.5kSPS—see Figure 22.
Figure 36 shows t his energy accumulat ion for full scale
signals (sinusoidal) on the analog inputs. The three curves
displayed, illustrate the minimum period of time it takes the
energy regist er t o roll-over when t he Act ive Power Gain
register contents are 7FFh, 000h and 800h. The Watt Gain
register is used to carry out power calibration in the ADE7753.
As shown, the fastest integration time will occur when the
Watt Gain register is set to maximum full scale, i.e., 7FFh.
00,0000h
7F,FFFFh
80,0000h
3F,FFFFh
40,0000h
AENERGY[23:0]
Time
(minutes)
WGAIN = 7FFh
WGAIN = 000h
WGAIN = 800h
6.2 12.5 4 8
Figure 36 - Energy register roll-over time for full-scale
power (Minimum & Maximum Power Gain)
Note that the energy register contents will roll over to full-
scale negative (800000h) and continue increasing in value
when the power or energy flow is positive - see Figure 36.
Conversely if the power is negative the energy register would
under flow to full scale positive (7FFFFFh) and continue
decreasing in value.
By using the Interrupt Enable register, the ADE7753 can be
configured t o issue an int errupt ( IRQ) when t he Act ive
Energy register is half-full (positive or negative) or when an
over/under flow occurs.
Integration time under steady load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1µs (4/CLKIN).
maximum range is given by writing 7FFh to the Watt Gain
register. This can be used to calibrate the Active Power (or
Energy) calculation in the ADE7753.
00000h
CCCCDh
F33333h
WGAIN[11:0]
000h 7FFh 800h
Active Power
Calibration Range
Positive
Power
Negative
Power
A
c
t
i
v
e

P
o
w
e
r

O
u
t
p
u
t
66666h
F9999Ah
133333h
ECCCCDh
Figure 34 – Active Power Calculation Output Range
ADE7753
–21–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
POWER OFFSET CALIBRATION
T he ADE7753 also incorporat es an Act ive Power Offset
register (APOS[15:0]). This is a signed 2’s complement 16-
bit register which can be used to remove offsets in the active
power calculation—see Figure 33. An offset may exist in the
power calculation due to cross talk between channels on the
PCB or in the IC itself. The offset calibration will allow the
contents of the Active Power register to be maintained at zero
when no power is being consumed.
Two hundred fifty six LSBs (APOS=0100h) written to the
Active Power Offset register are equivalent to 1 LSB in the
Waveform Sample regist er. Assuming t he average value
outputs from LPF2 is CCCCDh (838,861 in Decimal) when
inputs on Channels 1 and 2 are both at full-scale. At -60dB
down on Channel 1 (1/1000 of t he Channel 1 full-scale
input), the average word value outputs from LPF2 is 838.861
(838,861/1,000). 1 LSB in the LPF2 output has a measure-
ment error of 1/838.861 × 100% = 0.119% of the average
value. T he Act ive Power Offset regist er has a resolut ion
equal t o 1/256 LSB of t he Waveform regist er, hence t he
power offset correction resolution is 0.00047%/LSB (0.119%/
256) at -60dB.
ENERGY TO FREQUENCY CONVERSION
ADE7753 also provides energy to frequency conversion for
calibration purposes. After initial calibration at manufactur-
ing, the manufacturer or end customer will often verify the
energy meter calibration. One convenient way to verify the
meter calibration is for the manufacturer to provide an output
frequency which is proportional to the energy or active power
under st eady load condit ions. This out put frequency can
provide a simple, single wire, optically isolated interface to
ext ernal calibrat ion equipment . Figure 37 illust rat es t he
Energy-t o-Frequency conversion in t he ADE7753.
CF
0 11
CFNUM[11:0]
Energy
0 11 CFDEN[11:0]
DFC
0 23 AENERGY[23:0]
Figure 37– ADE7753 Energy to Frequency Conversion
A Digital to Frequency Converter (DFC) is used to generate
the CF pulsed output. The DFC generates a pulse each time
one LSB in the Active Energy register is accumulated. An
output pulse is generated when (CFDEN+1)/(CFNUM+1)
number of pulses are generated at the DFC output. Under
steady load conditions the output frequency is proportional to
the Active Power.
The maximum output frequency, with AC input signals at
full-scale and CFNUM=00h & CFDEN=00h, is approxi-
mately 23 kHz.
T he ADE7753 incorporat es t wo regist ers, CFNUM[11:0]
and CFDEN[11:0], t o set t he CF frequency. T hese are
unsigned 12-bit registers which can be used to adjust the CF
frequency to a wide range of values. These frequency scaling
regist ers are 12-bit regist ers which can scale t he out put
frequency by 1/2
12
to 1 with a step of 1/2
12
.
If the value zero is written to any of these registers, the value
one would be applied to the register. The ratio (CFNUM+1)/
(CFDEN+1) should be smaller than one to assure proper
oper at ion . I f t he r at io of t he r egist er s ( CF NUM+ 1) /
(CFDEN+1) is greater than one, the register values would
be adjust to a ratio (CFNUM+1)/(CFDEN+1) of one.
For example if the output frequency is 1.562kHz while the
contents of CFDENare zero (000h), then the output frequency
can be set to 6.1Hz by writing FFh to the CFDEN register.
Not e t hat for valu es wher e CF DEN> CF NUM, t he
performance of the CF frequency is not guaranteed. CFNUM
should always be set to a value less than CFDEN.
The output frequency will have a slight ripple at a frequency
equal to twice the line frequency. This is due to imperfect
filtering of the instantaneous power signal to generate the
Active Power signal – see Active Power Calculation. Equation 3
gives an expression for the instantaneous power signal. This
is filtered by LPF2 which has a magnitude response given by
Equation 9.
2
2
9 . 8
1
1
) (
f
f H
+
·
( 9)
The Active Power signal (output of LPF2) can be rewritten
as.

( )
t f
f
VI
VI t p
l
l
π 4 cos
9 . 8
2
1
) (
2

¹
¹
¹
¹
¹
;
¹
¹
¹
¹
¹
¹
'
¹

,
_

¸
¸
+
− ·
(10)
where fl is the line frequency (e.g., 60Hz)
From Equation 6

( )
t f
f
f
VI
VIt t E
l
l
l
π
π
4 sin
9 . 8
2
1 4
) (
2

¹
¹
¹
¹
¹
;
¹
¹
¹
¹
¹
¹
'
¹

,
_

¸
¸
+
− ·
(11)
From Equation 11 it can be seen that there is a small ripple
in the energy calculation due to a sin(2ωt) component. This
is shown gr aphically in Figur e 38. T he Act ive Ener gy
calculation is shown by the dashed straight line and is equal
With full-scale sinusoidal signals on the analog inputs and the
WGAIN register set to 000h, the average word value from
each LPF2 is CCCCDh - see Figure 31. T he maximum
posit ive value which can be st ored in t he int ernal 47-bit
register is 2
46
- 1 or 7FFF,FFFF,FFFFh before it overflows,
the integration time under these conditions with WDIV=0 is
calculated as follows:
s s s µ
CCCCDh
FFFFh FFFF FFF
Time min 12 . 3 = 5 . 187 = 12 . 1 ×
, , 3
=
When WDIV is set to a value different from 0, the integration
time varies as shown on Equation 8.
Time = Time
WDIV=0
x WDIV (8)
ADE7753
–22– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
t o V x I x t . The sinusoidal ripple in t he Act ive Energy
calculat ion is also shown. Since t he average value of a
sinusoid is zero, this ripple will not contribute to the energy
calculation over time. However, the ripple can be observed
in the frequency output, especially at higher output frequen-
cies. T he r ipple will get lar ger as a per cent age of t he
frequency at larger loads and higher output frequencies. The
reason is simply that at higher output frequencies the integra-
tion or averaging time in the Energy-to-Frequency conversion
process is shorter. As a consequence some of the sinusoidal
ripple is observable in t he frequency out put . Choosing a
lower output frequency at CF for calibration can significantly
reduce the ripple. Also averaging the output frequency by
using a longer gate time for the counter will achieve the same
result s.
t
E(t)

R
S
T
U
V
W
VI
4. (1+ 2. / 8.9Hz)
sin(4.
F
F
.
. . )
f f
f t
l l
l
VIt
Figure 38 – Output frequency ripple
LINE CYCLE ENERGY ACCUMULATION MODE
I n Line Cycle Ener gy Accumulat ion mode, t he ener gy
accumulation of the ADE7753 can be synchronized to the
Channel 2 zero crossing so that active energy can be accumu-
lat ed over an int egr al number of half line cycles. T he
advant age of summing t he act ive energy over an int eger
number of half line cycles is that the sinusoidal component
in the active energy is reduced to zero. This eliminates any
ripple in the energy calculation. Energy is calculated more
accurately and in a shorter time because integration period
can be shortened. By using the line cycle energy accumula-
tion mode, the energy calibration can be greatly simplified
and the time required to calibrate the meter can be signifi-
cantly reduced. The ADE7753 is placed in line cycle energy
accumulat ion mode by set t ing bit 7 (CYCMODE) in t he
Mode register. In Line Cycle Energy Accumulation Mode
t he ADE7753 accumulat es t he act ive power signal in t he
LAENERGY register (Address 04h) for an integral number
of line cycles, as shown in Figure 39. The number of half line
cycles is specified in the LINECYC register (Address 1Ch).
The ADE7753 can accumulate active power for up to 65,535
half line cycles. Because the active power is integrated on an
integral number of line cycles, at the end of a line cycle energy
accumulation cycle the CYCEND flag in the Interrupt Status
regist er is set (bit 2). If t he CYCEND enable bit in t he
Interrupt Enable register is enabled, the IRQ output will also
go active low. Thus the IRQ line can also be used to signal
the completion of the line cycle energy accumulation. An-
other calibration cycle will start as long as the CYCMODE
bit in the Mode register is set. Note that the result of the first
calibration is invalid and should be ignored. The result of all
subsequent line cycle accumulation is correct.
From Equations 6 and 10.
( )
∫ ∫

¹
¹
¹
¹
¹
;
¹
¹
¹
¹
¹
¹
'
¹

,
_

¸
¸
+
− ·
nT nT
dt t f
f
VI
dt VI t E
0
2
0
2 cos
9 . 8
1
) ( π
(12)
where n is a integer and T is the line cycle period. Since the
sinusoidal component is integrated over a integer number of
line cycles its value is always zero.
T her efor e:

+ ·
nT
VIdt E
0
0
( 13)
E(t) VInT
· ( 14)

+
+
Σ
CALIBRATION
CONTROL
LINECYC[14:0]
Output from
LPF2
LPF1
FROM
CHANNEL 2
ADC
ZERO CROSS
DETECTION
ACCUMULATE ACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LAENERGY REGISTER
AT THE END OF LINECYC
LINE-CYCLES
46
0
LAENERGY[23:0]
WDIV[7:0]
23 0
Figure 39 – Energy Calculation in Line Cycle Energy Accu-
mulation Mode
Note that in this mode, the 16-bit LINECYC register can
hold a maximum value of 65,535. In other words, the line
energy accumulation mode can be used to accumulate active
energy for a maximum duration over 65,535 half line cycles.
At 60Hz line frequency, it translates to a total duration of
65,535 / 120Hz = 546 seconds.
POSITIVE ONLY ACCUMULATION MODE
In Positive Only Accumulation mode, the energy accumula-
tion is done only for positive power, ignoring any occurrence
of negative power above or below the no load threshold as
shown in Figure 40. The ADE7753 is placed in positive only
Active Power
IRQ
Active Energy
PNEG PPOS PNEG
Interrupt Status Registers
No-load
threshold
No-load
threshold
PNEG PPOS PPOS
Figure 40 – Energy Accumulation in Positive Only
Accumulation Mode
ADE7753
–23–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
accumulat ion mode by set t ing t he MSB of t he MODE
register (MODE[15]). The default setting for this mode is
off. Transitions in the direction of power flow, going from
negative to positive or positive to negative, set the IRQ pin
to active low if the Interrupt Enable register is enabled. The
Interrupt Status Registers, PPOS and PNEG, show which
transition has occurred. See ADE7753 Register Descriptions.
NO LOAD THRESHOLD
The ADE7753 includes a "no load threshold" feature that will
eliminat e any creep effect s in t he met er. The ADE7753
accomplishes this by not accumulating energy if the multi-
plier output is below the "no load threshold". This threshold
is 0.001% of the full-scale output frequency of the multiplier.
Compare this value to the IEC1036 specification which states
that the meter must start up with a load equal to or less than
0.4% Ib. This standard translates to .0167% of the full-scale
output frequency of the multiplier.
REACTIVE POWER CALCULATION
Reactive power is defined as the product of the voltage and
current waveforms when one of this signal is phase shifted by
90º. T he result ing waveform is called t he inst ant aneous
reactive power signal. Equation 17 gives an expression for the
instantaneous reactive power signal in an ac system when the
phase of the current channel is shifted by +90º.
) sin( 2 ) ( θ ω + · t V t v
(15)
) t sin( I ) t ( ' i ) t sin( I ) t ( i
2
2 2
π
+ ω · ω ·
(16)
Where θ is t he phase difference bet ween t he volt age and
current channel, V = rms voltage and I = rms current.
) ( ' ) ( ) ( t i t v t Rp × ·
) 2 sin( ) sin( ) ( θ ω θ + + · t VI VI t Rp (17)
The average power over an integral number of line cycles (n)
is given by the expression in Equation 18.

· ·
nT
VI dt t Rp
nT
RP
0
) sin( ) (
1
θ
(18)
where T is the line cycle period.
RP is referred to as the Reactive Power. Note that the reactive
power is equal to the DC component of the instantaneous
react ive power signal Rp( t) in Equat ion 17. T his is t he
relationship used to calculate reactive power in the ADE7753.
The instantaneous reactive power signal Rp( t) is generated by
multiplying the channel 1 and channel 2. In this case, the
phase of the channel 1 is shifted by +90º. The DC component
of the instantaneous reactive power signal is then extracted by
a low pass filter to obtain the reactive power information.
Figure 41 shows the signal processing in the Reactive Power
calculation in the ADE7753.
+
+
Σ
CALIBRATION
CONTROL
LINECYC[14:0]
LPF1
FROM
CHANNEL 2
ADC
ZERO CROSS
DETECTION
ACCUMULATE ACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LVARENERGY
REGISTER AT THE END OF
LINECYC LINE CYCLES
47
0
LVARENERGY[23:0]
23 0
Instantaneous Reactive
Power Signal - Rp(t)
MULTIPLIER
90 DEGREE
PHASE SHIFT
I
Π
2
V
Figure 41 - Reactive Power Signal Processing
The features of the Reactive Energy accumulation are the
same as the Line Active Energy accumulation. The number
of half line cycles is specified in t he LINECYC regist er.
LINECYC is an unsigned 16-bit register. The ADE7754 can
accumulate Reactive Power for up to 65535 combined half
cycles. At the end of an energy calibration cycle the CYCEND
flag in the Interrupt Status register is set. If the CYCEND
mask bit in the Interrupt Mask register is enabled, the IRQ
output will also go active low. Thus the IRQ line can also be
used t o signal t he end of a calibrat ion. T he ADE7753
accumulates the Reactive Power signal in the LVARENERGY
register for an integer number of half cycles, as shown in
Figure 41.
The Reactive Energy accumulation in the ADE7753 not only
provides the reactive energy calculated using the phase shift
method, it is also useful to provide the sign of the reactive
power if it is desirable to use triangular method to calculate
react ive power. T he ADE7753 also provides an accurat e
measurement of the apparent power. The user can choose to
det ermine react ive energy t hrough t he mat hemat ical rela-
tionship between apparent, active and reactive power. The
sign of the reactive energy can be found by reading the result
from the LVARENERGY register at the end of a reactive
energy accumulat ion cycle.
2 2
) (Re
Re
Energy Active Energy Apparent Energy active sign
Energy active
− × ·
APPARENT POWER CALCULATION
Apparent power is defined as the amplitude of the vector sum
of the Active and Reactive powers -see Figure 42. The angle
θ between the Active Power and the Apparent Power generally
represent s t he phase shift due t o non-resist ive loads. For
single phase applications, θ represents the angle between the
voltage and the current signals. Equation 20 gives an expres-
sion of the instantaneous power signal in an ac system with a
phase shift.
ADE7753
–24– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Reactive
Power
Active
Power
Apparent
Power
θ
Figure 42 - Power triangle
( )
( ) θ ω
ω
+ ·
·
t t i
t t v
sin I 2 ) (
sin V 2 ) (
rms
rms
(19)
) 2 cos( ) cos( ) (
) ( ) ( ) (
θ ω θ + − ·
× ·
t I V I V t p
t i t v t p
rms rms rms rms
(20)
The Apparent Power (AP) is defined as V
rms
x I
rms
. This
expression is independent from the phase angle between the
current and the voltage.
Figure 43 illustrates graphically the signal processing in each
phase for t he calculat ion of t he Apparent Power in t he
ADE7753.
Current RMS Signal - i(t)
Voltage RMS Signal - v(t)
MULTIPLIER
Apparent Power
Signal - P
I
rms
V
rms
00h
00h
AD055h
VAGAIN
1C82B3h
17D338h
Figure 43 - Apparent Power Signal Processing
The gain of the Apparent Energy can be adjusted by using the
multiplier and VA Gain register (VAGAIN[11:0]). The gain
is adjusted by writing a 2’s complement, 12-bit word to the
VAGAIN register. Below is the expression that shows how
the gain adjustment is related to the contents of the VA Gain
r egist er .

,
_

¸
¸
¹
;
¹
¹
'
¹
+ × ·
12
2
1
VAGAIN
Power Apparent VAGAIN Output
For example when 7FFh is written to the VA Gain register
t he Power out put is scaled up by 50%. 7FFh = 2047d,
2047/2
12
= 0.5. Similarly, 800h = -2047 Dec (signed 2’s
Complement) and power output is scaled by –50%.
T he Apparent Power is calculat ed wit h t he Current and
Volt age RMS values obt ained in t he RMS blocks of t he
ADE7753. Shown in Figur e 44 is t he maximum code
(Hexadecimal) output range of the Apparent Power signal.
Note that the output range changes depending on the contents
of the Apparent Power Gain registers. The minimum output
range is given when t he Apparent Power Gain regist er
content is equal to 800h and the maximum range is given by
writing 7FFh to the Apparent Power Gain register. This can
be used to calibrate the Apparent Power (or Energy) calcu-
lation in the ADE7753 -see Apparent Power calculation.
00000h
AD055h
103880h
5682Bh
VAGAIN[11:0]
000h 7FFh 800h
Apparent Power
Calibration Range
Apparent Power 100% FS
Apparent Power 150% FS
Apparent Power 50% FS
Voltage and Current channel inputs: 0.5V / GAIN
Figure 44- Apparent Power Calculation Output range
Apparent Power Offset Calibration
Each RMS measurement includes an offset compensat ion
register to calibrate and eliminate the DC component in the
RMS value -see Channel 1 RMS calculation and Channel 2 RMS
calculation. The channel 1 and channel 2 RMS values are then
multiplied together in the Apparent Power signal processing.
As no additional offsets are created in the multiplication of
the RMS values, there is no specific offset compensation in
the Apparent Power signal processing. The offset compensa-
tion of the Apparent Power measurement is done by calibrating
each individual RMS measurements.
APPARENT ENERGY CALCULATION
The Apparent Energy is given as the integral of the Apparent
Power .
dt t Power Apparent Energy Apparent

· ) ( (21)
T he ADE7753 achieves t he int egrat ion of t he Apparent
Power signal by cont inuously accumulat ing t he Apparent
Power signal in an int ernal 48-bit regist er. The Apparent
Energy regist er (VAENERGY[23:0]) represent s t he upper
24 bits of this internal register. This discrete time accumu-
lation or summation is equivalent to integration in continuous
time. Equation 23 below expresses the relationship

¹
;
¹
¹
'
¹
× ·


·

0
0
) (
n
T
T nT Power Apparent Lim Energy Apparent
(22)
Where n is the discrete time sample number and T is the
sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7753 is 1.1µs (4/CLKIN).
Figure 44 shows a graphical representation of this discrete
t ime int egrat ion or accumulat ion. T he Apparent Power
signal is continuously added to the internal register. This
addition is a signed addition even if the Apparent Energy
remains t heoret ically always posit ive.
ADE7753
–25–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
46
0
+
+
Σ
APPARENT POWER
00000h
AD055h
time (nT)
T
APPARENT POWER ARE
ACCUMULATED (INTEGRATED) IN
THE APPARENT ENERGY REGISTER
Apparent Power
Signal - P
T
47 0
VAENERGY[23:0]
VADIV
23
0
Figure 45- ADE7753 Apparent Energy calculation
T he upper 52-bit of t he int ernal regist er are divided by
VADIV. If the value in the VADIV register is equal to 0 then
the internal active Energy register is divided by 1. VADIV is
an 8-bit unsigned register. The upper 24-bit are then written
in the 24-bit Apparent Energy register (VAENERGY[23:0]).
RVAENERGY register (24 bits long) is provided to read the
Apparent Energy. This register is reset to zero after a read
operat ion.
Figure 45 shows this Apparent Energy accumulation for full
scale signals (sinusoidal) on t he analog input s. The t hree
curves displayed, illustrate the minimum time it takes the
energy regist er t o roll-over when t he VA Gain regist ers
content is equal to 7FFh, 000h and 800h. The VA Gain
register is used to carry out an apparent power calibration in
the ADE7753. As shown, the fastest integration time will
occur when the VA Gain register is set to maximum full scale,
i. e. , 7FFh.
40,0000h
FF,FFFFh
00,0000h
80,0000h
20,0000h
VAENERGY[23:0]
Time
(minutes)
VAGAIN = 7FFh
VAGAIN = 000h
VAGAIN = 800h
14.8
4.9 7.4 11.1
Figure 46- Energy register roll-over time for full-scale
power (Minimum & Maximum Power Gain)
Note that the Apparent Energy register contents roll-over to
full-scale negat ive (80, 0000h) and cont inue increasing in
value when the power or energy flow is positive - see Figure
46.
By using the Interrupt Enable register, the ADE7754 can be
configured to issue an interrupt (IRQ) when the Apparent
Energy register is half full (positive or negative) or when an
over/under flow occurs.
Integration times under steady load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1µs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 000h, the average word value from
Apparent Power stage is AD055h - see Apparent Power output
range. T he maximum value which can be st ored in t he
Apparent Energy regist er before it over-flows is 2
24
or
FF, FFFFh. As t he average word value is added t o t he
internal register which can store 2
48
- 1 or 7FFF,FFFF,FFFFh
before it overflows, the integration time under these condi-
tions with VADIV=0 is calculated as follows:
min 8 . 4 1 = s 88 8 = s 1.2 ×
AD055h
FFFFh FFFF, 7FFF,
= Time µ
When VADIV is set to a value different from 0, the integra-
tion time varies as shown on Equation 23.
Time = Time
WDIV=0
x VADIV (23)
LINE APPARENT ENERGY ACCUMULATION
The ADE7753 is designed with a special Apparent Energy
accumulation mode which simplifies the calibration process.
By using the on-chip zero-crossing detection, the ADE7753
accumulates the Apparent Power signal in the LVAENERGY
register for an integral number of half cycles, as shown in
Figure 47. The line Apparent energy accumulation mode is
always active.
The number of half line cycles is specified in the LINCYC
r egist er . LI NCYC is an unsigned 16-bit r egist er . T he
ADE7753 can accumulate Apparent Power for up to 65535
combined half cycles. Because the Apparent Power is inte-
grated on the same integral number of line cycles as the Line
Active Energy register, these two values can be compared
easily. The active and apparent Energy are calculated more
accurately because of this precise timing control and provide
all the information needed for Reactive Power and Power
Factor calculation. At the end of an energy calibration cycle
the CYCEND flag in the Interrupt Status register is set. If the
CYCEND mask bit in the Interrupt Mask register is enabled,
the IRQ output will also go active low. Thus the IRQ line can
also be used to signal the end of a calibration.
T he Line Apparent Energy accumulat ion uses t he same
signal path as the Apparent Energy accumulation. The LSB
size of these two registers is equivalent.
+
+
Σ
CALIBRATION
CONTROL
LINECYC[15:0]
Apparent Power
LVAENERGY REGISTER IS
UPDATED EVERY LINECYC
ZERO-CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
46
LVAENERGY[23:0]
VADIV[7:0]
23 0
LPF1
FROM
CHANNEL 2
ADC
ZERO
CROSSING
DETECTION
0
Figure 47 - ADE7753 Apparent Energy Calibration
ADE7753
–26– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
CALIBRATING THE ENERGY METER
When calibrating the ADE7753, the first step is to calibrate
the frequency on CF to some required meter constant, e.g.,
3200 imp/kWh.
A convenient way to to determine the output frequency on CF
is to use the line cycle energy accumulation mode. As shown
in Figure 37, DFC generates a pulse each time a LSB in the
LAENERGY register is accumulated. CF frequency (before
the CF frequency divider) can be conveniently determined by
t he following expression:
Time Elasped
r 0] Registe : 3 LAENERGY[2 of Content
Frequency CF ·
When the CYCMODE (bit 7) bit in the Mode register is set
to a logic one, energy is accumulated over an integer number
of half line cycles. If t he line frequency is fixed and t he
number of half cycles of integration is specified, the total
elasped time can be calculated by the following:
cycles half of number
f 2
1
Time Elasped
l
×
×
·
For example, at 60Hz line frequency, the elasped time for
255 half cycles will be 2.125 seconds. Rewriting the above in
t erms of cont ent s of various ADE7753 regist ers and line
frequencies (fl):
0] : LINECYC[15
fl 2 0] : 3 LAENERGY[2
Frequency CF
× ×
·
( 24)
where fl is the line frequency.
Alternatively, CF frequency can be calculated based on the
average LPF2 output.
27
2
CLKIN × Output LPF2 Average
= Frequency CF
( 25)
Calibrating the Frequency at CF
When the frequency before frequency division is known, the
pair of CF Fr equency Divider r egist er s ( CFNUM and
CFDEN) can be adjusted to produce the required frequency
on CF. In this example a meter constant of 3200 imp/kWh
is chosen as an appropriate constant. This means that under
a steady load of 1kW, the output frequency on CF would be,
Hz
kWh imp
CF Frequency 8888 . 0
3600
3200
sec 60 min 60
/ 3200
) ( · ·
×
·
Assuming t he met er is set up wit h a t est current (basic
current) of 20A and a line voltage of 220V for calibration, the
load is calculated as 220V × 20A = 4.4kW. Therefore the
expect ed out put frequency on CF under t his st eady load
condit ion would be 4. 4 × 0. 8888Hz = 3. 9111Hz.
Under these load conditions the transducers on Channel 1
and Channel 2 should be selected such that the signal on the
voltage channel should see approximately half scale and the
signal on the current channel about 1/8 of full scale (assuming
a maximum current of 80A). Assuming at line frequency of
60Hz, energy is accumulated over FFh number of half line
cycles, the resulting content of the LAENERGY register will
be approximately 2971.4 (decimal). CF frequency is there-
fore calculated to be:
1398.3Hz =
255
60 × 2 × 4 . 971 2
= (CF) Frequency
Alternatively, the average value from LPF2 under this con-
dit ion is appr oximat ely 1/16 of t he full-scale level. As
described previously, the average LPF2 output at full-scale
ac input is CCCCD (hex) or 838,861 (decimal). At 1/16 of
full-scale, the LPF2 output is then 52,428.81. Then using
Digital to Frequency Conversion, the frequency under this
load is calculated as:
Hz 3 . 398 1 =
2
z 3.579545MH × 52428.81
= CF) Frequency(
27
This is the frequency with the contents of the CFNUM and
CFDEN registers equal to 000h. The desired frequency out
is 3.9111Hz. Therefore, the CF frequency must be divided
by 2797/3.9111Hz or 357.5 decimal. This is achieved by
loading t he pair of CF Divider regist ers wit h t he closest
rational number. In this case, the closest rational number is
found to be 1/358 (or 1h/166h). Therefore, 0h and 165h
should be writ t en t o t he CFNUM and CFDEN regist ers
respectively. Note that the CF frequency is multiplied by the
contents of (CFNUM + 1) / (CFDEN + 1). With the CF
Divide regist ers cont ent s equal t o 1h/166h, t he out put
frequency is given as 2797Hz / 358 = 3.905Hz. This setting
has an error of -0.1%.
Calibrating CF is made easy by using the Calibration mode
on the ADE7753. The critical part of this approach is that the
line frequency needs t o be exact ly known. If t his is not
possible, the frequency can be measured by using the PE-
RIOD register of the ADE7753.
Not e t hat changing WGAIN[11:0] regist er will also affect
the output frequency from CF. The WGAIN register has a
gain adjustment of 0.0244% / LSB.
Determi ne the kWHr/LSB Cali brati on Coeffi ci ent
T he Act ive Energy regist er (AENERGY) can be used t o
calculate energy. A full description of this register can be
found in the Energy Calculation section. The AENERGY reg-
ist er gives t he user bot h sign and magnit ude informat ion
regarding energy consumpt ion. On complet ion of t he CF
frequency out put calibrat ion, i. e. , aft er adjust ing t he CF
Frequency divider and the Watt Gain (WGAIN) register, the
second stage of the calibration is to determine the kWh/LSB
coefficient for the AENERGY register. Equation 26 below
shows how LAENERGY can be used to calculate the calibra-
t ion coefficient .
fl 2 0] : 3 LAENERGY[2
0] : LINECYC[15
seconds/Hr 3600
kW) (in Power n Calibratio
kWHr/LSB
× ×
×
·
( 26)
Once the coefficient is determined, the MCU can compute
the energy consumption at any time by reading the AENERGY
contents and multiplying by the coefficient to calculate kWh.
In the above example, at 4.4kW, after 255 half cycles (at
60Hz), t he result ing LAENERGY is approximat ely 2971
decimal. The kWHr/LSB can therefore be calculated to be
8.74×10
-7
kWHr/LSB using the above equation.
ADE7753
–27–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
CLKIN FREQUENCY
In this datasheet, the characteristics of the ADE7753 is shown
with CLKIN frequency equals 3.579545 MHz. However, the
ADE7753 is designed t o have t he same accuracy at any
CLKIN frequency within the specified range. If the CLKIN
frequency is not 3. 579545MHz, various t iming and filt er
characteristics will need to be redefined with the new CLKIN
frequency. For example, the cut-off frequencies of all digital
filters (LPF1, LPF2, HPF1, etc.) will shift in proportion to
the change in CLKIN frequency according to the following
equat ion:
MHz
Frequency CLKIN
Frequency Original Frequency New
579545 . 3
× ·
(27)
The change of CLKIN frequency does not affect the timing
characteristics of the serial interface because the data transfer
is synchronized wit h serial clock signal (SCLK). But one
needs t o observe t he read/writ e t iming of t he serial dat a
transfer-see ADE7753 Timing Characteristics. Table III lists
various t iming changes t hat are affect ed by CLKIN fre-
quency.
Table III
Frequency dependencies of the ADE7753 parameters
Parameter CLKIN dependency
Nyquist frequency for CH 1&2 ADCs C LKI N/ 8
PHCAL resolution (seconds per LSB) 4/ C LKI N
Active Energy register update rate (Hz) C LKI N/ 4
Waveform sampling rate (Number of samples per second)
WAVSEL 1,0 = 0 0 CLKI N/128
0 1 CLKI N/256
1 0 CLKI N/512
1 1 CLKI N/1024
Maximum ZXT OUT period 524, 288/CLKI N
SUSPENDING THE ADE7753 FUNCTIONALITY
The analog and the digital circuit can be suspended sepa-
rately. The analog portion of the ADE7753 can be suspended
by setting the ASUSPEND bit (bit 4) of the Mode register
to logic high See Mode Register. In suspend mode, all
waveform samples from the ADCs will be set to zeros. The
digital circuitry can be halted by stopping the CLKIN input
and maintaining a logic high or low on CLKIN pin. The
ADE7753 can be reactivated by restoring the CLKIN input
and setting the ASUSPEND bit to logic low.
CHECKSUM REGISTER
The ADE7753 has a Checksum register (CHECKSUM[5:0])
to ensure the data bits received in the last serial read operation
are not corrupt ed. T he 6-bit Checksum regist er is reset
before the first bit (MSB of the register to be read) is put on
the DOUT pin. During a serial read operation, when each
data bit becomes available on the rising edge of SCLK, the
bit will be added to the Checksum register. In the end of the
serial read operation, the content of the Checksum register
will equal to the sum of all ones in the register previously
read. Using the Checksum register, the user can determine
if an error has occured during the last read operation.
Note that a read to the Checksum register will also generate
a checksum of the Checksum register itself.
CHECKSUM REGISTER
CONTENT OF REGISTER (n-bytes) DOUT
+
+
Σ
ADDR: 3Eh
Figure 48– Checksum register for Serial Interface Read
ADE7753
–28– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE7753 SERIAL INTERFACE
All ADE7753 functionality is accessible via several on-chip
registers – see Figure 49. The contents of these registers can
be updated or read using the on-chip serial interface. After
power-on or toggling the RESET pin low or a falling edge
on CS, the ADE7753 is placed in communications mode. In
communications mode the ADE7753 expects a write to its
Communications register. The data written to the communi-
cat ions regist er det ermines whet her t he next dat a t ransfer
operation will be read or a write and also which register is
accessed. T herefore all dat a t ransfer operat ions wit h t he
ADE7753, whether a read or a write, must begin with a write
to the Communications register.
COMMUNICATIONS REGISTER
REGISTER # 1
REGISTER # 2
REGISTER # 3
REGISTER # n-1
REGISTER # n
IN
OUT
R
E
G
I
S
T
E
R

A
D
D
R
E
S
S
D
E
C
O
D
E

DIN
DOUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
Figure 49– Addressing ADE7753 Registers via the
Communications Register
The Communications register is an eight bit wide register.
The MSB determines whether the next data transfer opera-
tion is a read or a write. The 5 LSBs contain the address of
the register to be accessed. See ADE7753 Communications Register
for a more detailed description.
Figure 50 and 51 show the data transfer sequences for a read
and write operation respectively.
On completion of a data transfer (read or write) the ADE7753
once again enters communications mode.
COMMUNICATIONS REGISTER WRITE
CS
DIN
DOUT
SCLK
0 0 0 ADDRESS
MULTIBYTE READ DATA
Figure 50– Reading data from the ADE7753 via the serial
i nterface
COMMUNICATIONS REGISTER WRITE
CS
DIN
SCLK
1 0 0 ADDRESS MULTIBYTE WRITE DATA
Figure 51– Writing data to the ADE7753 via the serial inter-
face
A data transfer is complete when the LSB of the ADE7753
register being addressed (for a write or a read) is transferred
to or from the ADE7753.
The Serial Interface of the ADE7753 is made up of four
signals SCLK, DIN, DOUT and CS. The serial clock for a
data transfer is applied at the SCLK logic input. This logic
input has a schmitt-trigger input structure, which allows slow
rising (and falling) clock edges to be used. All data transfer
operat ions are synchronized t o t he serial clock. Dat a is
shifted into the ADE7753 at the DIN logic input on the
falling edge of SCLK. Data is shifted out of the ADE7753 at
the DOUT logic output on a rising edge of SCLK. The CS
logic input is the chip select input. This input is used when
multiple devices share the serial bus. A falling edge on CS
also resets the serial interface and places the ADE7753 in
communications mode. The CS input should be driven low
for t he ent ire dat a t ransfer operat ion. Bringing CS high
during a data transfer operation will abort the transfer and
place the serial bus in a high impedance state. The CS logic
input may be tied low if the ADE7753 is the only device on
the serial bus. However with CS tied low, all initiated data
transfer operations must be fully completed, i.e., the LSB of
each register must be transferred as there is no other way of
bringing t he ADE7753 back int o communicat ions mode
without resetting the entire device, i.e., using RESET.
ADE7753 Serial Write Operation
The serial write sequence takes place as follows. With the
ADE7753 in communications mode (i.e. the CS input logic
low), a write to the communications register first takes place.
The MSB of this byte transfer is a 1, indicating that the data
transfer operation is a write. The LSBs of this byte contain
the address of the register to be written to. The ADE7753
starts shifting in the register data on the next falling edge of
SCLK. All remaining bits of register data are shifted in on the
falling edge of subsequent SCLK pulses – see Figure 51.
As explained earlier the data write is initiated by a write to the
communications register followed by the data. During a data
write operation to the ADE7753, data is transferred to all on-
chip registers one byte at a time. After a byte is transferred
into the serial port, there is a finite time before it is transferred
to one of the ADE7753 on-chip registers. Although another
byte transfer to the serial port can start while the previous byte
is being transferred to an on-chip register, this second byte
transfer should not finish until at least 4µs after the end of the
previous byte transfer. This functionality is expressed in the
timing specification t
6
- see Figure 51. If a write operation is
aborted during a byte transfer (CS brought high), then that
byte will not be written to the destination register.
Destination registers may be up to 3 bytes wide – see ADE7753
Register Descriptions. Hence the first byte shifted into the serial
port at DIN is transferred to the MSB (Most significant Byte)
of the destination register. If the addressed register is 12 bits
wide, for example, a two-byte data transfer must take place.
The data is always assumed to be right justified, therefore in
this case, the four MSBs of the first byte would be ignored and
the 4 LSBs of the first byte written to the ADE7753 would be
t he 4MSBs of t he 12-bit word. Figure 52 illust rat es t his
example.
ADE7753
–29–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Figure 52 – Serial Interface Write Timing Diagram
Figure 53—12 bit Serial Write Operation
ADE7753 Serial Read Operation
During a dat a read operat ion from t he ADE7753 dat a is
shifted out at the DOUT logic output on the rising edge of
SCLK. As was the case with the data write operation, a data
read must be preceded with a write to the Communications
r egist er .
With the ADE7753 in communications mode (i.e. CS logic
low) an eight bit write to the Communications register first
takes place. The MSB of this byte transfer is a 0, indicating
that the next data transfer operation is a read. The LSBs of
this byte contain the address of the register which is to be
read. The ADE7753 starts shifting out of the register data on
the next rising edge of SCLK – see Figure 54. At this point
the DOUT logic output leaves its high impedance state and
starts driving the data bus. All remaining bits of register data
are shifted out on subsequent SCLK rising edges. The serial
interface also enters communications mode again as soon as
the read has been completed. At this point the DOUT logic
output enters a high impedance state on the falling edge of the
last SCLK pulse. The read operat ion may be abort ed by
bringing the CS logic input high before the data transfer is
complete. The DOUT output enters a high impedance state
on the rising edge of CS.
When an ADE7753 register is addressed for a read operation,
the entire contents of that register are transferred to the serial
por t . T his allows t he ADE7753 t o modify it s on-chip
registers without the risk of corrupting data during a multi
byte transfer.
Note when a read operation follows a write operation, the
r ead command ( i. e. , wr it e t o communicat ions r egist er )
should not happen for at least 4µs after the end of the write
operation. If the read command is sent within 4µs of the write
operation, the last byte of the write operation may be lost.
The is given as timing specification t9.
Figure 54– Serial Interface Read Timing Diagram
CS
SCLK
DIN A4 A3 A2 A1 A0 DB7
Most Significant Byte
t
1
t
2
t
3
t
4
t
5
t
8
1 DB0 DB7 DB0
t
6
Least Significant Byte
t
7
t
7
0 0
Command Byte
SCLK
X X X X DB11 DB10 DB9 DB8 DIN
Most Significant Byte
DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
Least Significant Byte
CS
SCLK
DIN A4 A3 A2 A1 A0
t
1
t
11
t
11
t
9
DB7
DOUT
t
12
DB0 DB0 DB7
t
10
t
13
Most Significant Byte Least Significant Byte
0 0 0
Command Byte
ADE7753
–30– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE7753 REGISTER LIST
Address Name R/W # of Bits Default Description
01h WAVEF ORM R 24 bits 0h The Waveform register is a read-only register. This register
contains the sampled waveform data from either Channel 1,
Channel 2 or the Active Power signal. The data source and the
length of the waveform registers are selected by data bits 14 and
13 in the Mode Register - see Channel 1 & 2 Sampling.
02h AEN ERGY R 24 bits 0h The Active Energy register. Active Power is accumulated
(Integrated) over time in this 24-bit, read-only register. The
energy register can hold a minimum of 6 seconds of Active
Energy information with full scale analog inputs before it
overflows - see Energy Calculation.
03h RAENERGY R 24 bits 0h Same as the Active Energy register except that the register is
reset to zero following a read operation
04h LAENERGY R 24 bits 0h Line Accumulation Active Energy register. The instantaneous
active power is accumulated in this read-only register over the
LINCYC number of half line cycles.
05h VAENERGY R 24 bits 0h Apparent Energy register. Apparent power is accumulated over
time in this read-only register.
06h RVAENERGY R 24 bits 0h Same as the VAENERGY register except that the register is reset
to zero following a read operation.
07h LVAENERGY R 24 bits 0h Apparent Energy register. The instantaneous real power is
accumulated in this read-only register over the LINECYC
number of half line cycles
08h LVARENERGY R 24 bits 0h Reactive Energy register. The instantaneous reactive power is
accumulated in this read-only register over the LINECYC
number of half line cycles.
09h MO D E R/ W 16 bits 000Ch The Mode register. This is a 16-bit register through which most
of the ADE7753 functionality is accessed. Signal sample rates,
filter enabling and calibration modes are selected by writing to
this register. The contents may be read at any time—see Mode
Register.
0Ah I RQEN R/ W 16 bits 40h Interrupt Enable register. ADE7753 interrupts may be
deactivated at any time by setting the corresponding bit in this 8-
bit Enable register to logic zero. The Status register will
continue to register an interrupt event even if disabled. However,
the IRQ output will not be activated—see ADE7753 Interrupts.
0Bh ST AT U S R 16 bits 0h The Interrupt Status register. This is an 8-bit read-only register.
The Status Register contains information regarding the source of
ADE7753 interrupts - see ADE7753 Interrupts.
0Ch RST ST AT US R 16 bits 0h Same as the Interrupt Status register except that the register
contents are reset to zero (all flags cleared) after a read
operat ion.
0Dh C H 1 OS R/ W 8 bits 00h Channel 1 Offset Adjust. Bit 6 is not used. Writing to bits 0 to 5
allows offsets on Channel 1 to be removed – see Analog Inputs
and CH1OS Register. Writing a logic one to the MSB of this
register enables the digital integrator on Channel 1, a zero
disables the integrator. The default value of this bit is zero.
0Eh C H 2 OS R/ W 8 bits 0h Channel 2 Offset Adjust. Bit 6 and 7 not used. Writing to bits 0
to 5 of this register allows any offsets on Channel 2 to be
removed - see Analog Inputs.
0F h GAI N R/ W 8 bits 0h PGA Gain Adjust. This 8-bit register is used to adjust the gain
selection for the PGA in Channel 1 and 2 - see Analog Inputs.
ADE7753
–31–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Address Name R/W # of Bits Default Description
10h PHCAL R/ W 6 bits 0Dh Phase Calibration register. The phase relationship between
Channel 1 and 2 can be adjusted by writing to this 6-bit register.
The valid content of this 2's compliment register is between 1Dh
to 21h. At line frequency of 60Hz, this is a range from -2.06 to
+0. 7 degrees. —see Phase Compensation.
11h AP OS R/ W 16 bits 0h Active Power Offset Correction. This 16-bit register allows small
offsets in the Active Power Calculation to be removed – see
Active Power Calculation.
12h WGAI N R/ W 12 bits 0h Power Gain Adjust. This is a 12-bit register. The Active Power
calculation can be calibrated by writing to this register. The
calibration range is ±50% of the nominal full scale active power.
The resolution of the gain adjust is 0.0244% / LSB—see Channel
1 ADC Gain Adjust.
13h WD I V R/ W 8 bits 0h Active Energy divider register. The internal active energy register
is divided by the value of this register before being stored in the
AENERGY regist er.
14h C F N U M R/ W 12 bits 3F h CF Frequency Divider Numerator register. The output frequency
on the CF pin is adjusted by writing to this 12-bit read/write
register – see Energy to Frequency Conversion.
15h C F D EN R/ W 12 bits 3F h CF Frequency Divider Denominator register. The output
frequency on the CF pin is adjusted by writing to this 12-bit
read/write register – see Energy to Frequency Conversion.
16h I RMS R 24 bits 0h Channel 1 RMS value (current channel).
17h VRMS R 24 bits 0h Channel 2 RMS value (voltage channel).
18h I RMSOS R/ W 12 bits 0h Channel 1 RMS offset correction register
19h VRMSOS R/ W 12 bits 0h Channel 2 RMS offset correction register
1Ah VAGAI N R/ W 12 bits 0h Apparent Gain register. Apparent power calculation can be
calibrated by writing this register. The calibration range is 50%
of the nominal full scale real power. The resolution of the gain
adjust is 0.02444% / LSB.
1Bh VADI V R/ W 8 bits 0h Apparent Energy divider register. The internal apparent energy
register is divided by the value of this register before being stored
in the VAENERGY register.
1Ch LI N EC YC R/ W 15 bits F F F h Line Cycle Energy Accumulat ion Mode Line-Cycle regist er.
This 15-bit register is used during line cycle energy
accumulation mode to set the number of half line cycles for
energy accumulation - see Line Cycle Energy Accumulation Mode.
1Dh Z XT OU T R/ W 12 bits F F F h Zero-cross Time Out. If no zero crossings are detected on
Channel 2 within a time period specified by this 12-bit register,
the interrupt request line (IRQ) will be activated. The maximum
time-out period is 0.15 second - see Zero Crossing Detection.
1Eh SAGC YC R/ W 8 bits F F h Sag line Cycle register. This 8-bit register specifies the number
of consecutive line cycles the signal on Channel 2 must be below
SAGLVL before the SAG output is activated - see Voltage Sag
Det ect ion
1F h SAG LVL R/ W 8 bits 0h Sag Voltage Level. An 8-bit write to this register determines at
what peak signal level on Channel 2 the SAG pin will become
active. The signal must remain low for the number of cycles
specified in the SAGCYC register before the SAG pin is
act ivat ed—see Line Voltage Sag Detection.
20h I P KLVL R/ W 8 bits F F h Channel 1 Peak Level threshold (current channel). This register
sets the level of the current peak detection. If the channel 1 input
exceeds this level, the PKI flag in the status register is set.
ADE7753
–32– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE7753 REGISTER DESCRIPTIONS
All ADE7753 funct ionalit y is accessed via t he on-chip regist ers. Each regist er is accessed by first writ ing t o t he
communications register and then transferring the register data. A full description of the serial interface protocol is given in
the Serial Interface section of this data sheet.
Communi cati ons Regi s ter
The Communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753
and the host processor. All data transfer operations must begin with a write to the communications register. The data written
to the communications register determines whether the next operation is a read or a write and which register is being accessed.
Table IV below outlines the bit designations for the Communications register.
Table V. Communications Register
Bit Bit Description
Locati on Mnemoni c
0 to 5 A0 to A5 The six LSBs of the Communications register specify the register for the data transfer
operation. Table III lists the address of each ADE7753 on-chip register.
6 RESERVED This bit is unused and should be set to zero.
7 W/ R When this bit is a logic one the data transfer operation immediately following the write to
the Communications register will be interpreted as a write to the ADE7753. When this bit
is a logic zero t he dat a t ransfer operat ion immediat ely following t he writ e t o t he
Communications register will be interpreted as a read operation.
DB0
W/R A4 A3 A2 A1 A0 0 A5
DB1 DB2 DB3 DB4 DB5 DB6 DB7
Address Name R/W # of Bits Default Description
21h VP KLVL R/ W 8 bits F F h Channel 2 Peak Level threshold (voltage channel). This register
sets the level of the voltage peak detection. If the channel 2 input
exceeds this level, the PKV flag in the status register is set.
22h I PEAK R 24 bits 0h Channel 1 peak register. The maximum input value of the
Current channel since the last read of the register is stored in this
r egist er .
23h RST I PEAK R 24 bits 0h Same as Channel 1 peak register except that the register contents
are reset to 0 after read.
24h VPEAK R 24 bits 0h Channel 2 peak register. The maximum input value of the
Voltage channel since the last read of the register is stored in this
r egist er .
25h RST VPEAK R 24 bits 0h Same as Channel 2 peak register except that the register contents
are reset to 0 after a read.
26h T EMP R 8 bits 0h Temperature register. This is an 8-bit register which contains the
result of the latest temperature conversion – see Temperature
Measurement.
27h P ERI OD R 15 bits 0h Period of the channel 2 (volatge channel) input estimated by
Zero-crossing processing.
28h-
3Ch Reserved
3Dh T MOD E R/ W 8 bits - Test mode register
3Eh C H KSU M R 6 bits 0h Checksum Register. This 6-bit read only register is equal to the
sum of all the ones in the previous read – see ADE7753 Serial Read
Operation.
3F h D I EREV R 8 bits - Die Revision Register. This 8-bit read only register contains the
revision number of the silicon.
ADE7753
–33–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Mode Register ( 09H)
The ADE7753 functionality is configured by writing to the MODE register. Table VI below summarizes the functionality
of each bit in the MODE register .
Table VI : Mode Register
Bit Bit Default
Location Mnemonic Value Description
0 D I SH P F 0 The HPF (High Pass Filter) in Channel 1 is disabled when this bit is set.
1 D I SLP F 2 0 The LPF (Low Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.
2 D I SC F 1 The Frequency output CF is disabled when this bit is set
3 D I SSAG 1 The line voltage Sag detection is disabled when this bit is set
4 ASUSP EN D 0 By setting this bit to logic one, both ADE7753's A/D converters can be turned off. In
normal operation, this bit should be left at logic zero. All digital functionality can be
stopped by suspending the clock signal at CLKIN pin.
5 T EMP SEL 0 The Temperature conversion starts when this bit is set to one. This bit is automatically
reset to zero when the Temperature conversion is finished.
6 SWRST 0 Software chip reset. A data transfer should not take place to the ADE7753 for at least 18µs
after a software reset.
7 C YC MOD E 0 Setting this bit to a logic one places the chip in line cycle energy accumulation mode.
8 D I SC H 1 0 ADC 1 (Channel 1) inputs are internally shorted together.
9 D I SC H 2 0 ADC 2 (Channel 2) inputs are internally shorted together.
10 SWAP 0 By setting this bit to logic 1 the analog inputs V2P and V2N are connected to ADC 1 and
the analog inputs V1P and V1N are connected to ADC 2.
12, 11 DT RT 1, 0 00 These bits are used to select the Waveform Register update rate
DT RT 1 DT RT 0 Update Rate
0 0 27. 9kSPS ( CLKIN/128)
0 1 14kSPS ( CLKIN/256)
1 0 7kSPS ( CLKIN/512)
1 1 3. 5kSPS ( CLKIN/1024)
14, 13 WAVSEL1, 0 00 These bits are used to select the source of the sampled data for the Waveform Register
WAVSEL1, 0 Lengt h Sour ce
0 0 24 bits Active Power signal (output of LPF2)
0 1 Reserved
1 0 24 bits Channel 1
1 1 24 bits Channel 2
15 P OAM 0 Writing a logic one to this bit will allow only positive power to be accumulated in the
ADE7753. The default value of this bit is 0.
MODE REGISTER*
ADDR: 09H
0 1 2 3 4 5 6 7
0 0 1 1 0 0 0 0
POAM
(Positive Only Accumulation)
WAVSEL
(Wave form selection for sample mode)
00 = LPF2
01= Reserved
10 = CH1
11 = CH2
DISHPF
(Disable HPF in Channel 1)
DISLPF2
DISCF
(Disable Frequency output CF)
DISSAG
(Disable SAG output)
*Register contents show power on defaults
(Suspend CH1&CH2 ADC’s)
8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0
DTRT
(Waveform samples output data rate)
00 = 27.9kSPS (CLKIN/128)
01 = 14.4 kSPS (CLKIN/256)
10 = 7.2 kSPS (CLKIN/512)
11 = 3.6 kSPS (CLKIN/1024)
SWAP
(Swap CH1 & CH2 ADCs)
DISCH2
(Short the analog inputs on Channel 2)
DISCH1
(Short the analog inputs on Channel 1)
SWRST
(Software chip reset)
CYCMODE
(Line Cycle Energy Accumulation Mode)
(Disable LPF2 after multiplier)
STEMP
ASUSPEND
(Start temperature sensing)
ADE7753
–34– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
Interrupt Status Register (0BH) / Reset Interrupt Status Register (0CH) /Interrupt Enable Register (0Ah)
The Status Register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs
in the ADE7753, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is logic
one in the Interrupt Enable register, the IRQ logic output goes active low. When the MCU services the interrupt it must first
carry out a read from the Interrupt Status Register to determine the source of the interrupt.
Table VII: Interrupt Status Register, Reset Interrupt Status Register & Interrupt Enable Register
Bit Interrupt
Locati on Fl ag Description
0h AEH F Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active
Energy register (i.e. the AENERGY register is half full)
1h SAG Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were
det ect ed.
2h C YC EN D Indicates the end of energy accumulation over an integer number of half line cycles as
defined by the content of the LINECYC Register—see Line Cycle Energy Accumulation Mode
3h WSMP Indicates that new data is present in the Waveform Register.
4h Z X This status bit reflects the status of the ZX logic ouput—see Zero Crossing Detection
5h T EMP Indicates that a temperature conversion result is available in the Temperature Register.
6h RESET Indicates the end of a reset (for both software or hardware reset). The corresponding
enable bit has no function in the Interrupt Enable Register, i.e. this status bit is set at
the end of a reset, but it cannot be enabled to cause an interrupt.
7h AEOF Indicates that the Active Energy register has overflowed.
8h PKV Indicates that waveform sample from Channel2 has exceeded the VPKLVL value.
9h PKI Indicates that waveform sample from Channel1 has exceeded the IPKLVL value.
Ah VAEH F Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Apparent
Energy register (i.e. the VAENERGY register is half full)
Bh VAEOF Indicates that the Apparent Enrgy register has overflowed.
C h Z XT O Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the
specified number of line cycles—see Zero Crossing Time Out
D h P P OS Indicates that the power has gone from negative to positive.
E h P N EG Indicates that the power has gone from positive to negative.
F h RESERVED Reserved
ADE7753
–35–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
OUTLINE D IMENS IONS
Dimensions shown in inches and (mm)
20 11
10 1
0.295 (7.50)
0.271 (6.90)
0
.
3
1
1

(
7
.
9
)
0
.
3
0
1

(
7
.
6
4
)
0
.
2
1
2

(
5
.
3
8
)
0
.
2
0
5

(
5
.
2
1
)
PI N 1
SEATI NG
PLANE
0.008 (0.203)
0.002 (0.050)
0.07 (1.78)
0.066 (1.67)
0.0256
(0.65)
BSC
0.078 (1.98)
0.068 (1.73)
0.009 (0.229)
0.005 (0.127)
0.037 (0.94)
0.022 (0.559)


20- Shri nk Small Outli ne Package
(RS-20)
ADE7753
–36– REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE7753 ERRATA (REV 1. 0)
The following is a list of known issues with the first revision
of t he ADE7753 silicon (rev 1. 0). T hese issues will be
resolved in the next version. Samples of this version of the
silicon can be identified from the content of the DIEREV
regsiter (Address 3Fh). The content of DIEREV register is
2 for Rev 1.2 silicon. In addition, the branding on top of the
package for Rev 1.2 should be as shown below:
20 11
10 1
AD7753
XRS
0240
K58207
ERRATA
1. SAGCYC
T he cont ent s of SAGCYC r egist er is equivalent t o
( SAGCYC-1) . For example, if t he desired number of
linecycles for SAG detection is 20d line cycles, one should
write 21d to the SAGCYC Register. This is not a silicon
bug.
2. CFNUM and CFDEN
CFNUM should always be less than CFDEN. The behav-
ior of the output frequency is not guaranteed for CF. This
is not a silicon bug.
ADE7753
–37–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
REVISION HISTORY
The main reason for revising the datasheet from version Pr.D
to Pr.F is to correct some of the mistakes contained in the
Pr.D and Pr.E version. In addition, changes were made to the
silicon to fix bugs noted in the Errata list and to modify the
product definition. The list below highlights the important
changes from Pr.D to Pr.F. Note that all page numbers are
referring to that of Pr.F.
Page 4
Read timing t
9
is determined to be 3.1us.
Page 12
The SAGCYC register value represents full-line cycles and
not half-line cycles. The line voltage SAG detection section
text was changed to reflect this design update. Figure 13
shows 3 line cycles, 3h in the SAGCYC register, changed
from 6 half line cycles, 6h in the SAGCYC register. The
section explaining Figure 13 has also changed accordingly.
Page 13
Peak Level record sect ion was changed t o show t hat t he
quantity stored in VPEAK register is 2 times the absolute
value of the WAVEFORM register contents for CH2. IPEAK
is 1 times the absolute value of the CH1 Waveform.
Page 18
1. The phase calibration register resolution has changed to
0. 048 from 0. 024. T his sect ion calculat ions have been
changed to reflect this new resolution.
2. Figure 27 updat ed wit h new PHCAL range and delay
block rat e.
Page 20
Figure 36 Timing was updated.
Page 21
1. The internal active energy accumulation register is 47 bits
instead of 53 bits. The equation also shows this change. This
change is also implemented in the equations of page 25 as
well as Figures 45 and 47 on page 25.
2. The maximum output frequency is changed to 23Hz.
3. T ext added t o explain CF NUM must be less t han
C F D EN .
Page 22
1. Figure 39 shows the actual internal register length to be 47
bits. This change is also on page 23, Figure 41.
2. Line Cycle Energy accumulation mode section changed to
15 bits for LINECYC Register.
Page 26
1. Equation 25 changed to have 2^27 bits for the denomina-
t or.
2. Content of LAENERGY register is 2971.4, and the CF
frequency output in the example calculation is 1398.3 Hz.
3. T he calculat ion of CF NUM and CF DEN changed
according to the effect of the abovementioned changes.
Page 31
1. The definition of the SAGCYC a register has changed to
full line cycles. LINECYC correct ed t o say 15 bit s and
remains half line cycles.
2. The PHCAL register description changed to reflect the
new effective length and resolution of the register and default
value of 0D.
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

PRELIMINARY TECHNICAL DATA

ADE7753–SPECIFICATIONS1,3
Parameter ENERGY MEASUREMENT ACCURACY Measurement Bandwidth Measurement Error1 on Channel 1 Channel 1 Range = 0.5V full-scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Channel 1 Range = 0.25V full-scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Channel 1 Range = 0.125V full-scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Phase Error1 Between Channels AC Power Supply Rejection1 Output Frequency Variation (CF) DC Power Supply Rejection1 Output Frequency Variation (CF) ANALOG INPUTS Maximum Signal Levels Input Impedance (dc) Bandwidth Gain Error1,4 Channel 1 Range = 0.5V full-scale Range = 0.25V full-scale Range = 0.125V full-scale Channel 2 Gain Error Match1 Channel 1 Range = 0.5V full-scale Range = 0.25V full-scale Range = 0.125V full-scale Channel 2 Offset Error1 Channel 1 Channel 2 WAVEFORM SAMPLING Channel 1 Signal-to-Noise plus distortion Bandwidth (-3dB) Channel 2 Signal-to-Noise plus distortion Bandwidth (-3dB) Spec 14

(AVDD = DVDD = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference, CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)
Units kHz Test Conditions/Comments CLKIN = 3.579545 MHz Channel 2 = 300mV rms/60Hz, Gain = 2 Over a dynamic range Over a dynamic range Over a dynamic range Over a dynamic range Over a dynamic range Over a dynamic range Over a dynamic range Over a dynamic range Over a dynamic range Over a dynamic range 1000 to 1 1000 to 1 1000 to 1 1000 to 1 1000 to 1 1000 to 1 1000 to 1 1000 to 1 1000 to 1 1000 to 1

0.1 0.1 0.1 0.1 0.2 0.1 0.1 0.1 0.2 0.2 0.1 0.1 0.2 0.2 0.4 ±0.05 0.2

% typ % typ % typ % typ % typ % typ % typ % typ % typ % typ % typ % typ % typ % typ % typ ° max % typ

±0.3

% typ

Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Line Frequency = 45Hz to 65Hz, HPF on AVDD = DVDD = 5V+175mV rms/ 120Hz Channel 1 = 20mV rms, Gain = 16, Range = 0.5V Channel 2 = 300mV rms/60Hz, Gain = 1 AVDD = DVDD = 5V ± 250mV dc Channel 1 = 20mV rms/60Hz, Gain = 16, Range = 0.5V Channel 2 = 300mV rms/60Hz, Gain = 1 See Analog Inputs Section V1P, V1N, V2N and V2P to AGND CLKIN/256, CLKIN = 3.579545MHz External 2.5V reference, Gain = 1 on Channel 1 & 2 V1 = 0.5V dc V1 = 0.25V dc V1 = 0.125V dc V2 = 0.5V dc External 2.5V reference Gain = 1, 2, 4, 8, 16 Gain = 1, 2, 4, 8, 16 Gain = 1, 2, 4, 8, 16 Gain = 1, 2, 4, 8, 16 Channel 1 Range = 0.5V Channel 2 Range = 0.5V Sampling CLKIN/128, 3.579545MHz/128 = 27.9kSPS See Channel 1 Sampling 150mV rms/60Hz, Range = 0.5V, Gain = 2 CLKIN = 3.579545MHz See Channel 2 Sampling 150mV rms/60Hz, Gain = 2 CLKIN = 3.579545MHz

±0.5 390 14

V max kΩ min kHz

±4 ±4 ±4 ±4

% typ % typ % typ % typ

±0.3 ±0.3 ±0.3 ±0.3 ±10 ±10

% typ % typ % typ % typ mV max mV max

62 14 52 140

dB typ kHz dB typ Hz

-2-

REV. PrF 10/02

PRELIMINARY TECHNICAL DATA ADE7753
Parameter REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Current source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency Spec 2.6 2.2 10 ±200 10 4 20 4 1 Units V max V min pF max mV max µA max kΩ min ppm/°C typ Note all specifications CLKIN of 3.579545MHz MHz max MHz min Test Conditions/Comments 2.4 V +8% 2.4V -8% Nominal 2.4V at REFIN/OUT pin

LOGIC INPUTS RESET, DIN, SCLK, CLKIN and CS 2.4 Input High Voltage, VINH Input Low Voltage, VINL 0.8 ±3 Input Current, IIN Input Capacitance, CIN 10 LOGIC OUTPUTS3 SAG & IRQ Output High Voltage, VOH Output Low Voltage, VOL ZX & DOUT Output High Voltage, VOH Output Low Voltage, VOL CF Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY AV DD DV DD AI DD DIDD

V min V max µA max pF max

DVDD = 5 V ± 10% DVDD = 5 V ± 10% Typically 10nA, VIN = 0V to DVDD

4 0.4 4 0.4 4 1 4.75 5.25 4.75 5.25 3 4

V min V max V min V max V min V max V min V max V min V max mA max mA max

Open Drain outputs, 10kΩ pull up resistor ISOURCE = 5mA ISINK = 0.8mA ISOURCE = 5mA ISINK = 0.8mA ISOURCE = 5mA ISINK = 7mA For specified Performance 5V - 5% 5V +5% 5V - 5% 5V + 5% Typically 2.0 mA Typically 3.0 mA

NOTES: 1 See Terminology Section for explanation of Specifications 2 See Plots in Typical Performance Graphs 3 Specifications subject to change without notice 4 See Analog Inputs Section

ORDERING GUIDE
IOL 200 µA TO OUTPUT PIN +2.1V CL 50pF 1.6 mA IOH

MODEL ADE7753ARS ADE7753ARSRL EVAL-ADE7753EB

Package Option* RS-20 RS-20 ADE7753 evaluation board

* RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small Outline Package in reel.

Load Circuit for Timing Specifications

REV. PrF 10/02

–3–

5V when loaded with the circuit in Figure 1. CLKIN = 3.2 Parameter Write timing t1 t2 t3 t4 t5 t6 t7 t8 Read timing t9 t10 t113 t124 t 13 4 A. Data access time after SCLK rising edge following a write to the Communications Register Bus relinquish time after falling edge of SCLK. CS Hold time after SCLK falling edge. Minimum time between byte transfers during a serial write. The measured number is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. TMIN to TMAX = -40°C to +85°C) Test Conditions/Comments CS falling edge to first SCLK falling edge SCLK logic high pulse width SCLK logic low pulse width Valid Data Set up time before falling edge of SCLK Data Hold time after SCLK falling edge Minimum time between the end of data byte transfers. 2 See timing diagram below and Serial Interface section of this data sheet. All input signals are specified with tr = tf = 5ns (10% to 90%) and timed from a voltage level of 1. 4 Derived from the measured time taken by the data outputs to change 0.8V or 2.579545MHz XTAL.1 TBD 30 100 10 100 10 Units ns ns ns ns ns ns ns ns (min) (min) (min) (min) (min) (min) (min) (min) (AVDD = DVDD = 5V ± 5%. PrF 10/02 . On-Chip Reference. Minimum time between read command (i. AGND = DGND = 0V.PRELIMINARY TECHNICAL DATA ADE7753 ADE7753 TIMING CHARACTERISTICS1. Bus relinquish time after rising edge of CS.B Versions 20 150 150 10 5 TBD TBD 100 3. Minimum time between data byte transfers during a multibyte read.6V. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. us (min) ns (min) ns (min) ns ns ns ns (max) (min) (max) (min) NOTES Sample tested during initial release and after any redesign or process change that may affect this parameter. a write to Communication Reigster) and data read.4V. 3 Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0. 1 Serial Write Timing t8 CS t1 t2 t3 t7 t4 t5 DB7 DB0 DB7 DB0 t7 t6 SCLK DIN 1 0 0 A4 A3 A2 A1 A0 Command Byte Most Significant Byte Least Significant Byte Serial Read Timing CS t1 t9 t10 t13 SCLK DIN DOUT Command Byte 0 0 0 A4 A3 A2 A1 A0 t11 DB7 t11 DB0 DB7 t12 DB0 Most Significant Byte Least Significant Byte –4– REV.e.

3 V to DVDD + 0. . To offset this phase response and equalize the phase response between channels. . . . . –65°C to +150°C Junction Temperature . .see characteristic curves. . Soldering Vapor Phase (60 sec) . It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal. Therefore. . .5V. .3 V Digital Output Voltage to DGND –0. . . A second reading is obtained with the same input signal levels when an ac (175mV rms/120Hz) signal is introduced onto the supplies. . . . The offsets may be removed by performing an offset calibration see Analog Inputs. . . . . +150°C 20 Pin SSOP. . . . . .1° over a range of 45Hz to 65Hz and ±0. . . . . . . –0. . . . .3 V to AVDD + 0. The magnitude of the offset depends on the gain and input range selection . . . proper ESD precautions are recommended to avoid performance degradation or loss of functionality. . . . .3 V Digital Input Voltage to DGND –0. –40°C to +85°C Storage Temperature Range . . . .2° over a range 40Hz to 1kHz. It is measured for each of the input ranges on Channel 1 (0. . Each phase correction network corrects the phase response of the corresponding component and ensures a phase match between Channel 1 (current) and Channel 2 (voltage) to within ±0. GAIN ERROR This quantifies the ADE7753 measurement error as a percentage of reading when the power supplies are varied.25V and 0. . However. 4.3 V Analog Input Voltage to AGND V1P. . .3 V to DVDD + 0. . . . . . Any error introduced is again expressed as a percentage of reading. . This gives the gain error observed when the gain selection is changed from 1 to 2. . . . .125V). . . . . . . . . . . . 4. . . . . 8 or 16. . two phase correction network is placed in Channel 1: one for the digital integrator and the other for the HPF. . . . . . . . –0. . . . ADC OFFSET ERROR The digital integrator and the HPF (High Pass Filter) in Channel 1 have non-ideal phase response. . . .3 V to +0. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REV.see Channel 1 ADC & Channel 2 ADC. . PrF 10/02 –5– . . . . A second reading is obtained with the same The gain error in the ADE7753 ADCs is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code . . . –0. . . . . This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. permanent damage may occur on devices subjected to high energy electrostatic discharges. V1N. . . . . . . . . . . CAUTION ESD (electrostatic discharge) sensitive device.3 V to +7 V DVDD to DGND .PRELIMINARY TECHNICAL DATA ADE7753 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise noted) AVDD to AGND . . . . . . . . . . GAIN ERROR MATCH The Gain Error Match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 (for each of the input ranges) and a gain of 2. . .3 V to +7 V DVDD toAVDD . Power Dissipation . . . . . . . . –0. . . WARNING! ESD SENSITIVE DEVICE Terminology MEASUREMENT ERROR The error associated with the energy measurement made by the ADE7753 is defined by the following formula: Percentage Error =  Energy registered by ADE 7753 − True Energy    × 100 %   True Energy   PHASE ERROR BETWEEN CHANNELS input signal levels when the supplies are varied ±5%. 8. . . . It is expressed as a percentage of the output ADC code obtained under a gain of 1. . . POWER SUPPLY REJECTION This refers to the DC offset associated with the analog inputs to the ADCs. . . . . . . . . . . . . V2P and V2N . . +215°C Infrared (15 sec) . . Any error introduced by this AC signal is expressed as a percentage of reading—see Measurement Error definition above. . . . . . . . . . . . . 112°C/W Lead Temperature. . . . The difference is expressed as a percentage of the ideal code. . . .3 V Operating Temperature Range Industrial . . . . For the AC PSR measurement a reading at nominal supplies (5V) is taken. . 0. . Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. . . Although the ADE7753 features proprietary ESD protection circuitry. or 16. . . . +220°C * Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. . . . 450 mW θJA Thermal Impedance . . . . . when HPF1 is switched on the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. . . . . . . . . For the DC PSR measurement a reading at nominal supplies (5V) is taken. . -6V to +6V Reference Input Voltage to AGND . . . . . . . . . . .

Calibration Frequency logic output. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance. and an overvoltage of ±6V can be sustained on these inputs without risk of permanent damage. These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0. Interrupt Request Output. This output toggles logic high and low at the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection. The CF logic output gives Active Power information. This pin provides the supply voltage for the analog circuitry in the ADE7753. i. Analog inputs for Channel 2.5 V1P. This is an active low open drain logic output.5V. See Line Voltage Sag Detection. This pin should be tied to the analog ground plane or the quietest ground reference in the system. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM Register—see Energy To Frequency Conversion.5V.e.see Applications Information. The on-chip reference has a nominal value of 2. This quiet ground reference should be used for all analog circuitry. multiplier. Channel 2 also has a PGA with gain selections of 1. –6– REV. 8 or 16. e. This pin provides access to the on-chip voltage reference. This pin should be decoupled to AGND with a 10µF capacitor in parallel with a ceramic 100nF capacitor. 1 2 MNEMONIC RESET DVDD DESCRIPTION Reset pin for the ADE7753. the quiet ground plane should only connected to the digital ground plane at one point. 2. In either case this pin should be decoupled to AGND with a 1µF ceramic capacitor.e. These inputs are fully differential voltage inputs with a maximum differential signal level of ±0. Active Energy Register at half level. An external reference source may also be connected at this pin. Analog inputs for Channel 1. 2.4V ± 8% and a typical temperature coefficient of 20ppm/°C. PrF 10/02 3 AVDD 4. filters and digital-to-frequency converter. Voltage waveform (Channel 2) zero crossing output. depending on the full scale selection . A logic low on this pin will hold the ADCs and digital circuitry (including the Serial Interface) in a reset condition. Maskable interrupts include: Active Energy Register roll-over.See Analog Inputs. The maximum signal level at these pins with respect to AGND is ±0. This pin provides the ground reference for the analog circuitry in the ADE7753. See ADE7753 Interrupts.g.7 V2N. current and voltage transducers etc. V2P 8 AGND 9 REFIN/OUT 10 DGND 11 CF 12 13 ZX SAG 14 IRQ . 4. The maximum signal level at these pins with respect to AGND is ±0. and arrivals of new waveform samples.25V and ±0. i.125V. Analog power supply. However. it is acceptable to connect this pin to the analog ground plane of the system . The supply voltage should be maintained at 5V ± 5% for specified operation. ±0. 8 or 16. Digital power supply. Both inputs have internal ESD protection circuitry. anti-aliasing filters. The supply should be maintained at 5V ± 5% for specified operation. This pin should be decoupled to DGND with a 10µF capacitor in parallel with a ceramic 100nF capacitor.see Applications Information. This provides the ground reference for the digital circuitry in the ADE7753. Because the digital return currents in the ADE7753 are small. This pin provides the supply voltage for the digital circuitry in the ADE7753. This output is intended to be used for operational and calibration purposes. Channel 1 also has a PGA with gain selections of 1. The typical performance graphs in this data sheet show the power supply rejection performance. This open drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (Channel 2) is crossed for a specified duration.5V. It is acceptable to place the entire device on the analog ground plane .5V. In order to keep ground noise around the ADE7753 to a minimum. This channel is intended for use with the di/dt current transducer such as Rogowski coil or other current sensor such as shunt or current transformer (CT). Both inputs have internal ESD protection circuitry and in addition an overvoltage of ±6V can be sustained on these inputs without risk of permanent damage. ADCs and reference. V1N 6.PRELIMINARY TECHNICAL DATA ADE7753 PIN FUNCTION DESCRIPTION Pin No. This channel is intended for use with the voltage transducer. 4.

All Serial data transfers are synchronized to this clock—see ADE7753 Serial Interface... PrF 10/02 –7– .. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. e.PRELIMINARY TECHNICAL DATA ADE7753 Pin No. Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see ADE7753 Serial Interface. Serial Clock Input for the synchronous serial interface. Alternatively. Refer to crystal manufacturers data sheet for load capacitance requirements. The SCLK has a schmitt-trigger input for use with a clock source which has a slow edge transition time.g.579545MHz. Chip Select. Ceramic load capacitors of between 22pF and 33pF should be used with the gate oscillator circuit. Data is shifted out at this pin on the rising edge of SCLK. A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7753. Data Output for the Serial Interface. Part of the four wire SPI Serial Interface. 16 CLKOUT 17 CS 18 SCLK 19 DOUT 20 DIN PIN CONFIGURATION SSOP Packages RESET DVDD AVDD V1P V1N V2N V2P AGND REFIN/OUT DGND 1 2 3 4 5 6 7 8 9 10 ADE7753 TOP VIEW (Not to Scale) 20 DIN 19 DOUT 18 SCLK 17 CS 16 CLKOUT 15 CLKIN 14 13 IRQ SAG 12 ZX 11 CF REV. The clock frequency for specified operation is 3. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus—see ADE7753 Serial Interface. optoisolator outputs. An external clock can be provided at this logic input. 15 MNEMONIC CLKIN DESCRIPTION Master clock for ADCs and digital signal processing. a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753. This active low logic input allows the ADE7753 to share the serial bus with several other devices. See ADE7753 Serial Interface.

Gain=8) TBD TPC 3— Error as a % of Reading (Gain=16) TBD –8– TPC 6— Test Circuits for Performance Curves REV.25V. PrF 10/02 .125V.PRELIMINARY TECHNICAL DATA ADE7753 Typical Performance Characteristics-ADE7753 TBD TPC 1— Error as a % of Reading (Gain=1) TBD TPC 4— Error as a % of Reading (Full-Scale input for Channel 1=0. Gain=4) TBD TPC 2— Error as a % of Reading (Gain=4) TBD TPC 5— Error as a % of Reading (Full-scale input for Channel 1=0.

This is achieved by adjusting the ADC reference—see ADE7753 Reference Circuit. Figure 4 shows the relationship between the Offset Correction register contents and the offset (mV) on the analog inputs for a gain setting of one.IOS V. 2. The maximum value which can be written to the offset correction registers is ±31 decimal —see Figure 4.5V.00781V REV. by using bits 3 and 4 in the Gain register.25V or 0. and there should be no signal on either Channel 1 or Channel 2. In order to perform an offset adjustment. Table II below shows the correctable offset span for each of the gain settings and the LSB weight (mV) for the Offset Correction registers. Error terms at Cos(w.125V Gain Gain Gain Gain Gain — — = = = = = 1 2 4 8 16 — Gain Gain Gain Gain Gain — = = = = = 1 2 4 8 16 — — Gain Gain Gain Gain Gain = = = = = 1 2 4 8 16 –9– The contents of the Offset Correction registers are 6-Bit.0313V 0. Each analog input channel has a PGA (Programmable Gain Amplifier) with possible gain selections of 1. 4. the maximum signal level on analog inputs for V1P/V1N and V2P/ V2N are ±0.t) are removed by LPF2 and by integration of the Active Power signal in the Active Energy register (AENERGY[23:0]) – see Energy Calculation. However. DC component (including error term) is extracted by the LPF for real power calculation In addition to the PGA. 1. the offsets will have contributed an error to the Active Power calculation. As mentioned previously the maximum differential input voltage is 1V.PRELIMINARY TECHNICAL DATA ADE7753 ANALOG INPUTS The ADE7753 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N are ±0.0625V 0. In addition. 8 and 16. The ADC analog input range selection is also made using the Gain register—see Figure 2.5V 01 = 0. As can be seen from Figure 3.Vin V1N Σ + Offset Adjust (±50mV) CH1OS[7:0] Bit 0 to 5: Sign magnitude coded offset correction Bit 6: Not used Bit 7: Digital Integrator (On=1.I 0 ω 2 ω frequency (rad/s) Figure 3— Effect of channel offsets on the real power calculation Table I Maximum input signal levels for Channel 1 Max Signal Channel 1 0.e. These registers allow channel offsets in the range ±20mV to ±50mV (depending on the gain setting) to be removed. Channel 1 also has a full scale input range selection for the ADC. Bits 0 to 2 select the gain for the PGA in Channel 1 and the gain selection for the PGA in Channel 2 is made via bits 5 to 7.25V 10 = 0. The gain selections are made by writing to the Gain register—see Figure 2. The analog inputs should be first connected to AGND.. Since this dc component is extracted by LPF2 to generate the Active (Real) Power information. Figure 3 shows the effect of offsets on the real power calculation.5V 0. Note that it is not necessary to perform an offset correction in an Energy measurement application if HPF in Channel 1 is switched on.5V with respect to AGND. i.V VOS. VOS. 2.0156V 0. Table I below summarizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections.5V. This problem is easily avoided by enabling HPF in Channel 1. 8 or 16. GAIN[7:0] GAIN REGISTER* Channel 1 and Channel 2 PGA Control 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 ADDR: 0FH PGA 2 Gain Select 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16 *Register contents show power on defaults PGA 1 Gain Select 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16 Channel 1 Full Scale Select 00 = 0. no error component is generated at dc by the multiplication. 4. By removing the offset from at least one channel.125V Figure 2— ADE7753 Analog Gain register V1P Gain (k) selection Vin + - k.125V 0. default ON) Figure 1— PGA in Channel 1 It is also possible to adjust offset errors on Channel 1 and Channel 2 by writing to the Offset Correction Registers (CH1OS and CH2OS respectively). Off=0.25V 0. A read from Channel 1 or Channel 2 using the . an offset on Channel 1 and Channel 2 will contribute a dc component after multiplication.I 2 IOS.5V 0.25V 0. Figure 1 shows how a gain selection for Channel 1 is made using the Gain register. the maximum ADC input voltage can be set to 0. PrF 10/02 ADC Input Range Selection 0. sign and magnitude coded. 0.125V. The weighting of the LSB size depends on the gain setting.

Figure 5 shows the principle of a di/dt current sensor.5 -5 -5. The offset correction can be confirmed by performing another read.97mV/LSB 0. The changes in the magnetic flux density passing through a conductor loop generates an electromotive force (EMF) between the two ends of the loop.induced by changes in magnetic flux density (d/dt) GAIN-dB -2 -2.PRELIMINARY TECHNICAL DATA ADE7753 Table II Offset Correction range Gain 1 2 4 8 16 Correctable Span ±50mV ±37mV ±30mV ±26mV ±24mV LSB Size 1. The digital integrator on Channel 1 is switched off by default when the ADE7753 is powered up. CH1OS[5:0] 1Fh 01. Note when adjusting the offset of Channel 1.5 di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR di/dt sensor detects changes in magetic field caused by ac current. 1111b Sign + 5 Bits -88.5 + EMF (electromotive force) .5 10 2 10 FREQUENCY-Hz 3 Magnetic field created by current (directly propor tional to current) Figure 7– Combined phase response of the digital integrator and phase compensator -1 -1.19mV/LSB 0. Setting the MSB of CH1OS register will turn on the integrator.5 Figure 4– Channel Offset Correction Range (Gain = 1) PHASE-DEGREES -89 -89.5 -4 The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. 10 GAIN-dB Waveform register will give an indication of the offset in the channel. The ADE7753 has a built-in digital integrator to recover the current signal from the di/dt sensor. -4. Figures 6 to 9 show the magnitude and phase response of the digital integrator. 1111b Sign + 5 Bits 0 -10 -20 -30 -40 -50 10 2 10 FREQUENCY-Hz 3 00h -50mV 0mV +50mV Offset Adjust Figure 6– Combined gain response of the digital integrator and phase compensator -88 3Fh 11.84mV/LSB 0. An integrator is therefore necessary to restore the signal to its original form. one should disable the digital integrator and the HPF. This offset can be canceled by writing an equal and opposite offset value to the relevant offset register. -90 -90.5 -6 40 45 50 55 FREQUENCY-Hz 60 65 70 Figure 8– Combined gain response of the digital integrator and phase compensator (40Hz to 70Hz) –10– REV.5 -3 Figure 5– Principle of a di/dt current sensor -3. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor. The EMF is a voltage signal which is proportional to the di/dt of the current. PrF 10/02 .61mV/LSB 1.77mV/LSB The current signal needs to be recovered from the di/dt signal before it can be used.

The default power on value in this register is FFFh. An active low in the IRQ output will also appear if the corresponding bit in the Interrupt Enable register is set to logic one. x8.579545MHz). When the digital integrator is switched off. x4.75 -89. PrF 10/02 The ADE7753 provides also the period measurement of the line.92 23. a more effective anti-aliasing filter is needed to avoid noise due to aliasing— see Antialias Filter. The Zerocross Time-out register can be written/read by the user and has an address of 1Dh . The phase lag response of LPF1 results in a time delay of approximately 0.85 -89.0 0.see ADE7753 Interrupts. The register is reset to its user programmed full scale value every time a zero crossing on Channel 2 is detected. the di/dt sensor has a 20dB/dec gain associated with it. x16 GAIN[7:5] PGA2 V2N ZERO CROSS LPF1 f-3dB = 140Hz 1.15 second (128/CLKIN × 212). LPF1 has a single pole at 156Hz (at CLKIN value of the Period register is approximately 7576d.PRELIMINARY TECHNICAL DATA ADE7753 -89.013% when the Channel 2. .see Temperature Measurement. Thus the maximum delay for an interrupt is 0.2ms/LSB when crossing and logic low on a negative going zero crossing on CLKIN=3.2 8@ 60Hz ZX ZX REFERENCE TO MULTIPLIER -63% to + 63% FS V2P V2 Channel 2 1 ADC 2 ZXTO detection bit Figure 11 . This zero crossing is used to produce an external zero cross signal (ZX) and it is also used in the calibration mode . the SAG pin will go active low. x2.9 -89. the ADE7753 can be used directly with a conventional current sensor such as current transformer (CT) or a low resistance current shunt.9Hz. The zero-crossing detection also drives one flag bit in the interrupt status register. and generates significant high frequency noise. The flag in the Interrupt status register as well as the IRQ output are reset to their default value when the Interrupt Status register with reset (RSTSTATUS) is read. the ZXTO flag in the Interrupt Status register is always set when the ZXTOUT register is decremented to zero .97ms (@ 60Hz) between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX. 45 50 55 FREQUENCY-Hz 60 65 70 40 Zero Crossing Timeout Figure 9– Combined phase response of the digital integrator and phase compensator (40Hz to 70Hz) Note that the integrator has a -20dB/dec attenuation and approximately -90° phase shift. As a result there will be a phase lag length of the register enables the measurement of line between the analog input signal V2 and the output of LPF1. the output of LPF1. The zero crossing signal is also used to initiate a temperature measurement on the ADE7753 . 16-bit internal register value ZXTOUT The ADE7753 has a zero crossing detection circuit on Channel 2.see Energy Calibration. The period register is an unsigned 15-bit register and is updated every period. When combined with a di/dt sensor. The resolution of the register is 128/CLKIN seconds per LSB. ZERO CROSSING DETECTION The zero crossing detection also has an associated time-out register ZXTOUT. This unsigned. The absence of a zero crossing is also indicated on the IRQ pin if the ZXTO enable bit in the Interrupt Enable register is set to logic one. The zero crossing signal ZX is generated from the line frequency is 60Hz. Figure 11 shows the mechanism of the zero crossing time out detection when the line voltage stays at a fixed DC level for more than CLKIN/128 x ZXTOUT seconds.see Serial Interface section. When the line frequency is 60Hz. –11– REV. However. Irrespective of the enable bit setting. If the register decrements to zero before a zero crossing is detected and the DISSAG bit in the Mode register is logic zero.7 -89. x1. The = 3.Zero crossing Time out detection PERIOD MEASUREMENT V2 LPF1 Figure 10– Zero cross detection on Channel 2 The ZX signal will go logic high on a positive going zero The resolution of this register is 2.579545MHz. the resulting magnitude and phase response should be a flat gain over the frequency band of interest. which represents 0.95 -90 -90.05 The phase response of this filter is shown in the Channel 2 Sampling section of this data sheet.8 PHASE-DEGREES -89. 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. frequencies as low as 13. Figure 10 shows how the zero cross signal is generated from the output of LPF1.

Figure 14 shows a line voltage exceeding a threshold which is set in the Voltage peak register (VPKLVL[7:0]). PEAK DETECTION Figure 12 . The SAG pin can also be used as a power supply monitor input to the MCU. If the supply is less than 4V ± 5% then the ADE7753 will go into an inactive state. for a number of line cycles. after they are multiplied by 2.see ADE7753 Interrupts. Writing 00h will put the sag detection level at zero. The power supply monitor has built-in hysteresis and filtering. Similarly. V2 VPKLVL[7:0] In addition to the detection of the loss of the line voltage signal (zero crossing). This is useful to ensure correct device operation at power up and during power down. The SAG pin will go logic low when the ADE7753 is in its inactive state. tains 03h the SAG pin will go active low at the end of the fifth line cycle for which the line voltage falls below the threshold. LINE VOLTAGE SAG DETECTION The ADE7753 can also be programmed to detect when the absolute value of the voltage or the current channel of one phase exceeds a certain peak value. Therefore writing 4Ah to the SAG Level register will put the sag detection level at full scale.On-Chip power supply monitor As can be seen from Figure 12 the trigger level is nominally set at 4V. the sag event is also recorded by setting the SAG flag in the Interrupt Status register. The tolerance on this trigger level is about ±5%.e.ADE7753 Peak detection SAGCYC[7:0] = 06H 6 half cycles SAG reset high when Channel 2 exceeds SAGLVL[7:0] SAG Both channel 1 and channel 2 are monitored at the same time. This gives a high degree of immunity to false triggering due to noisy supplies. the IRQ logic output will go active low. no energy will be accumulated when the supply voltage is below 4V. –12– REV. If the PKV enable bit is set to logic one in the Interrupt Mask register. The SAG pin will go logic high again when the absolute value of the signal on Channel 2 exceeds the sag level set in the Sag Level register. PrF 10/02 . If the SAG enable bit is set to logic one. i. This is shown in Figure 13 when the SAG pin goes high during the tenth line cycle from the time when the signal on Channel 2 first dropped below the threshold level. if the DISSAG bit in the Mode register is logic zero. The Voltage Peak event is recorded by setting the PKV flag in the Interrupt Status register. Figure 14 illustrates the behavior of the peak detection for the voltage channel. the ADE7753 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value. Since the Sag Cycle register (SAGCYC[7:0]) con- The contents of the VPKLVL and IPKLVL registers are respectively compared to the absolute value of channel 1 and channel 2. The Analog Supply (AVDD) is continuously monitored by the ADE7753. Peak Level Set Figure 13– ADE7753 Sag detection Figure 13 shows the line voltage fall below a threshold which is set in the Sag Level register (SAGLVL[7:0]) for five line cycles. The Sag Level register is compared to the most significant byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater.PRELIMINARY TECHNICAL DATA ADE7753 POWER SUPPLY MONITOR The ADE7753 also contains an on-chip power supply monitor. Shifting one bit left will give 4A30h. the IRQ logic output will go active low . As is the case when zero-crossings are no longer detected. Thus for example the nominal maximum code from LPF1 with a full scale signal on Channel 2 is 2518h—see Channel 2 sampling. The power supply and decoupling for the part should be such that the ripple at AV DD does not exceed 5V±5% as specified for normal operation. PKV reset low when RSTSTATUS register is read PKV Interrupt Flag (Bit 8 of STATUS register) Read RSTSTATUS register Channel 2 Full Scale SAGLVL[7:0] Figure 14 . Sag Level Set AVDD 5V 4V 0V Time ADE7753 Power-on Inactive Inactive State Active Inactive SAG The contents of the Sag Level register (1 byte) are compared to the absolute value of the most significant byte output from LPF1. after it is shifted left by one bit. the Current Peak event is recorded by setting the PKI flag in the Ineterrupt Status register—see ADE7753 Interrupts. This condition is illustrated in Figure 13 below.

PRELIMINARY TECHNICAL DATA ADE7753 Thus. As previously deMCU int. This will cause the IRQ line to be reset logic high (t2)—see Interrupt timing. In order to determine the source of the interrupt. This is achieved by carrying out a read from address 0Ch. On entering the ISR. The flag bits in the Status register are set irrespective of the state of the enable bits. Writing 00h will put the channel 1 detection level at zero. then the IRQ logic output goes active low. Multiplying by 2 will give 50A3D8h. the global interrupt mask will be cleared (same instruction cycle) and the external interrupt flag will cause the MCU to jump to its ISR once again. The contents of IPEAK represents the max absolute value observed on the channel 1 input. The IRQ logic output should be tied to a negative edge triggered external interrupt on the MCU. The contents of the VPEAK register corresponds to 2 times the maximum absolute value observed on the channel 2 input. ADE7753 INTERRUPTS ADE7753 Interrupts are managed through the Interrupt Status register (STATUS[15:0]) and the Interrupt Enable register (IRQEN[15:0]). This will ensure that the MCU does not miss any external interrupts. the nominal maximum code from the channel 1 ADC with a full scale signal is 2851ECh —see Channel 1 Sampling. Peak Level Record read command—see Interrupt timing. Mask Reset Jump to ISR Figure 15– ADE7753 interrupt management CS t1 t9 SCLK DIN DOUT Read Status Register Command 0 0 0 0 0 1 0 1 t11 DB7 t11 DB0 DB7 DB0 Status Register Contents IRQ REV.IPEAK and VPEAK respectively. When the MCU interrupt flag is cleared a read from the Status register with reset is carried out. Interrupt timing The ADE7753 Serial Interface section should be reviewed first before reviewing the interrupt timing. Using the ADE7753 Interrupts with an MCU The ADE7753 records the maximum absolute value reached by channel 1 and channel 2 in two different registers . If a subsequent interrupt event occurs during the ISR. Therefore. that event will be recorded by the MCU external interrupt flag being set again (t3). These registers are updated each time the absolute value of the Waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register. When carrying out a read with reset. flag set t3 Read Status with Reset (05h) ISR Action (Based on Status contents) ISR Return Global int. When an interrupt event occurs in the ADE7753. for example. flag ISR Sequence t2 Shown in Figure 15 is a timing diagram which shows a suggested implementation of ADE7753 interrupt management using an MCU. Clear MCU Mask Set int. On detection of the negative edge. Reading the RSTVPEAK and RSTIPEAK registers will clear their respective contents after the read operation. If an interrupt event occurs just as the Status register is being read. If the enable bit for this interrupt in the Interrupt Enable register is logic one. VPEAK and IPEAK are 24-bit unsigned registers. On returning from the ISR. At time t1 the IRQ line will go active low indicating that one or more interrupt events have occurred in the ADE7753. The IRQ output will go logic high on completion of the Interrupt Status register t1 IRQ MCU Program Jump to Global int. The Status register contents are used to determine the source of the interrupt(s) and hence the appropriate action to be taken. See the next section for a more detailed description. writing 50h to the IPKLVL register will put the channel 1 peak detection level at full scale and set the current peak detection to its least sensitive value. the system master (MCU) should perform a read from the Status register with reset (RSTSTATUS[15:0]). PrF 10/02 Figure 16– ADE7753 interrupt timing –13– . all interrupts should be disabled using the global interrupt enable bit. the ADE7753 is designed to ensure that no interrupt events are missed. the corresponding flag in the Status register is set to a logic one . At this point the MCU external interrupt flag can be cleared in order to capture interrupt events which occur during the current ISR. The detection is done when the content of the IPKLVL register is smaller than the incoming channel 1 sample.see Interrupt Status register. the MCU should be configured to start executing its Interrupt Service Routine (ISR). the event will not be lost and the IRQ logic output is guaranteed to go high for the duration of the Interrupt Status register data transfer before going logic low again to indicate the pending interrupt.

The resultant code is processed and placed in the Temperature register (TEMP[7:0]) approximately 26µs later (24 CLKIN cycles). If the loop gain is high enough the average value of the DAC output (and therefore the bit stream) will approach that of the input signal level. This noise shaping is also shown in Figure 18. Please note that temperature conversion will introduce a small amount of noise in the energy calculation. Only when a large number of samples are averaged will a meaningful result be obtained.. the noise is shaped by the integrator which has a high pass type response for the quantization noise. the data from Figure 18– Noise reduction due to Oversampling & Noise shaping in the analog modulator Antialias Filter Figure 17 also shows an analog low pass filter (RC) on the input to the modulator. The sigma-delta converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique.. This is what happens in the sigma-delta modulator.. The first is over-sampling. when the IRQ output goes low the MCU ISR must read the Interrupt Status register in order to determine the source of the interrupt. the ADE7753 will initiate a temperature measurement on the next zero crossing. In the ADE7753 the sampling clock is equal to CLKIN/4. To keep the oversampling ratio at a reasonable level. The converter is made up of two parts: the sigma-delta modulator and the digital low pass filter. Basically it means that frequency components in the input signal to the ADC which are higher than half the sampling rate of the ADC will appear in the sampled signal at a REV. an oversampling ratio of 4 is required just to increase the SNR by only 6dB (1-Bit).. If no interrupt is pending the IRQ output will stay high. the digital low pass filter. When bit 5 is set logic high in the Mode register..g. a noticeable error will accumulate in the resulting energy calculation over time. The 1-bit DAC in the feedback loop is driven by the serial data stream. the IRQ output will go low again. TEMPERATURE MEASUREMENT the 1-bit ADC is virtually meaningless. For any given input value in a single sampling interval. For simplicity reason. it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. Aliasing is an artifact of all sampled systems. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low pass filter. The temperature measurement is uncalibrated in the ADE7753 and has an offset tolerance that could be as high as ±20°C. oversampling alone is not an efficient enough method to improve the signal to noise ratio (SNR) in the band of interest. By over sampling we mean that the signal is sampled at a rate (frequency) which is many times higher than the bandwidth of interest.10100101. the IRQ output will go active low when the temperature conversion is finished.. ADE7753 also includes an on-chip temperature sensor. For example the sampling rate in the ADE7753 is CLKIN/4 (894kHz) and the band of interest is 40Hz to 2kHz.. The contents of the Temperature register are signed (2's complement) with a resolution of approximately 1 LSB/°C.. By averaging a large number of bits from the modulator the low pass filter can produce 24-bit data words which are proportional to the input signal level. PrF 10/02 –14– . A temperature measurement can be made by setting bit 5 in the Mode register. With the noise spread more thinly over a wider bandwidth. The IRQ output is held high until the last bit of the next 15-bit transfer is shifted out (Interrupt Status register contents)— see Figure 16.PRELIMINARY TECHNICAL DATA ADE7753 scribed. If enabled in the Interrupt Enable register (bit 5). The DAC output is subtracted from the input signal. the block diagram in Figure 17 shows a first order sigma-delta ADC. This filter is present to prevent aliasing. For example. If an interrupt is pending at this time. When reading the Status register contents. the IRQ output is set high on the last falling edge of SCLK of the first byte transfer (read Interrupt Status register command). When the zero crossing on Channel 2 is detected the voltage output from the temperature sensing circuit is connected to ADC1 (Channel 1) for digitizing. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. However. 1-Bit DAC 0 2kHz 447kHz 894kHz Figure 17– First Order Sigma-Delta (Σ−∆) ADC Frequency (Hz) A sigma-delta modulator converts the input signal into a continuous serial stream of 1's and 0's at a rate determined by the sampling clock. The temperature register will produce a code of 00h when the ambient temperature is approximately 70°C. If temperature conversion is performed frequently (e. the quantization noise in the band of interest is lowered—see Figure 18. MCLK/4 Noise 0 2kHz 447kHz 894kHz Frequency (Hz) Signal Analog Low Pass Filter INTEGRATOR Digital Low Pass Filter + LATCHED COMPARATOR + R C Σ - e VREF High resolution output from Digital LPF - 24 Noise . ADE7753 ANALOG TO DIGITAL CONVERSION Antialias filter (RC) Digital filter Shaped Signal Noise Sampling Frequency The analog-to-digital conversion in the ADE7753 is carried out using two second order sigma-delta ADCs. multiple times per second). This averaging is carried out in the second part of the ADC.

5kΩ 12.5V not 2. one needs to use an external voltage reference. the meter can be calibrated at multiple temperatures. The Active.e. will move into the band of interest for metering. The nominal reference voltage at the REFIN/OUT pin is 2. This is illustrated in Figure 21. one of four output sample rates may be chosen by using bits 11 and 12 of the Mode register (WAVSEL1.0).. the sensor has 20dB per decade gain.e.5kΩ Output Impedance 6kΩ REFIN/OUT 2.21V. The output sample rate may be 27. This will neutralize the -20dB per decade attenuation produced by the simple LPF.42V 12.7kΩ 12. The voltage of ADE7753 reference drifts slightly with temperature—see ADE7753 Specifications for the temperature coefficient specification (in ppm/°C) . When in waveform sample mode. Alternatively. For conventional current sensor. an external 2. REV.642.794V. However.0) to be read by the system master (MCU). For di/dt sensor such as Rogowski coil.144.42V.PRELIMINARY TECHNICAL DATA ADE7753 frequency below half the sampling rate. Note that the nominal reference value supplied to the ADCs is now 2. only frequencies near the sampling frequency. a simple RC filter (single pole LPF) with a corner frequency of 10kHz will produce an attenuation of approximately 40dBs at 894kHz—see Figure 18.42V. Maximum Load = 10µA PTAT 60µA 2.5V and an internal reference of 2. Real time compensation can be easily achieved using the on the on-chip temperature sensor.151 or 2851Fh.42V. The reference value used for Channel 1 is divided down to ½ and ¼ of the nominal value by using an internal resistor divider as shown in Figure 20.5V reference. The maximum code from the ADC is ±262. i.5165V.. care should be taken to offset the 20dB per decade gain coming from the di/dt sensor.144 Vout Therefore with a full scale signal on the input of 0. In waveform sampling mode the ADC outputs a signed 2’s Complement 24-bit data word at a maximum of 27.5/2.9kSPS. The 20dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensor.5V 1. However. if guaranteed temperature performance is needed. This is the reference voltage used for the ADCs in the ADE7753.6V 12. the ADC output code is nominally 165. e.642.5V be exceeded. Apparent Power and Energy calculation will remain uninterrupted during waveform sampling. i. Frequency components (arrows shown in black) above half the sampling frequency (also know as the Nyquist frequency. Channel 1 has three input range selections which are selected by dividing down the reference value used for the ADC in Channel 1. The value of the temperature drift varies from part to part.42×100% = 3% or from 0. i. this is equivalent to an input signal level of ±0.412 Decimal) and D7AE14h (-2. 7kSPS or 3.0492 × Vin × 262.5kΩ Figure 20 —ADE7753 Reference Circuit Ouput The REFIN/OUT pin can be overdriven by an external source. This will happen with all ADCs regardless of the architecture.25V or 0. Therefore. ADE7753 Reference circuit Figure 21 shows the ADC and signal processing chain for Channel 1. however. In waveform sampling mode the WSMP bit (bit 3) in the Interrupt Enable register must also be set to logic one.5kΩ Reference input to ADC Channel 1 (Range Select) 2.42V.2kHz. PrF 10/02 The waveform samples may also be routed to the WAVEFORM register (MODE[14:13] = 1. This allows the usage of very simple LPF (Low Pass Filter) to attenuate high frequency (near 900kHz) noise and prevents distortion in the band of interest. With the specified full scale analog input signal of 0.. CHANNEL 1 ADC Aliasing Effects Sampling Frequency image frequencies 0 2kHz 447kHz 894kHz Frequency (Hz) Figure 19 —ADC and signal processing in Channel 1 ADC transfer function Below is an expression which relates the output of the LPF in the sigma-delta ADC to the analog input signal level. 1. when using a di/dt sensor. One simple approach is to cascade two RC filters to produce the -40dB per decade attenuation needed.e. 40Hz . The interrupt request output IRQ signals a new sample –15– .412 Decimal).5V to 0. 894kHz. Code ( ADC ) = 3. In the example shown. 447kHz) get imaged or folded back down below 447kHz (arrows shown in grey).g.9kSPS (CLKIN/128).125V – see Analog Inputs section) the ADC will produce an output code which is approximately between 2851ECh (+2. any x% drift in the reference will result in 2x% deviation of the meter accuracy. Channel 1 Sampling Shown below in Figure 20 is a simplified version of the reference output circuitry. 14kSPS. However for specified performance it is not recommended that the full-scale input signal level of 0. 0.5kSPS—see Mode Register. The reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter. Figure 19 illustrates the effect. Since the reference is used for the ADCs in both Channel 1 and 2. Both ADCs in the ADE7753 are designed to produce the same output code for the same input signal level.5V (or 0. This has the effect of increasing the nominal analog input signal range by 2.

IRQ SCLK Read from WAVEFORM DIN DOUT 0 0 0 01 Hex Sign RMS register is equivalent to one LSB of a channel 1 waveform sample. 1.6V GAIN[4:3] REFERENCE HPF DIGITAL INTEGRATOR* CURRENT RMS (IRMS) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION Channel 1 (Current Waveform) Data Range After integrator (50Hz) PGA1 ADC 1 ∫ 50Hz 1EF73Ch 000000h Channel 1 (Current Waveform) Data Range V1 0. Irms = Irms 2 0 + IRMSOS × 32768 where Irmso is the RMS measurement without offset correction.i(t) 2851ECh 00h D7AE14h Irms(t) IRMSOS[11:0] SIGN 2 25 2 26 2 27 2 17 2 16 2 15 1C82B3h 00h HPF Channel 1 24 LPF3 + Σ 24 IRMS Channel 1 DATA . WHEN DISABLED. the ADC will produce an output code which is approximately ±2. 31.21V. taking the average and obtaining the square root: Vrms = 1 N 2 ⋅ ∑V (i ) (2) N i =1 ADE7753 calculates simultaneously the RMS values for Channel 1 and Channel 2 in different register. The update rate of the channel 1 RMS measurement is CLKIN/4.3mV. An offset may exist in the RMS calculation due to input noises that are integrated in the DC component of V2(t). The channel 1 RMS value is stored in an unsigned 24-bit register (IRMS). Current Signal .5mV.768 LSB of the square of the Channel 1 RMS register.125V. This is 12-bit signed registers which can be used to remove offset in the channel 1 RMS calculation. 0. E631F8h Figure 21 —ADC and signal processing in Channel 1 –16– REV.642. x16 V1P V1 V1N GAIN[2:0] 2. One LSB of the channel 1 The ADE7753 incorporates a channel 1 RMS offset compensation register (IRMSOS).868. 0. The timing is shown in Figure 22. Figure 23 shows the detail of the signal processing chain for the RMS calculation on channel 1. FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE FREQUENCY RESPONSE.6mV.467d with full scale AC inputs.868.412d—see Channel 1 ADC.46% of measurement error at -60dB down of full scale. 0. 0V 2851ECh 000000h E108C4h D7AE14h Analog Input Range 2851ECh ADC Output word Range 000000h D7AE14h 60Hz 19CE08h 000000h Channel 1 (Current Waveform) Data Range After Integrator (60Hz) *WHEN DIGITAL INTEGRATOR IS ENABLED. x2.42V. PrF 10/02 . The 24-bit data word is right justified .see ADE7753 Interrupt.see ADE7753 Serial Interface.PRELIMINARY TECHNICAL DATA ADE7753 availability by going active low. The channel 1 RMS value is processed from the samples used in the channel 1 waveform sampling mode. Assuming that the maximum value from the Channel 1 RMS calculation is 1.Channel 1 RMS signal processing The interrupt request output IRQ stays low until the interrupt routine reads the Reset Status register . THE OUTPUT WILL NOT BE FURTHER ATTENUATED.5V.5V. then 1 LSB of the channel 1 RMS offset represents 0.25V. 62. The 24-bit waveform samples are transferred from the ADE7753 one byte (8-bits) at a time.24 bits Figure 22 – Waveform sampling Channel 1 Figure 23 . x4. with the most significant byte shifted out first.467d (1C82B3h). x8. 1 LSB of the Channel 1 RMS offset are equivalent to 32. The offset calibration will allow the content of the IRMS register to be maintained at zero when no input is present on channel 1. x1. Channel 1 RMS calculation With the specified full scale analog input signal of 0. Channel 1 RMS offset compensation Root Mean Square (RMS) value of a continuous signal V(t) is defined as: Vrms = 1 T 2 () ⋅ ∫ V t dt T 0 (1) For time sampling signals. The equivalent RMS values of a full-scale AC signal is 1. rms calculation involves squaring the signal. 15.

064% of measurement error at -60dB down of full scale. the phase (1V differential). However. 14kSPS.561. then 1 LSB of the channel 2 RMS offset represents 0. However like Channel 1.42V x1. The RMS value will be slightly attenuated because of LPF1. PrF 10/02 DAE8h D7AEh . then the signal at the output of LPF1 will be attenuated by about 8%. the phase error between Channel 1 and Channel 2 is zero from DC to 3. Channel 2 RMS value is stored in the unsigned 24-bit VRMS register. Figure 26 . 62. 2. 8 and 16. energy measurement.9kSPS. Channel 2 waveform sample is a 16-bit word and sign extended to 24 bits.5mV. The equivalent RMS value of this full-scale AC signal is approximately 1. The interrupt request output IRQ signals a sample availability by going active low. For normal operation. low pass filter with a cutoff frequency of 140Hz. x8.73dB 50 Hz.5kSPS— see Mode Register.561. The offset calibration allows the contents of the VRMS register to be maintained at zero when no voltage is applied. The update rate of the channel 2 RMS measurement is CLKIN/4. The timing is the same as that for Channel 1 and is shown in Figure 22. Vrms = Vrmso + VRMSOS 2852h 2518h LPF Output word Range where Vrmso is the RMS measurement without offset correction. -23.1 and WSMP = 1) the ADC output code scaling for Channel 2 is not the same as Channel 1. When in waveform sample mode.5kHz.5V. The available output sample rates are 27. -0. the output of the ADC is passed –17– REV. This is all that have a PGA with gain selections of 1.5V. As can be seen from the plots.5V at PGA gain of 1). 0. the ADC output is passed through a single pole. When HPF is enabled. Channel 2 does response is almost zero from 45Hz to 1kHz. For example if the line frequency is 60Hz. For is required in typical energy measurement applications.125V. -0. before being passed to the Waveform register. PHASE COMPENSATION 0000h When the HPF is disabled. the outputs from the ADC swings between 2852h and D7AEh (±10. An offset may exist in the RMS calculation due to input noises and dc offset in the input samples. x16 GAIN[7:5] PGA2 V2N V1 Analog Input Range 0.52dB 0 -10 -2 -20 -4 50 Hz. the differential voltage signal between V2P and V2N should not exceed 0. Channel 2 has only one analog input range response of the filter. With the specified full scale AC analog input signal of 0.Channel 2 RMS signal processing Channel 2 RMS offset compensation H(f) = 2 1 + 60Hz 140Hz ( 1 ) = 0. Also shown in Figure 30 is the magnitude Unlike Channel 1.400d with full scale AC inputs. Channel 1 has a phase response illustrated in Figure 25 – ADC and Signal Processing in Channel 2 Figures 28 & 29. A HPF is not required to remove any DC offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation.V(t) -80 -16 2518h 0h VRMSOS[11:0] SGN 29 28 2 2 2 1 2 0 -90 1 10 10 2 10 3 -18 DAE8h Frequency (Hz) VRMS[23:0] LPF3 LPF1 Channel 2 + + 17D338h 00h Figure 24 – Magnitude & Phase response of LPF1 S The LPF1 has the effect of attenuating the signal. Assuming that the maximum value from the channel 2 RMS calculation is 1.PRELIMINARY TECHNICAL DATA ADE7753 CHANNEL 2 ADC Channel 2 Sampling In Channel 2 waveform sampling mode (MODE[14:13] = 1.2° Phase (°) -40 -8 -50 -10 Figure 26 shows the details of the signal processing chain for the RMS calculation on Channel 2. This is a 12-bit signed registers which can be used to remove offset in the channel 2 RMS calculation.see Channel 2 ADC. 0. 7kSPS or 3.919 = −0. -19. 4.322 Decimal).400 (17D338h) in the VRMS register. 2. the outputs from the LPF1 swings between 2518h and DAE8h at 60 Hz. 0 directly to the multiplier and is not filtered.25mV 0V REFERENCE V2P V2 ADC 2 LPF1 ACTIVE AND REACTIVE ENERGY CALCULATION VRMS CALCULATION AND WAVEFORM SAMPLING (PEAK/SAG/ZX) The ADE7753 incorporates a channel 2 RMS offset compensation register (VRMSOS). Channel 2 RMS calculation 60 Hz. -60 -12 -70 -14 Gain (dBs) Voltage Signal . 31. The plots in Figure 24 shows the magnitude and phase response of this filter. x2. With maximum voltage input (±0. The channel 2 RMS value is processed from the samples used in the channel 2 waveform sampling mode.5V. one of four output sample rates can be chosen by using bits 11 and 12 of the Mode register.73dB Note LPF1 does not affect the power calculation.7° -30 -6 60 Hz.25V. x4. 1 LSB of the channel 2 RMS offset are equivalent to 1 LSB of the RMS register. The signal processing chain in Channel 2 is illustrated in Figure 25.

1 10 PHASE-DEGREES 2 10 FREQUENCY-Hz 3 10 4 Figure 28 – Combined Phase Response of the HPF & Phase Compensation (10Hz to 1kHz) 0. thus reducing the amount of time delay by 4. The resolution of the phase adjustment allows the introduction of a phase lead in increment of 0. so that writing 0Dh to the register gives zero delay. a phase lead must also be introduced into Channel 2.2 0.1 0 -0.2 HPF 0. 0Bh represents -2 because the register is centered with zero at 0Dh.1° to 0. PrF 10/02 . The ADE7753 allows a small time delay or time advance to be introduced into the signal processing chain in order to compensate for small phase errors. A time advance of 4. despite being internally phase compensated the ADE7753 must work with transducers which may have inherent phase errors.6 0.1 -0. One LSB is equivalent to 2.1° to 0. The phase lead is achieved by introducing a time advance into Channel 2.18 V1 0 0 1 0 1 1 PHCAL[5:0] -100µs to +34µs 0.18lead at 60Hz) 0Bh in PHCAL[5:0] GAIN-dB V2P 0.. The ADE7753 provides a means of digitally calibrating these small phase errors.048° at the fundamental (i.2 0.22µs × 60Hz).PRELIMINARY TECHNICAL DATA ADE7753 However.5 0.05 -0.12 0.048°.16 LPF2 0.5°.e. or equivalently.3° is not uncommon for a CT (Current Transformer).1° at line frequency of 60Hz. In order to cancel the lead (0.4 0.48µs. These phase errors can vary from part to part and they must be corrected in order to perform accurate power calculations.3 0. The resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time.579545MHz).15 0. By changing the PHCAL register. a phase lead of approximately 0.02 60Hz 0 40 45 50 55 FREQUENCY-Hz 60 65 70 60Hz Figure 27 – Phase Calibration Figure 30 – Combined Gain Response of the HPF & Phase Compensation ACTIVE POWER CALCULATION Power is defined as the rate of energy flow from source to load. With a line frequency of 60Hz this gives a phase resolution of 0. this technique should only be used for small phase errors in the range of 0. V1P V1 V1N 24 PGA1 0.8µs to +33. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. The unit of power is the watt or joules/ –18– REV.9 0. The errors associated with phase mismatch are particularly noticeable at low power factors. For example a phase error of 0. the time delay in the Channel 2 signal path can change from –100.2 40 45 50 55 FREQUENCY-Hz 60 65 70 Figure 29 – Combined Phase Response of the HPF & Phase Compensation (40Hz to 70Hz) 0. Figure 27 illustrates how the phase compensation is used to remove a 0.18 ADC 1 24 0.08 V2 0. Because the compensation is in time.15 -0.1°) in Channel 1.8 0.1° phase lead in Channel 1 due to the external transducer.1 0.48µs (0.04 0.7 0.22µs time delay or advance.48µs / LSB 5 0 V2 V1 Channel 2 delay reduced by 4. The Phase Calibration register (PHCAL[5:0]) is a 2’s complement signed single byte register which has values ranging from 21h (-31 in Decimal) to 1Fh (31 in Decimal).1 PHASE-DEGREES 0.06 0. The register is centered at 0Dh. 360° × 2.14 1 V2 V2N PGA2 ADC 2 Delay Block 4.6µs (CLKIN = 3.05 -0. It is defined as the product of the voltage and current waveforms.48µs is made by writing -2 (0Bh) to the time delay block.

i.e. 800h = -2048 Dec (signed 2’s Complement) and power output is scaled by –50%.PRELIMINARY TECHNICAL DATA ADE7753 sec. This process is illustrated graphically in Figure 31. v() = t i() = t ω 2V sin ( t ) ω 2 I sin ( t ) (1) (2) where V = rms voltage.i(t) 2 5 2 -6 2 -7 2 -8 24 For Waveform Sampling 19999h LPF2 24 MULTIPLIER + + Σ WGAIN[11:0] 32 For Energy Accumulation Active Power Signal . The dc component of the instantaneous power signal is then extracted by LPF2 (Low Pass Filter) to obtain the active power information. ω − VI cos( t ) Since LPF2 does not have an ideal “brick wall” frequency response—see Figure 32. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 3 . P is referred to as the Active or Real Power.P CCCCDh V Voltage Signal . Note that the output range changes depending on the contents of the Watt Gain register. This ripple is sinusoidal and has a frequency equal to twice the line frequency. and the HPF APOS[15:0] sgn 2 6 I Current Signal . CCCCDh 00000h Current i(t) = √2×I×sin(ωt) Voltage v(t) = √2×V×sin(ωt) Figure 31 – Active Power Calculation For example when 7FFh is written to the Watt Gain register the Power output is scaled up by 50%. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The minimum output range is given when the Watt Gain register contents are equal to 800h. PrF 10/02 –19– .p(t) 19999Ah 000000h Figure 33– Active Power Signal Processing REV.v(t) Instantaneous Power Signal . The gain is adjusted by writing a 2’s complement 12-bit word to the Watt Gain register. Similarly. I = rms current. Note that for when reading the waveform samples from the output of LPF2. Since the ripple is sinusoidal in nature it will be removed when the Active Power signal is integrated to calculate Energy – see Energy Calculation. 0 p ( ) = v( ) × i ( ) t t t p( ) = t VI (3) dBs -4 -8 The average power over an integral number of line cycles (n) is given by the expression in Equation 4. As explained. Instantaneous Power Signal -24 1.0Hz 10Hz 30Hz 100Hz Frequency Figure 32 —Frequency Response of LPF2 p(t) = V×I-V×I×cos(2ωt) Active Real Power Signal = V x I 19999Ah Figure 33 shows the signal processing chain for the ActivePower calculation in the ADE7753. The gain of the Active Energy can be adjusted by using the multiplier and Watt Gain register (WGAIN[11:0]). This is the relationship used to calculate active power in the ADE7753. Shown in Figure 34 is the maximum code (in hex) output range for the Active Power signal (LPF2)..   WGAIN  Output WGAIN =  Active Power × 1 +   212   V. the Active Power signal will have some ripple due to the instantaneous power signal. 2047/212 = 0.5. I. VI. Equation 3 gives an expression for the instantaneous power signal in an ac system. 7FFh = 2047d.0Hz 3. the Active Power is calculated by low pass filtering the instantaneous power signal. -12 1 nT P= ∫ p (t )dt = VI nT 0 -16 (4) -20 where T is the line cycle period. Below is the expression that shows how the gain adjustment is related to the contents of the Watt Gain register.

Figure 36 shows this energy accumulation for full scale signals (sinusoidal) on the analog inputs. REV. the fastest integration time will occur when the Watt Gain register is set to maximum full scale. the ADE7753 can be configured to issue an interrupt (IRQ) when the Active Energy register is half-full (positive or negative) or when an over/under flow occurs. This discrete time accumulation or summation is equivalent to integration in continuous time. WDIV is an 8-bit unsigned register. As shown.1µs (4/CLKIN). illustrate the minimum period of time it takes the energy register to roll-over when the Active Power Gain register contents are 7FFh.0000h UPPER 24 BITS ARE ACCESSIBLE THROUGH AENERGY[23:0] REGISTER 80.0000h Current Channel LPF2 APOS [15:0] + + WDIV[7:0] 46 0 Σ WGAIN[11:0] Figure 36 . 7FFh. A read to the RAENERGY register will return the content of the AENERGY register and the upper 24-bit of the internal register is clear after a read to AENERGY register. Equation 7 below expresses the relationship  ∞ E = ∫ p(t )dt = Lim∑ p(nT ) × T   t → 0  n =1 (7) 00.FFFFh WGAIN = 7FFh WGAIN = 000h WGAIN = 800h 3F. The output of the multiplier is divided by WDIV. The three curves displayed. If the value in the WDIV register is equal to 0 then the internal Active Energy register is divided by 1. therefore negative energy will be subtracted from the Active Energy contents.e.1µs (4/CLKIN). Conversely Energy is given as the integral of Power. As well as calculating the Energy this integration removes any sinusoidal components which may be in the Active Power signal. Integration time under steady load As mentioned in the last section.5kSPS—see Figure 22.see Figure 36. power is defined as the rate of energy flow. The Active Power signal in the Waveform register is continuously added to the internal Active Energy register.P* 4 CLKIN WAVEFORM REGISTER VALUES OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER time (nT) Figure 35 – ADE7753 Active Energy Calculation The discrete time sample period (T) for the accumulation register in the ADE7753 is 1. The Active Power signal can be read from the Waveform register by setting MODE[14:13] = 0. the Active Power signal is accumulated in an internal 48-bit signed register. The upper 24 bit of this register is accessible through a read to the Active Energy register (AENERGY[23:0]). This can be used to calibrate the Active Power (or Energy) calculation in the ADE7753. 23 AENERGY[23:0] 0 40.. Like the Channel 1 and Channel 2 waveform sampling modes the waveform date is available at sample rates of 27.2 8 12.FFFFh Active Power Output 133333h CCCCDh 66666h 00000h F9999Ah F33333h ECCCCDh Positive Power Negative Power 000h 7FFh 800h WGAIN[11:0] Active Power Calibration Range Figure 34 – Active Power Calculation Output Range ENERGY CALCULATION As stated earlier. i.PRELIMINARY TECHNICAL DATA ADE7753 maximum range is given by writing 7FFh to the Watt Gain register.5 Time (minutes) Where n is the discrete time sample number and T is the sample period. the discrete time sample period (T) for the accumulation register is 1. Conversely if the power is negative the energy register would under flow to full scale positive (7FFFFFh) and continue decreasing in value. AENERGY[23:0] 7F.0000h 4 6. As shown in Figure 35. Note that the energy register contents will roll over to fullscale negative (800000h) and continue increasing in value when the power or energy flow is positive . P= dE dt (5) Where P = Power and E = Energy. 7kSPS or 3. After dividing by WDIV. 000h and 800h.Energy register roll-over time for full-scale power (Minimum & Maximum Power Gain) Voltage Channel OUTPUT LPF2 T Active Power Signal .9kSPS. the active energy is accumulated in a 48-bit internal energy accumulation register. The Active Energy register (AENERGY[23:0]) represents the upper 24 bits of this internal register. 14kSPS. PrF 10/02 –20– . This addition is a signed addition.0 and setting the WSMP bit (bit 3) in the Interrupt Enable register to 1. This relationship can be expressed mathematically as Equation 5. By using the Interrupt Enable register. Figure 35 shows a graphical representation of this discrete time integration or accumulation. The Watt Gain register is used to carry out power calibration in the ADE7753. E = ∫ Pdt (6) The ADE7753 achieves the integration of the Active Power signal by continuously accumulating the Active Power signal in an internal non-readable 56-bit Energy register.

g. The maximum output frequency.861 × 100% = 0.FFFFh before it overflows. After initial calibration at manufacturing. The Active Power Offset register has a resolution equal to 1/256 LSB of the Waveform register. hence the power offset correction resolution is 0. Note that for values where CFDEN>CFNUM. with AC input signals at full-scale and CFNUM=00h & CFDEN=00h. the average word value from each LPF2 is CCCCDh . single wire. the manufacturer or end customer will often verify the energy meter calibration. An offset may exist in the power calculation due to cross talk between channels on the PCB or in the IC itself. 1 LSB in the LPF2 output has a measurement error of 1/838. CFNUM[11:0] and CFDEN[11:0]. the performance of the CF frequency is not guaranteed.       VI = VI −  p(t ) 4  ⋅ cos( π fl t ) 2   2fl   1+      8 . Two hundred fifty six LSBs (APOS=0100h) written to the Active Power Offset register are equivalent to 1 LSB in the Waveform Sample register.00047%/LSB (0. If the value zero is written to any of these registers. optically isolated interface to external calibration equipment. to set the CF frequency.861 (838.1 or 7FFF. At -60dB down on Channel 1 (1/1000 of the Channel 1 full-scale input). One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency which is proportional to the energy or active power under steady load conditions.861 in Decimal) when inputs on Channels 1 and 2 are both at full-scale. These are unsigned 12-bit registers which can be used to adjust the CF frequency to a wide range of values. is approximately 23 kHz.1Hz by writing FFh to the CFDEN register.562kHz while the contents of CFDENare zero (000h). 60Hz) From Equation 6       VI 4 E (t ) = VIt −   ⋅ sin( π fl t ) 2   2fl    4π fl 1 +  8. PrF 10/02 From Equation 11 it can be seen that there is a small ripple in the energy calculation due to a sin(2ωt) component. FFFFh × 1. Under steady load conditions the output frequency is proportional to the Active Power.PRELIMINARY TECHNICAL DATA ADE7753 With full-scale sinusoidal signals on the analog inputs and the WGAIN register set to 000h.9 2 ADE7753 also provides energy to frequency conversion for calibration purposes. the register values would be adjust to a ratio (CFNUM+1)/(CFDEN+1) of one. This is a signed 2’s complement 16bit register which can be used to remove offsets in the active power calculation—see Figure 33.12 min s CCCCDh When WDIV is set to a value different from 0. If the ratio of the registers (CFNUM+1)/ (CFDEN+1) is greater than one. ENERGY TO FREQUENCY CONVERSION H (f ) = 1+ 1 f2 8 . Time = TimeWDIV=0 x WDIV POWER OFFSET CALIBRATION (8) The ADE7753 also incorporates an Active Power Offset register (APOS[15:0]).. the value one would be applied to the register. The offset calibration will allow the contents of the Active Power register to be maintained at zero when no power is being consumed. The ratio (CFNUM+1)/ (CFDEN+1) should be smaller than one to assure proper operation. 11 CFNUM[11:0] (9) The Active Power signal (output of LPF2) can be rewritten as. An REV. Assuming the average value outputs from LPF2 is CCCCDh (838. The Active Energy calculation is shown by the dashed straight line and is equal –21– . the average word value outputs from LPF2 is 838. then the output frequency can be set to 6. These frequency scaling registers are 12-bit registers which can scale the output frequency by 1/212 to 1 with a step of 1/212. The output frequency will have a slight ripple at a frequency equal to twice the line frequency.FFFF.12 µs = 187. This output frequency can provide a simple. For example if the output frequency is 1.5s = 3.119% of the average value. This is filtered by LPF2 which has a magnitude response given by Equation 9. Equation 3 gives an expression for the instantaneous power signal.861/1. the integration time varies as shown on Equation 8. Figure 37 illustrates the Energy-to-Frequency conversion in the ADE7753. The DFC generates a pulse each time one LSB in the Active Energy register is accumulated. CFNUM should always be set to a value less than CFDEN.000). The ADE7753 incorporates two registers. FFFF.9       0 Energy DFC 23 AENERGY[23:0] 0 CF (11) 11 CFDEN[11:0] 0 Figure 37– ADE7753 Energy to Frequency Conversion A Digital to Frequency Converter (DFC) is used to generate the CF pulsed output. This is shown graphically in Figure 38. the integration time under these conditions with WDIV=0 is calculated as follows: output pulse is generated when (CFDEN+1)/(CFNUM+1) number of pulses are generated at the DFC output. Time = 3FFF .119%/ 256) at -60dB. This is due to imperfect filtering of the instantaneous power signal to generate the Active Power signal – see Active Power Calculation.9    (10) where fl is the line frequency (e.see Figure 31. The maximum positive value which can be stored in the internal 47-bit register is 246 .

Also averaging the output frequency by using a longer gate time for the counter will achieve the same results. The number of half line cycles is specified in the LINECYC register (Address 1Ch). the IRQ output will also go active low. f . This eliminates any ripple in the energy calculation.535 half line cycles. The result of all subsequent line cycle accumulation is correct. The ADE7753 is placed in line cycle energy accumulation mode by setting bit 7 (CYCMODE) in the Mode register.9       (12) where n is a integer and T is the line cycle period.     nT   nT VI E (t ) = ∫ VI dt −  2  ⋅ ∫ cos( π f t ) dt   f 2  0 0  1 +  8 . The sinusoidal ripple in the Active Energy calculation is also shown. at the end of a line cycle energy accumulation cycle the CYCEND flag in the Interrupt Status register is set (bit 2). As a consequence some of the sinusoidal ripple is observable in the frequency output. Since the average value of a sinusoid is zero. the energy calibration can be greatly simplified and the time required to calibrate the meter can be significantly reduced. Thus the IRQ line can also be used to signal the completion of the line cycle energy accumulation. The reason is simply that at higher output frequencies the integration or averaging time in the Energy-to-Frequency conversion process is shorter. especially at higher output frequencies. this ripple will not contribute to the energy calculation over time.535. as shown in Figure 39. E(t) calibration is invalid and should be ignored. ignoring any occurrence of negative power above or below the no load threshold as shown in Figure 40. the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65. t) V 4. However. By using the line cycle energy accumulation mode. POSITIVE ONLY ACCUMULATION MODE In Positive Only Accumulation mode. the energy accumulation is done only for positive power. Since the sinusoidal component is integrated over a integer number of line cycles its value is always zero. Choosing a lower output frequency at CF for calibration can significantly reduce the ripple. the 16-bit LINECYC register can hold a maximum value of 65. Note that the result of the first Figure 39 – Energy Calculation in Line Cycle Energy Accumulation Mode Note that in this mode. Another calibration cycle will start as long as the CYCMODE bit in the Mode register is set.9Hz) U F. the energy accumulation of the ADE7753 can be synchronized to the Channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles. The ripple will get larger as a percentage of the frequency at larger loads and higher output frequencies. The ADE7753 is placed in positive only Active Energy No-load threshold Active Power No-load threshold IRQ PPOS PNEG PPOS PNEG PPOS PNEG Interrupt Status Registers –22– Figure 40 – Energy Accumulation in Positive Only Accumulation Mode REV.535 / 120Hz = 546 seconds. In Line Cycle Energy Accumulation Mode the ADE7753 accumulates the active power signal in the LAENERGY register (Address 04h) for an integral number of line cycles. The advantage of summing the active energy over an integer number of half line cycles is that the sinusoidal component in the active energy is reduced to zero. The ADE7753 can accumulate active power for up to 65. From Equations 6 and 10. T W l l l LPF1 WDIV[7:0] 23 FROM CHANNEL 2 ADC ZERO CROSS DETECTION 0 LAENERGY[23:0] ACCUMULATE ACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LAENERGY REGISTER AT THE END OF LINECYC LINE-CYCLES t Figure 38 – Output frequency ripple CALIBRATION CONTROL LINECYC[14:0] LINE CYCLE ENERGY ACCUMULATION MODE In Line Cycle Energy Accumulation mode. S F . In other words. it translates to a total duration of 65. Because the active power is integrated on an integral number of line cycles. f (1+ 2.PRELIMINARY TECHNICAL DATA ADE7753 to V x I x t. Therefore: E = ∫ VIdt + 0 nT 0 (13) (14) VIt E(t) = VInT + Output from LPF2 + Σ 46 0 − R VI sin(4. the ripple can be observed in the frequency output. f / 8. If the CYCEND enable bit in the Interrupt Enable register is enabled. PrF 10/02 .535 half line cycles. At 60Hz line frequency. Energy is calculated more accurately and in a shorter time because integration period can be shortened.

PrF 10/02 –23– . The number of half line cycles is specified in the LINECYC register. The DC component of the instantaneous reactive power signal is then extracted by a low pass filter to obtain the reactive power information. For single phase applications. In this case. active and reactive power. NO LOAD THRESHOLD 90 DEGREE PHASE SHIFT Instantaneous Reactive Power Signal . 0 LVARENERGY[23:0] LINECYC[14:0] Figure 41 . PPOS and PNEG. The default setting for this mode is off. The instantaneous reactive power signal Rp(t) is generated by multiplying the channel 1 and channel 2. it is also useful to provide the sign of the reactive power if it is desirable to use triangular method to calculate reactive power. Note that the reactive power is equal to the DC component of the instantaneous reactive power signal Rp(t) in Equation 17. RP = 1 nT nT ∫ Rp(t )dt = VI sin(θ ) 0 (18) where T is the line cycle period. REACTIVE POWER CALCULATION Reactive power is defined as the product of the voltage and current waveforms when one of this signal is phase shifted by 90º. going from negative to positive or positive to negative. Transitions in the direction of power flow. If the CYCEND mask bit in the Interrupt Mask register is enabled. Compare this value to the IEC1036 specification which states that the meter must start up with a load equal to or less than 0. The resulting waveform is called the instantaneous reactive power signal. The angle θ between the Active Power and the Apparent Power generally represents the phase shift due to non-resistive loads. The ADE7753 accumulates the Reactive Power signal in the LVARENERGY register for an integer number of half cycles. the phase of the channel 1 is shifted by +90º. The ADE7754 can accumulate Reactive Power for up to 65535 combined half cycles. At the end of an energy calibration cycle the CYCEND flag in the Interrupt Status register is set. Equation 20 gives an expression of the instantaneous power signal in an ac system with a phase shift.Rp(t) I Π 2 MULTIPLIER + + Σ 47 0 V ACCUMULATE ACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LVARENERGY REGISTER AT THE END OF LINECYC LINE CYCLES 23 LPF1 FROM CHANNEL 2 ADC ZERO CROSS DETECTION CALIBRATION CONTROL The ADE7753 includes a "no load threshold" feature that will eliminate any creep effects in the meter.0167% of the full-scale output frequency of the multiplier. REV. APPARENT POWER CALCULATION Apparent power is defined as the amplitude of the vector sum of the Active and Reactive powers -see Figure 42. V = rms voltage and I = rms current. The ADE7753 accomplishes this by not accumulating energy if the multiplier output is below the "no load threshold". Rp (t ) = v (t ) × i ' (t ) Rp (t ) = VI sin(θ ) + VI sin( 2ωt + θ ) (17) The average power over an integral number of line cycles (n) is given by the expression in Equation 18. The Interrupt Status Registers. This threshold is 0. the IRQ output will also go active low. show which transition has occurred.001% of the full-scale output frequency of the multiplier. This standard translates to . as shown in Figure 41. Re active Energy = sign(Re active Energy) × Apparent Energy2 − Active Energy2 Where θ is the phase difference between the voltage and current channel. The ADE7753 also provides an accurate measurement of the apparent power. θ represents the angle between the voltage and the current signals.4% Ib. Thus the IRQ line can also be used to signal the end of a calibration. Figure 41 shows the signal processing in the Reactive Power calculation in the ADE7753.Reactive Power Signal Processing v (t ) = 2 V sin(ωt + θ ) i( t ) = 2 I sin( ωt ) i' ( t ) = 2 I sin( ωt + π 2 ) (15) (16) The features of the Reactive Energy accumulation are the same as the Line Active Energy accumulation. This is the relationship used to calculate reactive power in the ADE7753. The user can choose to determine reactive energy through the mathematical relationship between apparent.PRELIMINARY TECHNICAL DATA ADE7753 accumulation mode by setting the MSB of the MODE register (MODE[15]). The sign of the reactive energy can be found by reading the result from the LVARENERGY register at the end of a reactive energy accumulation cycle. RP is referred to as the Reactive Power. See ADE7753 Register Descriptions. set the IRQ pin to active low if the Interrupt Enable register is enabled. LINECYC is an unsigned 16-bit register. The Reactive Energy accumulation in the ADE7753 not only provides the reactive energy calculated using the phase shift method. Equation 17 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90º.

For example when 7FFh is written to the VA Gain register the Power output is scaled up by 50%.Apparent Power Calculation Output range Apparent Power Offset Calibration The Apparent Power (AP) is defined as Vrms x Irms. 7FFh = 2047d. The Apparent Energy register (VAENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Similarly.5. The gain is adjusted by writing a 2’s complement.v(t) 17D338h 00h VAGAIN The Apparent Energy is given as the integral of the Apparent Power. 800h = -2047 Dec (signed 2’s Complement) and power output is scaled by –50%. As no additional offsets are created in the multiplication of the RMS values. This expression is independent from the phase angle between the current and the voltage.PRELIMINARY TECHNICAL DATA ADE7753 Apparent Power Reactive Power θ Active Power writing 7FFh to the Apparent Power Gain register.1µs (4/CLKIN). Figure 43 illustrates graphically the signal processing in each phase for the calculation of the Apparent Power in the ADE7753. there is no specific offset compensation in the Apparent Power signal processing.Power triangle v (t ) = i (t ) = ω 2 Vrms sin( t ) 103880h AD055h 5682Bh 00000h 000h 7FFh 800h ω 2 Irms sin( t + θ ) (19) p(t ) = v (t ) × i (t ) p(t ) = Vrms I rms cos(θ ) − Vrms I rms cos( 2ωt + θ ) VAGAIN[11:0] Apparent Power Calibration Range Voltage and Current channel inputs: 0. Below is the expression that shows how the gain adjustment is related to the contents of the VA Gain register. 12-bit word to the VAGAIN register.i(t) AD055h 1C82B3h 00h Apparent Power Signal . Apparent Power 100% FS Apparent Power 150% FS Apparent Power 50% FS Figure 42 . The channel 1 and channel 2 RMS values are then multiplied together in the Apparent Power signal processing. Figure 44 shows a graphical representation of this discrete time integration or accumulation. The offset compensation of the Apparent Power measurement is done by calibrating each individual RMS measurements.5V / GAIN (20) Figure 44. The discrete time sample period (T) for the accumulation register in the ADE7753 is 1. The Apparent Power signal is continuously added to the internal register.Apparent Power Signal Processing The gain of the Apparent Energy can be adjusted by using the multiplier and VA Gain register (VAGAIN[11:0]). The Apparent Power is calculated with the Current and Voltage RMS values obtained in the RMS blocks of the ADE7753. 2047/212 = 0. PrF 10/02 . Equation 23 below expresses the relationship ∞  Apparent Energy = Lim∑ Apparent Power (nT ) × T (22) T →0  =  n 0 Where n is the discrete time sample number and T is the sample period. Shown in Figure 44 is the maximum code (Hexadecimal) output range of the Apparent Power signal. This addition is a signed addition even if the Apparent Energy remains theoretically always positive. This can be used to calibrate the Apparent Power (or Energy) calculation in the ADE7753 -see Apparent Power calculation. APPARENT ENERGY CALCULATION Vrms Voltage RMS Signal .   VAGAIN  Output VAGAIN =  Apparent Power × 1 +   212   The ADE7753 achieves the integration of the Apparent Power signal by continuously accumulating the Apparent Power signal in an internal 48-bit register. Note that the output range changes depending on the contents of the Apparent Power Gain registers. The minimum output range is given when the Apparent Power Gain register content is equal to 800h and the maximum range is given by –24– REV. Irms Current RMS Signal .P MULTIPLIER Each RMS measurement includes an offset compensation register to calibrate and eliminate the DC component in the RMS value -see Channel 1 RMS calculation and Channel 2 RMS calculation. Apparent Energy = ∫ Apparent Power (t ) dt (21) Figure 43 .

1 14. the integration time under these conditions with VADIV=0 is calculated as follows: Time = 7FFF. 7FFh. the integration time varies as shown on Equation 23.P T APPARENT POWER ARE ACCUMULATED (INTEGRATED) IN THE APPARENT ENERGY REGISTER As mentioned in the last section.FFFFh before it overflows.FFFFh VAGAIN = 7FFh VAGAIN = 000h VAGAIN = 800h 80.2µs = 888s = 14. FFFF.1 or 7FFF. The LSB size of these two registers is equivalent. + Apparent Power + 46 0 40.e. The line Apparent energy accumulation mode is always active. As the average word value is added to the internal register which can store 248 . the discrete time sample period (T) for the accumulation register is 1. Because the Apparent Power is integrated on the same integral number of line cycles as the Line Active Energy register. The number of half line cycles is specified in the LINCYC register. illustrate the minimum time it takes the energy register to roll-over when the VA Gain registers content is equal to 7FFh. The active and apparent Energy are calculated more accurately because of this precise timing control and provide all the information needed for Reactive Power and Power Factor calculation. the average word value from Apparent Power stage is AD055h .Energy register roll-over time for full-scale power (Minimum & Maximum Power Gain) CALIBRATION CONTROL LVAENERGY[23:0] Note that the Apparent Energy register contents roll-over to full-scale negative (80. The maximum value which can be stored in the Apparent Energy register before it over-flows is 2 24 or FF.FFFFh.0000h) and continue increasing in value when the power or energy flow is positive .0000h Σ 00.0000h LINE APPARENT ENERGY ACCUMULATION The ADE7753 is designed with a special Apparent Energy accumulation mode which simplifies the calibration process. LINCYC is an unsigned 16-bit register.. –25– REV. At the end of an energy calibration cycle the CYCEND flag in the Interrupt Status register is set. the fastest integration time will occur when the VA Gain register is set to maximum full scale.0000h 4. 000h and 800h. With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set to 000h. these two values can be compared easily.see Figure 46.PRELIMINARY TECHNICAL DATA ADE7753 VAENERGY[23:0] 23 0 Integration times under steady load 0 47 VADIV APPARENT POWER T + 46 Σ 0 + Apparent Power Signal . i.0000h 20. Thus the IRQ line can also be used to signal the end of a calibration. The ADE7753 can accumulate Apparent Power for up to 65535 combined half cycles. By using the on-chip zero-crossing detection.FFFF.1µs (4/CLKIN). VAENERGY[23:0] FF. VADIV is an 8-bit unsigned register. the ADE7754 can be configured to issue an interrupt (IRQ) when the Apparent Energy register is half full (positive or negative) or when an over/under flow occurs. Time = TimeWDIV=0 x VADIV (23) Figure 45.8min AD055h AD055h 00000h time (nT) When VADIV is set to a value different from 0.ADE7753 Apparent Energy calculation The upper 52-bit of the internal register are divided by VADIV. Figure 45 shows this Apparent Energy accumulation for full scale signals (sinusoidal) on the analog inputs. The upper 24-bit are then written in the 24-bit Apparent Energy register (VAENERGY[23:0]). The Line Apparent Energy accumulation uses the same signal path as the Apparent Energy accumulation.4 11. the ADE7753 accumulates the Apparent Power signal in the LVAENERGY register for an integral number of half cycles.see Apparent Power output range. By using the Interrupt Enable register. The three curves displayed. RVAENERGY register (24 bits long) is provided to read the Apparent Energy.FFFFh × 1.8 Time (minutes) LPF1 FROM CHANNEL 2 ADC ZERO CROSSING DETECTION VADIV[7:0] LVAENERGY REGISTER IS UPDATED EVERY LINECYC ZERO-CROSSINGS WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION 23 0 Figure 46. The VA Gain register is used to carry out an apparent power calibration in the ADE7753. as shown in Figure 47. PrF 10/02 LINECYC[15:0] Figure 47 .ADE7753 Apparent Energy Calibration . the IRQ output will also go active low. If the value in the VADIV register is equal to 0 then the internal active Energy register is divided by 1.9 7. If the CYCEND mask bit in the Interrupt Mask register is enabled. This register is reset to zero after a read operation. As shown.

the MCU can compute Under these load conditions the transducers on Channel 1 the energy consumption at any time by reading the AENERGY and Channel 2 should be selected such that the signal on the contents and multiplying by the coefficient to calculate kWh.5 decimal. The desired frequency out is 3. Alternatively. the LPF2 output is then 52. If this is not possible.g. at 60Hz line frequency. CF frequency can be calculated based on the average LPF2 output. the CF frequency must be divided by 2797/3. As described previously. Note that changing WGAIN[11:0] register will also affect the output frequency from CF. CF Frequency= Average LPF2 Output × CLKIN 2 27 (25) Calibrating the Frequency at CF When the frequency before frequency division is known.3Hz 2 27 When the CYCMODE (bit 7) bit in the Mode register is set to a logic one. the frequency under this load is calculated as: Frequency (CF) = Frequency( CF) = CF Frequency = Content of LAENERGY[23 : 0] Register Elasped Time 52428. the total elasped time can be calculated by the following: Elasped Time = 1 × number of half cycles 2 × fl For example. This means that under a steady load of 1kW.4 (decimal).3Hz 255 Alternatively. Then using Digital to Frequency Conversion. At 1/16 of full-scale. the closest rational number is found to be 1/358 (or 1h/166h). i.8888 Hz 60 min × 60 sec 3600 Assuming the meter is set up with a test current (basic kWHr/LSB = current) of 20A and a line voltage of 220V for calibration.9111Hz. As shown in Figure 37. This is achieved by loading the pair of CF Divider registers with the closest rational number. e. If the line frequency is fixed and the number of half cycles of integration is specified. the output frequency is given as 2797Hz / 358 = 3. the Calibration Power (in kW) LINECYC[15 : 0] load is calculated as 220V × 20A = 4. Note that the CF frequency is multiplied by the contents of (CFNUM + 1) / (CFDEN + 1). With the CF Divide registers contents equal to 1h/166h. the average value from LPF2 under this condition is approximately 1/16 of the full-scale level. A convenient way to to determine the output frequency on CF is to use the line cycle energy accumulation mode.428. The WGAIN register has a gain adjustment of 0. DFC generates a pulse each time a LSB in the LAENERGY register is accumulated.74×10-7 kWHr/LSB using the above equation. The AENERGY register gives the user both sign and magnitude information regarding energy consumption. energy is accumulated over FFh number of half line 8. Therefore.81.4 × 0.4kW. Once the coefficient is determined.579545MHz = 1398. energy is accumulated over an integer number of half line cycles.4 × 2 × 60 = 1398. Equation 26 below shows how LAENERGY can be used to calculate the calibration coefficient. the frequency can be measured by using the PERIOD register of the ADE7753..861 (decimal). The kWHr/LSB can therefore be calculated to be 60Hz.81× 3. The critical part of this approach is that the line frequency needs to be exactly known.1%. 3200 imp/kWh. the average LPF2 output at full-scale ac input is CCCCD (hex) or 838. Rewriting the above in terms of contents of various ADE7753 registers and line frequencies (fl): CF Frequency = LAENERGY[2 3 : 0] × 2 × fl LINECYC[15 : 0] This is the frequency with the contents of the CFNUM and CFDEN registers equal to 000h. the pair of CF Frequency Divider registers (CFNUM and CFDEN) can be adjusted to produce the required frequency on CF. after 255 half cycles (at signal on the current channel about 1/8 of full scale (assuming 60Hz)..8888Hz = 3.e. CF frequency (before the CF frequency divider) can be conveniently determined by the following expression: 2971.0244% / LSB. This setting has an error of -0. Therefore the (26) × expected output frequency on CF under this steady load 3600 seconds/Hr LAENERGY[23 : 0] × 2 × fl condition would be 4. In this example a meter constant of 3200 imp/kWh is chosen as an appropriate constant. after adjusting the CF Frequency divider and the Watt Gain (WGAIN) register.9111Hz or 357. 3200 imp / kWh 3200 = = 0. Assuming at line frequency of decimal.PRELIMINARY TECHNICAL DATA ADE7753 CALIBRATING THE ENERGY METER When calibrating the ADE7753. CF frequency is therefore calculated to be: REV. A full description of this register can be found in the Energy Calculation section. the output frequency on CF would be. In this case. Calibrating CF is made easy by using the Calibration mode on the ADE7753. Determine the kWHr/LSB Calibration Coefficient (24) where fl is the line frequency. the resulting LAENERGY is approximately 2971 a maximum current of 80A). the resulting content of the LAENERGY register will be approximately 2971. voltage channel should see approximately half scale and the In the above example. the first step is to calibrate the frequency on CF to some required meter constant. On completion of the CF frequency output calibration. Therefore. at 4.905Hz.4kW.125 seconds.9111Hz. 0h and 165h should be written to the CFNUM and CFDEN registers respectively. cycles. the second stage of the calibration is to determine the kWh/LSB coefficient for the AENERGY register. PrF 10/02 –26– Frequency (CF ) = The Active Energy register (AENERGY) can be used to calculate energy. . the elasped time for 255 half cycles will be 2.

However. DOUT CONTENT OF REGISTER (n-bytes) The change of CLKIN frequency does not affect the timing characteristics of the serial interface because the data transfer is synchronized with serial clock signal (SCLK). PrF 10/02 –27– . the characteristics of the ADE7753 is shown with CLKIN frequency equals 3. Using the Checksum register.) will shift in proportion to the change in CLKIN frequency according to the following equation: New Frequency = Original Frequency × CLKIN Frequency (27) 3. the ADE7753 is designed to have the same accuracy at any CLKIN frequency within the specified range. Note that a read to the Checksum register will also generate a checksum of the Checksum register itself. For example. various timing and filter characteristics will need to be redefined with the new CLKIN frequency. In suspend mode.579545 MHz The ADE7753 has a Checksum register (CHECKSUM[5:0]) to ensure the data bits received in the last serial read operation are not corrupted.579545MHz. the cut-off frequencies of all digital filters (LPF1. etc.PRELIMINARY TECHNICAL DATA ADE7753 CLKIN FREQUENCY CHECKSUM REGISTER In this datasheet. During a serial read operation. In the end of the serial read operation. LPF2.288/CLKIN Nyquist frequency for CH 1&2 ADCs PHCAL resolution (seconds per LSB) Active Energy register update rate (Hz) WAVSEL 1. the bit will be added to the Checksum register. If the CLKIN frequency is not 3. when each data bit becomes available on the rising edge of SCLK. The ADE7753 can be reactivated by restoring the CLKIN input and setting the ASUSPEND bit to logic low.0 = 0 0 1 1 0 1 0 1 Waveform sampling rate (Number of samples per second) Maximum ZXTOUT period SUSPENDING THE ADE7753 FUNCTIONALITY The analog and the digital circuit can be suspended separately. REV.579545 MHz. The analog portion of the ADE7753 can be suspended by setting the ASUSPEND bit (bit 4) of the Mode register See Mode Register. The 6-bit Checksum register is reset before the first bit (MSB of the register to be read) is put on the DOUT pin. But one needs to observe the read/write timing of the serial data transfer-see ADE7753 Timing Characteristics. the content of the Checksum register will equal to the sum of all ones in the register previously read. the user can determine if an error has occured during the last read operation. HPF1. all to logic high waveform samples from the ADCs will be set to zeros. The digital circuitry can be halted by stopping the CLKIN input and maintaining a logic high or low on CLKIN pin. + Σ + CHECKSUM REGISTER ADDR: 3Eh Figure 48– Checksum register for Serial Interface Read Table III Frequency dependencies of the ADE7753 parameters Parameter CLKIN dependency CLKIN/8 4/CLKIN CLKIN/4 CLKIN/128 CLKIN/256 CLKIN/512 CLKIN/1024 524. Table III lists various timing changes that are affected by CLKIN frequency.

DIN COMMUNICATIONS REGISTER IN OUT IN OUT IN OUT DOUT REGISTER # 1 REGISTER # 2 REGISTER # 3 REGISTER ADDRESS DECODE The Serial Interface of the ADE7753 is made up of four signals SCLK. Hence the first byte shifted into the serial port at DIN is transferred to the MSB (Most significant Byte) of the destination register. Figure 52 illustrates this example. See ADE7753 Communications Register for a more detailed description.e. PrF 10/02 .PRELIMINARY TECHNICAL DATA ADE7753 ADE7753 SERIAL INTERFACE All ADE7753 functionality is accessible via several on-chip registers – see Figure 49. CS SCLK DIN DOUT COMMUNICATIONS REGISTER WRITE 0 0 0 ADDRESS MULTIBYTE READ DATA Figure 50– Reading data from the ADE7753 via the serial interface CS SCLK COMMUNICATIONS REGISTER WRITE DIN 1 0 0 ADDRESS MULTIBYTE WRITE DATA Figure 51– Writing data to the ADE7753 via the serial interface A data transfer is complete when the LSB of the ADE7753 register being addressed (for a write or a read) is transferred to or from the ADE7753. This functionality is expressed in the timing specification t6 . this second byte transfer should not finish until at least 4µs after the end of the previous byte transfer. ADE7753 Serial Write Operation The serial write sequence takes place as follows. The MSB of this byte transfer is a 1. The LSBs of this byte contain the address of the register to be written to. a two-byte data transfer must take place. Although another byte transfer to the serial port can start while the previous byte is being transferred to an on-chip register. On completion of a data transfer (read or write) the ADE7753 once again enters communications mode. –28– REV. i. The CS logic input may be tied low if the ADE7753 is the only device on the serial bus. With the ADE7753 in communications mode (i. Figure 50 and 51 show the data transfer sequences for a read and write operation respectively. Therefore all data transfer operations with the ADE7753. The CS input should be driven low for the entire data transfer operation. As explained earlier the data write is initiated by a write to the communications register followed by the data.. REGISTER # n-1 IN OUT IN OUT REGISTER # n Figure 49– Addressing ADE7753 Registers via the Communications Register The Communications register is an eight bit wide register.. Bringing CS high during a data transfer operation will abort the transfer and place the serial bus in a high impedance state. therefore in this case. The CS logic input is the chip select input. The ADE7753 starts shifting in the register data on the next falling edge of SCLK. Destination registers may be up to 3 bytes wide – see ADE7753 Register Descriptions. the CS input logic low). The serial clock for a data transfer is applied at the SCLK logic input. DOUT and CS. using RESET. During a data write operation to the ADE7753. The 5 LSBs contain the address of the register to be accessed. All data transfer operations are synchronized to the serial clock. must begin with a write to the Communications register. indicating that the data transfer operation is a write. The MSB determines whether the next data transfer operation is a read or a write. a write to the communications register first takes place. Data is shifted out of the ADE7753 at the DOUT logic output on a rising edge of SCLK. The contents of these registers can be updated or read using the on-chip serial interface. The data is always assumed to be right justified. This logic input has a schmitt-trigger input structure. whether a read or a write. then that byte will not be written to the destination register. DIN. i.e. for example. After a byte is transferred into the serial port. data is transferred to all onchip registers one byte at a time.see Figure 51. A falling edge on CS also resets the serial interface and places the ADE7753 in communications mode. which allows slow rising (and falling) clock edges to be used. the four MSBs of the first byte would be ignored and the 4 LSBs of the first byte written to the ADE7753 would be the 4MSBs of the 12-bit word. If a write operation is aborted during a byte transfer (CS brought high). However with CS tied low. Data is shifted into the ADE7753 at the DIN logic input on the falling edge of SCLK. This input is used when multiple devices share the serial bus. there is a finite time before it is transferred to one of the ADE7753 on-chip registers. all initiated data transfer operations must be fully completed. the ADE7753 is placed in communications mode.e. The data written to the communications register determines whether the next data transfer operation will be read or a write and also which register is accessed. After power-on or toggling the RESET pin low or a falling edge on CS. If the addressed register is 12 bits wide. In communications mode the ADE7753 expects a write to its Communications register. All remaining bits of register data are shifted in on the falling edge of subsequent SCLK pulses – see Figure 51. the LSB of each register must be transferred as there is no other way of bringing the ADE7753 back into communications mode without resetting the entire device.

indicating that the next data transfer operation is a read. The is given as timing specification t9. The serial interface also enters communications mode again as soon as the read has been completed. If the read command is sent within 4µs of the write operation. The DOUT output enters a high impedance state on the rising edge of CS. the read command (i. PrF 10/02 –29– . At this point the DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse. The LSBs of this byte contain the address of the register which is to be read.e. This allows the ADE7753 to modify its on-chip registers without the risk of corrupting data during a multi byte transfer. The read operation may be aborted by bringing the CS logic input high before the data transfer is complete.e. the entire contents of that register are transferred to the serial port. When an ADE7753 register is addressed for a read operation.PRELIMINARY TECHNICAL DATA ADE7753 t8 CS t1 t2 t3 t7 t4 t5 DB7 DB0 DB7 DB0 t7 t6 SCLK DIN 1 0 0 A4 A3 A2 A1 A0 Command Byte Most Significant Byte Least Significant Byte Figure 52 – Serial Interface Write Timing Diagram SCLK DIN X X X X DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Most Significant Byte Least Significant Byte Figure 53—12 bit Serial Write Operation ADE7753 Serial Read Operation During a data read operation from the ADE7753 data is shifted out at the DOUT logic output on the rising edge of SCLK. The MSB of this byte transfer is a 0.. As was the case with the data write operation. the last byte of the write operation may be lost. The ADE7753 starts shifting out of the register data on the next rising edge of SCLK – see Figure 54. At this point the DOUT logic output leaves its high impedance state and starts driving the data bus. All remaining bits of register data are shifted out on subsequent SCLK rising edges. a data read must be preceded with a write to the Communications register. CS logic low) an eight bit write to the Communications register first takes place. CS t1 t9 t10 t13 SCLK DIN DOUT Command Byte 0 0 0 A4 A3 A2 A1 A0 t11 DB7 t11 DB0 DB7 t12 DB0 Most Significant Byte Least Significant Byte Figure 54– Serial Interface Read Timing Diagram REV. Note when a read operation follows a write operation. write to communications register) should not happen for at least 4µs after the end of the write operation. With the ADE7753 in communications mode (i.

see Analog Inputs. Interrupt Enable register. However. Channel 2 Offset Adjust. This is an 8-bit read-only register. The Status register will continue to register an interrupt event even if disabled. Same as the Active Energy register except that the register is reset to zero following a read operation Line Accumulation Active Energy register. Writing to bits 0 to 5 allows offsets on Channel 1 to be removed – see Analog Inputs and CH1OS Register. Bit 6 is not used. Signal sample rates.see Channel 1 & 2 Sampling.see Analog Inputs. The contents may be read at any time—see Mode Register. 02h AENERGY R 24 bits 0h 03h 04h RAENERGY LAENERGY R R 24 bits 24 bits 0h 0h 05h 06h 07h VAENERGY R 24 bits 24 bits 24 bits 0h 0h 0h RVAENERGY R LVAENERGY R 08h LVARENERGY R 24 bits 0h 09h MODE R/W 16 bits 000Ch 0Ah IRQEN R/W 16 bits 40h 0Bh STATUS R 16 bits 0h 0Ch RSTSTATUS R 16 bits 0h 0Dh CH1OS R/W 8 bits 00h 0Eh CH2OS R/W 8 bits 0h 0Fh GAIN R/W 8 bits 0h –30– REV. Apparent power is accumulated over time in this read-only register. The data source and the length of the waveform registers are selected by data bits 14 and 13 in the Mode Register . Active Power is accumulated (Integrated) over time in this 24-bit. Channel 1 Offset Adjust. Same as the VAENERGY register except that the register is reset to zero following a read operation. The instantaneous active power is accumulated in this read-only register over the LINCYC number of half line cycles. Apparent Energy register. Bit 6 and 7 not used. The Status Register contains information regarding the source of ADE7753 interrupts . PGA Gain Adjust. This is a 16-bit register through which most of the ADE7753 functionality is accessed. This 8-bit register is used to adjust the gain selection for the PGA in Channel 1 and 2 . The Mode register. a zero disables the integrator. The Interrupt Status register. PrF 10/02 . Apparent Energy register. Channel 2 or the Active Power signal. Writing a logic one to the MSB of this register enables the digital integrator on Channel 1. The Active Energy register. the IRQ output will not be activated—see ADE7753 Interrupts. The default value of this bit is zero. filter enabling and calibration modes are selected by writing to this register. Same as the Interrupt Status register except that the register contents are reset to zero (all flags cleared) after a read operation. This register contains the sampled waveform data from either Channel 1. read-only register. The energy register can hold a minimum of 6 seconds of Active Energy information with full scale analog inputs before it overflows .PRELIMINARY TECHNICAL DATA ADE7753 Address Name 01h R/W # of Bits 24 bits WAVEFORM R ADE7753 REGISTER LIST Default Description 0h The Waveform register is a read-only register. The instantaneous real power is accumulated in this read-only register over the LINECYC number of half line cycles Reactive Energy register. Writing to bits 0 to 5 of this register allows any offsets on Channel 2 to be removed .see ADE7753 Interrupts.see Energy Calculation. ADE7753 interrupts may be deactivated at any time by setting the corresponding bit in this 8bit Enable register to logic zero. The instantaneous reactive power is accumulated in this read-only register over the LINECYC number of half line cycles.

Channel 1 Peak Level threshold (current channel). The maximum time-out period is 0. CF Frequency Divider Denominator register. Active Energy divider register. If the channel 1 input exceeds this level. R/W 6 bits 11h APOS R/W 16 bits 0h 12h WGAIN R/W 12 bits 0h 13h WDIV R/W 8 bits 0h 14h CFNUM R/W 12 bits 3Fh 15h CFDEN R/W 12 bits 3Fh 16h 17h 18h 19h 1Ah IRMS VRMS IRMSOS VRMSOS VAGAIN R R 24 bits 24 bits 0h 0h 0h 0h 0h R/W 12 bits R/W 12 bits R/W 12 bits 1Bh VADIV R/W 8 bits 0h 1Ch LINECYC R/W 15 bits FFFh 1Dh ZXTOUT R/W 12 bits FFFh 1Eh SAGCYC R/W 8 bits FFh 1Fh SAGLVL R/W 8 bits 0h 20h IPKLVL R/W 8 bits FFh REV. The signal must remain low for the number of cycles specified in the SAGCYC register before the SAG pin is activated—see Line Voltage Sag Detection. Channel 1 RMS value (current channel). This 16-bit register allows small offsets in the Active Power Calculation to be removed – see Active Power Calculation. Power Gain Adjust. The resolution of the gain adjust is 0. At line frequency of 60Hz. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register – see Energy to Frequency Conversion.see Zero Crossing Detection. The internal apparent energy register is divided by the value of this register before being stored in the VAENERGY register. This 8-bit register specifies the number of consecutive line cycles the signal on Channel 2 must be below SAGLVL before the SAG output is activated . —see Phase Compensation.see Line Cycle Energy Accumulation Mode.7 degrees. The Active Power calculation can be calibrated by writing to this register. PrF 10/02 –31– .06 to +0. The resolution of the gain adjust is 0. This 15-bit register is used during line cycle energy accumulation mode to set the number of half line cycles for energy accumulation .0244% / LSB—see Channel 1 ADC Gain Adjust. This register sets the level of the current peak detection. Zero-cross Time Out. Line Cycle Energy Accumulation Mode Line-Cycle register.15 second . Sag line Cycle register. this is a range from -2. Active Power Offset Correction. The calibration range is ±50% of the nominal full scale active power. The valid content of this 2's compliment register is between 1Dh to 21h. If no zero crossings are detected on Channel 2 within a time period specified by this 12-bit register.02444% / LSB. This is a 12-bit register. The calibration range is 50% of the nominal full scale real power. The output frequency on the CF pin is adjusted by writing to this 12-bit read/write register – see Energy to Frequency Conversion.PRELIMINARY TECHNICAL DATA ADE7753 Address Name 10h PHCAL R/W # of Bits Default 0Dh Description Phase Calibration register. The internal active energy register is divided by the value of this register before being stored in the AENERGY register. Apparent power calculation can be calibrated by writing this register. An 8-bit write to this register determines at what peak signal level on Channel 2 the SAG pin will become active. the PKI flag in the status register is set.see Voltage Sag Detection Sag Voltage Level. Channel 2 RMS value (voltage channel). CF Frequency Divider Numerator register. Channel 1 RMS offset correction register Channel 2 RMS offset correction register Apparent Gain register. The phase relationship between Channel 1 and 2 can be adjusted by writing to this 6-bit register. Apparent Energy divider register. the interrupt request line (IRQ) will be activated.

Die Revision Register. Table III lists the address of each ADE7753 on-chip register. Same as Channel 2 peak register except that the register contents are reset to 0 after a read. When this bit is a logic zero the data transfer operation immediately following the write to the Communications register will be interpreted as a read operation. Table IV below outlines the bit designations for the Communications register. The maximum input value of the Voltage channel since the last read of the register is stored in this register. The maximum input value of the Current channel since the last read of the register is stored in this register. Reserved TMODE CHKSUM R/W 8 bits R 6 bits 0h Test mode register Checksum Register. Channel 1 peak register. Each register is accessed by first writing to the communications register and then transferring the register data. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. If the channel 2 input exceeds this level. write-only register which controls the serial data transfer between the ADE7753 and the host processor. R/W 8 bits 22h IPEAK R 24 bits 0h 23h 24h RSTIPEAK VPEAK R R 24 bits 24 bits 0h 0h 25h 26h RSTVPEAK TEMP R R 24 bits 8 bits 0h 0h 27h 28h3Ch 3Dh 3Eh PERIOD R 15 bits 0h 3Fh DIEREV R 8 bits - ADE7753 REGISTER DESCRIPTIONS All ADE7753 functionality is accessed via the on-chip registers. Channel 2 peak register. Same as Channel 1 peak register except that the register contents are reset to 0 after read. Temperature register. Table V. When this bit is a logic one the data transfer operation immediately following the write to the Communications register will be interpreted as a write to the ADE7753. Communications Register The Communications register is an 8-bit. This is an 8-bit register which contains the result of the latest temperature conversion – see Temperature Measurement. Communications Register DB7 W/R DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 A5 A4 A3 A2 A1 A0 Bit Location 0 to 5 6 7 Bit Mnemonic A0 to A5 RESERVED W/ R Description The six LSBs of the Communications register specify the register for the data transfer operation. A full description of the serial interface protocol is given in the Serial Interface section of this data sheet. the PKV flag in the status register is set. Period of the channel 2 (volatge channel) input estimated by Zero-crossing processing. –32– REV. All data transfer operations must begin with a write to the communications register. PrF 10/02 . This 8-bit read only register contains the revision number of the silicon. This bit is unused and should be set to zero.PRELIMINARY TECHNICAL DATA ADE7753 Address Name 21h VPKLVL R/W # of Bits Default FFh Description Channel 2 Peak Level threshold (voltage channel). This register sets the level of the voltage peak detection. This 6-bit read only register is equal to the sum of all the ones in the previous read – see ADE7753 Serial Read Operation.

9kSPS (CLKIN/128) 14kSPS (CLKIN/256) 7kSPS (CLKIN/512) 3. The default value of this bit is 0.6 kSPS (CLKIN/1024) SWAP (Swap CH1 & CH2 ADCs) DISCH2 (Short the analog inputs on Channel 2) DISCH1 (Short the analog inputs on Channel 1) 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 ADDR: 09H DISHPF (Disable HPF in Channel 1) DISLPF2 (Disable LPF2 after multiplier) DISCF (Disable Frequency output CF) DISSAG (Disable SAG output) ASUSPEND (Suspend CH1&CH2 ADC’s) STEMP (Start temperature sensing) SWRST (Software chip reset) CYCMODE (Line Cycle Energy Accumulation Mode) *Register contents show power on defaults REV. By setting this bit to logic 1 the analog inputs V2P and V2N are connected to ADC 1 and the analog inputs V1P and V1N are connected to ADC 2. MODE REGISTER* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 POAM (Positive Only Accumulation) WAVSEL (Wave form selection for sample mode) 00 = LPF2 01= Reserved 10 = CH1 11 = CH2 DTRT (Waveform samples output data rate) 00 = 27. The Temperature conversion starts when this bit is set to one. ADC 1 (Channel 1) inputs are internally shorted together. ADC 2 (Channel 2) inputs are internally shorted together. Setting this bit to a logic one places the chip in line cycle energy accumulation mode. PrF 10/02 –33– . both ADE7753's A/D converters can be turned off. A data transfer should not take place to the ADE7753 for at least 18µs after a software reset. 11 TEMPSEL SWRST 0 0 CYCMODE 0 DISCH1 DISCH2 SWAP DTRT1.0 0 0 0 00 14.4 kSPS (CLKIN/256) 10 = 7.0 00 These bits are used to select the source of the sampled data for the Waveform Register WAVSEL1. The LPF (Low Pass Filter) after the multiplier (LPF2) is disabled when this bit is set. Software chip reset. All digital functionality can be stopped by suspending the clock signal at CLKIN pin. this bit should be left at logic zero.0 0 0 1 1 0 1 0 1 15 POAM 0 Writing a logic one to this bit will allow only positive power to be accumulated in the ADE7753. These bits are used to select the Waveform Register update rate DTRT 1 0 0 1 1 DTRT0 0 1 0 1 Length Source 24 bits Active Power signal (output of LPF2) Reserved 24 bits Channel 1 24 bits Channel 2 Update Rate 27. 13 WAVSEL1.5kSPS (CLKIN/1024) ASUSPEND 0 5 6 7 8 9 10 12. The Frequency output CF is disabled when this bit is set The line voltage Sag detection is disabled when this bit is set By setting this bit to logic one. In normal operation. This bit is automatically reset to zero when the Temperature conversion is finished.2 kSPS (CLKIN/512) 11 = 3. Table VI : Mode Register Bit Location 0 1 2 3 4 Bit Mnemonic DISHPF DISLPF2 DISCF DISSAG Default Value Description 0 0 1 1 The HPF (High Pass Filter) in Channel 1 is disabled when this bit is set.PRELIMINARY TECHNICAL DATA ADE7753 Mode Register (09H) The ADE7753 functionality is configured by writing to the MODE register.9kSPS (CLKIN/128) 01 = 14. Table VI below summarizes the functionality of each bit in the MODE register .

PRELIMINARY TECHNICAL DATA ADE7753 Interrupt Status Register (0BH) / Reset Interrupt Status Register (0CH) /Interrupt Enable Register (0Ah) The Status Register is used by the MCU to determine the source of an interrupt request (IRQ). Indicates that the power has gone from positive to negative. Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified number of line cycles—see Zero Crossing Time Out Indicates that the power has gone from negative to positive. Indicates that waveform sample from Channel2 has exceeded the VPKLVL value. Indicates that waveform sample from Channel1 has exceeded the IPKLVL value. When an interrupt event occurs in the ADE7753. Reserved 7h 8h 9h Ah Bh Ch Dh Eh Fh AEOF PKV PKI VAEHF VAEOF ZXTO PPOS PNEG RESERVED –34– REV. PrF 10/02 . Indicates the end of energy accumulation over an integer number of half line cycles as defined by the content of the LINECYC Register—see Line Cycle Energy Accumulation Mode Indicates that new data is present in the Waveform Register.e. but it cannot be enabled to cause an interrupt. Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no function in the Interrupt Enable Register. the VAENERGY register is half full) Indicates that the Apparent Enrgy register has overflowed. Indicates that the Active Energy register has overflowed. i. Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Apparent Energy register (i. When the MCU services the interrupt it must first carry out a read from the Interrupt Status Register to determine the source of the interrupt. the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is logic one in the Interrupt Enable register. the AENERGY register is half full) Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were detected. Table VII: Interrupt Status Register.e. Reset Interrupt Status Register & Interrupt Enable Register Bit Location 0h 1h 2h 3h 4h 5h 6h Interrupt Flag AEHF SAG CYCEND WSMP ZX TEMP RESET Description Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active Energy register (i. This status bit reflects the status of the ZX logic ouput—see Zero Crossing Detection Indicates that a temperature conversion result is available in the Temperature Register.e. this status bit is set at the end of a reset. the IRQ logic output goes active low.

73) 0.50) 0.94) 0.9) 0.127) 8° 0° 0.050) 0.008 (0.212 (5.301 (7.002 (0.78) 0.38) 1 10 0.022 (0.311 (7.005 (0.205 (5.203) 0.009 (0.068 (1.07 (1. PrF 10/02 –35– .066 (1.65) BSC SEATING 0.229) PLANE 0.98) PIN 1 0.64) 0.559) REV.0256 (0.PRELIMINARY TECHNICAL DATA ADE7753 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 20-Shrink Small Outline Package (RS-20) 0.21) 0.078 (1.67) 0.90) 20 11 0.271 (6.295 (7.037 (0.

For example. Samples of this version of the silicon can be identified from the content of the DIEREV regsiter (Address 3Fh). The content of DIEREV register is 2 for Rev 1. the branding on top of the package for Rev 1.0) The following is a list of known issues with the first revision of the ADE7753 silicon (rev 1. 2. In addition.2 silicon.2 should be as shown below: 20 11 AD7753 XRS 0240 K58207 1 10 ERRATA 1. SAGCYC The contents of SAGCYC register is equivalent to (SAGCYC-1). PrF 10/02 . This is not a silicon bug.PRELIMINARY TECHNICAL DATA ADE7753 ADE7753 ERRATA (REV 1. This is not a silicon bug. if the desired number of linecycles for SAG detection is 20d line cycles.0). The behavior of the output frequency is not guaranteed for CF. These issues will be resolved in the next version. one should write 21d to the SAGCYC Register. –36– REV. CFNUM and CFDEN CFNUM should always be less than CFDEN.

Page 26 1. The instead change well as internal active energy accumulation register is 47 bits of 53 bits. Page 22 1. The equation also shows this change.F is to correct some of the mistakes contained in the Pr. The calculation of CFNUM and CFDEN changed according to the effect of the abovementioned changes. The PHCAL register description changed to reflect the new effective length and resolution of the register and default value of 0D.1us. Figure 39 shows the actual internal register length to be 47 bits. changed from 6 half line cycles. and the CF frequency output in the example calculation is 1398. The section explaining Figure 13 has also changed accordingly. The maximum output frequency is changed to 23Hz. Note that all page numbers are referring to that of Pr. 2. Figure 27 updated with new PHCAL range and delay block rate.D to Pr. Text added to explain CFNUM must be less than CFDEN. PrF 10/02 –37– . REV.E version. Page 12 The SAGCYC register value represents full-line cycles and not half-line cycles.D and Pr.F. The line voltage SAG detection section text was changed to reflect this design update. Figure 41. Content of LAENERGY register is 2971. The definition of the SAGCYC a register has changed to full line cycles. 2.PRELIMINARY TECHNICAL DATA ADE7753 REVISION HISTORY The main reason for revising the datasheet from version Pr. 3. 2. 2. Page 4 Read timing t9 is determined to be 3. Figure 13 shows 3 line cycles. IPEAK is 1 times the absolute value of the CH1 Waveform. This section calculations have been changed to reflect this new resolution. The phase calibration register resolution has changed to 0. Page 20 Figure 36 Timing was updated. 6h in the SAGCYC register. This change is also on page 23.D to Pr. 2. Equation 25 changed to have 2^27 bits for the denominator.3 Hz.024. Page 18 1. 3h in the SAGCYC register. 3. changes were made to the silicon to fix bugs noted in the Errata list and to modify the product definition. This is also implemented in the equations of page 25 as Figures 45 and 47 on page 25. Page 31 1. LINECYC corrected to say 15 bits and remains half line cycles. Line Cycle Energy accumulation mode section changed to 15 bits for LINECYC Register.F.048 from 0. Page 13 Peak Level record section was changed to show that the quantity stored in VPEAK register is 2 times the absolute value of the WAVEFORM register contents for CH2. In addition. The list below highlights the important changes from Pr.4. Page 21 1.

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