CE/CZ1055

Digital Logic Tutorial 6: Combinational Logic

1. (a) Draw the circuit represented by the following Verilog module. Label the gates and wires. module whatisit (input a, b, c, d, e, output x, y); not n1 (nb, b); not n2 (ne, e); and a1 (w1, a, b); and a2 (w2, nb, c); nor no1 (w3, d, e); nand na1 (w4, w2, w3); or o1 (x, w1, w4); and a3 (y, ne, w1); endmodule

a b nb c

a1

w1
o1

a2

w2 w4
na1

d e

no1

w3

Note: since the wires are 1-bit, they dont need to be explicitly declared in the Verilog. (b) Write down a logic expression for each of the outputs. x = ab + ((bc) (d+e)) y = abe

ne

a3

(c) Rewrite the Verilog module using a single assign statement for each output. module whatisit2 (input a,b,c,d,e, output x, y); assign x = (a & b) | ~((~b & c) & ~(d | e)); assign y = a & b & ~e; endmodule The &, |, and ~ operators are bitwise, whereas &&, ||, ! are logical. They are interchangeable for 1-bit signals. 2. You are required to design a ferry boarding system to direct cars to one of four boarding ramps. The input to the circuit is a 2-bit binary number representing which ramp to use, and a 1-bit signal which is high when all ramps are full. These signals are generated by the (human) gatekeeper. The circuit has outputs that control four green lights, one above each of the ramps, with only one active at any time, and one red light which indicates that all ramps are full and vehicles should not proceed to join any ramp. (a) Show a block diagram for the circuit using a single decoder and any additional gates needed.
Q3 d3 d2 d1 d0 Q2

switch

i1 i0

Q1 Q0

en

full?

FULL

We want to enable the system when the queue is not full, so we need to negate the full signal.

(b) Write a Verilog module that instantiates a decoder module with the following declaration: module dec2to4 (input [1:0] a, input enable, output [3:0] one_hot); module queuecont (input [1:0] sel, input full, output [3:0] queue, output stop); dec2to4 (.a(sel), .enable(~full), .one_hot(queue)); assign stop = full; endmodule

We can negate the full signal in the port connection as shown, or use a not gate. 3. We would like to design a general circuit that implements either a sum of products (of the form ab+cd+ef) or product of sums expression (of the form (a+b)(c+d)(e+f)). (a) Use and and or gates as well as four 2x1 multiplexers to design a circuit that outputs the sum of products of the six inputs when a sel input is 0 and the product of sum when the sel input is 1.

a b a b c d c d e f e f

0 1 1 0 1 0 0 1 x

sel Note the input orders in the first stage and second stage are opposites. (Inputs have been duplicated for ease of drawing. Its of course possible to connect the identically named signals together.)

(b) Implement the circuit using Verilog conditional assign statements. module flexilog (input a,b,c,d,e,f, input sel, output x); wire st1, st2, st3; assign st1 = sel ? a | b : a & b; assign st2 = sel ? c | d : c & d; assign st3 = sel ? e | f : e & f; assign x = sel ? st1 & st2 & st3 : st1 | st2 | st3; endmodule

The order of the statements is of no significance. It is also possible to use a single multiplexer and build the whole circuit for each input: module flexilog (input a,b,c,d,e,f, input sel, output x); assign x = sel ? (a|b) & (c|d) & (e|f) : (a&b) | (c&d) | (e&f); endmodule The original solution would also allow us to implement a&b&c&d&e&f and a|b|c|d|e|f if we controlled the two multiplexer stages independently using different select signals.