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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2011

A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity
Hassan Mostafa, M. Anis, and M. Elmasry

Abstract—Nanometer SRAM cells are more susceptible to the particle strike soft errors and the increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, an analytical model for the critical charge variations accounting for both die-to-die (D2D) and within-die (WID) variations, over a wide range of bias conditions, is proposed. The derived model is verified and compared to Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper shows the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. It demonstrates that the adoption of the coupling capacitor reduces the critical charge variability. The derived analytical model accounts for the impact of the supply voltage, from 0.1 to 1.2 V, on the critical charge and its variability. Index Terms—Deep sub-micrometer, process variations, reliability, soft errors, static random access memory (SRAM).

Fig. 1. SRAM cell with the particle strike current pulse (i

(t)).

I. INTRODUCTION Reliability is one of the major design challenges for sub-micrometer CMOS technology. Shrinking geometries, lower power supply, higher clock frequencies, and higher density circuits all have a great impact on reliability [1]–[4]. As CMOS technology further scales, soft errors become one of the major reliability concerns. Soft errors are caused by alpha particles and high energy neutrons. These particles generate charges which disturb the node voltage and lead to soft errors [2]. In memory elements such as static random access memory (SRAM) and flip-flops, if the charge collected by the particle strike at the storage node, is more than a minimum value, the node is flipped and a soft error occurs. This minimum value is called a critical charge ( critical ), which is used as a measure of the memory element immunity to soft errors [2], [4]. This critical charge exhibits an exponential relationship with the soft error rate (SER) [2], and consequently, this critical charge should be designed high enough, to limit the SER. SRAM cells are more vulnerable to soft errors due to their lower node capacitance. Process variations are expected to worsen in future technologies, due to difficulties with printing nanometer scale geometries in standard lithography. Therefore, these variations are considered another main challenge in CMOS technology scaling [5], [6]. They are classified as die-to-die (D2D) variations and within-die (WID) variations. In D2D variations, all the devices on the same die are assumed to have the same parameters values. However, the devices on the same die are assumed to behave differently in WID variations [5]. Due to the existence of process variations, the critical charge has variations around its nominal value which results in SRAM failure to meet robustness constraints. Recently, researchers have attempted to calculate the critical charge nominal value as well as addressing the impact of process variations on the critical charge in memory elements such as SRAM cells and flip-flops. However, most of this research is conducted by using Monte Carlo analysis tools [1], which are time consuming and not scalable

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with technology. From a design perspective, few articles have been published on modeling the critical charge and its variations [7], [8]. However, all these models consider only the super-threshold SRAM cells with only D2D variations taken into account. The tradeoff between performance and power consumption makes the super-threshold SRAM design essential for high performance with the drawback of large power consumption. On the other hand, it makes the sub-threshold SRAM design, while energy efficient, has the drawback of performance degradation. To retain the excellent energy efficiency while reducing performance loss, near-threshold SRAM design is proposed [9]. Accordingly, an analytical critical charge variability model, accounting for all the SRAM cell operating regions and considering D2D and WID variations, is of paramount importance, to predict the SER variability over wide range of bias conditions. In this paper, an analytical model of the critical charge variability, accounting for both D2D and WID variations, is proposed, for a wide range of bias conditions including super-threshold, near-threshold, and sub-threshold SRAM operation. The derived model is simple, scalable in terms of technology scaling. Moreover, it shows explicit dependence on design parameters such as node capacitance, transistors sizing, transistor parameters, and supply voltage. The results are verified by using SPICE transient and Monte Carlo simulations and an industrial 65-nm CMOS technology transistor model. The rest of this paper is organized as follows. In Section II, the proposed critical charge model derivations are explained. The critical charge variability model is introduced in Section III. The proposed model is compared with SPICE transient and Monte Carlo simulations in Section IV. Finally, some conclusions are drawn in Section V. II. CRITICAL CHARGE MODEL DERIVATIONS Fig. 1 shows a typical six transistor (6T) SRAM cell. It consists of two cross-coupled inverters, that store two complementary logic values (“1” and “0”) at their output nodes. These output nodes are denoted by 1 and 2 . The SRAM cell has its highest susceptibility to particle strikes in the standby mode, in which, the storage nodes are disconnected from the highly capacitive bitlines. Thus, the access transistors a1 and a2 are excluded from the analysis. Assume that node 1 stores logic “1” and accordingly node 2 stores logic “0.” The critical charge are calculated for a 1-to-0 flip at node 1 or a 0-to-1 flip at node 2 . In the following analysis, it is assumed that node 1 is more susceptible to soft errors while the other case can be derived in a similar tendency. Therefore, in order to determine the critical charge model at node 1 , the particle strike is modeled by an exponential current pulse, connected to node 1 , given by [8]

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Manuscript received January 22, 2010; revised April 16, 2010, June 18, 2010; accepted August 07, 2010. Date of publication September 20, 2010; date of current version September 14, 2011. The authors are with the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON N2L3G1, Canada (e-mail: hmostafa@uwaterloo.ca; manis@vlsi.uwaterloo.ca; elmasry@uwaterloo.ca). Digital Object Identifier 10.1109/TVLSI.2010.2068317

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iinjected (t)  Q 2 exp(0t= ) 

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(1)

1063-8210/$26.00 © 2010 IEEE

Furthermore. are random dopant fluctuations (RDF).e. jVGS j  jVt j). and V tn2 are the standard deviations of the threshold voltages Vtp1 . Vtn1 . min is calculated by solving the following: C DD =2) = 1 +  [Ap(1V0 in1 ]: i (6) Equation (6) is a nonlinear equation that is solved numerically by using the Lambert W function (also called the Omega function). From (2). the proposed model deals with the D2D and systematic variations by using corner based analysis. the critical charge Qcritical is obtained as follows [7]. Now. f is the sum of min . ( ) [10].V . For simplicity.. the injected current injected ( ) continues decaying exponentially according to (1). the positive feedback of the cell becomes strong enough to continue flipping the cell state. The nodal current equation at node 1 is written as Q V  where 1 is node 1 capacitance. From the equations derived in Section III-A. these assumptions are verified in the simulation results (see Section IV). where jVt j is the transistor Mn2 . the currents ip1 .e. channel length variations. 0. Therefore. the goal is to find the condition on the current component. is employed.V V V = Q Q Q = CA (VDD =2) + [ip1 0 in1 ][tmin +  ]: t tmin =  ln( + tmin = ). respectively. p1 . A small change in these threshold voltages results in an incremental change in the critical charge that is calculated by using Taylor expansion around the nominal value. t . the value of . These currents have different dependence on jVGS j based on whether the transistors are operating in the super-threshold region (i. the near-threshold region (i. is introduced in [11] and given by where C2 is the capacitance of node V2 . All these process variation sources affect on the device threshold voltage. Also.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. we assume that once node V1 voltage hits its minimum value Vmin . M is assumed to be DD 2. and n2 . Thus. min is expressed as x tmin =  [0 0 01 (0exp(0 ))] x x< t t V t t V = M (7) partial derivative terms in (13) are computed numerically at the mean threshold voltages. In addition.. and is the falling time [2]. the delay tup is expressed as DD = tup = [Cp22V0 in22] (8) i ln 1 + exp jV 2j0jV j n i=K jV j0jV j 1 + ln 1 + exp E L 2 (10) t i i i t where is the sub-threshold swing coefficient. min ). The . This assumption is justified by noting that after the time min . and line edge roughness (LER). However. restoring current causes V1 voltage to either recover to logic “1” and no flipping occurs. that affect the device parameters. Now. 1 is assumed to remain constant at min .” If min is slightly below the switching voltage of the second inverter. NO. The V where 01 ( ) is defined for (exp(01)  0) [10]. is obtained by equating min to DD 2 and given by 1 Vmin = VDD 0 C1 (Q 0 [ip1 0 in1][tmin +  ]): (4) In this model.e. in consideration. This is due to the fact that t of the four transistors. the random variations are treated by using the following statistical analysis. n1 is the nMOS transistor n1 current.e. restoring current. and the time delay that 2 takes to rise from 0 V to DD 2 (this time is denoted by up ). ip2 . VDD =2. respectively. of VDD . @Qcritical 2 2 + @Qcritical 2 2 V V @Vtp1 @Vtp2 0:5 2 2 2 2 + @Qcritical V + @Qcritical V (11) @Vtn1 @Vtn2 where V tp1 . resulting in fluctuations in the critical charge. V tp2 . 11. The standard deviation of the critical charge variations is calculated as follows: V V t V V V = V V t V V V = V V = V Q M . V tn1 . and sat are obtained from the transistor model files. In this paper. the objective is to find the flipping time f .V i V = <V = V V V III. or flip V By solving the differential equation in (2) and using (3). Due to the fact that the inverter switching voltage M is defined as the threshold between logic “1” and logic “0. that causes node 1 to flip. node 1 voltage attains a certain minimum value min . has a gate to source voltage jVGS j. STATISTICAL CRITICAL CHARGE VARIATION MODEL Process variations affect device parameters. jVGS j  jVt j). which tries to pull-up node 1 . A unified physical current formula. [8]: Qcritical = Q(1 0 exp(0tf = )): (9) In the above derivation. with technological parameters shown in Table I. The value of min is given by threshold voltage. Vtp2 . jVGS j  jVtj) or the sub-threshold region (i. are identified as four independent and uncorrelated Gaussian random variables. This restoring current is controlled by its gate voltage 2 . n L E n K E V i V V V . an industrial 65-nm technology.e. and Vtn2 . sat is the velocity is saturation electric field. until 2 rises and exceeds DD 2. which refers to the SRAM cell flipping time. t where (5) By substituting (5) in (3). which are denoted by tp1 tp2 tn1 . where their gate voltage V1 is constant at VDD =2.. is the transistor channel length. [ p1 0 n1 ]. and in2 . This assumption simplifies the derivation of (13). p1 is the pMOS transistor. when the currents [ p1 0 n1 ] and injected ( ) are equal. min DD 2). for the time interval over which 1 is approaching min (i..M . M 2 2 rises to logic “1” decreasing the current component [ p1 0 n1 ] and resulting in a soft error. Consider the flipping case (i. This delay is driven by transistors p2 and IV. It should be noted that the correlation between the different transistors threshold voltages is neglected for random WID variations [12]. and a fitting parameter that is extracted from simulations. that just cause 1 to flip. and tn2 . and injected ( ) is the injected current pulse given in (1). The time at which min occurs is denoted by min and given by C M C1 dV1 = [ip1 0 in1] 0 iinjected (t) dt V i i t V i i (2) M V V i i tmin =  ln  [ip1Q in1 ] : 0 t V t (3) to logic “0” and flipping occurs. The primary sources of process variations. and VDD =2. that is used for all the transistor operating regions. the pMOS transistor Mp1 . By solving the nodal current equation at node V2 . These assumptions are validated by noticing that once 2 hits DD 2. VOL.M V = M V . in1 . RESULTS AND DISCUSSION In all the following simulations. 19. NOVEMBER 2011 2131 where is the total charge deposited by this current pulse at the struck node. it is evident that the critical charge critical is dependent on the threshold voltages of transistors p1 p2 n1 .. The time at which 2 hits DD 2 is denoted by f . node 2 voltage stays around 0 V. and then starts to rise. respectively.

the SRAM cell exhibits a soft error for VDD = 1 V and VDD = 0. Two nodes V and V for V = 0. B.0 V.3 V in (a) the non-flipping case and (b) the flipping case. Two nodes V and V for V = 1. Moreover. VOL. 2 and 3 are 1 GHz and 1 MHz. A. These simulations are performed to validate the nominal critical charge. is used in the simulation setups. shown in Table I. 2(b) and 3(b) show that when the V2 node voltage hits VDD =2. Q. The two nodes V1 and V2 voltages in the non-flipping case are shown in Figs. Figs. whereas. 3. 11. 2(a) and 3(a) for VDD = 1 V and VDD = 0. the SRAM cell is recovered. because the SRAM cell timing response is slower when VDD = 0. the simulations are repeated for different VDD values (from 0. Verification of the Model Assumptions The assumptions used in deriving (3) and (4) are verified. In the following. A large number of Monte Carlo runs (4000 runs) are used to provide a good accuracy in determining the critical charge mean and standard deviation. respectively. 1) Nominal Critical Charge: Fig.2132 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. Hardware-calibrated statistical models are used to account for Vt variations.2 V).0 V in (a) the non-flipping case and (b) the flipping case. since V2 voltage does not hit VDD =2. 2(b) and 3(b) show that node V2 voltage is around 0 V as long as node V1 voltage is falling. the clock frequencies used in Figs. NOVEMBER 2011 Fig. that causes the cell to flip is determined. 19. Verification of the Model Estimated Critical Charge To verify the critical charge nominal value. The clock frequency is 1 MHz and  = 250 ps. Then. . the analytical model is compared to the simulation results using SPICE transient and Monte Carlo simulations.1 to 1. and the critical charge variability model. respectively. 4 shows the nominal critical charge value calculated from the proposed model. Figs. the difference between them is less than 4% of VDD and is ignored.3 V than that when VDD = 1. It is clear that. VM is slightly less than VDD =2. Fig. 2. respectively. node V 2 voltage rises to VDD =2.3 V. Once node V1 voltage hits Vmin . However.3 V. and the critical charge variations model. V1 stays constant at Vmin . The SRAM sizing. to find the effect of reducing VDD on the critical charge mean and variations. The clock frequency is 1 GHz and  = 250 ps. the value of the current pulse charge. It should be noted that the actual value of the inverter threshold voltage. NO. For each Monte Carlo run. respectively. Also. and compared to TABLE I 65-nm TECHNOLOGY INFORMATION AND SRAM SIZING [13] SRAM cell is sized such that its stability is maintained. as reported in [13]. the validation results for this model are presented.

and Cc . The model results exhibit a good match with the simulation results. the near-threshold. is employed between the storage nodes (V1 and V2 ). This coupling capacitor Cc increases the nodal capacitances of the SRAM cell storage nodes. 19. Also. 2) Critical Charge Variations: In Section III. 5 shows the results from the proposed model. 11. Thus it is important to see the impact of increasing the node capacitance on the relative critical charge variations. and the super-threshold regions.6 V). It is obvious from Fig. Overall relative variations ( when = 250 ps. the transient simulations results for different supply voltage values. which is expected.4 to 0. The average Qcritical error for the sub-threshold. the model in [8] accounts only for D2D variations.8%. in which the value of Q is obtained by using SPICE simulations at the required corner. NO. Also. and the sub-threshold SRAM design. Note that each data point represents Q calculated from 4000 Monte Carlo runs. Therefore. 4 that reducing the supply voltage decreases the critical charge. and 11. and from the proposed model. when  = 250 ps. by applying the Miller effect as follows [8]: C1 = C1 + 2Cc C2 = C2 + 2Cc : (12) Fig. Usually. and 3. Although this method is used in calculating D2D variations by using corner-based or worst-case methods.9%. 2) In [8].  . a coupling capacitor. reduced for low power applications. 3. Fig.2%.1 to 0. NOVEMBER 2011 2133 Fig. Also.9%. 5. Finally. Consequently. the proposed analytical model advantages are summarized as follows. Fig.2%. VOL. respectively. This technique can not be used for the WID statistical variations. Q is calculated analytically without performing any SPICE simulations. since Q must be calculated for each statistical run. The WID variations modeling is much more complex and difficult than D2D variations modeling because D2D variations are easily modeled by using corner-based techniques .8%. versus V for  = 250 ps. Fig. 4. the limitation in [8] for WID variations modeling is refined. and 7. these results demonstrate that as VDD is is decreased. the near-threshold. whereas the average Qcritical error for the sub-threshold. are 4.2%. The decreasing rate of D. and the average error is 3. In (5). and the super-threshold regions.3 V). Q versus V for  = 250 ps. Cc . It should be mentioned that the unified current in (10) has different precision for different SRAM operating regions. and the super-threshold region (VDD = 0. The proposed model is in good agreement with Monte Carlo simulation results.7 to 1. 6. This precision affects the accuracy of the proposed model for different operating regions.6%. 3) Both D2D and WID variations are taken into account in the proposed model. are 2. respectively. their critical charge is increased significantly. have to be modified to account for Cc .IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. and 6. 5 shows the simulation result for Q VDD values. The maximum Qcritical error for the sub-threshold region (VDD = 0.3%.1%. as Cc and VDD Qcritical from the proposed model is compared with transient simulation results for different values of . respectively. The maximum Qcritical error for the sub-threshold. The maximum error is 7. are 5. 9.3%. are 7. the derivation of the critical charge standard deviation using the proposed model is for different described. Moreover. the near-threshold. It is obvious from Fig. ferent values of V   = ) versus C for dif- increase. and an average error of 6. and the super-threshold regions.5%. Qcritical exhibits a maximum error of 11. 1) The proposed model accounts for different bias conditions including the super-threshold. Accuracy of the Proposed Model Fig.6%. 6 portrays the overall relative variations (Q =Q ) versus Cc obtained from Monte Carlo simulations. 6 that.2%. for different values of VDD . Critical charge variations. and therefore. the near-threshold. VDD . Good agreement between the proposed model and the simulation results justifies all the assumptions used to derive the model. The model capacitances C1 and C2 . 6. Q (Q =Q =Q ) is larger for higher values of VDD . decreases. the value of the injected current pulse charge Q is obtained via iterative transient simulations by increasing Q by a small amount ( 0.3%. 6. Effect of the Coupling Capacitor on the Critical Charge Relative Variability One of the most common techniques to mitigate soft errors in SRAM cells is increasing its node capacitance. the near-threshold region (VDD = 0.001 fC) in SPICE till flipping occurs.2 V). respectively.9%. Q C.

” 2010. Des. S. 175–185. Singapore: World Scientific Publishing. Then. “Measuring leakage power in nanometer CMOS 6T SRAM cells. pp. (PACT). shifting all devices threshold voltage. by using corner-based methods.net [7] Y. E. Jin.e. and sub-threshold regions. J. 0. pp. Giot. VM . M. 28th Euro. Horstmann. Y. the coupling capacitor adoption. constraints on the SRAM static noise margin. Reconfig. 658–663. (IOLTS). 512–515. and 22 nm). Conf. Very Large Scale Integr. [13] M.” in Proc. since.” in Proc. [6] ITRS. T. and the pulse width. “Factors that impact the critical charge of memory elements. Equation (11) models the impact of the WID variations on the critical charge. and D. T. The simulations results are shown only for WID variations modeling due to space limitations. . Analytical formulas for the critical charge mean and standard deviation are required for this statistical framework design. WID variations modeling requires representing each device parameter. 9. including superthreshold. within the same die. the inverter threshold voltage. This assumption is verified for the proposed SRAM sizing. Sep. pp. 17. 32. Therefore..8% for all SRAM operating regions. The proposed model shows that.. Syst. B. Baba. [9] R. Signal Process. for an industrial 65-nm technology. Int. the proposed model is scalable in terms of technology scaling and can be used to predict the critical charge variability for future technology nodes. the new value of the critical charge is calculated from the proposed model analytical formulas at this corner. Therefore. on the critical charge variability. (DAC). H. Zhai. Keshavarzi. [12] J. (DAC). 2008.. Xie.. Accordingly. T. length. area. 45. are imposed. VOL. 1–7. “The international technology roadmap for semiconductors. Duarte. and critical charge. Chapeau-Blondeau and A. Chatila. De. and H. B. Karnik. 2006.” in Proc.. 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IEEE Int. “Analysis of soft error rate in flip-flops and scannable latches. Autom. Heijmen. NO. if VM is far from (VDD =2). Mudge. V. [Online]. Chip Conf. 12th IEEE Int. Kameyama. [5] S. Ibe. 294–299. NOVEMBER 2011 4) 5) 6) 7) which assume that all devices on a given die have the same parameter value. However. 11. no.