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6, JUNE 1976





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combinational circuit," in Proc. Symp. Math. Theory of Automata, Apr. 1963, pp. 484-528. D. B. Armstrong, "On finding a nearly minimal set of fault detection tests for combinational logic nets," IEEE Trans. Electron. Comput., vol. EC-15, pp. 66-73, Feb. 1966. F. J. 0. Dias, "Fault masking in combinational logic circuits," IEEE Trans. Comput., vol. C-24, pp. 476-482, May 1975. W. Kautz, "Testing for faults in cellular logic arrays," in Proc. IEEE Symp. Automata Theory and Logic Design, 1967, pp. 161-174. P. R. Menon and A. D. Friedman, "Fault detection in iterative logic arrays," IEEE Trans. Comput., vol. C-20, pp. 524-535, May 1971. R. W. Landgraff and S. S. Yau, "Design of diagnosable iterative arrays," IEEE Trans. Comput., vol. C-20, pp. 867-877, Aug. 1971. A. D. Friedman, "Easily testable iterative systems," IEEE Trans. Comput., vol. C-22, pp. 1061-1064, Dec. 1973. F. J. 0. Dias, "Multiple-fault analysis in combinational logic circuit," Ph.D. dissertation, Stanford University, Stanford, CA, July 1975. F. C. Hennie, "Fault detecting experiments for sequential circuits," in Proc. 5th Ann. Symp. Switching Theory and Logical Design, 1964, pp. 95-110. --, Finite-State Models for Logical Machines. New York: Wiley, 1968.

[13] H. W. Gschwind and E. J. McCluskey, Design of Digital Computers. Amsterdam, The Netherlands: Springer, 1975.

Francisco J. 0. Dias (S'72-M'75) was born in Sao Paulo, Brazil, on December 5, 1945. He received the B.S. degree in electrical engineering from the Escola Politecnica, University of Sao Paulo, Sao Paulo, Brazil in 1969 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1972 and 1975, respectively. From 1970 to 1971 he was an Instructor at Escola Politecnica and from 1972 to 1975 a Research Assistant at Digital Systems Laboratory while working towards the Ph.D. degree at Stanford University. Presently he is an Assistant Professor at University of SAo Paulo, where he has been involved in research projects of testing and reliability evaluation. His present interests include fail-safe systems, cellular arrays, and reliability calculations. Dr. Dias is a member of Sigma Xi.


Transition Count Testing of Combinational Logic Circuits

Abstract-Logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from the correct TC c(Ro). This paper presents a formal analysis of TC testing. It is shown that the degree of detectability and distinguishability of faults obtainable by TC testing is less than that obtainable by conventional testing. It is argued that the TC tests should be constructed to maximize or minimize c(Ro). General methods are presented for constructing complete TC tests to detect both single and multiple stuck-line faults in combinational circuits. Optimal or near-optimal test sequences are derived for one- and two-level circuits. The use of TC testing for fault location is examined, and it is concluded that TC tests are relatively inefficient for' this purpose.
Index Terms-Combinational logic circuits, fault detection, fault diagnosis, minimal test sets, test generation, transition count (TC) testing. Manuscript received July 9, 1975; revised December 2, 1975. This research was supported by the Office of Naval Research under Contract N00014-67-A-0269-0019, and by the Joint Services Electronics Program through the Air Force Office of Scientific Research/AFSC under Contract F44620-71-C-0067. The author is with the Department of Electrical Engineering and the Computer Science Program, University of Southern California, Los Angeles, CA 90007.


SEVERAL commercially available testers for digital logic circuits employ the following technique for fault diagnosis. A predetermined sequence of test patterns is applied to the unit under test (UUT). The response sequence R appearing at some selected test point P of the UUT is monitored. Rather than recording the entire sequence R at point P as is done in conventional testing, only the transition count (TC) c(R) of R is recorded, i.e., the number of times the signal at P changes value (from 0 to 1 or from 1 to 0). The TC c(R) is then compared to the TC c (Ro) that should appear at P if the UUT is fault-free. If c(R) and c(Ro) differ, it can be concluded that a fault has occurred in some part of the UUT having P as a primary output line. By repeating this procedure for other test points in the UUT a high degree of fault detection and isolation may be possible. We will refer to this test method as transition count testing or TC testing. Fig. 1 shows the flowchart for a typical TC testing algorithm. Consider the NAND network NA shown in Fig. 2. Fig. 2(a) shows the response sequence appearing on every line of NA resulting from the application of a particular test sequence S of length 5. Fig. 2(b) shows the corresponding TC's on every line. Suppose the fault f = "line

rm be any mr-bit binary sequence. ated test patterns such as Gray-coded or pseudorandom Definition 2: S is a TC test for N with respect to F if sequences are usually employed in TC test systems. Thus. For the given c(R) = E (ri @ ri+ ). Standard easily gener. (b) Corresponding TC. the number of test patterns it In this paper a formal analysis of TC testing is pre. to change from 11110 to Section V. eration of optimal or near-optimal TC tests to detect single and multiple stuck-line faults in combinational a stuck-at-1" is present in NA. a substantial reduction in fault dic..contains. only their TC's are needed. where I SI demade. sented. Note that although f also Definition 1: The TC c(R) of R = rlr2**-rm is given by changes the response sequence on output line Z2 (from m -I 00011 to 00111).614 IEEE TRANSACTIONS ON COMPUTERS. is Let R = rlr2*.F = fF1. notes the length of S. TC testing has the addi. the sequence obtained by complementrect response sequence Ro. PROPERTIES OF TRANSITION COUNT TESTS shown in Fig. S is minimal if for every TC Hence..sum modulo 2. ing every bit of R. by storing TC's instead of entire re.. Fault location using TC testing is examined in on zi. Let sponse sequences.If R = Fl2-. and rxl denotes the smallest integer greater than for an n-input logic circuit N.F2.quence of n-bit vectors where si C Bn for 1 < i < m. The number of bits required to represent c(R) is at Let Bn denote the set of all 2n n-bit binary vectors. This is reflected in a change in TC from 1 to 3 as II. where IRI is the length (number of bits) Bn can be considered as the set of possible test patterns of R.. ther the observed test response sequence R or the cor. . I SI < IS'I.FuJ be a set of possible faults in N. This causes the sequence circuits. (a) Response of NA to a test sequence S of length 5.. Typical TC testing algorithm. 11010.m be a seor equal to x.-. then c(R) = c (R). Hence. 1. chosen as the test point. Let S = S1S2 . it is not necessary to record eiIt follows from this definition that 0 < c (R) < m -1. i. ventional test methods. JUNE 11010 1976 11110 (a) zI z2 (b) Fig. most rlogl RI]. c(Ro) M c(RA) for 1 < i < u. Sections III and IV consider the genFig. the output of gate G1.. The properties of TC tests and the problem of constructing efficient TC tests for combinational circuits are investigated. unlike most con.e. very simple and inexpensive TC testers can be test S' for N with respect to the response observed at some test point when S is tional advantage that the basic test circuitry needed is a applied to the fault-free circuit N.. and let Ri be the cortransition detector and counter. 2. 2(b). i=l1 test sequence. Let Ro tionary size may be possible. therefore. Z2 is not a suitable test point for detecting f. fault f is detectable by transition counting if S is used as the test sequence and z.Pm. The relationship between TC testing and conventional testing is examined in Section II. and a general heuristic rule for designing "good" TC tests is proposed. it does not affect its TC.responding response when fault Fi E F is present. where z denotes arithmetic summation and @D denotes TC testing has the advantage that.

Every TC test S for Gn must include every test pattern in T. First we examine the problem of TC test generation for a single n-input (NAND) gate Gn. S should be constructed so that c(Ro) is either as large or as small as possible. although N responds incorrectly to every input combination. are minimal TC tests. . We conclude that a fault in N is TC detectable only if it is detectable. Proof: If S* is nonminimal there must be a TC test S for Gn of length n + 1 and S must contain every 1 A circuit is irredundant if no lines or gates can be removed from the circuit without altering its output function. hence the TC is zero. a sequence of length n + 2 is needed. To simplify the analysis only irredundant' NAND circuits will be treated. consider the following faults involving the output line z of N: fo = "line z stuck at 0" and fi = "line z stuck at 1.een-lenel.1) el= (0.c(Ro)) we should attempt either to minimize or maximize c(RO).1." The response to every input sequence applied to N with fo(fl) present is a sequence consisting of all 0's (l's). Two faults in N are said to be distinguishable if they produce different output sequences in response to some input sequence.' III.i) for 1 .1) en= (1. is a single-output circuit whose primary output line is the test point used for monitoring TC's. All faults in Gn can be detected in the conventional manner using a unique set of n + 1 test patterns T.ISI >n+ 1. * -. In order to maximize its fault coverage a TC test S should be chosen so that as few potential fault responses as possible have the same TC as the correct response Ro. we can state the following general heuristic rule for the design of TC tests.i-1).1.. An input sequence S to a single-output circuit N will be called a single (multiple) fault TC test for N if S is a TC test for all single (multiple) stuck-line faults in N when the primary output of N is the test point used for observing TC's. where the fault model is the standard stuck-line model. T is the unique minimal test set for Gn with respect to both single and multiple faults [1]. . while two faults in N are TC distinguishable only if they are distinguishable.0). the circuit under test. hence to minimize C(m.0.c(Ro)) should be minimized. If the UUT is purely combinational. hence. A fault F in N will be said to be TC detectable if some sequence S is a TC test for F. respectively. C(m.1. For n > 2. Any line in a circuit may be either stuck at logical 0 (s-a-0) or stuck at logical 1 (s-a-1). Faults that are distinguishable in the usual sense may not be TC distinguishable.. Rule 1: To maximize the fault coverage of a TC test 5. and a given set of test patterns may be rearranged in any way to increase or decrease c(RO).. and S2 = e1ue2. No input sequence is a TC test for N. FAULT DETECTION BY TRANSITION COUNTING In this section we consider the design of TC tests to detect stuck-line faults in combinational circuits. S* is a minimal TC test with respect to both single and multiple faults for an n-input gate Gn.m < 10. in the case of NAND gates. The fact that c(R) = c(R) implies that faults may exist that are detectable in the usual sense but are not TC detectable. Both single faults (only one line s-a0/1) and multiple faults (one or more lines s-a-O/1) will be considered. Thus.i) = 2(ml1).i) + C(m. Two faults are TC distinguishable if they produce output sequences with different TC's in response to some input sequence. In general some flexibility exists in choosing S and therefore in choosing c(Ro).HAYES: TC TESTING OF COMBINATIONAL LOGIC CIRCUITS 615 It is convenient to assume that N. fo and f.1. Each row of this table can be conveniently computed from the row above it using the following relationship (which is essentially Pascal's Formula): C(m + 1. If the UUT is sequential then arbitrary reorderings of input patterns are not usually possible.1) e2= (1. respectively. When using transition counting for fault detection. An example of such a fault is one causing the function z appearing at the observed output of N to change to its complement z. In the following sections we consider the problem of generating TC tests for single-output combinational circuits. The correct responses to u and ei are 0 and 1. are distinguishable but not TC distinguishable. It can easily be shown that C(m. Thus.. Let S by an input sequence for N whose correct m-bit output response is Ro. Table I shows all nonzero values of C(m. Let C(m. .c(Ro)) = 2(QOf)). T may be conveniently divided into n e-tests and 1 u-test [1] where. C(m. In each case the converse is false. however. the order in which test patterns are applied does not affect its behavior.1. We now pose the question: what is the "best" value of c(RO) so that as many faulty response sequences as possible have TC's different from c(Ro)? While the exact answer depends on N and the set of faults under consideration. Theorem 1: Let S* = uele2. For n = 1 and n = 2 it is easily shown that the sequences Si = uel. where n > 2. it is possible to formulate a general measure of the "goodness" of c(Ro). u = (1.i) be the number of binary sequences of length m wfth TC i.i)= C(m.1. This is equivalent to saying that the circuit is irredundant if it contains no undetectable single or multiple stuck-line faults. while the gate functions remain unchanged. In other words. it can be shown that this involves no significant loss of generality [1]. For example. it is of interest to find test sequences with the property that as many faults as possible produce incorrect TC's.

1. U S* is by no means the only minimal TC test for gn. enel.. Therefore. the resulting output N.. u.2 2 2 10 18 2 - - - . Let Tr (T1) be all tests in T producing result is output 0 (1) respectively from N. be extended to mulS*= u e1e2 en_lenel. otherwise t Chave T. In this case the output of Gn is effecchanges to x2. Let Ro denote the fault-free response of N to any seRo =***. quence S* = tlt2---tm with the following properties. the faulty output and c (R) = c (Ro) so S is not a TC test for the single response is not Ro. We have faults.. Hence. so SF is a TC test for Gn which is minimal with respect to both 2 3 4 5 6 7 8 9 2 5 2 7 2 2 9 . No single fault c(Ro) = 1 if u is the final test in S while c(Ro) = 2 oth. tiple faults when N has more than one output. Since n > 2... erwise. If e1 passes. eeju..* dnO. Hence. Property 1: S* contains every member of T. the position of u in S is such that it is either preceded or followed by a of TB is a TC test for single faults in NB. Suppose 2 e-tests precede NB. where a de2 2 notes the complement of u. R* = O O d . detectable if the output z1 of Nc is used as a test point. then we can write Lemma 1: Let T be any test set for all single faults in S =. however. This is an irredundant realization of Zc = (Zl. the output of Gn is effectively s-a-0.1. If e1 fails then the tional circuit N..fails.Z3). c redundant with respect to Z2. then ti+l C Tc for 1 < i < m . In some situations it may 14 42 8 70 14 2 70 42 be necessary to repeat test patterns in order to con16 56 112 140 112 56 16 18 72 168 250 250 168 72 struct a TC test. Corollary 1 cannot. b. i. F cannot be detected by using Z2 as a test point for monitoring TC's. Again the faulty response R* is whole is not redundant. sponse when fi is present. Z2 Case 1: u fails. Clearly c(R*) > 2. * Property 2: S* is an alternating sequence of tests where di C 10.1 1 0***.616 IEEE TRANSACTIONS ON COMPUTERS. Consider the circuit NB shown in Fig. S* is a single-fault TC test for N. This implies that ti yields the correct reR = 1 0 0. c(R*) = 0 c (R*). i). then we from TO and T1. the number of binary sequences of length m with possible input combinations TB are needed to detect all TC i. although a rigorous proof of this has not been found. Thus.. Theorem 2: Let T be any (possibly minimal) singleThis is the case where j inputs of Gn are s-a-1.Z2. It can be shown that none of the 8! sequences that are formed by permuting the members member of T exactly once. the sequence S' = e1e2e3au. ti must place d on line i when N is fault-free. although the circuit as a Case 2: u passes and all e-tests fail. 3 2 4 2 Although a is an inessential test in the sense that all the 4 2 6 6 faults it detects are detected by other members of S'. S* = u e1e2 ek enel.. . F is TC such that c(R*) = c(Ro).. S must contain a test ti which detects the fault "line vector is i s-a-d. F comprising lines a.. A similar argument holds if u is followed by a Corollary 1: No single fault can change any output pair of e-tests. Let Ro be It is believed that Lemma 1 also holds for multiple the correct response to S*. Consider Ro= l *--1 1 19 the circuit Nc in Fig.. This is due to the fact that much of Nc is tively s-a-1. I . in all cases c(R*) # c(R ). All 8 C(m.can change the output response of N to S from Ro to Ro. .. network N from z to z. 6 10 20 20 10 2 S* is an example of a TC test in which an individual 2 12 30 40 30 12 test pattern (ei) is repeated. is a minimal TC test for G3. t1 E T0.e. We now show that S* is a TC test for Gn... If ti C Td. an irredundant single-output combinational network N.. 4.> 3. and c all s-a-1 is present. ing sequence of O's and l's.. however. The fault f/ = "input j of Gn s-a-i" is detected Proof: Suppose fault fi = "line i s-a-d" is present in by ej only. If fj is present in Gn. the length of a TC test for Gn is function in an irredundant multioutput combinational at least n + 2. at least one member of TB must be repeated in any TC test for sequence of 2 or more e-tests. If the triple fault and c(R*) = 1. There are three cases to consider. R4 has the maximum possi1 and c(R*). Construct a test seS* = u ele2 ei . Case 3: u passes and j e-tests fail where 1 < j < n -1. Some fault test set for an irredundant single-output combinatest ei passes and some test ek. hence.. 2 For example. if I Tj > IT'l. where Z2 = X2.. . . 3 which realizes the function ZB = XlX2X3 + xlX2X3." Hence. U fault fj. quence S containing every member of T. (single) faults in NB. JUNE 1976 TABLE I i 0 single and multiple faults. a 2 2 8 8 12 is essential to making S' a TC test. Proof: The correct response Ro to S* is an alternatR * = 0 1d2 ---0 dn 1.

1.tlJ be a (not necessarily minimal) set of r tests for a two-level circuit N. For D < 1.thenr.t. Theorem 2 proves that every single fault in a singleoutput combinational circuit is TC detectable using less than twice the number of tests required for conventional testing.. m .0 0. Case 4: Some t° C TO fails and some to E TO passes. ..* to_ lto of length r + 2 is a TC test for N with respect to both single and multiple faults.TP) be a minimal set of r tests for a two-level circuit N. In the following section this problem is examined for the restricted but important class of two-level combinational networks.T1} for N. Case 2: All tests in TO fail. TX > 1 and Tll > 1... x1 x2 x2 Fig. For simplicity we will only consider sum-of-products realizations such as that shown in Fig.--d Odd.11tt°t . Hence. in all cases c(R) $ c(Ro)... The argument of the preceding case again implies that U c(R) 2. Hence.. Hence. Network NB realizing ZB = XlX2X3 + lx2xt3 xI RotoRo. .. Case 1: All tests in T1 fail.T1l. Proof: The fault-free response to S* is Ro: Ro=111 l. We can partition T into two sets: TO = consisting of the tests jt°.. so R is a sequence of l's and again c(R) = 0. Theorem 4: Let T = 1T0.. No single or multiple fault can change the response of N to S from Fig. Corollary 3: Let D be the absolute value of the difference between TI and T'j in a minimal single-fault test set T = IT0. FAULT DETECTION iNI Two-LEVEL CIRCUITS Every combinational function can be realized by a two-level circuit. R =1 d * * 0. Then.. Theorem 3: Let T = Itlytt. d Idd d . then l S*= t . Let D be the absolute value of 1 .. and c(Ro) = 1. T1I I < 2(171 -1). or. in functional terms.t -.... hence. Case 3: Some t' C T1 fails and some tJ C T' passes.T11 be a minimal single-fault test set for N. S* is a singlefault TC test for N.t ..thenm=r. a multiple fault can com- ble TC. A failure of one of these tests implies that one or more input lines of the output (NAND) gate Go are effectively s-a-1. respectively.. the output of N is effectively s-a-0 hence. Proof.. The following lemma is a stronger version of Lemma 1 for two-level circuits. t. Let Ro denote the fault-free response of N to any sequence S containing every member of T. . 1000. Then N has a single-fault TC test of length p < 2 max {l TI." The failure of all tests in T1 implies that all inputs to Go are effectively s-a-1 which in turn implies that the output of N is effectively s-a-0.. Let m be the length of a minimal multiple-fault TC test for N.. IV. our results can be immediately extended to productof-sums realizations by applying the Duality Principle. Lemma 2: Let T be any test set for a two-level circuit N. ' Proof: Let TO (T') be the subset of T producing output 0 (1). and c(R) > 2. If t' (a repeated test in S*) fails. a) IfD1<.. d. 3. If t 1 passes. t. the response R to S* is a sequence of O's and c(R) = 0. Then the sequence S* = t] t1 t2 tq _It qtptlt . It has been shown [2] that T also detects all multiple faults in N.1. as argued in the proof of Lemma 2..---. The problem of finding a minimal or near-minimal TC test sequence for an arbitrary combinational network N is not easy. When D > 1. it appears to be at least as difficult as the corresponding problem of finding a minimal test set for N. If Ro changes to Ro all tests in T' must fail. Corollary 2: Let T = rT0. then S* = titi ti ti_l1t0t0o *t°. 3... If D < 1. 4. the TC test S* defined in Theorem 2 may be nonoptimal. Irredundant network NC in which plement Z2. to R =0 d. we can refer to T unambiguously as a test set for and again c(R)( 2.. S* is a minimal single fault TC test for N..t°} and T1 = { producing response 0 and 1.d. for a sequence of length m. one or more prime implicants of the function realized by N have "disappeared.HAYES: TC TESTING OF COMBINATIONAL LOGIC CIRCUITS 617 x1 x3 x2 x3 X2- I xIxz~~~~~~~~~~~~ N. Let T be any single-fault test set for a two-level network N. In order for Ro to be a faulty response all tests in T must fail which is impossible by Lemma 1.. Then all tests in T1 must pass. the responses to S must be all O's which is a contradiction. b) IfD>1.m<r+2.. the TC test of length r defined in . We consider 4 cases. The only other sequence with the same TC as Ro is Ro.

the theorem [2] demonstrating the equivalence of single. To illustrate this problem we consider the derivation of TC location tests for an n-input NAND gate Gn. Theorem 4 also implies that provided D < 1. Thus.21 in c(R) obeys the in- -2ki < Di < 2ki. or else D5 = 0 which means that fi is not TC detectable.. Let s (n) be the length of a minimal single-fault TC location test for Gn. (For example. Thus. respectively [1].1.X3. Thus. FAULT LOCATION BY TRANSITION COUNTING We now turn to the problem of using TC tests for fault location (fault diagnosis). Let Lx] denote the greatest integer less than or equal to x.to1. then D5 = Di for some i in the range 1 S i < 4. if S distinguishes all TC distinguishable single (multiple) stuckline faults in N. [log2 (m + 1)] is a lower bound on test length. Using conventional testing. say el.n.0.g. If S is applied to Gn with fi the TC of R. x1 X2 x3 x4 x4 x2 Fig.X4) = (1. at least 2n tests are needed using transition counting. Gn.e6.2L4) + 1. the fault resolution obtainable by TC testing is inherently less than that obtainable by conventional testing. Two-level circuit ND. Consider the two-level circuit ND in Fig.2. Theorem 5: If s (n) is the minimum length of a singlefault TC location test for Gn. In order to distinguish m TC distinguishable faults and the fault-free condition.. Thus.X2. respectively. a TC location test of length n + 3 such as S4 = e4eie2eie2ue3 is required. The following theorem provides a lower bound on s(n) which is greater than the lower bound n + 2 for n > 6.. S is termed a single (multiple) fault TC location test for N.618 IEEE TRANSACTIONS ON COMPUTERS. JUNE 1976 Theorem 2 is a minimal single and multiple fault TC test for N. Let S=t t 73t? 15tllt°tl4t?ll.1.. k5 > 2. For D > 1. Thus a TC test for a two-level circuit N requires at most 2 more test patterns than are needed for conventional testing. Di = c(Ro) equality - Proof: Let S be any single-fault TC location test for present.e5.e4 such that ki = 1. Let ki be the number of occurrences of the test pattern ei in Gi for i = 1.e8 such that ki = 2. (1) In other words. that S is a TC test for each of the 20 possible single faults in ND. 5 which realizes the function ZD = X1X2X3X4 + X1X2X4. the number of distinguishable single-fault classes reduces to n + 1 since the faults "output s-a-0" and "output s-a-i" are not TC distinguishable. while n + 1 tests suffice for multiple-fault location in Gn using conventional testing. It can readily he verified that the sequences S2 = eje2eju and S3 = ele2elue3 are minimal TC location tests of length n + 2 for n = 2 and 3. s(n) > n + 2.t7.1) which produces output 0. hence it can be expected that fault location by transition counting will require substantially more test patterns. For n = 4.e2. ki > 1." This fault is detected by to and t15 and the resulting response to S is R = 0 1 0 0 0 1 0 0. Using TC testing.-1. Each incorrect response bit can cause a change of di E f-2. e. there is a minimal single-fault TC test for N that also detects all multiple faults. so that c(Ro) = c(R) = 4 and S is not a TC test for F. and so on. 5. Hence.0.tl4.1. however. a TC location test of length m + 1 or greater is needed. Consider first the problem of single-fault location in Gn.t3. Clearly for n > 2.e3. where n > 2. it follows that the number of e-tests in S is at least . then the observed response R differs from the correct response Ro in precisely ki bits. It might be expected that every single-fault TC test for a two-level circuit has this property. Similarly the number of multi- ple-fault classes reduces to 2n . Theorem 3 defines a multiplefault TC test of length r + 2." This fault can only be detected by ei.tl3. The numbers of distinguishable single and multiple fault classes associated with Gn are n + 2 and 2n. V. Hence. Let fi denote the single-fault "input line xi s-a-1. Let t1d denote the input pattern to ND representing the binary number i and producing output d. As noted earlier. for S to distinguish all single faults in Gn. to denotes the test (X1. This implies that f5 is indistinguishable from fi..) The test set T = It2. then s(n) > ([4J + 1) (n . the number of TC distinguishable faults is less than the number of faults that are distinguishable by conventional testing. xI ZD therefore Ro = 0 1 0 1 0 0 0 0. Consider the double fault F = "lines a and b s-a-i. In the same way it follows that there can be at most 4 e-tests say e5. there can be at most 4 e-tests. we now show that that is not the case.tlt5 is a complete and minimal set of tests for ND. Obviously. by enumeration.and multiple-fault test sets for two-level circuits cannot be extended to TC tests. There does not seem to be a simple relationship between s(n) and n. fi can cause the TC of the response to S to increase or decrease by at most 2ki. The inequality (1) implies that. If in addition k5 = 1. It can be shown.

single-fault TC location test for Gn. Theorems 6 and 7 show how a fault location test set T We now present a general method for constructing a for a gate can be used to construct a TC location test.the minimum possible value of c(RO). A better method of fault location is to apply a seS* is a single-fault TC location test for Gn of length ries of relatively short TC tests and observe the TC's at n(n + 1)/2 + 2. for 1 < i < n. As noted earlier at least 2n test patterns are needed in mercial TC testers cannot provide complete fault deteca multiple-fault TC location test for Gn. several different test points. where zero is Proof: The only multiple faults that need be con. As such it has then the output TC c (Ro) is decreased by which simplifies to j+ (l 1 n - L41) t Dj = k=1 2k-1 (1+1l)n-2 L1 2 .N2.TC detection tests in the preceding sections. Hence.. let n presence of stuck-type faults with a relatively small inTC location test for G6 is crease in the number of tests needed for conventional testing. but not all. e. Theorem 8 is 9.SSn is a multipleRule 1 given in Section II. then c(R) = 2i the intersection of Nl.-.. Each Fj derence of u. sequence 1 0 11 points of N when a single fault f is present in N. In addition to e -tests. c (RO) has the maximum pos(NAND) gate G. We now tion in all cases. pears that such tests are far too long to be of practical 3) s1s2S3 = enuen-I and Sr = en-li value.Nk denote the subnetworks of N that feed the 1 1 with TC c(R) = 1. ai-. fined in Theorems 1 and 3 have c (R) = 1.. the TC tests deISil fault TC location test for Gn of length 2n+1 . k test points in question. It can be 2) No occurrence of ei is immediately preceded or shown that if 171 = m. Finally.. In general. and ai-i = 0 otherwise.n define Si = ueiuei. points are used..Nk. while for the TC sidered are those comprising s-a-1 input lines to the tests in Theorems 2 and 7.. S must contain at least one occur. i=l tected or distinguished by TC testing.. If &-i is present.uei.2. Test points can be selected Proof: Let fi = "input line i of Gn s-a-i" which is systematically using a standard signal-tracing approach. Theorem 7: For i = 1. for each distinct multiple fault Fj on the input lines of Gn. where. can be distinguished by S*.. Let If fn is present the observed response is R = 0 0 1 1 Nl. For example. alternate members of TO n/2 + 2 which is less than 4(n2/8 + 1).. 5) The fixed test sequences frequently used in comTC test for Gn.. unless multiple test length is less than twice the optimum value. DISCUSSION guishable single faults result in different values of c(R) The main conclusions that can be drawn from the and so are distinguished by S*. The probtests and u-tests for Gn constructed as follows..2. cuit is basically a sequential process.. can be used to construct efficient TC tests. IS*] is less than 4 times the length of an optimal and T1. by Corollary 4. The length r of S* is previous sections are as follows. it apfollowed by ei for 1 < i < n.. + 1. so thatc(R*) = 2. where Si is an alternating sequence of u's and ei's and The results presented here illustrate the utility of = 2i. c(R) = 2n . This is analogous to the approach used for generating Theorem 6: Let S* = S1S2-*-Sr be a sequence of r e. all n + 1 TC distinVI. = 1 if xi s-a-1 is a fault in Fj. Let Fj be such a fault involving input sible value. n-1 1) Most.N2. Then a possible To illustrate Theorem 6.g. The fault f must be located in If any fJ where 1 < i < n . ISI < m22m2+1.. whereas the lower bound on s (6) given by ation methods forms a convenient source of test patSj terns for the construction of TC tests.x If S* is applied to Gn with Fj present. - .. Corollary 4: s(n) > n2/8 + 1...2 is present. . hence all faults in Gn * quired lower bound on s(n). Let Ro denote the correct response Suppose incorrect TC's are observed at k distinct test 1 1 to S*.--.there is a distinct (binary) number rF. = e6ue5e4e3e2ele5e4e3e2e5e4e3e5e4e5. The generation of TC tests for a combinational cirlines xb. The sequence S* = S1S2. 6) A TC test must be extremely long in order to propresent a procedure for constructing such a test whose vide significant fault location data. a single-fault causing the output of Gn to be s-a-O/1 changes c(R) to 0. detected by ei only. faults that can be detected or L distinguished by conventional testing can also be deLi+2=n(n-1)/2+2. lem of finding a TC location test S for an arbitrary com1) S* contains one copy of u and en and i copies of binational circuit using a given location test set T is ineach ei for 1 < i < n -1. The length of S* in Theorem 6 is n2/2 4) Very simple rules.2. Hence. Adding 1 to (2) to account for u yields the recreases c (Ro) by a unique amount. S6 3) A test set T derived using conventional test gener= 17. Hence. teresting from a theoretical point of view.HAYES: TC TESTING OF COMBINATIONAL LOGIC CIRCUITS 619 4 Now Dj can be represented by the n-bit binary number rFj = an-lan_-2"aO. where n > 3.x2.-. 2) Combinational networks can be TC tested for the = 6.

the Switchthe longest sequence consisting of all l's or all O's in a of Illinois. implying the possibility of many faulty machines with the same transition John P. Feb. 1975. the choices remaining are clearly indicated." IEEE Trans. pp. He can be as vague or as specific as he wants in imposing these constraints. New York: McGraw-Hill. The author is with the Electronics Laboratory. INTRODUCTION FAULT test generation is a complicated process. state distinguishing sequences and homing sequences that aid in identifying the behavior of the circuit being tested. If several different tests will suffice. JUNE 1976 some similarities with conventional test generation for REFERENCES sequential circuits. since 0 < c(R) < m . logic networks. Timesharing System Design Concepts. C-21. switching functions. R.. and some test patterns Dec. cf. 1944. 6. all in electrical engineering. puter architecture. r(R) is very easy to compute. Elspas and R. revised December 10. The Netherlands.E. Aug. the order in which the [1] J. A set of logic tables is then used to automatically propagate the effects of these constraints throughout the network. vol. where he worked in the area of fault diagnosisUniversity of digital response sequence R. Let S be a TC test for a sequential [3] B. usually contain many different subsequences such as [4] R. Metze. Ro must 13. the necessary values of the elements in the network become much more precisely (if not completely) defined. Like search Group at the Shell Benelux Computing Centre. bridge. 1496-1506. vol. 1971. fault test generation. in 1967 and 1970. . and a technique for encoding test results. Hayes. Since 1972 he has been Assistant Professor of 1 and 1 < r(R) < m. a widely used tech. As various logical decisions are made. c-25. AKERS..g| | l< Ph.IEEE TRANSACTIONS ON COMPUTERS. Royal Dutch/ Hague. From 1970 to 1972 he was a member of the Operations Rer(R) for R. Decisions that seem straightforward when made suddenly result in logical inconsistencies several steps Company. C-20.. As a result of this logic propaggtion. degrees from the University of Illinois. From 1965 to 1967 he was with the Digital There are some similar coding schemes which may also Computer Laboratory. in 1965 and the M. 1970. and comclude switching theory and logic design. 1975. "A new representation for faults in The design of TC tests for sequential circuits appears combinational digital circuits. ing that is easily implemented in a tester and results in Urbana. [2] D. One Fmust continually make decisions about how the elements of a network behave not only when a fault is present but also when it is absent. tests are applied is important.D. For example. propagation through the tables automatically results in a logical inconsistency. cf. His current automation. ECmachine M whose fault-free response is Ro. For example. Comput. He received the B. It is a type of cod. respectively.. 1-4. Comput.ware development. Transition counting is also related Electrical Engineering and Computer Science at the University of research interests into the concept of the check sum. University of Illinois. A Logic System for Fault Test Generation SHELDON B. 1972. the definition of run measure in [3]. degree from the National University The generation of transition counts can be viewed as of Ireland.Southern California. Syracuse. Ireland. 1964. Several examples are included. stuck-at faults. on March 3. Hayes (S'67-M'70) was born in Newcount as M. Schertz and G. by finding the length of ing Systems Group -at the Coordinated Science Laboratory. vol. where he was involved c(R). a logarithmic compression of the test response data.Short. we can determine a "run count" systems. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. Watson. their effects must not only be propagated forward in the network but often backward as Manuscript received July 9. to be quite difficult. "A NAND model for fault diagnosis in combinational logic networks. Index Terms-Fault diagnosis. may be repeated.." IEEE Trans. be useful for testing logic circuits. Dublin. The tables also indicate whether or not the generated test (which may include a number of unspecified values) is sufficient to detect the given fault. NY 13201. logic systems. design nique for detecting errors in data tables [4]. 858-866." IEEE Trans. In 1967 he joined ther investigation. Los Angeles. General Electric well. IEEE Abstract-This paper describes a logic system specifically designed for fault test generation. This structural variety in Ro tends to make c(Ro) take middle-of-the range values. The system is sufficiently general to permit its incorporation into almost any of the many fault test generation procedures. In the case of a redundant lead (untestable fault).S. pp. Comput. The mathematical programming techniques and softin the application of can have m = IRI distinct values. VOL. W. NO. Rule 1. pp. JR. and which merit furwhere he participated in the design of the IIliac 3 computer. I. "A bound on the run measure of A. Both c(R) and r(R) Shell Company. P. FELLOW. Electron.