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Allen and Holberg, CMOS Analog Circuit Design Bobrow, Elementary Linear Circuit Analysis, 2nd Edition Bobrow, Fundamentals of Electrical Engineering, 2nd Edition Burns and Roberts, An Introduction to Mixed-Signal IC Test and Measurement Campbell, The Scienceand Engineering of Microelectronic Fabrication Chen, Analog & Digital Control SystemDesign Chen, Digital Signal Processing Chen, Linear SystemTheory and Design, 3rd Edition Chen, Systemand Signal Analysis, 2nd Edition DeCarlo and Lin, Linear Circuit Analysis, 2nd Edition Dimitrijev, Understanding SemiconductorDevices Fortney, Principles of Electronics: Analog & Digital Franco, Electric Circuits Fundamentals Granzow, Digital Transmission Lines Guru and Hiziroglu, Electric Machinery and Transformers, 3rd Edition Hoole and Hoole, A Modern Short Course in Engineering Electromagnetics Jones,Introduction to Optical Fiber Communication Systems Krein, Elements of Power Electronics Kuo, Digital Control Systems,3rd Edition Lathi, Modern Digital and Analog Communications Systems,3rd Edition Martin, Digital Integrated Circuit Design McGillem and Cooper, Continuous and Discrete Signal and SystemAnalysis, 3rd Edition Miner, Lines and Electromagnetic Fields for Engineers Roberts and Sedra, SPICE, 2nd Edition Roulston, An Introduction to the Physics of SemiconductorDevices Sadiku, Elements of Electromagnetics, 3rd Edition Santina, Stubberud, and Hostetter, Digital Control SystemDesign, 2nd Edition Sarma,Introduction to Electrical Engineering Schaumannand Van Valkenburg, Design of Analog Filters Schwarz, Electromagneticsfor Engineers Schwarz and Oldham, Electrical Engineering: An Introduction, 2nd Edition Sedraand Smith, Microelectronic Circuits, 4th Edition Stefani, Savant, Shahian, and Hostetter, Design of Feedback Control Systems,3rd Edition Van Valkenburg, Analog Filter Design Warner and Grung, SemiconductorDevice Electronics Wolovich, Automatic Control Systems Y ariv. Ootical Electronics in Modern Communications, 5th Edition

An Introduction to Mixed -Signal I C Test and Measurement

Mark Burns
TexasInstruments, Incorporated

Gordon W. Roberts
McGill University

New York Oxford OXFORD UNIVERSITY PRESS 2001

Oxford University Press Oxford New York Athens Auckland Bangkok Bogota BuenosAires Calcutta CapeTown Chennai Oar es Salaam Delhi Florence Hong Kong Istanbul Karachi Kuala Lumpur Madrid Melbourne Mexico City Mumbai Nairobi Paris SaoPaulo Shanghai Singapore Taipei Tokyo Toronto Warsaw
and associated companies in Berlin !badan Copyright @ 2001 by Texas Instruments, blcorporated

Published by Oxford University Press, Inc. 198 Madison Avenue, New York, New York, 10016 http://www.oup-usa.org Oxford is a registered trademark of Oxford University Press All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior permission of Oxford University Press.

Library of CongressCataloging-in-Publication Data

Bums, Mark, 1962-

An introductionto mixed-signal IC test and measurement Mark Bums, GordonRoberts I

p.

cm.

- (Oxford series electrical computer in and engineering)
I. Roberts, Gordon

Includes bibliographical references and index. ISBN 0-19-514016-8 I. Integrated circuits-Testing. 2. Mixed signal circuits-Testing. W., 1959- II. Title. III. Series TK7874 .B825 2000

621.38IS-dc2I 00-042770

Printing number: 9 8 7 6 5 4 3 Printed in the United States of America on acid-free paper

PREFACE xvii

1.1 MIXED-SIGNAL CIRCUITS 1 1.1.1 Analog,Digital, or Mixed-Signal? 1 1.1.2 CommonTypesof AnalogandMixed-SignalCircuits 1.1.3 Applicationsof Mixed-Signal Circuits 3 1.2 WHY TEST MIXED-SIGNAL DEVICES? 5 1.2.1 The CMOSFabrication Process 5 1.2.2 Real-WorldCircuits 5 1.2.3 What Is a TestEngineer? 8 1.3 POST-SILICON PRODUCTION FLOW 10 1.3.1 TestandPackaging 10 1.3.2 Characterization versus Production Testing 11 1.4 TEST AND DIAGNOSTIC EQUIPMENT 11 1.4.1 Automated TestEquipment 11 1.4.2 WaferProbers 13 1.4.3 Handlers 13 1.4.4 E-BeamProbers 14 1.4.5 Focused BeamEquipment 15 Ion 1.4.6 Forced-Temperature Systems 15 1.5 NEW PRODUCT DEVELOPMENT 16 1.5.1 Concurrent Engineering 16 1.6 MIXED-SIGNAL TESTING CHALLENGES 17 1.6.1 Time to Market 18 1.6.2 Accuracy,Repeatability, Correlation 18 and 1.6.3 Electromechanical FixturingChallenges 18 1.6.4 Economics Production of Testing 19

Chapter 2: The Test SpecificationProcess
2.1 DEVICE DATA SHEETS 23 2.1.1 Purpose a DataSheet 23 of 2.1.2 Structure a DataSheet 24 of 2.1.3 ElectricalCharacteristics 27 2.2 GENERATING THE TEST PLAN 31 2.2.1 To Planor Not to Plan 31
v

vi

Contents

2.2.2 Structure a TestPlan 35 of 2.2.3 DesignSpecifications versus Production TestSpecifications 36 2.2.4 Converting DataSheet the into a TestPlan 37 2.3 COMPONENTS OF A TEST PROGRAM 38 2.3.1 TestProgram Structure 38 2.3.2 TestCodeandDigital Patterns 38 2.3.3 Binning 40 2.3.4 Test Sequence Control 40 2.3.5 WaveformCalculations OtherInitializations 41 and 2.3.6 Focused Calibrations DIB Checkers 41 and 2.3.7 Characterization Code 42 2.3.8 SimulationCode 42 2.3.9 "Debuggability" 42

2.4 SUMMARY 43

Chapter 3: DC and Parametric Measurements
3.1 CONTINUITY 45 3.1.1 Purpose ContinuityTesting 45 of 3.1.2 ContinuityTestTechnique 46 3.1.3 Serialversus ParallelContinuityTesting 48 3.2 LEAKAGE CURRENTS 50 3.2.1 Purpose Leakage of Testing 50 3.2.2 Leakage TestTechnique 50 3.2.3 Serialversus ParallelLeakage Testing 51 3.3 POWER SUPPLY CURRENTS 51 3.3.1 hnportance SupplyCurrentTests 51 of 3.3.2 TestTechniques 51 3.4 DC REFERENCESAND REGULATORS 52 3.4.1 VoltageRegulators 52 3.4.2 VoltageReferences 55 3.4.3 Trirnmable References 55 3.5 IMPEDANCE MEASUREMENTS 56 3.5.1 Input hnpedance 56 3.5.2 Outputhnpedance 58 3.5.3 Differentialhnpedance Measurements 59 3.6 DC OFFSET MEASUREMENTS 60 3.6.1 VMID AnalogGround 60 and 3.6.2 DC TransferCharacteristics (GainandOffset) 60 3.6.3 OutputOffsetVoltage(Vo) 61 3.6.4 Single-Ended, Differential,andCommon-Mode Offsets 62 3.6.5 Input OffsetVoltage(Vos) 64 3.7 DC GAIN MEASUREMENTS 65 3.7.1 Closed-Loop Gain 65 3.7.2 Open-Loop Gain 68 3.8 DC POWER SUPPLYREJECTION RATIO 71 3.8.1 DC PowerSupplySensitivity 71 3.8.2 DC PowerSupplyRejection Ratio 72

Contents

vii

3.9 DC COMMON-MODE REJECTION RATIO 72 3.9.1 CMRRofOpAmps 72 3.9.2 CMRR of DifferentialGainStages 75 3.10 COMPARATOR DC TESTS 77 3.10.1 Input OffsetVoltage 77 3.10.2 Thresho1dVoltage 78 3.10.3 Hysteresis 78 3.11 VOLTAGE SEARCH TECHNIQUES 79 3.11.1 Binary Searches versusStepSearches 79 3.11.2 Linear Searches 80 3.12 DC TESTS FOR DIGJTAL CIRCUITS 82 3.12.1 4H/4L 82 3.12.2 VldV/L 82 3.12.3 VaN/VoL 82 3.12.4 IoH/loL 82 3.12.5 IoSH IosLShortCircuit Current 82 and 3.13 SUMMARY 83

Chapter 4: MeasurementAccuracy
4.1 TERMINOLOGY 87 4.1.1 AccuracyandPrecision 87 4.1.2 Systematic Errors 88 4.1.3 Random Errors 88 4.1.4 Resolution (Quantization Error) 88 4.1.5 Repeatability 89 4.1.6 Stability 90 4.1.7 Correlation 91 4.1.8 Reproducibility 92 4.2 CALIBRATIONS AND CHECKERS 93 4.2.1 Traceabilityto Standards 93 4.2.2 Hardware Calibration 93 4.2.3 Software Calibration 93 4.2.4 System Calibrations Checkers 96 and 4.2.5 Focused Instrument Calibrations 97 4.2.6 Focused DIB Circuit Calibrations 101 4.2.7 DIB Checkers 102 4.2.8 TesterSpecifications 103 4.3 DEALING WITH MEASUREMENT ERROR 106 4.3.1 Filtering 106 4.3.2 Averaging 111 4.3.3 Guardbanding 113 4.4 BASIC DATA ANALYSIS 114 4.4.1 Datalogs 114 4.4.2 Histograms 115 4.4.3 Noise,TestTime,andYield 118 4.5 SUMMARY 120

viii

Contents

Chapter 5: Tester Hardware
5.1 MIXED-SIGNAL TESTER OVERVIEW 123 5.1.1 General-Purpose Testers versus Focused BenchEquipment 123 5.1.2 GenericTesterArchitecture 123 5.2 DC RESOURCES 125 5.2.1 General-Purpose Mu1timeters 125 5.2.2 General-Purpose Voltage/Current Sources 127 5.2.3 Precision VoltageReferences UserSupplies 128 and 5.2.4 CalibrationSource 128 5.2.5 RelayMatrices 128 5.2.6 RelayControlLines 130 5.3 DIGITAL SUBSYSTEM 131 5.3.1 Digital Vectors 131 5.3.2 Digital Signals 131 5.3.3 Source Memory 132 5.3.4 Capture Memory 132 5.3.5 Pin CardElectronics 134 5.3.6 Timing andFormatting Electronics 136 5.4 AC SOURCEAND MEASUREMENT 139 5.4.1 AC Continuous WaveSource AC Meter 139 and 5.4.2 Arbitrary WaveformGenerators 139 5.4.3 WaveformDigitizers 140 5.4.4 ClockingandSynchronization 141 5.5 TIME MEASUREMENT SYSTEM 141 5.5.1 Time Measurements 141 5.5.2 Time Measurement Interconnects 142 5.6 COMPUTING HARDWARE 143 5.6.1 UserComputer 143 5.6.2 TesterComputer 144 5.6.3 Array Processors DistributedDigital SignalProcessors 144 and 5.6.4 NetworkConnectivity 144 5.7 SUMMARY 144

Chapter 6: Sampling Theory
6.1 ANALOG MEASUREMENTS USING DSP 147 6.1.1 Traditionalversus DSP-Based Testingof AC Parameters 147 6.2 SAMPLING AND RECONSTRUCTION 148 6.2.1 Useof Sampling Reconstruction Mixed-Signal and in Testing 148 6.2.2 Sampling: Continuous-Time Discrete-Time and Representation 149 6.2.3 Reconstruction 152 6.2.4 The Sampling Theorem Aliasing 159 and 6.2.5 Quantization Effects 161 6.2.6 Sampling Jitter 166 6.3 REPETITIVE SAMPLE SETS 170 6.3.1 Finite andInfmite Sample Sets 170 6.3.2 Coherent Signals Noncoherent and Signals 171

Contents

ix

6.3.3 Peak-to-RMS Controlin Coherent Multitones 173 6.3.4 Spectral Selection 175 Bin 6.4 SYNCHRONIZATION OF SAMPLING SYSTEMS 179 6.4.1 Simultaneous Testingof Multiple Sampling Systems 179 6.4.2 ATE Clock Sources 181 6.4.3 The Challenge Synchronization 183 of 6.S SUMMARY 184

Chapter 7: DSP-Based Testing
7.1 ADVANTAGES OF DSP-BASEDTESnNG 189 7.1.1 ReducedTestTime 189 7.1.2 Separation SignalComponents 189 of 7.1.3 AdvancedSignalManipulations 190 7.2 DIGITAL SIGNAL PROCESSING 190 7.2.1 DSPandArray Processing 190 7.2.2 FourierAnalysisof PeriodicSignals 191 7.2.3 The Trigonometric FourierSeries 192 7.2.4 TheDiscrete-Time FourierSeries 195 7.2.5 Complete Frequency Spectrum 205 7.2.6 Time andFrequency Denormalization 210 7.2.7 ComplexFormof the DTFS 211 7.3 DISCRETE-TIME TRANSFORMS 213 7.3.1 The DiscreteFourierTransform 213 7.3.2 TheFastFourierTransform 216 7.3.3 Interpreting FFT Output 218 the 7.4 THE INVERSE FFT 230 7.4.1 Equivalence Time- andFrequency-Domain of Information 230 7.4.2 Parseval's Theorem 232 7.4.3 Applicationsof the Inverse FFT 233 7.4.4 Frequency-Domain Filtering 234 7.4.5 NoiseWeighting 239 7.5 SUMMARY 240 APPENDIXA.7.1 241

Chapter8: Analog Channel Testing
8.1 OVERVIEW 249 8.1.1 Typesof AnalogChannels 249 8.1.2 Typesof AC Parametric Tests 250 8.1.3 Reviewof LogarithmicOperations 250 8.2 GAIN AND LEVEL TESTS 251 8.2.1 AbsoluteVoltageLevels 251 8.2.2 AbsoluteGainandGainError 256 8.2.3 GainTrackingError 258 8.2.4 PGA GainTests 260 8.2.5 Frequency Response 265

~

x

Contents

8.3 PHASE TESTS 273 8.3.1 Phase Response 273 8.3.2 GroupDelay andGroupDelayDistortion 278 8.4 DISTORTION TESTS 280 8.4.1 Signalto HannonicDistortion 280 8.4.2 InteTnlodulation Distortion 283 8.5 SIGNAL REJECTION TESTS 284 8.5.1 Common-Mode Rejection Ratio 284 8.5.2 PowerSupplyRejection PowerSupplyRejection and Ratio 287 8.5.3 Channel-to-Channel Crosstalk 289 8.5.4 Clock andDataFeedthrough 293 8.6 NOISE TESTS 293 8.6.1 Noise 293 8.6.2 Idle Channel Noise 294 8.6.3 Signalto Noise,Signalto NoiseandDistortion 296 8.6.4 Spurious FreeDynamicRange 298 8.6.5 WeightingFilters 300 8.7 SIMULA nON OF ANALOG CHANNEL TESTS 304 8.7.1 MATLABModel of anAnalogChannel 304 8.8 SUMMARY 308

Chapter 9: SampledChannel Testing
9.1 OVERVIEW 315 9.1.1 WhatAreSampledChannels? 315 9.1.2 Examples Sampled of Channels 315 9.1.3 Typesof Sampled Channels 318 9.2 SAMPLING CONSmERATIONS 320 9.2.1 DUT Sampling RateConstraints 320 9.2.2 Digital SignalSource Capture 321 and 9.2.3 Simultaneous DAC andADC Channel Testing 326 9.2.4 Mismatched Fundamental Frequencies 330 9.2.5 Undersampling 333 9.2.6 Reconstruction Effectsin A WGs,DACs, andOtherSampled-Data Circuits 335 9.3 ENCODING AND DECODING 338 9.3.1 SignalCreation Analysis 338 and 9.3.2 DataFormats 339 9.3.3 Intrinsic Errors 344 9.4 SAMPLED CHANNEL TESTS 350 9.4.1 Similarity to AnalogChannel Tests 350 9.4.2 AbsoluteLevel,AbsoluteGain,GainError,andGainTracking 351 9.4.3 Frequency Response 356 9.4.4 Phase Response (AbsolutePhase Shift) 359 9.4.5 GroupDelayandGroupDelayDistortion 360 9.4.6 Signalto HarmonicDistortion,Intermodulation Distortion 360 9.4.7 Crosstalk 361 9.4.8 CMRR 362

Contents

xi

9.4.9 PSRandPSRR 362 9.4.10 Signal-to-Noise RatioandENOB 363 9.4.11 Idle Channel Noise 363 9.S SUMMARY 364

Chapter 10: FocusedCalibrations
10.1 OVERVIEW 369 10.1.1Traceabilityto NationalStandards 369 10.1.2Why Are Focused Calibrations Needed? 370 10.1.3Typesof Focused Calibrations 372 10.1.4Mechanics Focused of Calibration 372 10.1.5Program Structure 375 10.2 DC CALIBRAllONS 376 10.2.1DC OffsetCalibration 376 10.2.2DC Gain andOffsetCalibrations 378 10.2.3Cascading OffsetandGainCalibrations 380 DC 10.3 AC AMPLITUDE CALIBRATIONS 382 10.3.1CalibratingAWGs andDigitizers 382 10.3.2Low-LevelAWG andDigitizer AmplitudeCalibrations 389 10.3.3AmplitudeCalibrations ADC andDAC Tests 390 for 10.4 OTHER AC CALIBRATIONS 392 10.4.1Phase Shifts 392 10.4.2Digitizer andAWG Synchronization 396 10.4.3DAC andADC Phase Shifts 396 10.4.4DistortionTests 396 10.4.5NoiseTests 397 10.5 ERROR CANCELLATION TECHNIQUES 397 10.5.1Avoiding AbsoluteCalibration 397 10.5.2GainandPhase Matching 397 10.5.3DifferentialGainandDifferentialPhase 399 10.6 SUMMARY 400

Chapter 11: DAC Testing
11.1 BASICS OF CONVERTER TESTING 403 11.1.1 IntrinsicParameters versus Transmission Parameters 403 11.1.2Comparison ofDACs andADCs 404 11.1.3DACFai1ureMechanisrns405 11.2 BASIC DC TESTS 405 11.2.1Code-Specific Parameters 405 11.2.2Full-ScaleRange 406 11.2.3DC Gain,GainError,Offset,andOffsetError 406 11.2.4 LSB StepSize 409 11.2.5 DCPSS 410 11.3 TRANSFER CURVE TESTS 410 11.3.1AbsoluteError 410 11.3.2Monotonicity 412

xii

Contents

11.3.3 DifferentialNon1inearity 412 11.3.4 Integra1Nonlinearity 416 11.3.5PartialTransferCurves 419 11.3.6Major CarrierTesting 420 11.3.7 OtherSelected-Code Techniques 423 11.4 DYNAMIC DAC TESTS 424 11.4.1 Conversion Time (SettlingTime) 424 11.4.2 Overshoot Undershoot 426 and 11.4.3 RiseTime andFall Time 426 11.4.4 DAC-to-DAC Skew 426 11.4.5 Glitch Energy(Glitch Impulse) 427 11.4.6Clock andDataFeedthrough 428 11.5 DAC ARCHITECTURES 428 11.5.1ResistiveDividerDACs 428 11.5.2Binary-WeightedDACs 430 11.5.3PWMDACs 431 11.5.4 Sigma-Delta DACs 433 11.5.5 Companded DACs 434 11.5.6 Hybrid DAC Architectures 435 11.6 TESTS FOR COMMON DAC APPLICAnONS 11.6.1 DC References 435 11.6.2Audio Reconstruction 436 11.6.3DataModulation 436 11.6.4Video SignalGenerators 436 11.7 SUMMARY 437
APPENDIXA.ll.l 437

435

Chapter 12: ADC Testing
12.1 ADC TESTING VERSUSDAC TESTING 447 12.1.1 ComparisonofDACsandADCs 447 12.1.2 Statistical Behavior ADCs 448 of 12.2 ADC CODE EDGE MEASUREMENTS 454 12.2.1 EdgeCodeTestingversus CenterCodeTesting 454 12.2.2 StepSearch Binary Search and Methods 455 12.2.3 ServoMethod 455 12.2.4Linear RampHistogram Method 456 12.2.5Conversion from Histograms CodeEdgeTransfer to Curves 457 12.2.6AccuracyLimitationsof Histogram Testing 460 12.2.7Rising Ramps versus FallingRamps 461 12.2.8 Sinusoidal Histogram Method 462 12.3 DC TESTS AND TRANSFERCURVE TESTS 467 12.3.1DC GainandOffset 467 12.3.2 INL andDNL 468 12.3.3MonotonicityandMissingCodes 469 12.4 DYNAMIC ADC TESTS 470 12.4.1Conversion Time,Recovery Time, andSampling Frequency 470 12.4.2ApertureJitter 472 12.4.3 Sparkling 472

6.6.3.7 SUMMARY 480 13: DIB Design 13.8Transformers PowerSplitters 528 and .6.5Resistors 525 13.6.5.6Capacitors 526 13.3FlashADCs 475 12.6.5.4GroundLoops 518 13.5PDM (Sigma-Delta) ADCs 477 12.5.6.2.2Audio Digitization 479 12.1.4.3Multilayer PCBs 488 13.5 GROUNDING AND POWER DISTRIBUTION 514 13.2.3Parasitic LumpedElements 514 13.3 DIB TRACES. PogoPins.2.5Shielding 502 13.1.6.3.2 PRINTED CIRCillT BOARDS 486 13.4.5.4 TRANSMISSION LINES 504 13.3.5 ADC ARCmTECTURES 473 12.2Integrating ADCs (Dual-Slope Single-Slope) 474 and 12.6.4SocketPins 524 13.4PCBMaterials 489 13.2PowerDistribution 516 13.5.6.6Driven Guards 503 13.1 DIB BASICS 483 13.2TraceResistance 490 13.4TraceCapacitance 496 13.Contents xiii 12.4Semiflash ADCs 476 12.5.6.6. AND GUARDS 490 13.6 DIB COMPONENTS 519 13.5.1TraceParasitics 490 13.1Prototype DIBs versus PCBDffis 486 13.andSocketPins 520 13.1DC Measurements479 12.3.5.5.6.1.3DataTransmission 479 12.2.2ContactPads.2Transmission Line Termination 508 13.3Importance GoodDIB Design 486 of 13.3PowerandGroundPlanes 517 13.1DUT Sockets Contactor and Assemblies 519 13.1Lumped-andDistributed-Element Models 504 13.4Video Digitization 480 12.3Electromechanical Relays 521 13.1Purpose a DeviceInterface of Board 483 13.3.1Successive Approximation Architectures 473 12. SHIELDS.7Inductors FerriteBeads 528 and 13.1Grounding 514 13.3TraceInductance 491 13.2PCBCAD Tools 487 13.4.6 TESTSFOR COMMON ADC APPLICATIONS 479 12.3.2Dffi Configurations 484 13.

7.3 Diagnostics Characterization 553 and 14.5.7.5 System-Level Diagnostics 555 14.1.4) 569 .5 DIGITAL Dff FOR MIXED-SIGNAL CIRCUITS 565 14.1.4Why ShouldWe UseDff? 551 14.7.5.3.4 DIGITALBIST 562 14.2.8. 1149.8.4.2..1 Lower Costof Test 551 14.4 Easeof TestProgram Development 554 14.3Device-Driven Timing 567 14.1 Pseudorandom BILBO Circuits 562 14.5.2MemoryBIST 563 14.2Digital Resets Presets 566 and 14.6 VMID Reference Adder 535 13.8.8PowerSupplyRippleCircuits 536 13.1 OVERVIEW 549 14.7PoorDIB Component Placement PCBLayout 542 and 13.6Economics ofDff 555 14.2 Crosstalk 541 13.7.1 Local RelayConnections 530 13.1What Is Dff? 549 14.7 Current-toVoltageandVoltage-to-Current Conversions 536 13.2 IEEE Std. 1149.2.7 COMMON DIB CIRCUITS 530 13.6 MIXED-SIGNAL BOUNDARY SCAN AND BIST 569 14.2 Increased FaultCoverage hnprovedProcess and Control 553 14.3.2.7.4.5 Instrumentation Amplifiers 534 13.2 Built-In Self-Test 550 14.3Transmission Line Discontinuities 541 13.4 LengthyPreambles 569 14.3Differences between Digital Dff andAnalogDff 550 14.1 Partitioning 565 14.3MicrocodeBIST 564 14.5.1Mixed-Signal Boundary Scan(IEEE Std.4Resistive Dropsin Circuit Traces 541 13.2 ADV ANT AGES OF Dff 551 14.8 COMMON DIB MISTAKES 540 13.8.5TesterInstrument Parasitics 541 13.2.2RelayMultiplexers 532 13.7.13.6 Oscillations Active Circuits 542 in 13.3Full ScanandPartialScan 559 14.2.1 ScanBasics 556 14.4AnalogBuffers(VoltageFollowers) 533 13.8.7.1PoorPowerSupplyandGroundLayout 540 13.4.3 Selectable Loads 533 13.8.1 543 Chapter 14: Design for Test (Dff) 14.xiv Contents 13.8.9 SUMMARY 543 APPENDIX A.1 Standard Access Test Port andBoundary Scan 557 14.6.3.3 DIGITAL SCAN 556 14.1.1.7.

and Bypass Modes 575 14.4 Separation of Analog and Digital Blocks 577 14.2.5 Guardbanding and GaussianStatistics 618 15.9 DAC and ADC Converters 584 14.9.8.7 On-Chip Sampling Circuits 581 14.7.2 DATA VISUALIZATION TOOLS 598 15.7.6 Effects of MeasurementVariability on Test Yield 620 15.1 Common Concepts 573 14.2.7.3 The StandardGaussianCumulative Distribution Function <I»(z) 611 15.7 AD HOC MIXED-SIGNAL Dff 573 14.4 Non-Gaussian Distributions 615 15.11 Physical Test Pads 585 14.7.Contents 14.3 STATISTICAL ANALYSIS 606 15.7.2 Analog and Mixed-Signal IDDQ 588 14.1 INTRODUCTION TO DATA ANALYSIS 597 15.7.14.4.2 Six-Sigma Quality 628 .7.5 Histograms 604 15.1.1 589 Chapter 15: Data Analysis 15.4 STATISnCAL PROCESS CONTROL 627 15.6 Precharging Circuits and AC Coupling Shorts 580 14.3.1 Mean (Average) and StandardDeviation (Variance) 606 15.8 PLLTestabilityCircuits 583 14.1 Data1ogs(Data Lists) 598 15.3 Avoiding Overspecification 586 14.1.7.10 Oscillation BIST 585 14.7 Avoidance of Trim Requirements 587 14.3 Wafer Maps 600 15.4.2.8.4 Predictability of Failure Mechanisms 586 14.2 Accessibility of Analog Signals 573 14.9 IDDQ 587 14.6 Reduced Tester PerformanceRequirements 587 14.3.2.2 Visualizing Test Results 597 15.2 Design Margin as Dff 586 14.10 SUMMARY 589 APPENDIX A.1 The Role of Data Analysis in Test and Product Engineering 597 15.3.3.3 Analog Test Buses.2 Probabi1itesand Probability Density Functions 607 15.8.7.9.1 Digital IDDQ 587 14.8.2.8.4 Shrnoo Plots 601 15.3.2 Lot Summaries 599 15.7.6.7.8.1 Goals ofSPC 627 15.8 SUBTLE FORMS OF ANALOG Dff 585 14.7 Effects of Reproducibi1tyand ProcessVariation on Yield 623 15.2 Analog and Mixed-Signal BIST 571 14.8.3.1 Robust Circuits 585 14.5 Loopback Modes 579 14. T -Switches.5 Conversion of Analog Functions to Digital 587 14.3.

3Throughput 645 16.1 TestLanguage Standards 655 16.3.2 The ScientificMethod 649 16.7 ControlCharts 633 15.xvi Contents 15.andCpt 628 15.4.5 SUMMARY 659 ANSWERSTO SELECTED PROBLEMS 663 INDEX 677 .5 TestProgram Structure 652 16.1 CostModels 643 16.1 PROFITABILITY FACTORS 641 16.2 TestSimulation 656 16.1.2.1.4.3 TestingCosts 642 16.4.3.3.1.4 Gauge Repeatability Reproducibility 630 and 15.3 Noncoherent Sampling 658 16.3.4.4.1 Sources Error 649 of 16.4.4 Importance BenchInstrumentation 652 of 16.2 Costof Testversus Costof Tester 643 16.2.2Time to Market 641 16.4 Built-In Self-Test 658 16.4.4.4 EMERGING TRENDS 655 16.4.2 DIRECT TESTING COSTS 643 16.5Defect-Oriented Testing 658 16.2.5ParetoCharts 631 15.3 PracticalDebugging Skills 651 16.4Yield Enhancement642 16.3 Process Capability.4.6 CommonBugsandTechniques Find Them 653 to 16.1.3 DEBUGGING SKILLS 649 16.1What Is Meantby TestEconomics? 641 16.6 Scatter Plots 631 15.Cp.3.3.5 SUMMARY 634 Chapter 16: Test Economics 16.

this book will xvii . etc. It would be unwise to assign such an inadequately trained studentto drive from L. with little or no training on the basics of mixed-signal test and measurement. complex microprocessors are frequently combined with highperformanceanalog and mixed-signal circuits to form so-called "system-on-a-chip" devices. Mixed-signal IC test and measurementhas grown into a highly specialized field of electrical engineering. An example of this is a single chip modem combining a digital signal processor with precision analog-to-digital and digital-to-analog functions on a single silicon die.A. Similarly.books have been devoted to the subject of digital test and testability. the same cannot be said for analog and mixed-signal automated test and measurement. to Pittsburgh without a roadmap and without a working knowledge of trivialities such as stop lights and police sirens. new test engineersoften overlook basic deficiencies in the circuit architecture that prevent the device from being tested thoroughly and economically. though not absolutely necessary. This material is designed to be useful as both a university textbook and as a reference manual for the beginning professional test engineer. Like many specialized technical materials. Training for mixed-signal test engineers has historically started with a sink-or-swim training course covering the use of the test equipment itself. Complex digital circuits are now commonly combined with analog circuits as part of the continuing drive toward higher levels of electronic system integration. a new test engineer is often assigned to develop tests for a complex circuit without training in basic test definitions and common test techniques. It may take one to two years for a mixed-signal test engineer to develop enough knowledge and experienceto develop adequatetest solutions. This book was written in responseto the shortage of basic course material for mixed-signal test and measurement. For example. While many. This equipment-centric approach to training is analogousto teaching a student how to drive by simply explaining the mechanics of the automobile itself (pull this knob.However. The book assumesa solid background in analog and digital circuits as well as a working knowledge of computers and computer programming.Integrated circuits incorporating both digital and analog functions have become increasingly prevalent in the semiconductor industry. Such devices offer the semiconductorcustomer significant savings in manufacturing costs due to the resulting reduction of chip-to-chip interconnections. test engineering is still a relatively unknown profession compared with IC design engineering.). A background in digital signal processing and statistical analysis is also helpful. It has become harder to hire and train new engineers to become skilled mixed-signal test engineers. As a result. The slow learning curve for mixed-signal test engineers is largely due to the shortage of written materials and university-level courses on the subject of mixed-signal testing. push that pedal. The test engineer is also exp~ctedto contribute to the defmition of testability circuits that are incorporated into the design of the device to be tested. Again. there is little fonnal reference material or training on the subject of basic mixed-signal design for test (Dff).

windowing. The generictesterincludesinstruments suchas DC sources. resistiveladder. Chapter 3 introduces basic DC measurementdefinitions. This subject is not necessarily taught in formal ATE tester classes. Chapter 8 shows how basic AC channel tests can be performed economically using DSPbasedtesting. including binary-weighted. digital patterngenerators source capture and with and functionality. which include DACs. and other DSP-basedtesting fundamentals are covered in Chapters6 and 7.standards traceability. Again. yet it is critical in the accuratemeasurementof many DUT performance parameters. Testingof DACs is coveredin Chapter11. which are at the core of many mixed-signal test and measurement techniques. ADCs. Severalkinds of DACs are studied. consisting of combinations of op amps. gain. Test program structure and functionality are also discussed in Chapter 2. PGAs and other continuous-time circuits. Chapter 9 explores many of these same tests as they are applied to sampled channels. Chapter 10 explains how the basic accuracy of ATE test equipment can be extended using specialized software routines. offset. meters.including traditional binary-weighted. basic data analysisis presented in Chapter4. resolution. Traditional measurements INL. Fortunately. This chapter covers only nonsampled channels. DC power supply rejection ratio. and measurement repeatability. In addition. leakage. including continuity. and sigma-delta . Chapter 7 further develops sampling theory concepts and DSP-basedtesting methodologies. with an emphasison their respective weaknesses and common testing methodologies.' DAC sampling theory is applicable to both DAC circuits in the device under test and to the arbitrary waveform generatorsin a mixed-signal tester. severaldifferent kinds of ADCs are studied. analog filters. these two courses are usually required at most universities. A more thoroughtreatment dataanalysisand statisticalanalysisis delayed of until Chapter15. Chapter 6 presents an introduction to both ADC and DAC sampling theory. and many other types of fundamental DC measurements. and sigma-delta architectures. Chapter5 takesa closerlook at the architecture a genericmixed-signal of ATE tester. etc. frequency domain filtering. Hopefully. semi flash.softwarecalibration. The book is divided into 16 chapters. Chapter 1 presents an introduction to the context in which mixed-signal testing is performed and why it is necessary. and absoluteerror are discussed. flash. Chapter 2 examines the process by which test programs are generated. Coherent multi-tone sample sets are also introduced as an introduction to DSP based testing.pulse-widthmodulation(PWM).xviii Preface most likely becomepartially outdated beforepublication. DNL.as well as exposureto elementary probability and statistical concepts.waveform digitizers. from device data sheet to test plan to test code. ADC sampling theory is applicable to both ADC circuits in the device under test and to waveform digitizers in a mixed-signal tester. Chapter 12 builds upon the conceptsin Chapter11 to showhow ADCs are commonlytested. Chapter4 coversthe basicsof absolute accuracy. The prerequisite for this book is a junior-level course in linear continuous-time and discretetime systems. sample and hold (S/H) amplifiers. dual-slope.arbitrary waveformgenerators. FFT fundamentals. it will at leastserveas an amusing historicalrecordof how thingsweredonebackin the twentiethcentury. like Several kinds of DAC architectures are explored.

1149. for allowing him to develop this book as part of his engineering duties for the past three years.Also. on behalf of the test engineering profession. Chapter13 alsoillustratesseveralcommonDill circuits and their usein mixedsignal testing. We also thank Juli Boman (Teradyne. test floor overhead costs. Chapter 16 examines the economics of production testing. Inc. Peter Gordon. used Chapter13 explores~e gray art of mixed-signalDlB design. Finally. There are fewer structured approaches for mixed-signal DfI than for purely digital DfI. Topics of interestinclude component selection. and tester loading. Bob Schwartz. Jay Porter of Texas A&M University.transmissionlines. Dr. Rainer Fink and Dr.). statistical process control (SPC) is explained. test time. Inc. shmoo plots. Datalogs.). A brief review of statistical analysis and Gaussian distributions is presented in Chapter 15.. crosstalk. First. The editorial development help of Karen Shapiro was greatly appreciated. emerging trends that affect test economics and test development time are presented in Chapter 16. We are extremely grateful to the staff at Oxford University Press.) Pramodchandran Variyam (Georgia Techrrexas Instruments. all of Texas Instruments. David VanWinkle. and Geoffrey Zhang (Texas Instruments.4. The economics of test are affected by many factors such as equipment purchaseprice. Mark Bums would like to extend his gratitudeto Del Whittaker. A test engineer's debugging skills heavily impacts time to market. Their early adoptionof this work at their respective universities has helped to shape the book's content and exposeits many weaknesses. Inc. Cajetan Akujuobi of Prairieview A&M University.multisite testing. Justin Ewing (Texas A&M Universityffexas Instruments. as well as some of the industry standards such as IEEE Std. Chapter 14 gives a brief introduction to some of the techniques for analog and mixed-signal design for test. as well as the common of methodologies to probetheir weaknesses. It takes great courage and vision for corporate management to . Finally. Ming Chiang.) and Ted Lundquist (Schlumberger Test Equipment) for providing photographs Chapter 1. Chapter 16 examines the test debugging process to attempt to set down some general guidelines for debugging mixed-signal test programs.who have helped guide us throughthe process of writing an enjoyable book. The weaknesses each design are explained.). The preliminary versions of this complete manuscript were reviewed by a number of students andpracticing test engineers. and time to market. We would like to thank those professionals and students who gave us extensive corrections and feedback to improve this textbook: Steve Lyons (Lucent Technologiesfferadyne. 'Some or all of thesetrends will shapethe future course of mixed-signal test and measurement. The more common ad hoc methods are explained. This chapter also shows how measurement results can be analyzed and viewed using a variety of software tools and display formats. Jim Larson and Gary Moraes (Teradyne. and Brian Evans.power and ground layout.Preface xix architectures. Inc. Inc.1 and 1149. and Dr. we would like to acknowledge the help andconstructive feedback of the publishing editor. for We would also like to extend our sincere appreciation to Dr. Inc. and histograms are discussed. Inc. Simon Ang of the University of Arkansas for their help in developing this textbook. including a discussion of process control metrics such as Cp and Cpt.).shielding. dual-head testing.

he would like to extend his sincere appreciation to all the dedicated staff members and graduate students associated with the Microelectronics and Computer Systems (MACS) Laboratory at McGill University. Canada . for her constant support and encouragementduring this project. Professors Nicholas Rumin !lnd David Lowther. Mark Bums TexasInstruments. Quebec. whose financial and emotional supporthelpedhim throughfour yearsat the Massachusetts Instituteof Technology. For this. Mark ~on also extendshis appreciationto his parents. Professor Adel Sedra of the University of Toronto. Roberts McGill University Montreal. gave him the peace of mind neededto work on this book with Mark. Gordon Roberts would like to express his sincere gratitude to his best friend and partner. most important. He would also like to note the enormous contribution made by his friend. past graduatethesis supervisor and present-day mentor. Professor Sedra taught him more about the world of microelectronics than anyone else. deserve special mention for initially believing in this project and allowing it to take root and flourish at McGill University. past and present chairmen of the department of electrical and computer engineering. Her dedication to their two children.xx Preface expendresources the productionof a work that may ultimatelyhelp the competition. Eileen O'Reilly. he will be forever in debt.Texas Gordon W. On behalf of Gordon Roberts. Finally. and.Burt and Shirley Burns. Inc. for his invaluable advice over the past two decades. Brigid Maureen and Sean Gordon. Dallas.

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This is why they are not always considered to be mixed-signal circuits at all. Fortunately. Conversely. PGAs and analog switches involve a trivial interaction between the analog and digital circuits. since there are a wide variety of ADC and DAC designs and a wide variety of techniquesto test them. since they fonn the interface between the physical world and the world of digital logic. device is simply a combinationof digital logic and separate the analogcircuitry coexistingon the samedie or circuit board. comparators.2 An Introductionto Mixed-Signal TestandMeasurement IC circuits are thosethat involve somesort of nontrivial interactionbetweendigital signalsand analogsignals. One of the very simplest circuits that can be considered to fall into the mixed-signal realm is the CMOS analog switch. and other specialized functions such as Hall effect transistors. an ADC which is only required to sample once per second may employ a dual slope conversion . Thus. since testing of purely digital circuits has been extensively documentedelsewhere!-4 1. voltage regulators. The most common circuits that can truly be considered mixed-signal devices are analog to digital converters (AIDs or ADCs) and digital to analog converters (D/As or DACs). a DAC is a circuit that converts digital samples into analog voltages (or currents). OtheIWise. The line betweenmixed-signal circuitsandanalogor digital circuitsis blurry if onewantsto be pedantic. forming more complex circuits such as analog multiplexers and demultiplexers and analog switch matrices. the resistanceof a CMOS transistor is varied between high impedance and low impedanceunder control of a digital signal. comparators. analog switches. While the abbreviations AID and ADC are used interchangeably in the electronics industry. the tenn DAC will be used throughout the book rather than D/A. and mixed-signal are completely irrelevant in the context of mixed-signal test and measurement. ADCs and DACs are the most common mixed-signal components in complex mixed-signal designs. while the on-resistancemay be 100 Q or less. the blurry lines between digital. These circuits therefore benefit from the use ofPGAs.1. including many of the borderline examples. analog mixers. The off-resistance may be as high as one megaohm or more. This book encompassesthe testing of both analog and mixed-signal circuits. Comprehensive testing of DACs and ADCs is an expansive topic. An ADC is a circuit that samplesa continuous analog signal at specific points in time and converts the sampled voltages (or currents) into a digital representation. the testing of op amps. For example. analog. Operating as a digitally adjusted volume control.2 Common Types of Analog and Mixed-Signal Circuits Analog circuits (also known as linear circuits) include operational amplifiers. Another simple type of mixed-signal circuit is the programmable gain amplifier (PGA). Many circuits require a consistent signal level to achieve optimum performance. In this circuit. the PGA is set to high gains for low-amplitude input signals and low gains for high-amplitude input signals. Most complex mixed-signal devices include at least some stand-aloneanalog circuits that do not interact with digital logic at all. The PGA is often used in the front end of a mixed-signal circuit to allow a wider range of input signal amplitudes. Digital testing will only be covered superficially. Similarly. voltage references. and other purely analog circuits must be included in a comprehensive study of mixed-signal testing. Each digital representation is called a sample. Banks of analog switches can be interconnected in a v'ariety of configurations. this book will always use the tenn ADC for consistency. The next circuit following a PGA is thus provided with a consistent signal level. active or passive filters.

As an example of a mixed-signal application. Figure 1. and multimedia audio and video products all employ complex mixed-signal circuits.the PLL is combinedwith a digital divider to data constructa frequencymultiplier. we shall examine its operation in some detail. it is also important to perform system-level tests. The volume of the voice signal from the microphone be adjusted can automatically using a programmable gain amplifier (PGA) controlledby eitherthe DSP or the . filters. 50 MHz. say. While it is important to test the individual circuits making up a complex mixed-signal device.1. the Anothercommonmixed-signal circuit is the phaselockedloop. testing of thesetwo convertertypes is totally different. In the former case. depending the natureof the PLL designand its intended on use. They also convert the very high-frequency incoming signals from the basestation into lower-frequency signals that can be processedby the base-bandinterface. The mixers convert the relatively low-frequency signals of the base-bandinterface to extremely high frequencies that can be transmitted from the cellular telephone'sradio antenna. Again. The control microprocessor selectsthe incoming and outgoing transmission frequencies by sending control signals to the frequency synthesizer. whereas a IOO-MHzvideo ADC may have to employ a much faster flash conversion architecture. let us consider a common consumer product using many mixed-signal subcircuits. Similar differences the existbetween varioustypesofDACs. End-equipment applications such as cellular telephones. and base-band interfaceperfonn mostof the complexoperations. Overview of Mixed-Signal Testing 3 architecture. and mixed-signal circuits working together in a complex fashion. The weaknesses these two architecturesare totally different. ADCs. which control the mixers in the radio frequency (RF) section of the cellular telephone.2 shows a simplified block diagram of a complex mixed-signal application.the designweaknesses testingrequirements be very different from one PLL to the and can next. of Consequently. A relatively low-frequencyclock. or PLL. A cellular telephone consists of many analog. modems.3 Applications of Mixed-Signal Circuits Many mixed-signal circuits consist of combinations of amplifiers.such as helping coordinate the handoff from one base station to the next as the user travels through each cellular area. It representsan excellent example of a complex mixed-signal system becauseit employs a variety of mixed-signal components.The voice-band interfaceconverts user'svoice into digital the samples usingan ADC. System-level tests guarantee that the circuit as a whole will perform as required in the end-equipment application. The synthesizeroften consists of several PLLs. DACs. recovered the clock from the PLL is usedto latch the individual bits or bytesof the incomingdatastream. 1. is then multipliedby an integervalue to producea higher-frequency masterclock. Since the digital cellular telephone will be used as an example throughout this book. motor controllers. The control microprocessor handlesthe interface with the user. Thorough testing of large-scale mixed-signal circuits therefore requires at least a basic understanding of the end-equipment application in which the circuits will be used.Chapter 1 . digital.digital signal processor(DSP). PLLs are typically usedto generate high-frequency referenceclocks or to recovera synchronous clock from an asynchronous stream. In thelattercase. hard disk drives. suchas 1 GHz. and other types of specialized analog and digital functions. The cellular telephone user interfaces with the keyboard and display to answer incoming calls and to initiate outgoing calls. It also performs many of the supervisory functions of the telephone. The voice-bandinterface. the digital cellular telephone. switches.

Therefore. These samples are then passedto the DAC and low pass reconstruction filter of the voice-band interface to reconstruct the voltage samples of the incoming voice. The vocoder's output bits are sent to the base-bandinterface and RF circuits for modulation and transmission. Before the voice signal can be digitizedby the voice-bandinterfaceADC. Before the received voice signal is passedto the earpiece. the vocoding algorithm can compress the important characteristics of speech into a much smaller set of data bits than the digitized sound pressure samples. The vocoding process is therefore a type of data compression algorithm that is specifically tailored for speech. making the speaker'svoice difficult to understand. The DSP converts the incoming bit stream back into digitized samples of the incoming speaker's voice. This earpiece PGA is adjusted by signals from the control microprocessor. which monitors the telephone's volume control buttons to determine the user's desired volume setting. The base-band interface acts like a modem. it must first be low-passfiltered to avoid unwanted high-frequency components might causealiasingin the transmittedsignal. The vocoding process converts the individual samples of the sound pressure waves into samples that represent the essence of the user's speech. The characteristics of the vocal tract change very slowly compared to the sound pressurewaves of the speaker's voice. (Aliasing is a that type of distortionthat can occur in sampledsystems. the process is reversed. the signal must be passedthrough a low impedancebuffer to provide the current necessaryto drive the earpiece. ) The digitized samples are sent to the DSP. The incoming voice data are received by the RF section and demodulated by the base-bandinterface to recover the incoming vocoder bit stream. .Alternatively. Finally.the PGA may be controlledwith a specialized digital circuit built into the voice-band interfaceitself. the PGA and automatic adjustment mechanism form an automaticgain control (AGC) circuit. Either way. In the receiving direction. converting the digital bits of the vocoder output into modulated analog signals. where they are compressedusing a mathematical process called vocoding.4 An Introduction to Mixed-Signal Testand Measurement IC control microprocessor.its volume is adjusted using a second PGA. The vocoding algorithm calculates a time-varying model of the speaker's vocal tract as each word is spoken. The RF circuits then transmit the modulated analog waveforms to the base station. The smaller number of transmitted bits frees up airspace for more cellular telephone users.

masking. let us look at the idealizedIC fabrication process. Many of the fabrication defects that cause problems in mixed-signal devicesare difficult to photograph. After many additional steps of printing. are not even visible in a cross-section view. the IC printing process is subject to blemishes and imperfections. The increasing integration of circuits into a single semiconductor die is one of the most challenging aspectsof mixed-signal test engineering. A pattern of ultraviolet light is then projected onto the photoresist using a photographicmask. or they may cause minor variations in performance from one IC to the next. The various circuit blocks of a cellular telephone may be grouped into a small number of individual integrated circuits. An organic solvent is used to dissolve the nonexposed areasof the photoresist (Figure 1. the exposed areas of silicon aredopedto fonn an N-well using either diffusion or ion implantation (Figure 1. 1. the digital cellular telephonerepresents a good example of a complex mixed-signal system. a negative photoresist is. This allows the microprocessor to receive information such as incoming call notifications from the base station.analog multiplexers to control the selection of multiple voice inputs.3d). The a uneven surfaces are exaggerated in the diagram to show that the various layers of oxide.2 Real-World Circuits Like any photographic printing process. Overview pi Mixed-Signal Testing 5 Severalcommon cellular telephone circuits are not shown in Figure 1.3f.S complete integrated circuit can be fabricated as illustrated in Figure 1.3e).3a). such as doping profiles that define the boundaries between P and N regions. Certain characteristics. Cross sectionsof actual integrated circuits reveal a variety of nonideal physical characteristics'that are not entirely under the semiconductor manufacturer's control. These include DC voltagereferencesand voltage regulators that may exist on the voice-band interface or the basebandprocessor. Nevertheless. even with a powerful scanning electron microscope (SEM).wafer. and doping steps. Clearly. and poweron resetcircuits.3b). After baking the remaining photoresist. The actual circuit structuresare not nearly as well defined as textbook diagrams would lead us to believe.Chapter 1 .2. Next. The test engineer must be readyto test the individual pieces of the cellular telephone and/or to test the cellular telephone as a whole. The photoresist becomes insoluble in the areas where the mask allows the ultraviolet light to pass (Figure 1. 1.3a-f. Next.2 WHY TEST MIXED-SIGNAL DEVICES? 1. implanting. Some of the steps involved in printing a CMOS transistor pair are illustrated in Figure 1. polysilicon. Using a digital CMOS fabrication process as an example. . etching.2.1 The CMOS Fabrication Process Integratedcircuits (ICs) are fabricated using a series of photolithographic printing.laid down on top of the silicon dioxide. and metal are not at all flat. and chemical vapor deposition. Starting with a lightly doped P. etching. a layer of silicon dioxide (SiOV is depositedon the surface (Figure 1. Mixed-signal ICs are often extremely sensitive to tiny imperfections or variations in the printing and doping processes.they can have a profound effect on many important analog and mixed-signal circuit characteristics. a watchdog timer is often included to periodically wake the control microprocessorfrom its battery-saving idle mode.2. or they may all be combined into a single chip.3c). Even with these exaggerations. called a chipset. m addition. this diagram only representsan idealized approximation of actual fabricated circuit structures. These imperfections may cause catastrophic failures in the operation of any individual IC. the exposed areas of oxide are removed using an etching process (Figure 1.

a doping error mayor may not causean observable physical defect. CMOSfabrication steps. As circuit geometries continue to shrink.Metal 2 .substrate Figure 1. However.and other problemsthat result in IC performance failures. metal tracesare to the rounded imperfect. the parasitic capacitance between these traces and surrounding structures may represent significant circuit elements. and In digital circuits.3. these perfonnance sensitivities will only become more exaggerated. doping errorscan introducelarge DC offsets.Metal 1 . such imperfections in shape may be largely unimportant. in mixed-signal circuits.4 showsa nondefective circuit as photographed using a FIB machine (a device similar to a scanning electron microscope). Although a mixed-signal circuit may be essentially functional in the presenceof . However. Certaintypesof defectscanbe photographed quite easily. Figure 1.6 An Introductionto Mixed-Signal Testand Measurement IC For example. (b) Photoresist exposure (c) Photoresist selective removal (d) Oxide etch (e) N-well doping Vias j SiOZ Protective overcoat (PO) . The exact three-dimensional shape of a metal line and its spacing to adjacent layers may therefore affect the perfonnance of the circuit under test.distortions. Compared the idealizedtextbook circuit representation.Polysilicon gate -CE:J -CH:] (f) Finished lC P.

A completely defective via usually results in a totally defective circuit.FIB micrograph metaltraceson an integrated of circuitobtainedusinga Schlumberger AMS3000 (photocourtesySchlumberger Test Equipment). Depending on the amount of excessresistance.6 shows a defective via caused by photomask misalignment.8 shows a surface defect caused by particulate matter landing on the surface of the wafer or on a photographic mask during one of the processing steps.5-1.5 shows a defective metal contact. Not surprisingly. which may exhibit an abnormally high contact resistance. Overvie1. Incomplete etching can result in catastrophic shorts between circuit nodes.4. it may not meet all its required specifications. caused by underetching. Again.the results of a partially connected via can range from minor DC offset problems to catastrophic distortion problems. Catastrophicdefects such as short circuits and open circuits are often easier to detect with test equipment than the subtler ones common in mixed-signal devices. Several typical defect types are shown in Figures 1. and surface explosions causedby electrostatic discharge in a mishandled device. Other catastrophic defects include surface scratches.8. . A more subtle problem is a partially connectedvia.7 shows incomplete etching of the metal surrounding a circuit trace. Figure 1. since it represents a completeopen circuit. Finally. Figure 1. For this reason. the catastrophicdefects are often much easier to photograph as well.Chapter 1 . this type of defect results in a short between circuit nodes. Defects suchas theseare the reason each semiconductor device must be tested before it can be shipped to the customer. or via. Figure 1. Figure 1.mixedsignal devices are often tested exhaustively to guard against defects that are not necessarily catastrophic.\l of Mixed-Signal Testing 7 theseminor imperfections. Figure 1.broken bond wires.

Misaligned via. it can only measure quality if it already exists. Incomplete metaletch. Either a customer requests particulartype of productto fill a specificrequirement. A new semiconductor product typically begins in one of two ways. and systems engineers. In either case. as long as we define the product correctly.8. a marketingorganization a or realizesan opportunityto producea productthat the market needs. This apparent discrepancy is easily explained if we recognize that the product is actually the entire shipment of devices.6. Figure 1.7. each profession entails its own set of tasks and responsibilities. The quality of the product is certainly improved by testing. Although each of these engineering professions is involved in the development and production of semiconductor devices.8 An Introductionto Mixed-Signal Testand Measurement IC Figure 1. It has been said that production testing adds no value to the final product. The various engineering professions are easiest to define if we examine the process by which a new semiconductor product is developed and manufactured. testing does add value to the product. Perhaps this would be a good time to discuss the traditional roles of test engineers.2. semiconductor companies would not spend money to test products if the testing processdid not add value.5. Blocked etch (particulate defect). Underetched via. Figure 1. 1. Testing cannot change the quality of the individual ICs. Figure 1. However.systems engineers help define the technicalrequirements the new product so that it will operate of . design engineers. since defective devices are not shipped. product engineers. not just the individual ICs. Testing is an expensive process that drives up the cost of integrated circuits without adding any new functionality. Therefore.3 What Is a Test Engineer? We have mentioned the term test engineer several times without actually defining what test engineering is.

and writing to nonvolatile memory cells. design engineersdevelop the corresponding integrated circuit. A typical mixed-signalDUT must pass hundreds or even thousandsof stimulus/responsetests before it can be shippedto the customer. The ATE tester then observes the DUT's response to the various test stimuli to determine whether the device is good or bad (Figure 1. The test engineer's role is to generatehardware and software that will be used by automated testequipment(ATE) to guaranteethe performance of each device after it is fabricated. forming a single test/product engineering position. The test cost reduction responsibility is shared with the product engineer. Teststimulus and OUTresponse verification.9. fuse blowing. the new design meets the technical requirements of the customer's application. Test stimulus OUT OUT response () c:=:) '" ~ -'Good' bO:d / Pass Fail Figure 1. The disadvantage is that the product engineering responsibilities may interfere with the ability of the engineer to become an expert on the useof the complex test equipment. Hopefully. The systems engineers are responsible for defining anddocumentingthe customer's requirements so that the rest of the engineering team can design the product and successfully releaseit to production. Unfortunately.9). integrated circuits sometimes to meet the customer's needs. The test softwaredirects the ATE tester to apply a variety of electrical stimuli (such as digital signals and sinewaves) to the device under test (DUT). After the systems engineers have defined the product's technical requirements. Despite claims that production testing addsno value. Sometimesthe test engineer is also responsible for developing hardware and software that modifies the structure of the semiconductor die to adjust parameterslike DC offset and AC gain. The failure may be due to a fabrication defect or it fail may be due to a flaw or weaknessin the circuit's design. Circuit modifications can be made in a number of ways. . and tester hardware and software defects. These failures must be detectedbefore the product is shipped to the customer. Overview of Mixed-Signal Testing 9 correctly in the end-equipment application.Chapter 1 . The advantageof the combined job function is that the product engineering portion of the job can be performed with a much more thorough understandingof the device and test program details. The product engineer helps identify and correct process defects. Sometimesthe product engineering function is combined with the test engineering function. or to compensatefor grotesque manufacturing defects. The choice of combined versus divided job functions is highly dependenton the needs of each organization. design defects. this is one way in which the testing process can actually enhancethe quality of the individual ICs. The test engineer is also responsible for reducing the cost of testing through test time reductionsand other cost-saving measures. including laser trimming. The product engineer's primary role is to support the production of the new device as it matures and proceeds to profitable volume production.

1 Test and Packaging After silicon wafers have been fabricated. the individual packaged devices are separatedfrom one another by trimming them from the lead frame. The untested wafers (Figure 1. Consequently. Untested wafer. The wafers are then sawed into individual dies and the good ones are attached to lead frames.3. trace-to-trace capacitances increased. Bond wires are attached from each die's bond pads to the appropriate lead of the lead frame.3 An Introductionto Mixed-Signal Testand Measurement IC POST-SILICON PRODUCTIONFLOW 1. are which may affect sensitivenodesin the circuit. many additional production stepsremain before a final packaged device is ready for shipment to the customer. example. In addition.10. After the leadshavebeentrimmed and formed. Final testingguarantees the performance the devicedid not shift that of during the packagingprocess.the insertionof plastic over the surfaceof the die For changesthe electrical permitivity near the surface of the die.the devicesare ready for final testingon a secondATE tester. Then plastic is injection-molded around the dies and lead frame to fonn packaged devices. Finally.10) must first be probed using automated test equipment to prevent bad dies from passing on to further production steps.10 1. The bad dies can be identified using ink dots. Figure 1. Offline inking is a method used to electronically track bad dies using a computer database. which are applied either after each die is tested or after the whole wafer has been tested. Lead frames are punched metal holders that eventually become the individual leads of the packaged device.bad dies are inked after the wafer has been removed from the test equipment.Using pass/fail information from the database.the .

Tests are perfonned under many different conditions to evaluate worst-case conditions. Overview of Mixed-Signal Testing injection-molded plastic introduces mechanical stressesin the silicon. After final testing. LTX. such as Teradyne.Chapter 1 . which may consequently introduceDC voltage shifts. Product and test engineers must work very to closelyto make sure that the reducedtest list still catchesall manufacturing defects.12.11shows a tray of tested quad flat pack (QFP) devices in a plastic carrier tray. a . Figure 1. Extensive characterization is therefore economically unacceptable in high-volume production testing of mixed-signal devices. and Schlumberger. The Teradyne. Final testing also guaranteesthat the bond pads are all connected and that the die was not cracked. Other examples of exhaustive characterization testing would be DC offset testing using multiple power supply voltages and hannonic distortion testing at multiple signal levels. Figure 1. scratched. and the mainframe. Characterizationtesting must be perfonned over a large number of devices and over several production lots of material before the results can be considered statistically valid and trustworthy. Once worst-case test conditions have been established and the design engineers are confident that their circuits meet the required specifications. a more streamlined production test program is needed.2 Characterization versus Production Testing When prototype devices are first characterized. High-end ATE testers often consist of three major components: test head. a workstation.4.1 Automated Test Equipment Automatedtest equipment is available from a number of commercial vendors. Inc. The production test program is created from a subset of the characterization tests. The subset must be carefully chosen guaranteethat no bad devices are shipped.11. or otherwise damaged in the packaging process. Characterization testing can be quite time consuming due to the large number of tests involved. TestedQFPdevicesin a plasticcarriertray. the devices are ready for shipment to the end-equipment manufacturer. 1. For instance.3. 1.the distortion of an amplifier output may be worse under one loading condition than another. to name a few. All loading conditions must be tested to identify which one represents the worst-case test.the ATE test program is usually very extensive.4 TEST AND DIAGNOSTIC EQUIPMENT 1. Agilent Technologies. Catalyst mixed-signaltester is shown in Figure 1.

and one or more computers that control the instruments as the test program is executed. swap block. Figure 1. Therefore.Deviceinterface board(018)showinglocalcircuits(left)and OUTsocket(right).12. These circuits are the ones which require close proximity to the device under test. high-speed digital signals benefit from short electrical paths between the tester's digital drivers and the pins of the DUT. The computer workstation serves as the user interface to the tester. DIBs come in many shapesand sizes.but their main function . The mainframe contains power supplies. For example. The mainframe may also contain a manipulator to position the test head precisely. Although much of the tester's electronics are contained in the mainframe section.).13. It may also contain a refrigeration unit to provide cooled liquid to regulate the temperature of the test head electronics. or family board. measurement instruments. depending on the ATE vendor's terminology. TeradyneCatalyst mixed-signal tester(photocourtesy Teradyne. Manufacturing personnel can also use the workstation to control the day-to-day operation of the tester as it tests devices in production. A device interface board (DIB) forms the electrical interface between the ATE tester and the DUT.Inc. The test engineer can debug test programs from the workstation using a variety of software tools from the ATE vendor.12 An Introductionto Mixed-Signal Testand Measurement IC Figure 1. The DIB is also known as a performance board. the test head contains the most sensitive measurementelectronics. the ATE tester's digital drivers and receivers are located in the test head close to the DUT.

They provide a means of temporarily connecting the DUT to the ATE tester'selectrical instrumentation while testing is performed.14.16.15 shows a gravity-fed handler. Inc. The ATE tester then executes a series of electrical tests on the die before instructing the proberto move to the next die. 1. . Gravity-fed handlers often perform this task using a contactorassemblythat grabs the device pins from either side with metallic contacts that are in turn connectedto the DIB board. Either type of handler has one main purpose: to make a temporary electrical connection betweenthe DUT pins and the DIB board. The PIB and probe card serve the samepurpose for the wafer that the DIB board servesfor the packageddevice. Robotic handlers usually pick up each device with a suction ann andthen plunge the device into a socket on the DIB board. A robotic handler is shown in Figure 1.2 Wafer Probers Wafer probers are robotic machines that manipulate wafers as the individual dies are tested by the ATE equipment.3 Handlers Handlers usedto manipulate packageddevices in much the sameway that probers are used to are manipulatewafers. Gravity-fed handlers are normally used with dual inline packages.Chapter 1 ..4. The DIB alsoprovidesspacefor DUT-specificlocal circuits suchas in loadcircuitsandbuffer amplifiersthat areoftenrequiredfor mixed-signal devicetesting. The handshakingbetween tester and prober insures that the tester only begins testing when a die is in position and that the prober does not move the wafer in midtest. The PIB is a specialized type of DIB board that may be connected the probe card through coaxial cables and/or spring-loaded contacts called pogo to pins. Electroglas waferproberand probecard. The prober informs the tester when it has placed each new die against the probes of the probe card.for example). 1. and closeup views of a probe card and its probe tips. The probes are connected to the electrical resources of the ATE tester to through a probe interface board (PIB).Figure 1. Handlers fall into two categories: gravity-fed and robotic.while robotic handlers are used with devices having pins on all four sides or pins on the underside (ball grid array packages.4. The prober moves the wafer underneath a set of tiny electrical probes attached a probe card.14 shows a wafer prober manufactured by Electroglas. Probe card Probe tips Figure 1. Robotic handlers are also known as pick-and-place handlers. Overview of Mixed-Signal Testing 13 is to providea temporary(socketed) electricalconnection betweenthe DUT and the electrical instruments the tester. Figure 1.

Low voltage Figure 1. Some handlers also provide a controlled thermal chamber where devices are allowed to "soak" for a few minutes so they can either be cooled or heated before testing. Schlumberger IOS-10000 electronbeamprober (photocourtesy Schlumberger Test Equipment). Variations in the voltage levels on the metal traces in the IC appear as different shades of gray in the e-beam display (Figure 1.17. MultiTest gravity-fed handler.17).15. . Unlike an SEM.4. since they provide measurementaccessto internal circuit nodes. are used to probe internal device signals while the device is being stimulated by the tester. Deltarobotichandler. These machines are very similar to scanning electron microscopes(SEMs). or e-beam probers as they are often called.4 E-Beam Probers Electron beam probers. e-beam probers are extremely powerful diagnostic tools.16.this is an important handler feature. Since many electrical parametersshift with temperature. Figure 1.14 An Introductionto Mixed-Signal Testand Measurement IC In addition to providing a temporary connection to the DUT. handlers are also responsible for sorting the good DUTs from the bad ones based on test results from the ATE tester. an e-beam prober is designed to display variations in circuit voltage as the electron beam is swept across the surface of an operating DUT. Figure 1. 1.

1.Chapter 1 . When characterizing a small number of DUTs at a variety of temperatures. A FIB machine can cut holes in oxide and metal tracesand can also lay down new metallic traces on the surface of the device (Figure 1. Portable forced-temperaturesystemsallow DUT performance characterization Figure 1. The results of the experimental changes can then be observed on the ATE testerto determine the successor failure of the experimental circuit modifications. .18.5 Focused Ion Beam Equipment Focusedion beam (FIB) equipment is used in conjunction with e-beam probers to modify the device's metal traces and other physical structures. a handler's thermal chamber allows characterization and testing of large numbers of DUTs at a controlled temperature. Circuitmodifications implemented usingFIB equipment.18). a less expensive and cumbersome method of temperature control is needed. Figure 1.4. Overview of Mixed-Signal Testing 15 1. Experimentaldesign changescan be implemented without waiting for a complete semiconductor fabrication cycle.19. Temptronics forced-temperature system.6 Forced-Temperature Systems As previously mentioned.4.

power consumption requirements. and manufacturing personnel. test and product engineers work with the design engineers to define the testability features that will make the device less expensive to test and manufacture. This proactive approach is commonly called concurrent engineering. By contrast.5 NEW PRODUCT DEVELOPMENT 1. Once the device requirements are understood. Figure 1. These include product features. the test engineer's role on a well-managed project is proactive. The design engineers can catch mistakes in the test engineer's understanding of the device operation.20.the test engineer's role is completely reactive. These observability test modes can be very useful in diagnosing device design flaws.1 Concurrent Engineering On a poorly managedproject. product engineering. the 1. fornling a small thernlal chamber the DUT. They can help eliminate unnecessarytests or point out shortfalls in the proposed test list.explaining all the tests that are to be performed once the device is in production. but also systems engineering. electrical specifications. Concurrent engineering projectflow The flow begins with a definition of the device requirements.19). .20 shows a simplified concurrent engineering flow for the development and production releaseof a new semiconductor product. In this case. The nozzle of a forcedtemperature system can be seatedagainstthe Dill board or bench characterization board. Figure 1. True concurrent engineering involves not only design and test engineering personnel. The test engineer presents a test plan to the design engineers. In the initial design meetings.5. the design team begins to design the individual circuits. the test engineer might not see the specifications for a device to be tested until after the first prototype devices arrive.16 An Introductionto Mixed-Signa/'ICTestand Measurement under a variety of controlled thernlal conditions (Figure 1. Many forced-temperature for systems able to are raiseor lower the DUT's ambient temperature across full military range(-55 to + 125°C). die area estimates. The design engineersand test engineerswork together to add testability functions to the design that make the device easier and less expensive to test. Test modes are added to the design to allow accessto internal circuit nodes that otherwise would be unobservable in production testing. The devices must be screened as soon as possible to ship good prototypes to the customer even if they were never designed with testability in mind. etc.

Last-minute corrections and additions are added at this time. who then begin evaluating possible design errors. concurrent engineering is consistently much more effective than a disjointed development process with poor communication between the various engineering groups. the test engineer cannot be certain that the pinout or functionality of the design will not undergo last-minute modifications. setup conditions for each test. DIB hardware. While the silicon wafers and the DIB board are fabricated. Initially. In reality. 1. Marginsbeginto shrinkas are to . the test plan will serve as documentation for future test and product engineers that may inherit the test program once it is complete. This flow also assumesthat the market does not demand a change in the device specifications in midstream . Until pattern generation is complete.who then supports the day-to-day manufacturing of the new product. the test engineer can also debug many of the software routines in the test program before silicon arrives.6. Concurrent engineering is based on the assumptionthat adequate personnel and other resources are available to write test plans and generatetest hardware and software before the first silicon wafers arrive. The test interfacehardware is often fabricated only after the pattern generation step has been completed. a highperfonnance device may require several design passes before it can be successfully manufacturedat a profit. Once the test plan is complete. the main purpose of a test plan is to allow design engineers and test engineersto agree upon a set of tests that will guaranteethe quality of a product once it is in production. such as tape-out or pattern generation. Overviewof Mixed-SignalTesting 17 After the test modes are defined. the purpose of each test as it relates to the device specification. Any design problems are reported to the design engineers. Nevertheless. the test engineer continues developing the test program. Once the first silicon wafers arrive. and software on the ATE tester. Design engineers point out deficiencies in the proposed test coverage while product engineers point out any problemsthat may arise on the production floor. It also assumesthat only one additional design pass is required to release a device to production. the fabrication masks are created from the design database.1 Time to Market Timeto marketis a pressingissuefor semiconductor manufacturers. Finally. the test engineer begins writing a test program that will run on the ATE tester. A second designpass is often required to correct errors and to align the actual circuit performance with specificationrequirements. After the design and layout of the device is complete. Once the initial test hardware has been designed. all engineers working on the project meet to review the proposed test plan. Of course. using an offline simulation enviromnentrunning on a stand-alonecomputer workstation.6 MIXED-SIGNAL TESTING CHALLENGES 1. Eventually.a poor assumption in a dynamic world. the test engineer begins debuggingthe device. the test engineer begins to design the necessarytest interfacehardware that will connect the automatedtest equipment to the device under test.the idealized concurrent engineering flow is a simplification of what happens in a typical company doing business in the real world. The databasereleaseprocess is known by various names. the test engineer begins working on a test plan while the designprocesscontinues. and a hardware setup diagram for each test. the corrected design is releasedto production by the product engineer. In modem ATE equipment. A well-written test plan contains brief background information about the product to be tested.Profit marginsfor a new product highestshortly after it hasbeenreleased the market. Once the test plan has been approved.Chapter1 .

can test Repeatability is the ability of the test equipment and test program to give the same answer multiple times. but also meets the mechanical docking requirements. and various alignment pins and holes. and debugging the ATE test solution once silicon is available.improperly ranged instruments. Correlation efforts can representa major portion of the time spent debugging a test program. The test engineer must determine which answer is correct and why there is a discrepancy. Unfortunately. There are few mechanical standardsin the ATE industry to specify how a tester should be docked to a handler or prober. Repeatability. A good measurementtypically shows some variability from one test program execution to the next. Surprisingly. Mixed-signal test engineers often spend as much time running experiments for design engineers to isolate design errors as they spend debugging their own test code. connector locations. the time spent writing test code is often significantly less than the time spent learning about the device under test. 1. These problems frequently result from obscure hardware or software errors that may take days to isolate. Actllally.and Correlation Accuracyis a major concernfor mixed-signal engineers.2 Accuracy. It sometimes indicates that the tester is improperly configured.especiallywhen testinghigh-impedance high-frequency or circuits. giving the same incorrect answer repeatedly. Electromagnetic interference.the metallic contactsbetween DUT and DIB board are often very inductiveand/orcapacitive.6. The customer or design engineer often finds that the test program results do not agree with measurementstaken using bench equipment in their lab.3 Electromechanical Fixturing Challenges The test head and DlB board must ultimately make contact to the DUT through the handler or prober. Mixed-signal test programs are particularly difficult to produce in a short period of time. The test engineer has to design a DlB board that not only meets electrical requirements. improperly calibrated instruments. a measurementthat never changes at all is suspicious.and measurements made under incorrect test conditions all leadto inaccurate results. Electrical noise is the source of many repeatability problems. It is also common to find that two supposedly identical testers or DIB boards give different answers or that the same tester gives different answers from day to day. 1. designing the test hardware. Much of the time spent in the debugging phase of test development is actually spent debugging device problems. Although . Another problem facing mixed-signal test engineers is correlation between the answers given by different pieces of measurementhardware. Stray inductance capacitance the contactscan represent and of a major problem. Inaccurate answers caused a are by bewildering number of problems.cost-effective test programis often the main bottleneckpreventingthe releasea new product to profitable volumeproduction. The lack of a complete. Handlersand probersmust makea reliable electricalconnection betweenthe DUT andthe tester. These requirements include board thickness.18 An Introduction to Mixed-Si~nal IC Test and Measurement competitors introducesimilar productsat lower prices.6. defining the test plan. Perhapsthe most aggravating debug time of all is the time spent tracking down problems with the tester itself or the tester's software.It is very easyto get an answer test from a mixed-signalATE testerthat is simply incorrect. since electrical noise is present in all electronic circuits. DUT socket mechanical holes.

Unfortunately. a socketed device will often not perform quite as well as a device soldered directly to a printed circuit board. and production personnel. a five-second test program costing four cents per secondtimes one million devices per quarter costs a company $800. Multisite testing is a processin which multiple devices are tested on the same test head simultaneously with obvious savings in test cost. If we also include the cost of providing floor space. Multisite testing is primarily a tester operating system feature. although duplicate tester instruments must be added to the tester to allow simultaneous testing on multiple DUT sites. Since a mixed-signaltest program may perform hundredsor even thousands measurements each DUT. especially when it comes to production test programs.The conflictingrequirements low test time andhigh accuracy of will be a recurring theme throughout book. the tester can run almost continuously. but when test costs are multiplied by millions of devices a year the numbers add up quickly. Testing is perhaps the fastest-growing portion of the cost of manufacturing a mixedsignal device. each measurment of on must be performedin a small fractionof a second. Probers and handlers may cost five hundred thousand dollars or more. test time (especially data collection time) cannot be similarly reduced by simple photolithography. Another feature common in mainframe testers is multisite capability. For example. The purpose of the second head is to allow the tester to simultaneously test a device on one head while a second handler or prober is moving and sorting devices on the other head.21). Continuous process improvements and better photolithography allow the design engineersto add more functions on a single semiconductor chip at little or no additional cost. electricity.productiontest economics an extremelyimportant issuein the field of mixedis signaltest engineering. many testers can be equipped with two test heads that share the mainframe instruments in a multiplexing fashion (Figure 1. A 100-Hz sine wave takes 10 ms per cycle no matter how small we shrink a transistor. depending on its configuration. The word "site" refers to each socketed DUT. Thus dual-head testing allows a more efficient use of the expensive tester hardware. site I corresponds to the second DUT. For example. This may not seem expensive at first glance. this .6. site 0 correspondsto the first DUT. One secondof test time can cost a semiconductor manufacturer three to five cents. 1.4 Economics of Production Testing Time is money.000 per year in bottom-line profit. Mainframe ATE equipment is designed to minimize test time and maximize overall product throughput. When a handler or prober is docked to eachtest head. etc. The only hope of salvation from photolithography is the addition of test features into the design itself that aid in the testing of the DUT. A high-performance tester may cost two million dollars or more.Chapter 1 . the measurements but must be performedas quickly as possibleto reduceproductioncosts. For example. Performancedifferences due to sockets are yet another potential source of correlation error and extendedtime to market. Not only must the test engineerperform accuratemeasurements of mixed-signal parameters. Dual-head testing is especially important when the handler index time (the time it takes to remove one DUT from the tester and insert the next one) is significant compared to the test time. Clearly. it is easy to understand why testing is an expensivebusiness. Overview of Mixed-Signal Testing 19 severalcompanieshave marketed test sockets that reduce these problems.

Questions1. List four examples of mixed-signal circuits. Whena PGA is combined with a digital logic block to keepa signalat a constant level. Which type of digital circuit vocodes the speaker's voice samplesbefore they are passed to the base-bandinterface? 1. Which type of mixed-signal circuit convertsincomingmodulated voice datainto digital samples? 1. 1.21. Which type of mixedin signalcircuit actsasa volumecontrolfor the cellulartelephone earpiece? 1. Teradyne A575with dualtest heads.2.9.6 relateto the cellular telephone Figure 1. . Assumea particle of dust lands on a photomask during the photolithographic printing process a metal layer.1. List at least four production stepsafter wafers have been fabricated.2.3.3-1.8. whatis the combined circuit called? 1.20 An Introductionto Mixed-SignallC Testand Measuremem Figure 1. List four examples analogcircuits.4. 1. List at leastonepossibledefectthat might occurin the printed of IC.6. Which type of mixed-signal circuit converts the speaker's voice into digital samples? 1.5.7.10. Problems 1. Why does the cleanliness of the air in a semiconductor fabrication area affect the number of defects in IC manufacturing? 1. of 1.

ISBN: 0471851353 5. New York.80. January. Boston.Chapter 1 .1996.18. 1. 1. 1998. personnel.. Arthur D.14. NY 10158-0012. List three advantagesof concurrent engineering. NY 10158-0012. ISBN:0780310624 3. 321 HarrisonAve.15. Why would it be improper to draw conclusions about a design based on characterization data from one or two devices? 1.17. floor space. Miron Abramovici. Practical Digital Logic Design and Testing.Digital TestEngineering. handler depreciation.5 s. and that the averagetime to find a bad device drops to 0. How many dollars worth of product would have to be shipped to make a profit equal to the savings offered by the streamlined test program in Problem 1.18 is 20% (i. 1997 Teradyne User'sGroupproceedings.. J.11.Ken Martin. NY. etc. ParagK. 1996. JohnWiley & Sons. Melvin A. List three main componentsof an ATE tester.605 Third Ave. for each $1 worth of devices shipped to the customer. 1987. List at least four challengesfaced by the mixed-signal test engineer.ISBN: 04711444R7 . Assume a test program runs on a tester that costs the company 3 cents per second to operate..MA 02118 2.13.John Wiley & Sons.ISBN: 0023671718 4. Upper Saddle River. This test cost includes tester depreciation.18? If each device sells for $1.Digital Systems Testingand Testable Design. What is the putpose of a DIB board? 1. Breuer.12. electricity. assuming 5 million devices per year are to be shipped. 1. the company makes a profit of 20 cents). Johns. New York. Friedman. Overview of Mixed-Signal Testing 21 1. Assume that only 90% of devices tested are good.605 Third Ave. How much money can be saved per year by reducing a 5-s test program to 3. IEEE Press. Mark Bums.16. Max Cortner. What type of equipment is used to handle wafers as they are testedby an ATE tester? 1.New Jersey. 1.19. Assume the profit margin on the device in problem 1.PrenticeHall.e. Inc. Teradyne. David A. Revised Printing.. Analog IntegratedCircuit Design. High SpeedMeasurements Using Undersampled Delta Modulation. New York. What is the purpose of a test plan? 1. how many devices does this represent? What obvious conclusion can we draw about the importance of test time reduction versus the importance of selling and shipping additional devices? References 1.5 s.. Lala.

Of course. it is the test engineer's responsibility to make sure the error gets corrected or clarified so that a sensible test plan can be defined. In effect. if an inappropriate measurement is specified in the initial data sheet. The answerto the ownershipquestiondependssomewhaton the type of device being developed. semiconductor at manufacturers do not test every possible frequency in production. When development of a new device begins.1. As the project progresses. Oncedefmed. as it is often called. The definition of a production test plan usually begins with a device data sheet or specification sheet. a low-pass filter ripple specification of :t1.the test and product engineersrefer to the data sheetto define the test list. A test plan is a written list of tests and test procedures that will be used to verify the quality of a particular device under test (DUT). For example. Unfortunately. Data sheet errors should be promptly corrected to prevent further mistakes. Before exploring the art and science of mixedsignaltest plan generation. especially when one tries to define exactly how a data sheet is translated into a test plan. Likewise.1 DEVICEDATA SHEETS 2. For instance. Design engineersrefer to the data sheet as a blueprint to make sure they design the functions that the marketing and systems engineering organizations have specified. For this reason it is important to know which organization is responsible for controlling the data sheet's contents. the customerrefers to the data sheetwhile designing the device into the system level end application.1 Purpose of a Data Sheet Beginning test engineers often spend a great deal of time learning how to generatetest plans for mixed-signal devices. let us look at the function and structure of a data sheet in detail.CHAPTER 2. The test list must be comprehensive enough to guarantee that the manufactured devices meet the data sheet specifications. The data sheet serves many purposes. Therearetwo kinds of devices: catalogandcustom. Throughout the design process.a catalog or 23 . The test engineer often detects data sheetmistakes and ambiguities while writing the test plan or developing the test program. A catalogdeviceis onethat is defined the semiconductor by manufacturer by an IC designhouse. the data sheetservesas the design specification. the tester and device interface board (Dffi) can be considered the new device's first application. Test plan generation sometimesseemslike more of an art than a science. the test engineer is the first customer for a new design.O dB states that gain variation is guaranteed each and every frequency in the passbandof the filter. the data sheet does not directly translate into a fInite list of all required production tests. The data sheet thus serves as the formal communication channel between the marketing and engineeringpersonnel engagedin a project.

The feature summary allows the customer to quickly gauge the device's fit to a particular application. The device description gives a quick overview of the device's functionality.The test engineer only needsto get agreementfrom the design and systems engineers to make a data sheet change. we must first understand the purpose of each of these data sheetsections. Regardless of the customer's needs. this function might be tested in an indirect manner. It servesno purpose in the system-level end application. data sheet changes may be very easy to implement or they may be impossibly difficult. the customer and systems engineer share responsibility for the contents of the data sheet. application information. definedby a specificcustomer. Total test time would be only 1 ms (plus overhead introduced by the tester). the device description defines the various operations of the device in detail. For this reason.1. There are many indirect ways to guaranteethe operation of a l-s timebase counter without spending 1 s of test time. The test engineer refers to the pinout and packageinfonnation to design the DIB for each packagetype. though not necessarily in a straightforward manner. specification changes requested at the last minute give the appearance of a poorly run organization. The two divider stagescould then be tested simultaneously to guaranteethe functionality of the whole.! The first page of the data sheet provides a quick device summary. The test program must guaranteeall these functions. timing diagrams.2 Structure of a Data Sheet Data sheets may contain any of the following sections: a feature summary and description. principles of operation. and die layout.1 shows an example data sheet for a digital-to-ana1og converter (DAC).2). timing diagrams.by for contrast. For instance. In addition to approvals from the marketing or systems engineering team. The test engineer can generally ignore this section since the same infonnation is typically called out in subsequentsections of the data sheet. This data sheet is taken from a Texas Instruments data acquisition circuits data book. The sectionsthat are most pertinent to test engineering are the device description. Before we can understand the process by which the production test list is developed. This is an example of a design for test (Dff) test mode. though. producing a l-s timebase. electrical characteristics. principles of operation. 2. Since straightforward testing would representan unacceptably long test time of 1 s. The customer does not need .alIC Testand Measurement deviceis offeredto multiple customers use in their end applications. circuit schematic. electrical characteristics. the systemsengineering or marketing organization controls the data sheet. it is a good idea for the test engineer to get involved very early in the definition of a device so that specification changes can be suggested in a timely manner. In the case of a custom device. absolute maximum ratings. Suggestionsmade early in the new product development cycle give a customer more confidence that the testing process is under control.24 An Introductionto Mixed-Sigi. characterization data. Together with the principles of operation (Figure 2. For example. Figure 2. and package/pinout information. In the caseof a catalog device. Depending on the customer's requirements.It mustmeetthat customer's is exactrequirements. the customer's approval is also required before the data sheetcan be modified. The pinout and package infonnation is much more relevant to test engineering. the device description may depict a circuit that divides an externally generated I-MHz reference clock by one million. A customdevice. a special test mode might split the divider into two separatestagesthat each count to one thousand in only 1 ms.

~~~ ~~ 9 1011 1213 14 DBO NC-No internal connection The devices are B-bit.Chapter 2 .'ily.. OAUAS TEXAS. Therefore. Datasheetfor 8-bit multiplying DAC:features. . j . to Microprocessors On-ChIp Data Latches D OR N PACKAGE (TOP VIEW) OUT1 1 16 RFB : .. .. Inc liEXAS INSrRUMENrs 1 Figure 2. InS1romen1S 1991. The TLC75241 is characterized for operation from -25°C to BSoC. TLC75241 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS i SLAS061B-SEPTEMBER 1986.N TLC7524EN PLASTIC DIP (N) ~A. TLC7524E. TLC7524E.:TK* - . 5 5 ~ It ~ 3 2 (TOP N. and use .DATA PACO. . in TLC7524C. . description. The TLC7524C. The devices provide accuracy to 1/2 LSB without the need lor thin-film resistors or laser trimming.REVISED NOVEMBER 1991 : \ . TheTLC7524C characterized operation is for IromO°Cto 70°C. The 2. B-bit..converters are and CMOS. pinout. Easily Interfaced .The TLC7524E is characterized operation from 40°C to B5°C for - AVAILABLE T A I1'C to 70'C -25'C to BS"C -4I1'C to 8S"C SMALL OUTLINE PLASTIC DIP (D) TLC7S24CD TLC7524ID TLC7524ED OPTIONS PACKAGE PLASTIC CHIP CARRIER (FN) TLC7S24CFN TLC7524IFN TLC7S24EFN TLC7524CN TLC7S24. Od_""'" 01 ~- ~ POST oox OFfICE~0J03 . which produce the highest glitch impulse.n critical appl"a"ons Texas Instrumenls semiconduclor products and disclaimers Ihereto appears al the end of Ih.. standard warranly.VIEW) 4 S 6 7 1 20 19 18 17 16 V -9-P WR NC i 1S CS ."_oIT . Propaga"on delay "me 8 BIts 1/2 LSB Max SmWMax 100nsMax 80 ns Max Powerdissipa1lonatVoo'SV GND DB7 NC DB6 D FNPACKAGE 1-11IIu. Monotonic Over the Entire AID Conversion Range Segmented High-Order Bits Ensure Low-Glitch Output OUT2 GND DB7 2 3 4 15 REF 14 ~ 13 ~ Interchangeable With Analog Devices AD7524 PMI PM-7524 and Micro Power System~ MP7524 ' Fast Control Signaling lor Digital Signal-Processor DB6 s DBS 6 DB4 7 DB3 8 12 CS 11 DBO 10 DB1 9 DB2 .. Featuring operation from a 5-V to 15-V single supply. while dissipating less than 5 mW typically.digital-to-analog TLC75241 (DACs) designed lor easy interface to most popular microprocessors. modes test mayor may not be documented the datasheet. these devices interface easily to most microprocessor buses or output ports.or 4-quadrant multiplying makes these devices an ideal choice for many microprocessor-controlled gain-setting and signal-control applications. The Test ~pecification Process 25 to split the divider into two halvesandmay not evenneedto know that it can be placedin this testmodeat all.s data sheel of -_OO_".1. description DBS 8 : . multiplying DACs with input latches and load cycles similar to the write cycles 01a random access memory Segmenting the high-order bits minimizes glitches during changes in the most significant bits. CopyngIO: To. and . : InterfaceWith TMS320 CMOS Technology Applications Including KEY PERFORMANCE SPECIFICATIONS Reso!ullon Linearity error Selting"me . _01~- Please be aware that an important notice concerning ava"ab. .

the situation is reversed as shown in Figure 2. TLC7524E. '." 1~"F OUT2 Figure 2. ~ 1: I J."". The capacitances appearing at OUT1 and in Figure 2. ~R I _: -' -RFB OUT1 T 30 pF Ire! REF~ '-N\. Analysis of the circuit for all digital inputs high is similar to Figure 2. analog switches. of the WR signal.2. through a modification in the R-2R ladder. while the substrate.. and data input latches. Tables 1 and 2 summarize input coding for unipolar and bipolar operation respectively.TLC7524E. in this case. The current source termination resistor of the R-2R ladder. DBa-DB7 data bus inputs. IIk9fr 6 1 I 6.~ ~ -.TLC75241 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS ~I'~'R_~~P="R~Q 'Q~-Q~\/I~~n~V~"Q~Q '007 PRINCIPLES OF OPERATION The TLC7524C. 'ref would be switched to OUT1 . In this mode. These devices are capable 2-quadrant or 4-quadrant of performing multiplication 2-quadrant or full4-quadrant multiplication. the entire reference 1/256 represents the constant current flowing through the current source Ilkg represents leakage currents to the OUT2 are dependent upon the digital input code. and TLC75241 are 8-bit multiplYing DACs consisting of an inverted R-2R ladder. a microprocessor through the data bus and the CS and WR control analog output on these devices responds to the data activity on the the input latches are transparent and input data directly affects the or WR signal goes high. the data on the DBa-DB7 inputs are latched When CS is high.26 An Introductionto Mixed-Signal Testand Measurement IC TLC7524C. however.. TLC7524 Equivalent Circuit With All Digital Inputs Low Figure2. The equivalent circuit for all digital inputs low is seen current. Most applications only require the addition of an external operational amplifier and a voltage reference. Eight-bit multiplying principles operation DAC: of . When CS and WR are both low. the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch capacitance (120 pF maximum) appears at OUT1. These decoded bits. Binary-weighted currents are switched between the OUT1 and OUT2 bus lines. Iref' is switched to OUT2. When either the CS signal until th~ and WR signals go low again. With all digital inputs high. the data inputs are disabled regardless of the state The DAC on these devices interfaces to signals. control three equally-weighted current sources. analog output. With all digital inputs low. Circuit configurations for are shown in Figures 3 and 4. With all digital inputs low. thus maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are decoded.

The other twelve gain steps might be calculated mathematically depending on the accuracyrequirements of the test and the robustnessof the design. Only a functional pattern test is required to guaranteethe I-s interval. is The only way the I-s period of time could be in error is if the divider circuits are not functional or if the I-MHz external reference clock is not set to the correct frequency. These features are verified using what is often referredto as a go/no-go test or functional test. Parametric tests. the test engineer needs to understand the end application of the device. Often.The device description and principles of operation provide the test engineer with much of the information neededto understandthe system into which the device will be placed. A data sheet states that a programmable gain amplifier (pGA) can be set to gains from 0 to 30 dB in 2-dB steps. The test engineer should verify that all digital functionality has been guaranteed by either automatically generatedpatterns or by hand-coded functional pattern tests. It is up to the test engineer and design engineer to work through all the required functionality in the principles of operation and detennine what series of tests and test modes constitute an acceptablebalance between test thoroughness and costly test time.1. Fi~es 2. since it is not a function of device performance. it might be possible to measure only four of the sixteen gain steps. 2. An incorrect external frequency setting does not need to be tested during IC production. There are generally parameternames to the left side of the chart. The digital countercircuit either dividesby one million or it doesnot. Many of the features listed in the device description and principles of operation do not result in measurementsof electrical parameters. . The astute design engineer will make architectural decisions based not only on circuit perfonnance but also on test efficiency. In highly customized mixed-signal devices.Chapter 2 . followed by test conditions. Otherwise. a series of notes are listed below the electrical characteristics that give more complete background information for some of the specifications.3 and 2. An automated software process is often used to generate functional pattern tests. The experiencedtest engineer serves a critical role in helping to define what kinds of circuits can be most efficiently tested. While the format of the electrical characteristics section may vary widely from one manufacturer to another. It is not necessary measure exact countdownperiod in seconds to the and fractionsof a second. are those that return a value that mustbe compared against one or more test limits to determine pass/fail results.4 show the electrical characteristics for the 8-bit multiplying DAC. by comparison. This type of digital logic verification knownasafunctionalpattern test. the concurrent engineering process described in Chapter 1 will be impeded and the test engineer will not be able to contribute to the design definition and debug.3 Electrical Characteristics Electrical characteristics (or electrical specifications) provide the test limits and test conditions for many of the parametric tests in a mixed-signal test program. The Test Specification Process 27 Consider a second example of indirect testing which is more applicable to mixed-signal circuits. corresponding to the four gain setting paths of the binary architecture. there are some common features. The I-s timer is a goodexample a circuit that canbe tested of with a functionaltest. If the PGA is designedwith a binary weighted resistor structure. It mayor may not be necessaryto test each and every gain step. Functional tests result in a simple pass/fail result with no numerical reading.

25 MIN 145 NOM 15 j.VDD = ot10% V 1-0 0.10V Quiescent DBa-DB7 at VIHmin or Vilmax Standby DBa-DB7 at 0 V or VDD t.WR low.5 UNIT V V V V ns ns ns ns ns TlC7524E electrical characteristics over recommendedoperating free-air temperature range.ANALOG CONVERTERS SlASO61B-SEPTEMBER 1986REVISED NOVEMBER 1997 recommendedoperating conditions VDD=5V MIN NOM Supply vonage. nIY. VDD Referencevoltage.04 %FSRJO/. TLC7524E.5 VDD=15V MAX 5.TO.- nA IDD Supply current Vref=J. CS 5 pF 30 20 5 30 20 kn POSTOFFICE BOX655303.8 40 0 25 10 40 0 -25 -40 70 85.3. Vref High-level input voltage.at 0 V WR.16 5 0. WR. VIH low-level input voltage. IhICS) Data bus input setup time.2OQ J. WR. tsu(D) Data bus input hold time. tsu(CS) CS hold time.005 0.400 J.01 mA ~ kSVS ~uPP/ V°ltage sensitivity. . CS at 0 V.200 2 500 UNrr ~ ~ I 1 I -- i . DBo-DB7 at VDD.28 AnIntroduction Mixed-Signal Test Measurement to IC and TLC7524C. CSatOV - 30 120 120 30 120 120 OUT2 Reference input impedance (REF to GND) . TEXAS 75285 3 Figure 2. Vil CS setup time.10 MAX 15.5 1. VDD=5V VDD=15V MIN TYP MAX 10 -10 j.C 85 4. Vref=J.400 1 500 MIN TYP MAX 10 -10 j.v ugal u DD CI Inputcapac~nc~CS DBO-DB7. OUT1and OUT2at GND(unless otherwise noted) PARAMETER IIH IlL High-level input current Low-level input current OUT1 Ilkg Output leakage current OUT2 TESTcONDmONS VI=VDD VI = 0 DBo-DB7 at 0 V. Recommended operating conditions electrical and characteristics.BITMULTIPLYING DIGITAL..10V DBa-DB7 at VDD.75 5 j. Ih(D) Pulse duration.10 13. 0. WR. 5 PF OUT1 0 T Co Output capacitance U 2 OUT1 DBa-DB7atO V. - WR. CS at 0 V. TEXAS INSTRUMENTS ~ OALLAS. Vref= :1:10 V. tw(WR\ TlC7524C Operating free-air temperature. TA TLC75241 40 0 25 10 40 0 -25 -40 70 85 85 2.4 0. TLC75241 8.

Chapter2 .DB7 atOVto VDO orVDDtoOv. 4 POST BOX .5 MIN VDD 15V = TVP MAX :to. Cext= 13 pF.5 :t2.5 100 80 ~ andCSatO V.::!(100-kHz sinewave) WR TA = 25'C to MAX :to.. UNIT LSB LSB ns ns OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER Linearityerror Gain error Settlingtime (to 1/2 LSB) Propagationdelay from digital input to goo/. operatingsequence cs i 14 tsU(CS)~ i/I' ~ th(CS) - I WR ~ j4- tw(WR) ~ ~ ('j *1 'surD) ~ L ~th(D) 080-DB7 .4.REVISEO NOVEMBER 1997 operating characteristics over recommended operating free-air temperature range. DBa-DB7 atO V = :t1!!. OBO. Electrical specifications timingdiagram. Gain error is measured using the internal feedback resistor Nominal full scale range (FSR) = Vref-1 LSB.TLC75241 8. DAllAS.001 0.BIT MULTIPLYING DIGITALTO-ANALOGCONVERTERS SLAS061B-SEPTEMBER 1986. and . 2.5 100 80 See Note 1 See Note 2 See Note 2 :t2. OUT1 k)ad = 100 '1.5 %FSR %FSR/'C NOTES: 1.of final analog output current eedth h t OUT1 OUT2 F roug a or Temperature coefficient of gain TESTCONDITtONS VDD V =5 MIN TVP MAX :to. WR atOV. CS atOV.5 :to.-.. Vref = :t10 V.004 0. TheTestSpecification Process 29 TLC7524C. 75265 OFFICE 655303 TEXAS ~ TEXAS INSTRUMENTS Figure 2.TLC7524E.

the test engineer might use the internal resistor to measure gain error while the customer uses an external resistor. not tested" or "guaranteed by design. but only as a means of formally communicating the number of DAC input bits. Nevertheless. Note I statesthat the "Gain error is measured using the internal feedback resistor. it is not necessaryto verify that the average reading for a large number of tested devices is equal to ~e TYP value. Unfortunately. it is often just the average of the MIN and MAX test limits. Sometimes the data sheet lists a parameter with a note stating that it is "guaranteed. since the gain error specification is ambiguous without it. TYP. input capacitanceis often listed as a typical specification becauseit is largely dominated by the design layout and by the device package. if Note I was missing. and MAX.4 also shows the timing diagram for the example 8-bit DAC. For example. The MIN column and MAX column represent the minimum and maximum values allowed for a passing device. At present there are few if any good automation schemesthat allow the design engineer to specify mixed-signal tests in a way that allows automatic translation into ~ debuggedtest program. The test plan must fill in the gaps as needed. and is therefore not tested in production. However. In cases such as this." This piece of information is vital. The TYP column is sometimes used to specify parameters that are guaranteed by design and/or process. The TYP column representsthe typical reading expected from a good device. Timing diagrams are critical to test program development. The mixed-signal . For example." This is a formal way to notify the customer that this specification has been characterized and shown to be good by design. These are divided into three categories: MIN. For instance. the data sheet seldom lists all possible test conditions for each measurementin complete detail. an 8-bit DAC has 8 bits of resolution by definition.. These mayor may not all be tested in production on every single device. Resolution is sometimes listed as a typical specification.30 An Introductionto Mixed-SignalIC Testand Measurement In the example in Figure 2. Since the TYP value has no guaranteedcorrelation to the devices tested. Figure 2. but that they are neverthelessguaranteedby the manufacturer to meet minimum and maximum specifications. all specifications should be tested in an extendedcharacterization version of the test program. it has much less value to the customer than the guaranteedMIN and MAX specifications. In addition to electrical characteristics. The two engineersmight waste days trying to agree upon the correct value of gain error for a particular group of DUTs. The extended test program verifies that the device design meets all of the specifications listed in the electrical characteristics section of the data sheet. On the right side of the electrical specification table are the test limits. the lack of such a notice should not be taken as a guarantee that the parameter is tested in production. Data sheet ambiguities can lead to frustrating correlation efforts. Most data books contain a notification that parametersmayor may not be tested in production. characterization data can be collect~d from many devices to prove that the parameter never fails and therefore does not need to be testedin production. The TYP column is also used to list characterization data for parametersthat are difficult or impossible to measure in a cost-effective manner. The test engineer should also suggestthat clarifications be added to the data sheet wherever serious ambiguities might causethe customer problems at a later time. If a TYP value is specified at all. For example.4. . The digital patterns used in mixed-signal tests are sometimes generated manually due to frequency synchronization issues that will become more apparent in subsequentchapters. The production test program does not generally guarantee the TYP value.

Figure 2. Like the application information section. For example.2 GENERATING THE TEST PLAN 2. then the test engineer lacks the necessary overview of the test program that allows all the tests to fit together efficiently. This particular application diagram shows the customer how to use the DAC in voltage mode rather than current mode. Characterization data mayor may not be included in a data sheet.7 shows characterization data for a low-offset JFET op amp. There are several problems with this type of undisciplined approach. it does not necessarily represent guaranteed data. However. Application information can also be helpful in the design of circuitry located on the automated test equipment's device interfaceboard (DIB). Absolute maximum ratings are not intended for production testing.2.6 also shows the absolute maximum and recommendedoperating conditions for the example 8-bit DAC. Application information is often very helpful to the test engineer. If a test plan is not clearly documented before coding begins. The functional block diagram is extremely important on complex devices since it provides a top-level representation of all the device functions in a single diagram.5 shows the application diagram for the example 8-bit DAC. the functional block diagram helps the customer (and the test engineer) understand the overall functionality of a complex mixed-signal device. 11Ie TestSpecification Process 31 test generation process is still largely manual. It is analogous to the TYP data column and is not necessarily guaranteedby the production test program. Second.1 To Plan or Not to Plan Strictly speaking. The first test may then need to be rewritten from scratch so that the clocking schemesmesh properly. Certain characterization plots such as statistical histograms may be collected using the production tester simply because it is the easiest way to generate the data.- Chapter2 . Figure 2. a clocking schemethat works well for one test may be incompatible with the clocking schemerequired for a subsequenttest. by contrast. Thus timing diagrams are still very pertinent to mixed-signal test engineers. test plans are not absolutely necessary. Test plans force the design engineers and test engineers to work through all the details of testing at an early stage in the design cycle. First. list production test conditions such as minimum and maximum supply voltage under which all test limits must be met. the test engineer may create test-to-test compatibility problems if the details of all tests are not known up front. as well as the customer. The recommendedoperating conditions are therefore quite important to the test engineer. A test engineer can certainly generate a test program by simply sitting down at the tester computer and entering code based on the device data sheet. If it is included. characterization plots are more often generated using bench equipment such as oscilloscopesand spectrum analyzers. 2. since they define the permutations of test conditions under which all the specifications must be met. Application information is often added to the data sheet to aid the customer in designing the end application. Figure 2. device testability will probably not be identified early enough to allow the addition of test featuresto the design.6 shows a functional block diagram for the example DAC. - . The recommended operating conditions. Figure 2. Often the application information helps the test engineer understand the intended application for the device or helps in designing a thorough test list. These are specified limits beyond which device damage may occur.

a fixed voltage is placed on the current output terminal. OUT2atGND. OUT1=25V. In the voltage mode.32 An Introduction to Mixed-Signal IC Test and Measurement TLC7524C.5. Eight-bit multiplying DAC:application information.TEXAS75265 TEXAS INSTRUMENTS . which is operated in voltage mode. these devices meet the following specification: PARAMETER error REF at POSTOFFICE BOX655303 OALlAS. REF(AnalogOutputVoltage) OUT1 (FixedInput Voltage) OUT2 Figure 1. . The analog output voltage is then available at the reference voltage terminal. Voltage Mode Operation The relationship between the fixed-input voltage and the analog-output voltage is given by the following equation: Vo = VI (D/256) where Vo = analog VI D =fixed input voltage =digital input code converted to decimal TESTCONDmoNS VDD=5V. TA=25°C output voltage In voltage-mode operation. Figure 1 is an example of a current-multiplying DAC. ~ 5 Figure 2.TLC75241 S-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLASOG1 B - SEPTEMBER 1986 - REVISED NOVEMBER~ APPLICATION INFORMATION voltage-mode operation It is possible to operate the current-multiplying DAC in these devices in a voltage mode.TLC7524E.

. . .TLC7524E. . . Lead temperature 1.. . .TC:FNpackage . . -0. . . .5 V Digital input voltage range. . . . . . .6. 260°C 260°C TEXAS INSTRUMENTS 2 POSTOFFK:EBOX655303 ~ .II Operatingfree-airtemperaturerange.. .. . . absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range. . . . . . . . . . . ."'. . .. The TestSpecification Process 33 TLC7524C.6 mm (1/16 inch) from case for 10 seconds: 0 or N package 0°Cto70°C -25°C to 85°C -40°Cto85"C -65°Cto150"C . . . Vref . ."""""" .REVISED NOVEMBER 1997 functional block diagram 15 REF 2R 2R 2R 2R 2R 16 R RFB R R R I -cs 13 WR 10UT1 2 OUT2 -~ ~~==f~:2 Data Latches I 3 GND 4 DB7 (MSB) \ 5 DB6 v 6 DB5 11 DBO (LSB) I Da1aInputs Terminal numbers shown are for the D or N package. ..TA: . . . 101JA TLC7524C TLC75241 TLC7524E StDragetemperaturerange. . . . . . . . . . . . . .3 V to 16. .. . . . . . .. . . . .3V Reference voltage. . . . . . . .. . TLC75241 8-BIT MULTIPLYING DIGITAl-TO-ANAlOG CONVERTERS SLAS061B-SEPTEMBER 1986. VI -0.3Vto VOD +0. .Tstg Casetemperaturefor10seconds. :1:25 V Peakdigital input current. . . DAlLAS. . . . . . . . . . . . . multiplying functional diagram absolute DAC: block and maximum ratings.Chapter2 . . TEXAS 75265 Figure Eight-bit 2. . . VOO ". . .

.- D. DALLAS. 48 POS' OffIce .DD1 100 1 k '-Frequency-Hz Figure 63 1Dk 1oak IVCCtl-SupplyVolfage-V Figure 64 .TLO5xY ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS SLOSI7a-FEBRUARY'997 TYPICAL CHARACTERISTICS TLOS1 EQUIVALENT INPUT vs FREQUENCY 100 N 5V 100 TLOS2 NDISE VOLTAGE EQUIVALENT AND vs TL054 NOISE VOLTAGE INPUT FREQUENCY l! ~70 l! ~ c70 & 5V ~ g' ~ >40 0 3 3 50 ~ .04 c i c 0 c ~ .1 3 0 .Hz IDk 100k .34 An Introductionto Mixed-Siinal IC Testand Measurement TLO5x..8 CL-25pF TA=25"C See Figure 2.9 VI=10mV RL=2k!1 2. Hz Figure 62 Figure 61 TOTAL HARMONIC vs FREQUENCY DISTORTION UNITY-GAIN TLOS1 BANDWIDTH SUPPLYV:OLTAGE 3. .TLO5xA.1 ~ I 0 .004 x . ~ 2 a I D.20.2 ~ § I ~ n I 0 D. ~ 0" W I c > 10 10 100 f 1 k Frequency 10k 100k :: § ~ 10 10 100 f 1 k - - - Frequ ency .D1 T ~ 2. . Low-offset JFET op amp: characterization data.= ~ 20 .g 0 Z 50 : 30 ~ ~ c Z ~ ~ :40 ~ = 0" W I c > ~ . TEXAS NSrRUMENTS 50X """. E n c D. 3. . . 7 D 2 4 6 8 1D 12 14 4 16 = : .. 'EXA5 7526S Figure 2.7.2 1 . GA N .

Another way to eliminate clutter is to document default conditions. This diagram looks simple. A thorough test plan includes device background information that cannot be found in the data sheet. Early identification of tester deficiencies allows the test engineer time to find acceptablework-arounds. it can sometimes be difficult to understand why a particular test is being performed.the design engineer can even modify the IC design to accommodatetester deficiencies. an amplifier's absolute gain may be specified from 0 to 10kHz. then the test plan should explain why those frequencies were chosen. Depending on the needs and tastesof the person or organization generating a test plan. product engineers.for example. For example. The primary purpose of a test plan is to serve as a roadmap for the test engineer while the test program is being generated. A hardware diagram can include as much or as little detail as needed to explain the test. a device may have test modes that are not documented in the data sheet. It is a. It would be perfectly acceptableto simply draw a triangular buffer with the label "xIO gain. Simplified block diagrams such as this are often more useful in test plan diagrams than fully detailed schematic representations. Since test plans are not generally published outside a company. it is unnecessaryto draw an entire 256-pin DUT if only three pins of the DUT are relevant to a given test. When reading another person's test program. good idea to explain some of the details of a test like this so that a new engineer does not have to spend hours researchingthe purpose and meaning of the test. If the test engineer plans to test absolute gain at only three frequencies. the test plan helps to identify shortfalls in the target tester's capabilities. they can be eliminated from the diagram for clarity.2." Likewise. The following are some suggestionsfor a well-written test plan. to show the full schematic for an op amp gain stage having a gain of 10. but it may actually representa test for a small portion of a much more complicated device. It would probably be unnecessary.Chapter 2 . Since most of the other pins of the DUT are irrelevant during this test. The Test Sp!"cification Process 35 Similarly. or does it relate to expected weaknessesin the design? It should also answer other questions: What was the input signal level? What typical level is expected from the output of the device? Are other tests like signal-to-noise ratio tested at the same time as absolute gain? Another very useful addition to a test plan is hardware setup diagrams for each test. Default conditions such as . it is also used as the official communication channel between test engineers. For example. Was it an arbitrary choice. If too much detail is included. Sometimes. It should also explain any assumptionsthe test engineer is making about a particular test. This is another example of design for test (Dff). design engineers. it might include any of a number of sections. test hardware such as DIBs and probe interface hardware cannot be properly designeduntil all test details are known.and even customers. However. they tend to be less formal and less structured than device data sheets. A test plan should explain the purpose of each test and how it relates to a data sheet specification. For example.8. Finally. The test plan is an ideal place to list all test modes and how they are utilized. 2.2 Structure of a Test Plan The structure of a mixed-signal test plan varies from one engineer to the next and from company to company. showing a test diagram for a DAC full-scale output test. Consider the simple diagram in Figure 2. a data sheet might list a parameter called error vector magnitude that is documented more completely in a separatetelecommunication standard. then the diagram becomes too cluttered to clearly explain the test conditions. The test plan is also a good place to explain special test requirements that relate to the end application of the device.

A resistance test would normally be performed by forcing current across the resistor. and applying Ohm's law to calculate resistance. but they should perhaps be set aside in a separatesubsection after the generic testerindependentdescription. If it is indeed a production specification and the test engineer has no accessto measure the parameter. In the on-chip resistor example the resistanceand its tolerance is specified only to remind the design engineer of the requirements necessary to support another parameter such as absolute gain. it may contain parameters that either cannot be tested or do not need to be tested in production. and should probably be removed from the final data sheet. which can be measureddirectly without pulling the resistor out of the gain circuit.3 Design Specifications versus Production Test Specifications Since the data sheet is initially used as a design specification.Testplanhardwaresetupdiagram. nominal power supply settings and nominal digital timing can be documented in a "defaults" section at the beginning of the test plan. Beginning test engineers sometimes agonize over how to measure an internal parameter such as this without realizing that it is only an internal design specification. Test descriptions should be documented in a tester-independent manner if possible. measuring the voltage drop. Unless otherwise specified. These internal specifications are meant for the design engineers only. Such parametersdo not necessarily need to be tested in production. these defaults are assumed to apply to all remaining test descriptions. This makes it easier for all engineering team members to understand the purpose of the test and how it should ideally be implemented. A design for test (DfI) structure might be added to the design early in the design cycle to allow the necessarytest access.8. Absolute gain of a simple op amp inverting gain stage is the result of several parameters including two resistance values.36 An Introductionto Mixed-Signal Testand Measurement IC +Full-scale code 07-00 VREF 2. If absolute gain performance is the driving force behind the resistance specification. then resistance may not be directly measurable. Consider a very simple example of an on-chip resistor specification of 100 k. if the resistor is permanently connected into the feedback path of an op amp gain stage. then something must be done to make the parameter measurable.2. it also makes it easier to convert test programs from one tester to another. there is no .Q plus or minus 10%. Testerspecific information such as digitizer sampling rates and meter range settings can be added to the test plan. However. The experienced test engineer knows to verify with the design engineer whether or not the specification is a design specification or a production specification. 2.5 V OACOUT RLOAD 1 kQ + VOUT - Figure 2. If the test plan describes each test in a tester-independent manner. The op amp gain stage will probably require an absolute gain specification.

If the device includes internal control registers. make sure that a test is defined to measure the parameter in all modes of operation. If the pennutations of modes and test conditions are too large. Perhaps the DAC has to be tested in both modes. Nevertheless.or perhaps the DAC can be tested in only one mode and a much faster digital test can be executedto verify the other mode. For example. mixed-signal circuits have an obnoxious habit of interacting with one another in unexpected ways.is sufficient. Each electrical specification should raise a series of questions. No Dff structurewould be requiredto test the resistors' valuesin production. For example.how should they be set during each test? What loading should be applied to the output pins of the device? Should an external voltage reference be supplied to the device or should an internal voltage reference be enabled? Can the device drive the capacitive load presentedby the tester instruments or will a voltage follower need to be added to the device interfacehardware? Are there important electrical specifications that have not been included in the data sheet? Asking detailed questions like this can save the test engineer many headaches later in the project. 2.4 Converting the Data Sheet into a Test Plan One of the most difficult things to teach a new test engineer is how to convert a data sheet into a correspondingtest plan. but it may operate in two different modes with threedifferent voltage ranges and two possible power supply voltages. the signal-to-noise ratio of an amplifier may change depending on the operating mode of a completely separate digital circuit on the opposite side of the die. the production test program must consist of a small subset of possible test conditions but it is difficult to define the pruning process in a scientific manner. There is really no fixed series of steps that can reliably convert a data sheet into a test plan. The Test Spec!fication Process 37 reason measurethe resistance to valuesin production. the pennutations of possible test conditions will often grow to an unrealistic test list. For each sentence in the device description and principles of operation. etc. make sure a test is defined that guarantees the device can perform the described operation. The difficulty arises from the infinite permutations of possible tests implied by the data sheet. . die temperature. This effect may worsen with varying power supply voltage setting. These details must be discussed with the design engineers andsystemsengineers. make sure there is a test that verifies both interface modes. Measuringthe important parameter. How does a test engineer know which operating modes should be tested when there are so many possiblepermutations of test conditions? Obviously. a DAC might have a particular linearity specification. For example. These so-called worst-case conditions are commonly used to prune an infinite test list down to a more manageablesubsetof critical tests. a few suggestions are listed in the following paragraphs as a starting point. then discuss the problem with the design engineers and try to identify which pennutations are likely to cause the most problems. For each electrical parameter.Chapter 2 . if the description states that a DAC can operate in either of two digital interface modes. Unfortunately.2. Unlike many digital devices. The central function of a mixed-signal test program is the measurement of each of the electrical specifications listed in the device data sheet. absolute gain in this example.

3. test limits. AC parametric tests. Tester languagesvary from low-level C routines to very sophisticated graphical user interface environments. test sequencecontrol. After considering all these questions. A thorough test program may also contain code that allows offline simulation of the tests so that certain portions of the program can be debuggedwithout a tester or device. Make sure that the innocent-looking TBD placeholder for a simple DC offset test does not become an unexpectednightmare like "offset = I pV MAX" at the last minute. the test list can be pruned down to an optimum set of tests that most efficiently probe the DUT's weaknesses. In these cases. Test programs typically consist of all or most of the following sections: waveform creation and other tester initializations. Well-written test programs often contain extensive characterization code to perform tests not specifically required by the data sheet. the test code simply calls for the tester's digital subsystem . To be safe. Major deviations should be approved by the other members of the engineering team. written in the target tester's native language. 2. the data generatedfrom the digital subsystemof a tester are not clocked out one bit at a time by the test code. These characterization tests allow the design engineersto better evaluate the quality and robustnessof the IC design. Test code typically does not control the real-time details of each instrument. After thorough characterization of many lots of production devices. a limited set of tests must be specified. though. DC parametric tests. worst-case conditions can be determined through empirical characterization of the device performance.3.3 COMPONENTSOF A TEST PROGRAM 2. some parameters may be listed as TBD (to be determined).2 Test Code and Digital Patterns Test code and digital patterns make up the bulk of mixed-signal test programs. even if the exact specification is not known. tester languages often share some basic structural components.38 An Introductionto Mixed-Signal Testand Measurement IC In the early stages of device development. In this manner. There is a huge difference in test methodology between a IOO-mV DC offset test and l-pV offset test. The initial test program has to be written so that the test list and test conditions can be easily modified. and signal measurements that make up each measurementin the test program. it may be impossible to predict what modes of operation represent worst-case test conditions. the test engineer usually specifies as many permutations as is reasonable. It may at times deviate from the test plan if the target tester is incapable of performing tests exactly as specified by the test plan. digital timing tests. Test code controls the order and timing of instrument settings. Let us take a more detailed look at some of the structural components commonly found in a mixed-signal test program. Asking for rough estimates of expected performance is a good idea. calibrations.1 Test Program Structure The test program is a detailed. digital patterns (also known as functional tests). signal generation. Despite wide differences in their details. Instead. In the end. For example. 2. continuity. and binning control.comments should be added to the program to make this discrepancy clear. tester-specific version of the test plan.

The reason for this will becomemore apparentin Chapters6 and 7." . For this reason. Drive dataspecifies the desired state at the input to the DUT (HI. Digital patterns usually contain not only the 1/0 drive and expect data. Compare DAC scale '* the full output thedatasheet to limits *' Digital patterns consist of groups of data bits called vectors. It is not acceptable to round off the period of the vector rate to the nearestnanosecond as is often done in purely digital test programs. Thus the test code for a DAC full-scale output test might look something like this in pseudocode: dac_full_scalevoltage( set VI1 = 2.dac_full~scale". The CLKI frequency would be twice that of the CLK2 frequency. pin testfsout. etc Jump START 1 /* Infinite loop *1 This pattern would continue in an infinite loop. looping. Vectors are usually sent out at a regular rate. To generate a pair of clocks at two different frequencies from digital pins CLKI and CLK2. and other vector sequencing operations that make the pattern more compact. Set the DACoutputto +full scale(2. Compare data (also called expect data) specifies the required digital output from the device.5V. The Test Specification Process 39 to begin exercising the desired digital pattern at the appropriate time. one might write the following pseudocodepattern: label START pattern control CLKl CLK2 0 /* 0 /* 1 Vector Vector one */ two. The digital pattern sequencingcommands allow branching.Chapter 2 . but also the sequencing information for the vectors. The test code and the digital pattern must operate in steppedsynchronization for mixed-signal tests. called the bit cell rate. mixed-signal testers include handshaking functions in both the test code and digital pattern control that allow the tester computer and digital pattern subsystem to keep in step with one annther. r SettheDAC's voltage reference 2.5V) *' r connectmeter:DAC_OUT Connect DACvoltmeter the DACoutput*' '* the to fsout = read_meter{ '* Readthe voltagelevelat the DAC_OUT *' }. It would be unfortunate in the DAC test above if the digital pattern "dac_full_scale" did not execute until 50 ms after the meter measurement had already been performed. Another pattern issue unique to mixed-signal testing is that the pattern often must be executed at a very precise frequency. or HIZ). producing two frequencies. "Sampling Theory" and "DSP-Based Testing. Each vector representsthe drive and expect data that are to be sent out on each of the tester's digital pins at a specific time.5volts*' to startdigitalpattern= . LOW. The digital subsystemthen takes care of the details of generating the individual ones and zeros.

Such a scattered arrangement made it difficult to identify which test limits were applied to a device in a given version of the test program. The new code module. Weare all familiar with higher prices for faster PC microprocessors and memory chips. of course. a new type of test code module evolved to allow a more convenient summary of test flow. The-120 MHz devices would be labeled differently than the 100-MHz devices. The test and product engineersshould work together to ensure that the most commonly failed tests are placed near the beginning of the test program. If a large percentage of devices fail the continuity test. different grades of packaged devices are sorted into separateplastic tubes or trays by the handler.40 2. contains the test routine function calls.3 Binning An Introduction to Mixed-SiJ{nal IC Test and Measurement One of the functions of a test program is to sort each device into one of several categories. bad die on a wafer were often squirted with red ink dots to designatethem as failures. test limits. The most obvious bins are "pass" and "fail. the order of the various tests was simply determined by the order of test routine execution. Sometimes there are different grades of passing devices. and the binning information for each test result. Comparisons of measured results against test limits were performed after each measurement. Binning is not always a pass/fail operation. Now this inking is commonly performed offline or is done in a purely virtual manner using pass/fail databases and production lot ill numbers. . depending on the outcome of the various tests." Bin 1 might representthe 120-MHz devices. This is done to prevent a bad device from wasting valuable tester time after it has already produced a failing result. called bins.3. At final test. Fast binning is a tenD used to describe a tester's ability to bin a bad device as soon as it fails any test. The sequencer code allows the programmer to order the tests and group all the test limits into a central location in the test code. then the test program might be set up to split these devices into two quality grades. called a sequencer by some vendors. This allows the tester to sort bad devices as quickly as possible. a continuity test is usually inserted at the beginning of the test program. Test limits were therefore scattered all through the test program along with the instrument setups and measurement code. In older testers. while Bin 2 might represent the devices that could only operateup to 100 MHz. and binning information. They would also be priced differently. The purpose of the continuity test is to verify that all the electrical contacts between the tester and the DUT have been successfully connected. depending on the sophistication of the tester's software enviromnent. If a device is designed to operateat 100 MHz but some of the manufactured devices are actually able to operate at 120 MHz.4 Test Sequence Control Test sequencemay be controlled in a number of ways. It is therefore a good idea to use separatebins for continuity failures and data sheet failures so that the production staff can more easily recognize tester hardware problems. As tester software environments matured.3." but there are several others that might be added. For example. this indicates a probable error in the tester hardware. 2. The tester generates a binning signal that tells the handler or prober what to do with the various categoriesof devices. "good" and "great. Until recent years. the test limits. This made it difficult to verify that the test program limits matched the data sheetlimits.

Other operations. the sequencer modules may be coded as text or they may consist of graphical interfaceobjects linked together with arrows to indicate program flow and binning decisions.5 Waveform Calculations and Other Initializations Mixed-signal test programs use many precomputed waveforms. such as once per week. A I-kHz gain test requires a sinusoidalwaveform that does not change from one program execution to the next. test order. Software calibration is discussed greater detail in Chapter 10. Digital waveforms are also precomputed and stored in the digital subsystem of the tester. Many of the required initializations such as waveform computationsare performed only once when the test program is first loaded. The test engineermust calibrate the gain and offset of the voltage follower using focused calibrations to achievemaximum accuracy. Performing these initializations only once savesa large amount of test execution time.3. especially when extreme accuracy is required in the final test Fortunately. such as resetting tester instruments to a default state. Waveforms that do not need to change are precomputed and stored either in arrays or directly into memory banksin the tester instruments themselves.6 Focused Calibrations and DIB Checkers Sometimes instrumentation a testerdoesnot havesufficientaccuracy a given test. but most testersinvolve some type of first-run initialization code. These circuits are subject to failure. Sometimesfocused calibrations can be as difficult to develop as the devicemeasurementsthemselves. 2. many software calibrations are hidden from the user in the tester's operating system.The inaccuracies the fasterinstrumentcan then be as of corrected a process in knownassoftwarecalibration. The focused calibration routine determines inaccuracyof the instrumentusing slower. must be performed eachtime the program is run. Software calibrations must also be performed on circuitry placed on the device interface board. The test program should include DIB checker code to verify the functionality of any circuitry placed on the device interface board. Depending on the tester's software environment. and other active circuits are commonly placed on the DlB to extend the tester's functionality and accuracy. . The Test Spe~ification Process 41 separatefrom the test routines themselves. If the in for not. Other calibrations are performed on a regular basis. DIB checker routines are usually run along with focused calibrations when the program is flTstloaded. This makes it easier to audit the program for compliance with data sheet test limits.Chapter 2 . and pass/fail limits for each test. more the accurate instrumentation a reference. The gain and offset of the voltage follower adds errors into any measured results." in Electromechanical relays. Assume an op amp voltage follower is placed on the DIB to buffer a weak device output. op amp circuits. "Focused Calibrations. comparators.a special routine calledafocusedcalibration is requiredwhen the programfirst runs. The details of initializations are very specific to each tester. 23. These calibrations are performed automatically when the program is first loaded. This allows production personnelto avoid running thousandsof good devices through a bad DlB before discovering the error. One major class of first-run code is focusedcalibrations and checkers. The sequencer code thus provides a convenient summaryof the test list.

test debugging often turns into design debugging. debuggability. but it would provide thorough information about the filter's gain versus frequency characteristics. and location. However.3.known as test simulationor virtual test allows true closed-loop simulationof the testeranddevice.3. More important. 2. .42 An Introduction to Mixed-Signal Testand Measurement IC 2. Thorough characterization of a new device is critical. and product engineerswork together to resolve design problems. and hardware problems including bad DIE layout and broken tester modules. Offline code debugging techniques like this area good way to reduce debug time and avoid wasting valuable tester time. One of a mixed-signal test engineer's most valuable roles is to help the design engineers isolate design problems.3.a softwaremodelof the tester stimulates model of the DUT accordingto the instructionsin the test prowam. These experiments are critical to reducing the time it takes to get the problems worked out of a new mixed-signal design. and debuggability (despite the fact that "debuggability" is not a real word). The debugging time was found to be roughly twice the time spent writing test code." 2. A study at Texas Instruments showed that the test program debugging process takes about 20% of an average test engineer's week. The a testermodel and testeroperatingsystemthen capturethe responses from the DUT model and compare them to test limits. The successor failure of a mixed-signal product often dependson how well the design engineers. It might be said of test program structure that the three most important things are debuggability. the ideal output of a DAC might be simulated and stored into an array for use by a DAC linearity calculation routine. An example of a characterization test would be a filter responsetest implemented at each frequency from 100 Hz to 10 kHz in 100-Hz increments. intermittent failures.8 Simulation Code Simulation code is sometimes added to a mixed-signal test program to allow some of the mathematical routines to be verified. "Test Economics. Design debugging activities account for a large portion of the test program debugging time. A good test engineer with a well-structured test program can quickly modify the program and run experiments for design engineers or customers. Using test simulation. For example. Test simulationis explainedin more detail in Chapter16.7 Characterization Code Characterization tests are often added tQ a test program to allow thorough evaluation of the first few lots of production material. since it allows the design engineers to identify and correct the marginal portions of the design.9 "Debuggability" It is said that the three most important things in real estateare location. Such a test would never be cost-effective in a production test program. It is also a matter of locating measurementcorrelation errors. A more advanced type of simulation. Debugging is not only a matter of finding and fIXing test code bugs. location.test engineers. such simulations are not entirely effective in uncovering errors such as incorrect DUT register settings or improper tester instrument range settings.

Sincethese tests require very simple hardware and software. The translation is not a simple one-to-oneprocess.004%? Is the distortion at this frequency guaranteedto be less than 0.and we have seenhow tabular entriesand comments a datasheettranslatefirst into a test plan and then into a test in program. What is a test plan? Is there a rigorous method to convert any given data sheet into a test plan? Do the electrical characteristics listed in the tables of a data sheet correspond oneto-one with individual DUT measurements? 2. test In Chapter 3.1.we have reviewedthe basic structureof a data sheet. At what frequency does the total harmonic distortion for a TL051 JFET op amp exceed 0. what is the maximum power dissipated by the device? If a TLC7524C draws 1. minimum. (b) List at least six types of information that can be found in a data sheet. Rather.2. When the TLC7524C is packaged in the FN package.1-2.6. experience.5.3. Problems 2. the analog DC tests.8.4-2. we will begin looking at the test development process. Our study of true mixed-signal tests. What output load resistance should be attached to the DAC output (OUTl) during the settling time test? What capacitanceshould be attached in parallel with the load resistance? 2. what will happen to the DAC output when the data signals DBO-DB7 change from 00000000 to 11111111? 2.004% on every device? . Problems 2. we will study DC tests first to gain some familiarity with the language and methodology of analog and mixed-signal testing.the process to requiresa greatdeal of thought. (c) In which section of the data sheet are the maximum. What is the ideal relationship between the output voltage and the input voltage and digital input code when the DAC is operatedin voltage mode? 2. commonsense guarantee intent of the datasheetspecifications and to the without literallyperformingmillions of possible testsin a production program.with each data sheet entry corresponding one clearly definedtest. TheTestSpecification Process 43 2. What state must be applied to the -w:R: and CS signals to allow the DAC output voltage to change according to the data at DBO-DB7? If the CS signal is high and the -w:R: signal is low. involving a mixture of analog and digital signals.Chapter2 . what device signal is attached to pin 16? What signal is attached to pin 9? What pin is connected to the positive power supply? 2.8 refer to the TLC7524C data sheet in Figures 2. Do the absolute maximum ratings need to be verified during production testing? 2. and typical specification limits listed? 2.7.4.4 SUMMARY In this chapter.9.6. starting with the defmitions of some of the most basic tests in a mixed-signal test program. will be delayeduntil later chapters so that we can first develop a fundamental understanding of issues suchas accuracy and repeatability. When the TLC7524C is powered with a 5-V supply. (a) List at least three purposes of a data sheet.5 mA from the VDDsupply. would it passthe power dissipation specification? 2.

13.O.11. Dallas. Which section of a test program tells the handler or prober whether a device is good or bad? 2. DataBook.10. P.. Can a DUT's specifications be measuredunder all possible test conditions? 2.TX 75380-9066 .Box 809066.Data AcquisitionCircuits. What is the purpose of the DIB checker section of a test program? 2.Data Conversion DSPAnalogInterfaces.44 An Introductionto Mtted-SignalIC Testand Measurement 2.Texas and Instruments.12. Inc. What is the purpose of focused calibrations? References 1.

1. Relays are used extensively in mixed-signal testing to modify the electrical connections to and from the DUT as the test program progressesfrom test to test. a socket or handlercontactor assembly provides the contact between the DUT and the DIB.1 Purpose of Continuity Testing Before a test program can evaluate the quality of a device under test (DUT).CHAPTER 3. dependingon the mechanical/electrical performance tradeoffs made by the ATE vendor. The exact connection schemevaries from tester to tester. The tester's instrumentsare connected to the DIB through one or more layers of connectors such as springloadedpogo pins or edge connectors.1 CONTINUITY 3. The field is created by a current forced through a coil of wire inside the relay (Figure 3. ATEtest headto OUTinterconnection: In addition to pogo pins and other connectors.1. A typical interconnectionscheme is shown in Figure 3. 45 .2). When packaged devices are tested. the DUT must be connectedto the ATE tester using a test fixture such as a device interface board (DIB). electromechanical relays are often used to route signals from the tester electronics to the DUT. Figure 3. A relay is an electrical switch whose position is controlled by an electromagnetic field. When testing a bare die on a wafer. the contact is made through the probe needles of a probe card.1.

thousands of good devices could be rejected simply because a pogo pin was bent or becausea relay was defective. Without continuity testing. defective connections can be a major source of tester down time on the production floor. then the production floor personnel cannot distinguish between bad lots of silicon and defective test hardware connections. We will use the term "protection diode" throughout the remainder of this book with the understanding that a more complex circuit may actually be employed. Since an SCR behavesmuch like a diode when triggered. assuming normal input and output voltage levels.2 Continuity Test Technique Continuity testing is usually perfonned by detecting the presenceof on-chip protection circuits. Any of a variety of detection circuits can be used to trigger the SCR when the protected pin's voltage exceedsa safe voltage range. / -+if~ Coil -+ ~'V~ .2./ I .-: -'iO"'O+:. :-:-::. For example. but they are triggered by a separatedetection circuit. . These circuits protect each input and output of the device from electrostatic discharge (ESD) and other excessive voltage conditions. connected as shown in Figure 3. Diodes and silicon-controlled rectifiers (SCRs) can be used to short the excess currents from the protected pin to ground or to a power tenninal. Once triggered. Qt- 0 0 I 0 0 0 0+.1.46 An Introductionto Mixed-SignalIC Testand Measurement Wiper Contact ~ . SCRs are similar to ESD protection diodes. ~ Double pole. . resulting in open circuits or shorts between electrical signals. 3. the term "protection diode" is used to describe ESD protection circuits whether they employ a simple diode or a more elaborate SCR structure. Continuity tests (also known as contact tests) are performed on a device to verify that all the electrical connections are sound. single throw (DPST) ~ I Single pole. Notice that the diodes are reverse-biasedwhen the device is powered up.3).O"'o+I I I I ~ ~ ' I I i 0 . an SCR behaveslike a forward-biased diode from the protected pin to power or ground (Figure 3. Electromechanical relays. The SCR remains in its triggered state until the excessive voltage is removed. Any of the electrical connections between a DUT and the tester can be defective. single throw (SPST) Double pole. The ESD protection cir:cuits prevent the input and output pins from exceeding a small voltage above or below the power supply voltage or ground.!. double throw (DPDT) Figure3. While interconnect problems may not pose a serious problem in a lab environment. DUT pins may be configured with either one or two protection diodes. An ESD protection diode conducts the excess ESD current to ground or power any time the pin's voltage exceeds one diode drop above (or below) the power or ground voltage. the wiper of a relay can become stuck in either the open or closed position after millions of open/close cycles.4. If continuity testing is not performed. This effectively makes them "invisible" to the DUT circuits during normal operation.

3. A dead short to ground will .7 V. To verify that each pin can be connectedto the tester without electrical shorts or open circuits. In the caseof an SCR-basedprotection circuit. the current source initially seesan open circuit. I I I OUT Single ESO diode: : : . For the purpose of illustration. Protection diodes connected to the negative supply or ground are tested by reversing the direction of the forced current. Thus the difference between a diode-based ESD protection circuit and an SCR-based circuit is hardly noticeable during a continuity test. The rising voltage soon triggers the SCR' s detection circuit. VDD Dual ESO protection . ESD protection diodes connected to the positive supplyare testedby forcing a current ICONT the pin as shown in Figure 3. The voltage drop across a good protection diode usually measuresbetween 550 and 750 mV. I : To OUT: ESO Overvoltage circuits! : protection detection I I : SCR circuit Ground pin (or power supply pin) : I I L 2 OUT Figure 3. Dual and singleprotection diodes. while too little current may not fully bias them. Becausethe current source output tries to force current into an open circuit. DC and ParametricMeasurements 47 . its output voltage rises rapidly. Too much current may damage the diodes. VCaNT. that appears at the pin with respect to ground.4. If the tester does not see the expecteddiode drops on each pin. SCR-based ESDprotection circuit. but the ideal value dependson the characteristics of the protection diodes. Once triggered. the ATE tester forces a small current across each protection diode in the forward-biased direction.5 and measUringthe into voltage.Chapter3 Protected OUT pin: : : . we shall assumethat a conducting diode has voltage drop of 0. I I I I I I I I OUTpin L ~ Figure 3. The DUT's power supply pins are set to zero volts to disable all on-chip circuits and to connectthe far end of each diode to ground. then the continuity test fails and the device is not tested further. The amount of current chosen is typically between I 00 ~A and I mA. the SCR accepts current from the current source and the voltage returns to one diode drop above ground. diodes OUT pin I I I I .

Since even a small amount of stray capacitance presents a low impedance to very high-frequency signals. if only some of the supply or ground pins are not grounded. 3. an approach known as serial continuity testing.1 : ' l Figure3. Therefore. . then continuity to some or all of the nonsupply pins will fail. using relays to break the connections to the other power and ground pins. . However. perhapsby detecting a small amount of current leaking into the pin or by detecting the presence of an on-chip component such as a capacitor or resistor. serial testing is a time-consuming and costly approach. Modern ATE testersare capable of measuring continuity on all or most pins in parallel rather than measuring the protection diode drops one at a time. Continuity to the power or ground pin can then be verified by looking for the protection diode between it and another DUT pin. Checking continuity the diodeconnected the positivesupply. Continuity to these unprotected pins must be verified by an alternative method. Continuity to these power and ground connections mayor may not be testable.6(a).5. while an open circuit will causethe tester's current source to reach a programmed clamp voltage. If all supply pins or all ground pins are not properly connected to ground. Unfortunately. the result in a reading of 0 V. One such example is a high-frequency input requiring very low parasitic capacitance. The space-chargelayer in a reverse-biasedprotection diode might add several picofarads of parasitic capacitance to a device pin. These testers accomplish parallel testing using so-called per-pin measurementinstruments as shown in Figure 3. the protection diode must sometimes be omitted to enhanceelectrical performance of the DUT. One way to test the power and ground pins individually is to connect them to ground one at a time. Many mixed-signal devices have multiple power supply and ground pins. ' I :.3 Serial versus Parallel Continuity Testing Continuity can be tested one pin at a time. I : CONT: I D cir : . Since unprotected pins are highly vulnerable to ESD damage.they are used only in special cases. : : .The otherdiodeis tested the of to by reversing directionof the forcedcurrent.48 AnIntroduction Mixed-Signal Test Measurement to IC and DUT Current protection . flow through circuit .1. ]. the others will provide a continuity path to zero volts. a device pin may not include any protection diodes at all. the unconnectedpower supply or ground pins may not be detected. Occasionally.

. . . Then~!emaining pins canbe tested during a second passwhile the previously tested pins are ground~d~~hortsbetween adjacentpins would be detected using this dual-passapproach. . . Both analog pins and digital pins must be tested for continuity. Unfortunately. : I .6. as illustrated in Figure 3. subtler problem with parallel continuity testing is related to analog measurement performance.6(b). . . . I . . . First. . . I I I . The analog pins of the tester . . L I I . On some testers the per-pin continuity test circuitry is limited to digital pins only. the net current through each diode doesnot change. . : (a) OUT circuits I . by A second. . I I . : .Parallel continuity testing: (a) full parallel testingwith possible adjacent fault masking. . I . Figure 3. a more economical approach~sto test every other pin for continuity on one test pass while grounding the remaining pins. . there are a few potential problems to consider. . . : I L OUTcircuits (b) I I I . the problem can be solved by performing a continuity test on each pin in a serial mannerat the cost of extra test time. Pin-to-pin short . Twice as much current is forced through the parallel combination of two diodes. I i . .Chapter3 . I I . . I . . resulting in both pins passing the continuity test. (b) minimizing potentialadjacent fault masking excitingeverysecondpin. DC and ParametricMeasurements 49 Clearly it is more economical to test all pins at once using many current sources and voltage meters. Obviously. . a fully parallel test of pins may not detect pin-to-pin shorts. . . If two device pins are shorted together for some reason. However. . . The shorted circuit configuration will therefore result in the expected voltage drop across each diode. . . .

respectively. the analog pins can be connected to the per-pin measurement electronics of digital pins. this is a very time-consuming serial test method. Leakage currents can cause DC offsets and other parametric shifts.\ This type of early failure is known as infant mortality. Leakage can be caused by many physical defects such as metal filaments and particulate matter that forms shorts and leakage paths between layers in the IC. These two instruments can be connected to each device pin one at a time to measure protection diode drops. or simply leakage.leakageis typically measured twice. . Also. Unlessotherwise the specifiedin the data sheet.logic low). 3. Another reason to measure leakage is that excessive leakage currents can cause improper opemtion of the customer's end application. Clearly.2.2 LeakageTest Technique Leakageis measured simply forcing a DC voltageon the input or output pin of the device by under test and measuring small currentflowing into or out of the pin. This complicates the Dill design but gives high performance with minimal test time. although this can vary from one device design to the next. the digital perpin electronics may inject noise into sensitive analog signals. continuity testing on analog pins can be performed one pin at a time using a single current source and voltmeter. which should be avoided if possible. Leakage can also be measured on output pins that are placed into a nondriving high-impedance mode. Of course.logic high) and lIL (input current. the signal trace connecting the DUT to the per-pin continuity electronics adds a complex capacitive and inductive load to the analog pin. Alternatively. a tester having per-pin continuity measurementcircuits on both analog and digital pins representsa superior solution. When a voltage is applied to a high~impedance analog or digital input pin. Thesetwo currentsare referredto as lIH (input current.50 An Introductionto Mixed-Signal Testand Measurement IC may not include per-pin continuity measurementcapability. A good design and manufacturing process should result in very low leakage currents. A third reason to test leakage is that excessive leakage currents can indicate a poorly processed device that initially appearsto be functional but which eventually fails after a few days or weeks in the customer's product. This current is called leakage current. a small amount of current will typically leak into or out of the pin. The signal trace can also behave as a parasitic radio antenna into which unwanted signals can couple into analog inputs. Typically the leakage is less than I ~. Unfortunately.2 LEAKAGE CURRENTS 3.2. This allows completely parallel testing of continuity. full parallel testing of analog pins should be treated with care. One of the main reasons to measure leakage is to detect improperly processed integrated circuits. 3. Of course. On these testers.1 Purpose of Leakage Testing Each input pin and output pin of a DUT exhibits a phenomenoncalled leakage. which may be unacceptable. It is measured oncewith an input voltagenear the positivepower supplyvoltageand againwith the input near ground(or negativesupply). One solution to the noise and parasitic loading problems is to isolate each analog pin from its per-pin continuity citcuit using a relay.

tester vendors generally design both capabilities into the per-pin measurementcircuits of the ATE tester's pin cards. like continuity. 3. Therefore. parallel testingis desired. If no particular input voltage is specified. can be testedone pin at a time (serial testing) or all pins at once (paralleltesting). VIHand VIL.5-1. By contrast.a compromise be achieved can by testingeveryotherpin in a dual-pass approach. . leakage tests are implemented by forcing DC voltage and measuring current.1 Importance of Supply Current Tests One of the fastest ways to detect a device with catastrophic defects is to measure the amount of current it draws from each of its power supplies. Supply currents are therefore very easy to measure in most cases. Supply current is an important electrical parameter the customerwho needsto design a systemthat consumes little power as for as possible.2 Test Techniques Most ATE testers are able to measurethe current flowing from each voltage source connectedto the DUT. is often measured using the per-pin resources of digital pin cards. Again.I versusParallel LeakageTesting Leakage.the main reasonto measure power supply currentis to guarantee limited power consumptionin the customer'send application. assumingthe extra per-pin circuits are not prohibitively expensive.8 result in a low-impedance path from one of the power supplies to ground.3. Analog input leakageis typically tested at specific voltage levels listed in the data sheet. then the leakage specification applies to the entire allowable input voltage range. Of course. Continuity tests are usually implemented by forcing DC current and measuring voltage. Since leakage is usually highest at one or both input voltage extremes. it is often measured at the maximum and minimum allowable input voltages.serial testing is superiorto parallel testing from a defect detectionperspective.Evendevicesthat draw largeamounts currentby design like of shoulddraw only as much power as necessary. a tester with per-pin continuity measurement circuits on both analog and digital pins represents a superior solution. DC and Parametric Measurements 51 Digital inputs are typically tested at the valid input threshold voltages. from a test time perspective. Analog leakage.2. Many gross defects such as those illustrated in Figures 1. Low power consumption especiallyimportantto manufacturers batteryoperated is of equipment cellular telephones. Since leakagecurrentscan flow from one pin to another. Since the tests are similar in nature. As in continuitytesting.Chapter 3 . Supply currents are often tested near the beginning of a test program to screen out completely defective devices quickly and cost effectively.3. 3. The power supply is simply set to the desired voltage and the current from its output is measuredusing one of the tester's ammeters.3 SeriQ.3 POWER SUPPLY CURRENTS 3. though the output pin must be placed into a highimpedance(HIZYstate using a test mode or other control mechanism. However. Output leakage (10z) is measuredin a m~er similar to input leakage.power supply current tests are performed mostif not all devices. on 3. like analog continuity.

3. Other times there are too many DUT supply pins to provide each with its own separatepower supply. The function of a voltage regulator is to provide a well-specified and constant output voltage level from a poorly specified and sometimes fluctuating input voltage. The supply currentflowing into a DUT must settleto a stablevaluebeforeit canbe measured. Figure 3. such as power-down mode.IcCA.to l2-V ranging power supply to a fixed 5-V output level. But in power-down modes.4 DC REFERENCES REGULATORS AND 3.the test program and test plan have to be updated to reflect the characterized worst-case conditions. is The chargingprocesscan take hundreds millisecondsif the currentmust stabilizewithin of microamps. This normally takes 5-10 ms in normal modesof DUT operation. Sincethe Dffi usually includesbypasscapacitors the DUT. and IccD are the terms used when analog and digital supplies are measuredseparately. it is safe to assume that the supply currents are to be tested under worst-case conditionsI The test engineer should work with the design engineers~attem~t to specify the test conditions that are likely to result in worst-case test conditions.IDDD. eachcapacitor for mustbe allowedto charge until the average currentinto or out of the capacitor stable.52 An Introduction to Mixed-Signal Testand Measurement IC When measuring supply currents. . the digital supply currents are specified separately from the analog supply currents.lF) through a relay as shown in Figure 3. Design engineers often need to know how much current is flowing into each individual power supply pin. Thesetest conditions should be spelled out clearly in the test plan so that everyone understandsthe exact conditions used during production testing. Many devices have multiple power supply pins that are connected to a common power supply in normal operation. or idle mQ~e? In general. IDD (CMOS) and Icc (bipolar) are commonly used designations for supply current. The large bypasscapacitorcan be disconnected temporarilywhile the power-down currentis measured.lF)directly to the DUT and then connecta larger capacitor(say 10 J. The output of the voltage regulator would then be used as the supply voltage for other circuits in the system.The tester and Dffi circuits must also settle to a stablevalue. Supply currents are often specified under several test conditions. IDDA. In these cases.1.7.Sometypesof bypasscapacitors may evenexhibit leakage currentgreaterthanthe currentto be measured. standby mode. Another problem that can plaguepower supply current testsis settling time. Sometimes the test engineer can accommodate this requirement by connecting each power supply pin to its own supply. In these cases. and normal operational mode.the specifiedsupplycurrentis often less than 100~.1 Voltage Regulators A voltage regulator is one of the most basic analog circuits.8 illustrates the conversion of a 6. relays can be used to temporarily connect a dedicated power supply to the pin under test. For example. In addition.1 J. A typical solutionto this problemis to connectonly a small bypass capacitor(say 0. the only difficulties arise out of ambiguities in the data sheet. are the analog outputs loaded or unloaded during the supply current test? Is digital block XYZ operating in mode A. Often the actual worst-case conditions are not known until the device has been thoroughly characterized. mode B.

1 ~F 10 ~F . Line regulation is measuredunder maximum load conditions line regulation = IOO%X~ 1 Va-NOM max{LlVI}. max{ML). . ' 1 1 . Output no-load voltage is measuredby simply connecting a voltmeter to the regulator output with no load current and measuring the output voltage Vo. '. rather than as a percentagechange in Vo. . L ' .7. .input or line regulation.Chapter3 . . is created by varying the load current from the minimum rated load current (typically 0 mA) to the maximum rated load current. The test definition will be obvious from the specification units (i. Line regulation or input regulation measuresthe ability of the regulator to maintain a steady output voltage over a range of input voltages. As the output voltage changeswith increasing load current. current settling behavior. one defines the output voltage regulation as the percentage change in the output voltage (relative to the ideal output voltage. input or ripple rejection. Some of the important parameters for a regulator are output no-load voltage.1) The largest load current change. I 1 . . line regulation is sometimes specified as an absolute voltage change rather than a percentage. and dropout voltage. Load for regulation is measuredunder minimum input voltage conditions load regulation = IOO%X~ 1 Va-NOM max {ML}' minimum VI (3. . . VO-NOM) a specified change in the load current. .I . Tester: I DIS 1 1 1 .maximumIL (3. . 1 1 1 .e. 1 . DC andParametricMeasurements 53 . . Load regulation measuresthe ability of the regulator to maintain the specified output voltage V0 under different load current conditions fL. DUT 0. .2) . : VSUPPLY: : 1 1 1 1 1 VDD ~~g~~=::= 1: 1 " Tester control : : I . Load regulation is sometimes specified as the absolute change in voltage.I Rea y I ~ . AVo. Arranging different-sized bypass capacitors to minimize power supply Voltage regulatorscan be testedusing a fairly small number of DC tests. Like the load regulation test. : . Line regulation is specified as the percentage changein the output voltage as the input line voltage changes over its largest allowable range. Figure 3. . . volts or percentage). output voltage or load regulation.

measuring the output voltage. A 9-V voltage regulator is rated to have a load regulation of 3% for a maximum load current of 15 mA. measured at a particular frequency (commonly 120 Hz) or a range of frequencies. For the regulator shown in Figure 3.3. and again measuring the output voltage to calculate ~V o. Input rejection can also be measured at DC using the input voltage range and output voltage swing measuredduring the line regulation test. . then readjusting the input voltage to 12 V. 5-V DCvoltageregulator.85 V under a 5 mA maximum rated load current.8.05 to 4. 8. but this is a time-consuming test method. What is its line regulation? ADs. Exercises 3. Dropout voltage is the lowest voltage that can be applied between the input and output pins without causing the output to drop below its specified minimum output voltage level.73 V. What is its load regulation? ADs. 3. the line regulation would be computed by first setting the input voltage to 6 V. The output is then measuredto guaranteethat it is equal to or above the minimum acceptableoutput voltage. The output of a 5-V voltage regulator varies from 5. Input rejection or ripple rejection is the ratio of the maximum input voltage variation to the output voltage swing. the input can simply be set to the specified dropout voltage plus the minimum acceptableoutput voltage.1. Assuming a no-load output voltage of 9 V.10 V under no-load condition to 4. The output of a 5-V voltage regulator varies from 5. 250 mV or 5%. It is possible to search for the exact dropout voltage by adjusting the input voltage until the output reaches its minimum acceptable voltage. 3. Dropout voltage is testedunder maximum current loading conditions. In production testing.2. The line regulation would then be computed using Eq.54 An Introductionto Mixed-Signal TestandMeasurement IC +6to+12V (Unregulated) ~ I Vo +5V (Regulated) GND Figure 3.2).8. (3. 100m V or 2%. It is a measure of the circuit's ability to reject periodic fluctuations of rectified AC voltage signals applied to the input of the regulator. what is the worst-case output voltage at the maximum load current? ADs. with the appropriate load connected to the regulator output.95 V when the input voltage is changed from 14 to 6 V under a maximum load condition of 10 mA.

This allows the test program to evaluate the quality of the DC references even if they have no explicit specifications in the data sheet. The output of on-chip voltage referencesmayor may not be accessible from the external pins of a DUT. It is common for the test engineer to request a set of test modes so that reference voltagescan be measured during production testing. DC and ParametricMeasurements 55 Voltage regulators are commonly used to supply a steady voltage while also supplying a relatively large amount of current. The most common way is to use a programmable reference circuit that can be permanently adjusted to the desired level. many of the DC voltages used in a mixed-signal device do not draw a large amount of current.9.4. DC voltage trimming can be accomplished in a variety of ways. as EEPROM bits can be rewritten if necessary. For this reason. The design and test engineers can then determine whether failures in the more complicated AC tests may be due to a simple DC voltage error in the reference circuits. Fuses are blown by forcing a controlled current across each fuse that causes it to vaporize. then this technology may offer a superior alternative to blown fuses. The desired level is programmed using fuses.4. For example. or a nonvolatile digital control mechanism such as EEPROM or flash memory bits.Chapter3 3. the reference can be experimentally adjusted using a bypass trim value rather than permanently blowing the Fuse blowing data and control \ Normal mode trim \alue Control registers Trimmable voltage reference Reference voltage Bypassmodecontrol ATEdigital interface Figure 3.9.9. . Trimmable reference circuit. a 1-V DAC reference does not need to supply 500 mA of current.3 Trimmable References Many high-performance mixed-signal devices require reference voltages that are trimmed to very exact levels by the ATE tester. One such arrangement is shown in Figure 3. If EEPROM or flash memory is added to a mixed-signal device. There are various algorithms for finding the digital value that minimizes reference voltage error.2 Voltage References . Fuses can be constructed from either metal or polysilicon. low-power voltage references are often incorporatedinto mixed-signal devices rather than high-power voltage regulators. However. In the more advanced trimming architectures such as the one in Figure 3. DC reference test modes also allow the test program to trim the internal DC referencesfor more precise device operation. 3.

In this technique. Laser trimming is more complex than trimming with fuses or nonvolatile memory. It requires special production equipment linked to the ATE tester. a device that was correctly trimmed during the wafer probing process may not remain correctly trimmed after it has been encapsulatedin plastic. the bypass trim value is disabled and the programmed fuses are used to control the voltage reference. In this example. wafer probers are designed with this requirement in mind. In general.56 An Introductionto Mixed-Signal Testand Measurement IC fuses. As the discussion in this chapter is restricted to DC. Input impedance is a fairly simple measurement to make. They include a black hood or other mechanism to shield bare die from light sources. polysilicon fuses and EEPROM bits can be blown either before or after the device is packaged. they too are usually trimmed during the wafer probing process. if it behavesaccording to Ohm's law). Of course.. it can place slight mechanical forces on the die. This in turn introduces DC offsets. during nonnal operation. the fuses are pennanently blown to set the desired trim value. Because of these DC shifts. Input i-v characteristic curves for (a) linear impedance and (b) nonlinear impedance. The resistance value in turn adjusts the DC level of the voltage reference. Then. impedance and resistancerefer to the same quantity at DC. bypass mode control.1 Input Impedance Input impedance (ZIN). When plastic is injected around the silicon die.5. The laser trimming technique can also be used to trim gains and offsets of analog circuits. Trimming can also be accomplished using a laser trimming technique.e. Since light shining on a bare die introduces photoelectric DC offsets. make no contribution to impedance. inductors and capacitors have zero reactance. There is an important advantageto trimming DC levels after the device has been packaged.10. By contrast. a bare die must be trimmed in total darkness. is a common specification for analog inputs. impedance refers to the behavior of both resistive and reactive (capacitive or inductive) components in the circuit. also referred to as input resistance. Hence. . Once the best trim value has been detennined by experimental trials. 3. Since metal fuses can produce a conductive sputter when they vaporize. Laser trimming must be perfonned while the silicon wafer is still exposed to open air during the probing process. the bypass trim value is enabled using a special test mode control signal. If the input voltage is a linear function of the input current (i. a laser is used to cut through a portion of an on-chip resistor to increase its resistance to the desired value.5 IMPEDANCE MEASUREMENTS 3. Another potential DC shift problem relates to the photoelectric effect. and as such. then one simply forces a v v (a) (b) Figure 3.

Input impedance test setup. one measuresthe change in the input current (t:J) that results from a change in the input voltage (Af') and computes the input impedance using ZIN =M AV (3. Instead.l0(a) illustrates the input i-v relationship of a device satisfying Ohm's law.11. one cannot use Eq.3) to compute the input impedance. the i-v characteristic of an input pin is a straight line but does not pass through the origin as shown in Figure 3. Input impedanceis again calculated using Eq.4). another approach is needed. Here we see that the i-v characteristic is a straight line passing through the origin with a slope equal to ZIN-I.1 In the input impedance test setup shown in Figure 3. In casessuch as these.11 or the input impedance is terminated with an unknown voltage source otherthan ground. Example 3. I I I I I . Such situations typically arise from biasing considerations where the input terminal of a device is biased by a constant current source such as that shown in Figure 3. (3. In many instances.and computes input impedance a the according to ZIN = -V I (3. or vice versa. OUT : I I I : I OUT: RIN I BIAS circuit: I I I I I I I I I I ~ ~ Figure 3.021 mA.Chapter3 .3) Figure 3.10(b). : . The alternative method is to force two controlled currents and measurethe resulting voltage difference.4) If the input impedance is so low that it would cause excessive currents to flow into the pin. as it will not lead correctly to the slope of the i-v characteristic. Then SRCI is set to 1 V and the input currentis measuredagain at 0. (3.055 mA.11. This is often referred to as a force-current/measurevoltagemethod. DC and ParametricMeasurements 57 voltageV andmeasures currentI. What is the input impedance? VDD Tester fIN ~ ---r . voltage source SRC1 is set to 2 V and current flowing into the pin is measuredat 0.

1. Example 3. The test engineer should beware of saturating the input of the device with excessivevoltages. in caseswhere the output impedance is very high. . For this reason. However. (3." is calculated using Eq.2 In the output impedance test setup shown in Figure 3. 3.41k. which is a combination of RlN and the input impedance of the block labeled "DUT Circuit. We could just as easily have used 2.58 Solution: An Introductionto Mixed-Signal Testand Measurement IC Input impedance. Large changes in voltages and currents are easier to measure than small ones. I L I I : . The device data sheet should list the acceptable range of input voltages. Saturation could lead to extra input current resulting in an inaccurate impedance measurement. the easier it is to make an accurate measurement of current change.61 V. What is the total output impedance (ROUTplus the amplifier's output impedance)? . However.Q 0.25 and 1. .4) as follows Z IN = 2V-1V =29.12. I I OUT . the values of the excitation consisting of2 and 1 V are somewhat irrelevant. the forced-current measurementtechnique is reserved for low values of resistance. ZlN. yielding 1.75 V.2 Output Impedance Output impedance (ZOUT) measured in the same way as input impedance. though. However.12. current source SRCI is set to 10 mA and the voltage at the pin is measured. In Example 3. . It is typically much is lower than input impedance.050 and 0. This is true throughout many types of tests.5. Then SRC1 is set to -10 mA and the output voltage is measured at 1.021 mA Note that the impedance could also have been measured by forcing 0.42 V. : . I : : . so it is usually measured using a force-current/measure-voltage technique.020 mA and measuring the voltage difference.055 mA-0. . Output impedance test setup. the unpredictable value of ISlAScould cause the input voltage to swing beyond the DUT's supply rails. it may be measured using the force-voltage/measure-currentmethod instead. . I : I : I Tester RC1 fIN Vo : . the larger the difference in voltage. ' Figure 3.

(3. I I I I : . test Solution: The output impedance is found using Eq. Differential outputimpedance setup.5Q OUT 10 mA-(-lO mA) 3.61 V -1. DC and ParametricMeasurements 59 Using Eq.4) to be Z OUT =201mV-(-199mV)=10Q 20 mA-(-20 mA) . and the output voltage is measured at -199 mY. SRC2 is set to -10 mA and the differential voltage at the pins is measured at 201m V..4) with ZINreplaced by Zour. SRC2 is set to 10 mA. Then SRC1 is set to -10 mA.13. (3. Example 3.42 V =9.3 In the differential output impedance test setup shown in Figure 3.--I --R-.5. Example 3.] i I Tester SRC1 [IN] Vo i : : : I I SE to conve .3 illustrates this approach. . L ~ 'RC2 ' [IN] Figure 3.3 Differential Impedance Measurements Differential impedance is measured by forcing two differential voltages and measuring the differential current change. What is the differential output impedance? ~ ~ [---O-UT-. Differential input impedance would be measuredin a similar manner. we write Z = 1..Chapter3 Solution: .13 current source SRC1 is set to 10 mA.

VMID= 0 V. This is an unfortunate choice of terminology from a test engineering standpoint. j DUT c==:> OUT . In this textbook. Several integrated circuit design textbooks refer to this type of VMID reference voltage as analog ground. In fact.6 DC OFFSET MEASUREMENTS 3.5 V. and an internally generated VMID of 1. in a single-supply circuit having a VDDof 3 V.6. and Vss= -1. To simplify the task of circuit analysis. which we will refer to as VMID.15. we can translate our singlesupply circuit into a more familiar bipolar configuration with VDD= + 1. Vss. Using this definition of 0 V. we will use the term analog ground to refer to a quiet 0 V voltage for use by analog circuits and the term VMIDto refer to an analog reference voltage (typically generatedon-chip) that servesas the IC's analog "ground.5V Figure 3. +3. we can redefine all voltages relative to the VMIDnode.5V) Vss -1. but they could just as easily be replaced by current~ . In some cases.2 DC Transfer Characteristics (Gain and Offset) The input-output DC transfer characteristic for an ideal amplifier is shown in Figure 3. we can define any circuit node to be 0 V and measure all other voltages relative to this node." 3.5 V (Figure 3.6. the term "ground" has a definite meaning when working with measurementequipment since it is actually tied to earth ground for safety reasons. \ DUT VIN : I VIN : I : : ~ OUT : : ~ VMID (1. This reference voltage.14. Therefore.0 V VDD +1. since it serves as the ground reference in single-supply analog circuits. VMID may be generated offchip and supplied as an input voltage to the DUT.35 V.60 An Introductionto Mixed-Signal Testand Measurement IC 3. The input-output variables of interest are voltage. a Vss connected to ground.14).may be placed halfway between VDDand ground or it may be placed at some other fIXed voltage such as 1.1 VMIDand Analog Ground Many analog and mixed-signal integrated circuits are designed to operate on a single power supply voltage (VDD and ground) rather than a more familiar bipolar supply (VDD. Redefining VMID 0 V to simplify as circuit analysis. and ground). Analog ground is a term used in the test and measurementindustry to refer to a high-quality ground that is separatedfrom the noisy ground connected to the DUT's digital circuits.5 V. Often these single-supply circuits generate their own low-impedance voltage between VDDand ground that serves as a reference voltage for the analog circuits.5 V VDD .

The output of the filter is measuredusing a DC voltmeter. Output offset is depicted in Figure 3. As long as the output is not noisy and there are no AC signal components riding on the DC level. . It may be necessaryto add a buffer amplifier to the DIB to provide isolation between the DUT output and the tester's instruments. ATE testersusually have a low-pass filter built into their DC meter for such applications.3 Output Offset Voltage (Va) The output offset (V0) of a circuit is simply the difference between its ideal DC output and its actual DC output when the input is set to some fixed reference value.15 and label it "Typical. Some op amps will become unstable and break into oscillations if their outputs are loaded with the stray capacitance of the tester's meter and its connections to the DUT. The design engineer and test engineer should evaluate the possible effects of the tester's stray capacitanceon each DUT output. In this section we shall describethe method to measure offset voltages (which is equally applicable to current signals as well) and the next section will describe several methods used to obtain amplifier gain. output offset is a trivial test.6.Chapter3 .15 for an input reference value of 0 V.15. The second method of reducing the effects of noise is to collect multiple readings from the DC meter and then mathematically averagethe results. If the signal is excessively noisy. in signals. DC and ParametricMeasurements 61 Typical Ideal Outp offs I I Input-referred offset Figure 3. An ATE meter may add as much as 200 pF of loading on the output of the DUT depending on the connection scheme chosenby the test engineer. Amplifierinput-output transfercharacteristics its linearregion. the DC signal can be filtered using a low-pass filter. As the real world is rarely accommodating to IC and system design engineers. To illustrate the point. Of particular interest to the test engineer are the gain and offset voltages shown in the figure." In order to maintain correct system operation. 3. normally analog ground or VMJD. design engineers require some assurancethat the amplifier transfer characteristic is within acceptabletolerance limits. First. we superimpose another curve on the plot in Figure 3. The low-pass filter can be bypassed during less demandingmeasurementsin order to minimize the overall settling time. the noise component must be removed from the DC level in one of two ways.the actual transfer characteristic for the amplifier would deviate somewhat from the ideal or expected curve. This is equivalent to a software low-pass filter. Sometimes sensitive DUT outputs can be affected by the ATE tester's parasitic loading.

. .O. . The output common-mode voltage VCM0 is defined as the average voltage level at the two outputs of a differential circuit. The DC meter in this example has an input impedance R/N of 1 MQ. The two outputs of the circuit arelabeledOUTP andOUTN.16 where the DUT is assumed to have an output impedance ROUTof 100 k. ! Shielded or R1N VMEAS \ OUT ' coaxi~1 connection Figure 3.. . we shall use V0 to denote the output offset for both the single-ended and differential case. . A 1.1 % is introduced into this measurement. Tester : : OUT: circuit: .5-V reference voltage VMIDis appliedto the input of . According to the voltage divider principle with two resistors in series.091 may be necessary to Va or 9. Commonmode offset VO-CMis the difference between the output common-mode voltage and the ideal value under specified input conditions. Consider the circuit in Figure 3. A unity gain buffer amplifier provide better isolation between the DUT and tester instrument. 1 =0. . Usually these two quantities are the same and are specified on the data sheet. 3.62 An Introduction to Mixed-Signal IC Test and Measurement .4 Single-Ended.1MQ + 100k. the voltage that appears across the meter VMEAS with respect to the output V0 of the DUT is ~ MEAS - RJN RJN + RoUT v: 0 . and Common-Mode Offsets Single-ended output offsets are measured relative to some ideal or expected voltage level when the input is set to some specified reference level. . : I ! : .Meter impedance loading.6.16.17. . The input impedance of the tester can also shift DC levels when very high-impedance circuit nodes are tested.909Va It is readily apparent that a relative error of relative error = v:a -~ MEAS = (1-0909) . . It should be clear from the context which offset is being referred to.4 Consider the single-ended to differential converter shown in Figure 3. Differential. . : . Example 3. Differential offset is the difference between two outputs of a differential circuit when the input is set to a stated reference level.O. For simplicity sake. a 1 MQ v: - =0.

VCM-O= (Vp+ VN)/2 = 1.VM/D -3 mV = differential offset.the input of the DUT should be connected to the VMID voltage. compute the differential and common= mode offsets. producing the following two readings: Vp=1. respectively. Solution: OUTP single-ended offset voltage. if it is possible to do so and the output offsets are then specified relative to the VMIDvoltage rather than the ideal value. DC offset errors causedby the single-ended to differential converter can be distinguished from errors in the VMID referencevoltage.50 V.502 V Common-mode offset. This extra information may prove to be very useful to design engineers who must decidewhat needsto be corrected in the design.Differential outputoffsettest setup. VO-N=VN.507Vand VN=1. Any errors in the VMID voltage are evaluated using a separate VMID DC voltage test. Thus the inputs and outputs are treated as if VMID was exactly correct.VMID +7 mV = OUTN single-ended offset voltage.VN=+lO mV Output common-mode voltage.497V With an expectedoutput reference level of VMID 1. In this manner.5V SE to OIFF converter VN Figure 3. the outputs should both produce VMID.The voltages at OUTP and OUTN denoted Vp and VN. Vo= Vp. the circuit and ideally. VO-CM= VCM-O-VMID 2 mV = In the preceding example.Chapter3 . .17. VMID is provided to the device from a highly accurate external voltage source. DC andParametricMeasurements 63 : Tester OUT : OUTP Vp RC1 VIN= Tester 1. Vo-p = Vp . are measured with a meter. But what happens when the VMID reference is generated from an on-chip referencecircuit which itself has a DC offset? Typically there is a separatespecification for the VMID voltage in such cases.

5) If an amplifier has a gain of 10 V N and its output has an output offset of 100 mV.Q is to measure the DC output of an amplifier witb an output impedance of 500 k. What is the expected relative error made by this measurement? Ans.7. it is not uncommon to find the amplifer in a saturated state when measuring the output offset voltage. A differential amplifier has an output OUTP of 3. 0. Exercises 3. Eq.8. It is common in the literature to find Vos defmed as the output offset V0 divided by the measuredgain G of the circuit Vas=~ G (3. 0. (3.627 V. . 5 V (output). +0.5 V (input). What are the single-ended and differential offsets? The common-mode offset? Ans. What is the input offset voltage? Ans.6%.6. For a xlO amplifier characterized by VOUT 10V/N 5. then Vos= -10m V.5.477 V (input). 3. what are its input and output = + offset voltages? Ans. 3. In high-gain circuits. then its input offset voltage is 10m V. 5 V (output). that is. such as an open-loop op amp.4. 3.Q.2 V.3 V and an output OUTN of 2.5) are derived from the circuit in its linear region of op~ration.5 Input Offset Voltage (Vas) Input offset voltage (Vos) refers to the negative of the voltage that must be applied to the input of a circuit in order to restore the output voltage to a desired reference level.5) is not applicable. A perfectly linear amplifier has a measured gain of 5.V/N2 5 over a 10-V range.3 V and-o. This will always be true provide the values used in Eq. an amplifier requires a +10 mV input to be applied to its input to force the output If level to analog ground.8 V with its input set to a VMID reference level of 3 V. -0.6.64 An Introductionto Mixed-Signal Testand Measurement IC 3. 50 mV (CM). analog ground or VMID.5 V (DIFF).2V (SE). For a xlO amplifier characterizedby VOUT 10V/N. A voltmeter with an input impedance of 100 k. (3. As such. what is = + its input and output offset voltages? Ans. 3. 16.1 VN and an output offset of -3. +0.

as false gain values are often obtained when the amplifier is unknowingly driven into saturation by poorly chosen input levels.111111111111111111111.47 V =-10.1 Closed-Loop Gain Closed-loop DC gain is one of the simplest measurementsto make.5 I . Gain can also be expressedin decibels (dB).2 V/V 1.15. We refer to this gain as closed-loop as it typically contrived from a set of electronic devices configured in a negative feedbackloop.51 V-0. Both the input and output levels are referenced to an int~ally generat~d voltage VMIDof 1.5) as G=2.6) DC gain is measuredusing two DC input levels that fall inside the linear region of the amplifier. as the input-output signals are roughly comparable in level.4V-1. is defined as the slope of the amplifier input-output transfer characteristic. (3. Then SRC11s set to 1.7) The logarithm function in Eq . as illustrated in Figure 3. DC and ParametricMeasurements 65 3.21 20. It is computed by simply dividing the change in output level of the amplifier or circuit by the change in its input G =~ AV. The conversion from volt-per-volt to decibels is simply G(dB) = 2010gloIG(V/V)I (3.6V or. Chapter 3 . in terms of decibels G = 2010g1o 1-10.47 V is measured.7) is a base-1 log as opposed to a natural log. 0 Example 3.6 V and an output voltage of 0. S~C 1 is set to 1.18.4 V and an output voltage of2.5 V. denoted G. What is the DC gain of this amplifier in VN? What is the gain in decibels? Solution: The gain of the amplifier is computed using Eq. This latter point is particularly important.51 V IS measuredWith a voltmeter.7. (3.' An amplifier with an expected gain of -10 VN is shown in Figure 3. The range of linear operation should be included in the test plan.172 dB = --- .7 DC GAIN MEASUREMENTS 3. Closed-loop gain.(3..

SRC1 is set to 1. measurementis basically the same. . This results in a differential input of 200 mY. The differential output voltage is thus -2.-- A fully differential amplifier with an expected gain of+10 VN is shown in Figure 3.52 V is measured at OUTN. Then SRC1 is set to 1. . . Va x10 amplifier on-chip) (V MID generated Figure 3. .53 V is measured at OUTP and an output voltage of 0.48 V is measured at OUTN. This results in a differential output of 2.19. compute the differential gain of this circuit. Using the measured data provided. This results in a differential input level of -200 mY. : : :VOUT Tester : .6 - . .6 V. Gain may also be specified for circuits with differential inputs and/or outputs. ~ -Differential x10 amplifier VN Figure 3.05 V. Tester : INN' . Differential amplifier x10 gaintest setup.4 V.18. DUT 10 kn .6 V and SRC2 is set to 1. . Tester Vp . .49 V is measured at OUTP and an output voltage of 2. . . A x10 amplifier gain test setup. An output voltage of 2. . .66 An Introductionto Mixed-Signal TestandMeasurement IC Tester: VIN' : .19. The Example 3.4 V and SRC2 is set to 1. An output voltage of 0. DUT : OUTP . .03 V. . .

1 V appear at the output of a single-ended amplifier when an input of 1. 3.05V-2.5) to be G= 2. respectively. What is the amplifier output for a 2-V input? Similarly for a 3-V input? What is the correspondinggain of this amplifier in VN over the I-V swing? What is the gain in decibels? ADS.Chapter3 Solution: . An amplifier is characterizedby Vour= 2. 10. DC and ParametricMeasurements 67 The differential gain is found using Eq. What is the amplifier output for a 2-V input? Similarly for a 3-V input? What is the corresponding gain of this amplifier in V N over the I-V swing? What is the gain in decibels?Would a 4-V input representa valid test point? ADS. +3. If this level of error is unacceptable. the use of a differential voltmeter is the preferred technique in production test programs. a differential voltmeter can be used to directly measure differential voltages.5 V/N+ 0. 8. Therefore.4 and 1.7 V.5 VN. Alternatively. Exercises 3.05 V -2.03 V ~-~ where VI and V2are the actual input voltages measuredusing a differential voltmeter.5 V.5 VIN+ lover an output voltage range of 0 to 10 V. +2.6 V is applied. it may be necessaryto measurethe input voltages as well as the output voltages.6 V. What is the gain of the amplifier in V N? What is the gain in decibels? ADS. 3.-16. In casesrequiring extreme accuracy.35 dB. 7.2 V/V 200 mV -( -200 mY) Differential measurements can be made by measuring each of the two output voltages individually and then computing the difference mathematically.then it may be necessaryto use the tester's high-accuracy voltmeter to measure the exact input voltage levels rather than trusting the sourcesto produce the desired values.03 V =+10. 24. Sometimes the differential voltage is very small compared to the DC offset of the two DUT outputs. Obviously the differential voltmeter approachwill work faster than making two separatemeasurements.5 VN.11. . 11. Voltages of 0. A differential voltmeter can often give more accuratereadings in these cases.25 V1N2 over an output voltage +1 range of 0 to 12 V. An amplifier is characterized by Vour= 2.96 dB. The gain equation in the previous example would then be G= 2.75 VN. (3. The DC voltage sources in most ATE testers are well calibrated and stableenough to provide a voltage error no greater than 1 mV in most cases. No -the output would exceed 12 V.48 dB.8 and 4.75 V.10.9.

68 An Introductionto Mixed-Signal Testand Measurement IC The astute reader may have noticed that the gain and impedance measurements are fairly similar.V. Since the gain around the loop is extremely large. they do not depend on any value for the offsets. non-grounded for single-supply op amps) and VSRCl the programmed DC voltage from SRC1. By doing so. are normally chosen to be around 100 k. RLOAD provides the specified load resistancefor the Goltest.UT . Since many op amps have input-referred offsets ranging over several millivolts. Subsequently. the signal that is fed back to the input of the DUT amplifier denoted V/N-DUT directly related to the nulling amplifier output VO-NULL is according to VIN-DUT V. The nulling is amplifier and its feedback loop compensatefor the input-referred offset of the DUT amplifier. it is difficult to measureopen-loop gain with the straightforward techniques of the previous examples. feedback capacitor C is necessaryto stabilize the loop. the output of the op amp under test can be forced to a desired output level according to VO-DUT 2V . The second amplifier is known as a nulling amplifier. only that the appropriate slope is obtained from the linear region of the transfer characteristic. (3. (3.V = MID SRCI (3. Under steady-stateconditions.9) to be given by = ilVO-DUT=_ ( ilV IN-DUT Goi ~ ~ ) ilVSRCl (3. Since many op amps have Gol values of 10. in that they both involve calculating a slope from a DC transfer characteristic pertaining to the DUT. A capacitance value of 1 to 10 nF is usually sufficient.8) where VMIDis a DC reference point (grounded in the caseof dual-supply op amps. The two matched resistors. It is defined as the gain of the amplifier with no feedback path from output to input.Q as a compromise between source loading and op amp bias induced offsets. respectively. 3. We can overcome this problem using a secondop amp connectedin a feedback path as shown in Figure 3. then an input-referred offset of only 500 ~V will causethe amplifier output to saturate.8). It is difficult to apply a voltage directly to the input of an open loop op amp without causing it to saturate.UT = ~(V = O-NUU VMID) - (3.20.7. For example.6). forcing the output to one power supply rail or the other. together with the DUT op amp.10) ilVO-NUU . if the maximum output level from an op amp is :i:5 V and its open-loop gain is equal to 10.000 VN or more. Moreover.the open-loop voltage gain of the DUT amplifier is found from Eqs. This ensuresthat the DUT output does not saturatedue to its own input-referred offset.2 Open-Loop Gain Open-loop gain (abbreviated GoOis a basic parameter of op amps. and (3. The nulling amplifier forces its differential input voltage to zero through a negative feedback loop formed'by resistor string Rz and RI.000 V N . we cannot predict what input voltage range will result in unsaturatedoutput levels. R3. This loop is also known as a servo loopz.9) R1+~ where V +DUT and V-DUTarethe positive and negative inputs to the DUT amplifier.

20 with R)=IOO . very large gains can be measured without measuring tiny voltages. together with VMID to a value midway between the two power supply levels (its set actualvalue is not important as all signals will be referenced to it).20. -- For the nulling amplifier setup shown in Figure 3. 2 1 0/ (3. In this manner.005 V is measured at the nulling amplifier output.20. R2=100 ill and R3=100ill. labeledas R3. DC and ParametricMeasurements 69 Tester Tester VMID VO-NUU Figure 3.020 V is measured at the nulling amplifier output.0. First the change or swing in the nulling amplifier output dV O-NULL computed is dVO-NUU =2.015 V . it is a good idea to set the voltage divider ratio to a value approximately equal to the inverse of the expected open-loop gain of the DUT op amp RI ~:::G 1 from which we can write~ ::: Go/RI. The nulling loop method allows the test engineer to force two desired outputs and then indirectly measurethe tiny inputs that causedthose two outputs. Of course the accuracy of this approach dependson accurately knowing the values of R) and R2.005 V -4. SRCI is set to VMID V and a voltage of VMID+4. 7 - . and avoid saturating the nulling amplifer.11) Example 3. What is -1 the open-loop gain of the amplifier? I ~olution: i Open loop gain is calculated using the following procedure. SRCI is set to VMID+1 V and a voltage of VMID+ 2. Open-loop gain test setupusingnullingamplifier.020 V =-2.. In order to maximize the signal handling capability of the test setup shown in Figure 3.Chapter3 . and on matching the two resistors.

What is the input offset of the DUT amplifier? Ans. and the DUT op amp having an open-loop gain of 4. 21. For the nulling amplifier setup shown in Figure 3. it would obviously not be able to produce the 20-V swing. which forces L\VO-DUT -2 V.20 with R)=IOO .13. be used to compute the input-referred offset of the DUT.12. R2=500 ill and R3=100k. 3. In the example..013 mV Making use of the fact that L\V SRCI 2 V. VOS-DUT.5 mY.. (3. using Eq. 435. 1.9) the voltage swing at the input of the DUT amplifier. . if a 5-V op amp were used as the nulling amplifier.0.2 VN. denoted VO-NULL-Offset.. What is the open-loop gain in VN of the DUT amplifier? What is the gain in decibels? Ans.. the nulling amplifier should have produced two voltages centered around VMID. and R3=100ill. the offset that appearsat the output of the nulling amplifier. For the nulling amplifier setup shown in Figure 3. can Exercises 3. . In fact.015V) 100+ lOOk = -2. R2=100 ill.013 mV If the op amp in the preceding example had an open-loop gain closer to 100 V N instead of 1000 V N .'111 then.5 V IV L\VIN-DUT -2. an SRC1 voltage swing of 1 V results in a 2. Hence. A detailed circuit analysis reveals that this offset is caused exclusively by the inputreferred offset of the DUT. R2=100 ill. the open-loop gain of is = the amplifier is found to be Got = L\V O-DUT = -2 V = 993. and R3=100 ill.77 dB. 52.25 V. L\V1N-DUT.3-V swing at the output of the nulling amplifier. Instead.0.calculated is L\VIN-DUT =~L\VO-NUU =-~(-2. it had an average or common-mode offset level of approximately 3 V from this value.175 V + VMID appearsat the output of the nulling op amp when the SRC1 voltage is set to VMID.14. what is the output swing of the nulling amplifier when the SRC1 voltage swings by 1 V? Ans.70 An Introductionto Mixed-Signal TestandMeasurement IC ..20 with R)=l ill. The nulling amplifier would have been dangerously close to clipping against its output voltage rails (assuming ::!:15-Vpower supplies). then the output of the nulling amplifier would have produced a voltage swing of 20 V instead of 2 V. 3.o.000 VN. For the nulling amplifier setup shown in Figure 3. an offset of2.20 with R)=IOO .

4993 V.=~ ~J-: PS" v.8. For the parameters and measurement values described in Example 3.po~itive power supply (VDD) is being changed by SRC1. The power supply is set to 3. the input-referred offset voltage for the DUT is J-: OS-DUT = 100 4. PSS is defined as the change in the output over the change in either power supply voltage with the input held constant ~J-: PSS+=~ ~V I and PSS. constant '0 ~V I .1 V-2.21 is connected to its own VMID source forcing 1.1 V and a voltage of 1.-.0 mV 4 (313) ~ 3.9 V and the output measurement changes 1.5011 V is measured at the output of the amplifier.8 DC POWER SUPPLY REJECTION RATIO 3. Chapter3 ~ .8 I The input of the x10 amplifier in Figure 3.92 3.020 V +2. PSS is a type of gain test in which the input is one of the power supply levels. Nonnally it is specified separatelywith respect to the positive or negative power supply voltagesand denoted PSS+and PSS-. constant In In effect.4993 V = 9 mV/V=-40.9 V dB ~ .5011 ~VSRCI V-l.005 V 100+100k 2 ( ) =3. What is the PSS of the amplifier in VN? What is the PSS in decibels? to Solution: As t.12) As this method involves the same measured data used to compute the open-loop gain. Example 3.1 DC Power Supply Sensitivity Power supply sensitivity (PSS) is a measure of the circuit's dependenceon a constant supply voltage. The power supply voltage is then changed to 2.V. it is a commonly used method to detennine the op amp input-referred offset.h~.5 V.7. the positive power supply sensitivity IS I - PSS+=~=1. PS. DC and ParametricMeasurements 71 Input-referredoffset would then be calculated using J-: OS-DUT -~ R1 J-: O-NULL-Offset (3.

1 CMRR ofOp Amps Common-mode rejection ratio (CMRR) is a measurement of a differential circuit's ability to reject a common-mode signal VCMat its inputs. the DC gain of this same circuit was found to be -10.2 DC Power Supply Rejection Ratio Power supply rejection ratio (PSRR) is defined as the power supply sensitivity of a circuit divided by the magnitude of the closed-loop gain of the circuit in its normal mode of operation.21.9 DC COMMON-MoDE REJECTION RATIO 3.9. we write PSS+ PSSPSRR+ =TGr and PSRR.2 VN =882 . . Mathematically. .8.72 An Introductionto Mixed-Signal IC'Test andMeasurement RC1 VDD ~-~~ ! : . we found PSS+=0.5. Tester VMI (on-chip x10 amplifier VMID) : : I I I ~ 0 .uv/V Power supply rejection ratio is often converted into decibel units PSRR+IdB= 20 loglo (882 .09 dB 3. Figure 3. .8. 3. In Example 3.14) In Example 3. It is defined as the magnitude of the commonmode gain GCM divided by the differential gain GD.=TGr (3. Tester VIN : .uV IV) = -61. Hence the PSRR+would be PSRR+=~ IGI =0. Normally it is specified separately with respect to each power supply voltage.2 VN.009VN.009VN 10. Power supply sensitivity test setup. givenby .

501 V is measuredat the output of the op amp. as follows dV CMRR= ~ dV CM = dV v. (3. detailed circuit RF Tester R I IN - r .Op ampCMRRtest setup.498V.Chapter3 .22. Then SRCI is changedto 0.5). What is the CMRR of the op amp? Solution: As the measurementwas made at the output of the circuit. I I : I I I Va : I I ~ I VMJD : . DC and ParametricMeasurements 73 CMRR=I~ (3.16) The rightmost expression suggests the simplest procedure to measure CMRR.5 V and an is input common-mode voltage of2.2. As in Section 3. VMID set to 1. One can measure dVos directly or indirectly.5 V is applied using SRCI. ~~ I : I I . I I I I : Op amp (on-chip VMID) Figure3..15) This expression can be further simplified by substituting for the common-mode gain GCM= dV0/ dV CM' together with the definition for input-referred offset voltage defined in Eq.22 shows a simple CMRR test fixture for an op amp. This requires a few steps: The first is to find the influence of the op amp input-referred offset voltage Vas on the test circuit output. D G =~dV I GD dVCM dVCM I (3.9 Figure 3. we need to infer from these results the dVos for the op amp. as the following two examples illustrate. I OUT : I I Tester :VOUT RC1 VSRCI : : RF VMID . Example3. .7. one simply measuresdVos subject to a change in the input common-mode level dV CM. The test circuit is basically a difference-amplifier configuration with the two inputs tied together.5 V and the output changesto 1.. An output voltage of 1.

0.Op ampCMRRtest setupusingnullingamplifier. .18) LlVSRCI Tester Tester I RC1 : I I OUT: V SRCI I I L VO-NULL R2 Figure 3. which we shall denote as VO-NUU.5 LlVo. substituting measuredvalues LlVo= 1. we find LlVos= 1. Subsequently.. A CMRR value of -100 dB would require resistor matching to 0.0001%. = There is one major problem with this technique for measuring op amp CMRR: the resistors must be known precisely and carefully matched.5 V = 2. one can vary the common-mode input to the DUT and measure the differential voltage between the input SRC1 and the nulling amplifier output.5 V . Hence.With this test setup.7.rRJ TT TT "os With all resistors equal and perfectly matched.23.the CMRR of the op amp is given by CMRR = R1 Rl + ~ Rl TT (3. leading to a CMRR = 750 ~V Nor -62. This configuration is very similar to the one used previously to measurethe open-loop gain and input offsets of Section 3.0 V. This in turn can then be used to deduce the input-referred offset for the DUT amplifier according to VOS-DUT =~"O-NULL Subsequently. only the excitation and the position of the voltmeter are changed.74 analysis reveals An Introductionto Mixed-Signal TestandMeasurement IC "0 -!!J.:!:!!. (3. together with LlVCM=LlVSRCI 2.16). LlVos= 0. V0 = 2 Vos. LlV0 = 2 LlVos. an impractical value to achieve in practice.5 mY.17) I~ V: O-NULL VMID I I (3.5 dB. or when rearranged.498 V = 3 mV.501 V-1. A better test circuit setup is the nulling amplifier configuration shown in Figure 3. The basic circuit arrangement is identical.23. This result can now be substituted into Eq.

even if the op amp itself has a CMRR of -100 dB.501 V is measured the output of the DUT. What is the CMRR? . R2=100 n.11 Figure 3.24 illustrates the test setup to measure the CMRR of a differential amplifier having a nominal gain of 10. For example.0 V. the CMRR of the op amp is not as important as the CMRR of the circuit as a whole. In these cases. Both inputs are connected to a common voltage source SRCI whose output is set to 2.1. andR3=lOO n. No assumption about resistor matching is made.7.5 V .5 V.l7 2. The differential input amplifier CMRR specifications include not only the effects of the op amp. Next the differential gain of the DUT circuit is measuredusing the technique described in Section 3.22 may have terrible CMRR if the resistors are poorly matched.t'.9. we deduce ~VOS-DUT =~~VO-NUU ~+R2 100 = 100+l00k = 22 . Then SRC1 is set to 0.0V V dB 3.17).5 V.23with R)=lOOn.2 CMRR of Differential Gain Stages Integrated circuits often use op amps as part of a larger circuit such as a differential input amplifier. Our next example will illustrate this. Then SRCI is set to 0.5 V and a differential voltage of 10 mV is measured between SRCI and the output of the nulling amplifier. The gain was found to be 10. SRCI is set to set +2. Example3. A voltage of 1.498 V at is measuredat the DUT output. (3.10 ' Fornulling amplifier setupshownin Figure3.15).5 V and the measured voltage changes to-12 mY. we determinethe CMRR using the original definition given in Eq.uV [10 mV -(-12 mY) ] for a corresponding ~VSRCI= 2. -""" . k k togetherwith VMID to a value midway between the two power supply levels. a differential amplifier configuration such as the one in Figure 3. but also the effects of on-chip resistor mismatch.5 V and a second voltage of 1.- Chapter3 .2 VN.0. DC and ParametricMeasurements 75 I Example3. (3. Thus the CMRR is CMRR=~=11~=-99. As such. or 2. What is the CMRR of the op amp? Solution: Using Eq.

: .5 V and the measured voltage changesto -120 mY. Differential x10 amplifier ~ .15.0 V. CMRR test setup.0015 VN. Exercises 3. What is the CMRRofthe op amp in decibels? ADS. For the nulling amplifier CMRR setup in Figure 3.498 V = 3 mV corresponding to a ~VCM= ~VSRCI 2. and R3=100k. . For a I-V change in the input common-mode level. Then SRC1 is set to 0. : : Tester ININ+ : :VOUT .Q. 3.99 ~VN. . .Q.5 V and a differential voltage of210 mV is measuredbetween SRCI and the output of the nulling amplifier. . R2=500 k. .76 An Introductionto Mixed-Signal Testand Measurement IC : : DUT 10 k.2V/V ~ ~ ! . what is the expectedchange in the input offset voltage of this amplifier? ADS. the common= mode gain GCMis calculated to be equal to 0. Solution: Since ~Vo= 1. SRC1 is set to +3. . .23 with R)=100 ll. An amplifier has an expected CMRR of -100 dB. ' ' "SRCI ' I . In addition.16. RC1 rT' ! Va .24.501 V-1. = ~ 10. 21. ' . I : (VMID generated on-chip) Figure A x10 Differential amplifier 3. -93.Q . 1 TiS ! ). t . I . 'we are told that the differential gain Go ~N W ::: ~~ I I =M :::~~:::~ .15 dB. . : Tester: . 10 ~V.

5 V from the SRCI voltage. . Comparator inputoffsetvoltagetest setup. The differential input voltage can be ramped from one voltage to another to find the point at which the comparator changes state. Tester I IN+ : OUT: Tester + : ~ ri1SRC1 %VIN+ ~!1N IN-: !. Example3.25 has a worst-case input offset voltage of :1:50 V and a midsupply m voltage of 1. however.25 is connected to two voltage sources.55 V. Describe a test setup and procedure with which to obtain its input offset voltage. though. D-' I L Vo Comp~r~tf'1 ~ cP Solution: ~RC? VlN- Figure 3. dependenton the input common-mode level. One usually tests for the input offset voltage under worst-caseconditions as outlined in the device test plan.25. SRC2 is set to 1. This is usually a questionableassumption.45 to 1. resulting in an input offset voltage reading of+5 mY. SRCI and SRC2. as the switching point is expected to lie within this range.5 V and SRC 1 is ramped upward from 1. The comparator in Figure 3. Input Offset Voltage Input offset voltage for a comparator is defined as the differential input voltage that causesthe comparatorto switch from one output logic state to the other. assuming the DC sources force voltages to an accuracy of a few hundred microvolts.10 COMPARATOR TESTS DC 3.5V. It is best to measure small voltages using a voltmeter rather than assumethe tester's DC sourcesare set to exact voltages.Chapter 3 . When the output changes from logic La to logic HI. This switching point is. DC and P~rametric Measurements 77 3. the differential input voltage VINis measured.12 The comparator in Figure 3. The VIN voltage could be deduced by simply subtracting 1.10.

Assuming the threshold voltage is expected to fall between 1. the input voltage from SRC1 is ramped upward from 1. The output switches stateswhen the input is equal to the slicer's threshold voltage.10.3 Hysteresis In the comparator input offset voltage example. Slicer thresholdvoltagetest setup. 3.55 V. VTH.26.55 V. forming a circuit known as a slicer. the threshold voltage should be equal to the sum of the slicer's reference voltage VTHplus the input offset voltage of the comparator.26 is tested in a similar manner as the comparator circuit in the previous example.78 An Introductionto Mixed-Signal IC'Test andMeasurement Tester IN+ f : I I I ~~~ 1 Tester RC1 V1N+ V/N i I I i I I : L : ' V 0 Slicer Figure 3. the differential input voltage is measured. SRC2 is set to 1. 3.10. This characteristic is called hysteresis. the threshold may change to a lower voltage.5 V and SRCI is ramped upward from 1.13 The comparator in Figure 3.25 is connected to two voltage sources.45 to 1. On a falling input voltage.55 V in 1-mV steps. What is the hysteresis of this comparator? . This occurred on a rising input voltage. In theory. Threshold voltage error is defined as the difference between the actual and ideal threshold voltages. Example 3.45 and 1. Then the input is ramped downward from 1.45 V and the output switches when the input voltage reaches -3 mV. the output changed when the input voltage reached 5 mV.2 Threshold Voltage Sometimes a fixed reference voltage is supplied to one input of a comparator. Notice that threshold voltage will be affected by the accuracy of the on-chip voltage reference. The slicer in Figure 3. SRCI and SRC2.55 to 1.45 to 1. Hysteresis is defined as the difference in threshold voltage between a rising input test condition and a falling input condition. When the output changes from logic LO to logic HI.and it mayor may not be an intentional design feature. The input offset voltage specification is typically replaced by a single-ended specification. resulting in an input offset voltage reading of +5 mV. called threshold voltage.

If the output is high. Then the output is observedagain.5 V and the output is observed.11.1 Binary Searches versus Step Searches The technique of ramping input voltages until an output condition is met is called a ramp search. then the input is increasedby one quarter of the lOO-mV search range (25 mY) to try to make the output go low. on the other hand.5 mY).Chapter 3 . . the output is low. Instead of ramping the input voltage from 1. then the input is reduced by 25 mV to try to force the output high. Step searchesare time-consuming and not well suited for production testing. the input is adjusted by one-eighth of the search range (12. In a binary search. 3. or step search. A more efficient binary search technique may be used to reduce test time while maintaining the desiredsearchresolution. the input is adjusted up or down using a successive approximation algorithm. A binary search can be applied to the comparator input offset voltage test described in the previous section. the comparatorinput is set to 1.45 to 1. If.11 VOLTAGE SEARCH TECHNIQUES 3.55 V. This time. DC and Parametric Measurements 79 Solution: The hysteresisis equal to the difference of the two input offset voltages 5mV-(-3mV)=8mV It should be noted that input offset voltage and hysteresis may change with different commonmode input voltages. This process is repeated until the desired input adjustment resolution is reached. Worst-case test conditions should be determined during the characterization process.

The gain M is known to be approximately 10.14 Using a linear search algorithm find the input offset voltage Vosfor a xl 0 amplifier. The difference in input offset readings is equal to the hysteresisof the comparator. the next estimate for Vos can be calculated using the linear equation again 0 mV (desired VOUTFMxV/N +B =lOxV/N +120 mV Rewriting this equation to solve for VIN. if a O-mV input to a buffer amplifier results in a 10-mV output and a I-mY input results in a 20-mV output. If the comparator exhibits hysteresis. To get around this problem without reverting to the time-consuming ramp searchtechnique. Then a step search can be used with a much smaller searchvoltage range. a binary search is used once with the output state forced high between approximations. steps are always taken in one direction. Another solution to the hysteresis problem is to use a modified binary search algorithm in which the output state of the comparator is returned to a consistent logic state between binary search approximations. then there are two different threshold voltages to be measured. Solution: The input to a xlO amplifier is set to 0 V and the output is measured. The binary search algorithm assumesthat the input offset voltage is the samewhether the input voltage is increased or decreased. that is 120mV=MxOmV+B =lOxOmV+B => B = 120 mV (first-pass guess) Since 0 mV is the desired output. then a -I-mY input will probably result in a O-m output. The linear search algorithm keeps refming its guessesusing a V simple VOUT= MxV/N + B algorithm until the desired accuracy is reached. For example. A linear search is similar to the binary search.80 An Introductionto Mixed-Signal TestandMeasurement IC The problem with the binary search technique is that it does not work well in the presenceof hysteresis.except that the input approximations are based on a linear interpolation of input-output relationships. The value of offset B can be approximately determined using the VOUT MxV/N + B = linear equation. get we . A binary search can be used to find the approximate threshold voltage quickly. Example 3. To measurehysteresis. avoiding hysteresis effects. The following example will illustrate the method. In this way. The output state is set to a consistent level between approximations by forcing the input either well above or well below the threshold voltage. a hybrid approach can be used. Then input offset is measured again with the output state forced low between approximations.2 Linear Searches Linear circuits can make use of an even faster search technique called a linear search. yielding a reading of 120 mY. 3. since this is supposed to be a xlO amplifier.11.

1 mY. Exercises 3.2 mY). Solving for the two unknowns M = 120 mV-8 mV =9. The input offset voltage is known to fall between 464 and 496 mY. -8. The final estimate is thus -477 mV (Vas = +477 mY. requiring four binary iterations: (1) -480 mY.5 mY. (2) -472 mY.1mV 9.20.1 mY.6 mV and Vas= +477.V1N2 5 over a:t:5 V output voltage + range. A 32-mV search range with 2-mV resolution is required. but will require more iterations of the above process. the linear interpolations are calculated using the most recent two input-output data points until the input convergesto the desired measurementresolution. that is Vas = (0 mY-B) M = (0 mV-122 mY) =-13. During each iteration.20 using a linear search process starting with two points at VIN= -250 mV and-750 mY. the linear search technique will still work. -30.111111111 Chapter3 .4 mY. How many search iterations are required for a maximum error of 1 mV? List the input values and corresponding outputs.21. another output measurementis made. 3. +13. How many iterations are required for < 1 mV error in Vas? Ans. Now we have two equations in two unknowns 120 mV=MxO 8 mV=M(-12 mV+B mV)+B from which a more accurate estimate of M and B can be made. Two iterations produce estimatesof Vas= +471. Repeat Exercise 3. (3) -476 mY.4 mY. +57 mY. resulting in a reading of 8 mV. true answer is +477. Ans.333 V/V 0 mV-(-12 mY) mV)J=122 mV B=10 mV-[M(-12 The next input approximation should be close enough to the input offset voltage to produce an output of 0 mV. (4) -478 mY.333 The input offset voltage of the xl0 amplifier is therefore -13. DC and ParametricMeasurements 81 V]N= (0 mV-:120mY) 10 =-12mV Applying the best guess of -12 mV to the input. For an amplifier characterized by VaUT= 10V1N. assuming the circuit is linear. determine the input offset voltage using a binary search process. . In caseswhere the input-output relationship is not linear.

OL 3. First. Dynamic Von/VOLtesting is performed by setting the tester to expect high voltages above VOH and low voltages below VOL. To allow a distinction between pattern failures caused by VIH/VILsettings and patterns failing for other reasons. Sometimes a pin cannot be set to a static output level due poor design for test considerations.12 DC TESTS FOR DIGITAL CIRCUITS 3. The tester's digital electronics are able to verify these voltage levels as the outputs toggle during the digital pattern tests. It is possible to search for these voltages using a binary search or step search. Input leakage is and also specified for digital output pins that can be set to a high-impedance state. "Tester Hardware.12.5 JOSH and JOSL Short Circuit Current Digital outputs often include a current-limiting feature that protects the output pins from damage during short circuit conditions.3 VOH/V OL VOH and VOLare the output equivalent of VIHand VIL. Input leakage currents (11H IlL) were discussedin Section 3. but it is more common to simply set the tester to force these levels into the device as a go/no-go test. making the Von/VOLtests more difficult for the DUT to pass. VOLis the maximum guaranteed voltage when the output is in the low state.4 IonlIoL VOHand VoLlevels are guaranteedwhile the outputs are loaded with specified load currents.2. Short circuit current is measuredby setting the output to a low state and forcing a high voltage . so only a dynamic test can be performed. loH and JoL. Likewise. the protection circuits limit the amount of current flowing into or out of the pin. they are measuredat DC with the output pin set to static high/low levels." 3.the test engineer may add a second identical pattern test that uses more forgiving levels for VIn/V/L.12. Dynamic VOH/V testing is OL another go/no-go test approach. These voltages are usually tested in two ways.2. then the test program will fail one of the digital pattern tests that are used to verify the DUT's digital functionality. If the digital pattern test fails with the specified VIH/VILlevels and passeswith the less demanding settings. since the actual VOH/V voltages are verified but not measured. These currents are intended to force the digital outputs closer to their VOn/VOL specifications. If the device does not have adequate VIHand VILthresholds.12.12. 3. The diode bridge circuit is discussedin more detail in Chapter 5. This load current is called loR. then VIH/V/L thresholds are the likely failure mode. VOH the minimum guaranteedvoltage is for an output when it is in the high state. The tester must pull current out of the DUT pin when the output is high. loH and loL are forced using a diode bridge circuit in the tester's digital pin card electronics. the tester forces the loL current into the pin when the pin is low.2 VIH/VIL The input high voltage (VIH) and input low voltage (VIL) specify the threshold voltage for digital inputs. 3.12. If the output pin is shorted directly to ground or to a power supply pin.1 lIH/IIL The data sheet for a mixed-signal device usually lists several DC specifications for digital inputs and outputs.82 An Introductionto Mixed-Signal Testand Measurement IC 3.

86 to 4. a load regulation specification of 150 mV (MAX) and a dropout voltage specification of 1. What is its load regulation? 3.6. Assuming a no-load output voltage of 9 V. Hopefully.13 SUMMARY This chapter has presented only a few of the many DC tests and techniques the mixed-signal test engineer will encounter. Then the output is set to a high state and 0 V is forced at the pin.001 v + 100. The accuracy and repeatability requirements of seemingly simple tests like DC offset can present a far more challenging test problem than much more complicated AC tests. A DC offset of 100 mV is very easy to measure if the required accuracy is :f:l0 mY. the test engineer may find this to be one of the more daunting test challenges in the entire project. With a 7. is the input impedance? 3.2.75 V (MIN) to 6. but they can sometimes be excruciatingly difficult to implement. What is the impedance seenlooking into this pin? .Chapter 3 . DC and Parametric Measurements 83 (usually VDD)into the pin. However. the limited examples given in this chapter will serve as a solid foundation from which the test engineer can build a more diversified DC measurementskill set. a 1. This topic pertains to a wide variety of analog and mixed-signal tests.34 V under a 10-mA maximum rated load current. The current flowing out of the pin (lasH) is again measuredwith a current meter. A voltage of 1.V level occurs when the current is increased to 200 ~.3.5-V input voltage. A 9-V voltage regulator is rated to have a load regulation of 150 mV for a maximum load current of 15 mA.4. Accuracy and repeatability of measurementsis the subject of the next chapter.2 V is dropped across an input pin when a 100 ~A current is forced into the pin. What Subsequently.25 V (MAX). What is its line regulation? 3. 3. A 6-V regulator has an output no-load voltage specification of 5. Problems 3. The output of a 5-V voltage regulator varies from 4.32 V when the input voltage is changed from 14 to 6 V under a maximum load condition of 10 mA. The current flowing into the pin (losL) is measured with one of the tester's current meters. this book is intended to address mixed-signal testing.1. DC measurements are trivial to define and understand. The successful resolution of a perplexing accuracy problem can also be one of the most satisfying parts of the test engineer's day.254.5 V (MAX). Much of a test engineer's time is consumed by accuracy and repeatability problems. what is the expected output voltage at the maximum load current? 3. Several chapters or perhaps even a whole book could be devoted to highly accurate DC test techniques. These problems can be one of the most aggravating aspects of mixed-signal testing.5.95 V under no-load condition to 9. On the other hand if 1-~V accuracy is required. The output of a 10-V voltage regulator varies from 9. what is the lowest output voltage that a passing regulator could produce under maximum loading conditions? 3. The input pin of a device is characterizedby the i-v relationship: i = 0.

What is the amplifier output for a I-V input? Similarly for a 3-V input? What is the corresponding gain of this amplifier in VN over the I-V swing? What is the gain in decibels? 3.20 with R)=IOO . and the DUT op amp having an open-loop gain of 1000 VN.8.9..20 with R)=200 .Q.6 V are applied.3 V appear at the output of an amplfier when currents of -10 and + 10 mA. what is the output swing of the nulling amplifier when the input swings by 1 V? 3.0. and R3=100 k.20 with R)=100 .Q.5 V.0.7 V (OUTN) with its input set to a VMiDreference level of 2.7.4 and 1.9 V and a voltage of 1.20. A perfectly linear amplifier has a measured gain of 5. The no-load output voltage of an amplifier is 4 V. an SRCI input swing of 1 V results in a 130-mV swing at the output of the nulling amplifier. are forced into its output.. and R3=50 k. What are the single-endedand differential offsets? The common-mode offset? (All offsets are to be measuredwith respect to VMiD') 3. For the nulling amplifier setup shown in Figure 3.16. The input of a xlO amplifier is connected to a voltage source forcing 1.13. What is the expected relative error made by this measurement? 3. For the nulling amplifier setup shown in Figure 3. What is the open-loop gain of the DUT amplifier in VN? What is the gain in decibels? 3.4 V (OUTP) and 2. respectively.19. Voltages of 0.Q. R2=200 k.2 V.700 V is measuredat the output of the amplifier.0.o. A differential amplifier has outputs of2.1 VN and an output offset of -3. What is the PSS?What is the PSRR if the measuredgain is 9. For the nulling amplifier setup shown in Figure 3.2 and 3. respectively.0.Q is used to measure the DC output of an amplifier with an output impedance of 500 k. what error of -5% while captured measuring a I-V offset from an is the actual reading by the voltmeter? 3.1 V appear at the output of a single-ended amplifier when inputs of 1. An amplifier is characterizedby VOUT=1..Q. R2=300 k. the voltage drops to 3V. The power supply voltage is then changed to 5. R2=100 k. and R3=100 k.175 V (relative to ground) appearsat the output of the nulling op amp when the input is set to VMID.12.Q.8 VN? . What is the amplifier's output impedance? 3. and a VMID of2.5VIN+ 0.What is the input offset of the DUT amplifier? 3. load is attached to the output. What is the amplifier output for a 2-V input? Similarly for a 3-V input? What is the corresponding gain of this amplifier in VN over the I-V swing? What is the gain in decibels? 3.Q.5 VIN+ lover the input voltage range 0 to 5 V. A voltmeter with an input impedance of 500 k. A voltmeter amplifier. What is the output impedance? 3. What is the gain of the amplifier in VN? What is the gain in decibels? 3.708 V.11. An amplifier is characterizedby VOUT=3.10.35V/N2+1over the input voltage range 0 to 5 V..8 and 4. introduces What a measurement V/N2+ 5 over a :i:15-V range.84 An Introduction to Mixed-Signal TestandMeasurement IC 3. The power supply is set to 4.14. Voltages of 1.18.75 V. What is the input offset voltage? 3.1 V and the output measurementchanges to 1. When a 600-. For a x10 amplifier characterized by VOUT= 10V/Nare its input and output offset voltages? 3.5 V. an offset of3.15.17.

at what voltage on the positive terminal does the comparator change state? 3. Introduction to IDDQ Testing. Boston..11111111- Chapter 3 .5-V level.o.23 with R)=100.26.. what threshold voltage should we expect? 3. at what voltage level will the slicer change state? 3. A slicer circuit is connected to a 2-V reference and has a threshold voltage error of 20 mV. A comparator has a measuredhysteresis of 10m V and switches state on a rising input at 2. Paul J. Norwood.0 V and the measuredvoltage changesto -260 mV. Inc. DC and ParametricMeasurements 85 3.5-V reference has an error of + I 00 mV and the comparator has an input offset of -10m V.5VlN2 2 over a :l:1-V input voltage range.o. and R3=100 k. starting with two I points How at:l:1 many V. For a I-V change in the input commonmode level. R2=300 ill. SRC1 is set to +3.23. An amplifier has an expected CMRR of -85 dB. A comparator has an input offset voltage of 6 mV and its negative terminal is connected to a 2.22.21. For nulling amplifier CMRR setup shown in Figure 3. At what voltage doesthe comparator changeto a low state on a falling input? 3. ISBN: 0792399455 2. Analog Devices. After how would many have iterations been required did the using answer a binary change search by from less -1 than to I mY? iterations + 1 V? References 1. determine the input offset voltage using a linear search process. May.. . Analog Devices application note. If a slicer's 2. Thadikaran. Then SRC1 is set to 1.27. The technique has been presented with permission from Analog Devices. What is the CMRR of the op amp in decibels? 3. MA. Kluwer Academic Publishers. what is the expected change in the input offset voltage of this amplifier? 3. 1997. MA.24.5 V.25. The nulling amplifier/servo loop methods presentedin this chapter were adapted from the referenced application note to allow compatiblity with single-supply op amps having a VMIDreference voltage. 1982 tJ . How to Test Basic Operational Amplifier Parameters. Sreejit Chakravarty..5 V and a differential voltage of 130 mV is measured between SRC1 and the output of the nulling amplifier. For an amplifier characterized by VOUT=6VlN + 0. Inc. July.

It does not refer to consistent errors in the measurements. these terms are defined very differently in engineering textbooks3-s. the terms accuracy and precision are virtually identical in meaning. since the words precision and accuracy are so often used synonymously. This definition of precision is somewhat counterintuitive to most people. but as long as they are consistently wrong by the same amount. Rather than trying to decide which of the various error sources are included in the definition of accuracy. Roget's Thesaurus lists these words as synonyms and Webster's Dictionarr gives almost I identical definitions for them. However. usually expressed as a percentage of reading or a percentage of measurementrange (full scale). the word repeatability is far more commonly used in the test engineering field than the word precision.1.The variation of a measurementsystem obtained by repeating measurements on the same sample back-to-back using the same measurementconditions.The difference between the averageof measurementsand a standard sample for which the "true" value is known. However. Precision . the accuracy of an instrument (as distinguished from the accuracy of a measurement) is often specified in the absence of repeatability fluctuations and instrument resolution limitations. This textbook will use the term accuracy to refer to the overall closenessof an averaged measurementto the true value and repeatability to refer to the consistency with which that measurement can be made.1 Accuracy and Precision In conversational English. Combining the definitions from these and other sources gives us an idea of the acceptedtechnical meaning of the words: Accuracy . it is probably more useful to discuss some of the common error components that contribute to measurement 87 .CHAPTER 4 MeasurementAccuracy 4. Many sourcesof error can affect the accuracy of a given measurement. then the measurementsare consideredto be precise. The word precision will be avoided.instrument to absolute standards. Few of us would be impressed by a "precision" voltmeter exhibiting a consistent 2-V error! Fortunately. Unfortunately. The degree of conformance of a test. A series of measurementscan be incorrect by 2 V. The accuracy of a measurement should probably refer to all possible sources of error. precision refers only to the repeatability of a series of measurements. According to these definitions.1 TERMINOLOGY 4. the definition of accuracy is also somewhat ambiguous.

103 mY.2 Systematic Errors Systematic errors are those that show up consistently from measurementto measurement. However. 4.2. 102 mY. Using a digital voltmeter (DVM) we could take multiple readings of the offset over time and record each measurement. gain errors. Various types of calibration will be discussed in more detail in Section 4. 102 mV.1. Systematic errors can often be reduced through a process called calibration. Random errors are usually causedby thermal noise or other noise sources in either the DUT or the tester hardware. 103 mY.1. eyebrows may be raised.3.. Limited resolution results from the fact that continuous analog signals must first be converted into a digital format before the ATE computer can evaluate the test results. 101 mY. and nonideallinearity in the DVM's measurementcircuits. 102mV. assumean amplifier's output exhibits an offset of 100 mV from the ideal value of 0 V. ATE measurementinstruments have similar limitations in measurementresolution. . A typical measurementseriesmight look like this: 101 mY. Averaging and filtering are discussed in more detail in Section 4.1. The errors can result from a combination of many things. or by the tester itself. by bad DUT design.. Errors like this are caused by consistent errors in the measurement instruments.88 An Introductionto Mixed-Signal Testand Measurement IC inaccuracy. For example. 4. The DVM gives readings from 101 to 103 mY.3 Random Errors Notice in the preceding example that the measurementsare not repeatable. including DC offsets. On the other hand. notice that the measurementsare always rounded off to the nearest millivolt. 4. Such variations do not surprise most engineers becauseDVMs are relatively inexpensive. One of the biggest challenges in mixed-signal testing is determining whether the random errors are causedby bad Dffi design. They may be inclined to believe that the tester software is defective when it fails to produce the same result every time the program is executed. The tester converts analog signals into digital form using analog-to-digital converters (ADCs). when a two million dollar piece of ATE equipment cannot produce the same answer twice in a row. or perhaps the DVM was only capable of displaying three digits. Inexperienced test engineers are sometimes surprised to learn that an expensive tester cannot give perfectly repeatable answers. experienced test engineers recognize that a certain amount of random error is to be expected in analog and mixed-signal measurements. then averaging or filtering of measurementsmay be required. If the source of error is found and cannot be corrected by a design change. It is incumbent upon the test engineer to make sure all components of error have been accountedfor in a given specification of accuracy. This measurement series shows an average error of about 2 mV from the true value of 100 mV. 103 mY. The measurement may have been rounded off by the person taking the measurements.4 Resolution (Quantization Error) In the 100-mV measurement list. 101 mY.

if a test engineer gets the same answer 10 times in a row. Quantization error is a result of the conversion from an infmitely variable input voltage (or current) to a finite set of possible digital output results from the ADC. The resolution of a DC meter is often limited by the quantization error of its ADC circuits. Measurement Accuracy 89 7 6 5 ADC output 4 code 3 2 1 0 0 1. In fact. This inherent error in ADCs and measurementinstruments is causedby quantization error. a 23-bit voltmeter might be able to produce a measurementwith a l-~ V resolution. it simply means the meter cannot resolve variations in input voltage smaller than 1 mY. it is time to start looking for a problem.Chapter4 . resulting in a . Since all electrical circuits generate a certain amount of random noise.0 V - - - - - - - 2.1.25 V any time the input voltage falls between 1.1. In fact. An instrument's resolution can far exceed its accuracy. the meter would produce an output reading of 1. the tester instrument's full-scale voltage range has been set too high. If a meter has 12 bits of resolution. A large portion of the time required to debug a mixed-signal test program can be spent tracking down the various sourcesof poor repeatability. Figure 4.5 V will producean output code of 2.5 V. Output codesversusinputvoltages an ideal3-bitADC. Most likely. This does not automatically mean that the meter is accurate to 1 mV. measurementssuch as those in the 100-mV offset example are fairly common. Notice that an input voltage of 1. If this ADC were part of a crude DC voltmeter.2 V results in the sameADC output code as an input voltage of 1. 4.5 Repeatability Nonrepeatableanswers are a fact of life for mixed-signal test engineers.0 V ADC input voltage Figure4. but it may have a systematic error of 2 mV.0 V 3.3 V. any voltage from 1.0 to 1. that means it can resolve a voltage to one part in 212_1 (one part in 4095).0 V 4. for ADCs by nature exhibit a feature called quantization error. For example.0 and 1.1 shows the relationship between input voltages and output codes for an ideal 3-bit ADC. then a resolution of approximately 1 mV can be achieved (4 V /4095 levels). If the meter's full-scale range is set to :1:2 V.

4. The degree to which a series of supposedly identical measurements remains constant over time. 6 mY. a voltage of 104 mV would also have resulted in this same series of perfectly repeatable. The calibration process brings the tester instruments back into alignment with known electrical standardsso that measurementaccuracy can be maintained at all times. perfectly incorrect measurement results.7mV. if we configured a meter to a range having a 10-mV resolution. After the tester is powered up. % 19. A 5-mV signal is measuredwith a meter ten times resulting in the following sequenceof readings: 5 mY. A novice test engineer might think this is a terrific result. The same calibration processesused to . The tester must be recalibrated anytime the ambient temperature has shifted by a few degrees. Calibrations then have to be rerun once the tester recovers to a stable temperature. the measurementswill drift over time as the tester heats up. temperature. the tester's circuits must be allowed to stabilize to a constant temperature before calibrations can occur. Stability is an essentialrequirement for accurateinstrumentation. These changesare typically much slower than shifts due to temperature. 100 mY.1. etc. A signal is to be measuredwith a maximum uncertainty of %0. Repeatability is desirable. the temperature of the measurement electronics will typically drop. 8 mY. Testers are usually equipped with temperature sensorsthat can automatically determine when a temperatureshift has occurred.). 21 bits.humidity. 5 mY. then our measurementsfrom the prior example would be very repeatable (100 mY. and humidity. 8 mY.5 mY. What is the averagemeasuredvalue? What is the systematic error? Ans. Shifts in performance can also be causedby aging electrical components. assuming only quantization errors from an ideal meter ADC? ADS. Most shifts in performance are caused by temperature variations. 4.2. and all other time-varying factors is referred to as stability. 11 mY. 7 mY. A meter is rated at 8-bits and has a full-scale range of %5 V. 100 mY. When the tester chassis is opened for maintenance or when the test head is opened up or powered down for an extended period. Otherwise. resolution are required by an ideal meter having a %1V full-scale range? ADS. Shifts in the electrical performance of measurement circuits can lead to errors in the tested results. Unfortunately.1. How many bits of 4.5~V.2mV. 100 mY. 9 mY. What is the measurement uncertainty of this meter. but the meter is just rounding off the answer to the nearest 1O-m increment due to an V input ranging problem. Exercises 4. 4 mY. 7 mY.90 An Introductionto Mixed-Signal Testand Measurement I~ measurementresolution problem.3. For example. but it does not in itself guaranteeaccuracy.6 Stability A measurementinstrument's performance may drift with time. temperature.

it is a good idea to make sure the correlation errors are less than one-tenth of the full range between the minimum test limit and the maximum test limit. Bench correlation is a good idea. or they may be very subtle. the two testers may not even be manufactured by the same ATE vendor. Only after all the testers agree on all tests is the test program and test hardware debuggedand ready for production. program-to-program. but not on another presumably identical tester.7 Correlation Correlation is another activity that consumes a great deal of mixed-signal test program debug time. Often. The test engineer should compare all the test results on one tester to the test results obtained using other testers. In addition. It can be extremely frustrating to try to get the same answer on two different pieces of equipment using two different test programs. However. Dffi-to-Dffi. Correlation is the ability to get the same answer using different pieces of hardware or software. tester-to-tester. IC design engineers often build their own evaluation test setupsto allow quick debug of device problems. Bench equipment such as oscilloscopes and spectrum analyzers can help validate the accuracy of the ATE tester's measurements. Similar correlation problems arise when an existing test program is ported from one tester type to another. but can also be compensated for by periodic calibrations.Chapter4 . Whatever correlation errors exist. In fact. Tester-to-TesterCorrelation Sometimesa test program will work on one tester. The more common types of correlation include tester-to-bench. along with nomepeatability and systematic errors. 4. the testers are neither software compatible nor hardware compatible with one another. Of course correlation is seldom perfect. The test engineer will often need to help debug the bench setup to get to the bottom of correlation errors between the tester and the bench. test program problems are uncovered when the ATE results do not agree with a bench setup. The test engineer must consider several categories of correlation. Shifts caused by humidity are less common. Each of these test setups must correlate to the answers given by the ATE tester. and day-to-day correlation. Often the tester is correct and the bench is not. Test results from a mixedsignal test program cannot be fully trusted until the various types of correlation have been verified. Measurement Accuracy 91 account for temperature shifts can easily accommodate shifts of components caused by aging. The exact requirementswill differ from one test to the next. Other times.1. A myriad of correlation problems can arise becauseof the vast differences in Dffi layout and tester . they must be considered part of the measurementuncertainty. It can be even more frustrating when two supposedly identical pieces of test equipment running the same program give two different answers. a customer will construct a test fixture using bench instruments to evaluate the quality of the device under test. this is just a rule of thumb. Tester-to-BenchCorrelation Often. since ATE testers and test programs often produce incorrect results in the early stages of debug. The differences between testers may be catastrophically different. but how good is good enough? In general.

tester. Often. "Focused Calibrations"). etc. the test reduction techniques causemeasurementerrors becauseof reduced DOT settling time and other timing-related issues. These measurementsare taken using various combinations of test conditions that ideally should not change the measurementresult.. Program-to-Program Correlation When a test program is streamlined to reduce test time. and sometimes the differences cause correlation errors.but not reproducible. The difference between reproducibility and repeatability relates to the effects of correlation and stability on a series of supposedly identical measurements. the test program may consistently pass a particular DOT on a given day. A given test may have to be executed in a very different manner on one tester versus another. should not affect any measurementresult. DIB board. For this reason. the faster program must be correlated to the original program to make sure no significant shifts in measurement results have occurred. is the ability to achieve the same measurementresult on a given DUT using any combination of equipment and personnel at any given time. Consider the case in which a measurementis highly repeatable. but this is not a correct usage of the term. there should be no drift in the answers from one day to the next. the architecture of each tester will determine the best test methodology for a particular measurement. To some extent. measurementsmust be both repeatableand reproducible to be production-worthy. and yet consistently fail the same DOT on another day or on another tester. correlation between two different test approachescan be very difficult to achieve. by contrast.8 Reproducibility The term reproducibility is often used interchangeably with repeatability. the choice of equipment operator. Subtle errors in software and hardware often remain hidden until day-to-day correlation is performed.92 An Introductionto Mixed-Signal Testand Measurement IC software between different tester types. Conversion of a test program from one type of tester to another can be one of the most daunting tasks a mixed-signal test engineer faces. For example. Any difference in the way a measurementis taken can affect the results. If the tester and DIB have been properly calibrated. . Day-to-Day Correlation Correlation of the same DIB and tester over a period of time is also important. It is defined as the statistical deviation of a series of supposedlyidentical measurementstaken over a period of time.Repeatability is most often used to describe the ability of a single tester and DIB board to get the same answer multiple times as the test program is repetitively executed. Reproducibility. The test engineer should always check to make sure that the answers obtained on multiple DIB boards agree. These correlation errors must be resolved before the faster program can be released into production. The usual solution to this type of correlation problem is to improve the focused calibration process. DIB correlation errors can often be corrected by focused calibration software written by the test engineer (this will be discussed further in Section 4. In such a case.1. 4. DIB-to-DIB Correlation No two DlBs are identical. Clearly.2 and in Chapter 10.

amperes. followed by a correction of the nonideal behavior using a mathematical routine written in software.2. 4. Then a model of the instrument's nonideal operation can be constructed. In part (a) a "real" voltmeter is modeled as a cascadeof two parts: (1) an ideal voltmeter. Measurement Accuracy 93 4. The old one is sent back to a certified calibration laboratory.1 Traceability to Standards Every tester and bench instrument must ultimately correlate to standardsmaintained by a central authority. ATE testers are able to correct hardware errors without adjusting any physical knobs. Full automation can be achieved using a simpler procedure known as software calibration. which is a thermally stabilized instrument in the tester mainframe. gallons. bench instruments are periodically recalibrated so that they too are traceable to the NIST standards. and electrical units such as volts.2. The basic idea behind software calibration is to separatethe instrument's ideal operation from its nonidealities.2 CALIBRATIONS AND CHECKERS . 4. However.) indicates the functional relationship between Vmeasured VDUT. inches. Similarly. which recalibratesthe reference so that it agreeswith NIST standards. One major problem with hardware calibration is that it is not a convenient process. and (4.3 Software Calibration Using software calibration. oscilloscope probes often include a small screw that can be used to nullify the overshoot in rapidly rising digital edges.1) . Many testers have a centralized standards reference.this government agency is responsible for maintaining the standardsfor pounds.f(. Figure 4. In the United States. relationship can be expressed in more This mathematicalterms as vmeasured = f(vDUT) where. and (2) a black box that relates the voltage across its input terminals VDUT the voltage that is to measured by the ideal voltmeter. It generally requires a manual adjustment of a screw or knob.2 illustrates this idea for a voltmeter.2 Hardware Calibration Hardware calibration is a process of physical "knob tweaking" that brings a piece of measurementinstrumentation back into agreement with calibration standards. Robotic screwdrivers might be employed to allow partial automation of the hardware calibration process. By periodically refreshing the tester's traceability link to the NIST. such as the National Institute of Standards and Technology (NIST).Chapter4 4. all testersand bench instruments can be made to agreewith one another. The chain of correlation between the NIST and the tester's measurementsinvolves a series of calibration steps that transfers the "golden" standardsof the NIST to the tester's measurementinstruments.and ohms. This is one common example of hardware calibration. The standardsreference is periodically replaced by a freshly calibrated reference source. the use of robotics is an elaborate solution to the calibration problem.2. For instance. Vmeasured.

the voltmeter in Figure 4.94 An Introductionto Mixed-Signal T~stand Measurement IC The true functionalbehavior is seldomknown.3 includes a pair of calibration relays. the number of parametersused to describe the model. .) a model. the tester closes one relay and connects the voltmeter to VDUT Actual VM meter ~ "' + Vmeasured VDUT meter Ideal - - = Vmeasured . Hence. I v calibrated DUT .f(. Vcalibrated -I " -J (vmeasured) : I . Subsequently. (a) Modeling a voltmeterwith an ideal voltmeterand a nonideal componentin cascade.) is known precisely.2. I I I .I( VDUT ) Vmeasured (a) VmeasuredI(VDUT) = : I I I : . precise reference levels are necessary. In order to establish an accurate model of an instrument. I I VDUT U ' . which can connect the input to two separatereference levels. To avoid conflict with the meter's normal operation.3) where Vcalibrated replaces VDUT an estimate of the true voltage that appearsacross the terminals as of the voltmeter as depicted in Figure 4. Vrefl and Vrefl. it has two parameters.o.a mathematical procedure is written in software that performs the inverse mathematical operation vcalibrated (vmeasured) = 1-1 (4. respectively. If. Vmeasured : I I I I I Software routine : .2(b). then VcaJibrated= VDUT. (b) Calibrating nonidealeffectsusinga software the routine. I (b) Figure 4. I I I O I I I ---{::> ~' . I . that is.2) where G and offset are the gain and offset of the voltmeter.G and offset. For the linear or firstorder model described. For example. so one assumes particularbehavioror .The number of reference levels required to characterize the model fully will depend on its order. two reference levels will be required.v I I . such as a first-order model given by vmeasund = GVDUT offset + (4.f(. During a system level calibration. These values must be determined from measured data. relays are used to switch in these reference levels during the calibration phase.

6) factors.5) - (4. Vmeasured2. or cal factors ~efl The parameters for short. (4. . Subsequently. we can write two equations in terms of two unknowns vmeasuredl GVrojl +ojJset = vmeasured2 GVroj2 +ojJset = Using linear algebra (Gauss-Jordan elimination method).Chapter4 .4) can then be solved to be G = Vmeasured2 -vmeasuredl ~ef2. (4. Based on the assumed linear model for the voltmeter.3. Measurement Accuracy 95 Vrefl and measuresthe voltage.2) and Meter input V refl V METER Figure 4. are also known as calibration When subsequent DC measurements are performed. the two model parameters (4. they are corrected using the stored calibration factors according to . G and offset. voltmeter DC gain and offsetcalibration paths.this process is repeated for the second reference level Vrej2 and the voltmeter provides a second reading.Vrefl and Vref2 Vrefl offset = vmeasuredl -v measured2 Vroj2 (4.7) VDUT on one side of the expression in Eq.vmeasured -offset V calibrated G This expression is found by isolating replacing it by Vcalibrated. of the model. which we shall denote as Vmeasuredl.

and focused calibrations. 0. then each range setting requires a separateset of calibration factors. After replacement. This software is called a checkerprogram. What are the offset and gain of this meter? Write the calibration equation for this meter.mV)/1. Exercises 4. In addition to calibrations. A meter reads 0. or checker for short. performance verification (PV). A meter is assumedcharacterizedby a second-order equation of the form: vmeasured = offset + G1 calibrated V~librated' V + Gz Write the calibration equation for this meter in terms of the unknown calibration factors.5 mV and 1.1. The calibration factors are measuredand stored automatically during the tester's periodic system calibration and checker process.2. These include calibration reference source replacement. periodic system calibrations and checkers.6. Often calibrations and checkers are executed in the same program. Fortunately for the test engineer.1 V when connected to two precision reference levels of 0 and 1 V. this example is only for purposes of illustration. .5 4.2. vcalibrated +"'G: +4GZvmeasured vcalibrated -G1-"'G: +4Gzvmeasured . Most testers use much more elaborate calibration schemesto account for linearity errors and other nonideal behavior in the meter's ADC and associated circuits.96 An Introductionto Mixed-Signal Testand Measurement IC Of course.0995 VN.5 mV. most instrument calibrations happen behind the scenes. Vcalibrated= (Vmeasured. A ns. software is also executed to verify the functionality of hardware and make sure it is production worthy. 1. respectively. 0. and each of these possible configurations needs a separateset of calibration factors. Also..4 System Calibrations and Checkers Testers are calibrated on a regular basis to maintain traceability of each instrument to the tester's calibration reference source.-G1 or 2Gz 2Gz depending on the data conditions.0995.the new module must be completely recalibrated. A common replacement cycle time for calibration sourcesis once every six months. if the input stage has ten different input ranges. Calibration reference source replacement and recalibration was discussed in Section 4. Ans. A meter is assumedcharacterizedby a second-orderequation of the form: vmeasured = offset + G1 calibrated V~librated' V + Gz How many precision DC reference levels are required to obtain the parametersof this second-orderexpression? Ans. If a checker fails. For example. the meter's input stage can be configured many ways. There are several types of calibrations and checkers. the repair and maintenance (R&M) staff replaces the failing tester module with a good one.5. instrument calibrations at load time. - - 4.4. Three. 4.

However. Describea calibration V procedure that can be used to ensure that 2. Sincetesterinstrumentation may drift slightly betweensystemcalibrations. these calibrations may be repeated a periodicbasisafter the programhasbeenloaded. A simple example of focused instrument calibration is a DC source calibration. Measurement Accuracy 97 To verify that the tester is in compliance with all its published specifications. Although full performance verification is typically performed at the tester vendor's production floor. focused calibrations are often required to achieve maximum accuracy and to compensatefor nonidealities of DIB board components such as buffer amplifiers and filters. These software calibration and checker programs verify that all the system hardware is production worthy. A high-accuracy AC voltmeter is used to measure the RMS value from the A WG. 4. It may take several iterations to achieve the desired value with an acceptablelevel of accuracy. Focused calibration is not always necessary. focused calibration and checker software is the responsibility of the test engineer. They may on alsobe executed automatically thetestertemperature if drifts by morethana few degrees.The extracalibrations be limited to the subsetof instruments can usedin a particulartest program. A calibration routine that determines the error in a DC source's output level can be added to the first run of the test program. Example 4. To maintain accuracythroughoutthe day.Chapter 4 . accurate instruments and fast instruments that may be less accurate. periodic system calibrations and checkers are performed on a regular basis in a production environment.2. a more extensiveprocesscalled performance verification may be performed. Unlike the ATE tester's built-in system calibrations. This helpsto minimize programload time.500.500 V:t the DC source. By contrast.the testermay alsoperform a seriesof fine-tuningcalibrationseachtime a new test programis loaded. then the requested voltage is reduced by I mV and the output is retested.5Focused Instrument Calibrations Testers typically contain a combination of slow. 500 ~V does indeed appear at the output of . A high-accuracy DC voltmeter can be used to measurethe actual output of the DC source. it is seldom performed on the production floor. A similar approach can be extended to the generation of a sinusoidal signal requiring an accurate RMS value from an arbitrary waveform generator (A WG). Focused calibrations fall into two categories: (1) focused instrument calibrations and (2) focused DIB calibrations and checkers. If the source is in error by 1 mV. Finally. it may be required if the test engineer needs higher accuracy than the instrument is able to provide using the built-in calibrations of the tester's operating system.4. The A WG output level will thus converge toward the desired RMS level as each iteration is executed.1 A 2. The DC sourcesin a tester are generally quite accurate. The discrepancy between the measuredvalue and the desired value is then used to adjust the programmed A WG signal level. The accuracy of the faster instruments can be improved by periodically referencing them back to the slower more accurate instruments through a process called focused calibration.but occasionally they need to be set with minimal DC level error. for instance.signalis requiredfrom a DC sourceas shownin Figure4.

10 mV + 1 mV and measured again. including spectrum analyzer displays. Figure 4. The source is then reprogrammed to 2.499 V. the :f.10 mV + 1 mV = 2.491 V).:!V).'.510 V from the source.. calibration factor = 2.500 V and a high-accuracy voltmeter is connected to the output of the source using a calibration path internal to the tester. ft. Solution: The source is set to 2.10 mV and the output is remeasured. then the source is reprogrammed to 2. respectively.4. Spectral density plots are commonly defined in engineering textbooks with the length of the spectral line representing one-half the amplitude of a tone. A multitone signal can be viewed in either the time domain or in the frequency domain. Test time is not wasted searching for the ideal level after the first calibration is performed. Mathematically a multitone signal y(t) can be written as y(t) = Ao + ~ sin(27&J. it is stored as a calibration factor (e.500 V .3. while frequency-domain views are analogous to spectrum analyzer plots. of the kth tone. This recalibration interval is dependenton the type of tester used. DC source focused calibration. calibration factors may need to be regeneratedevery few hours to account for slow drifts in the DC source. frequency.500 V. Assume the high-accuracy voltmeter reads 2.g.500-V DC level is required during subsequent program executions.. and phase.+ ANSin(21l'fNt+f/JN) N (4.': '. The frequency-domain graph of a multitone signal contains a series of vertical lines corresponding to each tone frequency and whose length.. If the second meter reading is 2. Another application of focused instrument calibration is spectral leveling of the output of an A WG. . and </Jk denotes the amplitude.8) =Ao+ }::Aksin(27&ht+f/Jk) k=1 where Ak. Timedomain views are analogous to oscilloscope traces.500 V (plus or minus 500 . This process is repeated until the meter reads 2.500 V .500 V .491-V calibration factor is used as the programmed level rather than 2. However. Once the exact programmed level is established.t+f/JJ)+. In most test engineering work. An important application of A WGs is to provide a composite signal consisting of N sine waves or tones all having equal amplitude at various frequencies and arbitrary phase. Such waveforms are in a class of signals commonly referred to as multitone signals.. When the 2.98 An Introduction to Mixed-Signal IC Test and Measurement OUT input Programmab DC source VMETER . Calibration path connections are made through one or more relays such as the ones in Figure 4. it is more common to find this length defined as an RMS quantity. represents the root- .

5 and 4..the test engineer must evaluate the need for focused cf. wherefis the frequency expressedin Hz. This gain can then be stored as a calibration factor that can subsequentlybe retrieved to correct the amplitude error at that frequency. To correct for the gain change with frequency. The model consists of an ideal source connected in cascadewith a linear block whose gain or magnitude responseis described by G(f). We can therefore' model this A WG multitone situation as illustrated in Figure 4. Each line is referred to as a spectral line. Time-domain frequency-domain and viewsof a three-tone multitone The A WG produces its output signal by passing the output of a DAC through a low-pass antiimaging filter.2. Thus the amplitudes of the individual tones may be offset from their desired levels. Measurement Accuracy QQ mean-square(RMS) amplitude of the corresponding tone.82 V.6. The composite signal can then be generated with corrected amplitudes by dividing the previous requested amplitude at each frequency by the corresponding A WG gain calibration factor.5. Nevertheless.Chapter 4 . they can sometimes be omitted with little degradation in accuracy. Figure 4. the amplitude of each tone from the AWG is measured individually using a high-accuracy AC voltmeter.6. The ratio between the actual output and the requested output corresponds to G(f) at that frequency. the filter will not have a perfectly flat magnitude response. the processis called multitane leveling. This book will consistently display frequency-domain plots using RMS amplitudes. all having an RMS amplitude of 2 V. Focused calibrations were once necessaryon almost all tests in a test program.The DAC may also introduce frequency-dependenterrors.1 kHz.J2 x2 or 2. As testers continue to evolve and improve. Figure 4.5 illustrates the time and frequency plots of a composite signal consisting of three tones of frequencies 1. Of course. it may become increasingly unnecessary for the test engineerto perform focused calibrations of the tester instruments. . Due to its frequency behavior. so we could just as easily plot these values as peak amplitudes rather than RMS. Modeling AWGas a cascaded an combination an idealsourceand frequency-dependent of gainblock. Actual AWG VSOURCE [---~::::>~o G(f) VSOURCE - Ideal A AWG 't :& Figure4. Today. Because the calibration process equalizes the amplitudes of each tone. the peak amplitude of each sinusoid in the multitone is simply. The calibration process is repeated for each tone in the multitone signal.

5.1 kHz andis written as y(t) = 2.1 kHzxt: This wavefonn is loaded into the A WG and the three-tone signal is produced with equal levels of 2.0 V divided by the appropriate calibrationfactor.100 An./ntroductionto Mixed-Signal Testand Measurement IC calibrations on each test.J2 sin ( 21l"x2.8).1 kHz) = 1.For eachtone.2.0 V RMS per tone.1 kHz is desiredfrom an A WG. beginningwith the lowest-frequency tone and progressing in frequency. Solution: Three calibration factors are calculated as the ratio of the measuredsignal to the desired signal ca13 2.950V. the test engineer should still understand the methodology so that test programs on older equipment can be comprehended. The testervendor has no way to predict what kind of buffer amplifiers and other circuits will be placedon the DIB board.023and 1.5 kHzxt) + 2.it shouldbe possibleto get exactly2.1 kHzxt) Sequentially. 2.fI = 1 kHz.0 V. and 4. corresponding a peak amplitude to ofJi x 2.0Y =0. The testeroperatingsystemwill neverbe able to provide automatic calibration of these circuits.0. (4.980. /3= 4.975 VIv As long asthe AWG is linear.0Y = G(4.each up tone is loadedinto the A WG and the sinewave is passed from the A WG into a high-accuracy AC RMS voltmeter. Using Eq.J2 sin(21l"Xl kHzxt)+ 2.5 kHz.0 V. on the otherhand. a three-tone signalis mathematically created with parametersAo= Al = A2 = A3= Jix2. The three-tone signal is thus created usingthe equation y(t) = ~. of Example 4.will probablyalwaysbe required.0 Vat eachtoneby asking for 2. Calibrationof circuits on the DIB.h= 2. . Compute the calibrationfactorsandprovidea formulathat describes modifiedthree-tone the signal.the voltmeterreads:1. Each tone should have exact RMS amplitudeof 2. 0. This multitoneshouldhave0 DC offset. Even if calibrations become unnecessaryin the future. The test engineeris fully responsiblefor understanding the calibrationrequirements all DIB circuits.J2 sin (21l"x4.950 Y 2. call' 2-"2" cat) sin(2Jrx4.2 A multitonesignal consistingof threetonesat 1.

In order to perform an accurate measurement. As a result.023 V is measuredusing the voltmeter.3 can be used with no modifications. then we may find that the DUT breaks into oscillations as a result of the stray capacitance arising along the lengthy signal path leading from the DUT to the tester. : I I I Tester 1 k. Outline the steps to perform a focused DC calibration on the op amp buffer stage. resulting in an output : I I I : OUT : I I I I . Next the input is dropped to IV. following the same procedure as outlined in Section 4. Meqsurement Accuracy 101 4. let SRCI force 2 V and assume that an output voltage of 2.2. a model of the test setup is identical to that given in Figure 4.6 Focused DIB Circuit Calibrations Often circuits are added to a D ill board to improve the accuracy of a particular test or to buffer the weak output of a device before sending it to the tester electronics. If the output is not buffered.3.7 has been added to a Dill board to buffer an output of a DUT. The buffer will be used to condition the DC signal from the DUT before sending it to a calibrated DC voltmeter resident in the tester.2. It is reasonable to assume that the buffer is fairly linear over a wide range of signal levels.the behavior of the buffer must be accounted for. so that the following linear model can be used Vm ured GVDUT offset = + Subsequently. Example 4. a pair of known voltages are applied to the input of the buffer from source SRCI via the relay connection and the output of the buffer is measured with a voltmeter.3 The op amp in Figure 4.f(-) covers the Dill circuitry only. DC calibration for op amp buffer circuit. The only difference is that functional block vm ured=f(VDUT) includes both the meter and the Dill's behavior.Q :VOUT I I I I . . As an example. the meter may already have been calibrated so that the functional block.One must keep track of the extent of the calibration to avoid any double counting. Conversely.7. The buffer prevents these oscillations by substantially reducing stray capacitanceat the DUT output.Chapter 4 . To perform a DC calibration of the output buffer amplifier it is necessaryto assumea model for the op amp buffer stage.2(a).2. As the signal-conditioning Dill circuitry is added in cascadewith the test instrument. the focused instrument calibrations of Section 4. I L j ~eter V~ 9 + ~o Figure 4. This temporary connection is called a calibration path.

001 vcaiibrated 1. "Focused Calibrations.. if the voltmeter reads 1. ADCs.012V.001 V =1. then each unique signal path must be individually calibrated.by rearranging expression the and replacing Vcalibrated for VDUT.5).![ voltage of1.6) to be . Chapter 10.011 V N If the original uncalibrated answer had been used.uset 1. the actual voltage appearing at its'tenninals is actually v.012 V.must be measured at each frequency used in the test during a calibration run of the test program. Using Eq. Hence.023Vx1V = 2 V-I V = 1mV Hence.732 V-0. the frequency responsebehavior of the DIB circuitry must be correctly accounted for. The first run of the test program should not only~ .011VN = vmeasured V For example.732 V.2V-2..712V caiibrated 1.011 V/V 2 V-I V and the offset is found from Eq. a similar calibration processmust be performed on each frequency that is to be measured. DIB failures can be a major source of downtime on a production floor unless thorough checkers are available to quickly diagnose DIB hardware failures. Assuming that the meter has already been calibrated. the test program should also include DIB checkers to verify the basic operation of as many DIB circuits and signal paths as possible." will addressthese and other issuesin greater depth. we find the buffer has gain given by G= 2. there would have been a 20-mV error! This example shows why focused DUT calibrations are so important to accuratemeasurements. If additional circuits such as filters. Once found. (4.011 V/V X VDUT +0.023 V-1.R. the buffer amplifier also has a nonideal frequency responseand will affect the reading of the meter. the DUT output VDUT the voltmeter value Vmeasuredrelated according to and are vmeasured = 1. it is stored as a calibration factor. Like the A WG calibration example. are added on the DIB board and used under multiple configurations.012 V =1.102 An Introduction to Mixed-Signal Testand Measurement IC . 4. This is achieved by measuring the gain in the DIB's signal path at each specific test frequency.7 DIB Checkers In addition to focused DIB calibrations. =1.001 V The goal of the focusedDC calibrationprocedure to find an expression relatesthe DUT is that output in terms of the measured value.2. o. Its gain variation. we obtain -0. When buffer amplifiers are used to assistthe measurementof AC signals. (4. etc. together with the meter's frequency response.

but it should also perfonn a go/no-go test on as many of the DIB board componentsand signal paths as is possible. 2.Exercises Ans.6 V.. and 0. Calibration software in the tester compensatesfor the different PGA gain settings so that the digital output of the meter's ADC can be converted into an accurate voltage reading. when programmed to produce this level. determine a value of the programmed source voltage that will establish a measured voltage of 2.552 V is measured.316. What are the calibration factors? Ans. It is seldom possible to pass signals through every possible relay and every possible trace on the DIB board. Small signals are measured with the highest gain setting of the PGA. while large signals are measured with the lowest gain setting. The calibration software also compensates linearity errors in the ADC and offsets in the PGA and for .005 + V PROGRAMMED . 4. While the gain through a relay seldom requires focused calibration. relays can become defective with age.2. and 3 kHz. 4. A good example of a circuit in which a checker is useful is a relay path. It can be difficult to detennine whether or not a particular tester instrument is capable of making a particular measurementwith an acceptablelevel of accuracy. Consider the following DC meter example. only 2.jJ-' is to generatethree and tones at frequencies of 1.0.Using iteration. Mea~urement Accuracy 103 calibrate the DIB circuits.707. every path and every componentthat can be tested with checker code should be verified. All the specification conditions must be examined carefully.003 V.6 V to within a:i: 1 mV accuracy. the program should look for little or no output swing with the 1 V / -1 V input. 4. This ranging process effectively changesthe resolution of the ADC so that its quantization error is minimized.447. Chapter4 . However. However.7. They can also be welded shut by high currents or they can become stuck in the open state. An A WG has a gain responsedescribed by (R-y.8. The tester specification~ usually do not include the effects of uncertainty causedby instrument repeatability limitations.2. The DIB checker code should verify that each accessiblerelay can be opened and then closed.8. To verify the relay can be opened. 0.8 Tester Specifications The test engineer should exercise diligence when evaluating tester instrument specifications.ROGRAMMED required to generate a DC level and is of2. A DC source is assumed characterized by a third-order equation of the fonD V MEASURED = 0.651 V. 0. The easiest way to do this is to apply a 1 V / -1 V voltage pair at the input to the relay and look for a 2-V swing at its output while the relay is closed. The programmable gain stage is used to set the range of the meter so that it can measure small signals as well as large ones. A DC meter consisting of an analog-to-digital converter and a programmable gain amplifier (pGA) is shown in Figure 4.

: : I . This meter has five different input ranges. The different ranges allow small voltages to be measuredwith greater accuracy than large voltages. It is not clear from the table above what assumptions are made about averaging.lV Resolution 15.5 mV for the higher ranges.25 ~V 30.there may also be a repeatability error to consider.0. the test engineer does not have to worry about these calibrations because they happenautomatically. Example 4.O. Table4. I I Meter 4. I . Fortunately. This accuracy specification probably assumes that the measurement is made 100 or more times and averaged. the DVM100.lO% or 2. The test engineer should make sure that all assumptions are understood before relying on the accuracy numbers. Range control: Figure~ . Simplified DC voltmeter with input ranging amplifier.5 mV :r.104 An Introductionto Mixed-Signal Testand Measurement IC I . VDUT ADC ' : : : ' ' ' I I .4 A DUT output is expected to be 100 mV.0~V 152. the DVMlOO. I I I : I I ' Tester computer : : .1.5 V range to achieve the optimum resolution and accuracy. The accuracy is specified as a percentage of the measuredvalue.0.5V :r. For a single nonaveragedmeasurement.2V :r.2mV :r. .1 shows an example of a specification for a fictitious DC meter. The reading from the meter (with .5~V Accuracy (% of Measurement) :i:O.05%orlmV :r. .05%orlmV :r. I : .lO%or2. is set to the 0.5 ~V 305. Our fictitious DC voltmeter. but there is an accuracy limit of 1 mV for the lower ranges and 2. ADC. Table 4. Note: All specs apply with the measurement filter enabled.8.5mV .which can be programmed in software. DVM100 DC Voltmeter Specifications Range :i:O.lOV 6l.0. ' ' : Programmable : gain : amplifier (PGA) I I I .05% or 1 mV (whichever is greater) :r.5V :r.

LV. Such signals might benefit from local buffering and amplification before oassin2 to . Sometimesthe engineer may have to design front-end circuitry such as PGAs and filters onto the DIB board itself.3 mY. The accuracymight hold up for 100 days and then drift toward the specification limits of 1mV on day 101. for example. the specification of but hasa lower limit of 1 mY. the actual voltage at the DUT output could be anywherebetween 101. What range of outputs could actually exist at the DUT output with this reading? Solution: The measurement error would be equalto :1:0. Calculate the accuracy of this reading (excluding possible repeatability errors). since the vendor will not take any responsibility for use of instruments beyond their official specifications. Front-end circuits may also be added if the signal from the DUT cannot be delivered cleanly through the signal paths to the tester instruments. Measurement Accuracy 105 the meter's input filter enabled) is 102.3mY. sinceall low-passfilters require time to stabilizeto a final DC value. Repeatability enhanced is whenthe low-passfilter is enabled. meter also has a low-passfilter in serieswith its the input. sincethe filter reduces electrical noisein theinput signal. The accuracy therefore:1:1 is mY. Another possible scenario is that multiple testers may be used that do not all have IOO-~V performance. It is much safer to use the specifications as printed.3 mY. and with It may be possibleto empiricallydetennine throughexperimentation this DC voltmeter that hasadequate resolutionandaccuracy makea DC offsetmeasurement lessthan I 00 ~V of to with error. In additionto the ranginghardware. Very high-impedance DUT signals might be susceptible to externally coupled noise. The DIB circuits might be needed if the front-end circuitry of the meter is inadequatefor a high-accuracy measurement. meaning that the instruments are often better than their specified accuracy limits. The filter can be bypassed enabled. the instrument should probably not be trusted to make such a measurement in production. The test engineermust often choosebetweenslow. though.05% 100mY. Withoutthis filter the accuracy would be degraded nomepeatability.3 and 103. repeatable measurements fastmeasurements lessrepeatability. or 50 J. by The filter undoubtedly addssettlingtime to the measurement. Basedon the singlereadingof 102. Tester companies are often conservative in their published specifications. Sincethis level of accuracyis far better than the instrument's:tl mV specifications. This is not a license to use the instruments to more demanding specifications.Chapter 4 .depending the measurement or on requirements.

though.9.the signal component is assumedto change from 0 to IV. Example 4. since a lower cutoff frequency excludes more electrical noise. it takes longer to measure a series of DC voltages with a low-pass filter in the signal path. : I I 1 kQ I I : I I I . a lower cutoff frequency adds extra test time while the filter settles to a stable DC level.. Unfortunately. Thus.9) . The following two exampleswill quantify this tradeoff for a first-order system. of VI= 0) in Figure is 4. J? Y0 ~ I . The purpose of the filter is to remove all but the lowest-frequency components.e.3 DEALING WITH MEASUREMENT ERROR 4. It acts as a hardware averaging circuit to improve the repeatability of the measurement. For a particular measurement. 4. A DC voltmeter may include a low-pass filter as part of its front end. there is an inherent tradeoff between repeatability and test time.9 is used to filter the output of a DUT containing a noisy DC signal. Since the filter has a settling time that is inversely proportional to the cutoff frequency. RClow-pass filter. Solution: From the theory of first-ordernetworks. More effective filtering is achieved using a filter with a low cutoff frequency.106 An Introductionto Mixed-Signal Testand Measurement IC the tester instrument.the stepresponse the circuit startingfrom rest (i. instantaneously.5 The simple RC low-pass circuit shown in Figure 4.1 Filtering Analog filters are often used in tester hardware to remove unwanted signal components before measurement. a lower frequency cutoff corresponds to better repeatability in the final measurement.9 vo(t) =S 1.e-t/T ( ) (4. . Consequently. The test engineer must calibrate any such buffering or filtering circuits using a focused DIB calibration. How long does it take the filter to settle to within I % of its final value? By what factor does the settling time increasewhen the filter's 3-dB bandwidth is decreasedby a factor of 10? VI 9-1-:J:J l .3. ~_1:~_J Figure 4.

the time t = ts the output reachesan arbitrary output level of V0 is then 10 ts =Further.11) . Me~urementAccuracy 107 where S = 1 V is the magnitude the stepand '(= RC = 10-3 Moreover. so we can rewrite Eq. which is simply the . We shall make use of frequency-domain techniques. noise signals are characterized by a noise spectral density function. f To simplify our discussion.99 V. what is the RMS noise voltage that appears at the output of the filter? If the filter bandwidth decreases a factor of 10. ~ (expressedin rad/s) of a first-order network is l/RC. for example.11) as ts =-~ (l)b (4. is ts -. noise signals have their power spreadout over the entire frequency spectrum. or 0.- Chapter4 . As such. While periodic signals have power at distinct frequency locations (see.01).12). If the noise voltage has a constant spectral density of 17 V2/Hz.12) Hence. (Data sheets often specify noise using volts per root-hertz. Specifically. we recognize that (S (T ) S-V (l)b (4. which we shall denote as S(/)o It represents the average power over a I-Hz bandwidth centered at each frequency. Since settling time and 3-dB bandwidth are inversely related according to Eq. by what factor does the output noise voltage decrease? by Solution: To answer this question we must rely on our knowledge of noise and linear system theory.6 The simple RC low-pass circuit shown in Figure 4.V0)/ S is the settling error E or the accuracy of the measurement.XO-3. (4. It can also be expressed in terms of amps-squared/hertz or watts/hertz..5). S(/) will have units of volts-squared/hertz or V2/Hz. so we can rewrite the above expression as vo(t)=S ( l-e -(I) b t ) (4.46ms .11. the settling time becomes46 ms. (4. Example4.10) Clearly.10(0. a tenfold decreasein bandwidth leads to a tenfold increase in settling time.9 is used to filter the output of a DUT containing a noisy DC signal. . Figure 4.the 3-dB bandwidth of s.the time it takes to reach within 1% of 1 V.

14). oncewe substitute (4. Thus the RMS value of the noise signal can also be obtained in the frequency domain using the following relationship VRMs=F (4. the RMS value of the output noise voltage Vn is 0 Vno=~ or.18) = l/RC.16)as ~ ~ 2 1 dl (4.17) and that we can calculate the system transfer function for the RC low-pass filter to be G(/)=~(/)=--~-=-~ VI where ~ {J)b+j21Z"1 l+j~ {J)b (4.15) (4.13) Now to get back to the question at hand. 108 An Introduction to Mixed-Signal rest and Measurement IC square root of the noise spectral density as we have defined it here.14) and Sn (I) 0 are the input and outputnoise voltagespectraldensities. the noise that appearsat the output of the filter is related to the input noise voltage according to the following Sno (I) where Sn (I) I =Snl (I)IG(I)r (4.19) ~ no = 17 0 1+j. and G(/) is the system input-output transfer function.21Z"1 {J)b . respectively. Hence.16) Sn (/)=17 I y2 - Hz (4..we obtain Eq. We canthenwrite Eq.) The total mean-squared value of the noise is obtained by integrating the spectral density over the entire frequency spectrum. Vno= fSnl(l)IG(ltdl 0 Since we are told (4. (4.

12. (4.JiO.JiO reduction in output noise RMS voltage will occur.11.34 kHz. at this time we can not fonnally quantify the improvement until a mathematical definition for repeatability is given. How long does it take a first-order RC low-pass circuit with R = I ill settle to 5% of its final value? ADS. However. in the example above." In the preceding example.10. 72.2 nF.Q and C= 2.7 mY RMS. then a . is Exercises 4. Often the test engineer knows only the RMS noise value from the output of the DUT. Measurement Accuracy 109 Integrating and perfonning the squareroot.). rather than the output noise spectral density. and C = 2. What is the RMS-level of the noise voltage that appearsat the output? ADS.20) Here we clearly see that the output noise voltage dependson two factors: the level of the input noise voltage spectral density and the filter's 3-dB bandwidth expressedin fad/so If the filter's bandwidth is decreasedby a factor of 10. What is the 3-dB bandwidth of the RC circuit of Figure 4. For now.. 4. A noise signal having a spectral density of 10-9y2/Hz is applied to the RC circuit of Figure 4.. Thus.9 with R = I ill and C = 2.6 ~s.20) we can work backwards and obtain an estimate of the spectral density level 1]coming from the DUT 1] =4 (~ DUT )2 - y2 (4. We shall offer a formal analysisof the relationship between noise and repeatability in Chapter 15. Subsequently. expressedin Hertz. the concept of a noise spectral density was introduced and used to characterizethe noise at the input of the filter. Interestingly enough.2 nF? ADS.21) (J)DUT Hz where VDVT the DUT output noise (RMS volts) and ~UT is the 3-dB bandwidth of the DUT. 4.using Eq.9. y (4. we will offer without proof that the total variation in measurementvalues is proportional to the level of noise.2 nF to .. when R = I k.j.6. We can also conclude that the repeatability will improve.Chapter4 . "Data Analysis. we can expect the variability of measurementsto improve by a factor of . it was used to detennine the RMS level of the noise at the output of the filter. 10. we obtain the RMS output noise voltage to be Vno=~J".

.17. 10.16.-:::.LV-RMS. 250 Hz. by 4.~n IntroductionMixed-SignalTest Measurement to IC and ~ (4..LV-RMS to 100 !.the greater the noise reduction. The output of a DUT has an uncertainity of 10 mY. Settling time increasesby 2. How many samples should be combined in order to reduce the uncertainity to 100 !. Vno = VDUTV'%: V This expression clearly illustrates the noise reduction gained by filtering the output.14.22) Provided ~ « abUT. What filter bandwidth is required to achieve this level of repeatability? Assume that the DUT's output follows a first-order frequency responseand has a 3-dB bandwidth of 1000 Hz ADS. Assume that the DUT's output follows a first-order frequency response and has a 3-dB bandwidth of 100 Hz. f ~ Exercises 4. 6.51. but it needs to be reduced to a level closer to 500 !.LVRMS. The smaller the ratio ~ / abUT. Substituting Eq. A DUT output consisting of a noise component having a spectral density of 10-6V2!Hz is to be measured 100 times and the results averaged.15. a very narrow bandpassfilter may be placed on the DIB board to clean up noise components in a sine wave generatedby the tester.000. By what factor does the settling time increase. Other types of filtering circuits can be placed on the DIB board when needed. The variation in the output signal of a DUT is 1 mV RMS.20). we can write r. it is reasonableto assume that the noise has a constant spectral density over the frequencies of interest given by Eq.21). 4. By what factor should the bandwidth of an RC low-pass filter be decreasedin order to reduce the variation in a DC measurement from 250 !. Estimate the output noise voltage spectral density.5.25 (=2. ADS.LV? ADS. The variation in the output RMS signal of a DUT is 1 mV.37 x 10-9 V2!Hz. The filter allows a much more ideal sine wave to the input of the DUT than the tester would otherwise be able to produce..'IIIIIII..21) back into Eq. 100 !. (4.LV.. For example. (4. 4. The bandwidth should be decreased 6. What is RMS value of the noise component in the final result? ADS. (4. 4.13. . ADS.

( /2) ) )[ cos (2Jl"f (N -1)/2)j sin (2Jl"f(N -1)/2) ] Nsm 21if /2 = ( (4. Measurement Accuracy 111 4.e. The frequency response is obtained by first evaluating the z-transforrn of Eq. it becomes prohibitively expensive (i. that is. At some point. we can write the input-output relationship as I y(n) =-[x(n)+x(n-I)+. (4. the answer will become more repeatable and reliable. consider representing a sequence of numbers as x(n). one has to take four times as many readings and average them. But there is a point of diminishing returns. To reduce the effect of noise on the voltage measurement by a factor of two..2 Averaging Averaging is a form of discrete-time Averaging can be used to improve the repeatability of a measurement. where n indicates the order at which the samples appear in the sequence. we can average the following series of nine voltage measurements 101 mY. For example. If the length of the series is increased. the output is downsampledor decimated by N YD(n) =y(nN) (4. Now. . To better understand the above statement. 101 mY. Further.$ f. Nonetheless.regardlessof when the output is obtained. 101 mY. 103 mY.+x(n- N + I)] N 1 N =. There is a good chance that a second series of nine unique measurements will again result in something close to 102 mY. 103 mY. consider x(n) as input to a discrete-time system whose output is the average value ofx(n) and the N-I previous input samples. 102 mY. we are really only interested in the output after N samples.25) To introduce its effect on the system's frequency responsewill only add more complication to an otherwise sophisticated explanation. from the point of view of test time) to improve repeatability. 102 mV and obtain an average of 102 m V.$ Y2given by G(f) = ( sin(21ijN .Chapter4 . 102 mY.24) sin(21ijN /2) ) e-j2Kf(N-I)/2 Nsin(21if /2) Technically. let x(n) consist of both signal and noise.23) This system is called an N-point running averager and it can easily be shown that it has a frequency response"for -Y2. filtering.3.Lx(n-k+l) Nk=1 (4. one ..23) and then substituting z=e j2nft .. Mathematically. 103 mY.

So we shall work with the running averageresult only as the conclusions are the same. However. However.29) Here we see the output noise voltage reduces the input noise before averaging by the factor .[j. Normally.28) If we denote the noise from the DUT before averaging as VDUT. Thus the correct average value is (1 V + 0. If a series of measurementsis exEressed decibels. with no averaging taking place. to reduce the noise RMS voltage by a factor of two requires an increase in the sequencelength. -40 dBV.112 An Introductionto Mixed-Signal Testand Measurement IC would not expect the behavior of the noise to be influenced by the observation window. one should not try to averagereadings in decibels. However. . However. so the conversion from dB to linear units or ratios is not necessary.26) Substituting the appropriate relationships. (4. AC measurementscan also be averagedto improve repeatability. -20. we can write the final expression as . Hence. solving the integration and taking the squareroot. the actual voltages are 1 V. and 10 mY.j. Vn = VDUTHence. 0 ~ no 0 =k . The RMS voltage that appearsin the output discrete-time signal is found from an expression very similar to the continuous-time case given in Eq. To understand why we should not perform averaging on decibels.13). The average of these values is -20 dBV. (4. is easy to show that Vn = Jij. the voltage or gain measurementsare available before they are converted to decibels in the first place. by a factor offour. we obtain Vno = 17 J I[ sin.or-8. the output noise spectral density will then be given by Eq. 100 mY. N.(21l"jN/2) ] e-j2Zf(N-IJ/2 1 2 df (4. Once the average voltage level is calculated.[j.1 V +0. it can be converted to decibels using the equation dB = 2010glo(V). they should in first be converted to linear form using the equation V = 10d 120 before applying averaging. we obtain Vn = 0 Ii VN V (4.01 V)/3=37mV. consider the sequence0. it This can be seen directly from Eq.28) when N = 1.64dBV. in this case the integration is performed from -!j2 to If2to account for the periodicity of G(f) and becausethe sampling period is 1 Vno = 1/2 Sn[ (J)IG(J)F -1/2 f df (4.j V (4. (4. If the noise component in the input signal has a constant spectral density of 11V2/Hz.16). A series of sine wave signal level measurementscan be averagedto achieve better repeatability.27) -1/2 Nsm(21l"f /2) Finally.

if the device output is I 0 1 mV and the error in its measurementis -10m V. In such cases. Of course. If a particular measurementis known to be accurate and repeatablewith a worst-case uncertainty of :%:s.2. if the data sheet limit for the offset on a buffer output is -100 mV minimum. At some point. a reading of 91 mV may also represent a device with an 8l-m V output and a +10 mV measurementerror.3. 7 Table 4. How m many good devices are rejected becauseof the measurementerror? How many good devices are rejectedif the measurementuncertainty is increasedto :%:10 V? m Table 4.the test program mV limits should be set to -90 mV minimum and 90 mV maximum. the final test limits should be tightened from the data sheet specification limits by E to then make sure no bad devices are shipped to the customer.2 lists a set of output values from a DUT together with their measured values. Ideally. In other words guardbandedupper test limit = upper specification limit guardbandedlower test limit - E = lower specification limit +E (4. the resulting reading of 91 mV will cause a failure as required. There is a balance to be struck between repeatability and the number of good devices rejected. we would like all guardbands to be set to 0 so that no good devices will be discarded. To minimize the guardbands we must improve the repeatability and accuracy of each test. It is assumedthat the upper test limit is 100 mV and the measurementuncertainty is :%:6 V. Example 4. DUTOutputand Measured Values nUT Output 105 mV 101 mV 98mV 96mV 86mV 72mV Measured Value 101 mV 107 mV 102mV 95mV 92mV 78mV ~ .guardbanding has the unfortunate effect of disqualifying good devices. the added test time cost of a more repeatable measurement outweighs the cost of discarding a few good devices. 100 mV maximum.30) So.3 Guardbanding . for example. and an uncertainty of :%:10 exists in the measurement. but this typically requires longer test times. Measurement Accuracy 113 Guardbandingis an important technique for dealing with the uncertainty of each measurement.Chapter4 4. This way.

four devices are below the upper test limit of 100 mV and should be accepted. Now with a measurementuncertainty of:i:6 mV.VDAC_SNR test group and is executed during a test routine called T. Where should the guardbandedtest limits be set? Ans. 1. (1. only two devices are acceptable. The format of a datalog typically includes a test category.30) the guardbandedupper test limit is 94 mY.6). 2.4. Hence.1 Datalogs A datalog is a concise listing of the test results generated by a test program.2. test description.19.7). (4. 2.3. how many good devices are rejected due to the measurementerror? Ans. (1.8. What are the original device specification limits? Ans. 2.1).114 Solution: An Introductionto Mixed-Signal Testand Measurement Ie From the DUT output column on the left.VDAC_SNR. 1. but they all convey similar information. The exact format of datalogs varies from one tester type to another.10. Datalogs are the primary meansby which test engineersevaluate the quality of a device as it is tested.1). and a measuredresult. (1. If the upper test limit is 2. If the measurement uncertainty increases to :i:lO mY. (2. The others are all rejected. 4. Exercises 4. Consequently. according to Eq. For example.1.9.5-V guardbandedupper test limit). upper and lower test limits. then the guardbanded upper test limit becomes 90 mY. three otherwise good devices are disqualified. A short datalog from a Teradyne A580 tester is listed in Figure 4. (1.6).18.The other two should be rejected. Four devices (all good devices are rejected by the 1. 1.1).0)}. The gain error is part of the S.20.7. :i:45 mY. "DAC Gain Error" is the name given to test number 5000.5 V. The upper and lower limits for the test are also . The guardband of a particular measurement is 10 mV and the test limit is set to :i:25 mV. 4.5. (2. two otherwise good devices are disqualified. Each line of the datalog contains a shorthand description of the test. 4. 2.0 V and the measurementuncertainty is :i:0. A device is expected to exhibit a worst-case offset voltage of :i:50 mV and is to be measured using a voltmeter having an accuracy of only :i:5 mY. :i:35 mY. Five devices are rejected and only one is accepted. The following lists a set of output voltage values from a group of DUTs together with their measured values: {(2. With the revised test limit.4 BASIC DATA ANALYSIS 4.

4 63.00 Sequencer: 7000 DAC POSERR 7001 DACNEG ERR 7002 DAC POS INL 7003 DACNEG INL 7004 DAC POSDNL 7005 DACNEG DNL 7006 DAC LSB SIZE 7007 DACOffset V 7008 Max Code Width 7009 Min Bin: 10 Code Width -100.23 LSBs (least significant bits).000 .000 dB< dB< dB< dB< 0.0 mV 0.127 0.10.83 lsb < 0. Measurement Accuracy 115 listed.2 mV < 100.90 lsb < 0.0 T-UDAC-SNR 60. 4.50 lsb 0.0 mV < -0.00 T-VDAC-SNR 60.23 lsb < 1. while other bins usually representvarious categoriesof failure. a microprocessor may fail full speeddigital pattern testing at 750 MHz.00 dB.84 lsb < 0. In such a case. Sometimesmultiple good bins are defined.48 70.00 lsb < 0.10 and display only the results from test 5000.125 0.0 T=VDAC=SNR 55. andthemeasured valuefor this DUT is -0.000 1.43 <= 61. the 500-MHz processor might be graded into Bin 2 and sold at a lower price while higher-grade 750-MHz processors are graded into Bin I and sold at a premium.0 T UDACLin T-UDAC-Lin T-UDAC-Lin T-UDAC-Lin T-UDAC-Lin T-UDAC-Lin T-UDAC-Lin T-UDAC-Lin T-UDAC-Lin T-UDAC-Lin - dB dB dB dB dB dB < -0.9 LSBs.0 T-UDAC-SNR 60.0 6000 6001 6002 6003 6004 6005 DACGain Error DAC S/2nd DAC S/3rd DAC S/THD DAC SiN DAC S/N+THD S_UDAC_Linearity T UDACSNR -1.0 T=UDAC=SNR 55.00 T-UDAC-SNR 60. The upper limit is 0.00 mV < -100.0 mV < 0.000 dB dB dB dB . the theupperlimit is + 1.00dB.10 <= 86.5 <= 63.0 mV < 100. but may operate perfectly well at 500 MHz.4. Sequencer: 1000 Neg Sequencer: 5000 DAC 5001 DAC 5002 DAC 5003 DAC 5004 DAC 5005 DAC Sequencer: S_continuity PPMU Cont S VDAC SNR Gain Error S/2nd S/3rd S/THD SiN S/N+THD S UDAC SNR Failing Pins: 0 dB dB dB dB dB dB < <= <= <= <= <= -0.6 60.2 dB dB dB dB dB dB < 1.90 lsb < -0. Bin 1 usually representsa good device. so this test fails.000 1.90 lsb -0. the DAC Gain Error test may show slight repeatability errors: 5000 5000 5000 5000 DAC DAC DAC DAC Gain Gain Gain Gain Error Error Error Error T_VDAC_SNR T_VDAC_SNR T_VDAC_SNR T_VDAC_SNR .90 lsb < -0.50 lsb Figure 4. If we repeatedly execute the test program corresponding to Figure 4.90 lsb 1.000 . Test 7004 shows a test failure in which the measurement reads 1. Becausethe device is not a good one.3 <= 59. lower limit of DAC Gain Error is -1. allowing devices to be graded into several passing categories.000 1.1.00 lsb < 7.90 lsb 1.00 dB T VDAC SNR -1.90 lsb -0. For instance.2 Histograms When a test program is executed multiple times on a single DUT.131 dB dB dB dB < < < < 1.0 mV < -100.23 lsb (F) < 0. Usingtest number5000as an example.0 mV 3.00 mV 0.95 mV < 100.84 lsb < 0.129 0.0 mV 1. it is categorized into Bin 10 in this example.0 T-VDAC-SNR 60.00 T-UDAC-SNR 55. Example datalog from a Teradyne A580tester.000 1. The datalog lists an easily recognizable fail flag for values that fall outside the specified test limits.1.8 60.00 T-VDAC-SNR 55.0 T-VDAC-SNR 60.Chapter 4 .17 lsb < 1.4 mV < 100.1 dB dB dB dB dB dB 1.1.2 <= 63.13 63.90 lsb < -0. it is common to get multiple answersdue to imperfect repeatability.13 dB.

129 -0. Otherwise.000 T=VDAC=SNR-1. .12 (4. It shows both numerical results and a plot of the distribution of measured values.131 been dB dB dB dB dB dB to < < < < < < 1. the standard deviation is small.. the distribution should be closely packed.128 -0. The best approximation will be made when the number of readings N of the same quantity is very large.32) .000 1. the standard deviation is large. This histogram output also displays a number of useful values. Ideally. Histograms are also used to look at distributions of measurements over many DUTs to determine how much variability there is from one device to another. the total results would be the number of DUTs tested.u] /1 ~r_r_'\ .1300 dB.13 dB. while if the values tend to be distributed far from the mean. The extra resolution in this second example allows the variations in the results to be more easily seen.11 shows.130 -0.000 T=VDAC=SNR-1.u. The distribution plot is a convenient graphical way to understand the repeatability of the measurement. However.u and standard deviation 0" are the most important of these. Ideally a histogram should contain results from at least 100 devices (or 100 test executions on a single device in the caseof repeatability studies).-1. The mean . The population size is listed next to the heading "Total Results =".000 T VDACSNR -1. as the example in Figure 4. A histogram for the repeatability example above is shown in Figure 4.000 T_VDAC_SNR. The standard deviation is a measure of the dispersion or uncertainty of the measured quantity about the mean value. Testers generally use the full resolution of the measurement when comparing DUT performance against the specification limits. the mean value from 110 measurements is -0.000 dB dB dB dB dB dB has increased three digits after the decimal point in this second example.134 -0.000 T VDACSNR -1. The printout resolution is specified in the test program.31) For the DAC Gain Error example shown in Figure 4. The mean value is defined as . Only the datalog output values are rounded. The mean.11.000 of the datalog output dB dB dB dB dB dB < < < < < < -0. Standarddeviation is defined as O"=VN~[x(n)-. We can view the repeatability of a group of readings using a tool called a histogram. It is important to note that there may be a difference between datalog output resolution and the resolution of the value as it is compared against test limits. If the values tend to be concentrated near the mean. the more trustworthy a histogram becomes.u =- 1 N N Lx(n) n=] (4.representsthe most probable value of a measured variable. Another useful item in the histogram is the population statistics.132 -0.000 1.000 1. if the measurement repeatability is poor the histogram spreadsout into a larger range of values.11. or average. not the actual measuredvalues. It indicates how many times the meaSurementwas repeated on the same device. In the caseof multiple DUTs. The larger the population of results. all the results above would have been rounded off to -{}. A histogram with less than 50 results is statistically questionable becauseof the limited sample size.116 5000 5000 5000 5000 5000 5000 Notice An Introduction to Mixed-Signa/lC Test and Measurement DAC Gain DAC Gain DAC Gain DAC Gain DAC Gain DAC Gain that the Error Error Error Error Error Error resolution T_VDAC_SNR-1.000 1.000 1.

'.12dB 0. It would not be advisable to take such a shortcut if the range of values covered a 20-dB span.12125dB lower Test limit= lower Pop limit= Total Results= Underflows= Mean= Mean . The .127 -0.'.131 dB -0.:.6 any summation of a large number (N > 30) of statistically independent random variables converges toward a Gaussian distribution.140 -0. of Standarddeviation and mean are expressedin identical units.11. Histogram the DACgainerrortest. To be perfectly correct we would need to convert the logarithmic values into linear units such as V N before reading the mean and standarddeviation from a histogram.13003dB -0.120 Figure 4. However.129 -0.139 -0.0029 dB.13594dB Maximum Value= -0.123 -0. We can still view histograms of logarithmic values to get a general idea of the mean and standard deviation.135 -0.' -0. The histogram in Figure 4.:.0013333dB 18 - PLOTSTATISTICS -0. In our DAC example.133 -0.128 -0.132 -0. Measurement Accuracy 117 Test No 5000 Test Function Name T_VDAC_SNR -1dB Test label DAC Gain Error UpperTest limit= Units dB 1dB +Infinity 110 0 0.'.00292899 -0.364 .136 -0.13882dB Upper Pop limit= Results Accepted= Overflows= Std Deviation= Mean + 3 Sigma= Minimum Value= lower Plot limit= Cells= Full Scale Percent= -0.125 -0. The bell curve (also called a normal distribution or Gaussian distribution) is a common one in the study of statistics.'.121 -0.137 -0.'.124 -0. Notice that we have broken the previously stated rule that we should not calculate averages(and standarddeviations for that matter) using logarithmic units such as the decibel. The distribution of values has a shape similar to a bell.14dB Upper Plot limit= 15 Cell Width= 16.Chapter4 .3 Sigma= DISTRIBUTION STATISTICS - -Infinity 110 0 -0. According to the central limit theorem. we are often able to take this statistical shortcut when all the values are very near one another. 12473dB -0. but we should remember that these values are not entirely accurate.11 exhibits a common feature for analog and mixed-signal measurements. the standard deviation was found to be 0.36% Full Scale Count= - 16. The reason for this is that logarithmic curves are approximately linear over a limited span of values.

4. many measurements For through Gaussian you DAC the are the all DAC the distribution.121 sigma" standard dB. variations in a typical mixed-signal measurement caused a summation many different are by of sources mixed-signal of noise and crosstalk in exhibit both the the familiar device and Gaussian the tester distribution. In theory. As a of is Figure evident. will to wait In probably billions reality. 4.115 Figure 4. from the When warning a parameter that sign though familiar looking that across needs the bell for distributions shape measurement is DUTs. In of smooth similar other words.125 -0. never should are than a see +200 the -0.118 An Introduction to Mixed-Signal IC Test and Measurement Gaussian (normal) distribution""""" curve -0. example. fixed. As a result. 4. plots something many to be When indicate a test program a distributions or a fabrication incorrect may poor that process answers. standard from the deviation minimum is are sigma. sixth of from labels are of Figure -0. to real allow world some equal In the values beside only approximates general statements.12 the distribution illustrates graph has extends eventually only near-Gaussian.139 "Mean not as the the ideal First. and which deviation These "Mean indicates values +3 0.145 -0.12. see maximum this a distribution.13 gain example measurements stray more result. total Gaussian the variation distribution.140 -0.14). few a dB away from Although close distribution maximum would sample minimum Gaussian expect histogram and enough the to is value. and Yield The total yield devices of a given lot of material is defined as the ratio of the total good devices divided by the tested: . the -0. Gain measured Error points. Test Time. also indicate 4. a on repeatable.3 Noise. dB answer dB.130 -0.0029 displayed dB. distributions Common and these looking outliers distributions for design is yielding that are deviations not Gaussian. tenths of the a results bell to using shape. an answer As a willing example.13) DUT.12 to -3 extreme. a quite. It should bimodal repeatability sufficiently Gaussian may is quite be more distributions common or less to obtain bell-shaped. instruments.120 -0. Continuous normal (Gaussian) distribution for the DAC gain example." that the comparison of a value Gaussian to so in The is not actual truly is roughly to one the we the distribution ranging the values 4.135 -0. curve to a if in the in Gaussian years you infinity. not nonThey are (Figure a single (Figure are of 4.

a measurement with poor accuracy or poor repeatability will just exacerbate problem.'.139 -0.12-0. the 12.745 e 9.14-0.13-0.792 P16. '" :!:i: Outliers 1i1i1 ::::: ::::: .'.141 18. test time.15-0. 1 ~ !:~11 ~.000 devices passall tests.000 11i1111111jjjii! 1O.14. 800 .134 -0.15-0.15-0. Bimodal distribution.14-0.490 21.443 e r14.147 -0.15-0.12-0.126 -D.11-0.Chapter4 .'.'.13-0. Obviously.11-0. 23.094 c11.13-0.Statistical outliers.:.:.12-0.10-0.000 -0. 4. there are inherent tradeoffs between repeatability.103 -0.698 2.127 -0.~~~ I -0. ld = total good devices x I 00°/ total devices tested /0 (433) .14-0. then the yield on that lot of 10.132 -0.11-0.then there will be few failures on that measurement.12-0.13.12-0.349 Outliers 0. more good devices will fall beyond the guardband region and be disqualified. Measurement Accuracy 119 YIe .105 :.1&-0. and production yield.145 -0.11-0.'.396 n 7 047 t . As explained in Section 4.10-0. In other words.:.13-0.1&-0.124 Figure 4.3.' .14-0.000parts are tested and only 7. But if the distribution of readings on a production lot of devices is skewed so that it is close to one of the test limits.144 -0. then production yields are likely to fall.000 devicesis 70%.3.15-0.137 dB -0. If 10.140 -0.135 -0. If a device is well designed and a particular measurementis sufficiently repeatable.14-0.1&-0.: dB Figure 4.131 -0. .148 -0.129 -0.142 -0.13-0.'.

1 it was shown that averaging or filtering a measurement can make it more repeatable. 8 mV. We have examined many contributing factors leading to inaccuracy and nonrepeatability. digital pattern generators. Measurement repeatability can be enhancedthrough averaging and filtering. 7 mV. The test engineer and design engineer should work together to achieve an optimum balance between low silicon overhead with minimal power consumption and low test cost with minimum averaging. 5 mV. On the other hand. Test costs can be dramatically reduced with well-centered designs with plenty of margin. and their combined effects on test time and production yield. A 5-mV signal is measuredwith a meter ten times. how many devices passedthe test? ADS. Doing so while n. at the expense of added test time.taintaining low test times and high yields is the mark of a great test engineer.3. In the next chapter. We will study the various types of instruments such as waveform digitizers.5 SUMMARY In this chapter we have introduced the concept of accuracy and repeatability and shown how these concepts affect device quality and production test economics. 1. 4 m V. The constant balancing act between adequaterepeatability and minimum test time representsa large portion of the test engineer's workload. repeatability. .120 An Introductionto Mixed-Signal'ICTestand Measurement In Section 4. centering the design between test limits and making the design insensitive to process variations might make it unnecessaryto achieve such accuracy and repeatability. It might seem that this fundamental topic should have been presented in an earlier chapter. Only by working as a team can these two engineering disciplines produce a cost-effective product that will succeedin the marketplace.22. One of fundamental skills that separatesgood test engineers from average test engineers is the ability to quickly identity and correct problems with measurementaccuracy and repeatability. we will take a brief vacation from mathematical equations to examine the measurement instrumentation and other architectural features common to many mixed-signal ATE testers. Exercises 4. 6 mV.000 devices are tested with a yield of 63%. Using software calibrations. What is the mean value? What is the standarddeviation? Ans. If 15. arbitrary wavefonn generators.2 mY. we can eliminate or at least reduce many of the effects leading to measurement inaccuracy. 9 mV. 4. and other mixed-signal ATE instruments.887 mY. well-centered designs with good margin are often power hungry or silicon area intensive.21.with the unfortunate consequenceof longer test time. The subject has been delayed until Chapter 5 becausemany of the architectural features of mixed-signal testers are easierto understandin the context of accuracy. resulting in the following sequence of readings: 7 mV. 11 mV. 7. 8 mV. Unfortunately. 4. 7 mV. 9450 devices.

what is the gain and offset of this filter-buffer stage? 4.121 V when connectedto two highly accurate reference levels of -1 V and IV. What is the offset and gain of this meter? Write the calibration equation for this meter.5. 48 mY. At input levels of 1 and 3 V.9. However. Assuming linear behavior. What are the gain calibration factors? What voltage levels would we request if we wanted an output level of 500 m V RMS at each frequency? 4.25 V to within a:l: 0. 55 mY. This RC circuit is used to filter the output of a DUT containing a noisy DC signal. Measurement Accuracy 121 Problems 4. If the meter produces a reading of 0.Chapter 4 . 4..10.2 ~F. :1:250 mV.8. detennine a value of the programmed source voltage that will establish a measuredvoltage of 1. What is the averagemeasuredvalue? What is the systematic error? 4. only 1. A DC voltmeter is rated at 14 bits of resolution and has a full-scale input range of:l:5 V. Using the setup and results of Problem 4. what is the minimum and maximum DC levels that might have been present at the meter's input during this measurement? 4. etc. Using iteration.02 and 3.242 V is measured.039 mV and 1. Assuming that quantization error is the only source of inaccuracy in this meter.1. An AWG has a gain response described by G(J)= f:j!ij 1 f 1+ (4000) 2 and is to generate three tones at frequencies of 1. A 100 mV signal is to measuredwith a worst-case error of:l:lO ~V. what is the maximum quantization error that we can expect from the meter? What is the error as a percentageof the meter's full-scale range? 4. 49 mY. 57 mY. 60 mY. A simple RC low-pass circuit is constructed using a I-ill resistor and a 10-Jif capacitor. how many bits of resolution would this meter need to have to make the required measurement? If the meter in our tester only has 14 bits of resolution but has binary-weighted range settings (i. the output was found to be 1. mV.) how would we make this measurement? 4.8. A voltmeter is specified to have an accuracy error of :1:0. what is the calibrated level when a 2. 4.00 I V PROGRAMMED2 .25 V. what is the RMS noise voltage that appearsat the output of the RC filter? If the we decreasethe capacitor value to 2. 54 mY. A meter reads -1.5 mV accuracy. 58 mY.13 V level is measuredat the filter-buffer output? What is the size of the uncalibrated error? 4.6.007 V PROGRAMMED) and is required to generatea DC level of 1. Assuming the meter's ADC is ideal. 57 mY. and 3 kHz. A DC source is assumed characterized by a third-order equati. 61 mV. respectively.004 + V PROGRAMMED + 0.3.33 V.4. 2.7.Jfu. :1:1 :1:500 V.2. A DC voltmeter is set to a full-scale range of:l:l V.0. If the DUT's noise voltage has a constant spectral density of 100 nV /. what is the RMS noise voltage at the RC filter output? .1 of full-scale range on a :1:1% V scale.e.on of the fonn: V MEASURED = 0. respectively. Several DC measurementsare made on a signal path that contains a filter and a buffer amplifier. A 55-mV signal is measuredwith a meter ten times resulting in the following sequenceof readings: 57 mY.323 V DC. when programmed to produce this level.

97075. .1993. Audio Precision. 6 p. How much settling time does the first RC filter in Problem 4. Beaverton. ISBN: 1880156067. assumingthe test time is dominated by the settling time of the low-pass filter? 4. Electronic Instrumentationand MeasurementTechniques.. The DUT in Problem 4. Fourth Edition. 1230Avenueof the Americas. Moorehead. Rudolf F.11. Kiemele. Graf. William David Cooper. Assume that the more repeatable DC offset measurementin Problem 4. 2nd Edition.6. Albert H. NY. assuming it passesall tests. Air AcademyPress. CO. 5.10 to settle to within 0.of the histogram of a repeated series of identical DC measurements on one DUT is proportional to the RMS noise at the meter's input. Webster's New WorldDictionary. New York. TheNewAmericanRoget'sCollegeThesaurus. August1995. Schmidt. 1633Broadway. New York.Audio Measurement HandboQk. 0". Does the extra yield obtained with the lower filter cutoff frequency justify the extra cost of testing resulting from the filter's longer settling time? References 1. 10020. 10019. Assume that we want to allow the RC filter in Problem 4.1985. August. A DC meter collects a series of repeated offset measurementsat the output of a DUT. Toolsfor Continuous Improvement.10 require? Is the settling time of the second RC filter greater or less than that of the first filter? 4. it cannot be sold at all. Also assumethat the cost of testing is known to be 3. NY.MA. Modern Dictionary of Electronics.2 pp. Assume the difference between the maximum and minimum measuredvalues is roughly equal to 60: How much would we need to reduce the cutoff frequency of the low-pass filter to reduce the nonrepeatability of the measurementsfrom 50 to 10m V? What would this do to our test time. causing the production yield to rise from 92% to 98%. A first-order low-pass filter such as the one in Problem 4.ISBN: 0132517108.12 can be sold for $1. A histogram is produced from the repeated measurements. Inc.al.Prentice Hall. StephenR. It can be shown that the standard deviation. 147 4.463 pp. 6.10 is connectedbetween the DUT output and the meter input. The histogram shows a Gaussian distribution with a 50-mV difference between the maximum value and minimum value.12 results in a narrower guardband requirement.. If it does not pass all tests. New American Library. Simonand Schuster. Mark J.5 cents per second and that the more repeatablemeasurementadds 250 ms to the test time.1997. et. ISBN: 0750698667. Englewood Cliffs.NewnesPress. 1.ColoradoSprings. 3. Berdine.p. 1999.25. 5.2% of its final value before making a DC measurement. 5. Basic Statistics. Inc. Suite105.12.13. 9-71 pp..122 An Introductionto Mixed-Signal Testand Measurement IC 4. 80920.1155Kelly JohnsonBlvd. July. 1978. NJ.Boston. OR. Bob Metzler. 2. Ronald J.584 pp.

Unlike the ubiquitous PC. waveform digitizers. the cellular telephone base-band interface shown in Figure 1. However. and general-purpose ADCs and DACs. the same mixed-signal tester may be expected to test video palettes. The mixed-signal production tester cannot be focused toward a specific type of device if it is to handle a variety of DOTs.DC meters. the tester would soon resemble Frankenstein's monster and would be prohibitively expensive. relay control lines. clocking and synchronization sources. the tester must emulate this type of equipment using a few general-purpose instruments.1 MIXED-SIGNAL TESTER OvERVIEW .1 shows a generic mixed-signal tester architecture. testers are not at all standardizedin architecture. On any given day.2 Generic Tester Architecture Mixed-signal testers come in a variety of "flavors" from a variety of vendors. General-purposemixed-signal testers must be capable of testing a variety of dissimilar devices. It would be possible to install one of these stand-alone boxes into the tester and communicate with it' through an IEEE488 GPffi bus. Each ATE vendor adds special featuresthat they feel will give them a competitive advantagein the marketplace. The instruments are combined with software routines to simulate the operation of the dedicatedbench instruments. Consequently.1.1. data transceivers. and a digital 111 . relay matrix lines. Figure 5.2 may require a phase trajectory error test or an error vector magnitude test. Instead of implementing tests like phase trajectory error and error vector magnitude using a dedicated bench instrument.CHAPTER Tester Hardware 5.most mixed-signal testerssharemany common features. a test routine implemented on one type of tester is often difficult to translate to another tester type because of subtle differences in the hardware tradeoffs designed into each tester. The test requirements for these various devices are very different from one another.1 General-Purpose Testers versus Focused Bench Equipment. In this chapter. 5. mixed-signal testers from different vendors do not use a common software platform. Dedicated bench instruments can be purchased that are specifically designed to measure these application-specific parameters. It includes system computers. DC sources. time measurementhardware. 5. cellular telephone devices. For example. we will examine these common features without delving too deeply into specific details for any particular brand of tester. Furthermore. arbitrary waveform generators. if every type of DUT required two or three specialized pieces of bolton hardware. Nevertheless.

1. Digital vector sequencer Capture memory Source memory Waveform data from tester computer User computer Digital vec t or memory Timing and formatting Waveform data to tester computer or array processor Tester computer Digital pin cards Array processor Time DC sources Relay matrix and other interconnects t Sine er Clocks and synchronization Figure 5. This chapter will briefly examine the operation of each of these tester subsystems. .124 An Introductionto Mixed-SignalIC Testand Measurement subsystem for generating and evaluating digital patterns and signals. Genericmixed-signal testerarchitecture.

4 and 4. A tester may also provide a slower. this slower instrument may not be usable for production tests becauseof the longer measurementtime. However. a programmable gain amplifier (PGA) for input ranging. Figure 5. Tester Hardware 125 5. The high impedanceavoids potential DC offset errors causedby bias current leaking into the meter. .2. a low-pass filter.8). ~~~~~~ ~ Low-pass filter current sources : D}fferential to single-ended converter (instrumentation Range control amplifier) r-r~:~:~:l. leakage currents.I~ ~"""--=:=~ Meter result DC multimeter.8. very high-accuracy voltmeter for more demandingmeasurements such as those needed in focused calibrations. Tbe meter can also measure current flowing from any of the DC sources.2.2. The instrumentation amplifier provides a high-impedance differential input.Chapter 5 . The fast. This capability is very useful for measuring power supply currents.1 General-Purpose Multimeters Most testers incorporate a high-accuracy multimeter that is capable of making fast DC measurements. General-purpose . a high-linearity ADC. A more detailed DC multimeter structure is shown in Figure 5.2. Input selection multiplexer Normal inputs Voltage I { { + + + + - Sample and difference PGA :.L//--~~_. l~l . and other common DC parametric values.1. It also includes an input multiplexer stage to select one of several input signals for measurement. A PGA placed before the meter's ADC allows proper ranging of the instrument to minimize the effects of the ADC's quantization error (see Sections 4. A very simple DC voltmeter block diagram was presentedin Figure 4. general-purpose multimeter is used for most of the production tests requiring a nominal level of accuracy. The multimeter can also be connected to any of the tester's general-purpose DC voltage sources to measure their output voltage. and a sample-and-difference stage. This meter can handle either single-ended or differential inputs. integration hardware. Its architecture includes a high-impedance differential to single-ended converter (instrumentation amplifier).the low end of the meter may be connectedto ground through relays in the input selection multiplexer. impedances.2 DC RESOURCES 5. For single-endedmeasurements.

Finally. It also features a sample-and-difference front-end circuit. assuming the quantization error from the first measurement is positive. Example 5.35 V DUT output signals. Assuming all components in the meter are perfectly linear (with the exception of the meter's quantization error).!. resulting in a high-resolution measurementof the difference voltage. The lowest meter range that will accommodate a 5-mV signal is :!:10 mY. (~ ) .3. some meters may include an integration stage.a hardware samp1eand-hold circuit samples a voltage.35 V :t 10 mV. This filter can be enabled or bypassed using software commands. Solution: The simplest way to measureoffset using a single-ended DC voltmeter is to connect the meter to the OUTP output. and:!:l mY.:!:l V. a sample-and-difference stage is included in the front end of many ATE multimeters. :!:lO mY. Thus each measurementmay have a quantization error of as much as :!:.44 mV. This first reference voltage is then subtracted from a second voltage (near the first voltage) using an amplifier-based subtractor. we could range the meter input to the worst-case difference between the two outputs. Since we have a specification limit of ::!:5mV. = ::!:2. Therefore. and subtract the second voltage from the first (see Example 3.88mV. Using the sample-and-difference circuitry. We wish to use this meter to measurethe differential offset voltage of a DUT's output buffer. assuming a good device. 2 2 -1 Therefore.1). The difference between the two voltages is then amplified and measuredby the meter's ADC. this will be an unacceptable test method. giving us a compromise between accuracy and characterization flexibility. our total error might be as high as ::!:4.1 A single-endedDC voltmeter has a resolution of 12 bits. Each of the two outputs is specified to be within a range of 1. measure its voltage. we also need to be able to collect readings from bad devices for purposesof characterization. This process reduces the quantization error that would otherwise result from a direct measurementof the large voltages using the meter's higher voltage ranges. connect the meter to the OUTN output. Using this approach.126 An Introductionto Mixed-Signal TestandMeasurement IC The meter may also include a low-pass filter in its input path. we have to set the meter's input range to :!:10 V to accommodatethe 1. During the first phase of the measurement. :!:100 mY. we will choose a range of :!:100mV. which is 5 mV. while the quantization error from the second measurementis negative. compare the accuracy achieved using two simple DC measurementswith the accuracy achieved using the sample-and-differencecircuit. which acts as a form of hardware averaging circuit to improve measurementrepeatability.4). The meter input can be set to any of the following ranges: :!:lO V. improving the repeatability of DC measurements. The low-pass filter removes high-frequency noise from the signal under test. and the differential offset is specified to be ::!:5mV . measure its voltage. The samp1e-and-differencestage allows highly accurate measurements of small differences between two large DC voltages. It may also have a programmable cutoff frequency so that the test engineer can make tradeoffs between measurement repeatability and test time (see Section 4. In addition. However.

2. I . these supplies can be switched to multiple points on the DIB board using the tester's DC matrix (see Section 5. . This servesto reduce the effects of the meter's quantization error. 018. On most testers. 12 o + " 2 2 -1 which is well within the requirements of our measurement. 2 . a 100-mV difference between OUTP and OUTN will produce a full-scale 10 V input to the meter's ADC. The voltage drop would be proportional to the current through the DUT load (RLoAD).Chapter5 . the small resistance in the force line interconnections (RTRACE-H RTRACE-L) and would cause a small IR voltage drop. The maximum error is given by:t.and low sense) for forcing highly accurate DC voltages.4 . I . and OUT High force RTRACE-H i DAC +: I . General-purpose sourcewith Kelvinconnections RTRACE-L DC (conceptual diagram). Figure 5. . high sense. ( ) 5. : ~ Low force .3 shows a conceptual block diagram of a DC source having a differential Kelvin connection.~ : . or :t24 .the voltage at the OUTN pin is sampledonto a holding capacitor internal to the meter. commonly referred to as VII sources or DC sources. Many general-purpose supplies can force either voltage or current. These programmable power supplies are used to provide the DC voltages and currents necessary to power up the DUT and stimulate its DC inputs. I I I I \ 'I . our worst-case error IS twice thIS amount.uV. : Figure 5.1 100 mY =:t12.2. I . I Interconnect cabling. low force. Tester Hardware 127 During the first phase of the sample-and-differencemeasurement. I I I I I I : Highsense I I I I I I I : DC source : Low sense R LOAD : .uv.The small Desired voltage .5). the system's general-purposemeter can be connected to any DC source to measure its output voltage or its output current. . Without the Kelvin connection. A differential Kelvin connection consists of four lines (high force.3. depending on the testing requirements. The Kelvin connection forms a feedback loop that allows the DC source to force an accurate differential voltage through the resistive wires between the source and DUT.2 General-Purpose Voltage/Current Sources Most testers include general-purpose DC voltage/current sources. . I : . Then the meter is connected to the OUTP pin and the secondphaseof the measurementamplifies the difference between the OUTP voltage and the sampled OUTN voltage. Agam. Since the meter is set to a range of :tlOO mV. As mentioned in the previous section.

Testers may also include nonprogrammable user power supplies with high output current capability. These fixed supplies provide common power supply voltages (:tS V. since it connects the DUT's ground voltage back to the tester's instruments for use as the entire test system's 0 V "golden zero reference. Therefore. or some other vendor-specific nomenclature. Often.5 Relay Matrices A relay matrix is a bank of electromechanical relays that provides flexible interconnections between many different tester instruments and the DUT. :tIS V. they are immune to errors causedby IR voltage drops. or a connection to a . The purpose of a calibration source is to provide traceability of standardsback to a central agency such as the National Institute of Standards and Technology (NIST). This allows Dill circuits to operate from inexpensive fixed power supplies having high current capability instead of tying up the tester's more expensive programmable DC sources. The old calibration source is replaced by a freshly calibrated one so that the tester can continue to be used in production. The calibration source must be recalibrated on a periodic basis (six months is a common period).) for Dill circuits such as op amps and relay coils. At different points in a test program. respectively. This is one of the most important signals in a mixed-signal tester. in the output of the converter. The low-side sense line counteracts the parasitic resistance in the current return path. low-noise voltage references. Any noise and DC error on the DC reference of an ADC or DAC translates directly into gain error and increased noise. Clearly. an AC waveform. These voltage sources can be used in place of the general-purpose DC sources when the noise and accuracy characteristics of the standard DC source are inadequate. 5. A senseline is provided on the high side of the DC source and also on the low side of the source. all the instruments will produce DC voltage offsets. Also. the low senselines for all the DC instruments in a tester are often lumped into a single ground sense signal called DZ (device zero). DGS (device ground sense).2. The sense lines of a Kelvin connection carry no current. but they all perform a similar task.2.128 An Introductionto Mixed-Signal TestandMeasurement IC IR voltage drop would result in errors in the voltage across the DUT load. a particular DUT input may require a DC voltage." If any voltage errors are introduced into this ground reference signal relative to the DUT's ground. this is a highly tester-specific topic.2. the high-accuracy multimeter serves as the calibration source. etc. the source is removed from the tester and sent to a certified standardslab for recalibration.2. There may be several types of relay matrix in a tester. On some testers. A precision voltage reference is sometimesused to solve this problem.4 Calibration Source The mixed-signal tester's calibration source was discussedin detail in Section 4.3 Precision Voltage References and User Supplies Mixed-signal testers sometimes include high-accuracy. Calibration and standardstraceability is discussedin more detail in Chapter 10. One common example of a precision voltage reference application is the voltage reference for a high-resolution ADC or DAC. some testers may have multiple instruments that serve as the calibration sourcesfor various parameters such as voltage or frequency. "Focused Calibrations. 5. Since most instruments are referenced to ground." 5.

the purpose and functionality of a general-purposerelay matrix depends on the test engineer's DIB design. They have no hardwired connections to tester instruments.5.. DIB connections r--""'--~ Voltmeter + VoltmeterDC source 1 DC source 2 DC source 3 DC source 4 Digitizer 1 Etc. In addition to relay matrices. General-purpose relay matix. General-purposerelay matrices are used to connect and disconnect various circuit nodes on the DIB board. . voltmeter.4. It allows flexible interconnections between specific tester instrumentsand pins of the DUT through connections on the DIB board. and signal paths varies widely from one ATE vendor's tester to the next. A more instrumentspecific matrix is shown in Figure 5. Tester Hardware 129 DIB connections D'B r ~ connections Figure 5. matrices. Therefore.4. A general-purpose4 x 4 relay matrix is shown in Figure 5. A relay matrix allows each instrument to be connected to a DUT pin at the appropriatetime.Chapter5 ..5. The exact architecture of relays. many other relays and signal paths are distributed throughout a mixed-signal tester to allow flexibility in interconnections without adding unnecessaryrelays to the DIB board. Instrument relay matrix. Figure 5.

. many engineers consider it good practice to add extra flyback diodes even though they ake up quite a bit of DIB board space. Many test engineers also add flyback diodes across the coils of the relay. there is no better way to get a low-noise ground signal to the input of a DUT than to provide a local relay placed on the DIB directly between the DUT input and the DUT's local ground plane. The DIB traces are. The extra diode is probably redundant.6. Local DIB relays are also used to connect device outputs to various passive loads and other DIB circuits. Relaycoil driverwith flybackprotection diodes. Certainly it is possible to feed the local ground through a DIB trace. Relay coils produce an inductive kickback when the current is suddenly changed between the on and off states. The relay coils are driven by the tester's relay control lines. through a remote relay matrix. A relay control line driver is shown in Figure 5. I Figure 5. the test engineer can choose slightly more expensive relays with built-in flyback diodes. The test program controls the local DIB relays. : 1 : ' : ' I on OIB +12V Relay : . Local DIB relays minimize the radio antenna effect. is induced according to the inductance formula v(t) = L di lat. its output circuits contain flyback protection diodes to shunt the excess voltage to a DC source or to ground. : : Readback comparator I 1 . Since high kickback voltages could potentially damage the output circuits of the relay driver. after all. However. radio antennae. or flyback as it is known. The readback comparator allows a low-cost method for determining the state of a digital signal. and back through another DIB trace. Usually the need for a local DIB relay is driven by performance of the DUT.6 Relay Control Lines Despite the high degree of interconnection flexibility provided by the general-purpose relay matrix and other instrument interconnect hardware.130 An Introductionto Mixed-Signal Testand Measurement IC 5. On some testers. . Many noise problems can be traced to poor layout of ground connections between the DUT and its ground plane. : : : I Relay control signal : : OIB flyback Readback data TT' Y THRESHOW : I diode OIB .the control line is capable of reading back the state of the voltage on the control line through a readback comparator. but this connection scheme invariably leads to poor analog performance. d 10 es . there are always cases where a local DIB relay (placed near the DUT) is imperative.6.6. I I . as shown in Figure 5.2. : I I : : . To eliminate the board spaceissue. .-: I : I : . . Relay driver card ---- --- +12V ---------Built-In flyback d. The inductive kickback. For example. : : . . opening and closing them at the appropriate time during each test.

Digital signals are distinct from digital vectors in that they typically carry analog signal information rather than purely digital information.2 Digital Signals In addition to the simple pass/fail digital pattern tests. Each drive/compare cycle is called a digital vector.1 Digital Vectors A mixed-signal tester must test digital circuits as well as mixed-signal and analog circuits.3 DIGITAL SUBSYSTEM 5. low. The digital subsystemcan present high. It can also compare the outputs from the DUT against expected responses to determine whether the digital logic of the DUT has been manufactured without defects. the tester must also be capable of sourcing and capturing digital signals. The vectors of a digital pattern are usually sourced at a constant frequency. Each cycle of therepeating digital patternis calledaframe. The ability to changedigital timing on a vector-by-vector basis is commonly called timing on thefly. Usually.3. and high-impedance (HIZ) logic levels to the DUT. . An example digital pattern for testing a simple 3-bit counter is shown in Figure 5. Digital signals are digitized representations of continuous waveforms such as sine waves and multitones.7.3. Tester Hardware 131 5. The mixed-signal and digital-only sections of the DUT are exercised using the tester's digital subsystem.Chapter 5 . A series of digital vectors is called a digital pattern. 5. the samples of a digital signal must be applied to a DUT along with a repetitive digital pattern that keeps the device active and initiates DAC and/or ADC conversions. although some testers allow the period of each vector to be set independently. The tester applies a sequenceof drive data to the device and simultaneously compares outputs against expectedresults.7. RC El S0 ECQQQ TK210 VECTOR LABEL COMMAND 0000000 TEST_COUNTER: ~~~ -~ TSET S S S S S COMMENT 1 0 0 XXX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X Reset Counter l L L Check for' all O's L l l l l l Release Reset l l H Test for 001 XXX l H l Test for 010 XXX l H H Test for 011 XXX H L L Test for 100 XXX H l H Test for 101 X XX H H L Test for 110 XXX H H H Test for 111 XXX L l L Test for wrap XXX 0000001 0000002 0000003 0000004 0000005 0000006 0000007 0000008 0000009 0000010 0000011 0000012 0000013 0000014 0000015 0000016 0000017 0000018 0000019 0000020 HALT Figure 5. Digital pattern for 3-bit binary counter.

3 Source Memory When testing DACs. The ability to quickly modify the digital signal data is especially useful during the DOT debug and characterization phase. the digital signal samples representing the desired DAC analog wavefonn are typically computed in the tester's main test program code. In the caseof ADC testing. 5. One of the main differences between a mixed-signal tester and a digital tester with bolt-on analog instruments is the presence of source and capture memories in the digital subsystem. Looping frames are commonly used when testing DACs and ADCs. The addresspointer for source memory is incremented by one sample each time through the frame loop so that a series of different samplescan be sent to the DAC. Because its data are generated algorithmically by the main test program. This would be impossibly cumbersome if the digital pattern had to be generatedusing an expanded. For example. depending on the contents of source memory. a DAC may nonnally be testedusing a I-kHz sine wave digital signal. a long sequenceof waveform samples can be sent to or captured from the DOT with a very short digital frame pattern. The digital frame data. The digital signal samples are stored into a digital subsystem memory block called source memory (or send memory in some testers). a digital signal can be modified quickly without changing the frame loop pattern. Capture memory serves the opposite function of source memory.3. Each W may be either high or low during each loop of the frame. During the DAC characterization phase.132 An Introductionto Mixed-Signal Testand Measurement IC During a mixed-signal test. some tester architectures attempt to substitute deep.the digital output from the device is stored into the capture memory. the repeating frame vectors must be combined with the nonrepeating digital signal sample information to form a repetitive sampling loop. are stored in vector memory. Ws are placed wherever analog waveform sample data is to be supplied by source memory. This pattern shows a combination of a looping frame of ones and zeros combined with digital signal placeholders (W symbols in this example). nonlooping vector memory in place of source memory.nonlooping sequenceof ones and zeros. Each time the sampling frame is repeated. the contents of the vector memory and source memory are spliced together in real time as the digital pattern is executed. but it invariably results in frustrated users.3. An example digital pattern for a DAC sine wave test is shown in Figure 5. however.8. To generatea repeating frame with a new sample for each loop. 5. the frequency might be swept from 100 Hz to 10 kHz to look for problem areas in the DAC's design. In effect. Other differences will be pointed out throughout this chapter. Once a complete set of samples . The capture memory address pointer is incremented each time a digital sample is captured. This may reduce the cost of tester hardware. on the other hand. Combining the digital frame vectors with digital signal data.4 Capture Memory Devices such as ADCs produce a seriesof digitized waveform samplesthat must be captured and stored into a bank of memory called capture memory (or receive memory). digital signals must be captured and stored into a bank of memory as the looping frame initiates each ADC conversion. In fact. A sequenceof samples must be loaded into a DAC to produce a continuous sequenceof voltages at the DAC's output. the sampling frame results in a type of data compression that minimizes the amount of vector memory needed for the tester's digital subsystem.

they are transferred an array processor to the tester computerfor to or analysis.A simpleADC sinewavetestpatternis shownin Figure5. COMMAND SET LOOP 256 !*UDAC Most Significant Byte*! lpudac: NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT SEND NO_HALT SHIFT NO_HALT NO_HALT Frame NO_HALT NO_HALT loop NO_HALT (repeats LABEL pi n SDATA dig_src S D A TEL pi n A PLFDIG1_H DIG_BI plfdig TSET (S) TRIG 1 0 0 1 0 1 1 1 0 1 0 0 w w 0 0 0 0 0 0 0 S S DC NK -0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S S COMMENT 1 0 1 1*1 0 1*/ 0 1*1 0 0 0 1*1 0 0 0 0/*1 0 0 0 0 Toggle sdata for mod+ Mode Select 1 *1 Chip Address LSB 1 *1 Register Address LSB+ Data word LSB 1 *1 ~ ~ ~ 1 I 0 frame vectors ~8:::~~ti 256 times) !*UDAC Least Significant Byte*! NO_HALT NO_HALT ' NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT SHIFT NO_HALT SHIFT NO_HALT SHIFT NO_HALT SHIFT NO-HALT SHIFT NO_HALT SHIFT NO_HALT SHIFT NO_HALT SHIFT NO_HALT REPEAT 559 END_LOOP lpudac HALT 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1 1 0 0 W' W W W W W W W 0 1*1 Toggle sdata for mod+ 1*1 Mode Select 1 *1 1*1 Chip Address LSB 1 *1 1*1 Register Address LSB+ 1*1 Data word LSB 1 *1 . Tester Hardware 133 havebeencollected.f..8. DAC datasourcing pattern.g~ 1 1 0 DAC sample bits sourced Figure5.Chapter 5 .9. test .

134 An Introductionto Mixed-Signal TestandMeasurement IC LABEL I*ADC lpadc: COMMAND SET LOOP 256 Most Si gni fi cant NO_HALT NO_HALT pin pi n PLFSRC1_H SDATA plfsrc dig_cap START Byte* I (? TRIG 5 D A TEL A DIG_BI TSET (5) 1 0 0 1 1 1 1 1 0 1 0 0 X X 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 X X X X X X X X 0 5 5 DC NK 5 5 COMMENT -0 0 1 1 1 1 1 1 1 1 1 1 1 1 ~ NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO HALT NO::::HAL T I*ADC SHIFT ~ cHIFT 1 0 1 0 0 0 0 0 0 0 0 0 0 0 ~ /*/ /*/ /*/ /*/ Toggle sdata for mod+ Mode Select / */ Chip Address lSB / */ Register Address lSB+ /*/ Data word lSB / */ Frame loo p 10 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ~ 1 / 0 frame vectors (repeats NO_HALT 256 times) 1 NO HALT Least Significant Byte*1 NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO-HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO_HALT NO HALT REPEAT 559 END_L~ lpadc HALT /*/ /*/ /*/ /*/ Toggle sdata for mod+ Mode Select / */ Chip Address lSB / */ Register Address lSB+ SHIFT SHIFT SHIFT SHIFT SHIFT SHIFT SHIFT /*/ Data word lSB / */ "4-f-&~ 1 1 0 ADC sample bits captured {t ~HIFT '6ORE Figure 5. ADCdatacapturetest pattern. A pin card electronics board may actually contain multiple channels of identical circuitrY.5 Pin Card Electronics The pin card electronics for each digital channel are located inside the test head on most mixedsignal testers.3. a programmable . Each channel's circuits consist of a programmable driver.9. 5.

then the output state is considered a midpoint voltage. Tester Hardware 135 500 driver -I-" l . The driver can also switch into a highimpedancestate (HIZ) at any point in the digital pattern to allow data to come from the DUT into the pin card's comparator. Thus there are typically three drive states (HI. and HIZ) and five compare states (HI. The driver circuits may also include programmable rise and fall times. we can set the tester to expectvalid logic levels during the appropriate digital vectors without specifying whether the . If we want to test for valid VOHand VoL voltages from the output of a nondeterministic circuit such as an ADC. Normally the fixed rise and fall times are designedto be as fast as the ATE vendor can make them. DC matrix comparator.Chapter5 . and MASK). This is because electrical noise in the ADC and tester will produce somewhat unpredictable results at the ADC output. one for the VOHlevel and one for VOL.various relays. The pin card comparator is actually a pair of comparators. These are also controlled by another pair of DACs whose voltages are controlled by the test program.then the signal is considered a logic low. However. If the DUT output is between these thresholds. dynamic current load circuits. If the DUT is above VOH. LO.10. If it is outside these thresholds. Digital pin card circuits. A generic digital pin card is shown in Figure 5. f1 ~ 0 ~ D~T pin Calibration circuits Per-pin force and measure circuits Figure 5. then it is considered a logic high. we cannot set the tester to expect HI or LO. VOH and VoL. though fixed rise and fall times are more common. The usefulness of the valid comparison is not immediately obvious. The driver circuitry consists of a fixed impedance driver (typically 50 0) with two programmable logic levels. The comparator also has two programmable logic levels. Compariltor results can also be ignored using a mask. If the DUT signal is below VoL.10. Rise and fall times between 1 and 3 ns are typical in today's testers. These levels are controlled by a pair of driver level DACs whose voltages ar~ controlled by the test program. then it is considered a valid logic level. and other circuits necessary to drive and receive signals to and from the DUT. LO. VIH and VII. VALID. and MID.

The per-pin circuits also include a relatively low-resolution voltage/current meter. The per-pin measurementcircuits of a pin card form a low-resolution. The overshoot and undershoot characteristics are the result of a low impedance DUT output driving into the DIB traces and coaxial cables leading to the digital pin card electronics.3.12. Some testers may also include overshoot suppression circuits that serve to dampen the overshoot and undershoot characteristics in rapidly rising or falling digital signals. low-current DC voltage/current source for each digital pin. most ATE testers apply timing and formatting to the ones and zeros to create more complicated digital waveforms while minimizing the nUI)1berof ones and zeros that must be stored in pattern memory. These DC source and measure circuits can also be used for other types of simple DC tasks like input or output impedancetesting. The diode bridge forces a programmable current into the DUT output whenever its voltage is below a programmable threshold voltage.11 require four times as much 1/0 information and four times the bit cell frequency to achieve the same digital waveform as the formatted data.136 An Introductionto Mixed-Signal TestandMeasurement IC ADC should produce a HI or a La. including calibration of the pin card electronics during the tester's system calibration process. it is easy to interpret the ones and zeros very literally. The programmable drive start and stop times illustrated in Figure 5. Timing and formatting is a type of data compression and decompression. However. The exact details of these connectionsvary widely from one tester type to another.11 are generated using digital delay circuitry inside the formatter circuits of the tester. A dynamic load is a pair of current sources connected to the DUT output with a diode bridge circuit as shown in Figure 5. Another extremely important function that a digital pin card provides is its per-pin measurementcapability. The sink and source current settings correspondto the DUT's 10HandloL specifications (see Section 3. digital pin cards may also include dynamic load circuits.The pattern data are formatted using the ATE tester's formatter hardware.11 shows how the pattern data are combined with timing and formatting information to create more complex waveforms. In addition to the drive and compare circuits. While the pin card tests for valid logic levels. Drive and compare timing is . The ringing is minimized as the signal overshoot is shuntedto a DC level through a diode. 5. It forces current out of the DUT output whenever its voltage is above VTH. Notice that the unformatted data in Figure 5. VTH.10. These connections can be used for a variety of purposes.4). This gives us better control of edge timing than we could expect to achieve using subgigahertz clocked digital logic. Figure 5. The low-resolution and low-current capabilities are usually adequatefor performing certain DC tests like continuity and leakage testing.6 Timing and Formatting Electronics When looking at a digital pattern for the first time. as if they represent all the information needed to create the digital waveforms. Another key advantage to formatted waveforms is that the formatting hardware in a high-end mixed-signal tester is capable of placing the rising and falling edges with an accuracy of a few tens of picoseconds. which is typically located inside the tester mainframe or on the pin card electronics in the test head. the samples from the ADC are collected into the digital capture memory for later analysis. Digital pin cards also include relays connected to other tester resources sucli as calibration standards and system DC meters and sources.

0 0 1 0 0 1 1 1 . . I 1nn~~!4-' I . 0 0 0 1 0 . . . . Strobe comparisons are performed at a particular point in time. are generated by an ATE tester's pattern generator. Two digital signals. . 1 . 1 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 0 1 81GA 0 0 0 1 . . 0 0 1 1 0 .. : . I 0 0 1 I 1 I . 1 '. 0 1 1 01000 0 0 0 0 1 1 0 0 0 00"1'101'1'0'0'0000000100 0 0 . " . 0 .. Window timing is typically used when comparing DUT outputs against expected patterns. . --.. Notice that certain formats such is as Clock High and Clock Low ignore the pattern data altogether. !L_--J--J---1L . ! . 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 . ! 1 . .. : I . the drive data sequence 110XOO. The pattern generator's vector rate (i. . I . Complement surround (CS) format . 0 0 0 0 ... . ' 0 : . . . . .. The compare data sequenceis HHLXLL. . 1 1 0 0 1 1 1 0 . . . . SIGA is programmed to RO . 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . .~.. while window comparisonsare performed throughout a period of time. 1 0 I 1 1 0 0 0 0 . .. .. . 0 1 1 0 0 0 0 . I . l .. . . . : . 1 0 . .11. 0 0 0 0 . J' .I SIGA : -J--l_-U-lJl__f1-1 : U--l_J-r-l__J1' I . ! :i1:1:0:1. 0 0 1 1 . . 10010' '001'10000'101'0010000010001'1'01110'0'10 1 0 0 0 1 ' 0 0 0 1 . I .. .. . 1 0 0 0 0 0 0 1 . this dependson the specific tester. . .. 1 0 .. 0 0 0 . --" ~ .e. Drivedatacompression usingformatsand timing.. I . . . 0 .. This notation is used for clarity in this book. In each case. . . 0 0 0 0101' 1 0 . " 0 . 1 1 0 0 0 Tester Hardware 137 + 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 +10 ns 1 1 1 0 0 1 0 0 1 . . 81GB '0'1'10 .. refined during a calibration process called deskewing. though it is not universally used in the test industry. 1 0 0 0 0 1 1 0 0 1 1 0 0 . 1 0 0 0 0 0 0 1 0 0 0 . 30n S Unformatted drive data Bit cells . Figure 5.. . Since digital pin cards can both drive and expect data.. Again. . ' 1 ' 1 ' 0 ' SIGB U '. . .Chapter 5 .. . . .. . . In fact. .. 0 1 0 0 0 0 0 1 .. . 1 0 1 1 1 000' . SIGA and SIGB. . '-' \ - 'in 11~ 10n s~~' ~ ~. some digital pattern standards define H/L as driven data and 1/0 as expecteddata. " . I .. " . . . a distinction is made between a driven signal (lor 0) and an expected signal (H or L). ! 0 : I ! Non-return-tozero (NRZ) format Formatted drive data (Same waveforms with 75% fewer data bits) Figure 5. .. . 1 1 1 n ..12 shows examples of several different formatting and timing combinations that createmany different waveforms from the same digital data stream. I . its bit cell rate) is set to 4 MHz. while strobe timing is typically used when collecting data into capture memory. . : . 1 1 . This allows subnanosecondaccuracy in the placement of driven edges and in the placement of compare times (called strobes and windows). . ' .

J! . I . . 1 ~ ~ I ' . ' . . . . . . . . . . . ' ' I . . . . . 1 : ' . X : ! . . 1 . 1 I ' ' ' ' I r--l ~ r--l ! I I rI ! . . . ' . . U~L. . . O : I .!--JY . . I . 1 !L--! : 0 ' . 0 rl I .e. . . . . I I I . . . . n' !L_-. . .13 shows the digital wavefonns resulting from the specified pattern and timing set. 0 ! . I . . . 0 . . -U--rLJTLITl__r-r-un-n' . ~ Windowed : ' H : H : ' . The start time for 81GA is programmed to 50 ns and the stop time is programmed to 125 fig. : ' . . 0 . I rI : r-l : r-l! I . . I ' Figure 5. . I I . (NRZ) ! . UL-. I X : ' I . . . . Also notice that NRZ fonnat does not have a stop time. I ! : : ' . I . . . . nonformated ones and zeros). . I I (CLKLO) . . 'Return-to-one 1 r--l " . 0 rl . . ' . I I . . 0 : ! I I . . all . . L : ' . . . What SRAM depth would be required to produce this same pair of signals? SIGA 0 0 1 0 1 SIGB I 0 I 1 0 Solution: Figure 5. while 81GB is programmed to NRZ fonnat. . . . . I ' . . L : ' . 0 . X iL-l!L-li ' . I Clock high (CLKHI) low . : . . 0 . I . i rI U I ' . I X ! I ' I . (RO) . : h h : : Complement : surround (CS) U . ' . 0 : ' . . 0 ' I . ! . I .LJL. I ~JTL-n--1:==::I!:I==I:I==I: ~ ! ' . . . : ' I . I . 1 ' . The start time for 81GB is programmed jo 25 ns and the stop time is programmed to 175 fig. so the bit cell period is 250 lls. . ' .zero . . ! ' . . .t o-zero (RZ) . I 0 . ~ : r--l ! !r-L . . ' I X . . . 0 r-h I' . . . . I . . . I . . ' I . . 1 . . . An Introduction to Mixed-Signal TestandMeasurement IC . 0 I ! ! . 1 ' . In this example. . .!--JL. . . . L : comparisons ' I . . ' R et urn. . . . . Draw a timing diagram for the two signals SIGA and SIGB produced by this pattern. . r . . I I . . . . The vector rate is specified to be 4 MHz. 0 . ' I I . The following digital pattern is executed. . . . . Its initial state is programmed to logic low. 'Clock . . . : N on-re i I : : : : : t urn- t 0- U . . . . ! . . I 1 I! ' . Show the bit cells in the timing diagram and calculate their period. I : 0 . . . .n I fLJTL . 1 ! rI L-LJ . Its initial state is programmed to logic high.!-JL. . 1 r--l . I . I . . . 1 : ' I . . 0 I . : ' . . . . .12. I .138 . I I . 1 . I ' . .. so the l75-ns stop time setting is irrelevant. . Assume that we want to produce this same pair of signals using a bank of static random access memory (SRAM) whose address is incremented at a fixed rate (i. . . . fonnat. Somecommon digitalformats. . . . .

l I : : SIGB : ---11 . . I Return . to one . 1 . Non-return. they are only able to measurea single frequency during each measurement. . . Tester Hardware 139 io4-: Stop = 125 ~: .2 Arbitrary Waveform Generators An arbitrary waveform generator (A WG) consists of a bank of waveform memory. .Chapter5 . ~ . . I . ' . : : time ns . The RMS voltmeter is equally simple to use. timing edges fall on 25-ns boundaries. '. . It is connected to the DUT output and the RMS output is measured with a single test program command. . . 0 : . ..4 AC SOURCEAND MEASUREMENT 5. ' . '. Using DSP-basedtesting. . . the arbitrary waveform generator and the waveform digitizer. . '. . '. : ns+ : . . . . I . these various signal componentsCan easily be separatedfrom one another. . '. . Starttime= 25 ns ~:"'-: " "1 " I ' .1 AC Continuous Wave Source and AC Meter The simplest way to apply and measure single-tone AC waveforms is to use a continuous wave source (CWS) and an RMS voltmeter. But the CWS and RMS voltmeter suffer from a few problems. a DAC that converts the waveform data into stepped analog voltages. '. we would have to source a sequenceof 6x(250 ns / 25 ns) = 60 bits from SRAM memory at a digital vector rate of 1/(25 = 40MHz. . Start time =50ns~ +250 SIGA! l__J-~_-Jr--~---r-U-! I' " . . DSP-basedmultitone testing is a far more efficient way to test AC performancebecausemultiple frequencies can be tested simultaneously. . 0 . This ability makes DSP-based testing more accurate and reliable than simple RMS-based testing. and a programmable low-pass filter . " 0 . .I. . . ns) 5. . . DSP-based testing is made possible with a more advanced stimulus/measurement pair. The CWS is simply set to the desired frequency and voltage amplitude to stimulate the DUT. .4. . : 0 I ' I ! 1 : Figure 5. . 5. . : I : : 1 : . . '' .4. I . 0 : . : ! . . . ' I 1 I I I ! 1 . As we will seein Chapters 6 through 9. . First.I!L i: I . . .13. I JJ : I . . . Another problem that the RMS voltmeter introduces is that it cannot distinguish the DUT's signal from distortion and noise.but in production testing it would lead to unacceptably long test times. This would be acceptable for bench characterization. If we wanted to generate this same pattern using nonformatteddata from a bank of SRAM clocked at a fIXed frequency. 'to-zero . . U. .Formatted usingreturn-to-one non-return-to-zero data and formats.

43 Waveform Digitizers An A WG converts digital samples from a waveform memory into continuous-time waveforms. The digitized samplesof the continuous waveform are collected into a waveform capture memory. "ADC Testing"). "Sampling Theory.14 shows a typical A WG and waveforms that might be seen at each stage in its signal path.15. A digitizer usually includes a programmable low-pass filter to limit the bandwidth of the incoming signal. It may also include differential outputs and DC offset circuits. (Mathematical signal samples are representedas dots to distinguish them from reconstructedvoltages. A digitizer performs the opposite operation.) An A WG is capable of creating signals with frequency components below the low-pass filter's cutoff frequency.5. which we will discuss in Chapter 6. "Sampling Theory. 5. Flexibility in signal creation is the main advantageof A WGs compared to simple sine wave or function generators. Arbitrary waveform generator." Like the DC meter. An AWG usually includes an output scaling circuit (pGA) to adjust the signal level. Waveform digitizers may also include a differential to single-ended conversion stage for measuring differential outputs from the DUT. The purpose of the bandwidth limitation is to reduce noise and prevent signal aliasing.14. Undersampling is explained in more detail in Chapter 6. section. Figure 5. "Sampling Theory. the digitizer has a programmable gain stage at its input to adjust the signal level entering the digitizer's ADC stage. Digitizers may also include a sample-and-hold circuit at the front end of the ADC to allow undersampled measurementsof very high-frequency signals. which smoothes the steppedsignal into a continuouswaveform." An A WG might create the three-tone multitone illustrated in Figure 4. - ~ Smoothed AWG signal Low-pass filter ~ Sin~le-end~d to differential buffer amplifier Out+ Out- Waveform source memory DAC Range control Figure 5. converting continuous-time analog waveforms into digitized representations. The structure of a typical digitizer is shown in Figure 5.140 An Introductionto Mixed-Signal Testand Measurement IC AWG samples " iV :'~-. The frequency components must also be less than one-half the AWG's sampling rate." . It might also be used to source a sine wave for distortion testing or a triangle wave (up ramp / down ramp) for ADC linearity testing (see Chapter 12. This minimizes the noise effects of quantization error from the digitizer's ADC. This so-called Nyquist criterion will be explained in the next chapter.

4.4 Clocking and Synchronization Many of the subsections and instruments in a mixed-signal tester derive their timing from a central frequency reference. such as frequency."V~. Tester Hardware 141 Amplified OUT siQnal Noisy OUT signal Filtered OUT signal Sampled OUT signal In+ In. can . Since the clocking frequencyfor each instrument derivedfrom a commonsource.frequencysynchronization possible. .1 Time Measurements Digital and mixed-signal devices often require a variety of time measurements.16 shows a clock distribution schemethat allows synchronized samplingrates between the DSP-based all measurement instruments.. and therefore setsthe frequency of the DAC or ADC sampling rates. accuracyand repeatabilityof all the DSP-based the measurementsa mixed-signal program in test would be degraded. The reason these clocks must all be synchronized will become more apparent in Chapter 6.15.Qe control . the digital patterns in the frame loops in Figures 5. 5. "Sampling Theory. A digital tester with bolt-on analog instruments often lacks a good clocking and synchronization architecture. Ran. "DSP-Based Testing.5 TIME MEASUREMENT SYSTEM 5. and propagation delay. jitter. and digital pattern generators is another of the key distinguishing features of a mixed-signal tester.5.Chapter 5 .9 are generated at a specific frequency. For example. The A WG and digitizer also operate from clock sources that must be synchronized to each other and to the digital pattern's frame loop repetition rate. rise and fall times.8 and 5. This frequency determines the repetition rate of the sampleloop. Figure 5." and Chapter 7. These parameters be measuredusing the ATE tester's time measurementsystem (TMS). digitizers. Without is is precisesamplingrate synchronization. duty cycle. skew./\Differential to single-ended instrumentation amplifier PGA . - Figure 5." Proper synchronization of sample ratesbetween the various A WGs. 5. Waveform digitizer.. period.

An undersampling digitizer is similar in nature to the averaging mode of a digitizing oscilloscope. It does little good to measure a rise time of 1 ns if the shapeof the signal's rising edge has been distorted by a 50-0 coaxial connection. Synchronization in a mixed-signal tester.5.e. Accurate timing measurmentsrequire a high-quality signal path between the DUT output and the TMS time measurementcircuits.16. . Thus nonperiodic features such as jitter and random glitches cannot be measured using an undersampling approach. It is equally futile to try to measure a 100-ps rising edge if the bandwidth of the TMS input is only 300 MHz..17 illustrates several of the time measurementcapabilities of a typical TMS. repeating waveform.) can sometimes be measured using a very high-bandwidth undersampling waveform digitizer. 5. Most TMS instruments are capable of measuring these parameters within an accuracy of a few nanoseconds. fall time.2 Time Measurement Interconnects One of the most important questions to consider about a TMS instrument is how its input and interconnection paths affect the shape of the waveform to be measured. rise time. Some of the more advanced TMS instruments can measure parameters such as jitter to a resolution of less than Ips. Figure 5. Unfortunately. undersampling digitizers require a stable. undersampling digitizers are often considerably slower than dedicated time measurementinstruments. etc. Like digitizing oscilloscopes.142 An Introductionto Mixed-Signal Testand Measurement IC Digital vector sequencer Digital vec t or memory Source memory Capture memory Digital signal in Digital signal out Clocks and synchronization Figure 5. Timing parameters that do not change from cycle to cycle (i.

the execution of the test program.Chapter5 ..1 ~?f-Period (or frequency) I+- ~/---~--- - IN OUT -J-1 =n ---=i-~/-- -~:~... The user computer is responsible for all the editing and compiling processes necessaryto debug a test program.6 COMPUTING HARDWARE 5. The test engineer is most familiar with the user computer. since this is the one which is attached to the keyboard. It is also responsible for keeping track of the datalogs and other data collection information....1 User Computer Mixed-signal testers typically contain several computers and signal processors.. the user computer may also drive the measurement electronics as well.1 1 +- Skew ~~~7-"'.---~-k-. On more advancedmainframe testers. including I/O functions to the tester's measurementelectronics..17.d---""'~/---"""--delay ~ ~ - OUT1 OUT2 OUT /-- """'?f"-- ~/---~--- - -..'~~_- +- Jitter(long term) - Figure 5. ..6. _L~~7--~\~~L. On low-cost testers. may be delegated to one or more tester computers located inside the tester's mainframe. Tester Hardware 143 ?( -..:I/--~ -. 5. Timemeasurements.

Distributed processing can reduce test time by splitting the DSP computation task among several processors throughout the tester. This can be one of the more challenging and interesting parts of a test engineer's task.6.7 SUMMARY In this chapter we have examined many of the common building blocks of a generic mixedsignal tester. However. and digital pattern generators. combined with digital signal processing. which the test engineer must deal with. though. Unfortunately. By concentrating most of its processing power on the test program itself. the tester computer can execute a test program more efficiently than the user computer. We will also explain why it is so critical to mixed-signal testing that we achieve precise synchronization of sampling frequencies bewteen all the tester's .144 An Introductionto Mixed-Signal Testand Measurement IC 5. Of course. 5. For example. 5. In some cases. This allows data and programs to be quickly transferred to the test engineer's desk for offline debugging and data analysis. Some mixed-signal instruments may even include local DSP processorsfor computing test results before they are transferred to the tester computer.3 Array Processors and Distributed Digital Signal Processors Many mixed-signal testers include one or more dedicated array processors for performing DSP operations quickly. It also allows for large amounts of production data to be stored and analyzed for characterization purposes. The tester computer also performs all the mathematical operations on the data collected during each test. Each architecture has advantages and disadvantages.2 Tester Computer The tester computer executes the compiled test program and interfaces to all the tester's instruments through a high-speed data backplane.4 Network Connectivity The user computer and/or tester computer are typically connected into a network using ethemet or similar networking hardware.6. This type of tester architecture and test methodology is called distributed processing. Test time is further reduced by eliminated much of the raw data transfer that would otherwise occur between digitizer instruments and a centralized tester computer or array processor.6. 5. while ATE Vendor B may choose to use a more conventional sucessive approximation architecture for its A WG and digitizer. ATE Vendor A may use a sigma-delta-based digitizer and A WG. This is another difference between a mixed-signal tester and a boltedtogether digital/analog tester. distributed processing may have the disadvantage that the resulting test code may be harder to understandand debug. The test engineer's approach to measuring a given parameter will often be driven by the vendor's architectural choices. there are many differences between any two ATE vendors' preferred tester architectures. each tester has to test the same variety of mixed-signal parameters regardless of its architectural peculiarities. A test engineer's job often involves testing parameters the tester was simply not designed to measure. the more advanced digital signal processing (DSP) operations may be handled by a dedicated array processor to further reduce test time. In the following chapters we will see how digitizers. computer workstations have become fast enough in recent years that the DSP operations are often handled by the tester computer itself rather than a dedicated array processor. can provide greater speed and accuracy than conventional measurementtechniques. In the end. A WGs.

5. Name an instance where a local Dffi relay might prove to be a better choice for interconnecting signals than a general-purposerelay matrix.13.12. This pattern supplies 256 samples to the DAC using a total of 600 vectors (40 + 559 + 1) per frame loop. linearity error. Assume no errors due to nonrepeatability.11. Name at least six types of subsystemsfound in a typical mixed-signal tester. The Xs on SDATA represent the time at which the 10 bits of eachADC sample are captured into capture memory. What is the purpose of the PGA in a DC multimeter's front end? 5.7. The 10bit write is broken into two eight-bit write operations.1. The digital vectors are supplied at a constant rate of 6 MHz.). and Ws. The meter input can be set to any of the following ranges: :tlO V. 5. What is the purpose of the diodes in the output stage of the relay driver in Figure 5. (The first 8-bit write operation contains only the two most significant bits ofDAC data. The drive data for SDATA consists of a combination of ones.) The Ws representdigital signal data.3.:t.5.9.6. In Figure 5. Tester Hardware 145 instruments. gain error. The ones and zeros represent digital logic statesthat select the DAC for writing. The Xs represent a high-impedance . The error includes all sources of inaccuracy (quantization error.6? 5. etc. zeros.12. Why are Kelvin connections used to connect high-current DC power supplies to the DUT? 5. and:tl V. and the differential offset is specified in the device data sheet to be :tIS mV.1111i Chapter5 . SDATA is a serial input/output (I/O) interface to a DUT containing a 10bit DAC. What is the difference between a digital pattern and a digital signal? 5.5 V :t 25 mV.4. Most mixed-signal testing involves DSP-basedmeasurements of one type or another. Each of the two outputs is specified to be within a range of 3. 5. We wish to use this meter to measurethe differential offset voltage of a DUT's output buffer.8. What is the purpose of the low-pass filter in a DC multimeter's front end? 5. so the student will need to devote special attention to these chapters. A single-ended DC voltmeter features a sample-and-difference front-end circuit. Compare the accuracy achieved using two simple DC measurements with the accuracy achieved using the sample-and-differencecircuit.10. Problems 5. In Figure 5.:t5 V.8.9. The meter has a maximum error of 0..2 V.1% of its programmed range. What is the purpose of capture memory? 5. At what rate are the digital signal samples written to the DAC? How long does it take to supply all 256 samplesto the DAC? 5. they also contain some of the most important material.2. Why are the number of vectors in the frame loop and the frequency of the digital vectors in a sampling frame important when developing a digital pattern for a mixed-signal test? 5. Although the next two chapters represent some of the most difficult material in the book.. What is the purpose of source memory? 5. the SDATA interface is used to read samples from an ADC located on the DUT from Problem 5.

15? 5. The start time for the drive data is set to 500 ns. Next. A series digital bits aredrivenfrom a digital pin cardat a rateof 1 MHz (I-JlSperiod). Draw the waveform timing approximatelyto scale. respectively. Whatis thepurpose distributed of digital signalprocessing hardware? . To produce thesewaveforms usingclockeddigital logic without timing andformattingcircuits. and the stop time is set to 900 ns. and 5. Its initial stateis set to logic low. draw the waveformthat would resultif we setthe formatto non-retum-to-zero (NRZ).146 An Introductionto Mixed-Signal Testand Measurement IC drive state.15.19.14? 5.17. of The seriesof bits are 1011 1.what clock rate would be required? If we wantedto be ableto set the start and stoptimesto 500 and 901 ns.18.16. what rate would we haveto operate clockeddigital at the logic? 5. The format for this pin is set to return-to-zero OX (RZ) format.14. Draw this waveformusing the notationin Figure 5. Nametwo reasons AWGs anddigitizersareusedin mixed signaltestingratherthan that CW sources RMS voltmeters. Why is formatting and timing information combinedwith one/zeroinformation to produce digital waveforms? 5. Why is a programmable amplifierneeded the front endof the waveformdigitizer gain in illustratedin Figure5.12. Whatis the purpose the low-pass of filter in the AWG illustratedin Figure5. Why might Xs be requiredat this point in the patternratherthan onesand zeros? 5.

Unfortunately. Other texts have covered the subject of signal processing in much more detail:4 The reader is assumedto already have a strong theoretical background in DSP. For example. we will examine the basics of sampling theory before proceeding to a more detailed study of DSP-based testing in Chapter7. Then gain can be calculated using a simple formula: gain = Vout . The pure analog approach to AC testing suffers from a few problems. analog testing measuresRMS noise along with RMS signal. A true RMS voltmeter can then measure the output responsefrom the DUT. it is relatively slow when AC parametersmust be tested at multiple frequencies. making results unrepeatableunless we apply averaging or band-passfiltering. more accurate. The new approach became known as DSP-based testing. a new approach to production testing of AC parameters was widely adoptedin the ATE industry. Third. as mentioned in Section 5. without giving the subject an in-depth treatment. 147 . Second.1 Traditional versus DSP-Based Testing of AC Parameters AC measurementssuch as gain and frequency responsecan be measured with relatively simple analog instrumentation. /~. more repeatablemeasurementsthan traditional AC measurementsusing an RMS voltmeter. In the early 1980s. First.1. leading to a lengthy testing process. though. an AC continuous sine wave generatorcan be programmed to source a single tone at a desired voltage level. Before we can discuss DSP-basedtesting.1 ANALOG MEASUREMENTSUSING DSP 6. We will review the basics of sampling theory and DSP as they apply to mixed-signal testing.and at a desired frequency. In this chapter. we must first understand sampling theory for both analog-to-digital converters and digital-to-analog converters. Hopefully. A mixedsignal test engineer will never be fully competent without a strong background in signal processingtheory. Vou/. each frequency in a frequency responsetest must be measured separately.) Digital signal processing (DSP) is a powerful methodology that allows faster.CHAPTER 6 Sampling Theory 6. adding to test hardware complexity. To measure gain. a full treatment of sampling theory and DSP is well beyond the scopeof this book. this introductory coverage will both refresh the experienced reader's memory of DSP and allow the novice to understand the fundamentals of DSP-based testing. traditional analog instrumentation is unable to measure distortion in the presenceof the fundamental tone. although this book will undoubtedly fall into the hands of the DSP novice as well.4. Vin.1. Thus the fundamental tone must be removed with a notch filter.

: : : ATE digital Waveform :: . DUT anti- Waveform capture memory t \.1. ." AWG '. . a number of imperfections are introduced in the physical world that make the conversion between continuous time and discrete time fall short of the mathematical theory. : .2. t-\ ATE digital filter : : . : .e. In a purely mathematical world. as long as a few constraints are met. source memory ' .1 Use of Sampling and Reconstruction in Mixed-Signal Testing Sampling and reconstruction are the processes by which signals are converted from the continuous (i. . Figure 6. -------- !::\ : ":j --tv Anti-: imaging . Both sampling and reconstruction are used extensively in mixed-signal testing. The ATE tester samplesand reconstructs signals to stimulate the DUT and measureits response. ~ . Digitizer ~ : : Antialiasing filt er !\: :: :-: . Both mathematical and physical sampling and reconstruction occur as the DUT is tested. V . j-: : . a continuous waveform can be sampled and then reconstructedwithout loss of signal quality. . test with interface circuit. analog) signal domain to the discrete (i.2 is tested.2 SAMPLING AND RECONSTRUCTION 6. A '.. I I : : ~: : \j : .148 An Introductionto Mixed-Signal TestandMeasurement IC 6. : . . ..: V: . . imaging: filter : . capture: Figure Various~ signalsassociated a voice-band 6. I . I ~ I : . Many of these imperfections will be discussedin this section. : '. digital) signal domain and back again.:: . ~ memory filter : I ' ' .e.. Unfortunately.. : . . . The DUT may also sample and reconstruct signals as part of its normal operation. .. I : : : DUT DUTantialiasing . . Waveform source : . : I Waveform: memory : ' I : : I .1 illustrates the various types of sampling and reconstruction that occur when the voice-band interface circuit of Figure 1.

Continuous-time signaland its sampled equivalent. frequency/0. Continuous signalsare often described by mathematical equations.'. temperature. digital transmission. For example. We refer to Ts as the sampling period and its reciprocal Fs=l/Ts.such as the cellular telephone example in Chapter 1. we canwrite v[n]=A sin(2Jrfon1:.2 Sampling: Continuous-Time and Discrete-Time Representation Many signals in the physical world around us are continuous (i. To simplify'our notation. we often impose the condition that the ratio/ofF s be a rational fraction. and phaseshift t/J. must convert the continuous signals in the physical world into discrete digital representations compatible with digital storage. Familiar examples of real-world analog signals include sound waves. whose value in this particular case changes in a sinusoidalmanner with amplitude A. analog) in nature.2). Sampling Theory 149 6. substituting Eq.+t/J)=A sin( 2Jrtn+t/J) (6./ofF s =M/N. and pressure.1) where v(t) is a continuous function of time t. while the sampled waveform v[n] is said to exist in discrete time. it is commonpractice to drop the Tsterm in the argument of Eq.1) into (6. and mathematical processing. '~. as the samplingfrequency or sampling rate.Chapter 6 . Such a process is depictedin Figure 6.-"'-"""--""""". where M and N are integers.4) :+E?-t J~6:~~s r-A-\ ampler v(t) v[n] ::::::::::::i. (6.e. Sampling is a process in which a continuous-time signal is converted into a sequence of discretesamplesuniformly spacedat intervals of Ts seconds.2.3) For reasonsthat will become clear later in this chapter. such as v(t) = A sin (2Jrfor +t/J) (6. (6.2) as it is assumedto be constant for all time. allowing one to write v[n]=A sin ( 2Jr*n+t/J) (6.often written as v[n]=v(t)lt=nT s (6. t - n 0 Continuous-time signal Clock Fs=I/Ts 0123456 Sampled signal Figure 6. and n as an arbitrary integer..2. The continuous waveform v(t) is said to exist in continuous time... light intensity..2. . Many modern electronic systems.2) where v[n] defines the values ofv(t) at the sampling instants defined at t=nTs.

as depicted by the following two rules <5 (t) and = 0. We can also define a sampled waveform as a continuous function of time. To enable such a description we must make use of the concept of impulse functions. an impulse function. where it is infinitely large in such a way that it contains unit area under its curve. letting the pulse width go to zero while the pulse height goes to infinity. . is defined as having zero amplitude everywhere except at t=O. The use of this alternative notation is important in the next section where the samples are converted back into the original continuous-time signal. defmed by fv(t) v Pulse areas all equal to unity 2 <5(t-to)dt =v(to) v (6. It should be obvious from this description that we are going to encounter some difficulty in graphing the impulse function.3(a). an impulse is graphically representedby an arrow whose height is equal to the area (voltage x time) under the impulse. Mathematically.6) It is important to realize that no function in the ordinary sense can satisfy these two rules.3(b). we can imagine a sequenceof pulselike functions that have progressively taller and thinner peaks. t * 0 (6.illustrated in Figure 6.5) f<5(t) dt=l (6.150 An Introductionto Mixed-Signal Testand Measurement IC Discrete signals such as this can then be stored in computer arrays and processed using DSP functions.3. denoted by 4t). If we take this argument to the limit. However. Impulse definition. Hence.1) v(t) 1 ~ 2 1 Area = v t = 1 t impulse t 0 Unit -1 -% -1/4+1/4+% (a) +1 (b) Figure 6. as shown in Figure 6. then we have what we refer to as an impulse function. Up to this point we have defined a sampled waveform in the discrete-time domain as a sequenceof numbers defined by v[n]. An important property of impulse functions is the so-called sifting property. with the area under the curve remaining equal to unity as .

namely. It should now be clear that va(t) and v(n] are different but equivalent models of the sampling processin the continuous-time and discr~te-time domains.. through direct application of the sifting property of the impulse function. respectively.4. J :~~::::::. commonly referred to as a unit impulse train va(t)= L v(t) n=o(t-nJ. A continuous-time representation a sampledsignal as a series of impulsescreatedby of multiplying originalcontinuous-time the signalby a unit impulsetrain. Mathematically.) o(t-nJ. v(nT.8) as va(t)= n=- L v(nJ.) (6. in the integration process. v(n]. (6..Chapter6 . 0 Ts 2Ts 3Ts 4Ts STs6Ts Unit impulse train Figure 6. Equivalently. In order to keep track of which domain we are working in (i.4 illustrates the impulse representationof a sequenceof samples from a continuous-time signal. to denote a discrete-time signal. one must keep in mind that the values ofva(t) at the sampling instants are embeddedin the areacarried by each impulse function. continuous or discrete) we shall make use of parenthesesto encompass the argument of a continuous-time signal.9) Note that va(t) is not defined at the sampling instants because ~t-nTs) is not defined at t=nTs.). the value at t=to.8) Figure 6. .equally sized impulse functions.e. However.:::i~ t 0 Continuous-time signal p(t) v(t) Multiplier v(nTs] J iI]~I~~[ 2 T s] v [3 T s] V[ Ts ] v[O] v[4Ts] V[5 '1"] 's t 0 Ts 2Ts 3Ts 4TsSTs6Ts Sampled signal (impulse form) l_j_iJ_j-_li~' . and squarebrackets. SamplingTheory 151 Here the impulse function selects or sifts out a particular value of the function v(t). If va(t) denotesa signal that has been uniformly sampled every Ts seconds.) (6. then we can make use of the sifting property and write the following mathematicalrepresentation for va(t) in terms of a series of evenly spaced. the impulses are equal to the multiplication of the continuous-time signal times a unit impulse train. we can write Eq.

. 0:::::0 -0. 15 -2 0 5 time (sec\ 10 6.-:_:e 0:0' . .the combined effect of the DAC and filter can be modeled as a single reconstruction operation denoted with impulse response p(t) as shown in Figure 6. We shall refer to this plotting range as the observation interval. . 1t/4 phaseshift..0 . : 0 . (The stem command in MATLAB is an effective method for plotting discrete samples as a function of time. : . SettingA=l. zero phase shift.. .. . . and a period of 16 samples. andM=3.3 Reconstruction The inverse operation of sampling is reconstruction. 1 IjJ=O. .5 -1 :: : :: (j:::(j . SettingA=2. 0 ... plot 16 samples of a sine wave . 0:0 :: : :: (j:::(j . Reconstruction is a process in which a sampled waveform (impulse form) is converted into a continuous waveform by a circuit such as a digital-to-analog converter (DAC) and an anti-imaging filter. 0 . 0 :: . : : : : : : 0 . "':::'" :: : : : 0:::::0 0:::::0 e:_:_:_:_:_:_:e 0:0 . Ans. the .5. . . .) Ans. : : : -1 : . . we get: 2 or an equivalent software program. Using MATLAB 10 20 30 40 time (sec\ 50 60 70 having an amplitude of2.5 : : :: : 0:::::0 0 :_:':. . 1jJ=1t/4. : .2. Using MATLAB or an equivalent software program. .e 0. N=16. ". : . we get: 0:0' . 0 : : .. .2. : .0 0 6.152 An Introduction to Mixed-Signal IC Test and Measurement Exercises: 6. . reconstruction is the operation that fills in the missing waveform that appears between samples. 1o. : . '" .:::". : 0 . . : . Mathematically speaking. ... and a period of 16/3 samples. . In essence. andM=l. . '" .. 0:0 : :: : : (j:::(j .. In effect. N=16.. plot 64 samples of a sine wave having unity amplitude.-:_:':..1. : : :: : 0:::::0 0:::::0 e:_:_:_:'. .. . : : : : : Q : : : : .. 0. . f t : . ...':. "':::'" 0. : . : : : . : . "':::'" : :: : : 0:::::0 0:::::0 e:_:_:_:_:_:':. . . 0:0 : :: : : (j:::(j .

10) f i t l Example6. We shall have more to say about this in a moment.. (6. Solution: To begin. 1.of 1 s. 0.10) states that each sample is multiplied by a delayed version ofp(t) and the resulting waveforms are added together to form VR(t). )p(t -n1:.50. Everywhere else the sequenceis assumedto be zero.11) plot the output waveform VR(t).6(a).87.)p(t-n1:. A general formula that describes operation of reconstruction is given by the VR(t)= n=The shapeof the impulse responsedefines the shape of the waveform between adjacent samples. (6. convolution. p(t) is a triangular waveform with a pulse duration that lasts for 2 s and has a peak value of 1. O} corresponding to n = 0. 0. a pulse p(t-nTs) is generated with an amplitude proportional to the sample value v(nTs). time-invariant continuous-time systems.It is given a special name.00.87. at each sample time t=nTs. we can write the reconstructedwaveform as vR (t) = I v(n1:.0. (6. Following Eq. reconstructionoperation performs interpolation between sampled values.) n=O 6 . Assume a sampling period.. Collectively. Thus p(t) is commonly referred to as the characteristic pulse shape of the reconstruction operation. In other words. a plot of the characteristic pulse p(t) is shown in Figure 6. Reconstructing continuous-time a signalfroma data sequence.Chapter6 v(nTs] .10) appearsoften in the study of linear. Using a triangular reconstruction pulse shapep(t) defined as follows P(t)= { l-it-li 0 0~t<2 elsewhere (6. As is evident. Eq. The general form ofEq. . SamplingTheory VR(t) 153 I I lJ_l_J__J-4 f Reconstruction p(t) Clock 0 Ts 2Ts 3Ts 4Ts STs6Ts k~~::~::::i~ 0 Continuous-time signal t Sampled signal (impulse form) Fs=l/Ts Figure 6.1 An input sequencev(n] derived from a sinusoid has the following sampled values {O.5. Ts. all the pulses are summed to form the output continuous signal VR(t).6.) (6.50. and we say that the output is obtained by convolving the continuous-time equivalent signal ofv(nTs) withp(t). f v(n1:. with the limits of summation changed from 0 to 6 (as all other sample values are assumed equal to zero)..0.10).

11). it is more instructive to demonstrate this by superimposing all the pulses weighted by the sampled value on one time axis as shown in Figure 6. ... ". /" . However. . "" . . . the upper frequency range of the DAC limits this approach.'\. This same operation can be repeatedfor all the remaining time points. .6 ~ ~ ~ > 0. It is also clear from Figure 6.. . as the reconstructed signal is made up of various sized pulses. . ." \ / \ /\ .. as it is easiest to realize in practice. 3 /" "" .-0. To eliminate this high-frequency ..4 0. as shown in Figure 6.:. we can add up the contribution from each pulse.) p(t-2J:. . Convolving triangularpulsewith a sequence sampledvalues. .) Now we can an expression for each shifted p(t) according to Eq. .. The sum of all shifted and scaled square pulses will result in a "staircase" continuous-time waveform. .6(b). At any particular time point. It is also evident that the staircasewaveform is a rather poor approximation of the original waveform. . " " . . . . / \ . . .. . 2 y " . 4 5 "y ".4 "y "" " / """ """ " "/ . 1 0. However. " " . . time (sec) (b) Figure 6. ." . A better approximation would certainly be obtained by increasing the number of stepsper period used to reconstruct the waveform. /'.2 0 1 time (sec) (a) 1 0. (6.) p(t-J:. .v . " \ "" ".". The result is a straight-line interpolation between adjacent sampled values.+v( 6J:.6.6 s. . a of Most DACs make use of a square characteristic pulse.6 -0: 0.." \ ~ 0.. " "" .154 or when expanded as VR An Introductionto Mixed-Signal Testand Measurement IC (t) = v(O) substitute p( t) +v(J:." .8 :. ." .7. . " \ / . " 0. \ . )p(t-6J:. .2 0 ..8 /\ " " " . ..) +. . )+v(2J:. . and form a single point on the reconstructed waveform. . This is shown in the figure for t=2.7 that the reconstructed waveform VR(t)contains a large amount of undesirable high-frequency energy.. .'"' ./ y " / \ \ . .

In practice. Such a filter is known under different names as a smoothing or anti-imaging filter. a perfect reconstruction operation can only be approached. (6. energy. . typically one with a low-pass characteristic having a cutoff frequency of at most one-half F s. the DAC is usually followed by a postfiltering circuit. :" A t. p(t) = J: 1l" -t for -oo<t<oo (6. and its infinite length implies that to reconstruct a signal at time t exactly requires all the samples. Cascading a filter after the DAC effectively alters the characteristic pulse p(t) of the reconstruction process and provides a much better approximation to the original waveform. Illustrating the reconstruction operation with a DAC and an anti-imaging filter circuit. SamplingTheory 155 . ~. some imperfections are introduced in the reconstruction process. n 1- imaging filter Figure 6.12) J: 1'his is a very long pulse. There are two main sources of errors: (1) aperture effect due to the characteristic pulse shape.~..7. Consequently. In fact.13) r(t-nJ:) It is interesting to note that VR(t)is equal to v(nTs) at all the sampling instants as the sin(x)lx term in Eq..Chapter6 . perfect reconstruction can be obtained if the characteristic pulse of the overall reconstructionprocess has the following form Sin( -t1l" ) .12) into (6. Substituting Eq. Collectively. °\ " Q .° ci ". If either error is an important parameter of a particular test. and (2) magnitude and phase errors related to the anti-imaging filter. "Focused Calibrations").13) is equal to one. the DAC and the antiimaging filter are called a reconstruction filter.f 0" . then they would need to be measured and corrected using a focused calibration procedure (see Chapter 10. G. (6. Both types of errors lead to frequency-dependentmagnitude and phase errors. not actually realized. .10) allows us to write an exact interpolation formula for recovering the continuous-time information from the sampled values as VR (t) = f n=- v(nJ:) sin [ ~(t-nJ:) 1l"J: s ] (6. not just those around that time.°"0.

such an operation provides a useful aid to help us visualize the reconstructed waveform. if we make the change of variable substitution. to (N-I)xL.J)p (kJ:.l)p(t-nJ:.2) n=- Now. For this reason. and drop the time reference Ts2. This is executed in MATLABusing the following routine: . It is important to maintain the relative pulse duration with respect to the original sample values. increasing the size of the modified vector.156 An Introduction to Mixed-Signal Testand Measurement IC Convolution Using MATLAB Convolution is a frequently used operation in the study of linear systems. then we simply insert L-l zeros between each sample value. P. m=nL. Here we speak about the sampled characteristic pulse. Subsequently. Nonetheless. say. say V.10). Hence.2 (6. MATLAB has provided a built-in function called CONV to assist in such analysis. p[k] convolving with the signal v[k].15) = f' v(nJ:.. time-invariant discrete-time systems.we can rewrite Eq. As with all computer operations. Vexpand. P samples of p(k) are stored in a vector.2)p((k-nL)J:.14) allows us to write the oversampled waveform in terms of the new sampling period Ts2 as VR [k] = VR (t )It = kJ:. Ts2. Likewise. we can only approximate a continuous-time reconstructed waveform with a sequence of finely spaced sample values. n== L v(nLJ:.2-nJ:. we can then perform the convolution sum using the built-in function called CON V with vectors Vexpand and P. the reconstructedwaveform VR(t)is given by VR(t)= n=- L v(nJ:.J ) L. According to Eq. where L is a positive integer. (6. If N samples are stored in a vector.15) using discrete-time notation as vR[k]= m=- L v[m]p[k-m] (6.14) This waveform is then sampled with a finer sampling period Ts2 such that TsJ=LTs2. Tp.. A set of N discrete values v(nTs) are obtained by sampling a waveform at a rate of TsJ. Substituting t=kTs2into Eq.J) (6. (6. Here the number of samples stored in P is determined as the ratio of the pulse duration. as it has been resampledat its many zero locations. resulting in a new vector Vr of length (N-l)xL+P-l. say. (6. it works exclusively with discrete values.16) This equation is known as a convolution summation and is the basis of linear. To perform this operation using MATLABwe must first expand the time scale of the original sampled signal v[k]. to the new sampling period.

Superimposed on the plot in Figure 6.8. -0.9239.1 over one full period using a squarecharacteristic pulse described as p (t ) . 1. -0. -0. SamplingTheory 157 % Reconstruction Routine (V and P are input vectors) Vexpand=zeros((N-1)*L.7071. 0. 1.{ I 0 ~ t < 2 0 elsewhere Assumethe sample rate is 1 s. 1 0.Vexpand). 1. expand the time scale % form=1:N.0000.9239. 1. 1] Executing the reconstruction MATLABroutine.7071. Interpolate between sampled values using 16 sample points. 1. 1. end Vr = CONV(P. 1. 1. 1. 1.3827. -0. 0. We clearly see that the reconstructedwaveform is a poor approximation to the original sinusoid.9239. 1.3827. 1. 0.5 "ir: > -0.Chapter6 . Vexpand((m-1 )*(L)+1 )=V(m).3827. -0. 0.5 -1 0 5 time ( sec ) 10 15 Figure 6.7071. . -1. we get the staircaseplot shown in Figure 6. 1.0000.7071.1).1 we can write the sampled sequencevector as v= [0. % convolve P with Vexpand Example6. 1. using 16 points to define p(t) over the 1-s pulse duration results in the vector: p= [ 1.8. -0. Unfiltered DACoutput(MATLAB simulation). Our next example will explore the same sample values but will use a more effective pulse shape. Solution: From Exercise 6.2 Reconstruct and plot the sampled sinusoid given in Exercise 6.9239. 0.0. 0. 1.8 is the original sinusoid.3827] Likewise.

0.7071. 0.-0. 0.. 0. 0. 0.4375.9239.-0.9.6250. 1 .8125.9375.5000. 0. we get the plot shown in Figure 6.9239.0000.0625 ] Executing the reconstruction MATLABroutine.2500.. 0.1250. 0.9375.2."'".3750. but this time use a triangle characteristic pulse described as p(t) ={ I-it-l! 0 0~t<2 elsewhere Assume sample is 1 s andinterpolate the rate between sampled valuesusing 16 sample points. 0.3827.7500. "'. 0. 0. 1. Also superimposed in the plot is the original sinusoidal signal.0000. It is therefore fair to say that a reasonableapproximation of the original continuous signal is obtained by joining adjacent sample value with straight lines (this assumesthat there are at least 10 points per period).3 Repeat Example 6.9239.6250.8750.0625.1875.6875. 1.3125. 0.1250. 0.4375.7071.6875.. 0. -0.8125. In fact. 0. 0. little difference is visible. 0.5 "". 0.3827. 0. 0.5625.0000. 0. -1. -0.5 ~ 0 > -0. the reconstructed waveform is very similar to the original sinusoidal signal. 0. 0.9239. 0. 0.3125.0..7071. .1875.0. As is evident. 0.7071.7500.3827. -0. 0.2500. ) '/ 15 -1 0 5 ti me sec ( 10 Figure 6.. 0. using 32 points to define p(t) (as it has a 2-s duration) results in the vector: p= [0. 0.158 An Introductionto Mixed-Signal Testand Measurement IC Example 6.3827] Likewise. 0.5625./~--"""'" /// a: ~ 0.5000. -0. 0. canwrite the sampled we sequence vectoras V= [0.8750. 0. Low-pass filteredDACoutput(MATLAB simulation). . Solution: Fromour previousexample.9. 0.3750. 0.

(6. Specifically. The Nyquist rate is the minimum sampling rate allowable by the sampling theorem.11). in Exercise 6.2. and as far back as 1915 in the literature of mathematicians. 2. Interconnect sample points with straight lines 1 o.3.1 using the triangular pulse Ans. a lO-kHz sine wave appearing at the output of . Shannon introduced the idea back in 1949 for application in communication systems. A continuous-time signal with frequencies no higher than F max is completely described by specifying the values of the signal at instants of time separatedby 1/(2Fmax) seconds.30 ( ) 40 time sec 50 60 6. ~ > 0 -0. and its reciprocal is called the Nyquist interval. interested readers can refer to Jerri6 for a detailed account. interest and knowledge of the sampling theorem in engineering applications can be tracedback to Nyquist in 1928. A continuous-time signal with frequencies no higher than F max may be completely recovered from a knowledge of its samplestaken at the rate of 2Fmax per second. SamplingTheory 159 Exercises: 6. the sampling theorem for band-limited signals can be stated in two separate equivalent ways: but The Samo/in!! Theorem 1. Reconstruct the sampled signal displayed described by Eq.5 -1 0 10 20 . However. Part 2 of the theorem is exploited by waveform generators. The first part of the sampling theorem is exploited by ATE digitizers. For a historical account of the sampling theorem. the Nyquist frequency refers to F max. For this reason. The sampling rate 2Fmax is called the Nyquist rate. For example. Although somewhat confusing at times.Chapter6 . it is sometimes referred to as the Shannon sampling theorem.4 The Sampling Theorem and Aliasing The sampling examples of the previous subsections are all performed in accordance with the sampling theorem.

if it is sampled at a slightly lower frequency of 19.. less than two samplesper period are taken from the input sine wave. the signal reconstructed from these samples. As a result. it is important to limit the bandwidth of the signals that appear at the input to the digitizer to less than the one-half the Nyquist rate.160 An Introductionto Mixed-SignaliC Testand Measurement Input ~~~~~~~~~~ ~~~~~~~~~~ Sampler \ Perfect reconstruction v A V Output - Clock Fs=l/Ts Clock Fs=l/Ts Figure6. While aliasing is generally an effect that is to be avoided.10. The sampling and reconstruction process has distorted the input signal.1 kHz with no loss of signal information. Such a waveform is said to be undersampled. The cellular telephone base-band interface is one such example that might use undersampling to convert high-frequency inputs to lower-frequency signals to be digitized by a slow ADC.5. However. and frequency)..Undersampled waveand its reconstructed sine image. To better understandthis.10. specific information about its characteristics are lost.9 kHz.e. To understand this. The phenomenon of a higherfrequency sinusoid acquiring the identity of a lower-frequency sinusoid after sampling is called aliasing.shown on the right-hand side in Figure 6.2. we would like to addressa commonly asked question: What happens if we sample a sinusoidal at exactly twice its frequency? The answer is that information may be lost. the process of undersampling has been used to an advantage in several applications.10 consisting of a sampler driven by a sine wave. In general. if Shannon's theorem is satisfied. have exactly the same amplitude. but have a frequency spectrum that decay to zero as the frequency approaches infinity. it is not always clear how to satisfy the sampling theorem. Aliasing may also be advantageously utilized by a DUT as part of its normal operation. the output of this arrangement should correspond exactly with the input signal (i. undersampling is used to extend the measurementcapabilities of an arbitrary waveform digitizer. In the case shown here. phase. To avoid this ambiguity a low-pass antialiasing filter is placed before the digitizer to attenuate the high-frequency components in the signal so that their aliases become insignificant. practical signals are not limited to a fixed range of frequencies. consider the setup shown in Figure 6. hence it violates the sampling theorem. consider that an arbitrary sinusoidal (i.e. one with arbitrary amplitude and . As we will see in Section 9. Ideally. Subsequently. To avoid aliasing in practice. a DUT can theoretically be sampled by the digitizer at 20. followed by a perfect reconstruction operation. Finally. has the same amplitude as the input signal but has a much lower frequency (as an estimate of the reconstruction operation consider joining adjacent samples with straight lines).

Clearly. as M=l and N=64. is a result of nonlinear circuit behavior and component mismatches. for k=1 :64.5 Quantization Effects Mathematical sampling can be achieved with no loss of signal quality. will always introduce some amount of noise and distortion. We can therefore conclude that one should not attempt to sample at exactly twice the Nyquist rate. resulting in a unity sampling frequency. As the time index k is incremented in unit steps. f/J. A computer can come very close to mathematical perfection.Chapter6 . For example.2. phase) alwaysbe represented the sum of a sine and cosinesignaloperatingat the same can as frequency Csin(21£ +f/J)= Acos(21£ + Bsin( 21£ Jot f. the sampling period is by default equal to unity.17) Therefore. end. the following MATLAB routine can be used to create64 samplesof a sine wave with unity amplitude and zero phase shift: pi=3. It would have almost no distortion and very little noise. and (2) circuit related noise such as thermal and shot noise.t) f. all the samples from the sine wave are zero. The ADC included in a digitizer. For example. As is evident. the quantized waveform .11. The noise introduced by an ADC can be classified as: (1) quantization noise. 6. In a perfectly designed and manufactured ADC.14159265359. Distortion. Therefore. whereas those from the cosine signal are not.Sine cosine and waves sampled twice signal at the frequency.11 illustrates the samples derived from a sine and cosine signal sampled at twice their frequency. on the other hand. the majority of the noise will be causedby the quantization error of the conversion process. the frequency of the sampled sinusoid is 1/64 Hz. Figure 6.t) (6. analyzingthe effect of samplinga sine and cosinesignal allows us to generalize the result for a signal having an arbitrary phase.12 shows a set of samples obtained from a sine wave that has been digitized by a 4-bit ADC. v(k)=1*sin(2*pi/64*k). any information contained in the sine wave such as its amplitude would be lost and unobtainable from the samples. on the other hand. The quality of the sine wave is limited only by the tiny amounts of mathematical error in the computation process. SamplingTheory 161 Figure6. Figure 6. This sampling process would result in a nearly perfect sampled representation of the sine wave.

.. An LSB sets the largest distance that the ADC output will be from a sample obtained directly from the original waveform (see the expanded view on the right of Figure 6.4} Also shown in Figure 6.1...7..1.14. . . The distance between adjacent horizontal grid lines is known as the least significant bit (LSB). .12 could be stored in a computer memory as the sample set {7. ~ ~ .4. . 0.11. . ..5 -1 . ..11....4... SettingA=I. .. ~ . . . . . ..4.. . In general. together with an expanded view of a single sample shown on the right-hand side. .14.1. .162 An Introductionto Mixed-Signal Testand Measurement IC (6. The horizontal grid lines correspond to the limited outputs available from the ADC. ... . we get: 1 ~ . .. . .11. and a period of 12 s derived using a sampling rate of I Hz and a sampling rate of 1/8 Hz... . tjFO. .11.. .. . 0 .N=12. .. ~ ~ .7...5 ~ . ~ ..4.4. .14. ..... . . ~ .5 0 -10 0 5 0 0 10 ti me 0 15 0 0 20 0 25 . we get: 1 0.14. .7. ~ ~ ~ -0.7.4.12 is the original analog waveform superimposed on a regular spaced set of grid lines.1.. The vertical grid lines correspond to the sampling instances. ADS.. . ..14.5 0 n ~ ~ ~ n ~ ~ 0 0 0 0 0 0 0 0 -0. ..)..12).. . . zero phase shift.7. . andM=I... . To illustrate the effects of aliasing. .. .. .. aD-bit ADC with a full-scale analog input range of FS has a corresponding LSB step size of FS V =-0-LSB 2 -1 Exercises 6..11.14. . . 0 0 0 0 5 10 time (sec) 15 20 25 SettingA=l.1 1. .18) !! ~ in Figure 6.) . with time increasing from left to right..1. ... compare 24 samples of a sinusoid with unity amplitude. .. ~ . . Use MATLAB or an equivalent software program for your analysis. . ~ . . . tjFO. . andM=8. .. ... . . .1.. N=12.

Moreover.13. the analog waveform would contain a significant noise component as illustrated in Figure 6.14. The error waveform is the quantization noise added by ADC quantization process.18) and (6. 6 .. t~ ~~~ '6"" t: t.Chapter6 . the quantization errors of a random input signal exhibit a uniform probability distributions from -Y2 LSB to + Y2LSB. Higher resolution would provide more vertical . the quantized waveform is equal to the sum of the ideal sampled waveform and an error waveform. Clock Fs=l/Ts Clock Fs=l/Ts Thicknessof line indicatesthe uncertainty of sampledvalues Figure 6. ~ t: ~ ~~~ t~ t~ . (6.12.. The quantization errors in Figure 6. In Figure 6. If we separate the errors from the quantized samples.. quantization error can be reduced using an ADC with more bits of resolution (consider combing Eqs..Ji2 (6. However. '6"" t: ~ t.. error 1 LSB . SamplingTheory 163 ADC 1 1 ~ ~ Quantization . Perfect '\IV\.19) Obviously.12 do not look especially severeat flfSt glance. "True" sample Figure 6.. assuming a perfect ADC.13. Quantized wave sine samples. Statistically speaking. if we were to reconstruct a continuous-time waveform from these samples. recons. we can see how much noise has been introduced by the quantizationprocess. the ideal quantization error sequence Vq resembles a random sequence having an averageand RMS value given by vq-AVE =0 and vq-RMS =~ .Illustrating noisecomponent is associated a quantization the that with operation..19)).l i TJ Timing grid Analog waveform . Input t~ t~ :i~ i.l T . ~ ~ ~ t: ~ Output Wv ~ Sampler Quantlzer .

M= 1. X. .75.) Example 6.75. zero phase.25. -0. compute the RMS value of the quantization noise and compare this result with its theoretical predicted value. to discrete values denoted by Y. and 0. % roundsto nearest level A quantizer is the element of the ADC that limits the continuous input signal.164 An Introductionto Mixed-Signal Testand Measurement IC Ideal sampled signal + Quantized signal Quantization error signal Figure 6. % Least significant bit Y = round(X/LSB)*LSB.76 dB signal-to-noise ratio (SNR) with a full-scale sine wave input.4 Compute the quantization noise sequencethat results from exciting a 3-bit ADC with a full-scale amplitude sinusoidal signal of unity amplitude. values of -1.75. "Analog Channel Testing" for an explanation of the decibel unit and SNR measurements. Y vs.5. Also.5. 0.15. 0. Adding an extra bit of ADC resolution reduces the size of each LSB by one-half. % Full scale range LSB=FS/(2AO-1). The ADC would then interpret these levels and provide an output digital representation.75: % 3-Bit Quantizer (-1 <= X <= +0. The transfer characteristic. etc. A 15-bit ADC would therefore be capable of 91. or 6 decibels (6 dB).25. thereby reducing the RMS value of the quantization noise by a factor of two.75) 0=3. (See Chapter 8.14. A 16-bit ADC is theoretically capable of a 97. for this quantizer is shown in Figure 6. -0. -0.76 dB SNR. Representing the quantized waveform as a sum of the original sampled signal and a quantization error signal. In this case. and N=64. say X. graticules on the plots in Figure 6. 0.12. reducing the size of each LSB. Solution: To aid us in this investigation we shall make use of the following MATLAB routine for an ideal 3bit quantizer performing a rounding operation typical of an ADC having a full-scale input range between -1 and +0. for example in a 2's complement form. % # of bits of resolution FS=1.

SamplingTheory 165 Figure 6.16. t/1=O. Here we seethat the error sequencehas symmetrical responsebounded between :J::0. we get the error sequencein Figure 6. the results of this simulation agree reasonably well. . The RMS value of the error is computed to be 0.16. N=64. has and a mean value of -1. we would discover a much closer correspondence between experiment and theory.75.Ji2 = 0. The discrepancy is largely a result of the quantizer's low resolution of 3 bits.125.15.A=O.0722 based on an LSB of 0.Quantization errorsequence. the error sequenceshould have an averagevalue of 0 and an RMS value of 0.25 V.0842e-18 or nearly zero. According to the quantization theory presentedearlier.25/.< >II g Figure6. For all intents and purposes. and M=1 through the 3-bit quantizer. If we increased its resolution.Chapter6 . Now passinga near full-scale sinusoid having the following parameters. Idealquantizer transfercharacteristic. >.0670.

11111_ Exercises 6. 6. .2. . Imlng grid Jitter error. .166 An Introductionto Mixed-Signal Testand Measurement IC . If an ideal 7-bit ADC has an RMS quantization noise component of 1.4 mV.9 mY.6 Sampling Jitter '. Illustrating effectof clockjitter on the sampling the process..5 V gives an output of code of 4 for a code range beginning at 0 and ending at 15.5 V.7.2. A 4-bit ADC with an analog input range from -1. What is the LSB of an ideal 8-bit ADC that has a full-scale input range of 0-1 V? What is the expected RMS value of the corresponding quantization noise? Ans. What are the minimum and maximum values of the input voltage corresponding to this output code? Ans. Here we make use of the same regular spaced grid as that used in Section 6. 6. -0. 1.5 except that this time we added an additional set of vertical dotted lines to indicate the actual clock edge subject to random clock jitter.6. the actual sample can differ quite significantly from the ideal sample and the size of this error is proportional to the magnitude of the jitter.17 illustrates the effect of jitter on the sampling processof an ADC. Mathematically.1 Another source of signal quality degradation is sampling jitter.5.74mV. 6. what is the quantization noise for a 5-bit ADC having an identical full-scale input range? Ans. 3.5.5 to + 1. Figure 6.17. tj Figure 6.. Jitter is the error in the placement of each clock edge controlling the timing of each ADC or DAC sample. As is evident in this situation. -0.13 mY.7 V. P Digital grid Ideal clock edge Actual clock edge Actual sample Ideal sample Sa er L Analog waveform T.

(6. Now we have the jitter term separatedfrom the deterministic term.) (6.}cos( 2Jrfot}) + Aocos{2n fon1:.23) .20).t} (6. One example that allows us to draw some useful conclusions is the study of jitter on the sample points of a single sinusoid with peak amplitude Ao and frequency /0.24) Here we made use of the fact that when x is small.+t})) (6. according to Eq. The phase shift is assumed equal to zero without loss of generality. s+) (6.11- Chapter6 .2) according to: v[n]=v{t)l t = nT t .)+ Ao2nfot} cos{2Jrfon1:. denoted as vi.25) Recognizing that the derivative of a sine wave is a cosine wave further allows us to write the jitter-induced error in terms of the magnitude of the jitter and the slope of the signal at the samplepoint L I_III - v}[n]= [ ~ dtt= ] n1:. Without jitter. and adding it to the sampling expressiongiven in Eq. Since the magnitude of the jitter tj is assumedto be small comparedto the sampling period Ts. which we shall denote as tj. . f Due to the nature of tj. cos(x) = land sin(x) = x. SamplingTheory 167 we can calculate the effects of jitter on the samples obtained by an ADC by associating jitter with a random timing variable.26) .22) . 1 .)sin( 2n fot}) (6.20) .) (6. (6.23) as v[ n] = Aosin{2Jr fon1:. the sample points are v[n]=v{t)lt=n1:.21) With jitter present. +t} = Aosin(2nfo (n1:. is v} [n] = Ao2nfot} cos{2nfon1:.22) as v[ n] = Aosin{2n fon1:. the samplesbecome v[n] =v{t)lt =n1:. v[n] is now a random variable as well. (6. =Aosin{2Jrfon1:. We can separatethis expression into two parts. one that includes the deterministic component and the other due to jitter. consider using the trigonometric identity sin(A+B)=sin(A)cos(B)+cos(A)sin(B) so that we can rewrite Eq. (6. allowing us to claim that the error in the sample due to jitter.we can approximate Eq. To see this. Calculating the effects of jitter can become mathematically complicated in all but the simplest examples.) (6. .

30) Conversely.17. Let us define a l-LSB upper limit on the tolerable amount of jitter-induced noise Vj-RMS 1LSB < <.32) 2 1ft j-RMS (F.. F s-MAX !a-MAX) =2 is F...168 An Introduction to Mixed-Signal Testand Measurement IC This result should be readily apparent from Figure 6. \ I An 1) ° FS (6.J2 + 1) (6.. maximum sampling the frequency that can be used (i.J2 (2 D -1 ) (6. Assuming that the jitter tj has an RMS value of tj-RMS is independent of v(t). r (2 . (6.thenwe canfind a lower limit on the a F maximumallowable jitter givenby tj-RMS« 1fJo 2D -1 .27) At this point in our discussion we can use this result to set a limit on the maximum tolerable jitter allowable based on the A~C's speedand resolution.J2 ) (6.28) FS Substituting Eq..if we assume full-scaleinput sinusoid.2 (6.-MAX ) . the RMS value of the jitter-induced error is v= 21fA"h tJ"-RMS r::: JRMS .27) and rearranging allows us to bound the jitter according t9 tj-RMS v21fA"Jol~. S~2A".. We first have to define the amount of jitter-induced noise that we are willing to tolerate. then we can and approximate the RMS value of the error sequenceVj[n] as the product of the RMS value of 1jand the RMS value of the derivative ofv(t) at each sampling instant.29) Further. for aD-bit ADC having an RMS sampling jitter tj-RMS.-MAX< 1ft j-RMS 2.-11 < r= ..31) or we can concludethat the maximum conversionresolution(expressed number of bits) in available with a maximumsampling frequency s-MAX RMS sampling F and jitter tj-RMS is D MAX < log ( 2.-1 2° (6..e. For a sampled sinusoidal signal with peak amplitude A" and frequencyJ"... It suggests that a timing error will induce a larger sample error at the rapidly rising or falling points of a sine wave than at its peak or trough.

that is. is a discrete-time representation of differentiation allows us to approximate the jitter-induced error (for high oversampling ratios) as Vj[n]= [~ ]. -tj)-u(t-nr... Here the actual output waveform is separated into an ideal waveform and one that contains the jitterinduced noise. (6.f:. For example.-MAX and RMS sampling jitter tj-RMS is .35) Recognizing that the difference operation nonnalized by T. we can consider that the effective energy contributed by each pulse at the sampling instant is ep[n]~(v[n]-v[n-l])2 * (6.18. . ~ " The effect of sampling jitter on the operation of a DAC can be described by similar mathematical expressions derived for the A~C.Chapter6 .f. then we can write the jitter-induced error as Vj[n]~(v[n]-v[n-l])ft (6. the jitter-induced error can be described as Vj(t) ~[v(nr. Mathematically.32) with the appropriate changeof variable.)-v((n-l)r.34) by T.18. ~ i Further. except that tj is replacedby . Hence we can make use of Eqs. S~mplingTheory 169 Ideal output DAC output withjittered sample timing = I~ ~ + r-u-lr U ~ Jitter-induced error Figure 6. With an error pulse occurring on average once every clock period. (6. the pulse energy is distributed over a full clock period.27)-(6.)] (6.36) dt t=nT s This expression is similar to that given for the jitter-induced error of the ADC.Jtt: 1 (6. and taking the square-root value.33) where u(t) is a unit step function.)] [u(t-nr. The effectof clockjitter on the actualDACoutputcan be separated into an idealoutputand a jitter-induced errorsignal. Consider that the effect of clock jitter on the output of a DAC can be separatedfrom its ideal operation as shown in Figure 6. the maximum conversion resolution available with a maximum sampling frequency F. we can relate this energy back to the original sample value by dividing Eq.34) .

according to Eq.11. 6.5 kHz.170 An Introductionto Mixed-Signal Testand Measurement IC 11111111111111111111 DMAX < log2 ( ~ I~~ 1r V tj-RMS~-MAX +I ) (6.- 6. (6. a particular digitizer may operate with minimum jitter when its phase-locked loop phase discriminator input is near 16 kHz. a particular tester may produce minimum jitter if the digital pattern is exercised at the tester's master clock frequency divided by 2N. the caller's voice is a random signal that seldom.1S and RMS jitter of 2.5 bits. If extremely low noise measurementsare to be performed. the test engineer should understand which sampling rates provide the leastjitter in each of the tester's instruments and subsystems. Exercises 6. 84. 408. doubling the signal amplitude or signal frequency doubles the jitter-induced noise. what is the maximum conversion resolution possible with the ADC? Ans. 6. What is the RMS value of the error induced by an ADC having an RMS sampling jitter of 100 ps while measuring a I-V amplitude sinusoid with a frequency of 100 kHz? Ans.12. repeats.4I. For instance. If a 6-bit DAC has a sampling jitter of 500 ps RMS. 8. 0. Also.3 ps. What is the maximum sampling jitter that as-bit maximum sampling rate of 10 MHz? Ans. As another example. In the cellular telephone example.8. 44.3. where N is any integer.3 REPETITIVE SAMPLE SETS . if ever. What is the maximum sampling jitter that a 6-bit ADC can tolerate when it has a fullscale input range of 0-3 V and is converting a lOO~kHz. 6.1 Finite and Infinite Sample Sets In many mixed-signal systems such as a cellular telephone.10.I-V peak sinusoid? Ans. what is its maximum sampling rate? Ans.9. If an ADC is controlled by a clock circuit with a minimum clock period of 1 J. the waveforms sampled by the system's ADC sub-blocks are nomepetitive.5 ns.27) doubling the timing jitter doubles the noise level.107~. The cellular telephone digitizes the caller's . DAC can tolerate when it has a 6.LV.37) In either the DAC or ADC case. 6. Testers often have particular sampling frequencies or other conditions that produce minimum sampling jitter.

19 shows a short sequenceof 16 samples that repeats endlessly. however. Figure 6. the fundamental frequency F/ of N samplescollected at a sampling rate of F. is also equal to one VIP UTP = F.2 Coherent Signals and Noncoherent Signals In the example waveform of Figure 6.. Ihe use of repetitive. This smooth wraparound results from a property known as coherence. Ff In general. For all intents and purposes. If we reconstruct this sample set at a sampling frequency F.39) Ff The amount of time required to collect a set of N samplesat a rate of F. is F l f =~ N (6. allowing easier debugging with spectrum analyzers and oscilloscopes.3. N (6. the last sample of the first iteration wraps smoothly into the first sample of the second iteration because there is exactly one sine wave cycle representedby the 16 samples. the sample sets are only allowed to repeat long enough to collect the necessarymeasurementinformation. If desired.Finite sampleset. 1 t Chapter 6 . ~ r In the DSP-based testingenvironment.38) The period of the fundamental frequency is called the primitive period or unit testperiod (UIP) UTP=-1 (6.19. This frequency is known as the fundamental frequency or primitive frequency.40) .we can consider the cellular telephone sample sets to be infinite in length. For example. 6.signals often created on are and measuredusing a finite sample set of a few hundred or a few thousand samples. During production testing. I. the fmite sample sets in mixed-signal testers can be repeated endlessly. repeated indefinitely.19. then the sine wave would have a frequency of FJ16. Coherence is one of the most important enabling factors for fast and accurate DSP-basedtesting. Sampling Theory 171 5 5 5 9 10 11 1213 16 15 14 9 10 11 1213 16 15 14 13 6 Figure6. finite sample sets drives a number of A IE-specific limitations which the test engineer must understand. Notice how sample 16 feeds smoothly into sample 1 at the end of each sequence... the otherhand. voice and processes the samples in real time in a continuous process.

though.5~kHz sine wave.20. sinewave(k)= sln(2*pi*3/32*(k.19 would appear at 1 kHz. . The reason for this alternate tenninology is that the only coherent frequencies that can be produced with a repeating sample set are those frequencies that are integer multiples of the fundamental frequency. then we would have a noncoherent sample set as shown in Figure 6. then the fundamental frequency would be 16 kHz/16 = 1 kHz. it usually takes an extra fraction of a UTP to allow the DUT and ATE hardware to settle to a stable state before a sample set is collected. A fundamental frequency of 500 Hz could be achieved using 32 samples instead of 16 (16 kHz/32 500 Hz). If we wanted to produce a 1.5-kHz sine wave using a coherent sample set. that the UTP drives the test time. for example. The fundamental frequency is often called the frequency resolution. it might seem that minimizing the fundamental frequency would be a great idea. Remember. We would then calculate a sine wave with three cycles in 32 samplesaccordina to ~ pis3. end Since the fundamental frequency detennines the frequency resolution of a measurement. We might choose Ff~ 500 Hz. Since one UTP is equal 4 14 4 14 4 14 1 Figure 6. In the absenceof test time constraints.4).19 at a rate of 16 kHz.5 kHz sine wave. then we would have to choose a sampling system with a fundamental frequency equal to 1. if we source the samples in Figure 6. where N is any integer..5 kHz/N. (6. in terns of N and the sampling frequency. The astute reader will recognize that we first made use of coherent frequencies in Section 6. where!o~Fc' As an example.1 in the development ofEq. and then use the third multiple of the fundamental frequency to produce the 1. Hence. N.14159265359j for ks1:32.2. Noncoherent sample sets cannot be looped properly.20. . The sine wave in Figure 6.. a fundamental frequency of 1 Hz would provide good flexibility in test frequency choice. The next-highest frequency we could produce with 16 samples at this sampling rate is 2 kJiz. 1.1)). the coherent frequenciesF care FC =M ~ N where M is an integer 0. If we wanted to produce a 1.41) In practice.172 An Introductionto Mixed-Signal Testand Measurement IC (6.2..

5.. ~ " " Chapter6 . they can be analyzed with DSP operations using a preprocessing operation called windowing. SamplingTheory 173 For most to 1IFf. especially as the number of tones increases.. this would be unacceptable. and frequency designated by (Mil N) F. . while the secondwaveform consists entirely of cosine waves. phase1 =0. though.. and seventh spectral bins. Consider the 7-tone multi tone signal in Figure 6. The multitone signal calculated would be described as a three-tone multitone waveform with equal amplitudes at the third. 6. all the frequency components are created at the same phase (0 degrees).2. The endpoints of this waveform would wrap smoothly from end to beginning because the waveform is coherent. fifth. However.3... phase shift ~ . and 3.5 kHz using an expanded calculation given by the following MA TLAB routine pi=3. having different coherent frequencies) according to the following formula v[n]=t4sin 1=1 ( 2Jr~n+f/JI N ) (6. phase2=0. The integers representedby Mi are commonly referred to as the Fourier spectral ' bins. Many test situations call for the application of a coherent multi tone signal to excite a device. These waveforms exhibit a spiked shape that is unacceptablefor most testing purposes since it tends to causesignal clipping in the DUT's circuits. .141S926S3S9. The problem with this type of waveform is that it may have an extremely large peak-to-RMS ratio...21. Although noncoherent sample sets cannot be used to generate continuous signals through a looping process. windowing is an inferior production measurement technique compared to coherent. + phase1*pi/180) .e. production tests.42) I Here each sine wave is assigneda unique amplitude Ai." Returning to the l6-kHz sampling example. for k=1:32.3 Peak-to-RMS Control in Coherent Multitones Notice that in the multitone example in Section 6. the entire waveform will be noncoherent. multitone(k) phase3=0. The first waveform consists entirely of sine waves. Windowing will be discussed in Chapter 7. Such a signal is created by simply adding together a set of J unique sine waves (i. nonwindowed testing.5. i~ Any signal made up of a sum of coherent signals is also coherent. 2. . a I-Hz frequency resolution would require 1 s of data collection time.3. we could create a multitone signal with frequencies at 1. If one or more of the ~! frequency components are noncoherent. "DSPBasedTesting. = sin(2*pi*3/32*(k-1) + sin(2*pi*S/32*(k-1) + sin(2*pi*7/32*(k-1) end + phase2*pi/180) + phase3*pi/180.

22 shows how rand9mly selected phasesfor the seven tones of Figure 6. this might happen when an upgraded tester operating system includes a change to the pseudorandomalgorithm.22.then the program tries again until the desired ratio is found. but the use of hard-coded phasesremoves one more unknown factor from the measurementcorrelation effort.. Larger RMS signalsprovide better noise immunity and improved repeatability.174 An In""".Puresineand purecosineseven-tone multitones. Theoretically. The wavefonn in Figure 6. If the desired peak-to-RMS ratio is not achieved with one set of pseudorandomphases.=S. But this kind of signal is v(t) t Figure 6. In many test programs. a different set of phases should not causeany shift in measurementresults. This would provide the largest RMS voltage for a given peak-to-peak operating range. phases are chosen using a pseudorandom number generator with a unifonn probability distribution between 0 and 21rradians. .21. Unfortunately. there is no equation to calculate phases to give a desired peak-to-RMS ratio.21 produces a much less "spikey" wavefonn. Seven-tone multitone createdwith randomphases. What is the ideal peak-to-RMS ratio for a multitone signal? At first it might seem that it would be best to let the pseudorandomprocess search for a minimum peak-to-RMS ratio. . The peak-to-RMS ratio of a multitone can be adjusted by shifting the phase of each tone to a randomly chosen value.gM1IC v(t) Testand Measurement ~ Equal-amplitude sine waves Equal-amplitude cosine waves Figure 6. For example. or they can be hard-coded into the test program once they have been detennined through trial and error. These phase values can be generated each time the program loads. This second approach prevents a pseudorandomalgoritlun from choosing one set of phaseson a given day and another set of phasesat a later date.

(6. Repetitively exercising the same code levels results in less robust fault coveragein the DAC and ADC circuits. A multitone signal must contain at least six tones to hit a peak-to-RMS ratio of3.35:l. but it is still a good idea to use pseudorandom phase shifts for the tones ~ rather adding sine cosine than pure or waveforms. and 3 kHz. then accordingto Eq.and intermodulation distortion components.23. The second and third harmonic I . so this choice of bin. The problem with this multitone is that there is a great deal of distortion overlap.3. The number 4=22 is not mutually prime with the number 32=25. As it happens. The use of mutually prime bins does not necessarily prevent intermodulation distortion overlaps. it is based on the approximate peak-to-RMS levels encountered in typical analog signals. so we are just testing the same points repeatedly.41) the nearestFourier spectral bin is I ~ "' . 6. (Mutually prime numbers are ones containing no common factors). The problem with bin 4 is that it is not mutually prime with the number of samples.which would ruin the measurementaccuracy. the pseudorandom phase selection process should be set to search for a peak-to-RMS ratio of between 10 and 11 decibels. 2. and number of points is a poor one. I ' . For signals having fewer tones. but it makesthem less likely. the target ratio is not terribly important. Consider the example of a three-tone multitone at 1. the DUT will usually see a peak-to-RMS ratio of about 10-11 decibels (a ratio of about 3. we see that the quantization errors repeat four times in the sample set.32.harmonic distortion components.4 Spectral Bin Selection One of the common mistakes a novice test engineer makes is to choose spectral bins by simply calculating the nearest integer multiple of the fundamental frequency. This range is roughly equal to the peak-to-RMS ratio of broadband signals having near-Gaussian-distributed amplitudes and random phases. For this reason. In many end applications. Sampling Theory 175 susceptibleto large shifts in peak-to-RMS ratio if any of the filters in the ATE tester or DUT causefrequency-dependentphase shifts. a nonprime spectral bin hits fewer code levels on the DAC and ADC. Furthermore. Whether mutually prime bins are chosen or not.Chapter 6 . I : One of the problems with non-mutually-prime spectral bins is that they may cause the quantization noise of a coherent signal to contain periodic errors instead of errors that are f randomly distributed over the UTP. Although the 10-11 dB range appears in many data sheetswithout explanation. A change in peak-to-RMS ratio could lead to a clipped signal. one should verify that all distortion components fall into spectral bins that do not coincide with bins containing important signal information. samplingfrequency. if the test engineer wanted a 2-kHz sine wave using a l6-kHz sampling rate and 32 samples. which correspondsexactly with spectral bin 4. If we look at a quantized version of this signal from a 4-bit ADC in Figure 6. The same problem occurs with DAC convertersas well. Consider the sine example with 4 cycles in 32 samples. For example. I M= 2kHz =4 (16 kHz/32) . this ratio also tends to produce a multitone whose peak-to-RMS ratio is least sensitive to phase shifts from filters. Another problem with non-mutually-prime bins is that they tend to lead to overlaps between test tones.35:1).

40) to be N~50ms x 16kHz=800 An important constraint on the number of sample points used in most test systems is that N must be a power of two (i. we shall . . . . . . . All these overlaps would cause errors in any measurementinvolving the 1-.distortion. . . . distortion of the I-kHz tone falls on top of the 2. To avoid overlaps between harmonic distortion components and signal components. .and 3-kHz test tones. . . etc. . Use a 16-kHz sampling rate. . Therefore. . The signal should take no more than 50 ms to repeat. . . For example. .e. . A better approach is to use test frequencies close to the desired frequencies. the third harmonic of spectral bin 3 coincides with the tone at bin 9. . . ZP. Periodic quantization errors appear as gain error and harmonic distortion Figure 6. . . the number of sample points is found from Eq. . . Non-mutually-prime spectralbin selection leadsto periodicerrors. resulting in an overlap. Solution: With a maximum UTP of 50 ms and a sampling rate of 16 kHz. Consequently.). the second order intermodulation distortion between the 2-kHz tone and the 3-kHz tone appears at I and 4 kHz. . but located'at spectral bins that do not causeany intermodulation or harmonic distortion overlaps. . Also. . (6. . . . . but they are not mutually prime with one another.where P is an integer). . . . .2-. corrupting the I-kHz test tone. Example 6..but that they are also mutually prime with one another.23. . respectively. . . .176 An Introductionto Mixed-Signal Testand Measurement IC ~ Non-mutually-prime spectral bin . . . . 2. . The reason for this will be explained in more detail in Chapter 7. . .5 Select the spectral bins for a three-tone signal at I. but it is becausewe will ultimately use the Fast Fourier Transform (FFT) algorithm to measure the response of the DUT to the three-tone signal. . . bins 3 and 9 are both mutually prime with 512 samples. or 3 kHz tones (gain. . and 3 kHz with no more than :i:50 Hz error in the signal frequencies. frequency response. we should guaranteethat the tones are not only mutually prime with the number of samples.

shift to 63) 31.38). so the harmonic distortion overlap criterion is met. . shift to 31) 31. We want the highest possible N in order to achieve the greatest frequency resolution or the smallest fundamental frequency. Next we look for intermodulation components. that is. ~Pling Theory 177 select N equal to 512.25 Hz M 2 = 2 kHz = 64 (non-mutually-prime. !I. and 3-kHz signals are found using Eq.the computed spectral bin values were all even numbers sharing a factor of 2 with the number of samples. (6. and 97.25 Hz MJ = 3 kHz = 96 (non-mutually-prime.25 Hz = 968.Chapter6 . shift to 97) 31.75 Hz h =97x31. The resulting test frequencies. 2-.25 Hz In all three cases. Shifting the result by one in either a positive or negative direction eliminates their dependenceon the common factor of 2. which is located at 8 kHz. Intermodulation components appear at the sum and difference of any two tones. or bin 256).75 Hz h =63x31. =31x31. Working with 512 samples. 512.41).25 Hz In all three cases. First we list the harmonics of the three test tone bins (stopping at the Nyquist bin. to be M1 = 1 kHz = 32 (non-mutually-prime. andJ3are then J. the fundamental frequency becomes Ff =~=31. 63.25 Hz =3031.h. Harmonics are defined as all the frequencies at an integer multiple of the test tone and computed according to the following table: Harmonic/ Test Tone M) M2 M3 MA 31 63 97 2MA 62 126 194 3MA 93 189 4MA 124 256 5MA 155 6MA 186 TMA 217 8MA 248 - - - - - - - - - - None of these harmonics overlaps with the other harmonics or with the test tones.25 Hz = 1968. the closest spectral bin numbers that correspond to the 1-. together with Eq.25Hz 512 Subsequently. We now have to verify that there are no distortion overlaps using spectral bins 31. (6. 2F)-F2.the chosen test frequencies are within the desired:1:50Hz error margin and are therefore acceptable.

third-order distortions are those in which the magnitude of the integers add up to 3. This gives poor fault coverage for the circuit under test becauseit exercisesone side of the signal range more than the other. Since there are no overlaps in this example.23. . When we are at the bottom of the table. If we had chosen bin 62 for the 2-kHz tone. The choice of mutually prime bins does not guarantee a lack of overlap between intermodulation components and test tones or distortion components. In most cases. none of the harmonics interferes with any of the intermodulation components. The ability to measure multiple parameters using a single data collection cycle is an advantage of multitone testing. Thus the mutally prime rule prevents us from using even-numberedspectralbins. none of the intermodulation components falls on top of a test tone.).we choose a sample set consisting of an even number of samples. frequency response. As is evident from this table./ Test Tone M1 M2 M3 MA 31 63 97 IMA-MBI IMA+MBI 32 34 66 94 160 128 I2MA-MBI I2MA+MBI 1 29 163 125 223 225 IMA-2MBI 95 131 35 IMA+ 2MBI 157 257 159 Here the letter A and B represent the current and next row spectral bin. we can measure gain. This technique saves a tremendous amount of test time compared with single-tone testing approaches. but it may lead to the kind of quantization noise modulation illustrated in Figure 6. The DC offset of such an asymmetrical multitone is not centered between the maximum and minimum voltages. for example. we chosebin 63 instead of 62 becauseit was mutually prime with the number of samples. There are so many of thesethat it is usually sufficient to just limit the list to secondand third-order distortions.24 shows the difference between an all-odd multitone and a mixed odd-even multitone. The following is a table listing the intermodulation interaction between the three test tones: Intermod. Of course a single-tone signal with an even harmonic does not have the asymmetry problem. intermodulation distortion.178 An Introductionto Mixed-Signal Testand Measurement IC FI+3F2. As we have seen. Combinations of odd harmonics and even harmonics in a multitone signal result in a signal with asymmetrical positive and negative peaks relative to the DC offset of the signal. Figure 6. and signal-to-noise ratio with the same set of collected samples. the next spectral bin refers to the data at the top of the table. multitone DSP-based testing only provides accurate measurementsif the test engineer is careful with the selection of test tones. etc. but it does reduce the likelihood of such overlaps. There is a second reason that we chose 63 and not 62. etc. (Second-order distortions are those in which the magnitude of the integers in front of FI and F2 add up to 2. In the previous example. harmonic distortion. Careless selection of spectral bins will lead to answers that may be slightly incorrect. The lack of overlap between harmonic distortion componentsand test tones in this example is guaranteedby a choice of mutually prime bins. In addition. then the second harmonic distortion from the I-kHz tone would have affected the measuredlevel of the 2-kHz tone by a small but significant amount.

All we have to do is select slightly different test tones on the DAC side from those used on the ADC side.1. .non-mutually-prime or even-numberedbins can be used as a last resort. Spectralbins2. if the DAC and ADC have channel-to-channel crosstalk specifications. . The DAC responsemust be digitized before being stored into ATE memory.1 Simultaneous Testing of Multiple Sampling Systems Many DUTs contain both ADC and DAC channels. as in the case of the voice-band interface of Figure 6. The response of each channel would then be analyzed through a postprocessing frequency-domain operation and judged suitable or not. The respopseof the ADC is collected directly into ATE memory for later processing.' . The bottom line is that odd-numbered. crosstalk between the ADC and DAC channels can lead to small gain errors if we use the same test tones in both channels.4. Simultaneous testing requires a digital pattern loop containing the appropriate samples to excite the DAC channel.24. Often. we might test the gain of the ADC channel and the DAC channel simultaneously using this approach. and 7 (asymmetrical peaks) Figure 6. These channels are often tested simultaneously in an ATE test program to minimize test time.5. and 7 (symmetrical peaks) I~ . Unfortunately. At the same time. Then the feedthrough from DAC to ADC will show up in different bins from the ADC signals and vice versa.Chapter6 . an A WG converts another set of samples into analog form to excite the ADC channel. This is made possible by operating the various components of the ATE . If the situation is truly desperate. However.. SamplingTheory 179 - Spectral bins 3. mutually prime spectral bins should always be used wheneverpossible. the gain errors are small enough that we can live with them.4 SYNCHRONIZATION SAMPLING SYSTEMS OF 6. 6. Even spectral bins lead to asymmetrical peaks relative to the signal's DC offset. we can save some test time by measuring the crosstalk during the gain test. 5. For example.

14. minimum distortion overlap occurs. Subsequently. 1/512MHz. ADS. 6.What is the nearest coherent frequency 20 kHz when 512 samples collectedat a to are rateof 44 kHz?How manycyclesarecompleted oneUTP? in ADS. with a maximum test tone error of 100 Hz. ". this also implies that the fundamental frequency Ff is the same for all components and will guarantee coherent sampling sets in both signal paths.8 kHz and that the UTP must be less than 100 ms. 1501. and 3 kHz. as shown in Figure 6. 20. r.:. Use three tones at 1.the fundamental frequency Ffwill be Ff =~=3l.17.023 kHz. Assume that the sampling rate is 44. 512 Ils.6 A DUT's DAC and ADC both operate at a 32-kHz sampling rate.Usinga handanalysis.. Find a sampling system that tests the gain of a DAC channel and an ADC channel simultaneously. 2.180 An Introduction to Mixed-Signal Testand Measurement IC .How manycyclesof a 2. '" A2 + B2 6.2 r:. ADS.17cycles.What is the fundamental frequency 512 samples of collectedat a rate of 1 MHz? What is the corresponding UTP? Ans. Select the spectral bins of a two-tone signal at 15 and 30 kHz such that. In turn. Example 6. 233 cycles.16..15.13. Solution: Let us start by setting the number of samples in the waveform exciting the DUT's DAC and ADC at N=1024.2999.1.~IIIIII Exercises 6.9532 6-msUTP? in 1 ADS. A+B and DUT at different test frequenciesbut ensuring that they have the same UTP. 6.1375-kHz sinewavearecompleted a 7. 6. Let us consider the following example.--. compute peak-to-rrns the ratio of a two-tonemultitonedescribed by Asin(~t)+Bsin(OJ2t).25Hz 1024 .

If we then set the digitizer sampling rate to 16 kHz and collect 512 samples from the DAC output. In the remaining sections we shall examine some of the ATE clocking architectures that the test engineermight encounter. if it takes 30 ms to collect the DAC channel samples. This in turn requires that the sample set consist of 512 samples.or flying adders. Beginning with the ADC channel test. To allow simultaneoustesting of the ADC and DAC gain. since the UTP is the inverse of the fundamental frequency. we would create a sampling system with the same fundamental frequency as the ADC.Chapter 6 . It allows us to make coherent crosstalk measurements between two supposedly isolated signal paths. 6. as long. though.. all the clocks in a mixed-signal tester should be referenced to a single master clock so that all instrumentation can be synchronized to achieve coherent sampling systemsduring each test.. the sampling frequencies are often related by a simple integer multiple (i. assuming we drive the ADC and DAC from the samedigital pattern loop. though. The preceding example demonstrates one of the reasons we prefer to use the same fundamental frequency for both ADC and DAC. we will create an A WG waveform with 512 samples. 2 and 3 kHz. Ultimately. we would again achieve a fundamental frequency of 31. and 95 to meet all our testing criteria. For instance. Identical UTPs drive identical fundamental frequencies. Matching all the fundamental frequencies in a particular test would be easy if we could simply requestany arbitrary sampling rate from the ATE instruments. we might have a choice of any sampling frequency we want as long we want a multiple of 4 Hz. Sampling Theory 181 The desired three tones will then be located in spectral bins of 32. we shall select the sampling rate of the A WG to be 16 kHz and impose the constraint that it has a fundamental frequency of 31. Henry Ford once said that you could purchase a Model T automobile in any color you wanted. guaranteeing coherence.e. Unfortunately.25 Hz. . the ADC and DAC are not designed to sample at the same frequency. By feeding 1024 samplesto the DAC at 32 kHz. Fortunately. resulting in the desiredtest frequencies of 1. 67.2 ATE Clock Sources Mixed-signal testers use a variety of different approaches to clock generation. 64 and 96. then it also takes 30 ms to collect the ADC channel samples. We can choosebins 33. To achieve the same fundamental frequency as the AWG signal. We will source this signal from the AWG at a 16-kHz sampling rate. 63. 16 and 32 kHz). The other reason is that the UTP for the ADC and DAC is identical by definition. frequency synthesizers.25 Hz. For example.:asyou wanted black. we need to select different spectral bins than thoseused to test the ADC. many ATE testers have a limited choice of sampling frequencies.we can simply collect more samples on one channel than on the other to achieveidentical fundamental frequencies. Using this sampling system we know that the ADC sampleswill form a coherent sample set.4. and 97. Each of these has strong points and weak points that the test engineer will have to deal with. the ADC must collect 1024 samples (32 kHz sampling rate/1024 points = 16 kHz sampling rate/512 points). Using the sampling rate and spectral bins from the prior example. The most common clock generation schemesinvolve phase-locked loops. Sometimes a particular tester architecture gives us a similar choice of sampling rates. In these cases.having test tones at bins 31. Next let us consider theDAC channel test. Sometimes.

Clearly./ F D' .25. since a reference clock would have to come from the samedigital pattern generator feeding the DAC its samples. r MHz .43) This particular example imposes a number of restrictions on the test engineer. Frequency synthesizerswork by taking a reference clock (10 MHz.182 An Introductionto Mixed-Signal Testand Measurement IC . and other digital signals. First. More modem testers allow the test engineer to select a wider range of frequencies using a frequency synthesizer. The phase-locked loop (PLL) frequency generator is a circuit that produces an output clock equal to a reference clock times Mover N.5-15 i i X: ~ i . for example) and passing it through a series of dividers and frequency mixers to produce a very stable output frequency with very little jitter. Finally. the value of N must be between 2 and 2048. ATE PLL-based digitizer clocking source. The output of the divide-by-N stage should be as close to 20 kHz as possible for maximum stability of the PLL.2048 ~~ I a s ! Divide: by M ~ ! i ~ 20 kHz :t5 kHz +256 1024 : ~ ' Figure 6. adding a bit of wait time between tests. IVId e External clock (0-25 MHz) ! I : +2 byN .25 operates by first dividing the reference frequency F REF N. the externally supplied reference clock must be between 0 Hz and 20 MHz. It consists of several counter stagesand a voltage-controlled oscillator (VCO). this clocking architecture is very inflexible and puts a large burden on the test engineer. Finally. Internal clock (10 MHz) M i I ' Phase locked loop i U' : : 7. The value of M must be between 256 and 1024. Every time the PLL is reconfigured it must be allowed to settle to a stable state. but that is the price paid for low jitter. These synthesizers also take significant time to stabilize (25-50 ms). The VCO output must be between 5 and 10 MHz. Other frequencies will work. then by multiplying the result by M through the divide-by-M by counter in the negative feedback loop around the VCO. =-FREF NL (6. This PLL is used to generate the sampling clock for a digitizer. The PLL shown in Figure 6. The external reference is required if a DAC output is to be digitized. frame syncs. It can use either a fixed 10-MHz internal frequency reference or an externally supplied reference frequency. the frequency of the VCO output can be further divided by another counter stage. Synthesizers are not entirely . Next. An example ATE PLLbased clocking architecture is shown in Figure 6. where M and N are integers. but will introduce additional jitter into the clock.25. which divides the output by integer L resulting in the output sampling frequency F s given by M F. the value of L must be between 1 and 65535.

: I I d3 I' i'4-. flexible either. the pattern generator can only run at frequencies less than 25 MHz. A flying adder works by using a high-frequency reference clock and calculating the difference between the desired clock edgesand the clock edgesproduced by the reference clock. I I I -y ir--\ !\.!-":d2~: " :: . 6. The choice of filter cutoff frequency also places restrictions on two other integer dividers. flying adders are sometimes more prone to jitter than frequency synthesizers. but they may introduce a little more jitter than a frequency synthesizer. The following example shows how one particular tester's clocking architecture is arranged.r-\ frequency -Jf\_: I ~14 ." Becausethe edges are generatedby programmable delay circuits. the master clock operating a digital pattern generator may be divided by an integer before it is applied to the pattern generator's memory address counter. Clock generation using flying adder delays. Each desired clock edge is generated by delaying each reference clock edge by a carefully calculated amount of time as shown in Figure 6. Digitizers and A WGs often perform even more convoluted operations on the clock before the final sampling clock is produced. SamplingTheory 183 Reference.3 The Challenge of Synchronization The clocks generated by an ATE tester are sometimes modified further by the instruments or subsystemsthat use them. I : : I I I I I ! ir-\! -+-V\.4. a particular synthesizer may only be able to produce integer multiples of 4 Hz. It must be a multiple of 4 Hz. d4 ~ I : I I I I I Figure 6. For instance. For example. A new delay time has to be calculated for each delayed clock edge. I I I I I I I I I I I I I I I I I I . I I I I I I I I I :: I I : . the frequency stabilization time for a flying adder clock circuit is nearly instantaneous. However. However. The clock divider may have restrictions similar to the ones mentioned in the PLL example. .26. This clock is divided by an integer A to produce the clock for the digital subsystem's pattern generator.--V ir\ : -. I Desired: .Chapter6 . The master clock is also divided by another integer to produce a reference clock for a sigmadelta-based digitizer. thus the terminology "flying adder. The digitizer clock input must fall within certain ranges. Flying adders can allow an even more flexible clocking source with little settling time.26.based on the desired cutoff frequency of the digitizer's antialiasing filter. The calculation is performed on the fly by an adder circuit. The master clock for the tester must be set between 160 and 200 MHz.: I I I I I I I I : I I I : L- d1=0 ~ ..Y--\--Y---\---V--\--Y-\ J-' : : frequenc : y I : : . . the oversample divider (OSD) and the decimation factor (Dr).

specified in the DUT's data sheet. such as the fast Fourier transform (FFT). Exercises 6. and the divide-by-L equal to 64. The clock calculation task can be handled by software tools or by longhand calculations on paper.414 kHz and 12. in the analysis of the samples collected during a coherent mixed-signal test. The digital pattern must run at a particular frequency. With all the restrictions placed on a test engineer by the ATE clocking and divider architectures.5 MHz. . 195. An ATE PLL-based clock source such as the one in Figure 6. we will explore the use of digital signal processing algorithms. Since each tester presents a totally different set of clocking restrictions. this level of coverage should be adequatefor beginning mixed-signal test engineers. Sample sizes should be powers of two for use of efficient FFT routines. what is the output sampling frequency? Are all frequency constraints met in this configuration? ADS. digital signal processing allows a combination of low test time and high accuracy not possible with conventional. As we will see.25 is set with the divideby-N counter equal to 1024. The tester's clocks must fall within certain ranges at each stage in the frequency divider chains. regardless of clocking peculiarities.44) Clearly. The basic rules of coherent sampling theory taught in this chapter apply to all testers. we have presented an introduction to sampling theory and coherent sampling systemsas they are applied in mixed-signal ATE testing. The DUT's DAC and ADC must run at particular frequencies. the divide-by-M equal to 512. this book will not attempt to teach a general approach to working through the clock and clock divider calculations.184 An Introductionto Mixed-Signal Testand Measurement IC These integers must be chosen from a limited set of values listed in a digital filter table. Yes. the test engineer will have to spend time learning about a tester's clocking architecture and its restrictions so that the inevitable tradeoffs in test time and performance can be made in an informed manner. It can be a maddening process to calculate a coherent sampling system without violating any of the tester's clocking rules. setting up the sampling rates in a mixed-signal tester can be a complicated process. 6. intermediate frequencies are 24. sourced. and captured. While the treatment of this material is not as thorough as one might encounter in a signal processing textbook. Either way. it is sometimes impossible to find an acceptable sampling system for a given test. we have only seenhow coherent multitone sample sets are created. all the sampling rates and number of points must result in the same fundamental frequency for all the DACs and ADCs in the DUT and tester. Finally. Thus far. The final sampling rate of the digitizer is then calculated by the following formula F $ - FMCLK AxOSDxDF (6. With a reference frequency of 25 MHz.18. Constant reprogramming of the master clock may add extra test time because of frequency synthesizers. In the next chapter.5 SUMMARY In this chapter.3125kHz. purely analog instrumentation.

2. and M). RepeatProblems 6. N=128.1.3. f/J. calculate the N.12. Using the triangular characteristic pulse defined in Example 6. andM=65 (f) A=0.2 with a sampling rate of 8 kHz.9.5 6.10.1 and determine the frequency of the resulting sine wave. What is the RMS value of the error induced by an ADC having an RMS sampling jitter of 250 ps while measuring a I-V amplitude sinusoid with a frequency of 20 kHz? 6. reconstruct the samples obtained in Problem 6. Identify any situation where aliasing occurs.=0.5. t. Using a second-orderhold function where the interpolation is done by passing a quadratic function through the points at (n-2)Ts. 6.1. what would be the noise component for a 5-bit ADC having the sameinput range? 6. assumea 1 LSB maximum allowable voltage error. plot the samples of the signals described in Problem 6. what analog frequency will be heard? Repeat for A=l.3 and determine the frequency of the resulting sine wave.1. How does the reconstructed waveform compare to a zero-order hold function (square pulse) and a first-order hold function (triangular pulse)? 6. frequency of the resulting sine wave assuming a sampling rate of 1 Hz. N=64.=0. What are the minimum and maximum values of the input voltage corresponding to this output code? 6. and nTs. N=32. Sampling Theory 185 Problems 6. t.6.Chapter 6 . What is the maximum allowable sampling jitter that a 10-bit ADC can tolerate when it has a full-scale input range of 3 V and converting a I-V amplitude sinusoid with a frequency of 20 kHz? . t. 6. Hint: Reconstruct the discrete signal using MATLAB and observe the frequency of the reconstructed signal.= 11/8. For the following parameters of a sampled sine wave (A.4. N=64.5 V gives an output of code of 37 for a code range beginning at 0 and ending at 63. (1=0. Identify any situation where aliasing occurs.=0. t.N=32.1 over its UTP. t. What is the LSB of an ideal 12-bit ADC that has a full-scale input range of 0-3 V? What is the expected RMS value of the corresponding quantization noise? 6. What are the UTP and the fundamental frequency related to this collection of samples? (a)A=2.=11/2. andM=33 (e)A=l.7. reconstruct the samples obtained in Problem 6. 6.2.5.8.11. 6. and M=2. andM=l (b)A=I. A 6-bit ADC with an analog input range from -1. t. reconstruct the samples obtained in Problem 6. N=32. Using the square characteristic pulse defmed in Example 6. and M=25. andM=13 (c) A=2. t.5 to +1.=51d8. If a digital sinusoidal signal described by A= 1.N=32.=0. Using MATLAB or an equivalent software program.1 and 6. 6. (n-1)Ts. and M=5 is played through a DAC and speaker arrangementwhose sampling rate is 8 kHz. In each of the following questions. and M=5 (d)A=l. If an ideal 8-bit ADC has a 400 !lV RMS quantization noise component. N=64.

.

A.. 1971. Hoel. Oppenheim et al. 37. Proc. March 1989. Port. 6. NJ.W. Circuits. 3. MA. a divide-by-M counter with a range from 1 to 256 and a divide-by-L with a range of 1 to 65535.C. The accuracy of the test frequencies should be less than :1:100 Hz. The MIT Press. Assume that the sampling rate is 44. IEEE. Peak Factor Minimization of the Input and Output Signals of Linear Systems. August 1997. Vol.Prentice Hall. Paul G.. p 118 6. Discrete-Time Signal Processing.28. Matthew Mahoney. J. 1730 MassachusettsAvenue N. 65. Signals. Vol. With a reference frequency of 200 MHz. Cambridge. An ATE PLL-based clock source is set with the divide-by-N counter equal to 4096.1997 7. Select the spectral bins of a four tone signal at 1. Tutorial DSP-Based Testing of Analog and Mixed-Signal Circuits. and the divide-by-L equal to 128. NJ. ISBN: 039504636X. J.' ! . Sampling Theory 187 6. The Shannon Sampling Theorem -Its Various Extensions and Applications: A Tutorial Review. E. 2. No. Signals and Systems. With a reference frequency of 200 MHz. Englewood Cliffs. Washington D.26. and Systems. Houghton Mifflin Company. Schoukens. Sidney C. Jerri.27. Charles J. pp. Alan V. Stone. J. Schafer. June 1988 -'i~. William McC. what is the range of the output sampling frequency? References 1. September1985. ISBN: 0262192292 5.IEEE Transactions on Instrumentation and Measurement. Renneboog. 1565-96. Introduction to Probability Theory.1987. ISBN: 0138147574 4. the divide-by-M equal to 512. ISBN: 013216292X 3. Oppenheim. Englewood Cliffs. Siebert. Justify your answer by providing the appropriate distortion tables. Alan V. ISBN: 0818607858 2. what is the output sampling frequency? 6.2. 200361903. Boston. An ATE PLL-based clock source has a divide-by-N counter with a range from 1 to 1024. and 4 kHz such that minimum distortion overlap occurs. Ronald W.8 kHz and that the UTP must be less than 100 ms. The Computer Society of the IEEE. Prentice Hall. V. Ouderaa..Chapter 6 . MA.

1 Reduced Test Time In Chapter 6. we can perform many parametric measurements in parallel.CHAPTER 7 DSP-Based Testing 7. Using coherent test tones.e. This allows for much more accurate and repeatablemeasurementsof the primary test tones and their distortion components. Since we can create and measure signals with multiple frequencies at the same time. many good texts have been written on the subject. 189 . we are always guaranteed that all the distortion components will fall neatly into separateFourier spectral bins rather than being smeared across many bins (as is the case with noncoherent signal components).1 ADVANTAGES OF DSP-BASED TESTING 7. we will take a more detailed look at digital signal processing and the power it gives us in testing mixed-signal devices. we briefly touched on the advantagesof DSP-basedtesting before beginning our review of sampling theory. we will review the basics of DSP..In this chapter. sampled) waveforms of finite length. In this chapter.1. Once we have collected the DUT's output responseusing a digitizer or capture memory. The first advantageof DSP-basedtesting is reduced test time. DSP allows us to separateeach test tone in the output waveform from all the other test tones.1. Although a full stud! of DSP is beyond the scope of this book.1. DSP-based testing is a major advantage in the elimination of errors and poor repeatability. we can perform a series of gain and phase measurementsat a dozen or so frequencies simultaneously. further reducing test time. for example.2 Separation of Signal Components Separationof signal components from one another gives us a second huge advantage over nonDSP-basedmeasurements. Coherent DSP-based testing gives us several advantages over traditional measurement techniques. If we need to test the frequency response and phase responseof a filter. limiting our discussion to discrete (i. 7. We can isolate noise and distortion components from one another and from the test tones. We can then calculate a separategain and phasemeasurementat each frequency without running many separatetests. We can also measurenoise and distortion at the same time that we measuregain and phase shift. DSP-basedtesting allows us to send all the filter test frequencies through the device under test (DUT) at the same time.

Then we shall look at the different ways we can process digital signals. % Subtract offset from each waveform sample x=x-average. Depending on the sophistication of the tester's operating system. All these techniques are made possible by the application of digital signal processing to sampled DUT outputs. In MATLAB. voltage samples). There are many array processing functions that prove useful in mixed-signal test engineering. We can compute the DC offset of the digitized wavefonn using an averaging function. or vector. since it is limited to mathematical operations on time-ordered samples. making a separate array processor unnecessary in some of the newer testers. We can remove noise from signals to achieve better accuracy. This DC removal routine can be considered a digital signal processing operation. So much for semantics! ATE digital signal processing is often accomplished on a specialized computer called an array processor. One simple example is the averaging function. but the samples are ordered in time.2 DIGITAL SIGNAL PROCESSING 7. Subtracting the offset from each sample in the wavefonn eliminates the DC offset. These built-in operations are streamlined by the ATE vendor to allow .2. x average=sum(x)/Iength(x). There is a slight semantic difference between digital signal processing and array processing. An example of array processing would be the calculation of the average height of the students. A digital signal is also a set of numbers (i. the presence or absence of a separate array processor may not even be apparentto the user. since most arrays processed on an ATE tester are in fact digital signals. 7..e. If we want to measurethe RMS noise of a digitized wavefonn. we are able to take advantage of many built-in array processing operations in mixed-signal testers rather than writing them from scratch. We can perfonn interpolations between the samplesto achieve better time resolution. An array. However. such as a record of all the heights of the students in a class. resulting in an erroneous noise measurement. We can apply mathematical filters to emphasize or diminish certain frequency components.3 Advanced Signal Manipulations In this chapter we will see how DSP-based testing allows us to manipulate digitized output wavefonns to achieve a variety of results. tester computers have become faster over the years.190 An Introductionto Mixed-SignalIC Testand Measurement 7.1 DSP and Array Processing Before we embark on a review of digital signal processing. although a dedicated array processor is not needed to perfonn the calculations. Digital signal processing is thus a subset of array processing. we must flTst remove the DC offset. most automated test equipment (ATE) languages categorize all array processing operations under the umbrella of DSB. Fortunately. we might accomplish the DC removal using the following simple routine: . The average of a series of samples is equivalent to the DC offset of the signal. let us take some time to define exactly what a digital signal is. % DC Removal Routine % Calculate the DC offset (average)of a waveform. is a set of similar numbers. Otherwise the DC offset would add to the RMS calculation. However.1.

~. It may also shift the phaseof each frequency component. some of the computations may take place in parallel using multiple array processors. while the term "scalar" refers to a single value. For example. thus saving test time. DSP-Based Testing 191 the fastest possible processing time on the available computation hardware. Operations such as the discrete Fourier transform (DFT). fast Fourier transform (FFT). It is a mathematical method that gives us the power to split a composite signal into its individual frequency components. waveform[256].: ""c Not only are the built-in operations simpler to read. Although tester languages vary widely. The following are examples of array processingfunctions that are typically included in an ATE array processor.2 Fourier Analysis of Periodic Signals The tremendous advantage of DSP-based testing is the ability to measure many different frequency components simultaneously. It is based on the fact that we can describeany signal in either the time domain or the frequency domain. minimizing test time. and filtering operations will require a little more explanation. The term "vector" refers to an array of values. Fourier analysis allows us to convert a signal from the time domain to the frequency . waveform = waveform offset. they often execute faster than userdefined routines written in a language such as C. the following pseudocode is representative of typical ATE array processing operations: float offset. It is easy to see how we can apply a multitone signal to the input of a filter. offset =average( waveform[ 1 to 256 ] ). For example. A digitizer can then be used to collect samples from the output of the filter. inverse FFT. But how do we then extract the amplitude of the individual frequency components from the composite signal at the filter's output? The answer is a Fourier analysis.22 to a low-pass filter.22 and apply it through an arbitrary waveform generator (AWG) to the input of the filter.2. we can apply a seven-tonemultitone signal such as the one in Figure 6. We simply compute the sample set in Figure 6. Fourier analysis allows us to convert time-domain signal information into a description of a signal as a function of frequency. 7. The filter will amplify or attenuate each frequency component by a different amount according to the filter's transfer function. lIB .11- Chapter7 . vector average: averagevalueof an array vector RMS: root meansquareof the valuesin an array maximin: locateand reportthe maximumand minimumvaluesin an array vector add: add two arrays add scalar to vector: add a constantto each elementin an array subtract scalar from vector: subtracta constantfrom eachelementin an array vector multiply: multiplytwo arrays multiply scalar by vector: multiplya constantby eachelementin an array divide vector by scalar: divideeach elementin an array by a constant Digital signal processing operations are somewhat more complicated than the simple array processing functions listed.

175 years later. Let x(t) denote a periodic signal with period T such that it satisfies x(t)=x(t+T) (7. disk drives.we of are able to resolve the signal into an infinite sum of cosine and sine terms according to x(t) =ao+ L[ ak cos( kx 21l'fot) +bk sin (kx21l'fot) k=l 00 ] (7. The Fourier transform is largely applied to the analysis of aperiodic signals. Mixed-signal test engineering is primarily concernedwith the discrete form of the Fourier series and. 7.Jx(t) sin k-t 21l' dt 2T ( ) T To The frequency of each cosine and sine term is an integer multiple of the fundamental frequency!o= lIT: referredto as a harmonic. . The coefficients ak and bk represents the amplitudes of the cosine and sine terms. They are commonly referred to as the spectral or Fourier coefficients and are determined from the following integral equations: ao =- 1T Jx(t) dt To ) dt (7.3) To T ak =~Jx(t)COS ( k~t bk =. respectively.1) for all valuesof -00 <t< 00. specifically. quantityk!o representsthe kth the harmonic of the fundamental frequency. At the time of his death in 1830.192 An Introductionto Mixed-Signal Testand Measurement IC domain and back again without losing any information about the signal in either domain. the importance of Fourier's work in today's networked world is astounding. Jean Baptiste Joseph Fourier was a clever French mathematician who developed Fourier analysis for the study of heat transfer in solid bodies.2. His technique was published in 1822. coherent sample sets. For instance.and mixed-signal testing to name just a few. we shall limit our discussion mainly to the Fourier series. This powerful capability is at the heart of mixed-signal testing. Using a trigonometricFourierseriesexpansion this signal.radar systems.3 The Trigonometric Fourier Series Fourier's initial work showed how a mathematical series of sine and cosine terms could be used to analyze heat conduction problems. Applications of his method extend to cellular telephones. This became known as the trigonometric Fourier series and was probably the first systematic application of a trigonometric series to a problem.2) The first term in the series ao representsthe DC or average component of x(t). Therefore. he had extended his methods to include the Fourier integral leading to the concept of a Fourier transfonn. speech recognition systems.

.b..5) 1r+tan-I(~) This result follows from the trigonometric identity: cos( A + B) ifak<O = cos( A)cos( B)-sin( A)sin(B)..5><10-4Odt+ 10 0 f 10-4 f Sdt ) =~ 1 10 S (10-4-0. with their heights proportional to the amplitudes of the corresponding frequency components. 10-kHz clock signal shown in Figure 7. 2/0. Specifically. a phase spectrom can be drawn in the exact samemanner except that the heights of the vertical lines are proportional the phases of the corresponding to frequency components. where Ck Chapter7 . We prefer this representation as it lends itself more directly to graphical form. and so on. Figure 7.and tPk =! tan-I (~ ) ak if ak ~ 0 (7. vertical lines can be drawn at discrete frequency points corresponding to 0.1. t Solution: The spectral coefficients are determined according to Eq.1 and plot the corresponding magnitude and phase spectrum.SXIO-4)=2.. Likewise.3) as follows ao=~ 1 [ 0. 10-kHz clock signal. Ckversus /ifo. The following I/JTc exampleillustrates these two plots for a 5-V.. that is. DSP-Based Testing 193 A more compact form of the trigonometric Fourier series is 00 x(t)=}::ckcos(kX2Jr/ot-tPk) k=O (7. 10-kHz clocksignal. 3/0.5xI0-4 ~ .4) =~~2-.S 0. (7. Example 7. x(t) 5V OV ../0.1 Determine the Fourier series representationof the 5-V. Such a plot conveys the magnitude spectrom of x(t).

Magnitude phase and spectrum of 10-kHz plots clock signal. Therefore. 0 k even bk=.5xI0-4 = -~ k7r =- ) 1 5 k7r [ 5 =[cos(k1r)-cos(k k1r 0. k odd k1l' or.194 ak An Introductionto Mixed-SignalIC Testand Measurement =-=4'" [ O. the tenn [(-l)k -1 ]=0.2. ~kodd kJr The Fourier series representationthen becomes x(t)=2.S + L k=l.becomes x(t)=2. Figure7. . whenwritten in the fonn ofEq. hencethe clock signal consistsof only odd hannonics. (7.5xI0-4 10-4 21r)] (-1) k -1 .5xI0-4 =0 10-4 ~ bk = 2 [ OoSX1O-4 0 sin(k 104 2Jr t)dt+ f o COS( 10-4 27r t k 10 f 5 sin(k 104 21Z't)dt O.5xI0-4 f sin ( k 10-4 2JZ"t ) 1 0.SX1O-40 cos(k 104 27r t)dt+ J 2 10-" 10 =2kJZ" o 10-4 0.5 - L 00 00 10 -sin(k 21l'104t) k=l.2. For even values of k. k oddkH 10 -COS ( k 2H 104 t+- H 2 ) ascos(x+H/2) = -sin(x) and cos(x-H/2) =sin(x). The corresponding magnitude phase and spectrum plots arethenasshownin Figure7.4).

p 4 5 3 p 4 5 3 x 0 2 1 : . Observing the Fourierseriesrepresentation a clocksignalfor 10 and 50 terms. we can rewrite Eq.11- Chapter7 .2. . 10 Terms 6.7) In this fonn we see that the frequency of the fundamental is a fraction 10/ Fs of 2Jz:Further. -10 0'5 time. . 50 Terms . 7.the Fourier series representation more closely resembles the clock signal.6) as I x(t)lt=nTs =ao+~{akcos[k(¥)n]+bksin[k(¥)n]} (7. this tenn no longer has units of radians per second but rather just radians. (7.3 superimposed on one period of the clock signal.. (sec) 1 .4 The Discrete-Time Fourier Series As mentioned previously. . DSP-Based Testing 195 It is instructive to view the behavior of the Fourier seriesrepresentationfor the clock signal of the previous example consisting of 10 and 50 tenns. (sec) X 10 1 -4 -10 .6) As Fs=lITs. Superimposed of ontheplot is the originalclocksignal. Some large amplitude oscillatory behavior occurs at the jump discontinuity.[ akcos(k 2tr/o nTs)+bksin(k k=\ 2tr/o nTs)] (7. consider sampling the general fonn of the Fourier series representation given in Eq. as the number of tenns in the series is increased.2). . To understand the effects of sampling on an arbitrary periodic signal. Assuming that the sampling period is Ts. it is commonly referred to as a normalized frequency. This is known as Gibb's phenomenon and is a result of truncating tenns in the Fourier series representation. This we show in Figure 7. ~ x 0 2 I'" 1 . 0'5 time.3. (7. Clearly. sampling is an important step in mixed-signal testing. we can write ~ : x(t)lt=nT s =ao+ I. To distinguish this from our regular notion of frequency. 6. 10 -4 x Figure 7. . as it has .

by . equivalently. x(t) =~ sin7rt +. X(t)=.196 An Introductionto Mixed-Signal Testand Measurement IC Exercises 7. we are concerned with coherent sampling sets.Sin57rt+.!. ADS.3.sin37rt+. the information about the time scale is lost. the original samplescannot be reconstructed without knowledge of the original sampling frequency. x[n]. Therefore..7) can then be reduced to x[n]=ao+ ~{akcos[ k(~)n }+bksin[ k(~)n]} where frequency thefundamental the of reduces 1/N .9) .8) and eliminates the time reference altogether.1 using cosine terms only. fa =I/UTP=F f =Fs/N.I (7.[ cos( 7rt-f)+~cos( 37rt-f)+~cos( 7. 7r ( 3 5 ) 57rt-f)+. Express the Fourier series in Exercise 7. The discrete-time signal x[n] is simply a sequence of numbers with no reference to the underlying time scale."] 7. Find the trigonometric Fourier seriesrepresentation of a square-wavex(t) having a period of 2 s and whose behavior is describedby: x(t) = { +I -I ifO<t<1 ifl<t<2 ADS.2 cos-t--cos-t+-cos-t-+. UTP= NTs. For much of the work in this textbook. albeit to normalized Fs. that is.!.1. Except for the time reference Ts on the left-hand side of the equation... or. Equation (7.. 2 7r ADS. Find the Fourier series representation of a square-wave x(t) having a period of 4 s and whose behavior is described by: x(t) = { I if -I < t < I 0 ifl<t<3 I 7r I 37r I 57r =--. Hence.2. a sampling period or frequency must always be associatedwith a discrete-time signal. This is further complicated by the fact that one usually usesthe shorthandnotation x[n]=x(t)lt=nT s (7. x(t) ( 2 3 2 5 2 ) been normalized by the sampling frequency F s.

11) can be written in a more compact form using magnitude and phase notation as N/2 x[n]=~CkcOS[ k (N ) 21r tan-l n-f/Jk ] - (7. as is often the case in testing applications) x[n]=ao+N~1 {akcos[ k(~)n ]+bkSin[ k(~)n ]}+aN/2cos(1rn) re ao (7. (7.10) i As the roles of nand k are interchangeable in the arguments of the sine and cosine terms of Eq. (7.9) as the sum of N/2 trigonometric terms as follows (here it is assumed N is even.11) = L ~mN ~ ak = L (ak+mN+ aN-k+mN) ~ aN/2 = L ~ aN/2+mN m=O m=O m=O (7. x[n] will be periodic with respect to the sample index n. (7.12) will converge to fmite values.11111111111111111111111. it suggests that x[ n] will also repeat with index k over the period N. according to .13) re ck=Vak-+bk- - 1- 2 :- 2 and f/Jk= - [ ( ~ ak - ) if ~k ~ 0 1r+tan-l(~) if~k <0 (7.14) Equation (7.13) can then be graphically displayed using a magnitude and phase spectrum plot. the sums in Eq. (7. m=O Here ak represents the amplitude of the Likewise.12) represent the sum of all aliases terms that arise during the sampling process. x(t) DSP-Based Testing 197 As the original continuous-time signal is periodic and sampled coherently. The equations of Eq. bk is the amplitude of the sine component located at the kth Fourier spectral bin. As before. . Chapter 7 . (7. we can rewrite the infinite series given by Eq. Of course. Through a detailed trigonometric development outlined in the appendix at the end of this chapter. aorepresents the DC or average value of the sample set.12) bk = L (bk+mN -bN-k+mN) ~ cosine component located at the kth Fourier spectral bin. x[n]=x[n+N] (7.9). Eq. Since we are assuming that the original continuous-time signal is frequency band-limited.

Using the equations for the spectral coefficients in (7. the discrete-time Fourier series representation for the clock signal then x[n]=2. ~ =0. ~ =-0. Eo =0 and bs=0) are found even asfollows bk = f { (bk+lOm -qO-k+lOm) = -~ m=O ( I Jr m=O (k+IOm) f Ok - I (IO-k+IOm) ) k odd Here the summation involves the difference between two harmonic progressions where no closed-form summation formulas are known to exist.2.72528 sin [3(*)n] . together with the Fourier seriesresult of Example 7.. 4 (by definition. The result is ~=-3. at most. it suggeststhat a discrete time signal has a spectrum that consists of.11).the bk coefficients for k = I. Solution: With a 100-kHz sampling rate. a numerical routine was written that summed the first 100 terms of this series.e. we find the ak coefficients are as follows ao =L 00 00 aO+lOm ao = = 2. .as it relates the spectrum of a sampled signal to the original continuous-time signal. Further. these frequencies are all harmonically related to the primitive or fundamental frequency of 1/N radians. N/2 unique frequencies.5-3.2 Calculate the DTFS representationof the 10-kHz clock signal of Example 7. Moreover... Example 7. 10 points per period will be collected in one period of the 10-kHz clock signal (i. becomes b4=0 According to Eq. (7.198 An Introductionto Mixed-SignalIC Testand Measurement The importance of the above expressionscannot be understated.. 2.12).1. N=IO).1 when sampled at a lOG-kHz sampling rate.07516 sin[ l(*)n ]-0. Subsequently. This representation is known as a discrete-time Fourier series (DTFS) representation of x[n] written in trigonometric form It will form the basis for all the computer analysis in this text.5 ke {1.72528.3.07516.4} m=O ak= as = L (ak+lOm +alG-k+lOm) =0 L as+lOm=0 00 m=O m=O Subsequently.

the midpoint of each jump discontinuity is (5 . using magnitude and phasenotation.5.4. the sample value at a jump discontinuity is ambiguous and undefined. . .4 is a graph of the DTFS representation as a continuous function of sample index. . I When analyzing a waveform collected from a DUT we want to know the spectral coefficients ak and bk or ck and ~k so that we can see how much signal power is present at each frequency and deducethe DUT's overall performance. .0)/2 = 2. ~ 10 -10 ~ I ~ ~ samp e. . It is interesting to note that the samples are the intersection of this continuous-time function with the original clock signal.Evaluatingx[n) for one complete period (i. . .e. Also shown in the plot of Figure 7. As expected. . Thus far. .Chapter7 . .5+3. . . 0. Comparing samples a DTFSrepresentation the originalclocksignal.9983. as shown in Figure 7. .075l6 cos[ 1(-*)n+f]+0. 0. 4.'. 1. . . .9973}. . 4. 4. n.9973.. 6 . . . .0017. . Also shownis the of and the DTFSas a continuous functionof n. . . . . . . . . ..72528 cos[ 3(-*)n+f] It is important for the reader to verify the samples produced by the above discrete-time Fourier series. The small difference can be contributed to the error that results from including only 100 terms in the summation of the bk coefficients. 4.9}).0017. .0027. . . .5. c x 1 . 0.9983. n={O. . . n Figure 7. .4. . . . Of particular interest is the value that the discrete-time Fourier series assignsto the waveform at the jump discontinuity. . . . .. DSP~Based Testing 199 or. .0027. . . 0. In this particular case. In general. we write x[n]=2.2. . . . . all the samples correspondquite closely with samplesfrom the original signal. . 2.5. we obtainx={2. . Fourier analysis resolves this problem by assigning the sample value of the discontinuity as the midway point of the jump. we have only considered how to compute . . . .

In fact.. let us consider that we have N samples. consists of only N trigonometric terms and. In practice.11).wewrite for x[2]= tio+N~I {iik cos[2k(~ )]+bk sin[2k(~ )]}+iiN/2 cos(21r) =iio+iiICOS[ 2(~)]+~sin[ 2(~)]+ii2COS[ 4(~)]+~sin[ 4(~)J+'. The discrete-time Fourier series. {ilk coS[O]+bk sin [O]} + iiN/2 cos[O] k=1 = ao +iil +. [( N )] 21r +VJsm k . on the other hand. hence.15) Next.200 An Introductionto Mixed-Signal Testand Measurement IC the spectral coefficients from a Fourier series expansion of a continuous-time waveform.11) at sampling instant n=O N~-I x[O] =iio + 2. we write x[l] = iio -+N~l =ao+alcos ~ - {iik cos[ k( ~) ]+bk sin [ k( ~) ]}+iiN/2 cos[lr] +v:zsm r. As we shall see. (7.. 1.~ ...' +iiN/2-1 2( ~-1 )(~ )]+bN/2-1 [ 2( ~-1 )(~ )]+iiN/2 cos(2lr) cos[ sin (7. there is no error in its representation. the summation must be limited to a finite number of terms. To begin. Therefore.N-l.17) Continuing for all remaining sampling instants.. Consider that each one of these samples must satisfy the discrete-time Fourier series expansion of Eq.2. we can write the Nth equation as . n=2.. up to n=N-l. This is rather unlike the Fourier series expansion for a continuous-time signal that consists of an infinite number of trigonometric terms. [( N )] 21r +a2cos - [ 2 N )] 2lr ( [2( N )] +. . resulting in an approximation error.. there is a more direct way to compute the spectral coefficients of a discrete-time Fourier series from N samples of the continuous-time waveform. we shall outline two methods: one that highlights the nature of the problem in algebraic terms and the other involving a closed-form expression for the coefficients in terms of the sampled values. at n=l.denoted x[n] for n=O. (7. 2lr (7..16) +iiN/2-1 cos[(~-1 )(~)]+bN/2-1 sin[( ~-1 )(~)]+iiN/2 cos[lr] Similarly.+iiN/2-1 +iiN/2 (7. we can write directly from Eq.

In essence. .. the spectral coefficients foundasfollows are C=W-IX The next example will illustrate this method on the clock signal samplesfrom Example 7. co{(~p{~)] coS[(~)(2)(~)] ..we have a system of N linear equations in N unknowns. sin[(T-Ip)(~)] . Straightforward linear algebra can then be used to compute the spectral coefficients.... we find that all the trigonometric tenus have numerical values and the only unknown tenus are the spectral coefficients. . COS[(I)(2)(~)] Sin[(I)(2{~)] ....19) Multiplying both sidesby W-I.. Sin[(T-IP)(~)] . . .18 . . . Sin[( )(N-I{~)] T-I cos[( f)N-I{~)] X=WC (7. if we define vectors [ ( )] [( ) ( )] (7.. Sin[(T-I)(O{~)] .2. aN-I] and X=[ x[O] x[l] x[2] . For instant. x[N-l]] ther with matrix I I ~ cos[(~)(O)(~)] COS[(I)(O)(~)] COS[(I)(I{~)] sin[(I)(o{~)] sin[(I)(I)(~)] . ...1111111111111111111111111111. I co{ (I)(N-I{~)] an write Sin[ (I)(N-I{~)] . w= I . 1 C=[ao al ~ a2 ~ ... DSP-Based Testing 201 x[N -1]=ao +N~I {akcos[ (N -1)k(~ )]+bk sin (N-1)k(~ )]}+aN/2cos[(N [ -1)1Z"] =ao cos[ -1)(~)]+~ sin(N-1)(~)]+a2cos[2(N-1)(~)] +al (N [ +~sin 2(N-l) N +. (7.20) . Chapter 7 . on observing the behavior of each one of these equations...+aN/2-lcOS 2-1 (N-l) N 2Jr N 21Z" +bN/2-1 T-1 )(N -1)(~)]+aN/2 cos[(N sin[( -1)1Z"] Finally. ..

809 -0.951 -1 0.309 -0.309 0.000 0.588 1 0.309 -0.588 -0.5.309 0.000 0.0.309 -0.0.951 0.809 0 0.588 0. are 5.951 0.309 0.588 0.809 0. The latter set of magnitude and phase coefficients was derived using (7. 0. ~ .309 -0. 5.588 0.5.588 0.809 -0. 2.951 -0.588 -0.14).000 -1 -0.309 -0.588 0.951 -0.309 0. Compute spectral the coefficients theDTFSusinglinearalgebra.951 0.500 0 3.5 .2 that the clock signalsamples x={2.951 1 -0.588 1 ~ a3 ~ a4 b4 5 5 5 1 -0.0.0.809 -0.951 -0.000 -1.588 -0.0.0.5.309 0.809 -0.309 0.202 An Introductionto Mixed-Signal TestandMeasurement IC Example 7.588 1 -1 ao al 0 1 0.951 -0.951 1 -0.951 -0.951 -0.951 1 -0. of Solution: Using the procedure described.809 0.3 Considerfrom Example7. 0.588 1 0.078 0 ~ Co <A> - 2.5.588 -1 as Usingthematrix routinesavailable MATLAB.0.809 -0.951 -1 0.809 2. we seethat they agreereasonably well (the small difference is attributed to the seriestruncation as explained in the last example). 0.1 -1.078 If/ -~2 C I ~ C2 0 ~= 0 123 0 ~ -0.809 1 0.309 0 0.000 0.951 1 ~ a2 0 1 -0.000 5 1 -0.588 0.809 0.809 -0.588 0.0}.5 0 1 1 1 0.309 -0.309 -0.309 0 1 -0. 7265 a4 - ~= 0 C3 0.500 0 -3.809 0.951 -0. obtainthe following spectral in we coefficients: ao an 121 ~ 122 2.809 -0. 0.809 0 0.309 0 0.809 1 0. canwrite the following systemof linear equations matrix we in form: 2.2.000 1.588 0.000 1.7265 ~ -~ c4 <"4 b as 4 - 0 0 0 Cs if>s 0 0 0 0 On comparison with the results in Example 7.

. Specifically. ~sin[ p(~)n ]cos[ k(~)n ]=0 forallp Anned with these identities..2.Chapter7 . Another method exists for finding the spectral coefficients and one that is much more insightful as it provides a closed-form solution for each spectral coefficient.. This is achieved by writing the discrete-time Fourier seriesas . To arrive at this solution. we need to consider the orthogonal property of cosines and sines. a single expression for ak is usually written as was done for bk. forp=k=O forp*k forp=k*O [ 2tr N N-I. forp=k*O N. In many textbooks..11) with sin [ k (~) k n ] and sum n from 0 to N-l on both sides to obtain hk - =N 2 N-l ~ x[n]sin [ ( N 27r ) n ] k=1. for p * k ~cos p(~)n n=O cos k(~)n = N/2. DSP-Based Testing The preceding example highlights the fact that the spectral coefficients of the discrete-time Fourier series are determined by straightforward linear algebraic methods.N/2- . N/2. smp-nsmk-n= ~ ( )] . consider the following set of orthogonal basis functions N I [ ] [ ] { O. (7. we multiply Eq.11) WithCOS[ ~)n k( N-l on both sides to obtain' and sum n from 0 to Likewise. [ ( )] 2tr N { O. (7. we multiply Eq.

Not surprising. Likewise. 2. 5. 0. (7. we can computefrom Eq.0.0.3. =~{255in[(3)(*JO) ]+55in[ (2)(*)(6)~ ]+55in[ (2)(*)(9) ]}=O ]+55in[(3)(*)(6)] ]+255in[(3)(*)(5) +55in[(3)(*)(7) ]+55in[(3)(*)(8) ]+55in[ (3)(*)(9) ]}=-{} 7 and b4 =0 and bs=O.0. a4 = 0. 5. 0.7. 5. (7. 0. 0.204 An Introductionto Mixed-Signal Testand Measurement IC The details are left as an exercise for the reader in Problem 7.5 +0+0+0+0+ 2. Solution: With x={2.5.0}.0.23) Ii =~{255in[(1)(*)(0) ]+255in[ (1)(*J5) ]+55in[(1)(*J6)- +55in[(1)(*J7) ]+55in[ (1)(*)(8) ]+55in[(1)(*)(9) ]}=-307 b.5 10 a} "=0 Continuing.5.0. =~{255in[ (2)(*)(0) ]+255in[(2)(*)(5) +55in[(2)(*)(7) ]+55in[(2)(*)(8) b. Example 7. and as = o. 5.5 +5 + 5 + 5+ 5] = 2.0. from Eq.22) the following coefficients iio = 2-[2. a3 = 0.4 RepeatExample7. .0. the results are identical to those found in Example 7. we find a2 = 0.3 but computethe spectralcoefficientsof the DTFS using the orthogonal basismethod.

-0. 1 N-I ] Nn=o ak= 2 N-I () N 27r k=N/2. detennine the DTFS representation for these samples.7071 sin[(~)n] 7..333 cos[(¥)n-1r ]+0.6.N/2.7071}.. Also.N-l .x[n]cos [ k -21r n.2. 1. (7.5.22) over the rangek To begin.333 cos[(¥)n Ans.. Using the summation fonnulae in Eq.. expressthe result in magnitude and phasefonD.. (7. 0.0 cos[(~)n-~] ]+0. On doing so.2. A sampled signal consists of the following 4 samples: {0.3.. 1.16). 1.1667 cos[3(¥)n-I] \ 7. DSP-Based Testing 205 Exercises 7.7071. A sampled signal consists of the following set of samples {O.2301 cos[(*)n-I]+0..2. 1.5 CompleteFrequencySpectrum One of the most important insights that can be obtained from the closed-fonD expression for the spectral coefficientsis how they behavebeyondthe rangek=0. expressthe result in magnitude and phase fonD.1.2901 cos[ 3(*)n-I] 7. Also. detennine the DTFS representation of the Fourier series representation ofx(t) given in Exercise 7.. consider =N /2.Chapter7 . expressthe result in magnitude and phasefonD.24) N ~x[n]cos[ k(N)n]. we write ! -L. evaluatingEq..7071. Use 10 points per period and limit the seriesto 100 tenDs.2901 sin[ 3(*)n] Ans. I}.. N.. k=N/2+1..5+1.5-1. -0. Using linear algebra.2301 sin [(*)n ]+0.4.7071. Also. 1.N (7.7071cos[(~)n Ans. 0. 1. Detennine the DTFS representation for this sample set using the orthogonal basis method.1667 sin[ 3(¥)n] ]+0.

1.26) allowsus to concludeover the rangeof that to k=I. Next...N-I that aN-k= ak k (Bin) a 1 2 . (7.. (7. . 21Z' = 1. N-2N-1 Figure7.N/2 k=l...24)canbe re-writtenas 1 N-l -Lx[n]cos [ (N-k) .N/2 k [ (N-k) ( ..) n] ..N/2-1 Recognizing Eq..N/2-1 However.k. . (7... if we considerthe changeof variable substitution..25) as k=O.N-1: magnitude (a) spectrum and (b)phase spectrum.. k ~ N ..... Illustrating spectral the symmetry aboutN/2 for k=O. 2Jr () N N aN-k = Nn=O 2 N-l -Lx[n]cos Nn=o k=O. (7..206 An Introductionto Mixed-SignalIC Testand Measurement Here.. only the cosinetenDsare affectedby the index k. allowing us to write Eq. %-1%%+1 (b) .25) is equivalent Eq.n] .5. Eq.. Nh-1NhNh+1 N-2N-l . cos[(N -k)(21r/N)n ] = cos[k(21r/N)n J. (a) : !/ I N/2 Mirror If>k Jr : I I ! I I \' k (Bin) I 1 t -Jr I - : 0 1 2 ..

Chapter7 . (7.0777 .2.2 is shownin Figure7. we find using Eq. (7.24)-(7.07265 I + I ! 1 :r 9 k (Bin) 2 3 4 5 (a) 6 7 8 .6(b).togetherwith the trigonometric as identitysin[( N -k)(2Jr/ N)n ] = -sin[k(2Jr/N)n J. Similarly.k.5 for an arbitrarydiscrete-time are periodicsignal. onecanwrite bN-k= -bk Converting this result into magnitude and phase form.28) . the phasespectrumexhibits an odd symmetryabout N/2.07265 I + I I 0.3 over 10 frequency and for bins.27).0777 3.6(a)and the for corresponding phase spectrum appears Figure7.5 ro 0 0 4>k 0.for all k ~N-k=-t/Jk Here we see that the magnitudespectrumexcluding the DC bin has even symmetryabout binN/2.14) (7.-"6 CN-k. DSP-Based Testing 207 Followingthe samereasoning abovein Eqs. Thesetwo situations highlightedin Figure7. Plot the magnitude phasespectrum the clock signalof Example7. in Ck 3. Themagnitude spectrum the clock signalof Example7.

30) simplifies directly to ak+N= \NN-l 1 ~x[n]cos [ k( ) ] N n..1451 3(T)n ]+0.30) k=1.6150 0. 21& k=0. (7.N/2 (7.. Hence... ~ [ 21& ] k=0. Due to the periodicity of the cosine function. Plot the magnitude phasespectrum the DTFS representation a sampled and of of signal described by x[n]=0. (7.1451 k TC/2 k -TC/2 01234567 . NI k=1.. Eq.. write we Ilk+N Ilk for all k = (7.N/2-1 21& x[n]cos[(k+N)( N)n].2749 sin[2(T)n] +0..6150 0.22) by k+N so that we write ak+N = 1 1 N-l N N 2 N-l ~x[n]cos(k+N)(N )n. let us consider the periodicity of the spectrum. ck 0.2749 If>k 0.0649cos[4(T)n] sin[ ADS.1451 0. Consider replacing k in Eq.7.32) Exercises 7.N/2 (7.N/2-1 which is equalto Ilk.31) i ~x[n]cos[k(~)n]..6150sin[(T)n]-0.208 An Introductionto Mixed-SignalIC Testand Measurement Next.2749 0.

14).. 1 ~ .7. Illustrating spectralperiodicity: magnitude the (a) spectrum (b) phasespectrum. Therefore. 1 I I I I . :3N (b) Figure7. one can write bk+N = bk for all k Through the direct application ofEq.1. N (a) 2N 3N in) ~ r 1 I 1 I I I N ~ 1 . 1 1 I 1 I I I I I I .7 illustrates the full frequency spectrum of an arbitrary signal.. we should point out that most test vendors only provide spectral information corresponding to the Nyquist interval. DSP-Based Testing 209 Following a similar line of reasoning. k=0. 0 I .. twenty years ago when DSP-based ATE started to appear on the market memory was expensive. and ....33) for all k (7.Chapter7 . Ck r 1 1 1 I I ..Figure 7. I I I I 1 . 1 1 I I I I I I I 1 1 I I 1 .adjacentperiods of the spectrum are indicated with dashedboxes.. N ~ 1 1 I I I I 1 1 1 1 I I I I r .34) =I/Ik We can therefore conclude from above that the spectrum of a periodic signal x[ n] with period N is also periodic with period N. At this point in our discussion. .N/2.. the frequency spectrum of a discrete-time periodic signal is defmed for all frequencies. we can write _k+N. I I I 1 1 1 I 1 : 1 k (Bin) 1 I I I . combining spectral symmetry. I ._k C -c I/Ik+N (7. To aid the reader. 1 0 0 . This led to the elimination of redundant spectral information. Attempts to minimize memory usage were paramount.. Although less important today. together with its periodicity. (7. :O:N : .

resulting in a frequency denormalization scale factor of 1 kHz. (7.35 ~ / N. respectively.07265 k (Bin) 3.0777 2.8. To achieve this.0777 X-t=XIO. n by Ts. To obtain the actual time and frequency scales associatedwith the original samples. according to the translation n . the of a . nT s Conversely. Fs=lO kHz and N=lO.5 0.OOO 3. k-t (7. according to the sample indexes.2.07265 j(kHz) 60 70 80 90 Figure7. one simply multiplies the sample index. To reconstruct the original time scale. Ck 3.-.0777 0.5 0.36 Figure 7.0777 U Ck 2.8 illustrates the frequency denormalization procedure for the magnitude of the spectrum for the clock signal described in Example 7. one must perform the operation of time and frequency denormalization.6 Time and Frequency Denormalization The time and frequency scale associated with a data sequencex[ n] is described in terms of normalized time and frequency. knowledge of the sampling period Tsor sampling frequency Fs is required. For this particular case. the frequency scale is restored when one multiplies the sample index k by according to the translation F k. nand k.07265 0 0 1 2 3 4 5 6 7 8 9 0. Illustrating procedure denormalizing frequencyaxis.210 An Introduction to Mixed-Signal Testand Measurement IC 7.5.07265 0 0 10 20 30 40 50 3.-.

we get 2. Plot the frequency-denormalized magnitude spectrum of the following representationof a sampled signal describedby: DTFS x[n] = assuming sampling as rateof 16kHz. The main reason for this choice lies with the easein which the exponential function can be algebraically manipulated when compared with trigonometric formulas.38) Whenthepreceding formulaearesubstituted Eq.6150 0.11) into complex form. considerthat the cosine and sine functions can be written as cos( rp) = ejlp +e-jlp 2 . Ii x[n]=ao+ ejlp =cos(rp)+ jsin(rp) (7.(7 two into . sin( rp)= ~Ip -e-jlp 2j (7.1111_Exercises Chapter7 . DSP-Based Testing 211 7.11). Ans.2749 j(kHz) 0 2 4 6 8 10 12 14 7. ck 0. keN N~-l ( ak .7 Complex Form of the DTFS In most DSP textbooks. To convert the DTFS representation in Eq. the DTFS is expressed in complex form using Euler's equation ~ .2749 0. ( )n + N/2-1 ( a + "b ) k k=1 } keN -jk (~ )n (7.39) 2 +( ~) +( ~) e-j1En .2. (7.37) wherej is a complex number equal to H.6150 0.} 'b ) jk ~ k=l 2 ej1En L.8..

N X(k) = .b keN k=\ jk (3. we write 'b x[n]=ao+2..44) k=N12 k=NI2+1.40) Next. in general. the coefficients X(k) in front of each exponential tenn are. (7.N-l aN-k+ jbN-k 2 As is evident.. the imaginary part of each tenn is related to one-half the sine coefficients.NJ:!. we can write ~(!iJ£~ ) k=\ 2 e-jk(~)n = ~l ( aN-k k=N/2 + jbN-k ) ejk(~)n (7.2 aN/2 1 2-1 (7.41) 2 Substituting Eq.J. a . ( a + J'bkeN k k=\ 2 NJ:!.jbk k=O k =1.. The fact that the scale factor is not evenly distributed among each tenn can be a source of confusion for some. complex numbers..2. . ) -jk (3.. the real component of each tenn relates to one-half the cosine coefficient of the trigonometric series.!) n + N-l L. through the change of variable k ~ N -k in the rightmost summation tenn. The exceptions are the X(O) and X( N 12) tenns. For the most part. ( a - N k 2 k=N/2 + jb N ..40) leads to x[n]=ao+ NJ:!.. ) ( k 2. Conversely. ( k J keN k=\ 2 - a- ) jk (3.212 An Introductionto Mixed-Signal Testand Measurement IC Collecting the end tenns inside each sum.42) The DTFS can then be written in complex fonD as x[n]= N \ X(k) f k=\ where eJ'k N ( 211" ) /I (7.43) ao ak .!) n +2.!) n (7..41) into (7.keN 2 ) jk (3.!)n (7.... These two terms are directly related to the cosine tenns with a scale factor of one.

3 DisCRETE-TIME TRANSFORMS 7.1 CN/2el° . (7.44)canalsobe written.l)eJ3(*)n +0.9. Suchsignalsare known as discrete-time a of of aperiodic signals.14). Exercises 7. A DTFS representationfor a sequenceof data is given by x[n]=0.. we can construct a periodic sequencex[n] for which y[n] is one .25)eJ(*} +(0.45) :.l)ej7(1f)n +(0.t..25+1. Next.-jik - !2-1 (7. x[n] Ans.1.2 cos[ 5(*)n] Express in complexfonn. (7.' ..jO.11-- Chapter7 ...25+(0. canrewrite Eq.N-I 2cN-ke - .3.'0 Coel I k=O k-I.. together with substitutions from Eq.5.2COS[ 3(*)n ]-0.0 cos[(*)n ]+0. we shall I i . In this section. x[n] =0.1 + jo. 7. Consider an arbitrary sequence y[n] that is of finite duration over the time interval n=O to N-I. DSP-Based Testing 213 Alternativefonns of Eq. A signal of this type is shown in Figure 7.N! 2+1.25)eJ'1f)n -.2ejs(*)n+(0. consider thaty[n]=O outside of this range. demonstrate a similar setof harmonicallyrelatedexponential that functionscan alsobe usedto represent sequence N samples finite duration. From this aperiodic signal.. For instance.5 sin[(*)n] +0.2 Sin[ 3(*)n ]+0. or in tenns of N hannonically-related complex exponential functions.2.N X(k) = -cke 2 .5+ jo.9(a).44)in we polarfonn.as . I ..k=N!2 1+jl/lk k .jo.1 The Discrete Fourier Transform In the previous section it was shown how a sequenceof N samples repeated indefinitely can be represented exactly with a set of NI2 harmonically related sinusoidal pairs and a DC component. . (7.

The following vector describesthe spectralcoefficientsof a DTFS expressed in complexrectangular form X=[l 0.0 cos[ 3(T}n ]+2. +(1..3 c~s[4(-T}n] period.214 An Introduction to Mixed-Signal Testand Measurement IC Exercises 7.O7801r ]+0. _ (2") }3 (2")- }12" ) .0 sin 3(T}n] [ 7. A DTFS representation expressedin complex form is given by x[n] =2+(1+ jl)eJ s.(2" Expressx[ n] in trigonometric form..N-1 0 h . we can write y[n] as { N_I y[n]= ~X(k)e 0 j{~)n n-0. ) s..9(b).This is knownastheperiodic extension ofy[n]. The spectral makeup of the discrete-time signal no longer consists of harmonically related discrete frequencies.1. and as N ~ 00.. Under such . ADS.47) As we choosethe period N to be larger.3 0 4+fl 0. However. we note that as N ~ 00. x[n]~1+0.{x[n] n=0.0 sin[(T}n ]+2.we candescribe n] as y[ y [n] . the form of the mathematics in Eq..11. (7.fl)e sf' +(1+ fl)e 1.. ADS. x[n]=2+2.25-jO.l.. for very largeN. y[ n] matchesx[ n] over a longer interval.25+jO.46) Ifwe consider the complex form of the DTFS representationfor x[n].47) changes.25 4-fl 0 0.asillustratedin Figure7.. but rather becomes a continuous function of frequency.. In mathematical terms. Thus. the spectrum y[ n] is of identical to x[ n].fl)eJ'ls. +(1.N-1 otherwise (7. y [ n] = x [ n] for any finite value of n.0 cos[(T}n ]-2.10.7071 cos[(T}n+f ]+802462 COS[ 2(¥}n+0. ot erwlse (7..25] Write the DTFSin trigonometric form usinga magnitude phase and notation.

representation Eq. This implies that we really have no other choice but to work directly with Eq.49) As in all computer applications.9. to small values of N. (7. DSP-Based Testing 21S y[n] n 0 0 N-l (a) 2N x[n] 1-4 N~ n 0 0 N (b) 2N Figure 7. (7.47) are directly related to samples of Y (ejiiJ )uniformly X(k) = ~ ejiiJ spacedaccording to (N ) ~k N (7.47) in the limit becomes the in known as a Fourier transform andis writtenwith an integraloperation follows as 11" y[n]=~ where JY(diiJ) ejiiJlldm -11" (7. conditions. (a) Arbitrary signal of finite duration.Chapter7 . we must limit our discussion to finite values of N.47). It has been shown that the spectral coefficients X(k) associatedwith Eq. (b) periodic extension of infinite duration. of which mixed-signal testing is just one example. (7.50) . and preferably (as test time is always a major concern).48) Y(ejiiJ)= f y[n] n=-oo e-jiiJII (7.

before we move on to this topic. As test time is always paramount in mixed-signal test.I.. Under such conditions it is impossible to represent this signal exactly with a periodic signal having a finite period. we shall first consider an important degeneratecaseof the DFT.216 An Introductionto Mixed-Signal Testand Measurement IC (7. J. . a programmer at IBM.49) into (7. Tukey invented a new algorithm for performing the DFT computations in a much more efficient manner. translated Tukey's algorithm . IO(a). Windowing is a mathematical process that alters the shape of the signal over the observation interval and gradually forces it to decay to zero at both ends.2. W. The most common method is to extend the observation interval to large values of N so that the combined energy of the aliased components is made insignificant relative to the energy in the signal. Consider the situation where an aperiodic signal has infinite duration or exists with nonzero values over a much longer time than the observation interval of N samples. The spectral coefficients determined by the DFT would then correspond to samples of the Fourier transform of the signal shown in Figure 7. the spectral coefficients of a DTFS.3.N-I... and limiting the summation to the maximum possible nonzero values ofy[n].. We shall delay the introduction of our examples until we first describe the principles of the fast Fourier transform. for that matter. as explained in the next section. The net result is a concentration of the aliasing energy or frequency leakage into a few spectral bins instead of having it spreadacross many different bins.10(c). In practice it is important to keep the jump discontinuity to a minimum if the DFT is to reveal the spectral properties of the original waveform. As the DFT is essentially a special interpretation of a DTFS. one should avoid discontinuities in the periodically extended waveform. not Figure 7.51) : 'i Substituting Eq.5 can also be used to produce the spectral coefficients of the DFT. a more efficient algorithm is available to compute the DFT of a discrete-time aperiodic signal or.10(b) using a periodic extension of the finite duration signal shown in Figure 7. n=O..2 The Fast Fourier Transform ~ In the early 1960s J. The error is a form of time~domain aliasing and is directly related to the jump discontinuity that occurs at the wraparound point of the periodically extended waveform. we can write X(k)=-r. some reduction in the overall observation time can be achieved if the method of windowing is used. However.1O( c). Cooley.1O(a) for an exponentially decaying waveform. one can only approximate the waveform over the observation interval as shown in Figure 7. This eliminates the discontinuities in the periodically extended waveform at the expenseof decreasedfrequency resolution. X(N-I)} in Eq. In the words of Chapter 6. one should restrict all signals to be coherent rather than noncoherent. 11 . Further.X(l).. This algorithm is known as the fast Fourier transform (FFT) and represents one of the most significant developments in digital signal processing.51) is referred to as the discrete Fourier transform (DFT) of y[n]. 7. the algorithms in Section 7.50). (7. However. This is illustrated in Figure 7.. Instead. the set of coefficients {X(O). I N-) y[n] e -jk (~ )n N Nn:o Due to the importance of the interplay between the spectral coefficients of the DTFS representing the periodic extension of the aperiodic signal and its Fourier transform. (7.

. F.4 It is now known that this algorithm actually dates back at least a century.. another N multiplications and additions are necessary.10. (a) x[n] 104 N ~ n n 0 0 y[n] N (b) 2N 0 0 N-l (c) ..considerin Eq.Chapter7 . Therefore. The great German mathematicianC. (N-l)N complex multiplications and additions will be required. To understand significance the DFT algorithm. in total. (7. of of into computer code and the Cooley-Tukey fast Fourier transform (FFT) was born. to perform a DFT on 1024 samples. (a) Arbitrary signal of infinite duration. For N spectralcoefficients..(c) signalapproximation finiteduration.. so obviously we need a more efficient way to perform the multiplications in a DFT. Gauss is known to have developed the same algorithm. To minimize test time. n Figure 7.51) that N complex the of multiplications and N-l additions are required to compute each spectral coefficient X(k). This is where the FFT comesin. DSP-Based Testing 217 y[n] 0 0 N-l .(b) periodicextensionof infinite durationof short portion signal. a computer has to perform over one million multiplications. we would prefer that the DFT computation time be as small as possible. As an example.

this represents a huge reduction in computation time. although a DFT would have no problem doing so. The redundancy is removed by "folding" the redundant calculations on top of one another and performing each calculation only once. Since many redundant calculations are eliminated by the FFT. it is not possible to perform a standard Cooley-Tukey FFT on 380 samples. For a 1024-point FFT. most testers incorporate commercial DSP chips sets that compute the FFT using complex arithmetic and store the complex numbers in an array beginning with the DC bin followed by successiveharmonic bins up to the Nyquist bin. In older testers. Today. Compared to the one million complex multiplications required by the complex version of the DFT. Many ATE versions of the FFT do not produce peak voltage outputs. First. some produce voltage outputs multiplied by the number of samples over 2 (i. This suggests that the test engineer must become familiar with the FFT routine that they intend to use and determine all the necessary scale factors. One has to be careful. The butterfly network can be laid out in a decimation-infrequency configuration or a decimation-in-time configuration. the details of the FFT algorithm itself are largely unimportant to the test engineer. Although the FFT produces the same output as an equivalent DFT. Fortunately. It is quite possible that improvements in computation speeds will eventually make the FFT obsolete in mixed-signal testers. the savings in test time is so huge that test engineersusually have no choice but to use the FFT with its limited sample size flexibility. it has been the authors' preference to adjust the scale factors so that the FFT produces RMS levels instead of peak levels. 7. For reasonsthat will become clear in the next chapter. when interpreting the FFT output. many test metrics call for the combination of the power of several spectral components. the FFT that is performed in MATLAB is given by the equation . other than the difference in computation time. since the FFT operation is built into the operating system of most mixed-signal testers. though. Some produce voltage squared(power) outputs. For instance..3 Interpreting the FFT Output The output format of a mixed-signal tester's FFT depends somewhat on the vendor's operating system. etc. where n is an integer. only 1024xlO or 10240 complex multiplications are required. The difference between the FFT and DFT becomes more extreme with larger sample sets. Nevertheless. The same format is also used for most numerical software packagessuch as MATLAB. a I-V input with 1024 points produces an FFT output of 512 units). allowing DFTs instead: Until then.218 An Introductionto Mixed-SignalIC Testand Measurement The FFT works by partitioning each of the multiplications and additions in the DFT in such a way that there are many redundant calculations. since the DFT produces an exponential increase in computations as the sample size increases.s There are several different ways to split the calculations and fold the redundancies into one another. it only requires N log2(N) complex multiplications.e. In addition. The limited choice of sample sizes is the major difference between the DFT and the FFT. To better understand the steps involved. the format of the FFT output was arranged as an N-point array with the DC and Nyquist levels in the first two array elements followed by the cosine/sine pairs for each spectral bin. the more common FFTs can only operate on a sample size that is equal to 2n.3. Working with RMS values simplifies this approach. the mixed-signal test engineer should be prepared to work with 2n samplesfor most tests. The folding operation forms a so-called butterfly network because of the butterfly shapes in the calculation flowchart. let us consider the manner in which MATLAB performs the FFT and the corresponding scale factors needed to produce RMS spectral levels.

N/2 -21m{X(k)} k-I.N/2-1 and (7.52) In turn..N/2-1 whereIX(k)1 = ~Re{ X(k)}2 + Im{X(k)}2 and the phase is computed using l/Jk = tan-l(~) 1Z"+tan-l( -Im{ X( k)} Re{X(k)} ifRe{X(k)}~O (7. DSP-Based Testing 219 Y(k)=~ly[n] n=O e-jk(~)n (7..58) NI2 .14) to be ck .[i-'..55 ) where Re { } and 1m{ } denote the real and imaginary parts of a complex number.[i to obtain . (7.2....53) and the corresponding cosine/sine coefficients are found according to Eq.N/2 (7. Again..N/2 2Re{X(k)} k=I..56) 2IX(k)1 k=I.. respectively...2. The magnitude and phaserepresentationis determined using Eq..N/2 -I (7.{ Ck ck-RMS-... (7. we divide the spectral coefficients ck (except the DC term describedk=0) by . To do so..={IX(k)1 k=0.57) ) if Re{ X(k)} < 0 In many situations we shall find it more convenient to report the spectral coefficients in terms of their RMS values.Chapter 7 .. we must alert the reader to the different scale factors in front of these terms." . the complex spectral coefficients X(k) of the DTFS representation of the periodic extensionofy[n] are given by X(k)=~ N (7.44) to be ak= { Re{X(k)} k=0.:JL k =0 k_I (7.54) bk= { 0 k=0.

1414. -0.. -0.2}.the cosine/sine spectral coefficients are determined from Eqs.1414.0. -0..1.54) and (7.56) into (7.5657 + jO. 0.0707 0 + jO. -1. compute the spectral coefficients {ak} and {bk} of a multitone signal having the following 8 samples.1414. -1.5657 0 0. {0.0707 + jO.6 Using the FFT routine in MATLAB.N/2-1 (7.0000 Y = FFT (x) = 0.0.1. (7.1414. -0.0707 8 0 0. 1.J2IX(k)1 k =0 k=1. These samples were derived from a signal with the following DTFS representation xn ] =cos_2 8" [ [ 2tr ( )n-2 [ 2Ir tr ] +0.2 cos_3 8 ( )n-4 ] tr Also report the magnitude (RMS) and the phaseof each spectral coefficient.0. -0. -0..1414. Example 7.8.2].8.1414.1414.jO. 1..59) *iX(k)1 k=N/2 The following example will further illustrate this procedure.0.j4.5000 0 Subsequently.5000 =~ = 0.5657 0 + j4.58). we obtain IX(k)1 ck-RMS= .5657 .jO. Solution: With the samplesof the multitone signal described as x= [0.220 An Introductionto Mixed-Signal Testand Measurement IC On substituting Eq.0.1414.0000 0 ~ X 0 0 0.55) to be . the FFT routine in MATLAB produces the following output.0707. together with the scaled result 0 0 0.jO. (7.

2. {ck}={10.90. Ans. all others are zero. and A~I.9. M~lr(3.8659.500}.12. 1. {a3+jb3}~{0.0 sin[3 (2lr/10)n+lr/8] for n~0. -1. Using MATLAB.0 Q3 Q4 ~ b4 0. 1.OOOO}. N~64..1414 0 and ~ = ~ 0 1. 9.615. the corresponding magnitude (in RMS) and phaseterms (in radians) are as follows co-RMS cl-RMS c2-RMS c3-RMS c4-RMS ~ - - 0 t/Jo = 0. ljFO.lr/ 92 = /2 11'1 - 0 0 ~ tfJ4 lr/ /4 0 At this point in our discussion of the FFT.1414 0 Finally. compute the FFT of the 10 samplesofx[n] and determine the corresponding {Ck} and {l/JIc} spectral coefficients.. O..3.Chapter7 . Evaluate x[n]=1. 2.3726..50.14156)...815. it would be instructive to consider the spectral properties of a coherent sinusoidal signal and a noncoherent sinusoidal signal having equal amplitudes.M~3. For each case.172. tjJ=0. N~64..7071 0.50.4220. 7.0.970. Express the magnitude coefficients in RMS form.0. DSP-Based Testing 221 Qo QI Q2 0 Eo 0 = 0 0 0. Ans.1. compute the FFT of the 10 samples of x[n] and determine the corresponding {ak} and {bk} spectral coefficients.1414 0 0 and .3.7 Using MATLAB's FFT routine. Using MATLAB. .060}.834..3826+jO. Exercises 7. 3.697.9.1. 13.plot the RMS magnitude of the spectrum in dB relative to a I-V RMS reference level.13.9238}. Evaluate x[n]=(n-3)2 for n=0.5. 1.0868. {ck-RMs}={10.243. -- Example7. {l/JIc}={O. compute the spectral coefficients of a coherent and noncoherent sinusoidal signal with parametersA~l.

2.2). ~ magdBV_X(N/2+1) Z=fft(z)/length(z). P=O. end. % magnitude of spectrum Z % AC Terms magdBV_Z 20*log10(1/sqrt(2)*abs(X(N/2+1))). magdBV_Z(1 :N/2+1) % end =20*log1 0(1/sqrt(2)*abs(Z(N/2+1»). x(n )=A*sin(2*pi*M/N*(n-1 )+P). % magnitude of spectrum X % AC Terms magdBV_X magdBV_X(1) . end. x. % DC & Nyquist Terms magdBV_Z(1) = 20*log10(abs(Z(1))).M=3. % signal definition for n=1:N. plot(0:N/2.2). subplot(1. stem(O:N-1.1). ':'). subplot(1. . subplot(1. magdBV_X(1:N/2+1». A=1. ':'). % perform Fourier analysis X=fft(x)/length(x).222 An Introductionto Mixed-Signal Testand Measurement IC Solution: The following MATtAB routine was written to produce 64 samples of the coherent and noncoherentwavefonns and to perfonn the corresponding FFT analysis: % coherent signal definition. The resultsof the analysisfor the coherent wavefonn are shown in Figure 7. stem(0:N-1. figure(2). while the corresponding magnitude the spectrum of is shownon the right.units of dBV 20*log10(sqrt(2)*abs(X)). P=O. A=1. The timedomainwavefonn is shownon the left.units of dBV = 20*log10(sqrt(2)*abs(Z)).1).2. ~ % DC & Nyquist Terms =20*log10(abs(X(1))).2. subplot(1. . z. for n~1 :N. M=pi. % noncoherent signal definition N=64.11. -z - z(n)=A*sin(2*pi*M/N*(n-1)+P). The spectrum expressed dB relative to a I-V RMS reference is in level.2. plot(0:N/2. x N=64. magdBV _Z(N/2+1) % plot routine figure(1 ).

'..~):..-ZO.~j~~o 0-'0. .... ~ N -0. . ~. '.. .... ~ . '5-200.' . we clearly see a significant difference.12.. 1 0. one uses a zeroorder interpolation operation to produce a step or bar graph of the spectrum... 0 -0. : :::::::::::::. This is exactly the value specified in the code that is used to generatethe coherent sinusoid. or as we shall use in the next few examples..w...'..2~ o:~o sample..~11.. 3:0 ~ ... DSP-Based Testing 223 When this definition is used..~~~ i-300. 0 :~~ ::::::"0 "C: :~:: :0::::::: ~ ~: ~ 0.'.. :::::::::0 ~-100 c '::::::: :0::::::::: : :::::::. it is written as ck-RMS dBV ) =20 10glO ( ( ck-RMS I-VRMS ) (7.Noncoherent waveform time-domain and spectrum.5 ". ~.." ~ .... In the ..s ~ ::: ~ ! ~ ~....~::::::::Q. -10 '. ~-30' }-40 . plot On comparing the magnitude of the two spectra. the decibel units are referred to as dBV.... a single spike occurs in bin 3 with over 300 dB of separationdistance from all other spectral coefficients.5 ~':~:~.'1J!~~ ::..::::::::::.. n -500 1~.:. ~:i:ii:~ 0::::::.11. ~ . Z'O Bm 30 Figure7..'0 . ~j~..5 5 x 0 ~:..".. In some cases..Coherent waveform time-domain and spectrum.. f.":.'~I:.. n ~O -4000 1~ Figure7. _."'. 1::::::[ ~::~::: ~:i:::::: ~ .. a first-order interpolation operation.'. A closer look at the numbers indicates that the tone has an RMS value of 0.':':o]~r~ :.12. : i : ~. it is customary to plot the frequency-domain data as a continuous curve by interpolating between frequency samples instead of using a line spectrum. : -10 O"'Z~ sample. ~t:.5 t ti!:~i:~ ~::::::m ~:i~:i:~ ::::::::: :. ~ : :: : z~ Bin ~.Chapter7 . Mathematically.. plot The results for the noncoherent waveform were also found and are shown in Figure 7... : ::::::::: ::: "C::: : :. ~-10.'i:i:i~.60) Also. 0"'.707106 (-3.:..0103 dBV in the plot) or an amplitude of 1.l~ .. In the caseof the coherent sinusoidal waveform.". ::::::::::""...

z{n)=A*sin{2*pi*M/N*{n-1 )+P). A~1. Rather.224 An Introduction to Mixed-Signal Testand Measurement IC case of the noncoherent sinusoidal wavefonn. this approach is used by most benchtop instruments found in one's laboratory. N 01/ N representsthe number ofUTPs that the signal will complete in the observation interval. On the right is the magnitude of its spectrum.7 by collecting 8192 samples instead of 64. Our next example will illustrate the effect of a longer observation interval on the spectrum of a noncoherent sinusoidal wavefonn. Consequently. Instruments of this type are usually not expected to generate a result in a very short time. On the left is the plot of the time-domain wavefonn over the last 64 samplesof the full 8192 samples. multimeters. such as spectrum analyzers. they are only required to produce a result every 1 or 2 s. The . it is extremely difficult to detennine the amplitude of the noncoherent sinusoidal signal with its power smearedacrossmany frequency locations. as any more sampleswould fill the graph and mask all detail. end.8192. Determine the amplitude of the input signal from its spectrum.7 and compare it to the one derived here.7 was modified as follows: % noncoherent signal definition.8 Extend the observation interval of the noncoherent wavefonn of Example 7. no single spike occurs. M=pi. Example 7. When we refer back to the spectrum derived in Example 7. noncoherentmeasurementsystem. z . Samples taken from the input signal are unrelated to the sampling rate of the instrument. one can construct a less complex. Plot the corresponding magnitude of the resulting spectrum. Solution: The MA TLAB code for the noncoherent signal from Example 7. then they would be corrupted by the power in these leaked components. Here we distinguish between N. and NOI. NOI. and are therefore noncoherent. % observation interval N. the number of samples collected over the entire observation interval. % signal definition for n=1:NOI. The Fourier analysis was then repeated and the corresponding spectrum was found as shown in Figure 7.13. The most straightforward method to improve the measurement accuracy of a noncoherent wavefonn is to increase its observation interval. and digitizing oscilloscopes. If other signal components were present. the number of samples in one UTP. Generally speaking. What is worse. we see that the general shapeof the magnitude of the spectrum is much more concentrated around a single frequency and that the frequency leakage components are much smaller. such as 25 ms.64. the single-tone wavefonn appears to consist of many frequency components. which is usually more than adequate. In other words. P:O. Rather.

'.. 0. 4~ 'i. 8140 :"." 81 samp e. Noncoherent waveform time-domain and spectrum expanded plot observation interval.707 V RMS/I V RMS)].' .. .['. we provide in Figure 7. . one cannot rely on the peak value of the spectrumas was done in the coherent waveform case.5+j1i:~.13. i . 'fj.:.'.- "C ..i ~:~: ~..i > ~ : . "" 0 .'. 1 .. Rather. >-1 m - .. Ideally. we must take into consideration the power associated with the side tones. .23l8 dBV occurs in bin 402 [bin (M/N)NoJ].Chapter 7 . .. To improve the estimate.' '. ~ -:: c. the spectral peak value should be -3. " " " " . the frequency range is identical in each case. To see this more clearly... n : :::. whereas in the previous casewe plot from 0 to 63... let us consider that the power . -50 3~8 '- ~ .-40.' .14 an expanded view of the spectrumaround the spectral peak. . . . . In this case we are plotting the index or bin of each frequency components from 0 to 8191. 4~0 '.r..0103 dBV [= 2010g1o (0. i:: (/) -' -1000 2000 Bin : 4000 : Figure 7.. It is important to realize that each bin is equivalent to Bin ( Fs / N OJ) Hz. In other words.. t. 1 . '1 I.'!. DSP-Based Testing 225 astute reader may be wondering about the scale of the x axis. In order to estimate the amplitude of the input waveform. ...1i~. As the magnitude of these side tones drop off fairly quickly.. ~ E-3 ~ u. .ii~l~". .. '...:. . view tone Here we see that a peak spectral value of-3.: j~1. ~2 Bm .14..2 . ..' ' : 1 -20 ~-o: -1 :0::'. 4~6 Figure7. we must use several frequency components centered around the peak spectral concentration to estimate the waveform amplitude.' 0. ~:~: ~::. only the frequency granularity is different.Expanded of the noncoherent aroundthe spectralpeak.

In Section 7. z(n)=A *sin(2*pi*M/N*(n-1 )+P). Solution: Let us begin by investigating the spectral properties of the noncoherent waveform of Example 7.3. as in most production test situations. This window is shown in Figure 7. We could also improve the accuracy of the estimate by further increasing the observation interval. increasing the observation interval to 131. Compare the spectra with the results from a rectangular window (i. as denoted by the ". u= 1/epsilon * z . epsilon=sqrt(sum(w.072 samples will improve the amplitude estimate to -3.*" operation. the amplitude estimate becomes -3. consisting of 64 samples (Figure 7.1%.8 consisting of 64 and 8192 samples.15(b) for 64 samples. However. for n=1: NOI. Next. mcluding more side tones into this calculation will only help to improve the estimate.0355 dBV. On doing so.9 Through the application of a Hanning window. side tones less than -60 dB below the spectral peak value will improve the accuracy to within 0.12). N=64. In addition. The code is: % noncoherent signal definition z .* w.0109 dB. one is always searching for a faster solution. The next example will investigate this further.*w)/NOI). % windowing operation w= hanning(NOI)'. the method of wind owing was suggestedas a possibility.7.226 An Introductionto Mixed-Signal Testand Measurement IC associatedwith the input signal is mainly associatedwith the power of the five tones before and after the spectral peak. helped to improve the measurementaccuracy of the noncoherent waveform. each sample of the waveform is multiplied by a corresponding sample from this windowed function. Extending the observation interval in the previous example certainly helped to decreasethe amount of frequency leakage.e. For example. the windowed data are scaled by the window shape factor6 denoted by . Example 7.1. compute the magnitude of the spectra of the noncoherent waveforms described in Examples 7. Generally speaking. A MA TLAB script was written to perform the windowing operation. P=O. A=1. % observation interval % signal definition - MA TLAB provides a built-in function called hanning that generates the Hanning window. NOI=64. the nonwindowed results obtained previously). respectively.7 and 7. which. in turn. M=pi.. end.

612. -2. As side tones are present about the peak value of the spectrum. > a) 0 %_:~.. we obtain a combined RMS value of 0. forcing the endpoints the wavefonn to meet smoothly. Perfonning a square-root-of-sum-of-squarescalculation involving the RMS value of the signals presentin bins 1 to 7. This in turn implies an .. 60 .15(c). then the window shapefactor is simplygivenby E= Wl. Windowing results original (a) noncoherent waveform. 20 In Figure7. 1 0 2 20 40 sample. This leadsus to the new wavefonnshown in Figure 7.~~. we must consider these tones in the estimate of the signal amplitude.with N=64 the Hanningwindow has 8=0. This servesto equalizethe power in the windoweddata with that in the original wavefonn.. an expandedview of the spectrum about its peak is shown in Figure 7. dataare said the to havebeen viewed through a rectangular window.ased Testing 227 epsilon..n : . of An FFT was then perfonned on the modified wavefonn from which the magnitudeof the spectrum derived. and (d) spectrum magnitude. If the window time samplesare denotedw(n). Superimposed was is on theplot is the spectrum the original noncoherent of wavefonn derivedin Example7.E.n : : 60 : 0 20 40 sample. : Q~: : i-:o c% ~ : Rectangular: wi~ow: ~ -20 I 40 2. Althoughno specificwindow operation was explicitly perfonned.61) Nn=o In this particularcase. DSP-B. In order to estimate the amplitude of the signal present in the windowed data.15(d). (b) Hanning window.16. (c) windowed data. N-l ~ (n) (7.7070674.6 without windowing.1111_- Chapter7 . As is evident.ie. n 6'0 0 10 B.15. The windowedspectrum shownin Figure7.~..the Hanningwindowed spectrum much more concentrated is abouta single frequencythan the rectangular windowed spectrum. The window effectively squeezes endpointsof the the noncoherent wavefonn toward zero.0 samp e..

sO ~ . i.~ ..'.. . . .:. As we shall see in this next example consisting of a noncoherent multitone signal. very much like the coherent case.'. However.. windowing was used to improve the measurementof a noncoherent sinusoidal signal. view noncoherent around spectral tone the peak.. . For all intents and purposes. of course. : ~ 3500 4000 -3DDII . .17. :. .:. ~ ' '.:... . : " ~-150 . .. . The resultsare shownin Figure7. . . .s '0 E 2 -2 - 13 8(/) . .' . : . ~ ~ -Hanning - j : ~400 ..' : .. .. an accurate estimate was obtained without extending the observation interval over and above that of a coherent sinusoidal signal. .. D ..together with the spectrum resultingfrom a rectangular window..""'" ..' Figure 7. -1 1 2 3 4 ~ BIn 6 7 8 Figure 7. . . find the the to we spectrum much more closely concentrated abouta single frequency. . Spectral comparison rectangular Hanning of and windows..999944.. this is indeed not the case. . -: ....' '.preprocessing with the Hanning window is just as effective as the coherent measurement in this example. the Hanning window has a very narrow spectrum.. . . . . Clearly.... .' ~ ' ~ect:ang~lar windOw. ~.. is that a longer observation interval is necessaryand that side tones have to be dealt with. .. 1~ 1500 2~ 2~ .. 0 " c -50 . If we increase numberof samples 8192and repeatthe windowingoperation. ~ v ~ C -. . . The drawback. . . this is unity and was found with only 64 samples.228 An Introductionto Mixed-Signal Testand Measurement IC amplitude estimate of 0.. Expanded of thewindowed. It would be suitable for making measurementsin situations where more than one tone is present in the input signal. .wi~d'o~-'. . : I . . repeatability of measurmentsis degradedin windowed systemsin the presenseof random noise.16. . This example may incorrectly give the reader the impression that windowing can resolve the frequency leakage problem associated with noncoherent signaling with no added time expense..'. .17.250 ~ ". .' ~-100 :.. In the previous example. . . In fact. . . . Unless improved frequency resolution is necessary. .

..18. P2=O. A1=1. ~ ~ 0 ".18on the left-handside. : : : . ~ .M=Ji.10 Detennine the magnitude of the spectrum of a multi tone signal consisting of three noncoherent tones with parameters."". Solution: The following MATLAB routine was written to generate the 3-tone multi tone signal with a Hanning window over a 64-sample observation interval: % noncoherent 3-tone multitone signal definition NOI=64. :: :. A3=1. : . . : '0 E-150. ~ j ::: . % windowing operation w= hanning(NOI)'.~ ~ -20 . z(n)=A1*sin(2*pi*M1/N*(n-1)+P1) + A2*sin(2*pi*M2/N*(n-1 )+P2) + A3*sin(2*pi*M3/N*(n-1 )+P3). : .: : ."". end. M2=pi+1. . Bin :. N=64. tfr=O. N=64.M=Ji+l. and A=l. 5.. ~ -50. Theplot extends overthe Nyquistfrequency range. % observation interval % signal definition The routine was executedand the corresponding magnitudeof the frequencyspectrumwas derived usingthe frequency-domain conversion routineof Example7.'.. 0 .~ j. . -80 -1000 10. A2=1.Chapter7 .""""".M=Ji+2. u= 1/epsilon * z . tfr=O...""'i ' ""'.""'. M3=pi+2."'. A=l.~""""'. P3=O.-200 . . ~. Windowed three-tone multitone spectra with N=64 and 8192.7. :: . N=64. . 5. DSP-Based Testing 229 Example 7. M1=pi.. c '5-40 ~ .. :J ~ u . '0 E :J ~ u -60 ..*w)/NOI). epsilon=sqrt(sum(w."'.' ". A=l."':""..".* w.: c '5- 100 : ...... The result is shownin Figure7. N=64.:.. for n=1 :NOI.""""'~ 20 30 -2500 2000 Bin 40'00 ~ nli Figure 7. tfr=O.".":'.i"""""~"""""i.."". P1=O.

03 dBV. The transformation is lossless. Exercises 7.625 Hz.20) back into (7.5067. In fact. This is shown on the right-hand side of Figure 7.18.3151.4. Ans. -33. A signal has a period of 1 ms and is sampled at a rate of 128 kHz. Ans. If we substitute the expression for the frequency-domain coefficients given by Eq. meaning that all information about the original signal is maintained in the transformation. If the observation interval is increased.62) In practice. " .14. (7.3826. -~9.7562.1 Equivalence of Time. : 7. Since no information is lost in the transformation from the time domain to the frequency domain. Indeed. Surprisingly. 1 kHz. -36. each tone can be accurately measured with a relative error of no more than 0. to 8192 samples. we clearly see that we obtain our original information I x=w[w-1X]=WW-1x=x (7. it seemslogical that we should be able to take a frequency-domain signal back into the time domain to reconstruct the original signal.596. This was shown to be equivalent to a discrete-time Fourier series representationof a periodically extended waveform. this is possible and can be seen directly from Eqs. -22.7796. 7.-9.and Frequency-Domain Information A discrete Fourier transform produces a frequency-domain representation of a discrete-time waveform. 15. 7. The results of an FFT analysis of a noncoherent sinusoid indicates the following significant dBV values around the spectral peak: -38. 7.5-V amplitude. Estimate the amplitude of the corresponding tone. say.20). Express its amplitude in dBV units.. (7. the same FFr - . then better frequency resolution is obtained and a clear separationof each frequency component is evident. With the side tones around each spectral peak below 100 dB.230 An Introductionto Mixed-Signal Testand Measurement IC -.15. what is the frequency resolution of the resulting FFT? If the number of samples collected increasesto 8192 samples. 0. This is a direct result of frequency leakage..what is the frequency resolution of the resulting FFT? Ans.19) and (7. A signal has a 0.9061.19). the form of the mathematics used to perform the frequency-to-time operation is very similar to that used to perform the time-to-frequency operation. It is as if only 2 tones were present in the input signal. If 128 samples are collected.4 THE INVERSEFFf .16. -25.6514.001% using the method of the previous example. the spectrum appears to have only 2 spectral peaks. -7.

. Example 7. except for some possible array rearrangementsand some predictable scale factor changes. When the FFT is used to perform the frequency-to-time transformation.3. DSP-Based Testing 231 algorithm can be used.. and from their inter-relationship described. A flag is set to determine whether the FFT is forward or inverse.X=[X(O)X(I) . we first note from x[n] that the spectralcoefficientsof the DTFS written in trigonometric form areimmediately obviousas f. Our next example will illustrate this procedure using MATLAB.. theseare relatedto the in coefficients the DTFSaccording of to Y(k)=NX(k) To obtainX(k).45).Chapter7 . (7. 0 0 . Phase information at each test frequency must be combined with the magnitude information in the form of a complex number using either rectangular or polar notation. The calculations are so similar that some testers perform an inverse FFT using the same syntax as the forward FFT.r '" c2 = 2 c3 C4 ~ = -~ 0. Co cl - 0 1 and IPo Y1 - A.5 cos[ 3(¥)n] Determine time-domain the samples usingMATLAB'sinverseFFT routine. X(N-I)] and Y=[Y(O) Y(l) ..5 0 ~ ~4 0 0 Subsequently.. i . Y(N-I)] with N=8 are determined from Eq. Solution: The inverseFFT is performedin MATLABusing a vector Y that containsthe samples the of FouriertransformY(k) in complexform. As described Section7. It is worth noting that the magnitude of a spectrum alone cannot be converted back into the time domain. it is referred to as an inverse FFT. The specific format will depend on the vendor's operating system..11 A discrete-time signal is described by its DTFS representationas - -- x[n]=1+2 cos[ 2(¥)n+~ ]+0. to be .

7071 0 ~ 8 0 5.64) can be rewritten as a square-root-of-sum-of-squarescalculation given by . these time domain samples agree with those obtain by evaluating x[ n] directly at the sampling instances. we obtain the following time-domain samples 2.7678 -0.2 Parseva)'s Theorem The RMS value XRMS a discrete time periodic signal x[ n] is defined as the square root of the of sum of the individual samplessquared.232 An Introductionto Mixed-Signal TestandMeasurement IC x= 1 0 0.9142 -0.9141 -0.j5.4142 2. (7.25 0. according to Parseval'stheorem for discrete-time periodic signals statesthat the RMS value XRMS a of periodicsignalx[ n] described a DTFSwritten in trigonometric by termsis givenby 2 Co +- X RMS = 1 N/2 ~ L.0606 -0. Eq.6568.7071 0.4.0606 Of course.7071-jO.6568 0 Submitting the Y vector to MATLAB's inverse FFT routine.normalized by the number of samplesN.7071+ jO.25 0 0.6568+j5. 2 ck 2 k=1 When the magnitude of each spectral coefficient is expressedas an RMS value.4142 1 x=IFFT{Y}= 2.7678 1. 7.6568 2 Y = 8X = 0 2 5..

. occupies fewer spectral bins). corresponding The spectrum magnitude shownin Figure7.. Interpolation provides a higher degree of time resolution when measuring parameterssuch as rise and fall time. 8.4. By performing an FFT on this clock signal. The digitized samples are corrupted with a large amount of noise.by contrast. etc. 4. It is the easiest fonn to remember. We can removehalf of the at noisepowerby simply settingall the nonsignalFFT elements zero.66) 7. The clock signal. etc. additional zero-value bins to the FFT. to be made directly from the DTFS description. .which accounts half to for the numberof bins. Sincewe havecaptured cyclesof the square 2 wave. and other time-domain characteristics with twice the repeatability than if we had used the original noisy signal. Where would we use this type of double transfonn in mixed-signal testing? There are several applications for the inverse FFT.Chapter7 . locatedin a set of predictable is FFT spectralbins. Consider the sampled waveform in Figure 7.3 Applications of the Inverse FFT One might ask what useful purpose is served by perfonning an FFT and then undoing it with an inverse FFT. Whenever we perfonn an FFT or inverse FFT on N samples. we shall makegreatest of this fonn of Parse use val's theorem. By appending N. After cleaning up the square wave in this manner. we can measure rise and fall times.19(a). We can also interpolate points between the samples of a digitized wavefonn to allow more x axis resolution for time-domain measurements.. which is a digitized lOO-MHz digital clock. For example. bins 2. noise. DSP-Based Testing 233 XRMS= V ~ 6 t:k-RMS In this text. we can effectively changethe FFT frequency resolution from Fs/N to Fs/(N + Nz). we always get a result with N samples. thereareno extrascalefactorsto keeptrackof. which we would like to remove.e. One is the removal of noise in a time-domain signal to produce a smoothed wavefonn.19(b). Noise components in the time-domain signal are scatteredall over the frequency-domain FFT spectrum. Another useful application of the inverse FFT is interpolation of a limited sample set into a more detailed sample set. When the signal bandwidth is lower (i. This is a direct result of Parseval'stheoremdescribedin the previous subsection. settling times. the RMS noise level associatedwith a signal is the square-rootof-sum-of-squares of all bins (excluding DC) that do not contain signal-related power given by Xn= V ~.~nal ~ ~ 'U"~ (7. immediately following the Nyquist frequency at bin N/2. 6.e.19(d)]. a greater improvement can be obtained becausemore spectral bins can be set to zero.). we can produce a frequency spectrum of the clock shown in Figure 7.19(c). as The importance of Parseval's theorem is that it allows the computation of the RMS value associatedwith all aspectsof a signal such as distortion. is An inverse FFT then restoresthe original clock signal with half of the noise removed [Figure 7.the fundamental energyis locatedin spectral 2 bin with harmonics integermultiplesof 2 (i.

..20(b) has been expanded to include 4 times as many spectral bins. Frequency-Domam ~ Filtering Ot . rather we used the smallest numbers that can could be representedon our computer. . The expansion is accomplished by padding extra zeros in the middle of the original FFT data...20(d).:.4. Time-domain smoothing usingthe inverseFFT: (a) originalnoisyclock signal. 7. time-domain filtering is rarely used in mixed-signal testing applications. 2 = - i. recreates a time-domain signal with N z/ N interpolated samples interspersed between the original sample set.we did not use zeros here. as the spectrum of a signal is already available in the computer..4 .19. As such. and Figure 7. as shown in Figure 7. The inverse FFT. Figure 7. the time resolution improves by the factor (N + N z )/ N .n !j?. Frequency-domain filtering is faster to implement than time-domain filtering.20(b) shows the magnitude of the spectrum of this waveform from bin 0 to bin N-I. Frequency-domain filtering is performed by multiplying the signal spectrum by the desired filter's frequency response.= "tJ 0 : : :: : : : : IV roO. simulating electronic filters in traditional analog instrumentation. In other words.20(c) the spectrum from Figure 7.234 An Introductionto Mixed-Signal Testand Measurement IC > m . we avoided minus infinity on the logarithim plot of the spectrum. restored (d) time-domain signal. "tJ "tJ" 0 iV E ~ Q) IV -50 : : -5 > m "tJ sample. In this way. For numerical reasons.20(a) illustrates a sampled sine wave with 64 samples. :: .n ! i Figure 7. partially (c) zeroedspectrum. in turn. The parameterNz should be a power of two in order to maintain compatibility with the inverse FFT algorithm. 1 "tJ0 '- iv Q) IV - ~ - . : . :: :: .(b) magnitude i of clocksignalspectrum. "'g-1000 c% 20 Bin 40 sample. Another useful feature of DSP-basedtesting is the ability to apply arbitrary filter functions to the collected samples.= IV "tJ '- IV 0 E 2 0 -50 . Filtering can be applied either in the time domain or in the frequency domain. The inverse FFT of this expanded data results in a conversion back to the time domain with four times as many samplesas the original waveform.. Time-domain filtering is accomplished by convolving the sampled waveform by the impulse responseof the desired filter. In Figure 7.-1000 20 Bin 40 .

Time-domain interpolation usingthe inverseFFT..."" . where Ts is the sampling rate.:eros. e- 1~0 Bin sample.... filters are used to alter the phaseof a signal to improve its transient behavior (i..'.20.e.:'. .v 0:0 ~v.'j : ~ ~ c x -0. For instance. 0 5 ro i "C ~-0..""":. to obtain (z)1 H z=e j(jJT =H s ( )= ao + ale.67) . .'. U : : Q) -10 > "C CD C . 4 :'" o."'o.". n Figure7.67). 20 40 sample.68) l+~e J(jJT s +. Filter functions are selected to provide a predescribed frequency responsesuch as a low-pass or band-passbehavior..'. 0" o' x 0-200 E 2-300 ~ :: .."'.68) that the behavior of the filter can be collectively understood as a complex number representedin terms of real and imaginary parts as H(ej(jJoTs)=Re{H(ej(jJoTs)}+ j Im{H(ej(jJoTs)} (7.:' .".:" ""8-400~ ~ :: ""'.~ P.~o.. we see from Eq.~. In another application.'+aN~ J(jJNT s (7. (7.. ::.~ 0 .. £i Nz..~. .....5 o.I= "'.0 0 : 00: 0 0: oQ 00: ~~. the z-domain transfer function H(z) of an arbitrary discretetime filter is described by H( z)= 1 N aO+alz1 +...~.o~ : ~. In general.0.. ej(jJTs j(jJT j(jJNT s +..~~~i:. reduce ringing).+bNe s ~ For any single frequency ~.+aNz N l+~z +...... ~ DSP-Based Testing 235 ~ 00 ~ ~ ~-100 0 ~ ~ ~ 0. :: ."":" ....5 'o'.. The responseof the filter to physical frequencies is determined by substituting z =ej(jJT S into I [ "" Eq."..69) .:""" 2~0 . a low-pass filter is used to suppress the high-frequency content of a signal while allowing the low-frequency energy to pass relatively unchanged. n :: : ..'~:. (7.5 -10 ~-300 . """".~ 1 ~ :00 ~oooo Chapter7 .'..+bNz (7. r5?)-4000 ro 20 Bin 40 60 i-200 U) E-100 :I .'...:: ::: ~ "'.

.625.71)canbe rewrittenas Y out] 21l' ~ .17.0.~kT s v. 1. or in termsof magnitude phase and as H( ej(f)oTs) =IH( ej(f)oTs )I-#H( j"oT. 1..5.7676.875.~ of thefilteroutput related thetransform is to ¥in ( ejDff s)of theinputaccording to Yout (ej(f)Ts)= H (ej(f)Ts ¥in(ej(f)Ts) ) (7. the ADS.0. 7. the transform Yout ej(f)Ts ( ) ~~ c.70) From the convolution property of discrete-time Fourier transforms. ) (7.0.19.3536.~kT s N )=H(e ] .0.236 An Introductionto Mixed-Signal Testand Measurement IC -'11 Exercises 7. how manyzero-padded bins shouldbe added the spectral to databeforeperformingthe inverseFFT? ADS.5 cos[3(T)n] UsingParseval's theorem.I.. For the following signalx[n].1. k=O.0.{1. 3072.0.375. To increase time resolutionof the sampled the waveformto 0. 0.75+jO.25.N-I (7. A coherentsignal is sampledat a rate of 1 MHz over a 1024-~ time interval.~kT s N ) (7.25~..414. (e .73 ) . 7. N thenEq.18. computethe RMS value of eachfrequencycomponent (beginning with DC): x[n]=1+2 cos[2(T)n+~ ]+0. ADS. 0.. compute RMS valueofx[n] .computethe IFFT of the following sequence complexnumbers: of {1.75-j0.72) .71) If we limit the input to discrete frequencies (J)=-k. N ~in ) (e ] .375}.125}. (7. Using MATLAB.

. C -out e-j"(jk-out=H (k )C-In e-j"(jk-in k (777) .79) f/Jk-out =f/Jk-in -f/Jk-H Followinga similar line of reasoning usingthe rectangular but form of the DTFSrepresentation.. we can write k .80) Separating real andimaginary into parts.1.k-H substituted. we write at-out. N -1 as Yout (k)=H(k)Yln (k) Dividing both sidesby N (7.4 for k=O.74) ~=H(k)~ N N (7.78) -out Separatingthe magnitude and phasecomponentsleads to the result k C -out = H (k )l ck-In .75) leadsus to the relationshipbetweenthe input and output complexDTFS representation after filtering as Xout(k)=H(k)Xin(k) (7..jEt-out = [Re{H(k)} + j Im{H(k)}J( at-in . e-j"(jk-in (7. with the magnitude and phase form for H (k) =IH (k )lej.j[ -at-in Jm{H(k)}+bk-in Re{H(k)}] (7. we write k C e-j"(jk-out = I H ( k )l ej"(jk-H C k -In .jbk-in) = [ak-in Re{H(k)}+bk-in Jm{H (k)}J .. I (7.76) Returning to the trigonometric form of the DTFS representationwritten in polar form.we get ak-out =ak-in Re{H(k)}+bk-in Im{H(k)} bk-out =-ak-in Jm{H(k)}+bk-in Re{H(k)} (7.Chapter7 .81) . DSP-Based Testing 237 or with the shorthand notationof Section7. or.

f}j-1000 : : !? ro -0 '- 20 Bin. E U Q) . From the FFT result one creates a DTFS representation in either rectangular or polar form. Use MATLAB's built-in FFT and inverse FFT routines.' 40 ' . n Figure7.9355z2 Plot the corresponding magnitude spectra and time-domain signals before and after filtering. n .238 An Introductionto Mixed-SignalIC Testand Measurement -.0005 + O.OOllz! + 0. magnitude filter response magnitude filteredsignalspectrum. Solution: - Using the FFT data from Section 7.: .ro 5 10=- 1 ~ 0 :J ro -0 Q) '- IE Q) 0. apply a secondorder Butterworth filter having the following z-domain transfer function H (z) = 0. > !g 0 .5.s ro _0 ro -0 . Often. its spectrum was multiplied by the Butterworth filter transfer function and the resulting spectrum was converted back to the time domain via the inverse FFT. Next.21. this last step can be eliminated becausewe can extract all desired information from the filtered spectrum in the frequency domain.2. :: :: . > CJ -0 C sample. each frequency component of the input is scaledby the corresponding filter responseH(k) to produce the filtered frequency-domain output. The results are summarized in Figure 7. an inverse FFT can be performed on the filtered output to produce the filtered time-domain signal.21.12 Using the time-domain samples from the noisy clock signal of Section 7.(b) magnitude of spectrum.111 The procedure to filter a signal in the frequency domain is now clear. We first perform an FFT operation on the input signal to bring it into the frequency domain. E tli -"8-1000 Q) Bin sample.9334z!+0. Finally. filter transientsignal.5. Example 7.2 on the noisy clock signal. (c) of and of (d) ..0005z2 I-I.Transientandfrequency spectrabeforeand afterfiltering:(a) noisyclocksignal. ~ ~ -0 0 :J '- ro ro -50 :: .

then we can simply apply a brick wall band-pass filter to the FFT results. we can get a more accurateidea of how good or bad the telephone or audio equipment will sound to the consumer. Weighting filters are called out in many telecom and audio specifications becausethe human ear is more sensitive to noise in some frequency bands than others. The remaining noise can then be measuredby performing an inverse FFT followed by an RMS calculation. if a specification calls for a noise level of 10 !lV RMS over a band of 100 Hz to 1 kHz.Chapter7 7. The resulting reduction in tester complexity reducestester cost and improves reliability. The magnitude of the frequency responseof the A-weighting filter is shown in Figure 7. the weighting filter is applied to the analog signal before it is passedto an RMS voltmeter. The sameresults can be also achieved by adding up the signal power in all spectral bins from 100 Hz to 1 kHz. DSP-Based Testing 239 Noise weighting is one common example of DSP-based filtering in mixed-signal test programs. It is designed to approximate the frequency response of the average human ear. To do this we simply square the RMS value of each frequency component from . we can perform the same filtering function mathematically. Application of the A-weighting filter is a simple matter of multiplying its magnitude by the magnitude of the FFT of the signal under test. A very simple form of noise filtering can be used to measure the noise over a particular bandwidth. Application of a mathematical filter to a sampled waveform means the ATE tester does not have to include a physical A-weighting filter in its measurement instruments.22.4. eliminating all noise components that do not fall within this frequency range. phase variations have little effect on the listener and are therefore ignored in noise-related tests. I -so 10 10000~oooo Frequency (Hz) Figure7.A-weighting magnitude filter response. In DSP-basedtesting. For example.5 Noise Weighting .0 -60 L V 100 1000 . By weighting the noise from a telephone or audio circuit before measuring its RMS level. For matters related to hearing.22. ~o 0 -20 /'" I" V"""~ '" Gain (dB) . In traditional bench instruments. after the unweighted DUT signal has been sampled.

9.5 SUMMARY Coherent DSP-basedtesting allows the mixed-signal test engineer to perform AC measurements in a few tens of milliseconds. 1. respectively.20.1278. source memory.1107xlO-3 cos[ 2( ¥)n -2.25-j0.12. and capture memory of a mixed-signal ATE tester allow us to translate signals between continuous time and sampled time. 7.240 An Introduction to Mixed-Signal Testand Measurement IC 100 Hz to 1 kHz.0000. add them all together. For the Butterworth transfer function described in Example 7. determine the gain and phaseof the filter at the following three normalized frequencies: 0. 0. and 3 ( 2JZ" . digitizer. x[n] = 1+1. -O. respectively. /8) /8) Ans.12. Digital signal processing operations such as the FFT and inverse FFT allow us to perform operations that are unavailable using traditional non- .3229 ]+4.lo83. A signal with a DTFS representationgiven by x[n]=1+2 cos[ 2(¥ )n+~ ]+0.35. c2 k-RMS (7.22.82) k=BL Here BL and Bu are the spectral bins corresponding to the lower and upper frequencies of the brick wall filter (excluding any DC component). The A WG. ADS.5287xlO.3394. These same measurementsmight otherwise take hundreds or thousands of milliseconds using traditional analog bench instruments.3441e-jI. In this particular case.5 cos[ 3(¥)n] passesthrough a system with a transfer function described by that in Example 7.BL and Bu correspond to the 100 Hz and 1 kHz frequencies.5537xIO-4e:/J.. What is the DTFS representation of the output signal? Ans. 5. The gain and phase of a particular system at 1 kHz is 0.8 and -1r/4.7341. 2 ( 21f .7643XIO-3 cos[ 3( ¥)n -3.0566-jO.1278 ] 7. 7. and then take the square root of the total to obtain the RMS value of the noise according to V N-rms = F u "\:"' L.21. Express the result in rectangular and polar form.se:/J. I Exercises 7. Determine the spectral coefficient of the DTFS that correspondsto the output signal at 1 kHz when excited by a signal with a spectral coefficient described by 0.

7. compared to the push-the-button/read-the-answer simplicity of bench equipment. author of "DSP-Based Testing of Analog and Mixed-Signal Circuits". Chapter 9. "Sampled Channel Testing" will then extend these DSP-basedtesting conceptsto sampled channels such as ADCs. so it can overcome the repeatability problem inherent in windowing by simply averaging results or collecting additional samples. (7. Indeed. Bench instruments such as spectrum analyzers and digitizing oscilloscopes must use windowing extensively.83) .DSP-basedtesting also places a burden of knowledge upon the mixed-signal test engineer. In Chapter 8. since they are not synchronized to the instrument's sampling rate.83) suggests that it is also periodic in k as well. (7. Exasperated by the complexity of digital signal processing. DSP-based testing requires us to know a whole lot of "something.Chapter 7 .. DACs. a spectrum analyzer is not usually expected to produce an accurate reading in only 25 ms. Eq. as the role of nand k are interchangeable. Synchronization of input waveforms and sampling processes affords us the tremendous accuracy/costadvantageof coherent DSP-basedtesting. Fortunately. The signals entering a spectrum analyzer or oscilloscope are generally noncoherent.7 once told an amusing story about a frustrated student in one of his DSPbased testing seminars. so windowing is normally avoided whenever possible." we will explore the various types of DSP-basedtests that are commonly performed on nonsampled channels such as amplifiers and analog filters.84) . The insight provided by this observation can be used to re-arrange Eq. "Analog Channel Testing. We are fortunate in mixed-signal ATE to be able to use coherent sampling systems to bypass mathematical windowing. DSP-Based Testing 241 DSP measurementmethodologies. Despite its many advantages." The next two chapters will explore the use of DSP-basedmeasurementsin testing analog and sampled channels. mixed-signal testers give us control of both the signal source and sampling processes during most tests.83) in groups of N terms in the following manner x[n]=i( ao+mN+~{ak+mNCOS[ k(~)n ]+bk+mNSin[ k(~)n]}) (7.1 Fourier SeriesRepresentationof a Coherent SampledSignal Sampling a continuous-time periodic signal using coherent sampling principles leads to a discrete-time periodic signal x[n] with Fourier seriesrepresentationgiven by x[n]=ao+ ~{akcos[ k(~)n ]+bksin[ k(~)n]} (7. Matthew Mahoney. Time-domain interpolations. APPENDIX A. ATE equipment must be fast as well as accurate. However. and switched capacitor filters. As this signal is periodic with period N over the index n. frequency-domain filtering. the distressed student suddenly exclaimed "But this means we must know something!". and noise reduction functions are just a few of the powerful operations DSP-based testing makes available to the accomplished mixed-signal test engineer.

Subsequently. N will always be assumedto be even.. (7.86) sin[(~)(~)n]=o we can write Eq. In terms of the sampling theorem.85) as x[n]= L aO+mN + 00 L 00 N~-\ 2. N/2 representsthe sample set's normalized Nyquist frequency. (7.assuming is even. { [ak+mN+aN-k+mN]cos [ k (N ) ] 21r n m=O m=O k=\ (7.87) +[bk+mN-bN-k+mN ]sin[ k( ~)n ]}+ ~ {aN/2+mN cos[ (~)( ~)n ]} If N is odd.85) ~ {aN/2+mNCOS[( ~)(~)n ]+bN/2+mNSin[( ~)(~)n]} Recognizing that COS[(N-k)(~)n sin [ (N -k) (~ ) n ] 21f ]=cos[ =-sin k(~)n] [k (N ) n ] 2Jr (7.88) +(~ bk+mN .dueto the symmetryof the cosineand sine functions.84). Eq. so that we write x[n]= f m=O ao+mN +N~\ k-\ {( f m=O (ak+mN+aN-k+mN) ) cos[ k(~)n] (7. (7.additionalsimplificationscanbe made. Consider regrouping termsin Eq.242 AnIntroduction Mixed-Signal Test Measurement to IC and Further. then the upper limit in the summation should be replaced by (N-l )/2.asfollows the N x[n]=~ ao+mN+ N~\{ak+mNCos[ ~ k(~)n ]+bk+mNsin[k(~)n]} + + ~ N~\ {aN-k+mNCOS[(N-k)(~)n ]+bN-k+mNSin[(N-k)(~)n]} (7. In this work.87) can be rearranged such that the outer summation in the second and third term on the right-hand side is associatedwith each term inside the braces.

2 using cosine terms only.. ~ ~~~LL~ 5 0 (d) . ' .4.=o (bk+mN +bN-k+mN) 00 12N/2 = L 00 aN/2+mN m=O bk m=O (7. . determine the DTFS representation of the Fourier series representation of x( t) given in Exercise 7. Find the trigonometric Fourier series representation of the functions displayed in (a)-(d).2.... Using MATLAB. t (b) (a) . ]+bk sin[ k(~)n Fourier ]}+12N/2cos[1ln] (7..Chapter7 Finally.. 7 ~.. 7. by defining . t .1.. Using the summation formulae in Eq..1.90) series (DTFS) representation of x[n] Problems 7.s{~~~ -5 (c) 5 . -==t~fj:=J=::J~V -5 ..88) can be written in a less complicated manner as x[n]= 120 +N~l {12k k(~)n cos[ This representation is known as a discrete-time written in trigonometric form.89) =L m=O Equation (7. t 7. 7... Assume that the period in all casesis 1 ms...12). numerically compare your FS representationwith x(t).. expressthe result in magnitude and phase form.V -5 . --I ==J4~t=. t .. Find the trigonometric Fourier seriesrepresentation of a sawtooth waveform x(t) having a period of 2 s and whose behavior is described by: x (t ) = t if -1 < t < 1 . Also.. DSP-Based Testing 243 120 = L 00 aO+mN 12k = L (ak+mN+ aN-k+mN) m. Express the Fourier seriesin Problem 7. (7. Use 10 points per period and limit the series to 100 terms.3.

2e }7-n~ ( 2lr ) "[ 8 It ] 4 +O.2e [( 2lr 8 ) ] lr 4 j3-n~ [( ) ] 2lr 8 lr }S-n.cos 4trt+. numerically compare the samplesfrom your DTFS representationwith the actual samples given here. Derive Eqs.125.7. Begin by multiplying the DTFS representation given in Eq. Using MATLAB.244 An Introductionto Mixed-Signal Testand Measurement IC 7. express the result in magnitude and phase form.1451 3(-*)n ]-0. (7. (7. k odd ktr L 00 1 -cos(k 2trx103 t+~) 7.22) and (7. -1. 1 1 3 2 4 2 ( ) ( ) ] (c) x(t)=-1. determine the DTFS representation for these samples. Using MATLAB. 4..5+ k=l. O}.0649sin 4(-*)n] sin[ [ (b) x[n]=l+cos[(¥)n]+sin[(¥)n ]+cos[ 2(¥)n ]+sin[2(¥)n] -cos[ 3(¥)n ]-sin[ 3(¥)n] 7.10. .?: sintrt -~sin 21rt+~sin31rt-~sin4trt tr 2 3 4 ( +-.(7.21). 1. .tr +. A sampled signal consists of the following 5 samples: {0.4}. 0. 7.. Plot the magnitude and phasespectrum of the following FS representationsof x(t): (a) x(t) :. numerically compare the samples from your DTFS representationwith the actual samples given here..3e 3 Express x[ n] in trigonometric form. Plot the magnitude and phase spectra.5. ) x(t)=.1.tr +.[ cos( trt-%)+!cos( 2trt+~) (b) +. then sum n on both sides from 0 to N-J...3e 8 lr ] 3 +0. -0.23) from first principles.1. Plot the magnitude and phasespectrum of the following DTFS representationsofx[n]: (a) x[n]=0.( 2lr ) "[ +O... Using linear algebra. express the result in magnitude and phase form. Also..cos 3trt-.6. Also.8. 7. A sampled signal consists of the following set of samples {O.9. 3. Reduce the expression by using the set of trigonometric identities given in Eq..3. 7.4. A DTFS representationexpressedin complex form is given by }-n" x[n]=1+0. 2. Determine the DTFS representation for this sample set using the orthogonal basis method.11) by cos[k(21r/N)n J..2749 sin[ 2(-*)n] n +0.6150 sin [(-*) ]-0. . 4. Repeat using sin [k(2tr/N) n J.

7071.and7.7071.25)e1 3 (*)n] +(0.0.0. DS~-Based Testing 245 7. Given x[n]=0..5.. 7. 7.9)e1 2 (T)n]+(0. A DTFS representation expressedcomplex is given in fonn by x[n] =1+(1.25)eJ{ 7 (*)n] (a) Expressx[n] in trigonometric fonn.0.9.13.7071] (b) [0.9 cos[3(-T)n ]-0.16.25)e1S(T)n]+(1. -0.6..1. -0.7071.jI.8.7071. 7.4...25. How does it compare withx[n] found in part (a)? 7.-1.jo.0.1 sin[(-T)n ]+2.0. (c) Compute the FFT of the samplesfound in part (b) and write the corresponding DTFS representationin trigonometric fonn.jO.1.7071.1 cos[2(T)n] -0..9. verify your answers Problems 7.-0.-1. compute the FFT of the 10 samples of x[n] and detennine the corresponding {Ck} and {ifJIc} spectral coefficients. Derivethepolar fonn ofEq. 0.0000.0. Express the magnitude coefficients in RMS fonn. -0. (b) Using MATLAB.25+ jO. 0.4)e19 (*)n] +(0.15. Evaluate x[n]=n3-2n2-2n+1 for n=0.0.75.2+ jo. ..Chapter7 .1.7.5 cos[(-T)n ]+0.8+ jI. write a script that samplesx[n] for n = 0. (c) Compute the FFT of the samplesfound in part (b) and write the corresponding DTFS representationin complex fonn.9)e16 (T)n] Expressx[ n] in trigonometricfonn and plot the corresponding magnitudeand phase spectra.14.7071] 7.0.. (7. Usingthe FFT algorithmin MATLAB..45)from (7.7071. (b) Using MATLAB. Sketchtheperiodicextension the following sequence points: for of (a) [0. Given x[n] =(0. Using MATLAB.44)..0.25+0.2. write a script that samplesx[n] for n=0.17.25)e13(T)n].12.jO.0. How does it compare with x[n] found in part (a)? 7.1.11.0.1. +(0.4)e1(*)n] +(0.75+ jO.1 sin[ 3(-T)n] (a) Expressx[n] in complex fonn. to 7.0...7071.

derive the corresponding complex form of the theorem given in Eq. Using the FFT and IFFT routines found in MATLAB.3e [ (-8 ) 211" n+. The complex coefficients of a spectrum of a sampled signal are: {Xk}={0.0.2+jO.18 but view the data first through a Blackman window. 0.24.4. 0. (d) 8192 samples. Find the coherent sample set ofx[n] using MATLAB's lFFT routine assuming its spectrum is describedby the following: (a)x[n]=0.25+jO. 7.1cos[ 2(¥)n] -0.19. What is the RMS value of this signal? 7. compare the magnitude spectrum of this signal when the following samples are collected: (a) 64 samples.28. 3 4 +0. Repeat Problem 7.ls and is sampled at a rate of 1 MHz. (b) Blackman window. 0.4}. 0. Using the trigonometric identities described in Eq.what is the frequency resolution of the FFT? 7. Estimate the amplitude of the sinusoidal signal. Using the trigonometric form of Parseval's theorem in Eq. 7. If 128 samples are collected.27.20.25+0.26.0. Blackman. 0.31. 0.9 but this time use a Blackman window. An observation window consists of 128 points.9.3e [ (-8 )n-3 +0.5 cos[(¥)n]+0. verify that lFFT(FFT(x))=x.2e (-8 ) 11" ] J{ 7 2Jr n+-11" ] 4 .1. 7. 0.0.10 but this time use a Blackman window. (c) 1024 samples.25-j0. Consider generating a sinusoidal signal using parameters A=l.2-j0.64). derive the trigonometric form of Parse val's theorem given in Eq.estimate the amplitude of the sinusoidal signal. (7.3. and ( c) Kaiser window with f3=10 all on the samegraph. (7. (b) 512 samples.001}. 7. and Kaiser (f3=10) windows. together with the samp~es described in Exercise 7.246 An Introduction to Mixed-Signal Testand Measurement IC 7. 7. Using the built-in window functions found in MATLAB.23. 7.1 sin[ 3(¥)n] (b) x[n]=1+0. 1/1=0.21). plot the behavior of (a) rectangular window. andN=64. Repeat Problem 7. (7. What is the RMS value of this signal? 7. Next. Estimate the amplitude of the sinusoidal signal.9 cos[ 3(¥)n ]-0. 7.) n-11" ] 8 J.12. The magnitude coefficients of a spectrum of a sampled signal are: {ck}={0.22.18.64) as a starting point.64).25.29. compute the window shape factors for the rectangular. Repeat Example 7. RepeatExample 7.1sin[(¥)n ]+2. 0.05.30. (7.18 but view the data first through a Kasier (f3=10) window.5.25. 0. In all cases.] 11" J" 5 211" 3 +0. Investigate the effects of increasing the observation window on the spectrum of a noncoherent sinusoidal signal. M=9. By what factor does the accuracy of the calculation improve over the rectangular window? 7. 7.25.21. A signal has a period of 128 I. 7.2e J" 2Jr [( . what is the frequency resolution of the resulting FFT? If the number of samples collected increasesto 8192 samples.

NJ. and Prentice Hall.0020z2 1-1. by x[n]=0.32.ISBN: 013216292X 2.00402z1+ 0.2+jo. PrenticeHall. Oppenheim.jO.jo. NJ. January1985. Siebert.ISBN: 0133143864 S.25)e1 (*)n] +(0. RonaldW.and Applications(Third Edition).25. A signalwith noiseis described the following DTFSrepresentation.ISBN: 0262192292 4. Discrete-Time Signal Processing.35. Proakis and Dimitris G.what is theeffectivetime resolutionof this signal? 7. Oppenheim al. NJ 07632.64135z2 Whatis the DTFSrepresentation the outputsignal? of 7.25+2cos[(¥)n ]+IO-SCOS[ 2(¥)n] -10-7COS[ 3(¥)n ]-IO-Ssin[ 3(¥)n ]+IO-SCOS[ 4(¥)n] Whatis the RMS valueof thenoisesignalthat appears between bins 2 and4? References 1.5 cos[ 5(-*)n+f] passesthrough a system with the following transfer function H (z) = 0.TheFFT Fundamentals Concepts. Robert Ramirez. ISBN:0133737624 . Signals.1+2cos[(-*)n-f ]+0. Englewood Cliffs. NJ. Verify the samples Problem7.and Systems. Englewood Cliffs. Alan V. Manolakis. March 1989.and then converted back into the time domain.25)e1 (*)n] 3 (C) +(0. EnglewoodCliffs. The MIT Press. 1996. A signalwith a DTFSrepresentation givenby x[n]=0.25+jO.If of the spectrum this signalis padded of with 5120zeros..Circuits. September 1985.Chapter7 . et Prentice Hall.4)e1(*)n] +(0. John G.5610z1 +0. Alan V.34.4)e19(*)n] 7 7. SignalsandSystems. DSP-Based Testing 247 x[n]=(0.2.Cambridge.33. A coherent signalis sampled with a frequency I MHz over a I 024-~ time interval.0020+ 0. ISBN: 0138147574 3. Schafer. Digital Signal Processing: Principles.MA. in the 7. Algorithms. William McC. W. Englewood Cliffs.31by evaluating functionat eachsamplinginstant. PrenticeHall. August 1997.

1730 MassachusettsAvenue N. J. Harris. No. 200361903. F. Jan. The Computer Society of the IEEE.248 An Introductionto Mixed-SignalIC Testand Measurement 6. ISBN: 0818607858 . Vol.. 1978.1987.1. Washington D. On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform.C. Matthew Mahoney. 51-83.W. pp.. 7. 66. Proceedingsof the IEEE. Tutorial DSP-Based Testing of Analog and Mixed-Signal Circuits.

~ ~ 9 ~ -o-"'Ofo/co- -o.-'r 9 Force input PGA output (test mode) ~ Normal mode Monitor output channel.1 Types of Analog Channels Analog channels include any nonsampled circuit with analog inputs and analog outputs. analog buffers. Examples of analog channels include continuous-time filters. Analog STOUT .1 OVERVIEW 8. and cascadedcombinations of these circuits. Ing Ie-en d e d to differential power amp 1\1 OUTP OUTN OAC reference voltage +T = Figure 8. Dff allows the filter and PGA in Figure 8. programmable gain amplifiers (pGAs). "Sampled Channel Testing. "Design for Test (Dff)..'~ CHAPTER 8 Analog Channel Testing 8.1. switched capacitor filters." that a sampled channel may be broken into subsections using Dff test modes. and other sampling circuits will be discussed in Chapter 9. Since Dff allows portions of sampled channels to be reduced Filter input (test mode) TES PGA Oi sa Low-pass filter S.as illustrated in Figure 8.1 to be isolated from the rest of the sampled channel for more thorough testing. . amplifiers.1. DACs.. Channels including ADCs. we will seein Chapter 14. single-ended to differential converters. bus OfT for a OAC mixed-signal 249 . differential to single-endedconverters." However.1.

Finally. it is worth reviewing the basic characteristics of logarithms. To make accurate AC measurements with general-purpose digitizers and arbitrary wavefonn generators (A WGs). Focused calibrations can be used to compensate for the various measurement errors inherent in the general purpose A WGs. 8. Simultaneousmeasurementssave test time and thereby reduce production costs. analog channel testing is extremely common in mixed-signal device testing. common test techniques. The following is a quick review of logarithmic properties. digitizers.) for each test. 8. We will examine the definition of each type of test. signal rejection. The test definitions in this chapter are all based on the assumption that the signals to be sourced or measured are voltages. A principal advantage of DSP-based testing is that many of the parametersdescribed in this chapter can be measured simultaneously.2 Types of AC Parametric Tests Analog and sampled channels share many AC parametric test specifications. Most logarithms in the test and measurementfield are based on loglo calculations. In this chapter. Most of these specifications fall into a few general categories. this chapter will concentrate only on DSP-based methods of channel testing. Each of these categories will be discussedin the sections that follow. DSP-based testing is the primary technique used in high-volume production testing of mixed-signal devices. The analog tests described in this chapter will represent at least half of many mixed-signal test programs. the causesand effects of parametric failures. and common measurementunits (volts. but one that will suffice for now. Some fornl of voltage-to-current or current-to-voltage circuit will be needed in caseswhere the DUT produces AC current outputs or requires AC current inputs. Some circuits operate with currents rather than voltages. phase. Conversion from voltage ratio to gain in decibels G(dB)=20 IOgIOI~I=20 loglolG(VjV)1 (8. having no gain errors at any frequency. As previously explained in Chapter 7. including gain. distortion. and noise. In Chapter 10 "Focused Calibrations. decibels.1. we will assumethat the tester's digitizer and A WG are perfect. proper use of software calibration is often required. ATE testers are typically unable to measure or source AC currents directly. etc.250 An Introduction to Mixed-Signal Testand Measurement IC to analog channel subsections.3 Review of Logarithmic Operations Since many of the parametersin this chapter will be expressedin decibels.1) . and other instruments in an ATE tester.1. It is critically important for the mixed-signal test engineer to gain a solid understanding of analog channel testing." we will examine the focused software calibration techniques for a variety of DC and AC measurements. This is a naive assumption at best. Although many analog channel tests can be measuredwithout DSP-based techniques. common test conditions. an example of each test will be presented to clarify test definitions and techniques.

0 resulting in 20xlog(8. Analog ChannelTesting 251 Conversion from gain in decibels to voltage ratio G(VjV) = '#. 4 = 12.04 dB = -6. a power ratio of2 is equal to 3. i. 100 = 40 dB.02 dB.06 dB.5 resulting in 20xlog(0.0) = 18. 1/1000 = -60 dB. 6. ' 8.5) = -6. etc. 1/10 = -20 dB. 8 = 18.2) Conversion from a ratio of squared voltages 10 loglo (X2) = 20 loglo (x) to obtain to gain in decibels. Multiplying ratios is equivalent to adding decibels: 2. .01 dB. etc.J2 = 3.01 dB.02 dB.0/4. 1/2 = -6.0 = 0. leading to G(dB)=10 10glo(~)=10 10glo~ (8.0 = 8. since they are used frequently in test engineering.3) Converting from power ratio to gain in decibels. 2 = 6.02 dB -12.06 dB etc.1 Absolute Voltage Levels Absolute voltage levels are perhaps the simplest AC parameters to understand.04 dB.2 GAIN AND LEVEL TESTS 8. or equivalently. but they can be among the most difficult parameters to measure accurately using a general-purpose digitizer. 1000 = 60 dB. 1/.Chapter8 . Most electrical engineers are familiar with the use of bench equipment such as an oscilloscope or an AC voltmeter.e. we first make use of the fact that power is given by p= V2/R.0 x 4. I JI: I =1020 G(dB) (8.J2 = -3.) 1 = 0 dB. 1/100 = -40 dB.06 dB. Dividing ratios is equivalent to subtracting decibels: 2. The absolute voltage of a test tone is simply the RMS voltage of the signal .04 dB = 18. 6.02 dB + 12. we use G(dB)=lO 10glo~=10 IJI: r Jl:2 I~I 10glo-'2- ~ (8.2.02 dB. etc. 1/4 = -12. or equivalently. 1/8 = -18.04 dB.02 dB. Power ratios are half thesenumbers.4) Common voltage ratios and their dB equivalents (It is worth memorizing these ratios and their decibel equivalents. 10 = 20 dB.01 dB.06 dB.

resulting in an absolute voltage level at the filter output that is totally wrong. For example. It is aggravating to ask an en¥ineer to measure the voltage at the output of a differential circuit. A clean sine wave input may become clipped very badly by the defective filter. distortion. Spectrum analyzers offer a more frequency-selective voltage measurement capability. Electromechanical relays are often added to the DIB board to I facilitate the removal of loads from DUT outputs. and other test tones to be easily eliminated from the RMS measurement. including noise. and dBm (decibels relative to 1.0 mW at a specified load impedance). dBV (decibels relative to 1.252 An Introduction to Mixed-SignalIC T~stand Measurement . by contrast. RMS voltmeters and oscilloscopes.or RMS? ~ . The purpose of an absolute level test is to detect first order defects in a circuit. It is critical for a test engineer to be able to communicate these units of measure without ambiguity.2. and grotesque clipping or other distortion.2). Absolute voltage level test detects gross circuit defects quickly.Q in parallel with 500 pF. but they usually fall into a few common categories. Energy at other frequencies is eliminated from the measurement. then the DAC's AC output amplitude will likely show a 5% absolute voltage level error as well. Defective low-pass filter rvyv Clipped output signal Input signal Figure 8. DSP-based measurement techniques allow noise.~ Loading conditions can be very important to many AC and DC parametric measurements. such as resistor or capacitor mismatch. Device data sheetsusually list a specific loading condition or a worst-case loading condition. As a second example.. Absolute levels may be specified in RMS volts.the load must be removable so that tests like continuity and leakage can also be performed on the DUT output. distortion. If a buffer amplifier is designed to drive 32 . Obviously. then it makes no sense to test its absolute level in an unloaded condition. peak-to-peak.2 V. The test engineer must design this load into the device interface board (Dill). peak volts. When dealing with differential inputs or outputs. peak-to-peak volts. if the DC voltage reference for a DAC exhibits a 5% error. Absolute voltage level tests are a good way to find grossly defective circuits very quickly. Generally. the test engineer must determine the worst-case loading conditions for a given output and test AC parameters using that loading condition. I Units of measure for absolute level tests vary somewhat. In most cases." Does the answer refer to a single-endedor I differential measurement? Is it peak. evaluated at the test tone's frequency. :~ . which the output must drive during an absolute level test. but they are not always as accurate as RMS voltmeters in measuring the absolute voltage level of a pure sinusoidal signal. and other test tones. under test. each of these measurement units can be defined from either a single-ended or differential perspective (Figure 8. including absolute voltage level tests.0 volt RMS).3). only to get the reply "1. it will also exhibit very high harmonic distortion as well. Absolute level specifications can be applied to any single-tone or multitone signal. consider a low-pass filter having a defective op amp (Figure 8. measure the total signal RMS. DC reference voltage errors.

414 V RMS.0 V Peak. single-ended. Therefore.3.0 V Peak-to-peak 0. What voltage level correspondsto 0 dB? The decibel unit representsa ratio of values. . differential 4. When referring to a single-ended signal.0 V Peak-to-peak. single-ended 2.0 V I - AM ~g~i~ Gain=2 ~ 253 I1. Many times. as shown in Figure 8.707 V RMS. correlation errors between the bench and ATE tester turn out to be simple misunderstandings about signal level definitions. and as such it is inappropriate to refer to an absolute voltage level using decibels. Decibel units. Decibel units can be abusedas well. and single-endedreference levels are always used when measuring single-ended signals. dB units do not require a singleended/differential notation. we shall specify the measurementtype explicitly in this text to avoid confusion. must include a definition of the 0 dB referencelevel. single ended 0. Differential reference levels are always used when measuring differential signals. differential 1.p- -II Chapter8 . differential or 1 V peak. differential Figure 8. single ended 2. Nevertheless. it is acceptableto drop the single-ended / differential notation since there is no ambiguity. Analog ChannelTesting 1.707 V RMS Output signal: 1. differential. A signal level of +3.oV - Inputsignal: 1. Example8. Equivalent voltagemeasurements single-ended differential for and signals. But when referring to a differential signal. such as 1 V RMS. or decibels relative to I V RMS.0 V Peak-to-peak.4.calculate the signal amplitude in dBV.7 dB is meaningless. A common point of reference is 1 V RMS. the measurementis expressedin dBV. when used to specify absolute levels.0V - I JW I1.0 V Peak. Design errors can even be introduced if a customer specifies a differential signal level in the data sheet and the design engineer misinterprets it as a single-ended specification.becauseit has no point of reference. it is imperative to specify the measurement type. When this definition of 0 dB is used.1 I The positive side of a differential sine wave has a peak amplitude of 500 mY.0 V Peak 2. Absolute voltage levels must be specifiedusing a clear level definition. Assuming the negative side is perfectly matched in amplitude and is 180 degreesout of phase.

Example 8.).0 V RMS. We rely on the fact that a sine wave always has a peak-to-RMS ratio qf 1. but other times it is tied directly to the dBm unit (i.0. . -30 dBm at 50 . 0 dBm is the voltage corresponding to 1 mW of power dissipation at a particular load impedance. A specified load impedance must always be linked to the dBm unit.0 V RMS I resulting in signal level (dBV) =20 10glo \ 0.707VRMS 1.2 Convert a 250-mV single-ended RMS measurementinto dBm units at 600.singleended.0 mW). we convert RMS volts to dBV using the equation I RMS signal level . we start by converting the single-ended peak signal into differential RMS units. differential Next.. 11 1(dBV) =20 1 sIgna eve oglO 1.0. differential.414 (square root of two) 500 mV peak.4. Differential waveat 500 mV peak.0VRMS I =-3.707 V RMS.254 An Introductionto Mixed-Signal Testand Measurement IC WVI {::z= g~~~ - JW1 500 mV 500 mV Figure 8.. since different load impedanceswill dissipate different amounts of power at a given voltage level. single-ended = 1. differential = 0. Sometimes the load impedance is specified in a note in the data sheet.e.01 dBV Another commonly used absolute voltage unit is the dBm (decibels relative to 1.0 V peak. sine Solution: Since we need to compare this signal to 1.

this valuein dBV units.3162V. single-ended signal into dBV units.01dBV.absolute voltagelevelsareusuallymeasured using a generalpurpose digitizer in conjunctionwith Fourier analysis(i.4.05 dBV.2. differentialsignalinto dBm units at 50 Q.-15.Converta I-V RMS.Chapter8 Solution: . ADS. 0.133643 What is the amplitudeof this tone?What is its RMS value? Express V. -13.. Convert a I-V peak. differentialsignalinto dBV units.1.-3.3. +6. On a mixed-signal ATE tester. ADS.823 dBm at 600 Q ImW Exercises 8. To measure . An FFT analysis reveals that a particular tone has a spectral coefficient of -0. 8. Analog ChannelTesting 255 It is first necessaryto convert the voltage level to a power level using the equation power V2 =R Then the signal power is compared to the I -mW referenceusing the equation 10 10 glo ~ mW I The total equation is therefore signal level (dBm) ( ) = 10 10g10 (~ ImW ) Converting 250 mV signalinto dBm at 600 Q the signallevel (dBm) =10 loglo [ (250 mV)2/600) =-9. ADS.Converta I-V peak-to-peak. Ans. Digitizers are often capableof measuringeither single-ended signals or differential signals. DSP-based testing). 0.99dBm 8.2866-j0.2236V. 8.e.01 dBV.

0 VN).2 Absolute Gain and Gain Error In analog channels. When working with decibels. Absolute gain and gain error tests are well suited to the detection of gross functionality errors like dead transistors or incomplete signal paths.6) Often a channel's gain is specified using a minimum and maximum absolute gain.036 VN). The instrumentation amplifier converts a differential input signal into a single-ended signal before it is measured.04 dB (4. a channel's gain is specified in terms of its error relative to the ideal absolute gain.145 VN). This parameter is called gain error. mismatched resistors in an op amp gain circuit lead to gain errors. gain error is defined as the actual gain in dB minus the ideal gain GIDEAL dB (since subtracting logarithms is equivalent to dividing in ratios). In audio circuits. the digitizer uses an instrumentation amplifier at its front end. in volts/volt. the distortion caused by gain errors can lead to corrupted data bits. Gain error AG is defined as the actual (measured) gain of a channel.31 dB (or equivalently. Sometimes. a channel may have an absolute gain of 12. Extreme gain errors can also lead to clipped (distorted) analog signals.2. Distortion in turn causesan error in . Its gain error is therefore 12.0 VN = 1. Excessive gain errors can lead to a number of system-level problems. In data transmission channels.04 dB = 0. Gain errors are frequently the result of component mismatch in the DUT. then the test engineer must capture each side of the signal separately.35 dB . but its ideal gain should be 12. Distortion can be introduced if the gain error or offset of the signal causesthe circuit under test to clip either the top or bottom of the test signal. While absolute gain and gain error can be specified using either VN or decibels.256 An Introductionto Mixed-Signal Testand Measurement IC differential signals. The reason a full-scale signal is not used is that it might cause clipping (harmonic distortion). Gain tests are commonly performed at a signal level below the maximum allowed signal level in a channel. AG(dB) = G(dB)-G1DEAL(dB) (8.7) For example. absolute gain is simply a ratio of output AC signal level divided by input signal level at a specified frequency G=~ ~n Absolute gain is frequently converted from V N units to decibel units using the formula (8. The two signals must then be combined mathematically by subtracting the negative signal from the positive signal.using either two digitizers or using the same digitizer twice. gain error can result in volumes that are too loud or too soft.5) G(dB) =20 logJoIG(V/V)1 (8. though. If a digitizer lacks the capability to measure differential signals. 8. 4.35 dB (4.145 VN /4.12. For example. gain error is usually specified in decibels. divided by its ideal (expected) gain.

~ OUT low-pass filter OUTP OUTN J" ~ ~~-.5). The FFT of the captured waveform shows a signal amplitude of 1.5. 256 samples ~ OUT low-pass filter OUTP °UJN .3 A tester's A WG sources a sine wave to a low-pass filter with a single-ended input and differential output. In audio circuits.-I ' Chapter8 . 1024 samples 1.s very commonly average human ear IS maximally sensitive near 1 kHz. What is the frequency of the test signal? Which spectral bin in the FFT of the output signal most likely showed the 1.. since energy from the test signal is transferred into distortion components.025 V RMS Figure 8.6. since the Example 8. A separatedistortion test can be performed at full scale to determine the extent of clipping near the full-scale signal range. The output FFT shows a signal amplitude of 1.025 V RMS signal level? Assuming the digitizer is perfectly accurate in both sampling configurations. .50 dB.[~J~' Digitizer FFT 1. i.J: ~ ~~-+[~~:~~' Digitizer 16 kHz sampling rate. A digitizer sampling at 8 kHz captures 256 samples of the sine wave at the input to the filter (Figure 8. Analog ChannelTesting 257 the absolute gain reading. The digitizer is then connected to the output of the filter using electromechanical relays (Figure 8. ~ l-kH~ test tone. The digitizer captures 1024 samples of the output of the filter (differentially) using a 16-kHz sampling rate. What is the gain error of the filter at this frequency? Is the filter output too high or too low? Solution: 8 kHz sampling rate.25 V RMS at the thirty seventh FFT spectral bin. Sampling systemconfiguration duringLPF inputmeasurement.6). specified in the data sheet. what is the gain (in decibels) of the low-pass filter at this frequency? The ideal filter gain at this frequency is -1. gain measurementsare often performed a few decibels below full scale (typically 1 to 3 decibels below full scale). Gain and gain error tests are often tested with a single test tone.025 V RMS in one of the spectral bins. rather than a multitone signal. Sampling systemconfiguration duringLPFoutputmeasurement. Since we want to be able to distinguish between gain errors and distortion errors.25RMS V FFT Figure 8.

Gain tracking is often measuredin 6-dB steps (factors of 2) for characterization.). usually the O-dB level of the channel.8) Ideally.2.3 Gain Tracking Error Gain tracking.25 Hz/15. The reduction of levels saves considerable test time. The test frequency is therefore 37x31.25 Hz. Any signal energy falling in any other FFT spectral bin is therefore either noise or distortion. The number of steps is usually reduced to three or four levels after characterization of the device identifies which levels are most problematic.50 dB) filter output is lower than it should be. the output signal should also appear at 1156. the digitizer samples at 16 kHz and captures 1024 samples. Gain tracking error is also introduced by the quantization errors in a DAC or ADC channel.724 dB . But small amounts of nonlinearity and other subtle circuit defects can lead to slight differences in gain at different signal levels. the digitizer samples at 8 kHz and captures 256 samples. . and then measuring the gain at other signal levels (+3 dB.25 Hz = 1156. or gain tracking error. Thus gain tracking errors in a quantized channel are most severe at low signal levels. the quantization errors become a larger percentage of the signal. When sampling the input signal.25 Hz. When sampling the output signal.(-1. The gain is calculated using a logarithmic calculation as follows G ( dB ) =20 10 ~ glO V 1 1 =20 10 glO 1.625 Hz. -12 dB. regardless of the signal level (unless of course the signal is high enough to cause clipping). Since the output of the filter must occur at the same frequency as the input. is defined as the variation in the gain G (expressedin dB) of a channel with respect to a reference gain GREF (also expressedin dB) as the signal level Vin changes. The FFT spectral bin containing this signal energy must therefore be located at 1156.258 An Introduction to Mixed-Signal Testand Measurement IC First we have to understand our sampling systems. This sampling system results in a fundamental frequency of 16 kHz / 1024 = 15. although V N would also be an acceptable unit of measure. Gain tracking is calculated by measuring the gain at a reference level.724 dB In The gain error is therefore equal to -1. ~n = (dB) (8. A perfectly linear analog channel has no gain tracking error.224 dB. This results in a fundamental frequency of 8 kHz / 256 = 31.625 Hz = spectral bin 74. This means that the 8. Gain tracking error at each level is calculated by subtracting the reference gain GREF (dB) from the measuredgain G (dB) corresponding to that level. As the signal level in a DAC or ADC quantized channel falls. = -0. etc. a channel should have a constant gain.25 Hz. -6 dB. dG(dB) G(dB)-GREF vs. Gain tracking error is almost always specified in decibels.25 V 1 ~~ 1 =-1.

0 dB to -54.03 dB ' -0.09 dB Signal Level Gain Error ~G .05 dB gain tracking error from 0. Absolute Gainsfor GainTrackingMeasurement Signal Level 0 dB (500 mY) +3 dB Absolute Gain 0.04 dB -0.1.05 dB -0.00 dB -0. Table 8.25 dB at a +3. resulting in a series of absolute gain values.00 dB -0. gain tracking error is referenced to the gain at the O-dB signal level.ogChannelTesting 259 The data sheet for a single-ended analog voltage follower defines a 0 dB reference level of 500 mY at the voltage follower input. To convert each absolute gain into gain tracking error.1.01 dB -30 dB -0.0 dB signal level.02 dB) from the absolute gain at each level.02 dB 0.0 dB signal level and :to. The gain tracking specification for this device calls for a gain tracking error of :to.03 dB -30 dB -36 dB -42 dB -48 dB -54 dB -0.05 dB -0.01 dB -0.02 dB (reference gain) -0. Table8. Calculate the input signal level at -54 dB.07 dB Solution: We convert each absolute gain measurement into a gain tracking error measurement using the absolute gain at 0 dB as the reference level.02 dB Signal Level Absolute Gain -6 dB -12 dB -18 dB -24 dB -36 dB -42 dB -48 dB -54 dB -0.02 dB -0.2.Example 8.4 Chapter8 .06 dB -0.04 dB -0.18 dB (slight clipping causes test tone attenuation) 0.00 dB (by definition) +3 dB -6 dB -12 dB -18 dB -24 dB -0.1111. In this data sheet. we subtract the reference gain (0.07 dB -0.20 dB 0. Anal. Gain Tracking Errors Voltage for Follower Signal Level 0 dB (500 mY) Gain Error ~G 0. The gain tracking errors at each level are listed in Table 8.2. The gain error of the voltage follower is measured at each of the signal levels in Table 8.01 dB 0. Calculate the gain tracking errors at each level and determine whether or not this device passes the gain tracking test.

What is the gain error of the channelat an input level of 3. If its lowest gain setting is 0 dB. An FFT analysisreveals that the input and output signals have spectral coefficients of -0.. 1.2866-j0. 0 dB. and the gain step size from each gain setting to the next. Using the gain expression Exercise8.5 dB.260 An Introductionto Mixed-Signal Testand Measurement IC . 8.. and-12 dB. whenthe O-dBreference level corresponds to a 100-mVRMS input level? Ans.0 V RMS? to Ans.1 JI.5 dB. Ans.0 V RMS if the ideal gain is 1 V N? Whatis the gain errorwhen theinput is increased 5. For example. 8.11VN.044010 respectively. then it should ideally be programmable to any of32 different gains: 0 dB. are usually tested at .5 dB.6.2. the gain range in this example should be 46.5 dB from each gain step to the next (Figure 8.998mV RMS Exercises 8. 3. 1.0 dB.05 dB at all signal levels lower than -30 dB.7. 1. determine gain tracking errors at input in the levelsof 3 dB. The gain of an amplifier is measured with a I-kHz tone test. The absolute gain at each step in a PGA' s gain curve is often less important than the difference in gain between adjacent steps.133643 and 0. . 1 VN. a total gain difference between the highest and lowest setting. PGAs are commonly used as volume control circuits in cellular telephones.Whatis the gainof this amplifier? V. televisions. 4.6.. The gain range is defined as the highest gain (dB) minus the lowest gain (dB).7). consider a 32-step PGA that has an ideal step size of 1. Thegainof an analogchannel assumed be described the following equation is to by G=0.0709dB. Ideally. 8. like other gain specifications.. -0. -0. -0.0383dB. PGA gain specifications.-O.313150-j0. 0.0470dB.Ol V.46.11111111 This voltage follower fails the specification limits of :to.5 dB. -3 dB. -6 dB. The signal level at -54 dB is calculated using the formula -54 dB signallevel = OdBlevel x 10-54dB/20dB=500mVRMS 10-54dB/20 x = 0.9+0.0274dB. 0 dB. .. etc.4 PGA Gain Tests A programmable gain amplifier (pGA) can be set to multiple gain settings using a digital control signal.5. PGAs are often specified with an absolute gain at the first setting.15VN.

Programmable amplifier gain gain curve. if the PGA's gain is controlled by a sum of five binaryweighted resistors. For example. yielding better repeatability in the measurement.5dB per step 5 10 15 20 Gain setting (0-31) 25 30 35 Figure 8.3.7. since the change in output level is equal to the gain step size regardless of any gain errors in the digitizer or A WG. and gain range can all be measuredby setting the PGA into each of its 32 settings and measuring the output voltage level divided by the input voltage level. Although it is possible to measuregain steps in this manner. assumesuperposition is shown to be valid in a 3-bit PGA (8 gain stages)with 1. This eliminates the need for a focused calibration process. Measuring the gain at each major transition yields the gain measurementsin Table 8. it is probably best to adjust the input level at each step to produce a fairly constant output level at least 3 dB lower than the full-scale output level. This second technique avoids clipping while producing a strong output signal level at all gain settings.01000. each controlled by one of the PGA's control bits. The absolute gain of each step can be measured by leaving the input signal unchanged and observing the change in output voltage. 00100. Remember that strong signals are less susceptibleto noise. and 10000.00010. I L I .00001. then each step must be measuredindividually (since anyone resistor may be defective). such as 1 kHz. It is worth noting that the 32 gain measurements could potentially be reduced to only 6 measurements. assuming the PGA is well designed. This partial testing approach requires that superposition is proven to be a valid assumption through characterization of the PGA. Analog ChannelTesting 261 250 20 15 Gain (VN) 100 50 0 -50 0 PGA -1?Gain setting 1. This corresponds to the gains at 00000. The absolute gain. The complete gain curve can be calculated by adding the gains in a binary-weighted fashion. a particular frequency.Chapter8 . then only the op amp and the five resistor paths need to be tested.5-dB gain steps. However. If the PGA is designed with 32 individual resistorsin the op amp gain circuit. gain step size.

25 dB + 6.5-dB setting (101) 9.6 lists the absolute gain at each PGA step.25 dB = 4.4.. Calculated PGAGains Gain Setting 4. The output response at each of the 8 gain settings is listed in Table 8.01 dB = 7.01 dB = 9.01 dB = 10. Calculate the gain range.5-dB setting (Ill) Calculated Gain Gain = 0.48 dB + 3.the IC design engineer can reduce the test requirements from eight measurements to four. Is superposition a valid assumption for this PGA? Is it safe to modify the test program to measure only four gains and calculate the other four using a binary-weighted mathematical approach? Solution: Table 8. The remaining four measurementscan be calculated in a fraction of the time it would take to measure them explicitly.48 dB + 6. Calculate the gain step size at each transition.0-dB setting (110) 10.5 dB Gain = 0.5 A single-ended 3-bit PGA is stimulated with a constant 100-mV RMS sine wave input at 1 kHz.01 dB + 1.01 dB The remaining gains can be calculated using superposition of the measured gain steps (Table 8.5. " .3. Measured PGAGains ~ Gain Setting Measured Gain 0.48 dB + 3.01 dB + 1.25 dB+ 6. The test engineer should get involved early in the design process to suggest such architectural features.01 dB 1.74 dB Gain = 0.) The binary-weighted PGA is an example of a subtle form of design for test (Dff). I = 20 loglo I Vout 100mVRMS ! .4). .27 dB Gain = 0.25 dB 6.0-dB setting (010) 6.. Table 8. calculated using the formula G( dB) =20 loglo I ~ J-:.01 dB + 1.. Calculate the absolute gain at each gain setting.I Example 8.75 dB "" "\.48 dB L ~ ~ O-dB setting (000) 1. By choosing a design architecture that is based on a weighted structure with excellent superposition characteristics.01 dB + 3.5-dB setting (001) 3. or at least make the test impact of such design choices known to the design engineers.5-dB setting (011) 7.262 An Introductionto Mixed-Signal Testand Measurement IC Table 8.0-dB setting (100) 3.

48dB Gain Setting 6.87mV RMS 334.53 dB = 1. PGA Output Voltages with 100-mV Input Output Voltage 100. we did in Table8.53dB .4.97dB.95dB-l. Analog ChannelTesting 263 Table 8.5dB 3.50dB Table8.4.95dB 4.5 dB to 6.53dB 2.5 dB to 9.53dB 8.97dB 10.48dB = 1.5dB 1.52 dB-O.5 dB Chapter8 .5 dB 7.5dB Gain StepSize 1.57dB 8.95dB = 1.5.0 dB 10.5 dB 9.0 dB 4. Table8.0 dB 9.7.96mVRMS Table8.5dB MeasuredGain 6.5.0 dB to 10.06mVRMS 280.0 dB 3.5dB Gain Setting 0 dB 1.0. as .0.5-dBgain measurement.26mVRMS 140.8.53dB Gain range is calculatedby subtractingthe O-dB gain measurement from the 10.5dB Output Voltage 200.44dB 10.5.0 dB 6.52dB If we calculatethe gains at 4.calculated taking the differencein gain ~etween by adjacent steps.56dB 7.6.0 dB 10.45mV RMS 239.5dB to 3.97dB = 1.53dB 6. 7..5 dB 4.6.42dB 4.5 dB 9. PGA Measured Gains MeasuredGain 0.04dB = 1.50dB .04dB .5 dB using superposition insteadof actual measurements.53dB 2. gainrange = 10.57dB .0 dB to 4.-Gain Setting 0 dB 1. .OO dB = 10.00dB = 1.0 dB 7.44 RMS mV l67.7.we getthe resultsin Table8.0 dB 7.50mVRMS Gain Setting 6.2.5dB 3.0 dB 4. and 10.8.48 dB .0 dB 1. 9.04dB 7.7 lists the gain stepsizes.57dB = 1. PGA Gain StepSizes PGA Transition 0 dB to 1.0 dB to 7.00 RMS mV l19..

04 dB = 10. . Exercises 8.99 dB 0.043 V RMS in the one hundred eleventh spectral bin. .00 dB + 1.95 dB = 4. however. An analog channel with a differential input and differential output has an ideal gain of 6. +0.00 dB + 1. A .00 dB + 2.48 dB 0. This is one of the most common mistakes a novice test engineer makes. An analog channel is excited by a 100-mV single-ended sinusoidal signal.02 dB 0.43-mV RMS signal appears at the output when a 100-mV RMS sine wave is applied to its input? Ans. We would have to see superposition hold over at least three production lots (thousands of devices) before we would have confidence that we could change the test program to the faster superposition methodology. J Another reason this is a trick question is that we are looking at the results from a single DUT.8. An FFT analysis reveals a single peak value of 0.57 dB 8.48 dB 7.50 dB Calculated Gain using Superposition 0. We can account for the errors by tightening our guardbands (tightening the normal test limits by 0.95 dB + 6.04 dB = 7. ~ Error 0. then we cannot tolerate as much error and the superposition technique may not be acceptable.97 dB 10. . for example).53 dB + 2.0 dB 10.264 An Introductionto Mixed-Signal Testand Measurement IC Table 8.1055 dB.95 dB + 6.00 dB 0.52 dB The question of whether or not superposition holds and whether or not we can change to a superposition calculation instead of a full measurement process is a trick question for two reasons. . What is the frequency of the test signal? What is the absolute gain of the channel in V N? Ans.00 dB + 1.00 dB 0.02 dB Gain Setting 4. we would need to confirm with the design engineer that the PGA is designedin such a way that superposition should be a valid assumption. If the average device" performance is very close to the test limits.43 VN.5 dB 9. .53cdB+ 2.02 dB. First. Comparison Measured of Gainswith Calculated Gains. What is the gain error of the channel if a 202.02 dB.02-dB errors in the superposition calculations. ~ This gives us confidence that we are making a sensible decision about the expected j characteristics of the DUT.8. A digitizer captures 512 samples using a l6-kHz sampling rate.46875 kHz. : good engineer should never draw broad conclusions about device characteristics from a single DUT or even a limited sample of DUTs.5 dB Actual Gain 4. 8. Do we have test limits that are tight or loose relative to the behavior of the typical DUT? If the limits are loose.04 dB = 8. we have not specified the test limits. Also.9. we can probably tolerate the 0.5 dB 7.57 dB 0.53 dB + 6. 3. 0.

If so. meaning that all gains are measuredrelative to the circuit's DC gain. (8.03 dB Frequency response is usually measured using a coherent multitone signal so that all signal frequencies can be measured simultaneously. This approach allows a single-pass DSP-based test. The reason it must sometimesbe split is that the out-of-band components at the output of a filter may be extremely low in amplitude compared to the in-band components. in which the signal amplitude is varied.9) For this reason. a frequency responsetest measuresthe variation in the gain of a circuit as the signal frequency is varied.25-0. at two different amplification settings. frequency (8. Analog ChannelTesting 265 Frequencyresponseis similar to gain tracking in the sensethat it is a measurementof gain under varying signal conditions.8. the in-band and out-of-band components must be measured separately.25 dB to -0. Sometimes a frequency responsetest is used to measure the bandwidth of a circuit such as an op amp gain circuit to verify that its gain/bandwidth product is acceptable.11111111111. For example. Unlike gain tracking tests. an in-band test and an out-of-band test. the result can be unpleasant alias tones in the audio signal once it is reconstructedwith a digital audio playback DAC.5 Frequency Response Chapter8 . This amplification technique is especially useful if the nonamplified out-of-band componentswould otherwise fall below the digitizer's quantization noise floor. For example. Sometimes the test must be broken into two parts. a low-pass antialias filter removes high-frequency components from a digital audio recorder's ADC input.31) = 2 =-0. Ideally. If the antialias filter transfer characteristicsare not correct.9) are called relative gains. If a filter's transfer function is not within specifications. One signal frequency is chosen as the reference frequency and the gain of the circuit at that frequency is the referencegain. saving test time. Sometimes. . 'L The out-of-band components must sometimes be amplified by the front-end circuitry of the ATE digitizer or by a local gain circuit on the DIB board before they can be measured accurately. All other gains are measuredrelative to the reference gain AG(dB)=G(dB)-GREF(dB) vs. Frequency response is most commonly used to measurethe transfer function of a filter.2. it is often possible to measure the gain at a very low frequency (say. the reference frequency is 0 Hz. though. the in-band and out-of-band components should be measured simultaneouslyto save test time. Applying the sameamplification to the in-band componentsmight result in clipped signals. then the reference gain GREF the averageof these is maximum and minimum gains GREF (0. if a filter's absolute gain varies from +0. the gains computed according to Eq. When DC is used as the reference frequency. which saves test time. Sometimesthe reference gain is defined as the midpoint between the highest and lowest gain in the frequency response curve. 100 Hz) rather than making a separateDC gain test as described in Chapter 3. relative to a reference gain. the system-level consequences dependon the filter's purpose.31 dB acrossits in-band frequency range. I L r .

a DFT or FFT) on the waveforms collected at the DUT input and output.the DUT and tester must be allowed to settle to a stable state before valid data can be collected. or 50 mV RMS.e. The data sheet defines 1 kHz as the reference frequency. The settling time of an AC measurementis related to the signal frequency of interest and the filter characteristics of the DUT. the longer it takes to settle. For example. Example 8. Frequency response is calculated by first performing Fourier analysis (i. This precollection time is referred to as settling time. Specifications at intermediate points are determined by linear interpolation between the specified points. Measure the frequency responseof the filter. the tester's A WG must begin sending the input signal to the DUT for several milliseconds before the digitizer begins collecting samples. The gain at each frequency is then calculated by dividing the FFT's response to the DUT output signal by the DUT's input signal. The FFT allows a separategain calculation at each frequency of interest. Calculate the signal level of each input tone that will result in a combined signal level of 1.01-dB gain points must occur between 170 and 190 Hz (high-pass cutoff) and between 3550 and 3650 Hz (low-pass cutoff).. a 10-Hz high-pass filter is difficult to test in production because it takes many tens or hundreds of milliseconds to settle to a steady state. The phase of each tone is randomly selected to produce a signal with an acceptablepeak-to-RMS ratio. the higher the order of the filter. Also. and digitizer. "Sampling Theory" and Chapter 7. the longer it takes to settle.266 An Introduction to Mixed-Signal Testand Measurement IC . to produce a four-tone multitone signal with 100-mV RMS signal level.J4 . In general.8). . The reference gain (in dB) is then subtracted from each of the other gains to normalize them to the gain at the reference frequency. "DSPBased Testing. the amplitude of each tone is set to the desired total signal RMS amplitude divided by the square root of the number of test tones.0 V RMS. on a log/log scale. Therefore. The frequencies of the tones should be chosen so that they do not produce harmonic or intermodulation distortion overlaps. The absolute gain of the filter at the reference frequency is usually testedas a separatespecification to guaranteethat the filter's overall absolute gain is within specifications. the lower the frequency being tested. it is a good idea to get the DUT and AWG settling process started as early as possible in each test to reduce the test program's settling time overhead.") As in all AC measurements. To achieve a desired signal level. each tone must be set to I 00 mV RMS/. These upper and lower gain limits form the filter's gain mask (Figure 8.1111111 Frequency responseis usually measuredwith equal-level multitone signals in which the RMS amplitudes of the test tones are set equal to one another.4-kHz low-pass filter. Once the filter has settled and its output has been digitized. A WG. For example. A band-passfilter with a quality factor (Q) of 10 takes much longer to settle than one with a Q of I. (For a review of these and other considerations in making a multitone measurement. The data sheet also specifies that the -3.6 A band-passfilter is formed by cascading a 60-Hz high-pass filter with a 3. using a multitone signal. The filter's frequency response specification is shown in Table 8. For this reason..refer to Chapter 6.9. frequency response is simple to calculate.

/: t I r :I I ' I : I . I. 300 Hz 3000 Hz 3400 Hz 4000 Hz >4600 Hz 5 0 Upper limit :--::::::::::::::::::::::::__:: .. First.the 3-dB cutoff frequencies are specified. Second. ". ' .01 dB. I / L I' . "1. /' I.. we could sweep the frequency from 0 to 8 kHz in I-Hz steps.0 dB -14. the in-band responsehas to be guaranteedover a range of frequencies. I.5 dB -0.. !! I.0 dB 'I 1 .. so we have to find a compromise. I. :: ": " : .. I.~ ~~~ /" I I . and Solution: This specification points out a numberof problemswith frequency response testing.0 dB Freq. . I ' . ' . We do not have time to search for the exact frequency that results in a relative gain of -3.' :: I I . . Analog ChannelTesting 267 Table8. FilterGainMaskInflection Points Freq.' I. /: /.. '~t~l~~ ~ Chapter 8 . I .5 dB 0. (dB) -20 I. . I.28 dB Upper Limit -30 dB -25 dB -23 dB 0. but that would be unacceptably timeconsuming for production testing.8.~~ I. I... ' I . I I I I I I I - 25 ". A limited number of tones must be chosen. I. .t ower Iml k mas """'.I 5 mas -10 k \ / I. I.E~'\*%J.. 'I ' ' ' I I I I I I I I G aln ' - 15 I. . .IIII. I. I.. . I. I. .5 dB +0. : ..104 Figure8. Obviously. ' ' ' I . I. . .35 dB None None Upper Limit +0.5 dB -1. ~~ t Lower Limit -0. .9. I I I . I..0 dB -32. I. yet the data sheet does not specify which subset of frequencies should be measured in production. I I -30 -3 ~~ frequency! response: . Typical: ! : : L. Idealfilterfrequencyresponse gain mask. I. <10 Hz 50 Hz 60 Hz 200 Hz Lower Limit None None None -1. I.. .-- I I ' : I '' ' I I -40 10 ' I 100 Frequency (Hz) 1000 1.

9. . . " .. In this example. : I I I I I I Problem areas Problem : \ I I areas I I I I I I I : \ I I .01 dB and the other must be less than -3. " " \I.4430. We begin by choosing the problematic frequencies in the passband.. . . These correspond to the frequencies in Table 8. . Problem areas ~d_" . . I I . "Weighting Filters... . This is usually a procedure that the design engineer has performed prior to releasing the design into production. (Log/log interpolations are explained in Section 8." .7.2860. 1600. I I I I I I I I I I I I I I \19 ~~~~. 'I I " I I I I I I I . . 3460. I I ~ . Next we choose frequencies at the inflection points of the upper and lower masks. We can then interpolate between the gains at these frequencies (using a log/log interpolation) to find the approximate location of the -3-dB frequency. Since a 10-Hz tone would require a minimum of . the peaks and valleys of the in-band ripple are expected at 850. . The interpolation technique is more accurate. we can simply require that one gain must be greater than -3. . . . Problem areasin the filter frequencyresponse. .01 dB. We can see the potential problem areasby looking at a magnified view of the ideal frequency responseplotted against the gain mask (Figure 8. " .9. 190.9). and 3150 Hz. but the pass/fail technique is a bit faster.268 An Introduction to Mixed-Signal Testand Measurement IC .- " " I I I I I I I Figure 8. .': ". -~ . .2310. I I .corresponding to the peaks and valleys of the ideal frequency-responsecurve. The gains at these frequencies are the most likely to cross the upper gain mask. ... . Next we select frequencies at the center of the out-of-band side lobes. located at 100.-. One solution to the -3-dB frequency problem is to place two frequencies at the upper and lower limits of the -3-dB points (170. "I.. The solution to the first problem is to determine the frequencies that are most likely to causethe filter to fail the upper and lower frequency-responselimits of the filter through a detailed Monte Carlo or sensitivity analysis.") Alternatively. and 4860 Hz.-. ..-. I I . and 3560 Hz).

.. --..... ...... .. .-.-'. . L . ------~ -.... These "problem areas"are the logical choice for production testing._:.-.0 --..-_: 0 20m 30m 40m 50m 60m 10m Time (sec) BOm 90m 100m 110m 120m12Bm Figure 8.-:... 2860..I . ~ r .. Filterinputvoltageversustime.... .~ . 190.. 2310..-.--~ ..5 -3. ~ ..~. .... ----. ~ .10..L__. 3400.-.-.-:.Chapter8 . . and since the ideal characteristics are so far from the specified mask... ~ .-:..--~ .-'-- .5 .... This is another example where a robust design allows us to avoid costly testing. 4600. ' ....._J...1.. ..--. Clearly the choice of a limited set of frequencies is a complicated one.-. r ... .--. ......-.- L . The decision is based on the repeatability we can achieve with a single-pass test...L ... . . and 4860 Hz. 1000 (reference frequency). .I - - -. .0 1. 3460..0 r . For this example a single-pass test is probably acceptable.and 50-Hz tests from our frequency list._. .-... then we might worry about the measurementof such a small signal in the presenceof the much larger in-band si~als.0 V RMS at the filter's input.1-- . we have to adjust the frequencies of the actual test tones slightly to accommodate coherent DSP-based testing... When correlating the ATE tester results to measurementsmade with bench equipment.6 mV RMS to achieve a total signal amplitude of 1. but we can perform that characterization in a separatetest and later eliminate it from the production test list..~ . ~ .0 3. . ~ L- ... Analog ChannelTesting 269 ~.L .. .-:--.J . . ..JiG or 223.r -. If the lowest gain were instead -80 dB.. 850.. ~ r ' .. To calculate the desired signal level of each tone. - - -- --- - --- -.-:--..-. ~ L - . 300. .--~.-.. .. ~ r . Of course.0 -1... ~ ..-..0 V RMS/. _L- . i 2. we divide the total signal RMS by the square root of the number of tones.. 3150.I . ~ ...-.. Otherwise. .0 .r .. .. ..... ~ L- .. . .j . .5 -2. .. ' ..... ~ 10m . .. 1600.. We now have the following list of frequencies corresponding to the in-band and out-of-band regions of the filter: 60.--. 4..5 -1...~.r .-r . ..'-2... . the test engineer must communicate the exact frequencies used on the tester...--- -. . . .'.0 -2..--.I .. ..-'..-. .. differences in test conditions may introduce correlation errors between the tester and bench. 170.. -----. ..-. Of course. ~ - . since the lowest out-of-band gain specification is -32 dB. we should be prepared to verify that the average device does have this characteristic. The test engineer needsto work with the design team to predict which tones are most likely to cause filter response failures.. as explained in Chapters 6 and 7..-...... -3..-..-...0 -0.:- 0. 100... ~ -'- ..j . 200..~ ... . we will eliminate the 10.-.... ..5 3.. 4000. ~ r . .-.. .. : - - - - --. Each tone should therefore be set to 1.5 0....5 ' L .I - - - - - -'- - -- - '. ... 3000. 4430. " 100 InS of data collection time to capturejust one cycle. ..0 -.I - --'- - - - - - - -- - --- - - - -- -. We can either test the filter with this 20-tone multitone signal all Zitonce or we can split it into two tests. 3560. .5 1.j -4.

.--..-i ... .-- ~ .. ~ ~ .12. --- ~.-- "..--. .. : : :.. .01< ~ : -: : 0.--...5K 5. -30 ~ " -40 ..~- : ~ ---~ ---~ ... 2.--~ -50 ....11 shows the magnitude of the spectrum of the input signal.... -90 ~ -100 ..--~ --- . -- ~.-.-.--~ ..--. .. ---- :::: :.-- ~ .--- ~ .--. : ~.f -.. "---~ : ---~ " " .--~ -80 -90 -100' " .0K Frequency [Hz} Figure 8.. :- : : --~ ---~ .i .12 shows the magnitude of the spectrum of the digitized output. .--~ " -60 -70 ~:: ~ .--------~ -----: . : : : f ...i -20 ~-. 0 ~ -10 ~ '..11. 0 : -20 ~ :: .5K 4. digitized at a sampling rate of 16 kHz and 2048 captured samples.-3.:1... -i .5K 1.--~ :. ---~ ---~ .-.-.5K 2. " ." ::: . -110 -120 0 0.-- ~ ~ ~~- -: -j .. ..5K 2...5K 3.-....-- ~ . : -- : ~ : f : .5K ---~ .....-- .--:.50 ~ ".f .-.. " --- -30 ~-... ~ ..:11 3.0K 4.--~ .. :--.-. ~ -40 ~-. ~ ~ .--J :'" i.10 shows the 20-tone input signal.-:...5K 4... . i -J : : .-.-.. :: :.. -..0K ~- ::: : I~ : 1. ~ ".270 An Introductionto Mixed-Signal Testand Measurement IC Figure 8. ..--~ ~' .. : J ---~ ---~ ...~ ---~ : .0K 1... ~ : --~ --- : " ~:: J -. .. Figure 8. ~ ----- if... ~ . ". :: : ~ ~ -60 -70 -80 ~ .... Filter output voltage (dBV) versus frequency.. ~ : ~ : ~ .5K 5.-. ~ ~ . ~- -i ~. ~ : ~ .' .0K 4. : '.. Both plots have been converted to a logarithmic scale (dRV) so that we can see the low amplitude signal components (including noise) as well as the high ones.--~ --.. Filter inputvoltage(dBV) versus frequency.5K 1..-.0K Frequency [Hz} Figure 8. ~ : " ~ :: : ....-.-- f. " " . ~.-t .. Figure 8. -1.-. .- -i _: -110 ~ 0 :: -120: ." :::: ~'" : : : : ---~ ---. ---~ ---~ ---: : .- : : : ..... ~ ..--~ ..0K 3.0K 1...~....0K 2.'....." ~" :: :-- -: -i -.-:. : : : : ~ : -10 ." : ---~ .--~ -- .

0dB -32.151 dB 0.27 dB -33.0 dB +0.06 dB -1.280 dB -0.0 dB NA -3.) 0.50 dB +0.29 dB -4.44 dB -33.62 dB -4.853 dB -1.01 dB .82dB -32.10) The computed absolute gains and the frequency response(gains relative to the gain at 1 kHz) are listed in Table 8.50 dB -0.52dB -16.9.23dB -32.50 dB -0.00 dB -57. Analog ChannelTesting 271 The absolute gains are computed using the fonnula G( dB) =20 loglo I~I (8.72 dB Lower Limit -0. Note that this example filter failed in two places.50 dB -23 dB -13.Band-Pass FilterAbsolute Gainsand RelativeGain Measurements Frequency 1000 Hz (ref.50 dB -0.50 dB +0.50 dB +0. Table 8.097 dB 0. Resp.69dB NA NA NA NA -14.40dB -32.50 dB +0. corresponding to the lower mask problem areas in Figure 8.50 dB -0.168 dB -57.155 dB 0.002 dB -1.35 dB -3.098 dB -0.50 dB -0.292 dB 0.181 dB 0. Chapter8 .150 dB -0.1111111111~.0dB -32.01 dB 4000Hz 4430Hz 4600Hz 4860Hz -16.10.10.50 dB -0.017 dB 0.50 dB NA NA NA -3.266 dB 0.01 dB -1.) 60 Hz 100 Hz 170 Hz 190 Hz 200 Hz 300 Hz 850 Hz 1600 Hz 2310 Hz 2860 Hz 3000 Hz 3150 Hz 3400 Hz 3460 Hz 3560 Hz Absolute Gain 0.24 dB (interpolated) -3.21dB -75.0dB .87 dB -1.01 dB NA Upper Limit +0.128 dB 0.0dB -32.89 dB -1.013 dB -0.296 dB Fail -0.99dB -32.432 dB Fail -2.79 dB -5.46 dB -4.071 dB 0. NA 0.55 dB Relative Gain (Freq.013 dB 0. We can see from the enlarged view of the problem areas in the filter mask that the gains at these frequencies were going to be very close to failure.170 dB -1.50 dB +0.264 dB -2.38dB -75.018 dB 0.04 dB -2.50 dB +0.

What is the total RMS value of a multitone signal consisting of twenty-five tones having an RMS value of 100 mV each? ADS. If the mathematical frequency responsehas a limited number of independent variables that control its behavior.1 kHz? ADS.11.5424 0. Another technique for frequency responsetesting is to assume a perfect filter with a known mathematical frequency response.1 kHz 3. Also.1 kHz Input -0. The Fourier transfonn of the impulse responseis the filter frequency response. -2.13.3202.1002 -0.1747 dB. an impulse contains energy at many frequencies. Using log/log interpolation. What is the peak amplitude of each tone if they are all equal in magnitude? ADS.9999 Output -0. Therefore. frequency responsecan also be measuredby applying a narrow impulse to the circuit under test and observing the filter's impulse response.32 dB at 3400 Hz. 8.9252 dB.9180 . The advantageof this approach is that it gives the full frequency response.4181-jO. The problem with the impulse responseapproach is that it is very difficult to measurethe gain at anyone frequency with any degree of accuracy. the full filter transfer function can be - .jO.6286+jO.2294 + jO.2024 + jO. 0 dB. The small signal level makes the measurementvery susceptible to noise.7778 -0.5 V RMS.4 Hz. 8.2308 0.3.6636 0.1 kHz 2. since the energy contained in a narrow impulse i~ very small.0. An FFT analysis of the input and output samples reveal the following complex spectral coefficients: Tone 1. ADS. at all frequencies in the FFT spectrum. The frequency response behavior of an amplifier is measured with a multitone signal consisting of four tones.3966 -0.56 dB at 3000 Hz and -4. then the gain only needs to be measuredat a few frequencies.0134 + jO.0592 What is the relative gain (dB) of the amplifier at each frequency if the reference gain is based on the gain at 2.10.272 An Introductionto Mixed-Signal TestandMeasurement IC i : Exercises 8.1102 + jO. detennine the -3-dB frequency of a filter corresponding to a measuredgain of -1. An eight-tone multitone signal of 250 mV RMS is required to perfonn a frequency responsetest.8402 + jO. which interact with each other through distortion processes.12.888 dB.1 kHz 4. Using N equations in N unknowns. the gain at anyone frequency may be corrupted by distortion components from other frequencies. In addition to the traditional multitone technique. 125 mV peak. 8. and -5.

3. the amplitude of the kth tone is calculated according to [ f. the phase shift of the kth tone can be calculated using the formula tan-I ( -Im{X(k)} Re{X(k)} K+tan-I ) if Re{ X(k)} ~ 0 (8. then according to the development in Chapter 7. it can be calculated using the FFT results collected during the frequency responsetest.N/2 k =1.. the frequency responsetest often measures only the magnitude responseof a circuit.. In analog and mixed-signal testing. Assuming that the tester's FFT routine returns the complex coefficients of the discrete-time Fourier series in the form of a vector X. --- - . The phase information contained in the FFT results is frequently discarded because phase response is often an unspecified parameter. most testers include a DSP routine to convert the results of an FFT into polar notation (magnitude and phase). however. The polar conversion routines perform whatever corrections are necessaryto compute a correct phase shift.3 PHASE TESTS 8. If phase response is specified in the data sheet.. Why should we calculate the magnitude and phasesof all 511 complex spectral coefficients in a 1024-point FFT if only 10 of the phasesare of interest? A full polar conversion or polar FFT is an inefficient processthat can add unnecessarytest time. C To aid the user.. Although there are several different ways to approach frequency response testing. Although the built-in polar conversion approach is easier than doing the conversion manually. This technique works well for simple filters with wide design margins. The test engineer may find it more efficient to perform a manual polar conversion only on the tones of interest.1 Phase Response The transfer function (frequency response)of a filter or other analog channel is defined not only by the gain variations over frequency (magnitude response)but also by the phase shift variations (phaseresponse). it can be less efficient. Correspondingly.12) (bk = ( -Im{X(k)} Re{X(k)} ) if Re{X(k)} <0 .N/2-1 (8.11111111- Chapter 8 . Analog ChannelTesting 273 estimated from a limited number of gain measurements.11) where Re{X(k)} and Im{X(k)} denote the real and imaginary parts of the kth element of vector X. 8. coherent DSP-based testing is still the most common methodology for measuring the frequency response characteristics of a filter or other circuit in high-volume production testing. This technique has the advantage that only a few tones need to be measuredto predict the complete transfer curve of the filter. { ~Re{X(k)}2 + Im{X(k)}2 Ck= 2~Re{X(k)}2 +Im{X(k)}2 - k=O. but may not work as well with more complex filters having very tight specifications.

the output lags the input). a The phase shift at each frequency in a multitone test signal is calculated by subtracting the input signal phaseshift from the output signal phase shift. Example 8.e.. For example.11. The phase shifts can be calculated using a rectangular to polar conversion routine. Figure 8.Analog delayline producing -90 degreephaseshift (phase lag).12). along with the phasecalculated using Eq. The real and imaginary FFf results for the 10 digitized output tones are listed in Table 8. ~ _[~~J_e Iay line T= 1/4 P Delayed output signal Input signal Figure 8. using the same data collected while measuring the magnitude portion of the frequency response.39.14 shows the digitized representationof the input signal to the delay line. if ever. use a 1024-point sampling system with a 100-Hz fundamental frequency. Use random phase shifts to produce a peak to RMS ratio of approximately 3. This process can get very confusing. The phasesof the tones in this input signal were chosento produce a peak to RMS ratio of3..15. etc.ls analog delay line in I-kHz increments from 900 Hz to 9. All phase shifts can thus be measuredwith a single test. occur in practice. The test engineer has to account for this "wrapping" effect by adding or subtracting integer multiples of 360 degrees to the polar conversion results.). while a positive phase shift indicates the opposite.35:1. so we shall look at an example to illustrate the phasemeasurementprocess. For simplicity. use spectral bins 9.12. Polar notation is limited to a phase shift of at most :t180 degrees. Solution: ~ ~ " Figure 8. The real and imaginary spectral coefficients from an FFf analysis of the 10 digitized input tones are listed in Table 8.29. A negative phase shift indicates a positive time delay (i. we can calculate the real and imaginary components of the input and output signal of a circuit under test.e. a phase shift of -190 degreestranslates into a shift of + 170 degrees. line with a time shift of PI4 producing a phase shift of -90 degreesat a frequency of liP.35:l. and then correcting for any 360 degree wraparound. The digitized output signal is shown in Figure 8.13 shows an analog delay. Using multitoue DSP-based testing. Use odd harmonics so the time-domain signal will be symmetrical about the x axis (i.13. along with the calculated phases. 19. (8. The idea is to eliminate jump discontinuities in the phase behavior of the device as these rarely. 7 I ') ) Measure the phase responseof a 100-j.274 P An Introductionto Mued-SignalIC Testand Measurement H - . ~ - .9 kHz (10 tones).

.. Calculated SignalPhasesfor DigitizedInput Frequency 900 Hz i.207465 -0. ...0 -41. :.0 Subtracting input phases from output phases should yield the phase shift at each frequency. 275 ~ ~.9 kHz 4. ~ -~ 1. ~ : ~ : -~ .5 ~:~ ~ ~- Chapter ChannelTesting 8 Analog ~ : ~ : -.9 kHz 2.215668 -0.0 167.5 ~ -2. we have to account for the 360 degree ambiguity of the phase subtraction operation by first converting each phase shift to a value between -180 and +180 degrees. .286600 -0...0 103.0 -8.: --..0 3.-.071136 0. : 8m .252550 0_044010 -0.5 ' --1.0 -25.11... 11_-.--. -i : .9 kHz 7. : 4m : :.13)..238660 0.5 : - ~.... .0 ~ -2.0 225. -.. 4.223608 0..313150 -0.--- . --. . we either add 360 degreesor subtract 360 degrees .071136 Phase (deg) 231.-! -: :.0 133. : 7m : 8m ~ :..-i-..: :: ~ -~ -: ~ ~ ~ -.0 ~ -1 -L -j -: -i -: j.0 ' -1.. In the first correction step (column three in Table 8. Unfortunately.~ ~ .14.i.9 kHz 5.. Time (sec) I~ Figure8.1 ..-: -.i .0:---' 0.. --..--.0 167. To do this.308123 Imaginary Part 0. . --.308123 -0.133643 -0. ~ 3m ~ ~ .--: t~~~~~~-~i~~~:~~ ~t~~:::~ ~i~~:~~:~ ::::~~~~:-~j~:~:~~~~j~~~:~~:~:j:~~~~~~~j~~~~~~~~~t~~::~: 2..199009 -0. 1..071136 -0..0 ' -0..9 kHz Real Part -0. Table 8.. ~-.9 kHz 9. the polar conversion cannot distinguish between a shift of360 degreesand a shift of 0 degrees.-. --: : . : 5m t : .9 kHz 8..308123 -0.-! .--. ~ ..-. . : 10m ~ :. --' ~ 0. : : .--.5 ~ -i -~ -i : --.. The raw output-minus-input phase shift calculations and the results of the correction steps are shown in Table 8.13. ~ 9m -~ ~ .223607 0.0 ~ 0 ~ "---~ ~ 1m ~ ~ .245755 0.9 kHz 3. -: --: 1.---: -: . --.231275 -0. For this reason.190311 0.5 : -3..100-JlS delayline inputvoltageversustime. ~: -:: j -35 ~ " -4..0 -~---' -' --. : 2m ~ : .9 kHz 6. we have to correct the output-input phase calculations in a twostep process.-.: .0 233..

9 and caused by a a between discontinuities cannot the phase changes 3.---:-. 0 0 :. .-~. Then.12.-. . we see that there are several between the frequencies are distinguish of 1. 0 4.15.. .~...ls delay output line voltage versus time.-~--0 .190517 0. 0.. Table 8.~ ~--.-.9 since shift. ~ 0 ~-.~ 0 --~-- ~-..-.133008 -0.. -:.: : ~ 0 ' ~--.--.~-. --~--:--0 -: 0 ~ r . ~ ..9 kHz 9.-~ .276 An Introduction to Mixed-Signal IC Test and Measurement from each phase number to limit our phase shift answers from -180 to +180 degrees.~ .285237 -0.~ - r--.. .~. 0 .0 - . ..182579 -0.-: ~-0 :--.-..-:. ..-:. 0 0 0 0 . .5 r _3.-~ -.2 217.-.5 :--- -2. kHz. 0 ~-.~ :--..5m - L ' J '--L O--.: : .4 158.. 0 .~--.~.5m - ' J .0 ~ -: .9 kHz 3.---J 0 0 .5m - 305m - . 0 0 0 0 0 0 ~ -.. and the discontinuities mathematical 360-degree in the calculated wraparound effect. .. .-... ..r 0 ~ --.9 kHz 6. ~---: 0 0 0 -.. 0 ..4 215.--. ---.-:.---~ ~ 0 . 7. ~ ~ 0 : : ~ : : ~ ~ :: ~ ~ : ---: '0 : 0 ~ 0 ~ 0 : 0 ~ 0 : ~-. : .293618 -0.-~ --~-.~ ~ 0 ~---~0 0 : ~--.-:.-1 0 0 .005777 Part Phase (deg) -199.. polar calculations shift and a O-degree shift.. ..5 r.--:.9 -6.-. . 0 .:: . 8.5m -- 8. -. -- ---~.~..-.0 0 0 . .-..-.5m -.--~-0 .~....5'-... . Calculated Signal Phases for Digitized Output Frequency 900 Hz 1... 1...-. 0 0 -- 1..: ~---: : . . 0 0 0 0 0 3.-.1 ~.157590 -0. 0 0 0 . 0 ~- L O l L 0 0 .9 kHz 5. 0 . 0 .-. O . ~ 0 1 ~ 0 ~--. 0 0 0 0 .--~-0 ~ :--.9 kHz.9 and 5.--: .~ -. 0 0 -:.0 109.-... 100-J. :.314893 0.--~-0 . 5..-.1 179.-. 0 .5m - ' J J .-.-.--r. '- ~-.9 kHz Real Part -0. ~ .0 ~ 0 2.-1.~---.9 kHz 4.~--..~.-:. .-~ ..~---+--~ :--. .033096 -0.. 0 :--:--. 0.-:.--: 0 . In particular..9 kHz 2.. 2.-.-~.. 0 ~ l - r 0 -- :.5m -~ 6.~ 0 0 .3 150.-.0m . 4. .~ 0 .-.o : 0 : ~ ...298347 -0.0 :--- 0 : 0 _0- ~ ---.-:.~ 0 .---...298233 0. . . r 0 : ~---~ : :' . 0 - 10. 0 0 .~ " ~-. . - . ---~ 0 -1. .0 -3.316175 Imaginary 0.9 of Table These 4.9 kHz..: -~-- ~---.-0 0 ---~ ~ : ~---~ ~--~ :-..117421 0. 0 0 0 0 ~.0-.0 "..9 kHz 8.-:-.0 247. .. -:.0 0 ---:-0' --~. 0 --:.~ .1 '--0 .. 0 0 0 . 0 ~--... -. .252395 -0.-.258195 -0.5 -4.-. 0 -~- .~ : 0 ..r --. :--. j .13. 0 0 -:. ~-.-~ ---. 0' ~ ~-.-0 : :--. - - - -.--:. 0 0 . 0 .r 0 ---~ :--...~---~--.-. 0 0 .-.--~-0 .105152 -0. 0' . "0 -~ ~...9 kHz.: ..~ 0 0 . in the second phase and 5. we can see the discontinuity Observing 2.0 25..--..-0-.. .9 kHz 7. in the calculated phase shift between column 6. - - -- - - Time (sec) Figure8. . -0.-.--~ .~ .-... 0 ~ :' .5 2.. -:....5 ~ ~ : 0 :--.119020 0.0 1.9 and 4..5.. .292974 0..---~--..0 3.-~---~--.104827 -0. ..274162 -0. ' '0 -1.0 ~ -2.

9kHz 7.6 158.9 kHz 3.9-25=222. we either add or subtract 360 degrees from the wrapped result as needed to make the phase shift measurementscontinue in the correct direction.9 kHz 5.13) (8.3-133 = 82. we use a similar calculation. Actual Phase 900Hz 1.0-(-41)=258.0-167 = -173.2 225.1-103 -360 -360 -360 -242.9kHz 8.0=-31.1 9.4 (-8) = 117.4 215.In) :t360 Phase Adj.9kHz 2.13.0 Sometimes phasecalculations specifiednot in degrees radians.8 217.1 -173. Table 8.0 - -360 :'348.0 -137.not listed) and continues in a negative directionasfrequency increases.9 kHz 199.15) f(Hz) 360 degrees .0 247.0 6.0 .9 kHz 109.0 -208. taking the period (1/ f ) into account phase shift (sec) = period ( sec)x t/J(in degrees) 360 degrees = 1 x t/J(indegrees) (8.6 -66. The results of this correction processare shown in the last column of Table 8.7 -312.0 25.9 -6. we use the formula t/J in degreesor radians to phase shift in fractions of a phaseshift (fractions of cycle) = t/J(in degrees) 360 degrees or equivalently phaseshift (fractions of cycle) = t/J(in rad~ans) 2JC radIans (8.6 -277.9 kHz 179.14) To convert phase shift in degrees to phase shift in seconds.233 = -208. To convert phase shift cycle.9 kHz 4.8 -102.Chapter8 .0= -66. These numbers show a phase shift that starts at 0 degrees at 0 Hz (by definition .0 167= 12.9 = 47.but in seconds in are or or fractions of a cycle.3 150.13. PhaseCalculations Corrections and Frequency Phase Shift (Out .4-231.0 0 0 -360 -360 0 0 -31. Analog ChannelTesting 277 To compensatefor this 360-degreediscontinuity.

It is commonlydenotedas 1(1).17) 2ft !if where 8l/J is the change in phase shift expressed in either degrees or radians. . Many tone pairs can be measuredsimultaneously using DSP-basedtesting. Signal clipping is one potential problem with a circuit that exhibits poor group delay characteristics. then the peak to RMS ratio may change enough to causeextreme peaks. we have to measure the phase at two points that are sufficiently separated in frequency to allow an accurate measurement of phase change. It is defined as the group delay minus the midpoint between the maximum and minimum group delay in the frequency range of interest -rdistorlion(J)=-r(J)-~1~ (8.18) Group delay distortion mayor may not be a problem in the system-level application. -r(J) = (1/360)( dl/J/df). Instead. .but shifted in time (either delayed or advanced).16) f(Hz) 2ft radians 8. then the circuit will shift the various signal components relative to one another. Group delay is expressed in units of time. on the other hand. Group delay is typically measured with tone pairs centered around each frequency of interest.3.278 or equivalently An Introductionto Mixed-Signal TestandMeasurement IC . phaseshIft (sec) =penod ( sec x ) l/J(inradians) . In a simple delay line.which clip against the power supply rails of the analog channel. group delay is defmed as the derivative of phase with respectto frequency.2 Group Delay and Group Delay Distortion Group delayis a measurement time shift versusfrequency. The variation in group delay over frequency is called group delay distortion. In reality. The group delay of a delay line is therefore equal to the negative of the time delay through the circuit. This results in a change in shape as well as a shift in time.!-~~=~~~ f !if 360 !if (8. If. If different frequencies are shifted relative to each other. of Group delay is defined as the changein phase shift (fractions of a cycle) divided by the changein frequency (Hz) -r( ) = 8phase shift(fractionsof cycle) =-. 2ft radians I l/J(in radians) = x (8. Strictly speaking. This leaves the relative time shifts of the various signal components unchanged and therefore results in a signal that is identical in shape. the phase shift through a circuit is directly proportional to frequency. A constant group delay indicates a circuit that shifts each signal component by a constant amount of time. group delay varies over frequency. it is extremely difficult to resolve tiny changesin phase called for by the derivative operation.

and cellular telephones.hard disk drive read/write channels. -125.55. The midpoint is calculatedas the averagebetween -99.13.07.14.jO.11 ~.11)/2 -97.Groupdelay:-46.72and-96. -55.59~. Groupdelayis equalto the change phase(deg) dividedby 360xlOOO in degisec. (-99. -35.groupdelayerrorscanleadto corrupted data.12.8. -380. = Exercises 8. -47. . The phase shift (in degrees)of an analog channel as a function of increasing frequency appearsas follows from an FFT analysis: 0. Analog Channel Testing 279 Anotherproblemthat can arisefrom group delay distortionis incorrectdatatransmission in data communicationchannels. determine the phaseresponseof this amplifier (in degrees).-21. The frequency responsebehavior of an amplifier was measuredwith a multitone signal consisting of four tones.55~. -20.07.915~. -304. ADs. -72.13. Ans. Using the spectral data provided in Exercise 8. What is the phaseof this tone in degrees? Limit the phaseto a range of ::!:180 degrees. What is the unwrapped phase shift of the channel (in degrees)? Ans.70.-11. Also. An FFT analysis reveals that a test tone has a spectral coefficient of -0. -203. -415. -76. Groupdelay distortion at each frequencyis equal to the group delay minus the midpoint betweenthe maximumand minimum group delay.133643.2866 . determine the group delay distortion. -125. 56. in Solution: Groupdelay and group delay distortion are simple calculationsonce we have calculatedthe phase shift at eachfrequency. calculate the group delay of the amplifier. -165. -35.17.17.14.Chapter 8 . 8. Groupdelaydistortion:-17.16. 8.29.73. -155 degrees. 0. Frequency is change a constant is 1000Hz. The group delay and group delay distortionfor eachchange in frequency listedin Table8. 157.15. Using the spectral data provided in Exercise 8. ADs. 8.72-96.such as those used in modems.8 Calculate group delay and group delay distortion of the 1OO-~ delay line from the data the gathered thepreviousexample. -165. Example 8.54. -64. Since phasecarries important information in many data communication protocols.

Signal to total harmonic distortion is defined as the ratio of the RMS signal level of the test tone divided by the total RMS of the odd and even hannonic distortion components.6-{-208. such as clipping on only the upper or lower portion of the wavefonn.50 IlS -97. 7Ft.1 Signal to Harmonic Distortion Harmonic distortion arises when a signal passesthrough a nonlinear circuit. Ft is often referred to as the fundamental tone {not to be confused with the fundamental frequency of the sampling system.50~s -99. 4Ft.9) = -35.6) = -35. When passing a single test tone through the circuit under test. distortion can be measuredin parallel with absolute gain using the FFT results from the gain test.8)=-35.22 ~s -96.8~ 415 ns 135 ns -97. gives rise to both odd hannonics and even harmonics (2Ft. 6Ft.9 kHz 4.1 Group Delay -97. Since there are an infinite number of possible harmonics.6 -277.9 kHz and 6.9 kHz 5.0)=-35.0) = -35. 100-~ DelayLine GroupDelayand GroupDelayDistortion Calculations Test Tone Pairs 900 Hz and 1.0-{-173.78~s -97. the harmonic distortion components appear at integer multiples of the test tone's frequency.50 ~s 415 ns 8.0 -242.8-{-31. Harmonic distortion is often measured with a single tone test signal.4 DISTORTION TESTS 8. To enable complete characterization.4.6) = -35. the data sheet often calls out only a signal to second hannonic distortion and a signal to third hannonic distortion test.2 -348. but also integer multiples (hannonics) of the input frequency components.0)=-34. Signal-todistortion is often expressed in decibel units.1-{-IO2.9-{-277. similar to gain. 5Ft.).9 kHz 7. To save test time.7-{-242. Also.9 kHz and 4. the test engineer will often .9 kHz and 3. a sine wave at a particular frequency (specified in the data sheet).9 -208.9 kHz 6. the data sheet may callout a signal to total noise plus total harmonic distortion specification.14.0-{-66.280 An Introduction to Mixed-Signal Testand Measurement IC Table8.9 kHz and 7.11~s -97.9 kHz 8. Ft.9 kHz and 8.9 kHz and 5.781lS Group Delay Distortion 135 ns 135ns 415ns -1.Ffl. that is. The spectrum of the output of a nonlinear circuit includes not only the frequency components that appeared at the input.1 -173.1 -312.7) = -35. Distortion that is symmetrical about the x axis gives rise to only odd harmonics (3Ft.9 kHz and 9.78 ~s -97.2 -137.9 kHz Phase Change (deg) -66. etc.0-{-312.1) =-35.8~s 694 ns 1.).9 kHz 1.72~s -97.9 kHz and 2.9 kHz 2.2 -102.9 kHz 3. Asymmetrical distortion. etc. which covers all hannonic distortion components and all noise components simultaneously (any spectral component that is not signal is either noise or distortion).0-{-137.

Individual Spectral Components Are Expressed Termsof RMSValue. .Various Signalto noiseand distortionFormulae. H2 the RMS value of the second harmonic.. Analog Channel Testing 281 write a test program that reports all these permutations of signal to noise and distortion measurements..+H..2 .Chapter 8 . NoteThat OffsetIs Not Included Any of TheseFormulae.15.JHi+H..+Hs2+. This is a direct result of Parseval's theorem described in Section 7. in DC in Distortion Metric (VN) Signal to 2nd Harmonic Distortion (S/2nd) Signal to 3rd Harmonic Distortion (S/3rd) Signal to Total Harmonic Distortion (S/THD) Signal-tonoise Expression (dB) S H:- 20 loglo (H ) S 2 . and N is the RMS value of all the nonharmonic bins combined (noise will be explained in a later section).... . etc.2. Also note that the numberswill typically be positive since the signal is always larger than the distortion (unless the DUT is completely defective).... Note that we add RMS signal levels using a square-root-of-sum-of-squarescalculation.+H. S ':if:" 20 loglo ( S H) J S . VH2 +HJ +H4 +Hs +. 2 J 4 S 20 loglo ( S 1.2. The symbol S denotes the fundamental signal component expressedin RMS volts.2 .JHi+H. 2 ~(total signal RMS)2 -S2 20 loglo or ( 8 ~(total signal RMS)2 -82 ) . .+H...15.2. ) ~ N S .4..+N2 - (SIN) 20 I oglO N (~ ) S ) t-1V -t-ns -t Signal to Total 20 loglo [ IH2+H2+H2+H?+.+N2 Vll2 -t-nJ -t-n4 Harmonic Distortion plus Noise (S/THD+N) or S . H3 the RMS value of the third harmonic. The definitions of the various signal to noise and distortion parameters are listed in Table 8. Table 8.+.

the number of samples collected) must quadruple to drop the nomepeatability in half. Calculate S/2nd. which simply means the test engineer swaps the numerator and denominator in the log calculations. the S/(THD+N) calculation is defined in two different ways.and S/THD. which stands for signal to noise and distortion.or 10 kHz/512 = 19. if the specified distortion level is -85 dB. we do not have to multiply 996.094 Hz times 2.. very low levels of distortion are inherently very costly to test. This will lead to unrepeatable measurementsof distortion that mayor may not be tolerable. The extra collection and DSP processing time obviously adds test time and drives up the cost of testing.16. Both are equivalent. 5. The fundamental frequency is equal to the sampling rate divided by number of samples. 4. Example 8. the I-kHz sine wave is actually generated by an A WG at 51 times the digitizer's fundamental frequency. 3. the harmonic distortion components always fall into single FFT spectral bins. Testers usually include a very efficient RMS routine that can calculate the total signal RMS quickly. An FFT of the output signal shows several distortion components. For instance. although. It should also be noted that the abbreviation S/(THD+N) is often replaced by the equivalent expression.025 V 1. then the distortion component of interest may be very close to the noise floor of the DUT and/or ATE measurementhardware. The end result in either case is that data collection time (i.094 Hz. by 2.23mV 2. The only way to improve the repeatability is to averageor collect more samples with the ATE digitizer.32 mV . the second definition is sometimes faster to compute than pulling all the harmonics apart from one another only to recombine them later. etc. These can easily be calculated by multiplying the FFT bin of the fundamental tone. Frequency (fundamental tone) 2kHz (second harmonic) 3 kHz (third harmonic) 4kHz (fourth harmonic) 5 kHz (fifth harmonic) RMS Voltage 1.78mV 0. 51.54 mV 0. In the final row of the table.16. 4. or equivalently. To achieve coherent testing. SINAD.VoltageFollowerOutputLevelsat Fundamental SecondthroughFifthHarmonics and FFT Spectral Bin 511kHz 102 (2x51) 153 (3x51) 204 (4x51) 255 (5x51) Solution: Notice that in a coherent DSP-basedmeasurement system. S/3rd.9 A I-kHz sine wave passesthrough a voltage follower and a digitizer captures 512 samplesof the output signal at a sampling rate of 10 kHz. and 5 and then try to figure out which spectral bins they will fall into.e.531 Hz. Table8. 3. changes the sign of the dB number reported. especially when they are close to failing test limits. Repeatablemeasurementsof low-level distortion components can be extremely difficult and time-consuming to perform. Therefore. Therefore. listed in Table 8. or 996.282 An Introductionto Mixed-SignalIC Testand Measurement Sometimes the data sheet will callout specifications in negative decibels.

54 =58..1 dB \1 1+(0.4.23 my)2 1. Telecommunications and audio products usually specify a two.4 dB =52. Third-order intermodulation components are those for which p + q = 3.19) whereIMD]. Table8. denotedby.or fourtone test. say.Secondand thirdintermodulation frequencies two-tone for signalat F1and F2. lntermodulation distortion is expressed as a ratio of the signal RMS of anyone test tone. etc.32 mY) =50.54 myr 2. S1. +...025 Y ] +(2. v F) F2 freq Figure 8. are shown in Figure 8.F) andF2. J (8. F) and F2.17.16.Chapter8 . Analog ChannelTesting 283 Working with spectral bins instead of frequencies is therefore easier in some casesthan working with frequencies.16. Distortion components may appear at any sum or difference of any multiple of the test tones.78 2 2 mY) +(0.025 Y ) 20 I oglO ( 1. while digital subscriber line (DSL) testing may require hundreds of test tones. there may be distortion components at any intermodulation frequency F = I p x F) :t q x F 2 I.8 dB 8.025 Y mY ) 20 loglo [ (1.23 mY S/3rd SITHD ( 1. IMD2.17. . etc. where p and q may be any positive integers. +IMD.and third-order intermodulation components for two frequencies. The signal-to-distortion results are listed in Table 8. Second-order intermodulation components are those for which p + q = 2. Second.to the signal RMS of the intermodulation component(s) 20 loglo ( ~IMDI2 +IMDJ SI +IMD. The details of intermodulation tests vary widely from one type of device to another. Given any two test tones in a multitone signal. correspondsto the appropriate intermodulation distortion components.Signal-to-Distortion Results S/2nd 20 I oglo 1.2 lntermodulation Distortion lntermodulation distortion is very similar to harmonic distortion except that two or more tones are supplied to the DUT at once.

third-.lkHzl=900Hzand3.1kHz 11.1 kHz The third-order intermodulation componentsoccur at 12 x 1. Signal rejection tests are those which measure a channel's ability to prevent an undesired signal from propagating to the channel's output. or in the channel itself.1 kHz 11.2 kHz 13x 1.284 An Introduction to Mixed-Signal Testand Measurement IC The signal to intermodulation distortion calculations are usually specified with a limited number of distortion combinations. The undesired signal may originate in the power supply.OVRMS ) =70. Alternatively. When calculating specific combinations.0 kHz :t 2 x 1.3 kHz The signal to second-orderintermodulation ratio is given by the equation 20 10 ( 1.0kHz:t 1. and fourth-order intermodulation components. Calculate the signal to second-orderintermodulation distortion ratio.1 kHzl=I. Solution: The second-orderintermodulation componentsoccur at 11.5.1 Common-Mode Rejection Ratio A number of signal rejection specifications are common to analog and sampled channel testing.g. one at 1 kHz and the other at 1.1 kHz is 232 ~V.0 kHz :t 1.4 dB glo ~(193 JiVr +(232 JiVr 8. in dB. in another supposedly separatecircuit.0-V RMS sine waves. a signal to total noise plus distortion specification may be listed in the data sheet. Calculate the frequencies of the second-.2 kHz The fourth-order intermodulation componentsoccur at 12 x 1.5 SIGNAL REJECTION TESTS 8.1 kHzl=I.0kHz:t 1. The signal RMS at 100 Hz is 193 ~V and the signal RMS at 2. .1 kHzl =100Hz and2.10 A multitone test signal consists of a sum of two 1. sum of all third-order intermodulation components..1 kHzl =200 Hz and 4.3 kHz and 4. the test engineer adds or subtracts test tone FFT bin numbers and their multiples to determine which FFT bins are likely to contain intermodulation components.1 kHz.1 kHzl = 2.0kHz:t 2 x 1. e.2 kHz and 3.0 kHz :t 3 x 1.9 kHz and 4. Example 8.

S/3rd.INN is the dijf differentialinput voltageand G is the gain of the input circuit.0. Providedthat INp andINN are exactlyequal(i.3 kHz.04mV 1.e.55.1.!J= Gdiff (1)1 -V::v.19. In Chapter3.1.one at V 0.9560V 0.7.63. is a measurement of how well a channelwith a differential input can reject a common-mode signal.11.3..u. where V = INp . Determine frequencies all thirdthe of orderintermodulation frequencies. common-mode rejectionratio (CMRR).RMS sine waves.the total RMS value of the output signal is 0.0.04mV In addition.due to mismatched components the in inputcircuit.9.5. Ideally. One suchsignal rejectiontest. 85.84. anotherat 2. thenthe circuit should producezero output. 8. Ans.3. AnalogChannel Testing 285 Exercises 8. we studiedDC CMRR testingfor differential circuits.46.31. AC CMRR for analog channels definedin a similar manner DC CMRR.3. . andthe third at 5.5. AC CMRR is definedasthe AC gain of is to the channelwith a common-mode input divided by the gain of the channelwith a normal.95601V.=o I diff ) ) (8. CMRR(I)= G I ~J£.64mV 0.3.9. An FFT analysis of the output of an amplifier contains the following spectral amplitudes: FFT SpectralBin 31 62 (2x3l) 93 (3x3l) 124 (4x3l) 155 (5x3l) RMS Voltage 0. if the input signalis purely common-mode with no differential component).3. CalculateS/2nd.1 kHz.20) ( ~ diff I v constant cm AC CMRR is a frequency-dependent parameter and is therefore denoted with a frequency argument. differentialinput ( V.7.18.Chapter 8 .79dB.5kHz.9 kHz.53. Ans.05mV 1. a differential input circuit producesan output equal to GVdijf. However. a small amountof common-mode signalusuallyfeedsthroughto the output. S/THDandS/THD+N. A multitone test signal consistsof a sum of three 1.

7 mV RMS. Then the inputs are shorted together and a single-endedmultitone is applied to the two inputs simultaneously.286 An Introductionto Mixed-SignalIC Testand Measurement The common-mode gain is measured by connecting the two inputs together and applying a single-ended signal to them. The input signal level is 250 mV RMS. The output of the circuit is digitized differentially. Ifwe observe the positive input during the differential gain measurementand then during the commonmode measurement. the differential gain results can be reused instead of repeating the same differential gain measurementsagain. The calculation of CMRR for an analog channel is thus CMRR(dB)=20 10glo(I~) (8. Multitone testing can be used to measureCMRR at several frequencies at once. this gain should be very low. the differential gain of the channel has already been measured at several frequencies during an absolute gain or frequency response test. CMRR should produce a negative decibel result. 3400 Hz: 1.8 mV RMS.11 A differential gain circuit has a differential input. resulting in the following differential RMS output levels: 300 Hz: 0. a differential output and an ideal gain of 6. CMRR is often expressedin decibel units rather than VN. The output of the channel i~ again digitized. The common-mode gain is thus measured as if the channel had a single-ended input. since INp and INN are equal and the output GVdiffshould be zero. Ifhigh accuracy is not required. In such a case. Calculate the CMRR at each frequency. 1020 Hz: 500 mV RMS. resulting in the following differential RMS output levels: 300 Hz: 510 mV RMS. Often. Obviously.5 mV RMS.02 dB (2. it is often acceptableto simply divide the measuredcommonmode gain by the ideal differential gain of the circuit. 1020 Hz: 0. The measurement of CMRR is often performed at several frequencies. differential. single-ended. This very low gain is then divided by the differential AC gain of the channel to arrive at the CMRR value for the specified frequency. saving test time.would the signal level change? Solution: The differential gain at each frequency is calculated as follows 300 Hz: Gain = ~ 250 mV =2. 3400 Hz: 480 mV RMS.04VIV =2.00VIV =1.21 Example 8. rather than measuring the differential gain at each frequency of interest. since a channel may have different characteristics at different frequencies.92VIV 1020 Hz: Gain = ~ 250 mV 3400 Hz: Gain = ~ 250 mV . The level of each of the tones is 250 mV RMS. Since the gain of the circuit with a common-mode input is much smaller than the differential gain. A differential multitone signal is applied to the input of the circuit at 300. 1020. and 3400 Hz. Like many other AC parameters.0 V N).

8mV = 0. except that the interference signal is applied through the power supply rather than through the normal inputs.2 Power Supply Rejection and Power Supply Rejection Ratio Power supply rejection ratio is similar in nature to CMRR. Usually. PSRR is usually measured using a single tone or multitone signal.006V/V 250 mV The CMRR at each frequency is thus ( 300 Hz: CMRR = 20 loglo 0.04 V Iv V Iv . PSRR is much worse on the analog supply than on the digital supply.Herethe PSRwould be computed from the following formula . Analog Channel Testing 287 The common-mode gain at each frequency is calculated as follows 300 Hz: Gain= 0. even though the device will seldom see a sinusoidal ripple on the power supply.0028 2. PSRR is often specified for both the analog power supply and the digital power supply in mixed-signal devices. It consists of a DC level plus AC variations caused by circuits pulling time-varying currents from the power supply circuits or from a battery.7mV =O. 8. Powersupplyrejection(PSR)is definedasthe "gain" of a circuit with its input grounded or otherwisenonstimulated while an AC input signal is injected at a power supply pin. but not always. For instance.OO28V/V 250 mV 1020Hz: Gain= 0. the power supply voltage is never perfect. test setupfor a single-ended a amplifier is shownin Figure8. -I Since the signal level during the differential test is 250 mV RMS differential (125 mV RMS.5. we would see the signal level at the positive input increase by a factor of two during the common-mode test (250 mV RMS. PSRR is a measurementof a circuit's ability to reject a ripple signal added to its power supply voltage.17.0032VIV 250 mV 3400Hz: Gain=~=0. In real-world applications. single-ended). single-ended).Chapter 8 .

and 3400 Hz is applied to the input of the gain circuit in Example 8. resulting in the following differential RMS output levels: 300 Hz: 510 mV RMS. the AC input signal at the power supply pin must include a DC offset that corresponds to the normal power supply voltage so that the circuit remains powered up.20 mV RMS. Each of the tones is set to a level of 250 mV RMS.12 A differential multitone signal at 300. 3400 Hz: 480 mV RMS. decibel results from a good DUT should be negative. Calculate the PSR and PSRR at each frequency.22) As with all AC test metrics.17.288 An Introduction to Mixed-Signal IC Test and Measurement Vac VDD + - Vout Figure 8. differential. Power supply rejection ratio is defined as the PSR gain divided by the normal gain of the circuit according to PSRR(I) = l~ill G(I) l= ~ ( ~ ~nv=o I ac (8. Of course. Then the inputs are shorted to a DC midsupply voltage and a single-ended multitone is added to the power supply. similar to CMRR. 1020 Hz: 500 mV RMS.23) ) Like CMRR.15 mV RMS. The output of the circuit is digitized differentially. PSRand PSRRtest setup. The input signal level is 100 mV RMS. 3400 Hz: 0. they are frequency dependent and thus should be expressed as a function of frequency.11. PSR(I) =1 ~IVin=Vmid I (8. the Both PSR and PSRR are usually specified in decibels.12 mY RMS. Example 8. 1020. . 1020 Hz: 0. single ended. The output of the channel is again digitized. resulting in the following differential RMS output levels: 300 Hz: 0.

3 Channel-to-Channel Crosstalk Crosstalk is another common measurementin analog channels. though its exact definition can be very DUT specific.9 dB (orO.5 dB glO 2.00VjV 3400Hz: PSRR 2010 = glO ( 0. crosstalk is a measurement with no exact definition.12mY ) 100 mV =-58. Unlike CMRR or PSRR. AnalogChannel Testing 289 Thedifferentialgain at eachfrequency the same in the CMRRtest is as . 300Hz: Gain= 510 mV =2.0015VjV ) =-62.Chapter 8 Solution: . In general.92VjV 250 mV ThePSRat eachfrequency calculated follows is as 300Hz: PSR=2010g10 0.00VjV 250 mV 3400Hz: Gain=~=1.0012VjV) ) ) 2.5. . of course.15mY 1020Hz: PSR=2010g10 =-56.20mY =-53. Ideally.04VjV ) =-64.4 dB (orO.4 dB (orO.6 dB 1020Hz: PSRR=2010 ( 0.0020VjV) 100mV ThePSRRat eachfrequency thus is 300 Hz: PSRR =20 10glO( 0.0015VjV) 100mV 3400Hz: PSR=2010g100.92VjV 8.0012 IV V ( ( ( 0.04VjV 250 mV 1020Hz: Gain=~=2.0020 IV ) =-59.6 dB V 1. crosstalk is the gain from one channel to a secondsupposedly independent channel. the channels should be perfectly isolated from one another so that there is no crosstalk.

Modeling channel-to-channel crosstalk. ' I ' I I : '.=o ~ ' (8.18 where the crosstalk terms Xrl and Xlr are defined as X. divided by the gain of the secondchannel. crosstalk is often defined as the gain from one channel's input to another channel's output. . I . For now.24) I Yr=O ) Crosstalk is often measuredat several frequencies at once. The secondchannel's input is typically grounded (or connectedto a midsupply voltage in singlesupply circuits) during a crosstalk measurement.290 An Introductionto Mixed-Signal Testand Measurement IC In analog channels. using DSP-basedmultitone testing. I . The frequencies also have to be chosen so that the crosstalk components will not occur at the same frequencies as the harmonic and intermodulation distortion components of the primary signals. we will assume that crosstalk is defined as originally stated: the gain from one channel's input to another channel's output. a model of the channel-to-channel crosstalk is provided in Figure 8. ~ : I I ' Figure 8. If crosstalk is specified from channell to channel 2 and also from channel 2 to channell. Vout-r Vr I I I I I I Vout-l VI: I . distortion will be misinterpreted as crosstalk. = \ I G. divided by the gain of the second channel. Other times. like CMRR and PSRR. the crosstalk is not divided by the gain of the second channel at all. the two channels have to be stimulated with slightly different frequencies so that each channel's crosstalk responsecan be isolated from its primary signal. . however. Otherwise. .(!)= r \ §JL}j= (~IYr=O) ~I ( ) ~ X/r(l)= \ 3Jfl. The test engineer has to clarify the definition of crosstalk in each case. To aid the reader. Crosstalk may also be expressedas the gain from a channel's output to another channel's output divided by the second channel's gain.18.(I) (:!IJ ( r Y. OUT . To do this. : . then crosstalk can be measuredfrom each channel to the other channel simultaneously to save test time. Crosstalk is usually expressedin decibels.

19).08mY RMS. 1020.20mY RMS Solution: First. and 3400 Hz on both the left and right channels. 3400Hz: 0. 1020Hz: 0.08mV RMS.25 Hz. 512 samples 16-kHz sampling rate..22mV RMS L Output: 300Hz: 0. Simultaneous crosstalkmeasurements stereoaudiochannels. 512 samples Right signal plus L-to-R crosstalk I I I I I I . assume we havealreadymeasured gain of exactly 6.. f-+ Figure 8.L-to-R crosstalk .19. The fundamental frequency for the l6-kHz sampling rate/5l2-sample system is 31.02 dB througheachchannel.09mY RMS.07mV RMS. 3400Hz: 0. we can use spectral . The actual test frequenciesmust be equal to the desired frequencies within a tolerance of plus or minus 10%. Each path is single ended (Figure 8. We have two A WGs and two digitizers so we can perform two multitone crosstalk measurements simultaneously. I R-to-L crosstalk . 1020Hz: 0.Use a l6-kHz sampling rate and 512 samples for the AWGs and digitizers. Using the following a digitizedsignallevels. Using two digitizers and two AWGs. sincethe exact frequencies shouldbe slightly different for the left and right channels. For simplicity. 16-kHz sampling rate.A stereoaudio channel consists of two identical analog signal paths (left and right). for Apply the three-tone multitonewith a total signalRMS of 500 mY. For the right channel. R Output: 300Hz: 0.calculate crosstalk from L to R and from R to L. define a simultaneous sampling system that produces a multitone signal at approximately 300. The frequencies below are approximate. we design the sampling system.

and 109. Using the FFT from digitizer # l' s waveform. For the left channel we can use spectral bins 9. Note that we cannot use spectral bin 33 in the second multitone. These frequencies are within 10% of the desired frequencies. Left-to-right crosstalk is defined as 20 loglo( gain from L to R/gain in right channel) and right to left crosstalk is defined as 20 loglo( gain from R to L/gain in left channel).4 dB . instead measuring the components at bins 11.31. A WG #1 is set to produce the first threetone multitone signal for the right channel.33. we would not be able to distinguish between third harmonic distortion from spectral bin 11 and crosstalk at spectral bin 33. 35. The gain for both channels is exactly 6. The two digitizers are set to capture the waveforms at the left and right channel outputs. which gives frequencies of281.J3or 288.292 An Introductionto Mixed-Signal Testand Measurement IC bins 11. Crosstalk is calculated as follows.02 dB.20 10glo(~09mV/~88.68 m~)=-77.68 m~)=-77. while A WG #2 is set to produce the second threetone multitone for the left channel.3 dB 1020 Hz: Xlr =20 10glO(Q:~~mV/~88. which might result from the signal generatedby AWG #2 (the left channel's signal). 3). we look for crosstalk components at 9.68 m~)=-68.2 dB L-to-R crosstalk 300 Hz: X1r =20 10glO(~7 mV/~88. and 3344 Hz. and 107. Instead.2 dB 1020Hz: Xrl". Therefore. we ignore the spectral componentsat spectral bins 11. and 107 in the left channel's output. If we tried to use bin 33.68m~)=-76. and 107. 33.969. and 3406 Hz. 31. The signal level of each input tone is equal to the total signal level divided by the square root of the number of tones (in this case. we ignore spectral components at bins 9. and 109 (the right channel's signal).68 mV RMS.2 dB 3400 Hz: Xlr =20 10glo(~mV/~88. even though it would give a frequency closer to 1020 Hz. and 109.1dB 3400 Hz: Xrl =20 10glO(~:20 mV/~88. 31. which gives frequencies of 343.68_~)=-63. Similarly. each tone's amplitude is 500 mV RMS/. R-to-L crosstalk 300 Hz: Xrl =20 10glo(~08 mV/~88.68 m~)=-78. 1103. which is a gain of2 VN.. which might result from the right channel's signal.

Again. etc. clock and data feedthrough is not specified as a separate parameter. If the clock and data feedthrough is coherent with the digitizer. it can cause electromagnetic compatibility problems. Clock feedthrough often has a signal bandwidth well into the megahertz range. an undesirable property of a circuit under test. the feedthrough may be specified in terms of a maximum spurious tone.5. 293 8. the DC component is removed mathematically by subtracting the average of the digitized signal from each point in the captured waveform. Clock and data feedthrough is measured by digitizing the output of a channel and then applying one of several calculations to the resulting waveform. Unfortunately. The test engineer will have to make sure the exact definition of clock feedthrough or glitch energy is unambiguously defined. Noise can also be injected into a circuit by external forces.and many other system-level failure mechanisms. Often. . timeconsuming measurementsin a mixed-signal test program. relative to the level of a carrier tone. but not always. Noise tests can be among the most difficult. The removal of DC offset can be accomplished by applying a DC blocking capacitor or high-pass filter to the signal before measuring its RMS level.1 Noise . Excessive noise can result in a hissing noise in audio circuits. such as cellular telephones. so a high-bandwidth digitizer is typically used to measureclock feedthrough. It is simply consideredpart of the noise in a signal-to-noise test. Noise is one of the leading causes of long test time. excluding DC offset. Such a telephone would fail the Federal Communications Commission (FCC) compliance tests. since averaging or added measurementsare needed to remove the nonrepeatability caused by random noise.6. More often. Random noise is generatedby every real-world circuit. the spurious tone is specified in dBc (dB relative to the carrier level). Noise is generally. In this case. the systems engineers or customers will have to help clarify the test requirements. Becausethe energy in a spurious tone is concentrated around a single frequency. or quantization noise in the case of DACs and ADCs. Noise testing is another major category of analog and sampled channel testing. Spurious tones are often a major concern in communication devices. Digital feedthrough is usually very "spiky" in appearance. When spe~ified in this manner. Clock and data feedthrough may instead be specified in terms of total RMS voltage.6 NOISE TESTS 8. then an FFT can be performed on the output signal. specifications are often lifted from a competitor's data sheet. It can be generatedby thermal noise in the case of resistors.4 Clock and Data Feedthrough The definition of clock and data feedthrough is even less standardizedthan crosstalk. Analog Channel Testmg . A cellular telephone that generates a spurious tone in its transmit channel might interfere with other cellular telephones operating at the same frequency as the spurious tone. l/f noise in the case of CMOS transistors. corrupted data in a modem or cellular telephone. which does not clearly specify the test conditions or test definition (what data pattern is being sent to or from the DUT. Usually the systems engineers or the customers will be the only ones who can define their intentions. such as light falling on a bare die or electromagnetic interference coupling into a circuit under test. 8.Chapter 8 .).

Idle channel noise is the RMS voltage variation with no input signal (grounded inputs or inputs connected to a DC midpoint voltage).) This definition of noise includes random noise as well as harmonic distortion. It is important to realize that the bandwidth of the digitizer during this measurement is extremely important. the output should also fall into a noise-free state. is noise that is weighted more heavily at low frequencies. Sometimes noise is defined as any signal component other than the primary test signal. intermodulation distortion. Pink noise. White noise is noise whose RMS voltage is constant in any band of frequencies from F to F+M. Idle channel noise can be expressed in many different units of measure. The most straightforward idle channel noise measurement is to simply calculate the RMS voltage level from the captured samples. For example. like white light. interference. A digitizer with a wide bandwidth will see more RMS noise than a digitizer with a narrow bandwidth. etc. but of course all outputs exhibit some amount of noise. For this reason. regardless of the value of F. plus noise injected from external circuits or signal sources through a variety of coupling mechanisms. is also excluded from the calculation of noise. by contrast. . It is important to recognize. the input to the circuit under test is either shorted to ground or otherwise disabled into a quiet state.2 Idle Channel Noise Idle channel noise (ICN) is a measurement of noise generated by the circuit itself. There are several different ways to measure noise. that the spectral properties of noise and its statistical distribution are separateconcepts. They are combined for mathematical convenience. It is therefore preferable to measure distortion components separately from clock feedthrough. contains energy that is evenly distributed acrossthe frequency spectrum. (The 0 Hz. a good test program should isolate all the known failure mechanisms into separate measurements. Since test engineering is frequently concerned with characterization and diagnosis of failure mechanisms. distortion. Since white noise is spread evenly across the frequency spectrum. etc. however. Often the level of noise is assumed to exhibit a Guassian (normal) statistical distribution. The signal to total noise. sigma-delta converter self-tones. separately from random noise. clock feedthrough. a data sheet may specify idle channel noise as < 100 ~V RMS from 100 Hz to 10 kHz. Each of these tests looks for a different noise-basedweaknessin the circuit under test. There are also other definitions of noise performance such as spurious free dynamic range. 8. Signal-to-noise and signal-to-noise plus distortion are other figures of merit. it is critical to express the noise in terms of RMS voltage over a specified bandwidth. Ideally. or DC component. a wider bandwidth will allow more noise components to be added into the final calculation. Using DSP-based testing methodologies. During an idle channel noise test. etc. can also be calculated separately for additional characterization information.6. White noise.294 An Introductionto Mixed-Signal Testand Measurement IC The spectral density of noise energy is often described using color analogies. This is largely a result of the central limit theorem of large numbers. this output noise is measured by digitizing the output of the circuit and performing a noise calculation on the captured samples. Often a data sheet will callout such a signal to total noise plus distortion test as an overall measureof quality.

The idle channel noise would then be calculatedas noise (dB) =20 10g\o( 1 mV RMS 354mVRMS ) =-51 dB. then the noise can be expressed as 100. denoted Sn.uV from 9 to 11 kHz. Such a sine wave is said to be at a level of 0 dBmO. There are a variety of references that the test engineer will encounter. This corresponds to 500 mV /.uV/~x~=141.J11 kHz . one simply needs to multiply Sn by the square root of the frequency span (12 kHz 8 kHz = 4 kHz).fi = 354 mV RMS. Noise measurementscan be converted to decibel units as follows . Noise can also be specified in dBm. Analog Channel Testing 295 The measurementof noise can be nonnalized by the bandwidth of the measurementusing a unit of noise called the root spectral density. Idle . This type of measurementis expressed in units of volts per root-Hz (V / ~) and it can be used to estimate RMS noise over other frequency bands. Thus expressingnoise in decibel units is fairly straightforward. if a circuit generates 1 mV RMS idle channel noise and its full scale range is :t500 mV. One reference is simply 1.25) For example. if an RMS volt meter or digitizer allows only signal energy from 9 to 11 kHz to pass. then the noise is measured relative to a sine wave at 500 mV peak. for example.236. When using this reference the noise is expressedin dBV (decibelsrelative to 1 V RMS).0 mW signal level at a particular load impedance. since noise is sometimes unevenly distributed. A sine wave at 0 dB produces a O-dBm signal level at a specified point in the central office.9 kHz or 2.uV .many central office telephone channels use a reference level that is about 3 dB lower than the full scale range of the channel.41.uV RMS. For example. noise ( dB) =20 10g\O ( noise RMS reference RMS ) (826) . Idle channel noise may also be specified relative to a full-scale sine wave (full scale must be defined in the data sheet). / /~ ~ To estimate the RMS noise that would occur in the frequency span between 8 and 12 kHz. Using the previous noise result. relative to FS Idle channel noise can also be referenced to a O-dB level. referencing it to a 1. the RMS voltage is divided by the square root of the frequency span of the bandwidth B of the digitizer or RMS volt meter Sn (~ )= V noise RMS Jjj (8. and the RMS noise measurement is 100 ~V RMS.236 . For example.Chapter 8 . However. A separate measurement of root spectraldensity could be perfonned near 100-200 kHz for this range of frequencies. it might or might not be appropriate to estimate the noise from 100 to 200 kHz using the root spectral density measured between 9 and 11 kHz. we would then estimate noise from 8 to 12 kHz to be 2. To convert a plain RMS voltage measurement into a V / ~ measurement.0 V RMS. defined in the data sheet. except for the detennination of the reference voltage.

Signal-to-noise ratio is often measured using the same data collected during the gain and signal-to-distortion tests. Example 8. in dBmCO units.uV RMS =-82. it is necessaryto measure not only idle channel noise.14 A CODEC (coder decoder) is a device that is used by the telephone company's central office to digitize and reconstruct analog voice signals during a telephone call. Solution: First we take the 100 !.08 dBmCO 8. quantization noise will not be present unless a signal is present. It is different from idle channel noise in that it measures noise in the presenceof a normal signal.92 dBmCO 1. After filtering. usually a sine wave. The resulting signal is filtered with a software C-messageweighting filter that limits the bandwidth of the noise to 0 Hz to 3.6.3 Signal to Noise. Weighting filters were discussedbriefly in Chapter 7 and will be explained in more detail later in this chapter. the noise level is calculated as 100 !. This gives us ICN(dBmCO)=20 10glO ( 100.LVRMS signal and calculate its level in dBmCOunits. For this reason.4 kHz. The O-dBmOreference level is 1. Finally.4 V RMS for the DAC channel. The DAC output is digitized with a bandwidth of 20 kHz. resulting in the unit dEmO. However. Referencing the measurementto the central office level of 0 dEmO further gives us the dEmO unit. A dBmO measurement is therefore 90 dB higher than the equivalent dEmO measurement. the noise can be weighted with a C-message filter before calculation of the RMS noise voltage.92 dBmCO + 90 dB =+7. in a DAC or ADC channel. . leading to the unit dBmCO (commonly pronounced duhbrink'-o).296 An Introduction to Mixed-Signal Testand Measurement IC channel noise measurements can also be referenced to this O-dB level. but also signalto-noise ratio in mixed-signal channels. The dEmOunit of measurementcan be further refined by referencing the noise to a commonly accepted reference level of -90 dBm. When working with a purely analog channel. . The digitized voice information is transmitted between two central offices as the two customers speak to one another. A CODEC DAC channel is sent a data sequenceof all zeros (idle signal).LVRMS. This unit of measurement is called the dBm (decibel referenced to noise).4 V RMS ) Conversion to dBmCO is accomplishedby adding 90 dB to this result ICN (dBrnCO) =-82. Calculate the idle channel noise. the presence of a signal should not change the amount of noise generated by the channel. Signal to Noise and Distortion Signal-to-noise ratio is another parameter that measuresthe noise performance of an analog or mixed-signal channel.

The magnitude of the spectrum shows the signal and 5 significant distortion components. and third harmonic distortion components. Calculate the signal-to-noise ratio for this signal.15 256 samples of a I-kHz sine wave are captured with a digitizer at a sampling rate of 16 kHz. Notice from this table that individual signal components are added using a square-root-of-sum-ofsquarescalculation. second-. The only way to get a repeatable noise or low-level distortion measurement is to collect hundreds or thousands of individual samples for the FFT calculation. This is one reason why devices that.Chapter 8 . Note: The DC offset component is always excludedfrom these calculations.are designed very close to the specification limits are expensive to test.15 summarizes these typical noise and distortion measurements. the avoidance of an inverse FFT can save quite a bit of test time. Example8. A design with 6 dB of margin between the typical device performance and the specified limit can allow a much less expensive test than a device with 1 dB of margin. this definition includes distortion components and other signal degradation factors that should be separatedfor characterization purposes. so the signal-to-noise ratio is equal to SNR(dB)=20 lOglO 100. However. the test engineer can set the spectral coefficients to zero for all signal and harnlonic distortion bins that are to be excluded. it is common to measure signal to second distortion. This can lead to extremely long test times. or better yet.20. These two approaches are mathematically equivalent.21. signal to third distortion. Therefore. The data sheet for this device defines noise as anything other than the fundamental signal.harmonic distortion components are set to zero. Analog Channel Testing 297 Signal-to-noise ratio can be defined as the ratio of the primary signal divided by all nonsignal AC components. and third. To calculate the total noise in nonharnlonic bins. For example. since 6 dB of margin requires less accuracy and repeatability.uVRMSJ ~ ( IV RMS 1=80 dB . second-. Poor repeatability is one of the biggest problems with noise measurements. and signal to total harmonic distortion plus noise (S/THD+N). any signal component that is near the noise level will be unrepeatableas well. However. depending on the level of repeatability needed. Table 8. Then the test engineer can either perform an inverse FFT and calculate RMS of the time-domain signal.VRMS. Random noise by its very nature is nonrepeatable. Also. a distortion component at 100 ~V RMS may result in a very unrepeatable measurement if the noise level is also 100 ~V RMS. The fundamental tone was at V RMS. For example. signal-tonoise is more commonly measured by excluding harmonic distortion components. simply calculate the square root of the sum of squaresof all the remaining FFT bins. An FFT analysis of the output reveals the magnitude of the spectrum shown in Figure 8. The fundamental test tone. leaving the spectrum in Figure 8. or excluding selected harmonic distortion components. Taking the square root of sum of squaresof the modified spectrum gives an RMS noise level of 100 IJ.

.....-:... : 0 0 ' ....-:._:-. ~ 0 .-:.. 0 0 . ....~...--...-:..._:.: -80 ~..-~ .:::::::...:.. 0 0 0 0 ... 0 0 0 ~ ..-:. 0 0 0 . ---: -~..-:.6........-..--~ . stray oscillations...~.-~...-.....298 An Introductionto Mixed-SignalIC Testand Measurement -0 -1 0 ...~ 0 : 0 ' ~ 0 : . ....--:.. ..-.-~ -..-.. ..~-..-..-. :--. 0 0 0 0 -80 ~ 0 ... .--:--.....--0 ~ ....--: 0 0 0 0 ..-... ~ -0 ~ ..... ~.....--:-0 ........ : .-~ ....~......_:.-:..~. 0 ....-:... 0 0 ...-.... 0 0 0 ...20..... 0 0 ...--: 0 '4th' 0 0 '5thO 0 :_-0 0 .~ ..-~ -60 -70 -90 : ... 0 0 0 ......-~ ...-:-..~...r --0 ..... 0 0 ~ 0 0 ' 0 '0 ...~..~.. 0 : ~ : 0 0 ...-~-...-.-~ ._:-...-.. 0 0 0 0 0 0 .-_: 0 0 0 0 0 0 ..-.i ..i .. :--.-.. 0 . : .~.-. ..t .. clock feedthrough.~. .....:_:::::~::::::........ ~ .. : ...-..~-.. 0 0 : ..~..-:...-.~........... ..--~ ..~-.. .-0 0 0 ...... . -70 .............~.i .. :- : 0 : 0 ~ 0 ~ :0 0 ~-- : 0 0 0 0 ~- 0 ..-:... -~ .-~ .T.....-.. 0 0 . ...~ ..-....~-. 1 ...... ...--.._:....._:-......~. 0 .t .......sigma-deltaconverter self-tones. second and third distortion removed._: . 0 0' . Magnitude spectrum (dBV) for 1-kHz test tone with noise and harmonic distortion.... 0 0 ~ 0 0 --: 0 0 i ..-0 0 .._: 0 .. ...... -11 ~ 0 .~0 0 ......-~ .. .. ~ : ~ : ~ ~ .:::::::.. ..~. ~..-......~..... ~-0 0 .........::: ~:: 0 10 20 30 40 50 60 70 80 90 100 110 FFT Spectral Bin # ' 120 127 Figure 8..~... -- 0 ~ -.-:-.. : ~._:.-:.. ~0 .~...: : 0 4th 0 0 5th ~..... 0 ..-:-..-~ ....... 0 ~- -50 0 0 ~ ....._:..~.:.. 0 Fundamental Test Tone ..... 0 0 0 0 0 -122 ~::::::~:::::::~::::::~::::::::::::::~:::: 0 10 20 30 40 50 ::::::::::~:::::::::::::::~:::::::::::::::~::::::~:::::: 60 70 80 90 100 110 120 127 FFT Spectral Bin # Figure 8.-:.. A spuris definedas any nonsignalcomponent is confinedto a singlefrequency.. 0 -100~ 0 0 ....t ... .. .....~ .~ .-.-:-....-_:..-... ~ ....... . : 0 0 .~ -.~-...-0 0 ..-:.... ~..... 8...-: 0 .--..~-....~..-: ~ 000' 0 ---- : :2nd: :3rd: : : : : : -:..........~0 -20 -30 -40 --~ ......_eo: 0 0 0 0 0 0 0 0 .. ~ 0 r 0 ~ ..-~ . ~ ...--..-... ..-:. .-..-:. 0 0 0 0 . ....... --~--- 0 -. .......-0 ..... ..-. 0 0 0 .- ~ 0 .~.-.21...i ....... ~0 . .. .......--~ ... ...T....~-....-:....-. -30 -40 -50 -60 ~ -. 0 .. 0 : 0 0 i 0 0 : 0 0 .. ~ .-. .:......-......t-.-:.-:...~ . 0 ... 0 0 ~ 0 ....... ..._.i .-. any of dozens otherundesirable or of processes. .-0 .. 0 ~ 0 0 0 ~ 0 0 ~- .-:- 0 -.~ -100 -110 -122 0 0 0 ~ 0 .. .-~. ._:-..........-:--...~...--: 0 0 .-~ .. . -....... 0 0 0 ..... ~ 0 0 0 -90 .-. ...-:.._:: --~ ... .-..-: 0 ~ 0 .-..~... -..~ ...i .-. ..i . .......... . .. Spurscan be caused harmonic that by and intermodulation distortion... . ~ 0 .... .i .-~.~ .... 0 0 -10 ~ 0 0 -20 ~ .---..__:::::..........~. .....--: 0 : 0 ...:__:__.:..... 0 0 ....-.. Magnitude spectrum with fundamental test tone.i .-_.. ' ..--: 0 ._:-.......--.-~ --0 : ~ 0 : ..4 SpuriousFree DynamicRange Spuriousfree dynamic range is a specificationthat is critical to audio circuits as well as telecommunication circuits that mustpassFCC (or EC) certifications...~..... -0 0 ~.. ........~...~....-. . 0 0 .-_:- . 0 .-...... . ..~ ... .0 :: 0 ~ ....... ~ 0 .~ ... 0 0 0 0 0 0 0 0 0 ~ 0 0 0 0 0 ..--: ~........ .-.. -...:- ... ..0 ...-. ' 0 '....-:.::_::--~_:::::.. ._:.---~ 0000 0 :: .._:--.. 0 0 ~ . . 0 0 0 ~ -.--_:... ..... ~ 0 0 0 o . ~ : 0 ..::::::_...-: ... 0 ..

Detennine the root spectral density of a noise signal that has an RMS value of 250 ~V over a frequency range of 1 to 4 kHz..27 pvjJHi. 26.5 mV RMS) =66 dBc. but improves the spurious free dynamic range. The end result is less objectionable to the listener. FCC compliance specifications limit unwanted spurs in transmitted signals.21. I Calculate the RMS level of the noise signal between 1 and 2.564 pV j JHi. 25. This degrades the signal-to-noise perfonnance. Analog ChannelTesting 299 8. if a device has a O-dB carrier signal level specification of 3.20. spurs can be mixed into the transmitted signal.1111_Exercises Chapter8 . Spurious free dynamic range is often defined as the difference in decibels between the O-dB signal level (the carrier level) and the maximum spur in the frequency domain. For example. resulting in unwanted side lobes that might interfere with calls on other cellular telephones.2539 mV . Ans. then the spurious free dynamic range is 20 log\o(3 V RMS/1.0 V RMS and the largest spur in the frequency domain is 1. 8. 1. 4. Ans.2620 mV 0. For this reason.7270mV 0.2550 mV 0. What is the corresponding root spectral density of the noise over this frequency interval? Repeat for the frequency range between 1 to 3 kHz. . I Spurs are much more noticeable to the human ear than other types of noise.5 kHz.24 pvjJHi.0150 mV 0. 1 mV RMS.1 mV RMS. .5559 mV 0.4941 mV 0.4092 mV 0.5 mV RMS. sigma-delta converters sometimes include a randomizing circuit to inject random noise that spreadsthe inherent self-tones of the converter into many frequency bins. A digitizer sampling at 8 kHz captures 16 samples of a noise signal. For this reason. A spur shows up in a magnitude FFT or on a spectrum analyzer display as a spike in the frequency domain. In cellular telephone applications.1681 mV 0. An FFT analysis reveals the following spectral coefficients: FFT Spectral Bin 0 1 2 3 4 5 6 7 8 RMS Voltage 0. A spurious free dynamic range of 60 dBc would imply that no individual tone in the frequency domain is larger than 60 dB below the O-dB carrier signal level as defined in the data sheet..

on the other hand. A weighting filter is usually designed to mimic the response of a human sense.6.signal that was digitized at 16k Hz using 512 samples.09691 A standard linear interpolation is then performed to calculate the gain of the weighting filter at 1156. Three filters are commonly used in telecommunication and audio applications: the ANSI Aweighting filter.0. The frequencies.26 Hz =G1 +( G2 -GI) ( lOgIO(F. we have to use interpolation to find the gain at a particular frequency.09691-3 =0.25 kHz (G2= 0. such as hearing.22-8.16 Calculate the gain of an A-weighting filter at the thirty seventh FFT spectral bin of a. The corresponding filter gain specifications are listed in Tables 8. Example 8.est )-lOglo(fi) loglo (F2) -loglo(fi) 3.25 Hz. and the C-messageweighting filter (not to be confused with the ANSI C-weighting filter). Solution: The thirty seventh FFT spectral bin correspondsto 37x(16 kHz/512) = 1156.0 dB +(0.6 dB).) The most common weighting filters used in mixed-signal testing are designedto match the frequency responseof the human ear.300 An Introduction to Mixed-Signal Testand Measurement IC 8.18-8.0 dB) 3. distortion.25 Hz as follows gain at 1156. the psophometric filter.0 = loglo (1250) = 3. must be converted into a logarithmic format before interpolation can be calculated.25) =3.5 Weighting Filters Weighting filters can be applied to any FFT output before calculations of gain. the gain is already in log format.20.06305 loglo(fi) 10glo (F2) =10glo(1000) =3.39 dB .est) =loglo (1156. To apply a particular filter to the FFT of a test signal. First we have to convert these frequencies to logarithmic values 10g)O(F.6 dB . the test engineer must first calculate the gain at each FFT spectral bin. The spectral coefficients are then multiplied by the filter gain at that frequency to produce a weighted FFT. The weighting filters specify a linear interpolation between points on a log/log plot. Since the gains are expressedin decibels.24. The nearest two points on the A-weighting curve are located at FI = 1 kHz (GI = 0 dB) and F2 = 1. Since the weighting filters are only defined at a few frequencies. noise. are performed. etc. The frequency response of each filter is shown in Figures 8.06305-3 ( ) ) =0.

5 40 50 63 80 -70.9 -0.1 10000 12500 16000 20000 >20000 Gain(dB) -2.1 -16.1 -13.7 -39.2 1. ANSI A-Message Weighting Filter Gains Freq(Hz) Gain(dB) Freq(Hz) Gain(dB) 10 12.18.0 0.3 1.4 -10.4 -56.6 -30.8 Freq(Hz) Gain(dB) Freq(Hz) 1000 1250 1600 2000 2500 3150 4000 5000 6300 8000 0.0 1.7 -50.4 -63.5 -0.3 -6.22.1 -1. ANSI A-Message Weighting Filter Table 8.4 -34.6 -6.5 16 20 25 31.5 -44.2 -22.2 -1.5 100 125 160 200 250 315 400 500 630 800 -19.8 -3.Chapter8 .2 -26.6 -4.5 -4.6 1.3 Undefined .2 1.6 -9. Analog ChannelTesting '-'" 301 20 0 -20 I Gain (dB) -40 -so 10 100 1000 1'10 1'10 Frequency (Hz) I Figure 8.9 -8.0 0.

0 -43. Psophometric Weighting FilterGains Freq(Hz) 16.0 -0.0 0.0 -0.23.7 -2. Psophometric weighting filter.5 -15.0 -4.4 -63.0 -10. 800 900 .6 -8.19.9 0.6 -2.2 -5.0 0.6 Freq(Hz) 1000 1200 1400 1600 1800 2000 2500 3000 3500 4000 4500 Gain (dB) 1.302 An Introduction to Mixed-Signal IC Test and Measurement - ~O 0 V ~O -i\ Gain (dB) -40 / V / -60 -so -100 / 10 100 1000 1'10.6 -6. 1'10 Frequency (Hz) Figure 8.0 -60.9 -1.3 -3.0 Freq(Hz) 5000 6000 8000 >8000 Gain(dB) -36.0 -21.66 50 100 200 300 400 500 600 700 Gain(dB) -70.0 -41. Table 8.0 Undefined r'- k.0 -25.4 -3.

5 -15.0 -0.0 -0.3 -3.2 -5.0 -41.7 -2. Table 8.4 -63. I' -20 V -40 L L /V Gain (dB) -60 -so V -100 10 100 1000 1'10" 1'10 Frequency (Hz) Figure 8.0 -21.20.0 0.9 0.9 -1.0 -60.0 -4. . C-message weighting filter.0 -10.0 Freq(Hz) 3500 4000 4500 5000 >5000 Gain(dB) -36.0 Freq(Hz) 1000 1200 1300 1500 1800 2000 2500 2800 3000 3300 Gain(dB) 1.6 -2. C-Message Weighting FilterGains Freq(Hz) 60 100 200 300 400 500 600 700 800 900 Gain(dB) -70.0 -43.24.6 -6.Chapter8 .6 -8.0 Undefined SeeNote Note: Gain above 5kHz shall decrease by at least 12 dB per octave until-50 dB.4 -3. / Analog ChannelTesting 303 0 .

In order to run the same program multiple times and obtain a different number sequence each time but with identical statistics. a different set of filter gains must be calculated using this interpolation method. Exercises 8. Ans. the seed . during the first execution of the test program. To create a noise signal with a DC value of Voc and RMS value of Vrms we make use of the following linear transformation Noise = VDC + Vrms~ (8. the second block models the nonlinear input-output transfer characteristic. On subsequenttest program executions. Calculate the gain of a Psophometric weighting filter at FFT spectral bin 413 of a signal that was digitized at 16 kHz using 2048 samples. they are stored in an array for future use. To model the noise of the channel we make use of a normally (Gaussian) distributed random number generator available in MATLAB called randn. This number generator will produce a sequenceof independent (uncorrelated) numbers whose statistics are normally distributed with zero mean and unity standard deviation.7. Once all the gains for each weighting filter have been calculated.20Hz. weighting filter gain values should be calculated only once.7 8. Calculate the higher of the two frequencies of a C-message weighting filter that correspondto a gain of -0.55 dB. Through the appropriate software model. j " Mathematically modeling the behavior of an analog channel using MATLAB or some equivalent software is an important step for understanding the test methods described in this chapter.-. -6.27) where ~ is a random number generated by randn.97 dB. Application of the filter gains is a simple matter of multiplying the FFT results at each spectral bin by the filter gain at that bin.22. and the third block models the frequency responsebehavior of the channel.25. Ans. 8. To save test time.1 SIMULATION OF ANALOG CHANNEL TESTS MATLAB Model of an Analog Channel . This requires that we divide the analog channel into three components as shown in Figure 8.304 An Introductionto Mixed-SignalIC Testand Measurement 1_1111 For each different combination of sampling rate and sample size in a test program. The first block models the presence of noise in the channel. 8. To begin we must first model the large-signal behavior of an analog channel in the presence of noise. 1260.23. the appropriate filter gains can be applied to the results of the FFTs to make weighted measurements. we can apply a coherent test signal and analyze the responseof the channel using Fourier analysis as if one collected the data directly from a tester..

25. The nonlinear input-output transfer characteristic of the analog channel is simply modeled by expressingthe output signal in terms of the input signal through a power-series representation describedby 2 3 Vout=CO+ClvIN+c2v/N+cIN+. al=0. (8. Now to put it all together. low-pass.5. we shall limit our discussion to a first-order digital filter described by the following difference equation: vOUT (n) =aOvIN{n)+alvIN {n-l)-~vOUT (n-l) (8. Calculate the mean and standard deviation of the signal to third harmonic distortion ratio. the frequency response behavior of the channel can be modeled using a digital filter described by an nth-order difference equation. While the topic of digital filters is beyond the scope of this text.'.17 Consider a low-pass amplifier described by parameters ao=0. and c3=0.5.g.29) Through the application of z transforms. Repeat the simulation 10 times using a different seed each time. e. etc. this is achievedby passing the seednumber s to randn via the statementrandn( 'seed'.4 kHz with a 1-V RMS input signal.- N0 is e VOUT VOUT Output Inp freq Figure8.01. the normalized frequency response behavior of this filter is found to be 1 ~{f) Vin l = [ao +al cos(2Jrf)f [1 +~ cos{27rf)f +[ al sin {2Jrf)f +[~ sin (27rf)J2 Parametersao.5. al=0. cI=I. Example8. For example. In MATLAB. number that is used to initialize the random number generator should be changed. . Analog ChannelTesting 305 11111111. Simulate the behavior of the amplifier using MATLABin the presenceof a noise signal with zero mean and an RMS value of 1 mV. co=O. with ao=0.. c2=0.28 ) Finally. bl=1. A nonlinear modelof an analogchannelwith additivenoise. and bl are selected to control the shape of the filter response.5 and bl=l. The digitizer is set to collect 256 samplesat a rate of 16 kHz.1111111111111- Chapter8 . Compute the signal to third harmonic distortion ratio of the amplifier at approximately 1.OOI. high-pass. aI. let us consider the following example. s). we obtain a low-pass Butterworth responsewith unity DC gain.

306 An Introductionto Mixed-Signal Testand Measurement IC Solution: To begin. % filter coefficients z(1)= aO*y(1). NOISE=VDC+VRMS*randn.4375 kHz. y(n)=cO+c1*x(n)+c2*x(n)A2+c3*x(n)A3.5.5. output signal: z % % noise model s=1. % magnitude of spectrum Z units of dBV -x - - % AC Terms magdBV _Z = 20*log10(sqrt(2)*abs(Z)). M=23.4 kHz. c2=0. VRMS=1e-3. c1=1.4-kHz test tone. the fundamental frequency is 16 kHz / 256 or 62. randn('seed'. let us design the parametersof the 1. z(n)=aO*y(n)+a1*y(n-1 )-b1 *z(n-1).z(O)=Oinitial conditions for n=2:N. % input-output transfer characteristic cO=O. % . % % Amplifier model: input signal: x. = magdBV_Z(N/2+1) =20*log10(1/sqrt(2)*abs(Z(N/2+1))). we will obtain a test frequency of 1. x(n)=x(n)+NOISE. % frequency response behavior aO=0.s). b1=1. end. end. P=O. end. which is quite close to the desired 1. A=sqrt(2).01. % y(O)=O. x(n)=A *sin(2*pi*M/N*(n-1 )+P). The MATLABcode that describes the amplifier and its input test signal is listed on the following pages. % % FFT analysis on the output signal % Z=fft(z)/length(z). % DC & Nyquist Terms magdBV_Z(1) 20*log10(abs(Z(1))). for n=1 :N. or n=1 :N. % initialize the RN generator VDC=O. Also listed is the code for the Fourier analysis of the output signal. c3=0. a1=0.001. With N=256 and F.5 Hz.s=16kHz. Using M=23. end. % % Coherent signal definition % N=256. for n=1:N.

. . . . .. . -20 . . . . . . magdBV_Z(1 :N/2+1» % % compute distortion metrics 5=10A(magdBV _Z(1 *M+1 )/20). . . . . . . . .26. . . . .. .50071 V. . . .26. . . . . . . . . . ... . . . . . . . . . . . . . . . .21. . . . . . . . and the RMS value of the third harmonic is 0.28759 mV RMS =64. Here we find that the RMS value of the fundamental is 0. . . . . . . . .50071 VRMS 10 ( H3 ) =20 10 glO glO 0. Analog ChannelTesting 307 plot(0:N/2. . . . . . . . . ~ . :::::: . . i. . . . . . . ~ . . . . . . . . .. . . . . . . . . . i ~ i : ~ ~ .28759 mV.MATLAB analog channel model output spectrum (dBV). . the signal to third harmonic is S j 3rd (dB) =20 0. . . % %end The spectral data that result from the first MATLAB simulation are shown in Figure 8. . . . 5N3rd=20*log10(5/H3).. . The results are tabulated in Table 8. . . . ~: . . ~ . .:. . . -40 . . . . . . . . . . . . . . . . . . : -100 -120 0 20 Bin Figure 8. :: .. . .. . . . . . . . ~ .816dB ~ ( ) Next. . 0 . .Chapter8 % plot spectrum . . . . Hence. H3=1OA(magdBV_Z(3*M+1)/20). . . . -80 : . . we ran the simulation nine more times with a different seed each time. . . . . . . . i Output spectrum (dBV) -60 . . . . .

3).24979 0. even though all the tests we have discussed so far are purely analog in nature.50080 0. For instance. MATLAB AnalogChannelModelTest Results RN Seed 1 34 65 1111 653 897 7775 5554 88898 23157 Signal (V RMS) 0. as this example demonstrates. Unfortunately.0902 dB.22247 0. then to guard against the variation that occurs with noise the test limit should be raised by an amount related to the standard deviation of the underlying noise distribution (see Section 4.655 65.995 65. 65 dB. we cannot calculate the gain of a DAC in volts per volt.805 65.017 65. 8.50079 0.720 66.36339 dB.50073 0.25223 0. say.28159 Mean Value: Standard Deviation: Signal to Third Harmonic Ratio (dB) 64.36339 As is evident from Table 8.28759 0. These same tests are perfonned on sampled channels.36339 dB (same as that in the table).31756 0. If the data sheet called for a device with a signal to third harmonic ratio greater than. which may include DACs and ADCs. and other sampling circuits. In Chapter 9.50073 Third Harmonic (mV RMS) 0.50079 0.000 different devices would escape the test and be labeled as good devices. Nevertheless.27865 0. three standard deviations to 65 dB + 3 x 0. ADCs. only 13 out of 10. In this way.50071 0.726 dB with a standard deviation of 0.987 65.50077 0. switched capacitor filters.648 65. For example.3. "Sampled Channel Testing.308 An Introductionto Mixed-Signal Testand Measurement IC Table 8.36339 dB. . These channels require some slight differences in measurement definition.037 66. the average value of the signal to third harmonic is 65.726 0. because a DAC does not have a voltage input.582 65. say. a good device can be incorrectly rejected. many of the measurement techniques are almost identical in nature to purely analog tests." we will continue developing DSP-basedtesting techniques as they apply to channels containing DACs.50077 0.816 65.21.21.22068 0.22915 0.50073 0. then the limit should be raised by.25935 0.8 SUMMARY This chapter provides a basic foundation for DSP-basedmixed-signal testing. if the effect of noise is assumed to be nonnal with a mean value of 0 dB and a standard deviation of 0. or 66.50076 0.

An FFT analysis reveals a signal amplitude of2.5 V.0.: . differential signal into peak. What is the total RMS value of a multitone signal consisting of sixteen tones having an RMS value of25 mV each and twenty-four tones having an RMS value of 10 mV each? . Detennine the gain of the following channels: (a) Vau!=0. 53. What is the frequency of the test signal? What is the absolute gain of the channel in VN? In dB? 8. What is the amplitude of this signal? What is its phase?What is its RMS value? Express the signal amplitude in dBV units. single-ended signal.1 Vi~+0. differential.l V RMS in spectral bin 301.. 544. An analog channel is excited by a I-V RMS single-ended sinusoidal signal from an arbitrary wavefonn generator. -3.99 Vin (b) Vau!=0. Signals are present in the following FFT bins: 31..01 Vi~-RMS (a) What is the gain error of the channel at an input level of2.0 V RMS? (b) What are the gain tracking errors at input levels of 3.lOO V.8. What are the frequencies of the corresponding signals? ~ 8. A digitizer captures 2048 samplesof a signal with a sampling rate of 32 kHz.5 V peak-to-peak. Analog ChannelTesting 309 Problems 8. G = 2.01 Vi~ ( c) Vau! =ao+alVin +a2Vin 2 +a3Vin 3 +. 8. " 8. An FFT analysis reveals that a particular tone has a spectral coefficient of -0.1+2Vin +0.1+0.! .+aNVin N (d) VaU/ 4 tan-I (Vin) = 1 f 8.1. 8. -6. (c) 100 mV RMS. The gain of an analog channel as a function of the RMS signal level at its input is ~ assumed bedescribed thefollowing to by equation. when the O-dB reference level corresponds to a 3. (b) 0. 1011.707 and b))=O.414 V peak.5 V RMS if the ideal gain is 2.3. An FFT analysis reveals that a signal is present in the eleventh bin with a spectral coefficient described by a))=0. 8.1-0. r . . 54. differential signal into dBV units. single-ended signal into dBV. and -12 dB. 527. 0. The output of the channel is digitized at a rate of 32 kHz and 1024 samples are collected and stored in memory.4. 749.0 V N? What is the gain error when the input is increasedto 4.5-j0.0 V RMS input level? Plot the gain tracking error as a function of input level in dB.6.2. What is the amplitude of this tone? What is its phase?What is its RMS value? Express the signal amplitude in dBV units.7. The small-signal gain of a channel is defined as the derivative of the output voltage with respect to the input voltage..111111111- Chapter8 .1 Vin-RMS +0. Perfonn the following signal conversions: (a) 1. single-ended signal into dBm units at 600. (d) 700 mV RMS.5.

jO.0063 0.2768 -0.0000 .12.0228 .0019 0. 7064 0.jO. in VN? What is the relative gain (dB) of the amplifier at each frequency if the reference gain is based on the gain of the first tone? 8.jO. determine the group delay distortion of this channel.843 1 -0. 8. The frequency responsebehavior of an amplifier is measuredwith a I-V RMS multitone signal consisting of eight equal-amplitude tones.335.jO.97 Hz was -2.6575 Output 0. An FFT analysis of the output samples reveal the following output signal amplitudes (RMS).0309 .349.0107 . 8.3 Hz was found to be -0. Using log/log interpolation.00006 0.5488 0.OOOO (a) What is the RMS value of the input and output signals as a function of frequency? (b) What is the phase of the input and output signals as a function of frequency? Limit the range of the phase of each tone to :1:180 degrees.11.6338 -0.13.310 An Introduction to Mixed-Signal Testand Measurement IC 8. in increasing frequency order: 353.7735 .3363 0. The frequency response behavior of a frequency selective analog channel is measured with a multitone signal consisting of eight tones.001. What is the amplitude of each tone if they are all equal in magnitude? 8.500 and 20.jO.7535 + jO.9.9418 . A data sheet calls for the -1 dB gain point of a low-pass filter to occur between 19.jO.jO.6186 -0.0004 + jO.jO.8435 0. What is the absolute gain of the channel at each frequency. A frequency response measurementwas made and the gain at 19. An FFT analysis of the input and output samplesreveal the following complex spectral coefficients (in V): FFf Bin 0 1 2 3 4 5 6 7 8 Input 0.331.jO.jO. determine the frequency at which the gain is -1 dB.jO.jO.4 dB. (c) What is absolute gain of this amplifier as a function of frequency? (d) What is the relative gain of this channel as a function of frequency if the reference gain is based on the gain of the tone corresponding to the fourth FFT bin? (e) What is the phase shift (in degrees) of the analog channel as a function of frequency? Provide an unwrapped description of the phase.jO.4896 . (f) What is the group delay of this channel? Also.000 Hz.81 mY.7078 .9609 .158.4663 0.9999 -0.7132 + jO.8374 0. A fifteen-tone multitone signal of 1 V RMS is required to perform a frequency response test.10.9727 -0.486.9609 .257.2319 + jO.8270 .5466 .314.2768 -0.8208 .01 dB and the gain at 20. An FFT analysis of the output of an amplifier contains the following harmonically related spectral amplitudes: .5371 + jO.

Vout ao+alVtn+a2Vt~ = +a3Vt~. Detenninethe frequencies second-order third-orderintennodulation of and frequencies. Vout=aO+aIVtn+a2Vt~+a3V~.3 kHz. 8. and the fourth at 5.01mV 311 FFT SpectralBin 101 202 303 404 505 (a) Whatis the signalto second hannonicdistortionratio? (b) Whatis the signalto third hannonicdistortionratio? (c) Whatis the signalto total hannonicdistortionratio? (d) If the RMS value of the noise component 125 mY.17. What are the third-order intennodulationproducts(amplitudeand frequency)producedby this amplifier if the input is described by Vtn (t) =Al sin (21l"fit) + A2 sin (21l" 2t) . An amplifier's input-outputbehaviorcan be described mathematically the following by third-order polynomial.555V 10mV 1 mV 0.one at 1.14.707V 31 ~V 42 ~V 11~V 4~V .3kHz.1 kHz.0V RMS sinewaves. A multitonetest signalconsists a sumof four 1. An FFT analysis reveals the following spectral amplitudes: FFT SpectralBin 0 1 2 3 4 5 6 7 8 RMS Voltage 2300~V 32 ~V 14~V 12~V 0. 8. A digitizer sampling at 4 kHz captures 16 samples of a I-kHz sinusoidal signal corrupted by noise. f 8. calculatethe signal to total is hannonicdistortionplus noiseratio. An amplifier's input-outputbehaviorcan be described mathematically the following by third-order polynomial. of anotherat 2.1S. 8. What is the signal to third hannonicdistortionratio of this amplifier if the input sinusoidalsignal is described by Vtn (t) =Asin(21l"ft).1 mV 0.16.Chapter 8 . anotherat 3. AnalogChannel Testing RMS Voltage 0.2 kHz. .

.02 and c3=0.5. (b) The relative gain of this channel as a function of frequency.ct=l. simulate the behavior of the amplifier subject to a 1 V RMS.5. Subsequently.5. at=0.5. c2=0. 1.Jfu? Express this result in dBm units at 50 . and c3=0. Using the MATLABmodel of the analog channel described in Section 8. (f) The signal to total hannonic distortion plus noise. at=0. The frequencies of the sixteen tones should be unifonnly distributed between 500 and 3500. 8.02.18.5.ct=l. ( c) The phase shift (in degrees)of the analog channel as a function of fr. at=0.5. c2=0. Subsequently.004. compute the following parameters associatedwith the output signal assuming that the digitizer collects 512 samplesat a rate of8 kHz: (a) The signal to secondhannonic distortion ratio.312 An Introduction to Mixed-Signal Testand Measurement IC (a) What is the total RMS level of the noise? (b) Detennine the signal-to-noise ratio of the channel. Set one tone to 1140 Hz and the other to 1328 Hz. 8. bt=l.0. co=0.7 with parameters ao=0. bt=l. Subsequently. ct=l.004. co=O. Assume that 512 samples are collected at a rate of 8 kHz. Assume that 512 samples are collected at a rate of 8 kHz.4-kHz sinusoidal signal in the presenceof a noise signal with an RMS value of 200 !lV.23.19. (d) The total RMS level of the noise that appearsat the output. (e) The signal-to-noise ratio.. (b) The signal to third harmonic distortion ratio. Detennine the root spectral density of a noise signal that has an RMS value of 543 !lV evenly distributed over a frequency range of 19 to 23 kHz.Provide an unwrapped description of the phase.uV /.01. sixteen-tone multitone signal in the presence of a noise signal with an RMS value of I mY. (d) The group d~lay and group delay distortion of this channel. co=O. simulate the behavior of the channel subject to a I-V RMS. 8. (b) The signal to third-order intermodulation distortion ratio. simulate the behavior of the channel subject to a I-V RMS. (c) What is the root spectral density of the noise over the 2-kHz Nyquist interval. 8. c2=0..22. and c3=0. What is the RMS value of a noise signal measured over a 12-kHz bandwidth if its root spectral density is 10 .compute: (a) The absolute gain of this amplifier as a function of frequency.equency. bt=l. 8. (c) The signal to total harmonic distortion ratio.7 with parameters ao=0. Calculate the gain of a C-messageweighting filter at the FFT spectral bin 73 of a signal that was digitized at 8 kHz using 512 samples.001.20. 8. two-tone multitone signal in the presence of a noise signal with an RMS value of 200 !lV. Using the MATLABmodel of the analog channel described in Section 8.compute: (a) The signal to second-orderintennodulation distortion ratio.5.7 with parameters ao=0.Hz and include the reference frequency of I kHz. Using the MATLABmodel of the analog channel described in Section 8.21.

Audio Measurement Handbook. c2=0.. Bob Metzler.02.004. 97075. August. simulate the behavior of the channel subject to a 2. inc. and c3=0. Analog ChannelTesting 313 8. Assume that the digitizer collects 512 samples at a rate of8 kHz.Chapter8 . Perform the simulation over an i1}put range of -80 to 0 dB in 5-dB increments. 1993.5. co=0. Audio Precision. Using the MATLABmodel of the analog channel described in Section 8. OR. Beaverton. References 1. Subsequently. p.LV. b)=I.5.5. cl=l.7 with parameters ao=0. compute the signal to harmonic distortion plus noise ratio as a function of the input signal level. a)=0.8-kHz sinusoidal signal in the presence of a noise signal with an RMS value of 500 !.24. 147 .

let us look at examples of sampled channels and how they are applied in systemlevel applications like cellular telephonesand disk drive read channels.three for the transmit channel and three for the receive channel.1 What Are Sampled Channels? Sampled channels are similar to analog channels in many ways. The similarities and differences between analog channel testing and sampled channel testing will be discussed later in this chapter. sampled channels operate on discrete waveforms rather than continuous ones. filters.1. switched capacitor filters (SCFs).C1{APTER 9 Sampled Channel Testing 9. The test requirements for sampled channels are very similar to those described in Chapter 8. DACs. sample-and-hold (S/H) amplifiers. and all the other tests common to analog channels. they require additional test considerations that are not applicable to continuous analog channels. signal-to-noise ratio. analog-to-digital converters (ADCs). 9.1. PSRR. CMRR. Discrete waveforms consist of a sequence of instantaneous voltage samples that are either representedas digital values or as sampled-and-heldanalog voltages. distortion. and cascadedcombinations of these and other circuits." However. Sampled channels are often tested for gain error. the sampled nature of the signals transmitted by sampled channels forces some additional considerations in their test requirements.though. while the receive (RECV) channel is the signal path that receives the far-end speaker's voice. The transmit channel of a digital cellular telephone includes a number of ADCs. aliased interference tones.1 OVERVIEW 9. A digital cellular telephone (Figure 9.1) contains at least six sampled channels . "Analog Channel Testing. Examples of sampled channels include digital-to-analog converters (DACs). First. The data stream is mixed with a high-frequency carrier signal so that it can be transmitted via radio waves to the cellular base station. Because sampled circuits may be subject to quantization errors. Unlike analog channels. and signal processing circuits that convert the speaker's voice into a modulated stream of digital data.2 Examples of Sampled Channels Sampledchannels form the interface between the physical world around us and the mathematical world of computers and digital signal processors. 315 . The transmit (XMIT) channel is the signal path that transmits the near-end speaker's voice. and reconstruction image tones. Both channel types consist of a signal transmission path from one or more inputs to one or more outputs.

Digitalcellular telephone diagram. which transmit data over telephone lines at audio frequencies. power amp) Display Keyboard I or Frequency synthesizer Figure 9. filters) Di ital r B b d/ RF interface ase. volume Figure 9. block The flISt step in voice transmission is to digitize the speaker's voice using an ADC connected to the cellular telephone's microphone. Since the IF signal is much lower in frequency than the RF signal. \1 -. .8 GHz or more). it can be generated using a DAC channel operating at a lower sampling frequency (Figure 9. ~ -+t?~[~~J-+<~~~1\ PGA A [\ .3).316 An Introductionto Mixed-Signal Testand Measurement IC Base station J~ XMIT RECV XMIT RECV . Unlike modems. depending on the type of cellular telephone. filter. XMIT channel Microphone V input V L ow-pass f .2. Voice-band .an ( . and digitize the speaker's voice (Figure 9.n MIC U EAR U . Iownoise amp.lt I er ADC ADC audio samples (to DSP) Mic. The RF transmission frequency is 900 MHz or higher. The digitized voice signal is then routed to either a digital signal processor or a specialized modulator logic block. RF section mixers.1. The voice-band interface circuit is a sampled channel that contains a number of circuits that amplify. Since it would be impossible to directly generate this 900-MHz modulated signal by feeding samples into a DAC (at a rate of 1. which converts the ones and zeros of the digitized voice samplesinto an amplitude/phasemodulation protocol similar to that used in computer modems. Voice-band XMIT(ADC)channel. cellular telephonesmust transmit the data into an antenna using a radio frequency (RF) power amplifier. rf (ADC Inte ace DAc:' PGAs.2). it is necessaryto use an RF mixer circuit to upconvert an intermediate frequency (IF) signal to the RF frequency range.n .

controlling the amplitude of an RF cosine waveform.5).econstructs the amplitude/phase-modulated data waveform. the receive Q-channel.4. : ' RF . Thus there are six separatesampled channels in this cellular telephone example: the voice-band interface transmit channel. sine Low-pass filter :: ~ downconverter Figure 9. By adding the RF cosine and sine waveforms together. the transmit Q-channel. The I-channel waveform is sent to an RF mixer circuit. the RF section of the cellular telephone t. The received data bits are downconvertedto IF I and Q channel signals by the RF section. This composite RF waveform is suitable for transmissionthrough the cellular telephone's antenna. digitized by an IF ADC channel. and the voiceband interface receive channel. I : . the transmit I-channel. ! : I Low-pass XMIT IF samples (from DSP) filter :: RF sine : RF upconverter Figure 9. Sampled ChannelTesting 317 RF cosine : .Chapter9 . I-channel Low-pass:: : Antenna . XMIT l-channel and a-channel.4 and 9. and . RF cosine Antenna : : I : : : I : Low-pass filter :: I-channel RECV IF samples (to DSP) Q-channel RECV IF samples (to DSP) : I RF : I . demodulated into voice samples by the digital signal processor. the receive I-channel. The receive channel works in a very similar manner. The sine and cosine amplitude samplesare then converted into analog waveforms using two separatemixed-signal channels: the in-phasechannel (I-channel) and the quadrature channel (Q-channel). and converted into audio voice waveforms by the voice-band interface circuit. Similarly. The digital signal processor converts each amplitude/phase pair of the modulation protocol into a sine amplitude sample and a cosine amplitude sample. except that the direction of the signal is reversedand the DACs are replaced by ADCs (Figures 9. the Q-channel waveform controls the amplitude of an RF sine waveform.3. RECVI-channel a-channel. XMIT IF samples (from DSP) Q-channel filter : .

and a wide variety of testing requirements are needed.f '-' ~E>~E~J-:~~f\ ~ ~ Low-pass DAC filter PGA 1\ V Earpiece output Ear volume Figure 9. DIAO channels characterized one or more digital signal are by . signal-to-noise. digital audio record and playback devices. etc. Digital audio channels are similar to the voice-band interface transmit and receive channelsof a cellular telephone.318 An Introduction to Mixed-Signal Testand Measurement IC DAC audio samples (from DSP) RECV channel .5. Before we look at these common tests in detail. The read coil signal is typically noisy and distorted by the physical properties of the disk's magnetic storagemedia. For convenience. the signal source and measurement quality degrades. and AIAO to refer to these four types of sampled channels. 9. and digital telephone answering devices (DTADs). A disk drive read channel is a sampled channel that is used to recover 1/0 data from the read coil of a disk drive read head. PSRR. Digital telephone answering devices. the sampled channels of a digital audio circuit must record and play back much higher-quality audio than that required for a telephone conversation. Other examples of devices containing sampled channels are disk drive read channels. However. Despite the wide differences in functionality and quality requirements. Voice-band RECV (DAC) channel. most sampled channels have a series of common test specifications. DIDO. One of the major challenges in read channel testing is that the signals operate at extremely high frequencies. AIDO. are more similar to telephones in that they do not need to record and play back especially high-quality audio signals. At higher frequencies.1. including gain error. analog in/digital out. The read channel must digitize the high-frequency signal generatedby the magnetic variations of the data stored on the spinning disk drive platter. depending on the end application of the channel. though. on the other hand. digital in/digital out. One of the major challenges in digital audio testing is that the signals are low in frequency but they have very tight signal-to-distortion and signal-to-noise specifications. Let us look at some examples of each of the four categories of mixed-signal channels to see how they operate on continuous and sampled waveforms. The read channel must clean up and correct the signal using a variety of analog and/or digital filters before data can be recovered. ATE testers are more adept at measuring and sourcing low-frequency signals with a high degree of accuracy. Falling into the digital in/analogout (DIAO) categoryare DACs and cascaded combinations of DACs and other circuits. we will introduce the notation DIAO. Clearly.3 Types of Sampled Channels Sampled channels fall into four basic categories: digital in/analog out. and analog in/analog out. let us look at the different kinds of circuits that can be classified as sampled channels. the uses for sampled channels are very diverse. making the highfrequency read channel difficult to test.

V t-\ Mic. In this test mode. overshoot. Furthermore. The cascadedcircuit has a digital input and a digital output.etc. A PGA ' s transmission channel consistsof an analog input and an analog output.it should be~ samples channel . While a digital filter can be tested as a sampled channel by measuring its frequency response. The third category is digital in/digital out (DllO). the PGA does not sample or reconstruct its signals in any way. even though it does have a digital input. since it converts a digital input into an output with analog characteristics (rise time. filters the samplesusing a mathematical algorithm. DllO circuits are actually quite common in mixed-signal testing. so it is considered an analog channel rather than a sampled channel. ADC audio {t U AnalogLoopback Path Loopback mode digital input '\. which accepts digital samples at its input. The digital control lines feeding a PGA are not generally used to transmit signal information.). analog in/digital out (AllO). Consider the analog loopback mode illustrated in Figure 9. Sampled ChannelTesting 319 Analogloopback multiplexer '\. /' PGA !\ Earpiece Output Ear volume Low-pass filter \j E DACchannel audiosamples Figure 9. Digital input digitaloutput(DIDO)sampledchannel(Ioopback mode). yet it is a mixed-signal sampled channel.~ Microphone PGA input Low-pass filter ".6.volume Loopback mode digitaloutput . so we cannot really consider the PGA to have a digital signal input. and produces digital samples at its output. I test inputs and one or more analog signal outputs.Chapter9 . a DIAO DAC channel's analog output is connected through a specialtest multiplexer to the analog input of an AllO ADC channel. as far as testing is concerned. ADCs and cascadedcombinations of ADCs and other circuits fall into the second category. Comparators and slicers fall into this category sincethey act as one-bit ADCs. Note that a programmable gain amplifier does not fall into this category. undershoot. A very high-speed digital line driver might also be considered a simple DIAO channel. AllO circuits are characterized by one or more analog signal inputs and one or more digital signal outputs.6. While it may not be obvious that a DllO circuit would have anything to do with a mixed-signal sampled channel. Another example of a DIDO sampled channel is a digital filter.

aliasing. Another example of AIAO sampled channels is the switched capacitor filter (SCF). and digitizer sampling rates must mesh with the sampling rate of the DUT. 9. sampling rate synchronization headaches.320 An Introductionto Mixed-Signal Testand Measurement IC noted that it can be tested much more efficiently and thoroughly using traditional digital methodologies. and aliasing. we are often burdened with very specific sampling rate constraints placed upon us by the DUT specifications. the transmit (ADC) and receive (DAC} channels in a codec device may be specified at a sampling rate of exactly 8 kHz. We will also look at the structure of the digital pattems that source and capture digital signal samples on the digital side of mixed-signal sampled channels. sampling them and applying a high-pass. In the next section we shall look at some of the sampling considerationswe face as we design cost-effective tests for sampled channels. In theory. Other than these constraints. imaging. low-pass. and that the various Nyquist frequencies are above the maximum frequency of interest. The tester's sampling systems must mesh with this sampling rate so the waveforms . since it does not contain any analog circuit elements. even though it never converts the analog signal into the digital domain. Otherwise. in which the digital output of an AIDO channel is looped back into a DIAO input.we only need to insure that the fundamental frequency of the A WG is related to the fundamental frequency of the digitizer by an integer ratio (usually a ratio of Ill). For example. such as quantization noise.2 SAMPLING CONSIDERATIONS 9. or other filter characteristic to the analog samples. and sin(x)lx rolloff characteristics associatedwith ADC and DAC channels. But since they introduce a sample-and-hold operation. S/H amplifiers and switched capacitor filters do not introduce quantization errors. since they hold nonquantized voltages using capacitors. coherent DSP-basedtesting is not possible. One of the main differences between testing analog channels and testing sampled channels is that the sampling rate of the ATE tester's digital patterns. In general.Difficulties arises from a number of factors. they suffer from all the same imaging. A third example of an AIAO sampled channel is the simple sample-and-hold (S/H) amplifier. it is considered a sampled channel. but it may exhibit quantization errors. Achieving a coherent DSP-based sampling system that meets the requirements of both the DUT's various sampling circuits and the ATE tester's various instruments can be quite challenging. however. Once we begin testing sampled channels. we are fairly free to choose whatever sampling frequencies we want. Since the switched capacitor output is a "stepped" waveform. Switched capacitor filters operate on sampled-and-held or continuous analog input signals. The resulting circuit has an analog input and output. sampled channelsare more difficult to test than analog channels.and extra complexity in the form of coherent sampling loops in the digital pattern. image and alias tones. just like any other sampled circuit.2. The data sheet for a mixed-signal DUT often requires a specific sampling frequency or list of sampling frequencies for each of the DUT's sampled channels. This sampled channel converts a continuous analog input waveform into a sampled-and-heldanalog waveform. The output of a switched capacitor filter is a sampled-and-held version of the filtered waveform.1 DUT Sampling Rate Constraints When making a coherent DSP-basedanalog channel measurement. An analog in/analog out (AIAO) sampled channel can be formed by placing a device in digital loopback mode. A WG sampling rates.

and digital signal outputs from an ADC channel. Ideally. The pattern also includes a feature not found in purely digital patterns: source and capture shift and load commands. digitizers.2 Digital Signal Source and Capture When testing mixed-signal devices. all sampling rates in the test program can be derived from this single master clock frequency using digital clock divider circuits. Figure 9. 9.- Chapter9 . such as sampling rates and output loading conditions. this mayor may not be possible. The most cost-effective testing for this type of device is simultaneoustesting of both the transmit and receive channel at the same time. called microcode instructions. In some cases.879962 MHz. we would run the risk of generating correlation errors between the tester and stand-alone bench equipment operating at 38.88 MHz clock to 40 MHz. most testershave constraints that limit the clock frequencies that can be generated or utilized by each instrument.88 MHz may actually fit the tester's constraints better if we shift it slightly to 38. Unfortunately. The DUT usually requires these samples to be applied and captured at a particular sampling rate. Of course. Sampl~d ChannelTesting 321 generatedand digitized by the DUT's sampled channels are coherent with the tester's A WGs. the tester must apply digital signal samples to the DUT's inputs and collect digital signal samples from its outputs. test time can be minimized using this approach. Again.it may be acceptableto force-fit the sampling rate of a DUT into a sampling system that is more agreeableto the ATE tester's instruments. determine when the data . Correlation errors in mixed-signal tests are often the result of minor discrepancies in test conditions. for instance. digital capture data rate. However. These often take a long time (25-50 ms) to settle to a stable frequency after their frequency setting is changed. A WG. is often required by the DUT to control the timing of the digital signal samples.88 MHz. This type of test requires that all sampling rates must be coherent.2. digital source data rate. including the transmit channel. a digital pattern rate that is divided from the tester's master clock by a factor of 2N may generate less sampling jitter than one generatedusing other divide ratios. Since digital divider circuits require no additional setting time. certain frequencies may result in a better quality of test than others. These pattern commands. It is often better to select a single master clock frequency and let the tester's low-jitter master clock generator stabilize to this frequency. It is much safer to use the exact specified master clock and sampling rate combinations outlined in the device data sheet. A frequency that is not ideal on one type of tester may causeno problem on another. called a sampling frame. A repeating digital pattern. this constraint is highly tester dependentand may not be an issue on some types of testers. The lower jitter may result in superior signal-to-noise ratio measurements. it is seldom acceptableto shift a clock by more than a fraction of a percent. It would seem that a tester costing one million dollars or more would be able to produce any sampling rate the test engineer desires. we may find that a device whose master clock is specified at 38. For example. Sometimes it is necessaryto switch the master clock back and forth between various frequencies. digital pattern frame syncs. For example. these constraints are highly tester dependent. Ifwe shifted the 38. This is one of the reasonsthat it is so difficult to convert mixedsignal test programs from one tester platform to another. and digitizer. Unfortunately.7 shows an example of a digital pattern consisting of a repeating frame. Even when a tester's clocks are highly programmable. and digital patterns. Yet another headache in selecting sampling rates is the long settling time of low-jitter frequency generators and/or phase-locked loops (PLLs). adding undesirable test time as the clock source stabilizes. digital signal inputs to a DAC channel. receive channel.

They also determine when the digital samples from the DOT will be stored into capture memory. Finally.dB. and digitizer must all be equal (or at least related by an integer ratio). Mixed-signal digitalpatternexample. ready to be inserted one sample at a time into the looping frame pattern.7 is specific to a particular ATE tester.322 An Introductionto Mixed-SignalIC TestandMeasurement for source memory will be substituted in place of the normal pattern data. the digital source and capture instruments have their own fundamental frequencies. The waveforms stored in source memory are computed by the tester computer during an initialization run. the samples collected during the looping frame pattern are stored one sample at a time into capture memory using the STORE command on the fifth vector. Other microcode instructions initialize loop counters.7.. Likewise. the example pattern in Figure 9. Naturally. the master clock and frame sync are usually required to operate at very specific frequencies. etc.. the FSYNC frequency may be specified to run at a rate of MCLK divided by 16. For example. . In Figure 9. the microcode SHIFT commands determine the time at which of each bit of the data word is shifted into or out of the DOT.- HALT . Figure 9. The sampling frame usually consists of one or more high-frequency clocks and one or more frame synchronization signals that determine the timing of the input and output sample data stream. RMS value.8 shows these timing relationships. --- Capture one ADCsample Finish the 12-cycle frame Loop back to ADC_DAC . a multibit parallel data word is written into the RFill pin group using a W character linked with the SEND command on the third vector.- . defined as the sampling rate divided by the number of samples sourced or captured. If the DOT has a serial input or output.d9. and ramps can be stored into various locations in the source memory. determine loop endpoints. multitones.- 1 1 0 1 -- -. Like A WGs and digitizers... The captured samples can then be moved into an array processor or tester computer for DSP analysis (DFTs. a digital audio device data sheet may specify that DAC channel samples are to be applied in parallel on DUT pins DAC7-DACO on the second rising edge of the master clock (MCLK) after the frame synchronization signal (FSYNC) goes low.W . stop the pattern. R F I R D RFIA (H) R F I W R P C M D C pi n LABEL COMMAND RFID11 dig_src pi n RFID11 dig_cap XXK 1 1 0 1 1 0 1 Prepare to collect 512 samples Send Frame Sync (PCMDCK) Source one DAC sample - RFID (H) S S S COMMENT SET_LOOP 512 ADC_DAC: START TRIG SEND REPEAT 7 END_LOOP ADC_DAC ... the data sheet may specify that the ADC channel samples will be available at ADC7-ADCO on the third rising edge of the master clock after FSYNC goes low. Signals such as sine waves. Likewise. - .dO .7..X STORE . digital capture.dO. but all true mixed-signal testers provide a looped source and capture capability.. FFTs. Coherent DSP-basedtesting requires that the fundamental frequency of the digital source. In addition to the timing of the digital signal data inputs and outputs.until 512 samples are collected Figure 9.. A WG. etc). average value. Different testers will use a variety of notations to specify the STORE and SEND operations.

There are many more subtle problems that occur when the test conditions are shifted in this manner. mixed-signal channels are usually specified at a particular frequency. When making coherent DSP-basedmeasurements. For example. An interesting question arises when we try to test mixed-signal devices on digital testers: Do we really need source and capture memory to test mixed-signal devices? Let us look at the alternative.. as shown in Figure 9.Chapter9 . The frequency of these clocks (relative to the sampling frequencies of the tester's A WGs and digitizers) must be quite accurate to synchronize the fundamental frequencies of all the various sampling systems._~~S£~~~~O~_k~ ~~:--~J DAC7 -DACO DAC sample 1 : ! ADC7 -ADCO --D !O .9. The performance of the DUT may shift slightly as well. .. the cutoff frequency of a switched capacitor filter changeswith its master clock.72016460905. If a frame consists of 1024 digital samples. It may be necessaryto switch to a non-power-of-2 sample size or it may be necessaryto shift the master clock slightly to allow a coherent measurement. MCLK . For this reason it is usually not acceptable to round off the clock periods to the nearestnanosecondor even the nearestpicosecond. by contrast. it mayor may not be possible to generate certain sampling rates. : : between frame syncs DAC sample 2 0 0 ADC sample 2 Figure 9. I FSYNC ~.ns) period. . Shifting the master clock by 1% will shift the 3-dB point of the filter by I % as well. so it is best to test the DUT at exactly the specified frequenciesto avoid correlation errors. I . Their timing can often be rounded off to the nearest nanosecondto simplify the automated test pattern generation (ATPG) process. are often tested at frequencies higher or lower than the normal operating frequency. Digital circuits. For example. Sampling frametiming diagram. a device with a master clock of 41. Mixed-signal test programs may consist of dozens of these patterns. then the pattern would require 102400 vectors. Notice that the frame sync pattern is identical from one DUT sample to the next. the test engineer should take care.there is a huge difference between a 25-ns master clock period and a 38._~.~. When shifting the master clock to accommodatethe tester's instruments.327 MHz may produce a fundamental frequency that cannot be easily matched by the tester's high-performance digitizer.8. ADC sample 1 Unlike digital circuits..88-MHz (25. I. rather than a particular period. A mixed-signal DAC pattern could be written as a "flattened" series of sampleswith a repeating digital sample frame. I . Depending on the tester's architecture.each of which requires a 100 vector frame.9 would require many megabytes of vector memory. Sampled ChannelTesting 323 . Testing mixed-signal devices using patterns such as the one shown in Figure 9. A frequency accuracy of one part in a million or better is required to achieve acceptable signal-to-noise performance in coherent DSPbased tests. including the DUT's sampling rates.

- ..dO 1 .d9.11 shows how DUT output data is captured within a repeating capture frame. Also.dEB91 .d9. The Ws and Xs are place holders for digital signal samples.324 An Introductionto Mixed-SignalIC Testand Measurement an obvious waste of digital pattern memory.dO .10 shows how source memory and vector memory are combined to weave together the digital frame data with the digital samples. involves a serial shifting operation that takes multiple data clock cycles.0 . Similarly. dO 1 . Notice that the frames in Figure 9.dO.X 1 .- REPEAT 8 SEND STORE REPEAT 8 SEND REPEAT B Repeat this pattern STORE 0 1 .0 1 . what if we suddenly needed try a frame of 102 vectorsratherthan a frame of 100 vectors? We would haveto to manuallyinsert the new vectorsor digital samples into the huge flattenedvector set or use a cumbersome digital pattern compiler to recreatea totally new digital pattern. The samples are specified with a digital signal sample notation. Flattened mixed-signal DACframes. such as W or X instead of 1 or O. Digital samples can be sourced to and captured from the DUT in either a parallel fonnat or a serial fonnat.. In parallel fonnat. by contrast. What if we neededto quickly characterize DAC's a performance using a frequencyof 2 kHz insteadof I kHz? Likewise. which are either read from source memory or written to capture memory. Figure 9. RRP F FC I I M R WD DRC RFID (H) 555 pi n RFID11 LABEL COMMAND pi n RFID11 RFIA dig_cap (H) TRIG XXK COMMENT dig_src START . Versatile mixed-signal testers include built-in hardware features that ease the conversion from parallel to serial and serial to parallel data fonnats. Only the value of the DAC input data and ADC output data changes from one frame to the next.- .d2991 .dB --1 1 0 1 1 1 Prepare to collect 512 samples ADC_DAC SEND STORE .easily modifieddigital patterns mixed-signal for tests.. as previously shown in Figure 9..9 pose a debuggingproblem. Fortunately.d94 . the data for each sample are loaded into the device with a single clock cycle.dB . Serial fonnat.. Figure 9.- for 512 samples Figure 9..9. A mixed-signal tester allows digital samples to be inserted into or extracted from a repeating frame loop..X 1 0 1 Source 1st DACsample 1 1 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 Capture 1st ADCsample Finish the 12-cycle frame Source 2nd one DACsample Capture 2nd ADCsample Finish the 12-cycle frame Source 3rd DACsample Capture 3rd ADCsample Finish the 12-cycle frame .- .- . A true mixed-signal tester uses source and capture memory to implement a type of vector compression that is ideally suited to mixed-signal sampling frames.d9..1 .dB .7.X 1 . . flattenedpatternssuch as the one in Figure 9.9 consist of the samebasic pattern of ones and zeros for each sample. mixed-signal testerarchitectures provide sourceand capturememoryto allow compact.. as shown in the previous examples.

: I 00000000 00 10 01 : : : I ' : : : . Sourcememorysampleinsertion.. 01 JUMP LOOP1 .11. . : . Mixed-signal testers accommodatethe MSB-first / LSB-first translation using built-in digital logic in the digital subsystem.. . 00000011 XXXXXXXX .samples : . LABEL:LOOP1: .l. : : . the test engineer does not have to spend additional time writing software translation routines... Using the hardware serial/parallel conversion features. a mixed-signal tester should be capable of shifting the digital signal data into or out of the DUT with the most significant bit (MSB) first or the least significant bit (LSB) first. 00 10 : 00000001::i::J°0000000 i : .::~~~fP1: 00100100 STORE' . WWWWWWWW SEND :: ' : XXXXXXXX I I.. Capturememorysampleextraction. j .10010010: " JUMP LOOP1: 11101001 ~ ' : i : : : I. I . 11111111 00000000 01 00 : : ' .. when capturing serial data from a DUT's digital signal output. : . data are loaded into source memory in a parallel format. y~ . Likewise. 00000010 00000011 . In addition to the parallel/serial data conversion. 00000000 00 : . : : . Sample~ ChannelTesting 325 Digital pattern with repeating frame loop ~ Combined digital vectors (OUT stimulus) samples j r . i Digita. Digital vectors (OUT stimulus and output samples) j : r . j LABEL:LO .1pattern with repeating frame loop --"' 00 10 01 Capture memory waveform . Figure 9.. '00000001 XXXXXXXX 00000000 : ' 00000010 XXXXXXXX 10 01 : . .. The digital subsystem hardware performs a parallel to serial shift operation controlled by digital pattern microcode instructions such as SEND and SHIFT. : 00000000 00 10 01 00 .Ji . . : 00000000 'xxxxxxxx ' 11111111 : : ..11-Source ~emory wave orm Chapter9 ..10. data ((an be translated from serial format to parallel format before they are stored into capture memory. When supplying serial data to a DUT's digital signal input. . : : : : I. : 11101001 11111111 10 01 :: : 'Fi9ure 9. : 00100100 10' 11111111 00000000 10010010 01 00 10 . Jillll...

mixed-signal ATE testers cannot predict every data fonnat.13.2. together with the capture memory. Occasionally the test engineer will run across an "oddball" data fonnat that requires an explicit software bit scrambling operation. a central office codec may have a transmit (AD C) channel and a receive (DAC) channel that both operate at a sampling rate of 8 kHz. For example. it just adds some overheadto the test development process and makes the code a little harder to follow. This scrambling operation must be perfonned in software before the samplesare loaded into the source memory. and signal-to-noise of the DAC channel can be tested while the same tests are being perfonned on the ADC channel. frame syncs. The fourth sampling system consistsof the ADC and the capture memory. a device may have a 14-bit digital signal fonnat that must be shifted into the device serially. followed by the most significant 6 bits shifted into the DUT MSB first. Before we want to use the tester's parallel to serial shift hardware. the absolute gain. distortion. the test engineer will often test both channels at once to save test time. Notice that the order of the bits is scrambled. The third sampling system is fonned by the source memory and the DAC channel.12 shows why this is an odd fonnat. Figure 9. The A WG is one sampling system and the digitizer is another.13. we have to produce data samples that have the same scrambled bit order. we have shown four different sampling systems operating simultaneously.13. etc. initialization patterns. The AC measurement system for simultaneous ADC and DAC testing is shown in Figure 9. In order to ensure that each sampling system fonDS a coherent DSP-basedmeasurement. with the least significant 8 bits shifted into the DUT MSB first. This is not a catastrophic problem. Scrambled bit order in a two-byte interface.12. For example. The AWG produces a test tone with frequency Ft that stimulates the ADC channel of the DUT.326 An Introductionto Mixed-Signal Testand Measurement IC MCLK WRSYNC lJ 07 00 U lolollllll~ SDATA-i11111111 013 08 013012011 :><:><-::: 010090807 060504030201 00 Figure 9.3 Simultaneous DAC and ADC Channel Testing When a DUT contains two or more channels that can be tested simultaneously. Unfortunately. . saving test time. the digital subsystem must also provide any necessaryreset functions. For example. In Figure 9. In addition to the digital source and capture memories shown in Figure 9.the sampling rate and the number of samples collected must be chosen in consideration with the other sampling systems. Consider the situation involving the A WG and ADC. 9. master clocks. The various parameters of these two channels can be tested in parallel.

(9. : OUT OUT antialiasing UT AOC :f \ : i-. : : : I : V : ATE digital filter : : I I . ~ ! OUT antiimaging filter I : : : I I I I ~ ! j : I : : : I ~ Digitizer ~ Antialiasing filter .Chapter 9 . I Waveform: capture I memory ~~ Figure 9. : . Assuming that the AWG is operating at a sampling rate of Fs-AWG cycles through NAWG and samples. : : I .2) Ff-AWG .1) as is F. : ! Waveform V source memory !\i : : ! A\ ! . canexpress testtonefrequency we the as F=MAIVG. : I I J .!: : : I I I .-AIVG 1'. ATEdigital f\:~ ' :I '. I I I I I .=MAWGFr-AWG where the fundamental frequency for the A WG is given by -~ N AWG - (9. I I : I I ~ . We can also expressEq. Sampled Channel Testing : j : AWG i-. Simultaneous DACand ADCchanneltesting.N AIVG I where MAWG a spectral bin number for the A WG.13.: V .f-\ \: .

Recognizing that Eqs.2) and (9.4) or F. we can state that the requirement for coherencebetween the DAC and digitizer is M DACF f-DAC M DIGlTlZERF f-DIGJ77ZER = (9. this also implies that the test frequency is equal in both the ADC and DAC channels as MAWG=MADC =MDAC =MDIGJ77ZER (9. 6) ADC The number of samples collected in the capture memory NADC should be made a power of two in order for the sample set to be compatible with the FFT analysis that will follow.' rt (9.9) Of course.10) .7) Any two sampling systemsthat satisfy this equation will be coherent with one another. Following a similar development. This requirement is met by any combination of sampling rates and number of samplesin which Ff-AWG Ff-ADC = =Ff-DAC =Ff-DIGJ77ZER (9.M ADC ~ NADC 1. (9.328 An Introduction to Mixed-Signal Testand Measurement IC As the ADC together with the capture memory forms another coherent sampling system with sampling rate F S-ADC NADC and samples.=MADCFf-ADC (9. The simplest sampling combination that meets all coherence requirements is one in which all four sampling systems have the same fundamental frequency.5) where MADC a spectral bin number for the ADC and Ff-ADC the fundamental frequency for the is is ADC given by F -~ - f-ADC N ( 9 . their sampling rates and number of samples are not independent.5) are equal in a coherent sampling system allows us to write the following expression MAWGFf-AWG =MADCFf-ADC (9.8) Since the ADC and DAC samples are usually collected using a single digital pattern loop.we can also write the test tone frequency as .

625 Hz (matches DAC) . Sampled Channel Testing 329 In the 8-kHz codec example.625 Hz fG: Fs-AWG= kHz x 4 = 32 kHz 8 NAWG= 512 x4 = 2048 Ff-AWG = 32 kHz / 2048= 15. This is useful for testing the DAC's anti-imaging low-pass filter. if we want to collect 512 samples from the ADC channel while sending 512 samples to the DAC channel. free of images. Similarly. For example. Often test engineers will double or quadruple the sampling rate of the digitizer and/or A WG to give a higher Nyquist frequency.-ADC=8 kHz lVADC 512 = Ff-ADC = 8 kHz / 512 = 15. we could use the following sampling system Fs-ADC =Fs-AWG =8 kHz NADC =NAWG =512 Fs-DAC = Fs-DIGITIZER= 8 kHz N DAC = N DIGITIZER= 512 In this case. we have to double or quadruple the number of sampleswe collect with the digitizer or source with the A WG. A higher Nyquist frequency allows a digitizer to detect more frequency componentsin the output spectrum of a DAC.625 Hz. To maintain fundamental frequency compatibility with these higher sampling rates. For example.625 Hz Digitizer: Fs-DIGlT/ZER 8 kHz x 2 = 16 kHz = NDIG/TIZER 512 x 2 = 1024 = Ff-DIGlTlZED = 16 kHz /1024 = 15.Chapter 9 .625 (matches Hz ADC) DAC: Fs-DAC= kHz 8 NDAc=512 F/-DAC= 8 kHz / 512= 15. a higher Nyquist frequency allows an AWG to produce a cleaner test stimulus. the simplest sampling system is fonned by choosing an 8-kHz samplingrate on all four systems. each of the four sampling systems has a fundamental frequency of 8 kHz/512 = 15. we can use the following sampling system to double the fundamental frequency of the tester's digitizer while quadrupling the fundamental frequency of the A WG: F.

625 Hz. or 140.625 Hz x (3/2) = 23. M DAC = (3/2)M DIGI11ZER. Therefore. example. so we need to use the minimum number ofDAC samplespossible (no more than 1024 samples). as can be seenfrom Eq. in the previous example we could have used the following sampling system: DAC: Fs-DAC= kHz 8 NDAC=512 Ff-DAC=8 kHz / 512 = 15. Due to sampling constraints inherent to the tester.625 Hz Digitizer: F. the spectral bins in the DAC channel are also related to the spectral bins in the digitizer channel in much the sameway. Example9.4375 Hz Clearly. this same frequency will appear at spectral bin 6 in the FFT of the digitizer's samples.11) For instance. (9.-DIGITIZER = 8 kHz x (3/2) = 12kHz NDIGITlZER 512 = Ff-DIGITIZER = 8 kHz x (3/2) / 512 = 15. the test engineer will occasionally find that the use of an integer-ratio sampling approach is the best way to achieve a coherent sampling set given the constraints of the DOT and ATE tester. However. Since the digitizer's fundamental frequency is 15.e. In this subsection. i.330 An Introductionto Mixed-Signal Testand Measurement IC 9. both the DAC sampling rate and the digitizer sampling rate must be integer multiples of 1 Hz. if we use bin For 9 in the DAC channel. so it is sometimes inferior to the more straightforward approach using equal fundamental frequencies. Find a coherent sampling system compatible with these constraints.4 Mismatched Fundamental Frequencies The example of the previous subsection dealt with the situation where the fundamental frequencies were made equal. The ATE tester's sourcememory will be needed for other DAC tests.625 Hz x (3/2).2. we shall investigate the fact that they need only be related by a ratio of two integers. Note that this integer-ratio sampling approach will often force us into even-numbered spectral bins.1 A DAC must be tested with a sampling rate of 5 MHz and a test tone frequency of approximately 5 kHz. The output of the DAC is sampled by a digitizer with a maximum sampling rate of 20 kHz. the digitizer fundamental frequency is 3/2 times that of the fundamental frequency of the DAC. .8) when rearranged Ff -DIGlTlZER Ff-DAC = M DAC M DIGITiZER (9. it will produce a frequency of 9 x 15.625 Hz.

4. we can write F lx-2=11d£=67x F s-DIGlmER 1000 or F 256 (9. A 20-kHz sampling rate would only allow us to collect only 4 sampleswith a fundamental frequency of 5 kHz. and NDIG/T/ZZER = 67. due to source memory limitations. the digitizer's samplingrate would have to be 19.Chapter 9 .104.M D/GmzER F. According to the informationsupplied.3.we shall consider that the and test and sampling frequencies are exactly 5 kHz and 5 MHz. Thus. Hz . we also know that NDAC to be has less than 1024. This we obtain through the development in Section 9.15) s-D/Gn"/ZER X 1000 67 = -~V ?~f. and look for power in spectral bin 64 (64 x 20 kHz / 256 = 5 kHz). we must make an adjustment to the sampling rates F DAC F DIGITIZERorder for the DAC and in and digitizer to be coherent. let us first considerthe DAC. The DAC operates a samplingrate of approximately at 5 MHz andis exercised a toneat approximately kHz. However. In addition. we shall select MDIG/77ZER the nearest prime number. In turn. This can only be satisfied if MDAC= 1.we can relate the sampling rate. by storing 1000 samples of a single cycle of a sine wave in the = sourcememory we can produce a 5-kHz test tone to exercise the DAC. Unfortunately. Next.-D/GlTlZER N D/GlTlZER Substituting known values. resulting in NDAC 1000.5 kHz =M DIGiTiZER -20kHz N DIGlTIZER Our first attempt at solving for the two unknowns (NDIGJTJZZER MDIG/77ZER) to consider and is setting the fundamental frequency of the digitizer equal to the fundamental fi:equency of the DAC. respectively. Sampled Channel Testing 331 Solution: First.numberof samples testfrequency and according to . = 256. as we are attempting to approachthese frequencies as closely as possible.16) With the DAC samplingrate set to 5 MHz. and are So instead.47 to satisfycoherence. let us considerthe digitizer. where we found M DAC~ N DAC . This is clearly not enough samples. 5 MHz/IOOO or 5 kHz. we create a problem. ~-DAC (9. as NDIGITIZZER MDIG/TlZER not mutually prime. One possible solution is to collect 256 samples at 20 kHz. on doing so. this bin would result in the same samples over and over.5 kHz=MDAC-5 MHz NDAC In order to detennine values for the two unknowns (NDAC MDAC). Hence canwrite by 5 we .

Therefore.16) as a product of prime numbers and eliminate any common terms.test engineers will often devise software tools to aid in the selection of sampling rates. as That is.18) ~~ '" ~ ~ 67x5 ] =[597. Summarizing. In order to satisfy this constraint.999.104 Hz 256 67 74.999.625 Hz 4.17) we find Fs-DIGl11ZER = 19. the final solution is: DAC Sampling rate Number of samples Spectral bin Fundamental frequency Test tone frequency 4. for a given set of DUT and tester constraints.875 Hz. the sample rates of the DAC and digitizer will have to be altered such that they are both integer numbers. etc. we must first express the rational fraction in Eq. Fs-D1GlTlZER 28 = 67x53xY Fs-DAC 67x53 =-F25 s-DAC (9. all sample rates must be integer numbers. In other words. This is particularly important when more that two sampling systems are required to be made coherent. As there are numerous steps to follow to obtain coherence.875 Hz (matchesDAC) In conclusion. sample sizes. (9. = Subsequently.104 Hz.from Eq. Fs-DAC 4. I i I .17) Next.999.19) and [ ] indicates a rounding to the nearest integer operation. The ATE tester imposes a further constraint where by all sampling rates have to be integer multiples of I Hz. To achieve this. That is. (9.999.875 Hz 1000 1 4.875 Hz (approx. we are not done yet. select F s-DAC a multiple of 67 x 53 which is nearest the desired frequency of 5 MHz. and a different Fourier spectral bin for each to achieve a coherent sampling system. 5 kHz) Digitizer 19.015] =597 (9.332 An Introduction to Mixed-SignalIC Testand Measurement . n I ! Fs-DAC 67x53 Xn where n =[ = (9. we used a different fundamental frequency for the DAC and digitizer. .'_1 Unfortunately.999.875 Hz 4.

: : I . This technique is called undersampling.1. Ans. 9. and as a result they may appear as lowamplitude in-band alias tones.2.5 Undersampling Undersampling is a technique that allows a digitizer or ADC to measure signals beyond the Nyquist frequency.000 125 System #2 23. However. . : . Sampled ChannelTesting 333 Exercises 9.000 Hz 1. aliasing filter : : I I I I capture memory ~ : Figure 9. we may remove the filter if we want to allow our digitizer or DUT to collect samples from a signal that includes components above the Nyquist frequency. High-frequency input Low-frequency alias signal ~ .If Fst=32 kHz. Any input signal frequency.390625xFs2. Low-pass antialiasing filter and ADC.976 Hz.951 Hz and F s2=22. A digitizer sampling at a frequency of Fs has a Nyquist frequency equal to FJ2.14. which is above the Nyquist frequency will appear as an alias component somewhere between 0 Hz and the Nyquist frequency. then Fs2=23.000 Hz: System #1 Sampling rate Number of samples Spectral bin 32.000 Hz 2. .1 but this time limit the sampling frequencies to integer multiples of 1 Hz.14. 9. Frequenciesthat extend beyond the Nyquist rate of the ADC may not be fully attenuatedby the filter. Ft. What are the sampling frequencies? Ans. The amplitude of these alias components can be used to compute the filter cutoff performance at frequenciesbeyond the Nyquist frequency.11111111- Chapter 9 .( [--~~~ & ' J 1'\1 ATE di gital Waveform . Repeat Exercise 9.011236 kHz. Anti- : . Coherence requires Fst = 1. We normally try to filter the input signal so that it has no components above the Nyquist frequency. One possible solution: F st=31. Two sampling systems described in the following table are operating with a test tone of approximately 2. Undersampling can also be used to measure the out-of-band rejection of a low-pass antialiasing filter before an ADC as shown in Figure 9. .2.024 89 Slightly adjust the sampling rate of each system so that the two sampling systems will become coherent.

this is equivalent to F~= F. Provided that the bandwidth of the digitizer's front end is adequate.15.\ \ \ \ \ \ . . First. . it is an image and the aliased tone will appear at frequency Fs-F'ra. This means the signal-to-noise ratio of the aliased signal will probably be degraded compared to a fully sampled measurement.. Fia.. Call this result. (9.a~Fs (9. . Care must be taken when selecting frequencies so they each fall into a unique in-band FFT bin.nF. Undersampling Aliased reconstruction a high-frequency sine wave.. Finally. Undersampling is often used when we have a digitizer or a DUT ADC with a limited sampling rate.20) where [ ) indicates a rounding down to the nearestinteger operation. Otherwise. .a = { F:a . Mathematically. Undersampled signal Figure 9. Second. check whether Fia is above or below the Nyquist frequency F s/2. but we want to capture a signal with components beyond the Nyquist frequency. all the noise components from 0 Hz to the digitizer or ADC input bandwidth will be additively folded back into the range from 0 Hz to F s/2. To calculate the expected alias frequency of a test tone denoted Fta. If it is below the Nyquist frequency then Fia is the frequency of the aliased tone. where n = [~ ) F. we can express these two conditions as F. 2.~ ~Fs/2 Fs-Fta IfFs/2<F." " . These problems can usually be corrected using focused software calibration techniques. There are several things to consider when using undersampling. .334 ." An Introduction to Mixed-Signal TestandMeasurement IC ' " .21) .15). Repetitively subtract Fs from the test frequency Ft until the result is between 0 and Fs.. the digitizer's front end may be less linear or may have a gain error at the frequency of the test signal. ifO<F. Next. perform the following steps: 1..we can use undersampling to collect samplesfrom the high frequency signal (Figure 9. the aliased image of two or more tones in a multitone signal may fold back to the same frequency.. Mathematically..

20 kHz - 20 kHz - 20 kHz = 5 kHz. such as a DAC. Recall from Chapter 6 that perfect reconstruction cannot be realized in practice. or other sampled-datacircuit.4) 5kHz=M~ or rewriting M N = Nx5 kHz 20 kHz =~ 4 .and 75-kHz components at a sampling rate of 20 kHz.15 kHz = 5 kHz. Care must be taken when undersampling multitone signals to avoid overlaps between different frequencies. In particular. It can only be approached. a perfect smoothing operation has a brick-wall frequency response.2. so we would expect to see the aliased tone at 5 kHz. Notice that both input frequencies (65 and 75 kHz) fold back into the same FFT spectral bin. and Other Sampled-Data Circuits Reconstruction is performed by first converting the discrete samples into a stepped or staircaselike waveform using some form of sampled-and-held process. that is. This is the nature of aliasing . in turn. one that rejects all signal frequencies completely except those in some frequency region that are allowed to pass unattenuated. It would be a mistake to undersample a multitone signal with both 65. (9.6 Reconstruction Effects in A WGs. limit the quality of the signal produced by an A WG. At what frequency do we expect the 65-kHz tone to appear? Assuming N samples were collected. we shall investigate the effects of images and sin(x)/x rolloff. Each undersampled tone must be selected so that it falls into a unique spectral bin. Sampled ChannelTesting 335 Example 9. Such frequency response behavior is impossible to realize with any real .2 A sine wave with a frequency of 65 kHz is sampled by an ADC at a sampling rate F s of 20 kHz. 9. This result is less than the Nyquist frequency of 10 kHz. As a result. Again.it is a many-to-one mapping process. This frequency is above the Nyquist. at what spectral bin will this frequency appear?Repeat the example with an input tone of75 kHz. some signal artifacts are introduced into the reconstructed waveform. Solution: We subtract 20 kHz from 65 kHz until we get an answer less than 20 kHz 65 kHz . . we keep subtracting 20 kHz until we get a number less than Fs: F'ta=15 kHz. this tone shows up in spectral bin N/4. since the aliased versions of the two tones would overlap at 5 kHz. Ideally. DACs.Chapter9 .. followed by a filtering operation to smooth the signal and remove the frequency images. The spectral bin is calculated using the equation Eq. These. DAC. An FFT is performed on the samplescollected by the ADC. so we expect to see an aliased sine wave at 20 kHz . Repeating the example with a 75-kHz input tone.

The effects of the sample-and-hold operation can be corrected for by multiplying the spectrum of the discrete-time signal by the inverse of Gsin(x)/x(I). the effects of the sin(x)/x rolloff on a single tone at frequency Ft can be corrected in software by boosting its amplitude by a correction factor given by ... then one can easily show that the frequency response behavior G(/) of the sampled-and-heldoperation introduced by the DAC is given by Gsin(x)/x (I) = ffi sin( Jr{ ) (9. this single test acts to verify that the filter's pass-bandand stop-band regions meet the maximum and minimum attenuation requirements. . A common test performed on a DAC followed by a low-pass anti-image filter is to test the circuit with a test tone set very close to the Nyquist frequency of the channel. etc.. ) (9. respectively. 45 kHz. we also have to take into account the frequency-domain effects introduced by the DAC through the sampled-and-hold operation.336 An Introductionto Mixed-Signal Testand Measurement IC circuit. leading one to describe this filter behavior as a sin-x-over-x rolloff.23) takes on the form sin(x)/x. For a single tone with frequency Ft.. one must tolerate some of the image energy appearing in the reconstructed signal.16. that is. (9. 1 Gsin ( x ) /x(Fr) I= (Jr~) Sin ( Jr. For example.25. Assuming that the each sample is held for the full duration of the sampling period. In addition to the images generatedby the reconstruction process. as well as many other frequencies such as 15. correction factor = . While aliasing is a many-to-one mapping process.3. a 5-kHz sine wave reconstructed at a 20-kHz sampling rate would produce images at 65 and 75 kHz.Fr . With x=JrI/Fs. the magnitude of an image decreasesmonotonically toward zero as the frequency of the image increases. the image tones. This is typically the worst-case condition.. appearin the will reconstructedwaveform at the following frequencies Flmage=nFs:tFr where n=1.24) Fs . Instead. Eq. imaging is a one-to-many mapping process.23) A plot of the magnitude ofGsin(x)/x (I) is shownin Figure9. only in reverse. Using the previous aliasing example.. denoted by Fimage. (9. but reject most of the image tone that appearsvery close to it at F s-Ft. From this plot we seethat reconstructedtones near the Nyquist frequency are attenuatedmuch more than tones located near DC.2. Further. In other words. 35. Ts=l/Fs. as the anti-imaging filter must pass the test tone at Ft undisturbed.22) The imaging process follows the same mapping rules as the aliasing process.

4F. 3F. correction_factor =x/sin(x). Figure9. 7F. Therefore. Compensation can also be perfonned in hardware.14159265359. Frequency SF.O. one must know ahead of time whether sin(x)/x correction factors need to be included in the software description of the test samples.0 V peak by sin(x)/x rolloff. . SF.Sin(x)/xgain versusfrequency. In fact. Sin 8kHz 1£ )= 1. N=2000. Example 9. An example MATLAB procedure is: % Correcting for DAC sin(x)/x effect % pi =3. . M=800.321 20 kHz Next we multiply the peak value we want by the correction factor to get a sample set that will be attenuatedto 3. Calculate the sample set for a 3. . Sampled ChannelTesting 337 0 0 N F. A=3. 6F.Chapter9 1 Gain (VN) 0. P=O. Boost the signal level to correct for sin(x)/x rolloff.5 .3 . Solution: I. 8-kHz sine wave that is to be reconstructed at 20 kHz using a conventional DAC..0. First we calculate the correction factor correction factor = J~~) ( . t yquis frequency t 2F.16. some DAC channels include a sin(x)/x correction factor in the low-pass anti-imaging filter that automatically corrects for most of the rolloff.0-V peak. x = pi*8e3/20e3.

.4.1 Signal Creation and Analysis In the previous example.3. A 1 V RMS sine wave with a frequency of 65 kHz is sampled by an ADC at a sampling rate of 32 kHz. IVDACI (V) I 0. end These samples can be reconstructed using a sample-and-hold process (A WG or DAC) followed by a lO-kHz low-pass filter to remove the sampling images. Ans.0-V peak waveform at 8 kHz. Exercises 9.3 ENCODING AND DECODING 9.998 ! . Ans.015j(kHz) i &.321.338 An Introductionto Mixed-SignalIC Testand Measurement for n=1:N. & - ' I 1 : 16 31 i 33 : 48 32 63i 65 64 9. we produced a sample set whose values were expressedin Volts.016 : ! I 0. IVADcl . I I i ' I ' I I ! ! I I i 0. If .032 t ii 0~ 030: ~ t i 0. P" 16 48 9. Samplesfrom a 1~ RMS sine wave with a frequency of 1 kHz are reconstructed with a V DAC at a frequency of 32 kHz. When we create a sample set for a DAC or when we analyze captured samples from an ADC. i' I I I I I : I i ' I .3. Sketch the RMS magnitude of the reconstructed waveform spectrum that includes the test tone plus the four lowest image tones. I ! I ! 31 i 33 32 ! I ! 63 i 65 64 i : ~ j(kHz) . sinewave(n)= correction_factor * A * sin(2*pi*M/N*(n-1)+P). we have to work with code steps (also called quanta or LSBs). The term LSB is commonly used to refer to a single step in a DAC or ADC transfer curve. resulting in a 3. The sample-and-hold process will attenuatethe 8-kHz sine wave by 1. I 1 V RMS 1 I I I I J I ' I I : I i . but this terminology can be a bit ambiguous. Sketch an RMS magnitude spectrum that includes the five lowest frequencies that could alias into the sameFFT spectral bin as the 65-kHz tone.

sign/magnitude. The encoding and decoding process depends on the encoding scheme of the DAC or ADC. two's complement.0 V would have the code-to-voltage relationship shown in Table 9. before we can analyze the output of an ADC.0 to 3.007843 V 01111111 (decimal 127) 10000000 (decimal 128) 1. we need to know its ideal gain and format. that would correspond to 8 steps of noise.003922 V 11111111(decimal 255) 1. Binary for DAC Code 00000000 (decimal 0) 00000001 (decimal 1) Voltage 1.1.0 V One LSB is equal to the full-scale voltage range.2 Data Formats There are several different encoding formats for ADCs and DACs including unsigned binary.0 V + 255 LSBs = 3. Sampled ChannelTesting 339 we tell a design engineer that his ADC generates3 LSBs of noise. The most straightforward data format is unsigned binary. the term "LSB" is much more common in data sheet specifications than the less ambiguous "quantum". Similarly. The test engineer should always make sure the data format has been clearly defined in the data sheetbefore writing test code.1. Unsigned binary format places the lowest voltage at code 0 and the highest voltage at the code with alII's. 9. mu-law. VFS+ -VFS_dividedby the number of DAC codes minus one VLSB= VFS+-VFs# DAC codes -1 (9. and A-law.0 V 1. This information is used to convert the ADC output from integer values into floating point voltage samples. one's complement. Let us look at some common encoding schemesand seehow we would create and analyze encoded and decodedwavefonns.~- Chapter9 .3. One common omission in device data sheets is DAC or ADC data format.0 V + I LSB = 1. Unfortunately.25) . To convert a series of desired voltages into a series of DAC codes. For example.996078 V 1. an 8-bit DAC with a full-scale voltage range of 1. This information is used to encode a series of floating point voltage samples into integer DAC samples. Table Unsigned Format an8-Bit 9. so we shall use the term LSB when referring to a single division in a DAC or ADC transfer curve. we have to know the DAC's ideal gain in bits per volt as well as its encoding format.0 V + 127 LSBs = 1.0 V + 128 LSBs = 2. do we mean 3 steps or do we mean that the 3 least significant bits of the ADC digital output are toggling randomly? If the three least significant bits (D2-DO) were toggling.

As is evident fiom the table.0 V)/255 = 7. the voltage corresponding to one LSB is equal to (3. To multiply a two's complement number by -1. When the most significant bit is one. Sometimes the full-scale voltage is defined with one an additional imaginary code above the maximum code (i. Isb~size. This level corresponds to input digital code O. Positive numbers are encoded the same as unsigned binary in two's complement. Isb_size) float vs.0 V .0 V)/256 = 7. together with the LSB voltage obtained fiom Eq. mfs =voltage at code 0. 26) or VMS=VFS+- ( #DACcodes -1 2 ) VLSB (9. all bits are inverted and one is added to the result. The midscale (MS) value is computed fiom either of the following two expressionsusing knowledge of the lower and upper limits of the DAC's fullscale range.mfs. } float decode_sample(code. This source of ambiguity should be clarified in the data sheet.. Isb_size in volts *' return (mfs + Isb_slze*code).8125 mY. The C-code for encoding and decoding floating point numbers to unsigned binary format might appear as follows: int encode_sample(vs.1. float mfs. code 256 in our 8-bit example).{ '* vs = voltage sample. Isb-size in volts *' return ((int)(0.5+ (vs-mfs)'(lsb_size))).e. Converting the above procedure into a MATLAB routine is a relatively straightforward exercise.0 V. If so.25) VMS =VFS-+ # DAC codes VLSB 2 (9 .0 V . Also evident fiom this table is the LSB is equal to 5 mV. (9. the number is negative. Another common data format is two's complement. { '* code= unsigned } binary code. It can be used to express both positive and negative values.27) . The two's complement encoding scheme for an 8-bit DAC is shown in Table 9. mfs.respectively. This decision is based on the fact that the above procedures are required to be resident in the tester and are usually written with a C code syntax. except that the most significant bit must always be zero. all outputs are made relative to the DAC's midscale value of 2.mfs. mfs = voltage at code 0. then the LSB size would be (3.340 An Introductionto Mixed-Signal TestandMeasurement IC In this example. Here we choose to present the conversion software routine using C code instead of the usual MA TLAB code representation seen previously in other chapters.843 mY. denoted VFS-and VFS+.1.lsb_size) int code. Isb_slze.2.

The midscale level corresponding to input code 0 for this type of converter is . Two's Complement foran8-Bit Format DAC. voltagesample. the most significant bit is zero for positive values and one for negative values. Code 10000000 (decimal-128) 10000001 (decimal-127) 11111111 (decimal-I) 00000000 (decimal0) 00000001 (decimal1) Voltage 2. } One's complement format is similar to two's complement.. Like one's complement.995V ~ 2.3 shows sign/magnitude format for the 8-bit DAC example.Isb_size) float VB. thereby making 11111111 a redundant code. Isb_size in volts *1 return (Isb_size*code). float Isb_size. vs .2. except that it eliminates the asymmetry by defining 11111111 as minus zero instead of minus one.360V 2. In sign/magnitude format.0 V + 1 LSB 2.0 V + 127 LSBs = 2. Sign/magnitude format is occasionally used in data converters. { 1*code = unsigned binary code.0V+ 126 LSBs= 2.0 V (midscale voltage) 2.365V 2. + } float decode_sample(code.lsb_size) int code. One's complement format is not commonly used in data converters becauseit is not quite as compatible with mathematical computations as two's complement or unsigned binary formats. sign/magnitude format also has a redundant negative zero value.127LSBs= 1.0 V -128 LSBs= 1.635 V The C-code for encoding and decoding floating point numbers to two's complement format might appear as follows: Int encode_sample(vs.Isb_slze. Sampled ChannelTesting 341 Note that the two's complement encodingschemeis slightly asymmetrical since there are morenegative codes thanpositiveones.630 V 2.0 V . Table 9. { . Table9.0 V-I LSB 1.5 vs/lsb_size). Isb-size volts *1 In return ((int)(O.~ Chapter9 .005V ~ 01111110 (decimal 126) 01111111 (decimal 127) 2.

0 V 2.lsb_size) int code. Isb_size.28) = VFS+-VFS- (9.127 LSBs = 1.365 V 2.0 V 2.v 2.995 V 2.2 Table Sign/Magnitude 9.0 V-I LSB = 1.5+ -1*vs/lsb_size».630 V 2. { /* code = unsigned binary code. + else return (MSB I (int)(O.Isb_size) float vs.635 V 01111110 (decimal126) 01111111 (decimal 127) The C-code for encoding and decoding floating point numbers to sign/magnitude format might appearas follows: int encode_sample(vs. { /* vs = voltage sample.5 vs/lsb_size». Formatforan8-BitDAC Code 11111111 (decimal-127) 11111110 (decimal-126) Voltage 2. } . mfs =voltage at code 0.29) # DAC codes.0 V + 126 LSBs = 2. Isb_size in volts */ if(MSB & code) return (Isb_size*code).0 V -126 LSBs = 1.0 V .0 V + 1 LSB = 2.mfs.370 V 10000001 (decimal-I) 10000000 (decimal-O) 00000000 (decimal 0) 00000001 (decimal 1) 2.3.342 An Introductionto Mixed-Signal Testand Measurement IC 11111111I VMs VFS.005. Isb-size in volts */ if(vs>=O)return ((int)(O.+ # DAC codes-1 VLSD=V = 2 FS+ whereVLSB givenby is VLSB ( ) - ( # DAC codes -1 VLSD 2 ) (9.0 V + 127 LSBs = 2. float mfs. /*Exampe:MSB is 10000000 8-bit converter */ for } float decode_sample(code. Isb_size. else return (-1*(MSBAcode)*lsb_size).

Then the compressedsignal may be digitized and reconstructed using an ADC and DAC. Mu-law is used in North American and related telephone systems. the analog signal is passed through a linear-to-logarithmic conversion before it is digitized.~ .Chapter 9 . Sampled Channel Testing 343 Two other data fonnats. They define a varying 3 2 Output (V) 1 0 -1 Linear ADC / .17 shows the transfer curve of a simple 4-bit companded ADC followed by a 4-bit DAC. Figure 9. In a true logarithmic companding process such as the one in Figure 9. Today the mu-law and A-law data fonnats are sometimes found not only in telecommunications equipment but also in digital audio applications. a companding converter has worse signal-to-noise ratio when signal levels are near full scale. regardlessof the signal strength. These two data fonnats are examples of companded encoding schemes. mu-law and A-law. were developed in the early days of digital telephone equipment. such as PC sound cards. The idea behind companding is to digitize or reconstruct large amplitude signals with coarse converter resolution while digitizing or reconstructing small amplitude signals with finer resolution.DAC pair 1 0 -1 Companding ADC / DAC pair 3 2 Output (V) -2 -2 -3 -3 -2 -1 0 1 2 -2 -1 0 1 2 Input (V) Input (V) Figure 9. The reconstructed signal is then passed through a logarithrnic-to-linear conversion 'to recover a compandedversion of the original signal. The mu-law and A-law encoding and decoding rules are a sign/magnitude fonnat with a piecewise linear approximation of a true logarithmic encoding scheme. Compared with a traditional linear converter having the same number of bits.17. The companding process results in a signal with a fairly constant signal to quantization noise ratio. Companding is therefore a simple fonD of lossy data compression. This tradeoff is desirable for telephone conversations. since it limits the number of bits required for transmission of digitized voice.17. while A-law is used in European telephone systems. The logarithmic processcompressesthe signal so that small signals and large signals appear closer in magnitude. Comparison linearand companding of 4-bit ADC-to-DAC transfercurves. but better signalto-noise ratios when signal levels are small. Companding is the process of compressing and expanding a signal as it is digitized and reconstructed.

Thus. say. a peak level of 4096 quanta in A-law corresponds to a central office power level of +3. But in low-resolution converters.3. These intrinsic errors can be compensatedfor in the final measured result by knowing ahead of time the gain error of a perfect ADC/DAC process as it encodesand decodesthe signal under test. All these parametersmust be modeled correctly. the procedure is relatively straightforward. In mu-law encoding.5.Next. The DAC levels are midway between the ADC levels. "DSP-based Testing of Analog and Mixed-Signal Circuits. and number of samples. phase shift. Let us first consider the A WG encoding process of a single sinusoidal signal.4 quanta. Today. MATLAB. these errors may be less than the errors generated by noise in the signal. the samples are encoded into the corresponding format of the DAC found within the A W G. offset. since the piecewise linear sections could be implemented with traditional binary weighted ADCs and DACs. Notice that the decision levels are listed in integer units called quanta. . the same cannot be said for an ADC. In the process of encoding the samples. frequency. The piecewise approximation was much easier to implement in the early days of digital telecommunications than a true logarithmic companding scheme. the Alaw and mu-law encoding and decoding process is often performed using lookup tables combined with linear sigma-delta ADCs and DACs having at least 13 bits of resolution. In high-resolution encoding and decoding processes. Each of the piecewise linear sections is called a chord. Subsequently.2. We can model the encoding/decoding processwith the block diagram shown in Figure 9. followed by a quantization or rounding operation.14 dEmO. as the DAC has an ideal gain of VLSB volts per bit.19. a 0 dBmO A-law signal level corresponds to a peak level of 4096x10-3. otherwise the results will be incorrect. The DAC restoresthe samples to their original level.e.J7/20 or. Likewise..including signal level. The mu-Iaw and A-law ADC decision levels are shown in Tables 9. or in signals that are very small relative to the full-scale range of the converter.3 Intrinsic Errors Whenever a sample set is encoded and then decoded.344 An Introductionto Mixed-Signal Testand Measurement IC LSB size that is small near 0 and larger as the voltage approachesplus or minus full scale. equivalently. Therefore. 5664. This process is made somewhat difficult. A more complete discussion of A-law and mu-law codec testing can be found in Matthew Mahoney's book. The negative decision levels are mirror images of the positive levels. The logarithmic nature of these curves is apparent in Figures 9. This is achieved by modeling the perfect DAC/ADC in software using.17 dBmO.J4/20 quanta equal to 2853. In the case of a DAC.20(a). Unfortunately. as these errors are dependent on the exact input signal characteristics. the quantization errors can make a sine wave appearto be larger or smaller than it would otherwise be in a higher-resolution system. as only a finite number of bits can be used to represent each sample.4 and 9. The steps in each chord are of a constant size. produce the output analog waveform). quantization errors are added to the signal. One begins by writing a numerical routine that generates the samples using a floating point number representation.the samples are stored in the waveform source memory and passedto the DAC to be decoded (i. a sine wave with a peak level of 8159 quanta corresponds to a power level at the central office of +3.18 and 9. which must be converted to volts during a separatescaling process."J 9. they are scaled by a factor of 1/ VLSB. a 0 dBmO mu-law signal level correspondsto a peak quanta level of 8159x10-3.

Sampled ChannelTesting 345 150 10 50 Jl-law code Jl-law code = sign + chord + step 10010101 Chord~ Sign Step 0 ~ CSJ .18. PI~cewlse -50 -10 -150 -10000 -8000 -6000 -4000 -2000 0 2000 level 4000 6000 8000 10000 ADC decision Figure 9. Jl-law ADC (encoder) decision levels. Table 9.4. linear chords . Jl-lawEncoder Decision Levels Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 1 35 39 43 47 51 55 59 63 67 71 75 79 83 87 91 95 2 103 111 119 127 135 143 151 159 167 175 183 191 199 207 215 223 Chord 3 239 255 271 287 303 319 335 351 367 383 399 415 431 447 463 479 4 511 543 575 607 639 671 703 735 767 799 831 863 895 927 959 991 5 1055 1119 1183 1247 1311 1375 1439 1503 1567 1631 1695 1759 1823 1887 1951 2015 6 2143 2271 2399 2527 2655 2783 2911 3039 3167 3295 3423 3551 3679 3807 3935 4063 7 4319 4579 4831 5087 5343 5599 5855 6111 6367 6623 6879 7135 7391 7647 7903 8159 .Chapter9 .

A-lawADC(encoder) decision levels.346 An Introductionto Mixed-Signal TestandMeasurement IC 150 A-law code = sign + chord + step 10 50 A-law code 0 -50 -10 -150 -5000 -4000 -3000 -2000 -1000 Sign Chord~ Step 10010101 ::!]I c:sJ .19. . PI~cewlse linear chords 0 1000 2000 3000 4000 5000 ADC decision level Figure 9. A-lawEncoder Decision Levels Step 0 1 2 Chord 3 4 5 6 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240 248 256 272 288 304 320 336 352 368 384 400 416 432 448 464 480 496 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 2176 2304 2432 2560 2688 2816 2944 3072 3200 3328 3456 3584 3712 3840 3968 4096 . Table 9.5.

21 using the following MATLAB code: . : . Intrinsic =VDAC-IDEAL V. If we want to generate a very low level sine wave with an RMS amplitude of 8 LSBs. (a) ~ . Rather. '' ' ' I . valid only for a particular as sample set. the output contains intrinsic errors causing the output to differ from the input. I ~ . I . (b) equivalent Of particular interest is the quantization operation. 30) Ideally. To quantify these errors. we could calculate the quantized/reconstructedsample set (normalized by an LSB) shown in Figure 9.) in the figure. process: (a) nonlinear model. The fact that the output signal VDAC-IDEAL is related to the input Vinby a gain constant Gintrinsic suggests that we can model the nonlinear quantizer operation as a linear opemtion with gain Gintrinsic shown in Figure 9. ' ' I I : V DAC-IDEAL I . In X Iv : : ' I I I . the entire encoding/decodingprocedure should have a gain of unity (i. This representation is.. I V LSB I . I Floatin -point g Vin ~ j numerical domain : .Chapter9 . If the sample set is changed.20. Asm ( 21f"TTn+lfJ M 1V ) ~.-~ : . Figure 9. : : Samples J:. of course. denoted Q(. .e. Subsequently. I : . Modeling the AWG waveform encoding/decoding linear model for a particular sample set. : ' Ideal DAC j . . This block is the source of signal dependenterrors mentioned above. In V /v (9.then a new Gintrinsic constant must be derived. Floating-point numerical domain Samples Vin = ' j : : IdealDAC : I I : . gain For example. . output equals input). let us say that we want to generate a low level sine wave at the first Fourier spectrel bin with no offset and 0 radians of phase shift using an 8-bit two's complement DAC. jn A sin (21f~n+lfJ) ~ X Iv V LSB (b) ' : I :: " I ~ : I I VDAC. I : : . we first define the gain of the entire encoding process as the ratio of the output VDAC-IDEAL the input Vin' This gain is referred to as the intrinsic gain of the over encoding processfor a particular sample set and is defined as G . . . Sampled ChannelTesting j 347 .the intrinsic gain error ~Gjntrinslc a particular input becomes for A '" Gintrinsic = Gintrinsic _ 1- VDAC-IDEAL-Vin Vin V/V (931) .20(b). L ~ . .JDEAL . . ' .

861 LSBs. The intrinsic error of a DAC or ADC quickly approachesthe noise floor of the measurementas the number of samples increases. % normalize all results in terms of LSBs input + P). P=O. as long as we use Fourier spectral bins that are mutually prime with respect to the sample size.the intrinsic gain and in~nsic gain error becomes 0.139 LSBs. respectively. Spectral bins that are not mutually prime will produce the same samplesrepeatedly. ~ Attempting to apply this same approach to uncover the intrinsic errors associated with an ADC is much more difficult. the input signal to the digitizer changes with each test and. Quantized sine wave: intrinsic error =-0.00325 V N .026 LSBs.139 LSBs. p 20 10 Signal ( i) 0 -1 ~O 0 20 i 40 60 Figure 9.026 LSBs. knowing the intrinsic error corresponding to a particular sample set provides no additional insight into the quantization errors that occur during a particular test. Thus.23. If we perform an FFT on the output signal. . x(n) = A*sin(2*pi*M/N*(n-1) end "/. In general. since it tends to minimize intrinsic errors. This is another reasonto use mutualr yp ri m e S ectral bins.348 An Introduction to Mixed-Signal Testand Measurement IC % Coherent signal definition -x% N=64. respectively. q(n) = LSB*round(x(n)/LSB). we see that we get an RMS level of 7. M=1.0173 VN. % Quantize % LSB=1. hence.21.861-8. so does the quantization error. corresponding to an intrinsic error of +0. Subsequently. which in turn produces the same quantization errors over and over. we get a different signal level of 8. The intrinsic gain and gain error will then be 1. end OJ. Unlike the situation with the A WG. If we shift the phase of this sine wave by 1Ii3 radians as shown in Figure 9. for n=1:N. intrinsic error is less of a problem with higher-resolution converters and/or larger sample sizes. A=sqrt(2)*8. for n=1:N. Intrinsic error is the result of consistent quantization errors. A block diagram illustrating the decoding/encoding process for the digitizer is shown in Figure 9. corresponding to an intrinsic error of(7.22.9826 and -0.00325 and 0.0) -0.

The digital decimal representation of a 1:1-law converted signal is 10110011.7. A set of samples derived from a 0. The input is formatted using a 2's complement number representation. 0. 4.Chapter 9 .8.~~~ : I :: 1 I I i. Exercises 9.Modeling digitizer/ADC the waveform decoding/encoding process.6. -303 to -287.22. What is the RMS amplitude of the captured test signal? ADS. Quantized wave phase sine with shift:intrinsic = +0.026 error LSBs.888 mV/bit. : : 1 1 1 ~ . 9. What is the ideal gain of a 10-bit DAC with a full-scale voltage range of 0 to 5 V? ADS.23.05 V N. 1 1 1 I 1 I I O. 0.5 V.742 V.5 to 2. What is the midscale voltage level? What is the expected output voltage level if the input digital code is 1001101? ADs. .707 V RMS sinusoidal signal is found to have an intrinsic gain error of 0. .l I : I ~~~~~ ~--~~~~~~ ' Figure9. In what decimal range is the input signal? ADS. 9. Sampled Channel Testing 349 20 1 Signal [ i ] -1 ~O 0 i 40 60 Figure9. I Iv I 1 : I I V ADC-/DEAL VLS/J ~. A 7-bit DAC has a full-scale voltage range of 0. 1.. 'It ' er or AOC I9 IZ X FIoalng-pain t :: : numerical t : : domain: " ' " 1 1 I 11': In : i :. 9.7047V.5079 V.5.

the inputs and outputs of an analog channel are actually stimulated and measured using sampled channels. the load.waveform_into_A WG( ) routine must first convert the continuous floating~point waveform. float sample[512]. Figure 9. analysis (math) . Whether the routine "load_waveform_into_A WG( )" is supplied by the ATE vendor as part of a library or whether the routine is written by the test engineer.512). Let us look at the similarities and differences between the DSP-basedanalog channel gain test shown in Figure 9." I' " I " . I Waveform L Waveform encoding (math) Figure 9. In DSP-based testing.i++) sample[i] A * sin(2*pi*i/512). A for (i=O.'II . The digitizer's integer samples are stored into a bank of memory.350 An Introductionto Mixed-Signal Testand Measurement IC 9. ~ load_waveform_lnto ~AWG(sample. the quantized waveform is passedthrough the A WO's DAC. To create a continuous analog stimulus waveform. etc. ~ m s Analog:: II " II II ~ Antialiasing filter Waveform capture: memory I I 1 : I I I I : I . Since most A WGs produce their wavefonns by applying integer values to a DAC.).14159265359.24 and a DAC-to-ADC sampled channel test shown in Figure 9.i<512. The resulting continuous waveform passesthrough the DUT's analog channel and into the input stage and low-pass anti-imaging filter of a digitizer.DSP-based analog channel test.I '. Digitizer II II . DUT Anti. such as the FFT. "sampled" by calculating 512 evenly spacedvalues using a C code loop such as: int i.1 Similarity to Analog Channel Tests Sampled channel tests are very similar to the analog channel tests described in Chapter 8. It must also calculate the necessary A WO attenuation settings and mathematical scaling factors that make this waveform come out of the A WO at the proper voltage level.24 shows the full stimulus~to-analysispath for an analog channel test A continuous mathematical sine wave is.414V. it must perform a yery important first step. .4 SAMPLED CHANNEL TESTS 9.pi=3.25. : Wa : :: channel . then through a reconstruction filter and various signal conditioning circuits (programmable attenuators. = 1. into a quantized integer waveform.:: imaging:: filter " . These samples are then available for DSP operations. This scaled and quantized integer wavefonn is then compatible with the A WO's waveform memory.4. AWG . sample[ ]. in effect. .24.

f ' orm. where they are available for DSP operations. this means that we have to apply more rigorous testing to sampled channels.4. The continuous signal is then filtered and resampled by the DUT's ADC channel. or whatever terminology is preferred) rather than RMS volts.) vary from one DUT to the next. producing digital output samples. The same process occursin this case. We could also show how DAC channels.' . and other signal conditioning circuits may move from the ATE tester to the DUT or vice versa. 9. OUT Antlimaging filter . The digital samples from the source memory are then shifted into the sampled channel's DAC input. The DAC output is low-pass filtered.2 Absolute Level. This waveform is then passedthrough an analog channel. since all the effects of sampling (aliasing. " " . " . filters. Theseare capturedand storedinto the digital subsystem's capturememory. etc. ADC absolute level is equally easy to measure. A continuous mathematical waveform is sampled by a mathematical process as before." encoding (math) analysis (math) Figure9. . The sampled channel gain test is therefore almost identical to DSP-based analog channel testing. Moreover. imaging.DAC-to-ADC sampledchanneltest. ) . "' . Gain Error. . . producing a continuous waveform.25. ADC channels. "' . . These sampling effects are often a major failure mode for sampled channels. Sampled ChannelTesting 351 Digital pattern source memory . The only difference is the possible compensation for intrinsic DAC errors. 'm L " " ' " " . and see how they must be modified as we apply them to sampled channels. Now consider the sampled channel test in Figure only the position of the components is shifted from the tester to the DUT. quantization errors. DAC Analog channel A . In this way. Waveform ~ L Waveform r . such as a diagnostic loopback path inside the DUT. switched capacitor filters. absolute voltage level measurementsare performed the sameway as any other AC output measurement. Absolute Gain. Otherwise. The only difference is that the location of DACs. The difference is that we express the output measurement in terms of RMS LSBs (or RMS quanta. ' . when compared to bench measurementsmade with noncoherent test equipment. . but this time the integers are stored in the source memory of the digital pattern subsystem rather than being stored in the AWG waveform memory. ure: O ry : .. . . and any other sampled channel could be reduced to a similar measurement system. Let us look at each of the analog channel tests described in Chapter 8. 9. . ': :' . RMS bits. Unfortunately. a measurementis made independent of the sample set used. RMS codes. ADCs.25. . ntl-:' aliasing filter ADC Digital pattern capture memory .Chapter9 . better correlation is made possible. and Gain Tracking The process for measuring absolute level in DACs and other analog output sampled channels is identical to that for analog channels.Wa:' is:: . "' .

if we have an 8-bit two's complement DAC with a full-scale range of -1 to + 1 V. not 256. ~ . Notice that there are only 255 steps between codes in an 8-bit converter.33) = VLSD Gintrinsic ~ Vln It is interesting to note that GDAC also includes the sin(x)lx frequency rolloff of the sampled-andhold action of the DAC. Code 128 does not actually exist in an 8-bit two's complement DAC. where the term "bit" refers to the LSB step size. which is equal to the gain in the case of a DAC or inverse of the gain in the caseof an ADC. In i I I I I numerical domain: LSB Floating-point :: I I I I I .34) ~ : : V.we would calculate the ideal gain as 2. Similar issues exist on an ADC's gain specification. but in bits per volt or volts per bit.0 1 256 = 7.84 mV /bit. is Similarly. Gain in mixed-signal channels is defined not in volts per volt.0 V as code 128.V/ V Vln (9. Data sheets do not always define the gain of a converter in bits per volt or volts per bit. Modeling the test setup for a DAC. If the data sheet is not clear on this definition. Therefore one LSB is equal to 2. absolute gain is measured using the same voltage-in/voltage-out process as in analog channels. The absolute gain of a DAC is expressedas the ratio of its output signal VDAC divided by the input signal Vin (expressedin LSBs) GDAC VDAC =-. For example the data sheet in this 8-bit DAC example might define -1. the absolute gain of an ADC without intrinsic error compensation is given by GADC=~ Vln bits/V=~x~ VLSD bits/V Vln (9.0 V 1255steps or 7. For example.0/255 or 7. such as switched capacitor filters and sample-and-hold amplifiers. measurementof absolute gain in mixed-signal channels is complicated by the fact that the input and output quantities are dissimilar.0 V as code -128 and 1. Thus GDAC a frequency-dependentparameter.352 An Introductionto Mixed-Signal TestandMeasurement IC In some sampled channels. I I I I I I I I I I .. : I I I I I I I I I I L Actual DAC V' XVLSB-ACTUAL DAC xGsin (x)/x : : I I I I I In ( ) f V DAC Figure 9. Often they define the ideal LSB step size instead. In this case.32) As VI~ =l/VLSD ( Gintrinsic) we can write the DAC's Vln. its ideal gain is 2. we sometimes see a data sheet that defines the upper voltage of a DAC as 1 LSB above the maximum valid DAC code. X Iv ~ I I I I I ~ v'.81 mV/bit. so it is an imaginary point on the DAC curve.84 mV. GDAC absolute gain as V /bit (9.. However. By contrast. the test engineer should request clarification.26.

the ideal gain is assumed to be l/V LSD bits per volt. Converter gain cannot be specified in decibels. The ideal output range is 1.39) In the case of an ADC.40) Example 9.0 to 4.35). at a DAC sampling rate of - .Chapter9 . the ideal gain of a DAC. (9. A sample set corresponding to a I-kHz sine wave at 0.the ADC gain error becomes DADC V V=.0-V level correspondsto imaginary code + 128. gives (f L\GDAC ) = As VDAC-/DEAL Gintrinsic Vin. Gain error L\G is equal to the actual gain GACTUAL divided by the ideal gain G/DEAL (which includes any sampledand-hold effects) L\G = GACUTAL G/DEAL V IV (9. (9.DAC Vin VI V (9.g. which includes the sampled-and-hold effect.VADC V I V L\GADC=VLSBVin Vin I (9.719 mY. Subsequently. that is. we can write = 1 1 V .8 V RMS is desired. Sampled ChannelTesting 353 where DADCis the ADC digital output expressed in LSBs.0 V / 28 = 11.36) For example..37) Substituting the above result into Eq.38) Gintrinsic Gsin(x)/x(f) L\GDAC f ( )= Gsin(x)/x 1 ( f ) VDAC V VDAC-/DEAL I V (9. because it is a ratio of dissimilar quantities (e. is GDAC-/DEAL (I) =VLSBX Gsin(x)/x (I) V/bit (9.4 An 8-bit two's complement DAC with a single-ended output has an ideal LSB size of3. volts per bit). write a MATLAB routine that produces a 5l2-point sample set that will generate a I-kHz sine wave at 800 mV RMS. can be expressedin decibels. the 4.35) Either result can be converted into decibel units using the standard conversion expression ( L\G=20 10gIO GACroAL G/DEAL ) dB (9. as we have no accuratemeansof computing its intrinsic gain. Assuming a perfect DAC.0 V-I LSB. together with the measured result in Eq. V ADCis the corresponding output signal level in volts and Vin is the ADC input voltage signal.33). Converter gain error. however.

354 An Introductionto Mixed-Signal Testand Measurement IC 16 kHz. x(n) = A*sin(2*pi*M/N*(n-1) P). An FFT is perfonned on the scaled sample set.0/2AD. Of course. We shift the spectral bin to 31 to achieve a prime bin. 32 is a poor choice since it is not a mutually prime number and will generate excessive intrinsic error.0 V % % Coherent signal definition -x% N=512. A=sqrt(2)*0. end %end We next need to calculate the absolute gain of a perfect DAC so we can compare our DAC's gain to the ideal gain. according to Eq. for n=1:N. we know from Section 9.6 that the gain of the DAC at this frequency due to the sampled-and-hold operation is . P=O. The Fourier spectral bin is found by dividing 1 kHz by the fundamental frequency of the sample set: M= 1 kHz / (16 kHz / 512) = 32. It should be 800 mY RMS. Thus. As the frequency of the tone is Ft = 16 kHz / 512x3l or 968. + end % % Quantize result and perform DAC operation % for n=1:N.2.8. (9. we need to consider the sampled-and-hold effect of the DAC on this sample set.30).127 mY.-% least-significant bit using an imaginary bit at 4. but because of intrinsic quantization error. and the sampling frequency is 16 kHz. Using the FFT output.8 Y. M=31. If the DAC output is digitized and the actual RMS voltage is detennined to be 780 mY RMS instead of 800 mY. % 8-bit DAC LSB=3. We also have to compute the Fourier spectral bin for a I-kHz tone with a l6-kHz sampling rate and 512 samples. the sample set has an intrinsic gain of Gintrinsic =1.{i x 0.00016 yjy Next. The resulting MA TLAB code is therefore: % DAC Encoding/Decoding Procedure % D=8.75 Hz. q(n) = LSB*round(x(n)/LSB). what is the gain and gain error of the DAC at 1 kHz? Include sin(x)/x rolloff and intrinsic error in the gain and gain error calculations. The peak amplitude of the tone is set at . Solution: First we need to calculate the sample set for the DAC. the sample set produces an RMS output of 800. we calculate the voltage level at bin 31.

33 mY. However. if a low-level signal is to be tested. Since many of the tests in this chapter are subject to intrinsic error and/or sin(x)/x effects. The test engineer should at least verify that intrinsic errors will be negligible before dropping intrinsic error correction from the gain calculations. intrinsic error is usually very small. They are. Intrinsic error and sin(x)/x corrections are usually not performed on any of the remaining tests in this chapter.25 HZ 7r ) ) =0.994 V/V 16 kHz The expected = 795. 256 bits 800 mV 1. however.994 x 800.33) with intrinsic error compensation. ADCs. (9. Often. Sampled channel gain tracking error is measured in a similar manner to analog channel gain tracking error. Sampled ChannelTesting 355 Sin . so it is often ignored in gain and gain error calculations. Substituting the appropriate values. Since our DAC produced 780 mV RMS.75 Hz)= ( ( 968. (9. quantize signals and are therefore subject to intrinsic error. since these do not quantize the signal as they sample it.33 mV = 0.98072V IV = -0. subject to sin(x)/x rolloff since they produce a steppedversion of the waveform samples. ADCs collect instantaneousvoltage values and therefore do not see sin(x)/x rolloff. on the other hand. Gsin(x)/x(968. Intrinsic error is especially important in gain tracking measurements. or if the number of samples is small. we obtain GDAC at 1 kHz = 3 V x 780 mV x 1 =11. we load the sample set into digital source memory and start a digital pattern that sends the samples to the DAC at 16 kHz. intrinsic error may become much larger if a low-resolution converter is tested. It is important to realize that some of the variation in gain at different levels is caused by differences in quantization error.127 mV Finally. These corrections are usually applied only to gain and absolute signal level .1691 dB The absolute gain of a DAC is determined from Eq.00016V/V - - Fortunately.Chapter9 . A digitizer collects the output. A perfect DAC would produce a sine wave at a signal level of 795.42 mV I bIt .33 mV RMS. Intrinsic error does not apply to SIR amplifiers and switched capacitor filters. However. RMS amplitude from the ideal DAC will then be 0.39) would be L1GDAC = 780 mV 795. and an FFT shows a signal level of 780 mV RMS.75 HZ 16 kHz 7r968. the correlation errors between bench equipment and tester can be traced to a bench measurementthat does not take such effects into account. the test engineer should always keep these potential error sources in mind as the performance of sampled systems are measured. the gain error according to Eq. The intrinsic errors in each sample set should be extracted from the measurementof each level before calculating gain tracking error.

The I-kHz test tone is passed through the DAC and filter. In coherent DSP-basedmeasurements. and S/H amplifiers should be tested for out-of-band images that appearpast the Nyquist frequency..4. sin(x)/x rolloff and intrinsic errors are usually considered part of the specified measurement. The additional attenuation is due to the filter. The best way is to provide design for test (Dff) accessto the input and output of the filter and measure its frequency response using standard analog channel testing. = 16kHz . The images from the DAC must first be calculated.25 Hz. Since a sample-and-hold process introduces sin(x)/x rolloff. then it can be measured in one of two ways.356 An Introductionto Mixed-Signal Testand Measurement IC . The imageof the I-kHz toneis locatedat F. In the remaining tests. If image attenuation is specified rather than filter frequency response. As usual.these images will appear at specific Fourier spectral bins. Notice that the digitizer used to measure these frequencies must sample at a high enough frequency to allow measurementspast the Nyquist rate of the sampled channel. the test engineer should ask for clarification. Each of the primary test tones and the potential images should be measured. Also notice that each sampling process in a sampled channel has its own Nyquist frequency. i11.3 Frequency Response Frequency response measurements of sampled channels differ from analog channel measurementsmainly becauseof imaging and aliasing considerations.6. Solution: . Calculate the frequency of the first image of the I-kHz test tone. These images may themselves be imaged by the l6-kHz switched capacitor filter. measurements. as explained in Section 9.then the test is a simple matter of comparing the amplitude of each in-band test tone with the amplitude of its image or images.2. one at 4 kHz and the other at 8 kHz.968. 9. Note that we will have to use a digitizer with a Nyquist frequency greater than 15031.75 Hz = 15031. The alternate test approach is to measure the attenuation of each test tone's first image compared to the ideal attenuation expected from sin(x)/x rolloff. the quality of this filter determines how much image energy is allowed to pass to the output of the channel.25 Hz to see this .5 The 16-kHz DAC in the previous example is followed by a low-pass filter with a cutoff frequency of 8 kHz. switched capacitor filters. if there is any doubt about this issue. Example 9. A digitizer samplesthe filter output and sees a signal level of 780 mY at the I-kHz frequency and a signal level of 5 mY at the out-of-band image frequency. An 8-kHz DAC followed by a l6-kHz switched capacitor filter has two Nyquist frequencies. If the filter's frequency response is specified. Frequency responsetests in channels containing DACs. Since sampled channels often include an anti-imaging filter. the images should appear even lower than the filter's gain curve would indicate. Calculate the gain of the filter at the image frequency relative to the gain of the filter at 1 kHz. The specification for a low-pass anti-imaging filter in a sampled channel may be stated in terms of the frequency response of the filter itself or it may be stated in terms of image attenuation of the total sampled channel.

Subsequently..':'. Modeling frequency the domaineffects associated theAWG. ( ) 16kHz (7r968.27. A logical choice for the digitizer sampling rate would be 32 or 64 kHz. keep the presentation relatively straightforward.75 HZ 16kHz .27.---r--. 1 . with frequency. denoted V'DAC.Chapter9 . .25 Hz)VRMS where the two gain factors are computed as follows SIn 7r Gsin (x ) /x(968.75 Hz)VRMS and VDAc(15031. Of particular interest is the spectrum corresponding to the output of the DAC.993981VIV=-Q. Ifwe useda digitizer with a 16-kHzsampling rate.75Hz) =0. i I 780 mV ill : I I I I IVAWGI ! I I I I VAWG f 5 mV 1 : 15. Sampled ChannelTesting IVDAcl GSin(x)lx(lkHz)xVRMs ! I ill 1 357 GSin(x)lx(15kHz)xVRMS : : I 15. '. say. VRMS. .75Hz)= .25.25Hz) = Gsin(x)/x (15031. . since these are integer multiples of the DAC sampling rate. together with a block diagram that identifies each significant component of the AWG. L r ~~t~~I-[)~c: xVLSB-AC1VAL V'DAC xGsin(x)lx 1 I (I) + ~ J DAC : ~ ~ 0 8 16 xG filter (I) .75 Hz) = Gsin(x)/x (968. i ! f I V' In : .image back onto the test tone at 968. we show only the test tone and its To first image..052 dB 968.thenthe digitizer would aliasthe 15031.75 Hz. ' . making the image measurement Hz impossible. thus the test tone and all of its images will have equal amplitude. .:ci---f VRMS Jrj:Jt. i . let us plot the spectral information that we are given in the problem. This we do in Figure 9.This particular spectrum is periodic. '.-r I I I I : 15. Next. f I I 0 8 16 0 8 16 Figure 9. the sample-and hold operation will modify the magnitude of the test tone and its image according to VDAC(968.

75 Hz) Gsin(x)/x (968.75Hz) = Gfilter (968.25 Hz) V AWG (968.064061V/V=-23.25 Hz) VRMS Therefore.for its image.25 Hz .25 Hz) 0.75 Hz) =Gfilter(15031.25 Hz) Gfilter (968.75 Hz) =Gfilter (968.25 Hz) Gfilter(968.75Hz)VDAC or VAWG(968.75 Hz) Gsin(x)/x(15031.25Hz)= 7r 15031.25 Hz) =G filter (15031.75 Hz) VAWG (968.75 Hz) Gsin(x)/x(968.25 Hz) Gsin(x)/x(968. we can expect the relative gain of the first image amplitude to the test tone amplitude to be VAWG (15031.993981 780mV 0.75Hz) Gsin(x)/x (15031.75 Hz)VRMS Likewise. sm 7r 16 kHz ( Gsinx) /x(15031.25 = Gfilter(15031.25 Hz) Hz)VDAc or V:4WG (15031.358 An Introductionto Mixed-Signal Testand Measurement IC and 15031.75 Hz) V AWG (968.25 Hz ) Gsin(x)/x(968.00994625 =-20.05 dB .25 Hz) Substituting known parameter values gives Gfilter (15031.25 Hz ( ( ) ) =0.75Hz) = VAWG (15031.25 Hz) Gsin(x)/x (15031. the low-pass filter will alter the magnitude of the test tone according to VAWG(968.the gain of the filter at the image frequency relative to the gain of the filter at 1 kHz is derived from this equation to be Gfilter(15031.we write V AWG(15031.25 Hz) Gfilter (968.25 Hz) Gsin(x)/x(15031.868dB 16 kHz Similarly.064041 V IV = 5 mV = 0.75 Hz) Subsequently.75 Hz) = VAWG(15031.

75 V RMS is desired. Unlike DAC channels. The additional information gives us a more thorough characterization of the DAC/filter combination. The location of alias components in the ADC output spectrum is determined using the technique outlined in Section 9. ADC channels do not suffer from sin(x)/x errors. 167. what are the gain and gain error of the DAC at 5 kHz? Ans.10. an analysis of the output codes indicates an RMS output value of 167.1. very fast settling time).7 mV/bit. then the idealized sin(x)/x correction should be valid. However. they can be measuredwithout any additional compensation. there will be an additional low-pass filtering effect. With a I-V RMS sinusoidal signal at 3 kHz applied to its input. The potential error source is the shape of the DAC steps. Therefore. "Design for Test"). Also.27 bitsN. Determine the gain and gain error of the ADC at 5 kHz. the phase shifts through the analog reconstruction and anti-imaging filters of the A WGs and digitizers are not guaranteed by most ATE vendors.4. 9.5 to 3. as well as measuring the true filter characteristics using a Dff test mode and analog channel test methodologies (see Chapter 14. A sample set corresponding to 5-kHz sine wave at 0. 0.9.982 VN (-0.07 V N. These problems are pointed out only as .~ ' Chapter9 . An ideal analysis reveals an intrinsic gain error of -0. The solution to this problem is a complicated focused calibration process that is beyond the scope of this book. Exercises 9. 9.27 LSBs. A 9-bit two's complement formatted ADC operating at an 8-kHz sampling rate has a full-scale range of 1 to 4 V. If the DAC output is digitized and the actual RMS output is found to be 0. The phase relationships are often not guaranteedto any acceptable level of accuracy. However.81 V. The problem with this measurementis that it is difficult to determine the exact phase relationship between analog signals and digital signals in most mixed-signal testers.16 dB).4 Phase Response (Absolute Phase Shift) This is one of the more difficult parameters to measure in a mixed-signal channel (AIDO or DIAO).65 dB). An 8-bit unsigned binary formatted DAC has a full-scale range of 0.e. These alias components are likely to appear if the lowpass anitaliasing filter of the ADC channel is inadequate. The filter gain may not be accurately measurableusing the sin(x)/x correction method in the previous example.. Again. assuming a DAC sampling rate of 32 kHz.5 V. This is the reason we usually prefer to measureboth the absolute level of images relative to the reference tone. ADC channels must be tested for alias componentsrather than images. this answer mayor may not correlate perfectly with a frequency response measurement of the continuous low-pass filter at these same frequencies.13. If they are very sharp (i. Ans. This approach allows us to verify the filter characteristics separate from the DAC characteristics. if the steps of the DAC waveform are not sharp. we prefer to measure both the filter in isolation (using a Dff test mode) and the alias components of the composite ADC/filter channel.1.21 VN (1. Sample~ ChannelTesting 359 Unfortunately. 1.

4. The reason for this is that the filter itself may be the source of the distortion. since they are based on a change-in-phase over change-in-frequency calculation. 9.5 Group Delay and Group Delay Distortion These tests are much easier to measure than absolute phase shift. We know our test tone is actually at a frequency slightly different from 3 kHz because we chose a prime bin number (bin 193). A 3-kHz test tone (spectral bin 193) is applied to the input of the ADC.and 9-kHz energy at its output which then gets aliased back into the 0-4 kHz band. except for the obvious requirement to work with digital waveforms rather than voltage waveforms. The following example shows how this is done. Group delay and group delay distortion specifications are much more common. In ADC channels. so we will look more closely at these measurements.2.4. we have to realize that some of the distortion components may fold back according to the rules of aliasing. The ." 9. lntermodulation Distortion These tests are also nearly identical to the analog channel tests. but let us use a slightly different approach. The only difference between analog channel group delay measurements and mixed-signal channel measurementsis a slight difference in the focused calibration processfor this measurement. We can measure the phase shifts in a mixed-signal channel in the same way we measured them in the analog channel.6 Signal to Harmonic Distortion. producing 6.360 An Introductionto Mixed-SignalIC Testand Measurement a warning to the new test engineer who might think that analog waveforms coming from an A WG or analog waveforms captured by a digitizer are exactly lined up with the digital samples coming out of a DUT or going into a DUT. Solution: The second and third harmonics would normally appear near 6 and 9 kHz. Calculate the frequency and spectral bin numbers of the second and third harmonics of this tone. Note that we may see distortion at these frequencies even if the low-pass antialiasingfilter is set to cut off everything above 4 kHz. if our third harmonic is down by an extra 2 dB becauseof sin(x)/x rolloff. sin(x)/x attenuation is usually considered part of the measurement in distortion tests. Fortunately. We could calculate alias frequenciesusing the traditional approach outlined in Section 9. then we consider the extra 2 dB to be part of the performance of the channel. Example 9. In other words. But since the Nyquist frequency of this channel is 4 kHz. Instead of converting all the tones from bin numbers into frequencies.5. The modified calibration process removes the group delay distortion of the A WG or digitizer. we know these tones will fold back in band due to aliasing. The calibration processesfor analog and mixed-signal channels will be discussed in more detail in Chapter 10. We have to test these componentsjust like any other distortion components. let us work with bin numbers instead. phase response of mixed-signal channels is not a common specification.6 512 samples are collected from an ADC channel sampling at 8 kHz. "Focused Calibrations.

2. then what is the defmition of crosstalk? Is it the single-ended level of the DAC divided by the ADC digital output. the ratio of an ADC output. would be a good guessfor the definition of DAC to ADC crosstalk.) We have to subtract 512 from the third harmonic once. A very low-level crosstalk signal may not be large enough by itself to toggle one LSB of a low-resolution ADC in a quiet state. if these bins existed in a 512 point FFT (which they do not). The difference is that we have to worry about the exact definition of signal levels. For example. we do need to check to make sure we have no overlap between distortion components of one tone and images of other test tones causedby reconstruction. We use a rule similar to the one in Section 9. 9. This is because the distortion appears at the expected frequencies. (If we were working with a multitone signal. then we can say the crosstalk from one to the other is defined as the ratio of the output of the inactive channel divided by the output of the active channel. bin 126.512 = 67.an ADC with an inactive DC input can mask low-level crosstalk. which correspondsto 1968. But this is not a solid rule to follow.po Chapter9 . it will appear at bin 126. If there is any second harmonic distortion at the input to the ADC. Therefore. crosstalk is defined by a ratio of voltages (converted to decibels). The third harmonic should appearat bin 67. But what if the channels are dissimilar? If we have one DAC channel that has a differential output and it generatescrosstalk into an ADC channel with a single-ended input. Bin 67 correspondsto 1046. converted into equivalent input volts? Generally. When working with digital samples. Sampled ChannelTesting 361 Nyquist frequency exists at bin 256 (one half the sample size). we do not have to worry about calculating alias frequencies as we did in the preceding ADC example. the result is the alias bin number. However. converted to RMS volts.75 Hz.they are usually converted into volts using either the ideal gain of the converter or the actual gain of the converter. rather than appearing at aliased frequencies. When measuring DAC harmonic distortion frequencies. A low level sine wave added to the input to an ADC allows the very small crosstalk signal to appear as part of a multitone signal . If the result is less than the Nyquist bin (number of samples divided by 2).875 Hz. If the result is larger than the Nyquist bin. The point is that the test engineer has to make sure the data sheet clearly spells out the definition of crosstalk when dissimilar channels are involved. which is already less than 512 but greater than the Nyquist bin. One difference between analog channel crosstalk measurements and quantized channel crosstalk measurementsrelates to ADC quantization. The result is 579 . so we are done. relative to a DAC output in RMS volts. An AC dithering signal is sometimes applied to the ADC input rather than a DC signal. If we have two identical DAC channels or two ADC channels. which is less than the Nyquist bin.4. subtract the result from the number of samplesto get the alias bin number. we subtract 386 from 512 to arrive at the alias bin of the second harmonic. or if the ADC itself generatessecond harmonic distortion.7 Cro$stalk Crosstalk measurementsin sampled systems are virtually identical to those in analog channels. to get an answer less than 512. The secondharmonic is at (nonexistent) bin 386. we would need to make sure we did not have any other test tones at this frequency. For this reason. The second and third harmonics would appear at bins 193 x 2 = 386 and 193 x 3 = 579.5: keep subtracting the number of samplesfrom the bin number until the result is less than the number of samples.

like crosstalk. However. DAC quantization. DAC and ADC channels do not have both PSR and PSRR specifications.4. it has PSR. on the other hand. When measuring crosstalk into a DAC output. the DAC input is set to zero or midscale. overcoming the quantization masking effect. a dithering signal is sometimes unnecessary. unlike ADC quantization. the ripple from a power supply may not be large enough to appear at the output of a low-resolution ADC with an inactive DC input. Like crosstalk.41) where Vripple = RMS voltage added to power supply (typically around 50-100 mV RMS) D ADC= ADC digital output expressedin RMS LSBs with Vripple added to power supply ADC gain = gain of ADC from normal input to output. For similar reasons. data sheetsusually list DAC channel PSRR. Otherwise the calculations are identical. if the ADC output is only toggling between one or two LSBs. then dithering is unnecessary. ADC CMRR tests may be affected by quantization masking effects. Unfortunately. but no PSRR. 9. or if the crosstalk is well above 1 LSB in amplitude. A DAC has no analog input. If the output of the ADC toggles by several LSBs becauseof noise. in bits per volt The definition ofDAC PSR is even simpler. 9. A dithering source can be used at the input to the ADC to uncover CMRR components below the 1 LSB level. so there is no such thing as DAC CMRR. A dithering signal can be added to the input of the ADC to allow an accurate measurement of PSRR. and is given by PSRDAC .9 PSR and PSRR Unlike analog channels. often have CMRR specifications. but that is a minor semantic issue. However. except that the outputs are measured in RMS LSBs and gains are measured in bits per volt. dithering may improve accuracy and repeatability of a crosstalk measurement. and the crosstalk appearsas a nonquantized continuous-time signal.. ADC CMRR is tested the same way as analog channel CMRR. meaning PSR. DAC PSR is . However. 20 lOglO ( ~ VOU! ) dB (9. ADCs have PSRR but no PSR. Here is the definition of the ADC supply rejection PSRRADC=20 lOglO ( DADC/VriPPle GADC ) dB (9.8 CMRR DACs do not have differential inputs. does not act as a hiding place for crosstalk signals. For this reason.42) ripple ADC PSRR is typically measured with the input grounded or otherwise set to a midscale DC level.362 An Introduction to Mixed-Signal Testand Measurement IC when it otherwise might be invisible by itself. ADC channels with differential inputs. and therefore no VN gain.4. The noise in the DUT is often high enough to act as a dithering signal.

If we instead apply a DC level. ICN testing of ADCs again involves quantization effects. The ENOB is related to the SNR by the equation ENOB= SNR(dB)-1. For example. So the exact DC offset will make the ICN measurement vary wildly. signal-to-noise ratio (SNR) is again tested in a manner almost identical to that in analog channels.02 dB 9. Like analog channel ICN. a dithering source in this case would introduce additional quantization noise. In this case.4. However. Sampled Channel Testing 363 often measuredwith the DAC set to a static midscale value. a 23-bit ADC that has only 98 dB of signal-to-noise ratio with a fullscale sine-wave input might as well have only 16 bits of resolution. The output of the converter is captured using a digitizer or capture memory. This level can be determined by characterization. except the DAC is set to midscale. ICN in these devices is zero by design. combined with knowledge of the DAC architecture. If the ADC input is midway between two decision levels. If the input is equal to one of the ADC's decision levels. Despite this seeming flaw in test definition. as discussedin Chapter 8. as long as the auto-zero or squelch function is operational. we may get a fixed DC code out of the ADC and our ICN measurementwill be zero LSBs RMS. or negative full scale. destroying the ICN measurement. Because of the extreme sensitivity of an ADC ICN measurement to DC offset. so they should be characterizedas well. DAC channel ICN is usually measuredin RMS volts over a specified bandwidth.10 Signal-to-Noise Ratio and ENOB In sampled channels. This is becausea perfect 16bit converter has a SNR of about 98 dB. some ADC channels include an auto-zero or squelch function to reduce the ICN of a DC input to zero regardlessof the input offset. (ENOB). usually the most positive setting. Extreme care must be taken to provide the exact DC input voltage specified in the data sheet during an ICN measurement. (9. whichever produces the worst results. Correlation can be a nightmare in ADC ICN tests.4. or effective number of bits. PSR specsapply to worst-case conditions. Often DAC ICN is specified with a specific weighting filter. becauseSNR is a ratio of similar values. positive full scale. ADCs may also suffer from worst results near one end of the scale or the other. this is how ADC ICN is measured. The apparent resolution of a converter based on its signal-to-noise ratio is specified by a calculation called the equivalent number of bits. Unfortunately. so the DAC is simply set to midscale.43) . it is important to realize that DACs may be more sensitive to supply ripple near one end of their scale.11 Idle Channel Noise Idle channel noise (ICN) in DAC channels is measured the same way as in analog channels. Excessive noise in an ADC or DAC can make it appear to have fewer bits of resolution than it actually has. which means the DAC should be set to the DC level that produces the worst results. The resulting waveform is analyzed using an FFT and the signal-to-noise ratio is calculated as in an analog channel.Chapter 9 . 9. resulting in an unweighted ICN measurementof 1/2 LSBs RMS. Usually there is not much difference in ICN results at different settings. we do not care whether we are working with volts or LSBs. then we will get a random dithering between two levels.761 dB 6. the ADC will produce different amounts of noise depending on the exact DC level and the ADC's own DC offset. Otherwise the test results will be completely wrong.

which we have only mentioned briefly.14 bitsN.74 dB. Determine the PSRR of the ADC. A sampled channel has 9.57. With its input shorted to a DC midsupply voltage and a 100-mV RMS sinusoidal signal added to the power supply. "Focused Calibrations. the RMS digital output of the channel is found to be 11. For all intents and purposes. The digitizer has a maximum operating frequency of 200 kHz and an allocated captured i memory capacity of 2048 samples.625 kHz. quantization effects. What is the corresponding SNR of the channel? ADS.0625 kHz. A 7. 7.12. A codec is operating at a 32-kHz sampling rate. 9. Exercises 9.5 SUMMARY DSP-basedmeasurementsof sampled channels are very similar to the equivalent tests in analog channels. 9.3 equivalent number of bits of resolution. Focused calibrations provide the additional accuracy that the ATE vendor may not include with an off-the-shelf.0.5 LSBs. An A WG has a maximum operating frequency of 100 kHz and an allocated source memory capacity of 4096 samples.364 An Introductionto Mixed-SignalIC Testand Measurement . ADS. We also have to deal with a new set of sampling constraints. since the DUT must now be synchronized with the ATE tester's sampling system. Often this represents one of the biggest challenges in setting up an efficient mixed-signal test program. the digital source and capture memory is assumedunlimited. Problems 9. Select the appropriate test parameters so that the~ I .5 dB." will explore this subject in more detail. ADS. and imaging.1. Another difference between analog channel tests and sampled channel tests is in the focused calibration process. A 2's complement formatted ADC has a nominal gain of 73. 78. aliasing. An ADC channel is sampled at 16 kHz and 256 samples are collected.68-kHz test tone (spectral bin 123) is applied to the input of the ADC. 9. The next chapter. bin 113.11. bin 10. While focused calibrations are sometimes unnecessaryin measurementsrequiring limited accuracy. a good command of focused calibration techniques is a must for the professional test engineer. Calculate the frequency and spectral bin numbers of the second and third harmonics of this tone. The most striking differences relate to bit/volt gains and scaling factors. Coherent testing requires that we interweave the DUT's various sampling rates with the sampling rates of the ATE tester instruments. general-purpose ATE tester.13.

000Hz 1. A DAC anddigitizer arearranged according the valueslisted in the following tableto to work with a testtoneof approximately 6. detenninethe test parameters the DAC of andthe digitizer.What shouldthe A W~ sampleratebe to establishcoherence with the ADC If the samplerate mUstbe a multiple of 1 Hz? How many samples shouldbe collected thewavefonncapture by memory? 9. 9.024 143 Slightly adjust the samplingrate of eachsystemso that the two samplingsystems are coherent. An A WG andADC are arranged accordingto the valueslisted in the following table to work with a testtoneof approximately kHz 15 AWG Samplingrate Number of samples Spectralbin 128.000 Hz 1500 175 ADC 44.both the DAC and digitizer samplingratesmustbe integermultiplesof I Hz.3. 9.both the A WG and ADC samplingratesmust be integermultiplesof 3 Hz. 9.000Hz 2. I . Sketchthe RMS magnitude the spectrum of that includesthe six lowestfrequencies could alias into the samespectralbin as the test that . A I-V RMS sinewavewith a frequency 63 kHz is sampled an ADC at a sampling of by rate of 24 kHz.7.2.r Chapter9 . Likewise. A I-V RMS sinewavewith a frequency 55 kHz is sampled an ADC at a sampling of by rate of 24 kHz. Due to samplingconstraints inherentto the tester. samples. Detenninethe new samplingratesof theDAC andthe digitizer.5.2 only 1024.000Hz 1.4. Due to samplingconstraints inherentto the tester. Sketchthe magnitudeof the sampledspectrumthat includesthe six lowestfrequencies relatedto this testtone. The A WG hasa memoryof 4.the ADC mustbe testedwith a sampling rate of 16 kHz and a sinewave of approximately kHz. For the codectest setupshownin Figure 9.024 349 .6. Sampled ChannelTesting 365 A WG and the ADC are coherent.000 513 Digitizer 44.15kHz DAC Samplingrate Number of samples Spectralbin 24. 9. Sketchthe magnitudeof the sampledspectrumthat includesthe six lowestfrequencies related this testtone. Determine new samplingratesof the the A WG andthe ADC. A I-V RMS two-tonemultitonesignalwith frequencies 55 and63 kHz is sampled of by an ADC at a samplingrateof 24 kHz. to 9. Slightly adjustthe samplingrate of each systemso that the two samplingsystems are coherent.13.

1 G(f)= ~ What is the RMS amplitude of the in-band test tone and the RMS amplitude of the lowest-frequency image? 9. Label the key points of interest such as lower and upper limits. Assume the sine wave is described by parameters M=l. Determine the RMS amplitude of the in-band test tone.12. N=32.5-V RMS sine wave with a frequency of 1 kHz are reconstructed with a DAC operating a sampling rate of 32 kHz.8. Assuming a perfect DAC operating at a sampling rate of 16 kHz.9. Samples from a 0. The input is formatted using a 2's-complement number representation.3-V RMS sine wave with a frequency of 5 kHz is reconstructed with a DAC operating a sampling rate of 12 kHz. What is the intrinsic gain of this . Repeat for M=8. A set of samples derived from a 0. What gain factor should be used to correct for the sampled-and-holdoperation? 9. or some other equivalent software routine. 9. write a MA TLAB routine. Subsequently.J2 .11.15.5 kHz is reconstructed with a DAC at a sampling rate of 16 kHz.17. Do these two test frequencies overlap below the Nyquist frequency? Do the test tones overlap if the test tones are shifted to 55 and 65 kHz? 9. followed by a first-order low-pass filter having the following frequency response.14.0 to 4.5 V? 9. A sample set corresponding to an approximately 3-kHz sine wave at 0. What is the ideal gain of a 10-bit DAC with a full-scale voltage range of 1. A 6-bit DAC has a full-scale voltage range of2. 9. 9.5 V RMS is desired. 9. midscale level and the LSB. plot the combined ADC-DAC transfer characteristic corresponding to thesetwo chords. What is the midscale voltage level? What is the expected output voltage level if the input digital code is 1001001? Repeat for a sign/magnitude format.10.045 V N.0 V.366 An Introductionto Mixed-Signal Testand Measurement IC tones. Samplesfrom a 2.6-V RMS sinusoidal signal is found to have an intrinsic gain error of -0. What is the actual amplitude of the test signal? 9. A=4. A I-V RMS tone of 6. What is the RMS amplitude of the in-band test tone and the RMS amplitude of the three lowest-frequency images? 9. Using MATLAB determine the intrinsic error of a quantized low-level sine wave with an RMS amplitude of 4 LSBs.13. that produces a 1024-point sample set that will generate this desired signal. and P=O. Plot the first two positive chords of a mu-law ADC and DAC on separate graphs. Plot the transfer characteristic of a 3-bit DAC formatted according to the following: (a) unsigned binary format (b) 2's-complement format (c) sign/magnitude format Pay particular attention to the behavior around input code 000.16.

A sample set corresponding to a 12-kHz sine wave at 0. A 12-kHz DAC is followed by a low-pass filter with a cutoff frequency of 6 kHz.65 V RMS is desired.5 LSBs. Calculate the frequency and spectral bin numbers of the fifteenth and twenty-third harmonics of this tone.' measuredand the actual RMS output is found to be 203. A digitizer sampling at 4 kHz captures 16 samples of a 0.25.21.20.5 V RMS is desired. second image frequency.0 V. Sampled ChannelTesting 367 sampling set? If the samples are held for the duration of the sampling period by the DAC. An FFT analysis reveals the spectral I amplitudes with this in the following measurement. . A 64-kHz DAC is followed by a low-pass filter with a cutoff frequency of 32 kHz. 9. An ideal analysis reveals an intrinsic gain error of -0. assuming a DAC sampling rate of 32 kHz. Determine the gain of the ADC and its corresponding PSRR. or some other equivalent software routine. that produces a 5l2-point sample set that will generate a 4-kHz sine wave at 500 mV RMS. The output of the channel is again analyzed. channel signal-to-noise ' I I Express this result in terms of its equivalent number of bits (ENOB).and third-order intermodulation distortion components. What are the gain and ri. gain error of the ADC at 4. resulting in an RMS digital output of 11. The ADC channel is sampled at 8 kHz and 512 samples are collected. 9. A sample set corresponding to an approximately 4-kHz sine wave at 0. Assuming a perfect DAC. The output of the ADC is analyzed.5-kHz test tone (spectral bin 161) is applied to the input of the ADC. what are the gain and gain error (in dB) of the DAC at 12 kHz? 9. resulting in an RMS digital output of 52. Then the input is shorted to a DC midsupply voltage and a 1OO-m RMS sinusoidal signal is added to V the power supply. A digitizer samples the filter output and sees a signal level of 250 mV at the l5-kHz frequency and a signal level of 0. A 2.71 V. Is their any frequency overlap between these distortion components and the images created by reconstruction? 9.19. If the DAC output is digitized and the actual RMS output is found to be 0. Calculate Determine the the total RMS level of the ratio noise of the associated channel. A l5-kHz test tone is passed through the DAC and filter. Calculate the gain of the filter at the second image frequency relative to the gain of the filter at 15 kHz. at a DAC sampling rate of 16 kHz.045 V N. An ADC channel is sampled at 16 kHz and 1024 samples are collected. A I-V RMS sinusoidal signal at 1 kHz is applied to the input of an ADC.33 LSBs.23. An 8-bit sign/magnitude formatted DAC has a full-scale range of 1. A l5-kHz spurious signal appearsat the input of the DAC.r r Chapter9 .2 kHz? 9.24. what is the effect on the amplitude of the desired signal? 9. write a MATLAB routine. A two-tone multitone signal consisting of frequencies 3 kHz (spectral bin 191) and 3. A signal level of 1 VRMS is applied to the ADC input at a frequency of 4. What is the intrinsic gain error of this sampling set? 9.18.1 mV at the .2 kHz (spectral bin 205) is applied to the input of an ADC. 9. A 10-bit 2' s-complement formatted ADC has a full-scale range of 0 to 5 V. Calculate the frequency and spectral bin numbers of the second.25 LSBs.2 kHz. table.22.5-kHz sinusoidal signal corrupted by noise from a DAC channel. The ADC output is .26. At what in-band frequency does the spurious tone appear? 9. Calculate the frequency of the second image of the 15-kHz test tone.0 to 4.

The Computer Societyof the IEEE. MatthewMahoney. 1987.W. 1730 Massachusetts Avenue N.ISBN: 0818607858. Washington. DSP~Based Testing AnalogandMixed-Signal of Circuits.368 An Introduction Mixed-SignalIC andMeasurement to Test FFT SpectralBin 0 1 2 3 4 56 7 8 RMS Voltage 2300~V 32 ~V 0. .C. 179-199 pp. 70036-1903.707V 12 ~V 15~V 31 flV 12~V 11 ~V 4~V References 1.D..

1. Transferal accuracy of standards from the NISTto ATE measurements.1. Calibration is the process of transferring accuracy standards from one sourceor measurementinstrument to another. formerly the National Bureau of Standards(NBS).Figure 10. This process. pound. These highly accurate instruments are removed from the tester on a periodic basis (typically once every six months) and sent to one of the NISI-licensed laboratories for recalibration.1 Traceability to National Standards NIST standards Liscensed calibration ATE system -:HAPTER 10 FocusedCalibrations Before discussing focused calibrations. The first calibration technique is to remove errors through adjustment of physical controls such as potentiometers and variable capacitors. AIE calibration reference sourcesare used by the tester as the "golden" standard for the volt.1 shows a typical chain of standardstransferal from the NISI standardsto an A IE measurement. etc. etc.- .ed 0 U T lab lab calibrations calibrations measurements Figure 10. meter. From the NISI. we should review the purpose and process of instrument calibration in general. In many countries.-10. second. . ampere.the NISI is in charge of maintaining standardsdefining the volt. ohm. 369 . inch. In the United States. a calibration reference source can be reinstalled into the AIE tester. In the United States. There are three ways to calibrate a measurementinstrument. Once it has been recalibrated.which in turn maintain "copies" of the calibration standardsto be used to maintain the accuracy of bench instruments such as A IE calibration reference sources or high-accuracy voltmeters. is one of the techniques used by the NISI-licensed laboratories to bring measurementinstruments and calibration reference sources . a central standardsagency has been established so that all measurementscan be referenced through calibration processesto a common set of standards. second.1 OVERVIEW 10. It is also chartered with the task of licensing calibration laboratories. the tester can perform daily or weekly system calibrations to maintain accuracy on a day-to-day basis. the accuracy standards are transferred through a number of calibration processesto achieve a high accuracy A IE test measurement.that agency is the National Institute of Standards and I~chnology (NIST). F?cus.. ampere. Using the freshly calibrated reference source. called hardware calibration.including a final focused calibration stage.

This second technique is basically a software-controlled version of hardware calibrations.but they are also executed automatically by the tester's operating system. Full ATE system calibrations can be initiated manually if needed. focused calibrations can be used to store values that must be measuredat least once. 10. The first step involves the standard system calibrations. A second calibration technique allows hardware euors to be couected using digitally controlled adjustment circuits such as programmable gain amplifiers and timing verniers. Load boards must be physically attached to the tester during the calibration process. Focused calibrations can also be used to transfer ATE accuracy standards to an uncalibrated circuit. The second step involves the test engineer's own focused calibrations. Since accuracy drift is most commonly causedby a change in tenlperature. The first use of focused calibrations is to transfer accuracy standardsfrom one ATE instrument (such as a high-accuracy voltmeter) to another. Hardware calibrations are not commonly used in ATE testers since this process cannot be automated easily. are measurementsmade by a test program on its initial execution. If the tester's instrumentation experiencesa temperature shift. The third and most powerful technique used in ATE testers is to leave hardware euors as they are and simply compensatefor them using software algorithms. but do not need to be .2 Why Are Focused Calibrations Needed? Focused calibrations. the tester measures its own euor and then eliminates the euor using the digitally controlled adjustment circuit. which occur automatically. or when a specific event occurs. many measurementsare calibrated in a two-step process. such as a DIE buffer amplifier or an on-chip measurement circuit. temperature-based recalibration is an important feature. but most modem testers can calibrate themselves automatically. Since the system calibration processes and the focused calibration processes are implemented using software couections rather than manually adjusted knobs. since either process can be implemented with automatic software algorithms without the need for a calibration technician to twist knobs. less accurate instrument. the test engineer may need extra accuracy above and beyond the normal specifications of the ATE instruments. Finally. such as once per week. One such event is the loading of a test program. production testing must automatically stop until the instruments have been recalibrated using the high-accuracy calibration reference sources. Although the periodic ATE system calibrations improve the accuracy of the ATE tester to meet its guaranteedspecifications. The second and third techniques are known collectively as software calibrations. Less advanced testers may require a calibration process using calibration-specific hardware called load boards. the term "software calibration" is commonly used to describeboth the system and focused calibration processes. There are at least three reasons a test engineer may choose to perform focused calibrations. this technique is commonly used in ATE testers to adjust electrical parameters such as gain and propagation delay.1. The level of automation in system recalibration is dependentupon the tester model. Using this process.370 An Introductionto Mixed-Signal Testand Measurement IC into compliance with accuracy specifications. Another event that can initiate a system calibration is a temperaturechange that exceedsa certain number of degrees. which may initiate a series of system calibrations on the appropriate tester instruments. which must be explicitly written into the test program. Systenl calibrations occur at periodic intervals. The extra accuracy is achieved using focused calibrations. Therefore. Since the programmable circuits allow an automated calibration process. after automatic system calibrations are complete but before DUT testing begins. or focused cals as they are often called.

the test engineer has to write the focused calibration routines for a particular test program. which narrows the billions of possible measurementsetups down to a short list of test conditions.Chapter10 . gain.hours calibrating itself for millions of measurement setups that would never even get used by a particular test program. the standard system calibration processmay suffice without additional focused calibrations. Unfortunately. such as the 13 kHz/2 kHz example. All three types of focused calibration are commonly used in mixed-signal test programs. We have to "focus" on the exact measurement conditions that have to be calibrated with a high level of accuracy. depending on their configuration. For example. though. Since only the test engineer knows what that list should be. etc. thus the term "focused calibrations. The tester might waste. and then reusing the measured value during subsequent test executions. input mode setting. ATE instruments such as digitizers and A WGs may have a slightly different offset. we would be unhappy with the time it would take to calibrate a general-purpose mixed-signal tester for all possible conditions. The resulting "unfocused" system calibration process results in an acceptable tradeoff between accuracy and calibration time. the calibration time would be unreasonably long. however. For a two million dollar price tag we would naturally expect a premium level of accuracy without any extra effort on our part. the tester's operating system performs a subset of the possible calibrations to achieve a fairly high level of accuracy across all the possible setups. If the tester's operating system tried to calibrate these instruments for absolutely any possible hardware configuration and any possible signal type. Each measurementsetup has its own peculiarities. That gain error is then automatically removed from any subsequentmeasurements.even if the sampling rate and test tone is different. It is easy to understand why we need to transfer accuracy standardsto DIB circuits and why we need to reduce test time by measuring unchanging values only once. When accuracy requirements are not particularly demanding. a digitizer's gain error might be measured at an 8-kHz sampling rate with a I-kHz test tone. Instead. the standard system calibrations may leave an unacceptable amount of residual error in the measurements. When test limits are tight relative to the device characteristics. filter setting. . leading to a unique set of measurementerrors. we can substantially reduce test time. Even with this advanced calibration technique. say. An example would be a one-time measurementof the actual signal level of a sine wave to be applied at the input to an op amp gain circuit. But why should we have to write extra calibration routines to improve the accuracy of the standard tester instruments? ATE testers can cost two million dollars or more. test tone frequency. applying an interpolation process to estimate errors at intermediate conditions. small errors may still remain. The short list consists of only those measurementsetupsused in a particular test program. Advanced testers may utilize a calibration processes that measures errors at several test conditions. The problem is that a general purpose mixedsignal tester can be configured to perform any of a seemingly infinite number of measurements. sampling rate." Most of the residual errors remaining after a standard system calibration can be removed through the focused calibration process. ATE vendors could certainly calibrate the tester in every possible measurement setup. In this chapter. For example. The answer to this question relates to calibration time. The differences in the digitizer's performance at a 13-kHz sampling rate and a 2-kHz test tone will introduce small gain errors in the final measurement. FocusedCalibrations 371 measured for each DUT. we will look at examples of each of these focused calibration techniques. By measuring these values only once. a 13-kHz sampling rate with a 2-kHz test tone. and phase shift characteristic for each and every gain setting.

' . Included in this discussion are focused calibration approaches for DC measurements.1. computations. Development of new focused calibration techniques is an important skill that mixed-signal test engineers should master. AC amplitude measurements. As we will see in Chapter 14. In this chapter. Some measurementerrors are tolerable. . phase measurements. In this case. A PGA has entirely different electrical characteristics (offset.Output: 'signal' ) . Again. and instruments between the signal under test and the final measurementresult. Figure 10.3 Types of Focused Calibrations In Section 4. : I path I I filters. this path may include DUT circuits such as buffer amplifiers and test accesssignal paths. etc.372 An Introduction to Mixed-Signal Testand Measurement IC 10.) : I . accessedthrough special on-chip test circuits. etc. " path. a digitizer set to an input range of :tl V represents a different signal path than a digitizer set to a range of :t2 V. . we should not use a calibration processfrom the I-V range setting to correct errors introduced by the 2-V setting. Many focused calibration techniques must be developed as needed for a particular situation. The purpose of focused calibrations is to reduce the errors inherent in the source and measurement signal paths for each test. For example.. ~ Source signal path Figure 10. ." the input node under test may actually be an internal node of the DUT. A measurement signal path includes all the circuits. but others are not. Source and measurement .2. I I I ~ DUT ---Subclrcuii - - : 1 I " " under '. A source signal path includes all the mathematical computations. and noise measurements. Digitizer: I : . L :::::::::::i ~::::::::::::' Measurement signal path signal paths for AC gain test. 10.2 shows a typical sourcepath and a typical measurementpath for an AC gain test.etc. ' . gain. frequency response. It is up to the test engineer to understand which errors are unimportant and which errors must be reduced. This is because the digitizer's input range adjustment circuit is implemented as a programmable gain amplifier (pGA). DIB circuits (attenuators. the on-chip circuits arepart of the measurementpath and must be calibrated on a DUT -by-DUT basis as if they were part of the tester. tester instruments..'. mainly to introduce the concept that the tester's results are not always accurate enough to meet our needs in mixed-signal testing. ' : : : I I DIB circuits: (attenuators. Each unique signal path must be calibrated separately. distortion measurements.2. Each combination of instrument configuration and interconnection path represents a unique signal path. This is by no means a complete list of all types of focused calibrations. we took a brief look at focused calibrations. filters. we will take a much more detailed look at calibration processes and common techniques for performing focused calibrations.I test I I . I I Input: signal I . Therefore. and electrical circuits between the idealized mathematical signal representation in the ATE computer and the input node under test.4 Mechanics of Focused Calibration Analog measurementsare never perfectly accurate.1.) at each gain setting. "Design for Test. but the techniques discussedwill form a good base of knowledge from which the test engineer can draw. :-.

. The object of calibration is to measure the nonideal characteristics of the source path or measurementpath. FocusedCalibrations 373 Circuit1 Vln DC gain = G1 offset = 01 Vout= Circuit2 DC gain = G2 offset = O2 Circuit3 DC gain = G3 offset = 03 Vout Vln composite DC gain + Composite DC offset x Composite DC offset = 0\ x G2 X G3 + 02 x G3 + 03 Composite DC gain = G\ x G2X G3 (a) '\tv Circuit 1 phase shift =P1 Composite Circuit 2 phase shift =P2 phase shift Circuit 3 phase shift =P3 W = P\ + P2 + P3 (b) J r- Circuit 1 Circuit 2 Circuit 3 delay = T1 delay = T2 delay = T3 / : / Composite delay = T\ + T2+ T3 (c) characteristics. Figure 10.since they are multiplicative in nature. timing parameterssuch as delay time are additive in cascaded circuits [e. When measuring DC offsets of a cascaded signal path.. etc. we can generally assume that composite path produces an offset that is the sum of the characteristics of each circuit element in the signal path.).g. Characteristics such as Figure 10. the basic concept of calibration is the same in all cases. Gains are easier to cascade. if a voltmeter has a DC offset of +2 mV when set to a 2-V range. if a DIB voltage follower has a gain of 1. since the offset from each stage is amplified by the gain of the following stage. For example. a separatemeasurementmust be made at each frequency of interest. Phase shifts.g. The gain through a cascadedsignal path is equal to the product of the gains of each element in the path. cascaded (c) delaycharacteristics.3(a)]. then we know that we must subtract 2 mV from any DC measurementwe make with this voltmeter when it is set to the 2-V range.3(b)]. However. then we know that at a frequency of 1 kHz we must divide the RMS voltage level measured at its output by 1. However. timing.3.Chapter10 . are additive. offset. unlike DC offsets and gains. cascaded (b) phase-shif . Similarly. Since gains often vary with frequency. Figure 10.. and then extract these characteristics from the measured result using a software adjustment. Likewise.3(c)].01 VN at 1 kHz. The phase shift through a signal path at a particular frequency is equal to the sum of the phase shifts through each of the individual elements in the signal path [e. Figure 10. the total offset is more than a simple summation of all offsets in the path [e.g. (a) Cascaded signalpath gain and offset characteristics.01 to calculate the actual RMS voltage present at its input. The focused calibration process varies with the type of measurement (gain.

Whatever gain or scaling errors are inherent in the . the absolute voltages are irrelevant. The advantageof measuring the whole signal path as a single instrument during focused calibrations is that it simplifies the calibration process. We simply need to measure the output signal amplitude and the input signal amplitude with the same instrument. dividing the measured output level by the measured input level. we can choose to work with a single calibration for each unique signal path. By cascading the appropriate calibration factors for a particular test setup. the phase shift through Circuit 1 may be affected by the circuit-to-circuit interactions. Even though the gain of an analog circuit is defined as output voltage divided by input voltage. since they are neither additive nor multiplicative. When cascadedcalibration factors and composite calibration factors produce equally accurate results.3(b) will be loaded down by the input impedance of Circuit 2. We have a choice of generating a composite calibration factor for an entire signal path or generating a series of cascadedcalibration factors for the individual blocks of the signal path. For example. For example. The reason for this type of nonideal cascadedbehavior is often related to interactions between the output of one circuit and the input to the next. The test engineer should be ready to encounter either type of calibration approach when reading test code from other engIneers. it is important to note that these simple cascadingrules may not be valid in all cases. we can calibrate the combination of a DC voltmeter and a DUT voltage follower as if the voltage follower were part of the voltmeter's front end. since the tester's calibration software cannot predict how the tester will be configured for a particular test. we have discussedcalibration as a method to eliminate measurementor source errors. Alternatively.3(c) may affect the propagation delay through Circuit 2. since they cancel each other out in the final calculation. When working with a cascadedcalibration. though. we can measure the characteristics of each block in the signal path. The advantage of measuring each block individually and then cascading the calibration factors is that we can arrange the blocks in many combinations without needing a separatecalibration factor for each configuration. the output stage of Circuit I in Figure I O. The test engineer should be prepared to verify the basic cascading rules for a given signal path before performing a cascadedfocused calibration. In fact. we will get the correct gain of 5. the output slew rate of Circuit 1 in Figure lO. Instead of keeping track of several calibration factors that must be combined to calculate the total gain and offset errors of the cascadedsignal path. Sometimes measurementpath errors are irrelevant. an AC gain measurement of an analog channel does not actually require accurate voltage measurements. For example. this is the way a tester's system calibrations are often performed. For example. If the loading is severe enough. we can keep a single gain and offset calibration factor for the composite path. as previously discussed. Having said all this.999 VN. the choice of calibration technique is a matter of personal taste. So far.374 An Introduction to Mixed-Signal Testand Measurement IC distortion and noise are difficult to extract from a signal path.999 VN. Likewise. But when cascaded. the output slew rate of Circuit 1 may be altered by the input capacitance of Circuit 2. Furthermore.they may have a gain of 5. If we calibrate the cascadedcircuit as a single element. which is almost equal to the ideal 6 VN. the tester can handle many permutations of hardware configuration with a limited number of calibration factors. maintaining individual calibration factors for each block. Composite calibration factors are also superior in that they do not make assumptionsabout the interactions between circuit blocks. two circuits may have a gain of 2 and 3 V N when measured separately. The input and output levels could be expressedin volts or digitizer LSBs.

the test program should allow the test engineer to force a recalibration at any time.1. Premeasurement of input signals is a test time reduction processrather than a calibration process. Strictly speaking. a focused calibration to achieve highly accurate absolute voltage measurementsis unnecessary. It is important to note that we have to use the same instrument with the exact same settings for both input and output measurementsif we want the error cancellation approach to work. we can measure gain by simply dividing the measuredoutput voltage by the calibration factor (measured input voltage). a tester may calibrate all its instruments every four hours and also any time the temperature changes by more than three degrees Celsius. Nevertheless. but we can make some general comments. we destroy the error cancellation effect. 10.Chapter10 . Another common rule of recalibration is that we need to regeneratefocused calibrations any time the tester performs automatic calibrations of its own. Focused calibrations should also be regenerated when test conditions change. As previously mentioned. or any other measurementsetting of the measurement instrument. For example.5 Program Structure The focused calibration process is an integral part of most test programs. Rather than measuring the unchanging input signal each time a new DUT is tested. Since the errors cancel out in the final gain computations. the resulting code can be difficult for the novice test engineer to work with. After the calibration factors are generatedand stored. The use of calibration factors for premeasurementof inputs is one of the simplest. the test program should regeneratethe focused calibrations. On subsequentprogram runs. Calibration factors are stored as global program variables whose values are retained from one program execution to the next. highly accurate results for analog channel testing. a digitizer's gain error is compensated by the tester's operating system using the automatic system calibrations. FocusedCalibrations 375 measurementinstrument will cancel in the ratio of output over input. If a test tone has to be modified from 1 to 2 kHz or if the digitizer's input range has to be altered. the input signal can be measured once and then reused to save test time. we can measure the input voltage level once. since signals are never converted into fully accurate. For example. familiar units such as RMS volts. If the test engineer . during the focused calibration process. After the tester performs its automated system calibrations. to aid in the debugging process. as frequently happens during the test debugging process. most powerful ways to achieve fast.the stored value is still called a calibration factor for lack of a better term. sampling rate. we would have to work with absolutevolts or otherwise calibrate the gain variation from one instrument setting to the other. Consequently. For example. then the test engineer has to modify the focused calibration portion of the test program as well as the normal DUT testing portion of the program. A forced recalibration is then required to compensatefor the new digitizer errors inherent in the modified test configuration. and store it as a calibration factor. However. Focused calibration factors should be regenerated on a periodic basis to account for potential drift in the tester instruments and DIB circuits. subsequent executions of the test program retrieve the calibration factors and use them to make the necessary DUT measurements. this technique is not really a calibration process. The test program typically performs the focused calibrations for all the tests during a first-pass program execution. If we change the voltage range. since it does not transfer accuracy standards from one instrument or circuit to another. The details of recalibration vary significantly from one type of tester to another.

the definition of the ideal output is usually defined as either 0 V or VDD/2 depending on the power supply configuration. digitizers. the definition of midscale is generally halfway between ground and the power supply voltage.376 An Introduction to Mixed-SignalIC Testand Measurement m load Force re-cal (manual) System calibrations y Force re-cal (manual) y Continue testing Figure 10. however. The definition of midscale varies. the DC offset of a voltmeter can be measuredby grounding its input. then the digitizer results actually pass through two calibration processes. and the DUT testing portion of the test program. DC offset calibrations can be performed on DC voltage sources. Likewise.5 V. an op amp having a single +5-V power supply (VDD)has a midscale voltage defined as VDD/2 = 2. then the focused calibration is no longer valid.1 DC Offset Calibration The offset of an instrument or circuit can be measured by setting its input to midscale and observing the offset from the ideal level at its output.4. for example.2. the focused calibrations.DC voltmeters. Example flowchart of system calibrations and focused calibrations. A WGs.2 DC CALIBRATIONS 10. as . For example. Therefore. refines the accuracy of the digitizer by performing a focused calibration. Figure 10. In op amp circuits having a single power supply. In an op amp buffer circuit having a bipolar power supply. If the characteristics of the digitizer change because of a periodic system recalibration. focused calibrations involving a particular ATE instrument should be considered invalid after system calibrations are performed on that instrument. the definition of midscale is usually ground (0 V).one general system calibration and one focused calibration. The DC offset of tester instruments can also be measured to generate offset calibration factors.4 shows an example flowchart for the system calibrations. and various types of DIB circuits such as buffer amplifiers and filters. For example. depending on the type of circuit or instrument to be calibrated. 10.

0-V range.ideal offset */ } In this pseudocodeexample.0-V peak sine wave with 2. for(i=O. before testing DUT's */ ) { int i. . the global variable OffsetCal is a calibration factor whose contents remain unchangedbetween one execution of the program and the next. whether there is a sine wave at its output or not. An A WG needs to produce a single-ended 1.3. Solution: There are many ways to approach this problem.32).5V /* i.. we can set the A WG to a DC level of 2.lV when set to its 5.0*PI*i/256). the DC offset of a voltage source can be measuredby setting it to force 0 V and then measuring its actual output as described in Section 4.i++) waveform[i]=2. To produce a calibrated waveform from the A WG.2.5-V DC offset.1 Chapter10 .5. but we need an input offset accuracy of:tl mV for this measurement. Using this assumption.i<32.i++) waveform[i]=(2.2. Using similar techniques.~ Example 10. The AWG has an offset specification of:tlO mY. float waveform[32]. : for(i=O.waveform(waveform WG .5V-OffsetCal) + sin(2. configure_AWG_to_state_XYZ( ). actual offset . the DC offset of A WGs and digitizers can be calibrated by measuring their offsets and then compensatingfor their offset during subsequentmeasurements. set meter input AWG. . Similarly. The tester has a high accuracy DC voltmeter with a total error (gain plus offset) of :tlOO I. = OffsetCal =read_meter() .i<256.2.e.5-V offset): calculate_and_load_calibrated_waveform( ) { int i. FocusedCalibrations 377 detailed in Section 4.5 V by simply creating and loading a short waveform containing the value 2. The simplest approach is to take advantageof superposition. 11111 .5 in each sample: calibrate_AWG_offset( 1*Run this routine only once. load_and_start_A . Determine a calibration process necessaryto achieve the:tl mV DC offset accuracy from the AWG. float waveform[256].5. we subtract this offset from the desired signal when we calculate the actual DUT signal we want (sine wave with a 2. We can assume that the A WG has the same DC offset..

less accurateinstrument. filter settings. Voun). then we should measurethe A WG's offset using a 10-kHz sampling rate as well.378 An Introduction to Mixed-Signal IC Test and Measurement configure_AWG_to_state_XYZ( ). /* .. must also match the DUT test for maximum accuracy. VIm) and measure the corresponding output levels (Voun. Now measure OUT response */ } The resulting wavefonn should have an offset very near 2.e.2.2 DC Gain and Offset Calibrations The DC gain together with the offset of a circuit or instrument is very easy to measure.2) V1N2-V1NI offset=VoUTI-GDc V1NI (10. By using the DC voltmeter to measurethe actual perfonnance of the A WG under a specific set of conditions. etc. The accuracy of this calibration also relies on the assumption that if we ask for a 10-mV increase in DC offset.1) we can deduce the two unknowns Goc and offset by applying two different input DC voltage levels to the circuit (VIM. In theory. It is usually best to assumethat any change in hardware configuration will give different perfonnance..5 V. load_a nd_sta rt_A WG. The preceding example demonstrateshow the accuracy standard of one instrument could be transferred to another. etc..3) .we can compute the gain and offset using the following equations GDc=~= ~V1N and VOUT2 -VOUTI (10. A WGs and digitizers may generate different DC offsets at different sampling rates. Subsequently..256). but the theory mayor may not hold true in practice. The DC voltmeter in an ATE tester is generally more accuratewhen measuring DC offsets than the A WG or digitizer. input gain (range setting).. this is usually a safe assumption. Unless the A WG is out of specification (i. If we need a 10-kHz sampling rate during the DUT test.waveform (waveform . such as low-pass reconstruction filter cutoff frequency. Other A WG settings. for example. then we will get approximately 10 mV of increased offset. we have transferred the accuracy of the meter to the A WG without having to calibrate the A WG in every possible configuration. failing system calibrations). Assuming that the input-output DC behavior of a circuit is described by the first-order linear equation VOUT =GDc VIN + offset (10. Of course the accuracy of this calibration relies on the fact that we set the A WG to the exact same conditions during the calibration measurement as we plan to use during the actual DUT test. 10. sampling rate should not affect offset.

not volts. Subsequently. rather than simply trusting the DC source to produce the programmed voltage levels. or (10.2 .5) = VOUT offset GDC - (10.6) We shall refer to this equation as the calibration equation. The gain and offset values will then be stored as calibration factors in global program variables for later use with this ~quation. alternatively Chapter10 . FocusedCalibrations 379 offset=VOUT2-GDC V1N2 (10. we seldom know exactly the functional behavior between the output and input signals of any circuit or instrument. the gain will be expressedin units of bits per volt and the offset in tenns of bits. So.4) The nature of the input and output variables need not be expressedin volts. (10. to the ATE digitizer.2. it relates the measured value to the corrected or calibrated value.the calibrated signal is determined from Eq. Each DC signal is digitized separately and the DC gain and offset is calculated using Eqs.0-V RMS sine wave plus 2. one voltage at a time.4). they can also be expressedin tenns of LSBs.~ or. Rather.2) and (10. a Dffi circuit may be an ADC whose output is in LSBs. our corrected level is really only an estimate of the true level.3). This dependson whether the meter is more or less accurate than the DC voltage source. as explained in Section 4. Devise a calibration process that will correct the DC offset errors of the digitizer and voltage follower. Apply the calibration to the measurementof a single-ended DUT output signal with a 1.5). we introduce a new variable called the calibrated signal.5-V offset.. In order to make this distinction clear. Solution: The combined instrument (voltage follower plus digitizer) can be calibrated the same way as we would calibrate the digitizer by itself. The gain and offset errors of the Dffi circuit or measurement instrument can then be corrected using the inverse equation V1N VOUT = -offset GDC In most situations.these two voltages can be measured with a highaccuracy voltmeter.3. An analog voltage follower is placed on the DIB to buffer a weak DUT output before passIng It . If necessary.~ . Two accurate DC voltages are applied to the voltage follower.and write V1N VCALlBRATED (10. they should be averaged to eliminate any variation in sample value that is causedby noise. Hence. Example 10. (10. As the digitizer output will consist of a series of samplesrather than just one value. VCAL1BRATED. For example.

= then the composite behavior becomes VDIG=GDIG (GBUFV1N-BUF +offsetBuF + offset ) DIG (10. a voltage buffer can be modeled such that its input and output behavior is describedby VBUF=GBUF VIN-BUF+ojJsetBuF Similarly. For example. there is a better way to calculate DC offset of the waveform. However.7) VDIG=GDIG VIN-DIG+offsetDIG Now. and we are left. 10. Since the average value of a coherent sine wave without offse~ is always zero.380 An Introductionto Mixed-Signal TestandMeasurement IC Note that the DUT signal is supposedto be the sum of a sine wave at 1. we can still measure the DC offset of the composite signal by computing the average of all the samples.VIN-DIG VBUF.2.3 Cascading DC Offset and Gain Calibrations A series of individually calibrated circuits or instruments can be calibrated collectively by combining individual calibration factors. The sine wave component averagesto zero. a digitizer can also be modeled by a first-order equation given by (10. since the first spectral bin correspondsto the DC offset of the signal. then we can simply read the first spectral bin of the FFT. This savesthe extra computation time of a separateaverage calculation.12) .0 V RMS and a DC offset near 2. Since the DC + AC signal is probably part of an AC test.10) where GCOMP =GDIG GBUF and (10. we will probably need to perform an FFT on the digitized signal at some point.11) ] - offsetcoMP GDIG offsetBuF +offsetDIG = (10. If we are already performing an FFT on the signal anyway. with only the DC offset of the waveform. if these two stagesare cascaded.8) (10.5 V.9) or VDIG =GCOMPVIN-BUF+offsetcoMP (10.

using Eqs. the composite gam of three stages m cascade with gams. Subsequently. . t Oz. from input to output.5. respectively. l f .14) and (10..002 and Gz = 2.) These offsets and gains are measured and stored as calibration factors on the first execution of the test program. and G3.14) offsetcoMP==G2G3~+G302 +~ The derivation details are left as an exercise in the problem set at the end of the chapter.the calibration equation becomes Tl'CAliBRATED Y " !' . Gz.5. The voltmeter produces a reading of 2. The voltmeter has an offset of 03 = -1 mV and a DC gain of G3 = 0.523 V.15) . GI. Solution: We start by calculating the gain and offset of the composite signal path.102 and an offset of 01 = 10m V and Oz = 20 mV. - VDIG -offsetcoMP G CaMP - (10 13) . I. For Instance. and 03.Chapter10 . . . (10. respectively. The Dffi circuits have a DC gain of GI = 1.--- offset =03 v Circuit 1 V1N DC gain offset =01 =GI Circuit 2 DC gain Gz offset Oz = = VOUT Figure 10. What is the actual output voltage of the DUT? DC voltmeter DC gain =G3 - .15) Example 10. A DUT output is applied to the input to the first Dffi circuit and the voltmeter measuresthe output of the second Dffi circuit.997.3 A signal path consists of two cascadedDffi circuits and a medium-accuracy ATE voltmeter as shown in Figure 10. ~xtending this appro~ch t~ include addition~l stages in c~cad~ is relatively straightforward. (The gain of the voltmeter is measured by forcing two input voltages from a DC source and measuring them with the voltmeter. is simply GCOMP ==GIG2G3 (10. Gain is defined as output measurement change divided by actual input voltage change as measured by a more accurate meter.. Three-block signal path. and offsets 01. FocusedCalibrations 381 We can therefore consider this composite circuit to have a gain of GDIG GBUF and an offset of GDIG offsetBuF+offsetDIG. (10.

(10. we need to transfer the accuracy standardsfrom a more accurate tester instrument to the A WG and digitizer using a focused calibmtion process. The details of this focused calibration process depends entirely on the architecture of the ATE tester.102xO. Exercises 10.09989 Thus the DUT output is equal to 1.382 ~ An Introduction to Mixed-Signal TestandMeasurement IC GCOMP =GIG2G3=1.31VN. A x10 inverting amplifier is used to boost a signal before it is applied to a digitizer. rewriting.4 mY.13 V N with an' offset of -5. The first commonly used AC amplitude calibration technique is to calibrate the digitizer first.there are several common techniques from which the test engineer can choose.09989 V/V =39.9 VN and an offset of 25 mV .1825 V IN 2.10) to write the input-output DC behavior of this signal path 2. a tester that has an accumte AC voltmeter allows a different type of AC amplitude calibration than a tester that lacks one. the digtizier was found to have a gain of 1. as in the DC gain example.997 =2. using a DC calibration step involving a highly accurate DC voltmeter.1 Calibrating A WGs and Digitizers If we want to perform highly accurate AC voltage measurementsusing multitone DSP-based testing techniques. the digitizer calibmtes the A WG. Sometimes the absolute voltages are unimportant. VCALIBRATED= -12. For instance. Nevertheless. GcoMP=-12. To guarantee the highest level of AC source and measurement accuracy. but often we need to source or measure an accurate voltage at each frequency of interest. Each step is . A calibration sequencedetermined that the amplifier has a gain of -10.1. we often have to make sure our digitizer and/or A WG is calibmted for absolute voltage accuracy.523V =VINx2.002x2. Next.31 V / V 10.9 mV or. In addition. What is the composite gain and offset for this cascade combination? Write the calibration equation for this test setup.1825 V.8 mV Ans.8 mV.09989+39.3 AC AMPLITUDE CALmRATIONS 10. offsetcoMP=22.9 mY) =1. VDIG-22. followed by an antialiasing filter response calibration.9 mV offsetcoMP= G2G3 +G3O2 +~ °1 Next we apply Eq.523 V -39. we get V = (2.3.

the digitizer's DC gain is determined using the two accurately defined DC voltage levels (VDCIand VDC]. Another possibility is to use a highly accurate AC signal source to calibrate the digitizer. Highlighting the steps of the first calibration digitizer using digitizer and determine method: (a) transfer voltmeter source using two different frequency accuracy to DC voltage source.ter V ~ DIG . (b) DC calibrate with DC voltage (c) measure AWG excitation response model of AWG./~:G (c) Antialiasing G filter (d) V . Let us look at the flTst two techniques in detail.. The first method begins by measuring the DC gain of the digitizer as shown in Figure 10. to determine filter's frequency response model.""L (10.6. . The second commonly used technique is to calibrate the A WG using a highly accurate RMS voltmeter and then use the A WG to calibrate the digitizer. and repeat AC response measurement linear mode! of complete test setup.-_J---~~-. (e) summarized in Figure 10.16 ) . This third possibility is not commonly used becauseATE testers are much more likely to have a high-accuracy RMS voltmeter than a high-accuracy sine wave generator.7.~ - Chapter10 . FocusedCa/ibrations 383 DC voltmeter + VM (a) Vin .V AT? VDIG2 -V DIGI V T? iilf ."".). This technique was common on older testers where a highly accurate sine wave signal source or RMS voltmeter was not available.6.. VDIG Vin VDIG Vin~_J~~_J~-~J~--n \J-l. With the digitizer's antialiasing filter bypassed. Figure voltage 10.V ~ levels. as summarized in Figure 10.6(a) and (b). according to G DIG ~ =-11&= 6.""'. and then calibrate the A WG with the digitizer.-~ VMEAS DC source (b) ~-L--=~~':-.'~/J~G V (e) V.. (d) insert antialiasing filter.--~~J:::""".= ~YDC DC2-YDCI ..

and digitizer are known at each frequency.6(e). (10. they should still be measured a second time and any residual errors should be stored as calibration factors. In other words. These levels can either be corrected by boosting or attenuating the requestedsignal level in math. we can write GAWG(I)=~=-. This is not a perfectly safe assumption. filter. but it is the best we can do on older testers that do not have high-accuracy AC instruments. The DUT will amplify or attenuate each tone and produce an analog output. though. Whether the A WG signal levels are corrected or whether their errors are simply recorded depends on how accurate the absolute voltage of each test tone must be. .17) GDIG Vln This first technique is predicated on the assumption that the digitizer's gain is flat across the frequency band of interest. Next.18) Furthermore. Devise a calibration scheme based on DC calibration of the digitizer with a high-accuracy voltmeter and a DC source.6(d)] and the same signal is digitized again (denoted VDIG). It may also have to suffice for high-frequency measurementsinvolving frequencies beyond the range of the tester's high accuracy RMS voltmeter. Even if the signal levels are corrected.18) as Gfilter ( 1 ) =VDIG VDIG (10. the input-output model given by Figure 10. The antialiasing filter's frequency responseis then determined from Gfilter ( ) Vfilter 1 V =- AWG =G 1 VDIG (I)G DIG T in AWG (10. the frequency response behavior of the A WG is determined by comparing the digitizer's frequency domain data with the ideal input signal levels. the digitizer's antialiasing filter is enabled [Figure 10. and 3 kHz is to be generatedby an A WG and applied to a DUT input. the AC frequency response of the A WG is derived by generating a multitone signal that contains the frequencies of interest as shown in Figure 10. Also. Subsequently. that is.4 A three-tone multitone signal at 1.6(c).384 An Introductionto Mixed-SignalIC Testand Measurement Next. or the errors can simply be recorded as calibration factors so that their effects can be removed from the final test result.!-~ Vln (10. The output will be sampled by a digitizer and the level of each tone will be measured in RMS volts. Example 10. The level of each tone should be 500 mV RMS. devise a calibration schemefor the A WG so that eachtone is as close to 500 mV RMS as possible. we can write Eq. the AWG output can be adjusted to produce signal levels closer to the desired value. as VDIG= GAWG (I) GDIG Vln. GDlo(/)=GDIGfor I<Fs.19) Once the overall characteristics of the A WG.2. Since VDIG = GDIG VAWG.

990 V/V VDC2 -VDCI Next we create a three-tone multitone from the A WG using a calculation routine such as: = for(i=O.9980 ~ 0. V2= 0. (10.497 V V I V Gfilter (2 kHz) Gfilter(3kHz)=-= = -V.9746 V I V The total gain of the digitizer at each frequency is therefore calculated as .i++) waveform[i]= 1.990 1 1 V IV 0.Chapter10 Solution: .475 V. The DC gain of the digitizer is then found to be equal to GDIG VDIG2 -VDIGI =0.i<512. = 0.498 V =1.9896 I V V V2 0.480 V. and source it to the digitizer. and Vj = 0.010 V and VDC2= -0.990 V IV 0. The gain of the AWG at each frequency is then computed according to Eq.00606 V/V 1 GAWG(2kHz)=--==0.(10.998 V. VDCI = +1. We collect sampleswith the digitizer and measurethe signal level of each tone using an FFT.990 V IV 0.500 V Next we enable the digitizer's antialiasing filter and measure the signal levels again. 0. This produces two accurately measured input voltages. These signal levels are recorded in variables Vj = 0. 1*3kHz tone */ We then load this wavefonn into the AWG.001 V.987 V and VDIG2= -1. VDIGI= +0.460 V.480 V V.498 V 0.969696 GDIG 0.475 V = 0.500 V ~ V2 Vin 0.414*500mV*sin(2*PI*67*i/512) 1* 2kHz tone */ + 1.414*500mV*sin(2*PI*97*i/512).460 V V3 0.19) according to ~' Gfilter(lkHz)=-==0. The signal levels are recorded in variables VI = 0.497 V. and V3 = 0.498 V. and two digitizer DC measurements. whose antialiasing filter is still bypassed.953535 Iv V 0.414*500mV*sin(2*PI*31*i/512)1kHztone*/ /* + 1. The gain of the antialiasing filter at each frequency is therefore given by Eq.472 V =0.17) 1 GAWGU kHz)=--= GDIG Vin 0.472 V =0.472 V.480 V V/V 0. FocusedCalibrations 385 First we apply two DC voltages to the digitizer (antialiasing filter bypassed) and measure their levels with a high-accuracy voltmeter and with the digitizer.500 V GAWG kHz) (3 =--1 GDIG V3 Vin = 1 0. V2 = 0.

we expect each signal level from the A WG to be very close to 500 mV RMS. G2. using the calibrated digitizer for maximum accuracy. capable of measuring sine waves from the AWG. we can produce a composite multi tone signal containing all the frequencies of interest at highly accuratesignal levels. Gz. These actual voltage levels should be saved as calibration factors for later use. Next we have to adjust the AWG signal levels so that each tone is equal to 500 mV RMS. and G3 should also be saved as calibration factors for later use.20) For instance.7(a).7.8 = 1. we first calibrate the gain of the A WG at each test tone as shown in Figure 10. The gain of the A WG is defined as the ratio of the actual sine wave output level divided by the desired level GAWG ( f ) =VAWG Vin (10. We do this by dividing the desired RMS level of each tone by the A WG gain at each frequency: G_AWG_1 kHz=1.9 V RMS.i<512. .00606. or 3 kHz using this configuration. anytime the program needs to know the exact signal levels produced by the A WG whe:!) sourcing this multi tone signal. G_AWG_3kHz=O. The actual signal level produced by the A WG can be measuredusing a highly accurate RMS voltmeter. We repeat this process for each frequency of interest to build up a frequency responsecalibration table for the A WG. Once we know the gain of the A WG at each frequency of interest. When this waveform is loaded into the A WG.969696.2.9649 V IV Now whenever we make a measurementat 1. We can correct this error by requesting a signal level of 1. then the gain of the AWG is 0. if we request a I-kHz sine wave with a signal level of 1. The calibration steps were highlighted in Figure 10.25 V RMS the next time we want 1. more common method of A WG and digitizer calibration relies on a highly accurate RMS voltmeter.9798 V IV V IV = 0. so it is a good idea to measurethe actual signal level at each frequency again.0 V RMS and we get a I-kHz sine wave with a signal level of 0. Using this technique.414*500mV/G_AWG_3kHz)*sin(2*PI*97*i/512).9880 = 0. and G3 to correct for the digitizer's gain errors. The digitizer gain factors G\. G_AWG_2kHz=O. when measuring the output of the DUT at these frequencies.i++) /* Note: These values /* and stored during would normally be calculated */ */ the focussed calibration as shown process /* rather than being hard-coded here.0/0.8 VN at 1 kHz.0 V RMS.386 An Introduction to Mixed-Signal Testand Measurement IC G1 G2 G3 = G filter = G filter = G filter (1 kHz) (2 kHz) (3 kHz) GDIG GDIG GDIG = 0. for(i=O. These focused calibration factors can be used when we test the DUT at each frequency. There will still be small errors.953535.414*500mV/G_AWG_1 kHz)*sin(2*PI*31*i/512) + (1. The second.414*500mV/G_AWG_2kHz)*sin(2*PI*67*i/512) + (1. we can divide the uncalibrated output result by the focused gain calibration factors Gl. */ waveform[i]= (1.

5 Repeat the previous example using a high-accuracy AC voltmeter rather than a DC voltmeter as the accuracy standard.The test engineer shouldrealizethat this will limit the accuracy higher-frequency of focused calibrations. (b) measurefrequencyresponsebehaviorof filter and digitizercombined usingAWGand createlineargain model.7.~. .(c) linearmodelof complete setup.21) The only problemwith this techniqueis that most AC voltmetersare less accurate higher at frequencies thanat audio-band frequencies.ter~~ V (b) ~ f--o VDIG VIn 0- (c) Figure 10. Focused Calibrations 387 Vin 0- f\. Secondcalibrationmethod:(a) measure AWG AC responseusinghighlyaccuratevoltmeter and create linear gain model.Chapter 10 . test While measuring tones from the AWG with the high-accuracy voltmeter.we also the AC measure them with the digitizer (antialiasingfilter enabled)as shownin Figure 10. VAWG ~.7(b).. The digitizer gain at eachfrequencycan be easily calculated dividing the digitizer result (FFT by outputat eachfrequency interest) the RMS signallevel asmeasured the AC voltmeter of by by GDIG(f)=~ VAWG (10. Example 10.

8 mV VAWG(3kHz) =476.500 V As in the previous example.4848 V GAWG(2kHz)= 0.4848 V G3 =Gfilter (3 kHz) GDIG(3 kHz) = 0.475 V. which may be represented by two's complement integers or by a floating-point waveform normalized to 1 unit peak.range. The voltmeter gives three readings VAWG kHz) (1 VAWG(2 kHz) =503. A typical digitizer produces a nonscaled waveform. it often requires a mathematical scaling and correction process before it produces anything that even resemblesabsolute volts. For example.9798VIV =0.5030 V GAWGUkHz)= 0. Once a waveform has been captured by a digitizer.953VIV 0. the filtered digitizer measures the signal levels V'I = 0.503 V 0.006 V/V 0. .475 V G2 = Gfilter (2 kHz) GDIG (2 kHz) = 0.497 V =0.388 An Introduction to Mixed-SignalIC Testand Measurement Solution: This technique is more straightforward than the previous one.970 V/V GAWG kHz) (3 = 0. As the AWG sources each tone.4767 V = 0.500 V =1. and a I-V peak input is applied. if the digitizer is set to a :1:2. Therefore the AWG's gain is calculated using Eq.4767 V =0. we measure its output with the digitizer and also with a high-accuracy RMS voltmeter. we have to multiply by a scaling factor (in this example.500 V =0.0mV = 484. If we want to convert this unscaled output into something that approximates absolute voltage.7 mV These results are assumed to be accurate. we have assumedthat the output of the digitizer is in volts and the output of the FFT gives us RMS volts.9880 IV V =0. (10. The combined filter and digitizer gain can be calculated simply by comparing its output at each frequency by the known input G1=Gfilter (1 kHz) GDIG(1 kHz) 0.5 V unit peak amplitude.497 V. So far. we produce single tones from the A WG at each tone of interest (1.20) as follows 0. Notice that this calibration process is considerably easier to follow than the previous one. Instead of producing a three-tone multitone signal. the scaling factor would be 2).2. then its output may appear as a sine wave with a 0.460 V 0. and V'3 = 0. This is not necessarily true in practice.9649 IV V The remaining focused calibration steps are the same as before.460 V. and 3 kHz). and is often more accurate as well. where the unit is undefined. V' 2 = 0.

the electrical noise inherent to all analog measurementsis basically independent of the signal level (quantization noise notwithstanding). Our objective in calibrating a low-amplitude test tone is to measureonly the test tone. the simultaneous ADC and DAC crosstalk test described in Chapter 9 uses a different frequency for the DAC channel (digitizer) than the ADC channel (A WG).3.- Chapter 10 FocusedCalibrations . not the noise and distortion that inevitably accompany the test tone. The post-FFT scaling technique makes the code a little harder to follow. even when the test tone amplitude is small.22) RMS'o/a1 the RMS of the composite sine wave plus noise signal that we could expect to is measure using an RMS voltmeter. 10.oise (10. usually equal to the squareroot of the number of samples or some similar factor. We have to remove any such scaling factor from the FFT output by dividing the FFT result by the scaling factor. As a result. crosstalk. Some of the noise even comes from the voltmeter itself. low-amplitude signals cannot be accurately calibrated in such a simple manner. The details of scaling digitizer and FFT outputs is highly dependent on the type of digitizer. Notice that we can combine all the scaling factors and the focused calibration adjustments after the FFT operation to save test time. rather than scaling the whole time domain waveform. including distortion and noise. we only have to correct a few values. However. When measuring the RMS voltage of a high-amplitude sine wave corrupted by small amounts of noise. electrical noise can introduce significant RMS voltage measurementerrors into lowamplitude sine wave measurements. the post-FFT process can save quite a bit of calculation time. More often than not. The total RMS of a sine wave plus a random noise signal is given by RMStotal=~RMS~gnal +RMS. a true RMS voltmeter's reading is dominated by the RMS signal level of the test tone. so we will not cover these operations in any more detail. When using the A WG to calibrate the digitizer or vice versa. Small amounts of noise introduce almost no amplitude error becauseof the way sine waves and random noise combine into a composite RMS signal level. and PSRR. signal to distortion.2 Low-Level A WG and Digitizer Amplitude Calibrations The RMS voltmeter calibration approach works nicely for high-amplitude 'signals. Low-amplitude sine waves and multitones are often sourced and/or measured during tests such as gain tracking. RMSnoise the amplitude of the noise corrupting the sine is . we often have to perform one calibration for the A WG signal and then perform a second calibration for the digitizer signal. since we never see a correctly scaled time domain waveform. CMRR. However. an FFT routine introduces scaling factors of its own. For example. It is worth noting that the digitizer tones and A WG tones may not be identical during a given test. However. Unfortunately.18. Using this post-FFT scaling technique. RMS voltmeters measurethe total RMS voltage at their input (up to a certain bandwidth). 389 Depending on the tester's operating system. The distortion is not much of a problem because it is generally many orders of magnitude lower than the test tone amplitude. The scaling process should be part of the training offered by the ATE vendor. the FFT of this signal mayor may not produce RMS volts in each spectral bin.

3 Amplitude Calibrations for ADC and DAC Tests ~ So far. We first generate a high-amplitude sine wave from the A WG to calibrate the gain of the digitizer at each test frequency of interest.) Digitizing the multitone signal with this new digitizer configuration and comparing the outputs of an FFT with the known signal amplitudes. I J 10. we can generatecalibration factors for the digitizer that are tailored for this new input configuration. ~ i . even if it contains a small amount of noise. though. However. and distortion components. Voltage errors in these casessimply cancel out in the final result. (10.3. But what would we do with these residual errors? The answer is that we fine-tune our final measurementsby realizing that the input was not quite what we requested. Each A WG test tone amplitude can then be adjusted to produce a highly accuratemultitone signal. If. we can then produce a low-level sine wave or multitone signal from the A WG that approximates the signal we need during the DUT test. can differentiate between signal. on the other hand. We have seen how an AWG waveform can be calibrated to produce a fairly accurate signal level at each frequency of interest.:~ If we need to calibrate the digitizer for measurementsof very low-level signals. If the RMS amplitude of the sine wave is much larger than RMS amplitude of the noise.we can often ignore absolute voltage measurementssince we are working with ratios of output voltage divided by input voltage. In this case. The digitizerlFFT combination. After we have generated a set of gain calibration factors to correct the digitizer's amplitude error at each frequency of interest. When working with DACs and ADCs. using the voltmeter-based calibration technique of the previous example. the digitizer can be reconfigured into a mode more suitable for low-level signal measurements. and RMSsignal the RMS amplitude of the sine wave itself (the amplitude we actually want is to measure). Therefore. we can apply the gain calibration factors to accurately measure the signal level of the lowered A WG test tones. the sine wave amplitude is not large compared to the noise level. giving a much more accurate measurementof the low-level test tone components generatedby the A WG. For instance.390 An Introductionto Mixed-SignalIC Testand Measurement -r wave. Since we have just finished characterizing the digitizer's amplitude error at each frequency. When we measure analog channel~. we can use the RMS voltmeter to make an accurate measurementof a high-level sine wave.22) becomes insignificant due to the squaring operations. These calibration factors can later be used to correct measurementsof low-level DUT signals measured using the digitizer in this particular \I input mode. the digitizer's input range may be dropped from ::t1. The absolute voltage calibrations discussedin the previous sections are adequatefor measuring the output of DACs using a digitizer.OV to ::tIOO~V. we usually have to worry about absolute voltages. then the RMSnoise component of Eq. and how the residual errors can be measured and stored as calibration factors. :. After producing the low-level A WG signal. and a high-pass DC blocking filter may be added to its signal path to prevent signal clipping on this lowered range. DSP-based testing provides a solution to this problem. the amplitude of the composite signal is very close to the amplitude of the sine wave we wish to measure. we can use this A WG calibration technique to produce a highly accurate single tone or multitone signal. we have mainly discussed calibrations for purely analog channels. signals generatedby an A WG are never exactly correct and we need to compensatefor ADC input signal level errors. unlike the RMS voltmeter. noise. (Small DC offsets in the signal can cause digitizer clipping on low signal ranges because the digitizer's front end is set to a high gain. the noise portion of the equation above introduces a significant measurement error.

The level of each tone should be 300 mV RMS.6 We wish to measure the gain of an ADC at 1. and 267 mY.44 V when two known DC voltage levels of 1.2.{3 kHz) = 0. GDIG=GDIG(2 kHz) = GDIG(3 kHz) = 1. indicates RMS readings of 0.kHz output amplitude =118. GAWt.9946 VN. and 3 kHz are 299.(3 kHz) = 1. each having a 1 V RMS level. ~ Exercises 10. The calibration factors are: 1. 2.290. GAwG(2 kHz) = 0.3. 2. AWG. Focused Calibrations 391 Example 10. . 326.1111111'11111111111111111111.7 mY. We use the technique of Example 10. and filter at 2 and 3 kHz from the calibrated data gIven. and 3 kHz is to be generated by an AWG and applied to a DUT input.32 V are applied as input. Ans. What RMS amplitude values should be used to program the A WG? If the corresponding digitized output at each frequency is 311. with the antialiasing filter bypassed. The RMS voltage levels of each tone are measured and stored as calibration factors. what are the RMS levels of a DUT whose values read by the digitizer at each frequency is 517. and 3 kHz.310.3. the A WG output is measuredwith a highly accurate RMS voltmeter. respectively.kHz amplitude =499 mV RMS The calibrated A WG multitone is applied to the ADC and samples of the ADC output are collected by the tester's capture memory. in RMS LSBs: 1.1486 VN. A three-tone multitone signal at 1. 10. Gfllle. respectively. respectively. AWG programmed amplitudes at 1.88 LSBs RMS Calculate the ADC gain at each frequency.21 V at 3 kHz.(2kHz) = 0.2.32 LSBs RMS 3 . 2.19 V at 3 kHz. DUT RMS levels at 1. Subsequently. and 337.52 LSBs RMS 2 .2.kHz output amplitude =120.1 mY. At each frequency. 520. Next.9835 VN.8831 VN.925 V at 2 kHz and 1. and 3 kHz: 310. and 294 mV. and 450 mV. an AWG is set to produce a two-tone multitone signal at 2 and 3 kHz.5. and 3 kHz: 497. 494. Determine the individual gains of the digitizer.kHz amplitude =501 mV RMS 2 . and 408. An FFT is performed on the ADC resulting in the following amplitudes. respectively.93 V at 2 kHz and 1.0531 VN. expressedin bits per volt.1.kHz output amplitude =127.234 and 4.4 to create a fairly accurate three-tone multitone signal with approximately 500 mV RMS at each frequency. The measuredvalues at 1. The digitizer.kHz amplitude =500 mV RMS 3 .19 and 4. the antialiasing filter is connected in the measurementpath and the digitizer RMS output now indicates 0. Ans. Gfllte. A digitizer produces readings of 1. Chapter10 .

and subtract the difference from the measuredphase shift. Like the gain measurement. . most phase measurementsare implemented by simply digitizing the input and output signal of a circuit and then computing their frequency spectra.(t) at each frequency is simply calculated as ' ~tfJ(f) =tfJoutput . Fortunately. they also modify the phase shift of each test tone. the error cancellation depends on the entire measurementpath remaining in the same configuration in both the output measurementand the input measurement. The gain at each frequency is given by the output/input calculations G~c (1 kHz) G ( = 127. 23824 b. we never know when a tester's AWG will produce more significant errors after calibration.1 Phase Shifts In the same way that signal paths modify the amplitude of multitone signals. The total phase shift through multiple cascadedcircuits is equal to the sum of the phase shifts through each of the individual circuits.tfJinput (f) (f) (10. In fact.4. Its!V -. The following example will illustrate this approach. phasesare additive. IV Its These answers are nearly the same as if we divided by the ideal voltage level of 500 mV RMS. However. Therefore.32 LSBs .240 64 b. Consequently it is always a good idea to measure the actual input signal levels with as much accuracy as possible so that the final measurementresults can be adjusted for any residual input errors. It cancels out in the final calculation. from which the phase shift ~f/. 10.4 OrHER AC CALIBRATIONS 10. leading to correlation problems at a later time. if the paths need to change for some reason. we can simply measurethe difference in phase shift between the two configurations.88LSBs499 mV - 501 mV 120. Therefore.52 LSBs = 254. Whereas cascadedgains are multiplicative in nature. The input and output phase at each frequency is derived. just like the gain errors in an analog gain measurement. However.392 An Introductionto Mixed-Signal TestandMeasurement IC Solution: We are tempted to simply divide the ADC outputs by 500 mV to calculate the gain of the ADC at each frequency. we kept a record of the small errors in the AWG amplitudes. -. the phaseshift of the measurementpath is irrelevant. phase errors from cascadedDIB circuits and measurementinstruments are fairly easy to extract. so we can make a more precise measurementof gain.23) Whatever phase shifts are introduced by the measurement path are present in both the input measurementand the output measurement.53 bits/V ) ADC 2 kHz GADC 500 mV ( 3kHz ) _118.

these gains are complex numbers. GDUT.::~ V Figure 10. Solution: The input to the DUT is set at a fairly high signal level of 1.8(b). (The dashed line is to indicate that there is really only one physical digitizer.. This large change in amplitude requires us to set our digitizer to a low input range for the DUT output measurementand a high input range for the DUT input measurement. equivalent (b) linearmodelrepresentation. consider the linear equivalent model of the measurement setup shown in Figure I 0. FocusedCalibrations 393 A DUT includes an analog channel with an attenuation of 100 VN. Since the attenuation is so high.0 V RMS. In general. having a magnitude and phase shift component. V W~~~~--V A ~!. let us sketch a diagram of the test setup.~~~~:~~~ ! Inputrange::t10mV DIGI ~ yr~~ l (a) ~~~~~~--" VDIGI . : I I I I I I GDIGI VDIGI : :' I VDUT ! (b) ~-WG ~ Inputrange::t10 mV GDIG2Input ran. .J~-.:>T-{~::::>. L V v--L__::=. 1 V RMS -10 mV RMS Vjn ~ . where we illustrate the digitization of the input and output nodes of the DUT using two separate instances of the digitizer. In order to keep track of the test data."/--T-l__-=:_~. Here the A WG.8(a).) Now.Example10. we have to measure a very small signal at its output and measure a very high signal at its input.]1~~=AWG l\. f\. resulting in an output signal level of about 10m V RMS.111111111111. respectively.:. This we do in Figure 10. each representing a different range setting on the actual digitizer..7 Chapter10 . DUT and the digitizer on each range setting are modeled with gains GAWG.8.GDIGIand GDIG2.. OUT phase measurement setup: (a) samplinginput and output signals to OUT using a digitizer twoseparate with rangesettings. Determine a calibration scheme that will allow an accurate phase shift measurementof this DUT circuit at a frequency of 1 kHz.. Inputrange::t1 V -10 mV RMS 1 V RMS Vjn 0 Gfilter -1~...

an additional set of measurementsmust be made that involve the digitizer alone. and obtained from an FFT analysis and the phase shift causedby each stage of the test setup as tlt/JAWG. as shown in Figure 10. tlt/JDUT. (10.26) For the phase measurement at hand.Similarly. To obtain this phase mismatch. we are interested in the phase shift caused by the DUT.26) from (10. . (10. For the case described. we write the final result in terms of the data collected from the spectral analysis of the digitizer outputs as tlt/JDUT =(t/JDIGl-t/JDIG2)-(t/JDIG3 -t/JDIG4) (10. obtain this.27).27). and rearrange to get To tlt/JDUT =(t/JDIGl-t/JDIG2)-(tlt/JDIGl-tlt/JDIG2) (10. In practice.9(a). we shall select a signal level of 10 mY. The other has three values can be measured once during the focused calibration process and stored as calibration factors. (10. the phase shift difference between the output of the second digitizer and the input is t/JDIG2 -t/JIN =tlt/J AWG tlt/JDIG2 + (10. we can write VDIGl=GAWG GDUT GDIGI V/N (10.28) Substituting Eq. and tlt/JDIGI. subtract Eq. tlt/JDUT.24) from which we can deduce the total phase difference from output of the first digitizer with respect to the input is t/JDIGl-t/JIN tlt/JAWG+tlt/JDUT +tlt/JDIGl = (10.25). to be measured for each DUT. Subsequently.394 An Introductionto Mixed-Signal Testand Measurement IC According to linear system theory. we have information about the first two terms on the right side ofEq.9(b) to be tlt/JDIGl tlt/JDIG2 t/JDIG3 -t/JDIG4 = (10. the 10-mV signal is digitized on the two range settings. Next.28) into (10.29) Note that only one of these measurements. f/JJN t/JDIGI. The latter two terms represent the phase shift mismatch of the digitizer on the two range settings.the phase mismatch can be found according to the linear representation shown in Figure 10.27) Through the FFT analysis of the digitizer's two outputs.t/JDIGI. we would probably combine the three premeasuredcalibration factors into a single calibration term tPcAL (t/JDIG2 t/JDIG3 t/JDIG4Jto reducethe numberof = + separatecalibration factors.25) Here we distinguish between the phase of the input and output signals. Consider removing the DUT from the test setup and have the AWG generatea signal suitable for the digitizer on the 10-mV and I-V ranges.

-_r~~~~ '-'--l_2::. Exercises 10. VCALIBRATED =tan-I (VDIB).~~ '"' ---v V DIG3 : L Input range :1:10mV ~-«:~~~~~}-o V (a) DIG4 Input range :1:1V 10 mV RMS Vin O -t. The phase difference between the input to a DUT and its output was measured with a digitizer on separate ranges to be -1d16 radians. Write the calibration equation for a DIB circuit that is described by the following output-input equation. 10. v~/~~~l I I VAWGv-"".Chapter10 .4.5. the same phase reference. that is. In addition..".(b) equivalent linearmodelrepresentation.:>T~--~-&~: GAWG GDIGI VDIG3 : : I I I I I VDUT Input range :1:10mV L ~~n: (b) ~ V Figure10./i f\. . Both phase measurements were made in the exact same manner. VDIB = tan (V IN) . FocusedCalibrations 395 11111111 10m V RMS Vin .Measuring phaseshift difference betweentwo rangesof a digitizer:(a) digitizinga signalwith two rangesettingson a digitizer. 0 radians.9. it was determined through a separatemeasurementthat the phase shift difference between the two ranges is +1d16 radians. ADs. What is the phase shift createdby the DUT at this frequency? ADs.

source memory. we cannot use an output-minus-input calculation for . but during phase measurementsthe phase synchronization is critically important. we have to know exactly where the phase of each test tone is located relative to the digital samplessent to or captured from the converter circuit. Test engineers do . One possible solution to this problem is to produce a square wave or similar signal from the digital pattern generator at the frequency of interest and capture it using the digitizer. we might expect the phase shift of the digitized waveform to always come out the same. A WGs. we have treated the AWG and digitizer as if the timing of their waveform creation and capture circuits were well controlled relative to one another and relative to the digital patterns. we can multiply the collected samplesby the inverse transfer curve to extract much of the distortion caused by the digitizer. Since mixed-signal testers do not typically align analog waveforms through ADCs and DACs. This only works if the digitizer sampling times can be repeatedly synchronized to the digital pattern generator.4. if we know the transfer characteristics of a digitizer at a particular frequency. Once the digitizer's phase shift at each frequency of interest is calibrated relative to the digital pattern. Each tester has a different way ofresynchronizing waveform instruments like A WGs. digitizers. digitizers. Fortunately. the A WG and digitizer may very well start sourcing and digitizing samples at a different time each time we make a DSP-based measurement. Some testers may not require resynchronization at all. However. phaseshift and digital signals precisely." the calibration of absolute phase shifts is beyond the scope of this book. the distortion of a tester instrument's DAC or ADC can be compensated to a large degree by thoroughly characterizing the input/output transfer characteristics of the converter. "Sampled Channel Testing. Unfortunately. this technique can be used to determine the digitizer's phase shift relative to the digital pattern generator.2 Digitizer and AWG Synchronization Thus far. Since a square wave has known amplitude and phase characteristics. much of this type of software calibration for distortion removal is already performed by the tester's operating system (at least in advanced mixed-signal testers). 10. it can be used to calibrate the A WG. we may find that the phase of the digitized waveform is different every time we executethe samemeasurement. if we produce a I-kHz sine wave with the A WG and repetitively digitize it.not commonly involve themselves with this kind of advanced focused calibration . In other words. During gain measurements. By building a software table of input voltage versus output code (in the case of ADCs) or input code versus output voltage (in the case of DACs) we can compensate for the nonlinearities of voltmeters.396 An Introduction to Mixed-SignalIC Testand Measurement 10.4. If we do not take care to resynchronize the A WG sample timing with the digitizer sample timing. These details should be covered by the ATE vendor's training class. Unfortunately.3 DAC and ADC Phase Shifts As mentioned in Chapter 9. distortion characteristics vary with frequency.we do not usually worry about the relative timing of the A WG and digitizer. For example. since distortion is neither an additive nor a multiplicative process. 10. and DC sources. and capture memory. so there are many subtleties involved in this process. To measurethe phase shift through an ADC or DAC.4.4 Distortion Tests It is difficult to extract distortion components from cascaded signal paths.

However.correcting each noise component in the FFT spectrum by the digitizer gain at that frequency. We try to take advantage of error cancellation techniques whenever possible.though. 10. 397 process. Occasionally. In theory. This is because uncorrelated random noise always adds constructively rather than destructively. Phase matching is defined as the difference in phase shift from one channel to the other.5 ERROR CANCELLAnON TECHNIQUES 10. Gain matching is defined as the ratio between one channel's gain and the gain of the other channel. accuracy with which measurements can be made. This is becausethe gain errors and phase errors sometimes cancel or "wash out" in the final calculation.2 Gain and Phase Matching Many OUT circuits. Let us look at a couple of techniques that allow us to avoid focused calibration altogether.5 Noise Tests Noise tests. In practice we find that the in-band frequency characteristics of most digitizers are flat enough to produce a reasonably good measurementof noise without any additional focused calibrations. require a high level of performance matching between two supposedly identical circuits. "~ . we should measure the frequency responseof a digitizer across the full spectrum of the noise measurement. since they provide tester performance that might not otherwise be achievable.1 Avoiding Absolute Calibration At thIs point in the chapter. ATE vendors and bench equipment manufacturers are quite familiar with these types of software calibration techniques. ~c. This assumption is verified by correlating the ATE tester's noise measurement to bench equipment as part of the usual tester-to-benchcorrelation effort. 10.4. the reader is probably happy to see the words "avoiding" and "calibration" in the same phrase. whatever noise is measured by the tester is guaranteed to be a worst-case fJ measurement. thus simplifying the focused calibration process. One approach to measuring these parameters is to use two A WGs and two digitizers to measurethe gain and phase of the two channels. a test engineer wants to subtract the noise generatedby the measurementpath ~'.1_1- ChapterFocusedCalibrations 10 . like stereo audio Land R channels and cellular telephone I and Q channels.. If we do this. since noise is a random process and its exact time-varying nature is unknown until after the measurementis made. we have to calibrate the performance mismatch bewteen the two A WGs and digitizers so their mismatch can be subtracted from the 1 ." from the total noise measured. since it leads to simplified test techniquesproviding very high accuracy. The noise floor of the tester's instruments is often the limiting factor in the . Therefore.5. We have already seen how gain measurementsand phase shift measurementscan sometimesbe made without relying on absolute voltage and phase values. The professional test engineer is equally happy to avoid generating hundreds of unnecessary calibration factors. are not typically calibrated as thoroughly as AC amplitude and phase measurements. This is a fact of life for mixed-signal test engineers. 10. that noise from the tester will not cancel noise from the OUT. This idea is fraught with problems. It is fair to assume. like distortion measurements.5.

due to a limitation in the tester's clocking architecture. One UTP representsthe time it takes to cycle through all the samples in a DSP-based measurementwaveform. unnecessary. In such a case. calibration is Sometimes the A WG and digitizer cannot be accurately synchronized for a phase-matching measurement. one channel at a time.10. then we would normally get three identical waveforms. A UTP (see Chapter 6) is a unit test period. as shown in Figure 10. This makes phasematching measurementsvery difficult. In this case. Because the AWG and digitizer never stopped between the first and third UTPs. Focused .398 An Introduction to Mixed-Signal Testand Measurement IC UTP1 Output 1 (__A__-y I UTP2 Swap connections A I UTP3 Output 2 . we produce three sets of samples: one set for Channell. . and one set of garbage samples that contain an abrupt change from Channell to Channel 2. final answer. A simpler solution is to use a single A WG (or source memory pattern) to apply the same signal to both channels at once and then measure the two outputs using a single digitizer. Now if we switch the digitizer from one channel to the other in the middle of the secondUTP. Therefore.10.Three-UTP technique for AWG/digitizer alignment. one set of Channel 2. we can measurethe difference in phaseshift from one channel to the other very accurately by simply subtracting the phase shift of one set of samples from the phase shift of the other set.) ~ I I I I I I I I I I I y I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Mathematical overlay shows gain and phase matching Figure 10. Mathematical overlay shows gain and phase differences. their sample timing is perfectly aligned. If we allow the A WG and digitizer to continue through three UTPs instread of stopping after the first UTP. The garbage samples are discarded. a three-UTP approach can be used to keep the digitizer and A WG sample timing alignedbetweenthe two phase shift measurements. Whatever gain errors and phase shifts are introduced by the A WG and/or digitizer on one channel will be introduced on the other as well.

DUT channelr I r~-.::.5. differential gain and phase could be calculated directly from these two captured waveforms.since the sample timing between the A WG and digitizer remains constant from one channel's sample set to the other... ov~ ~ J ~-J-~~<~~~~~~J D.-.3 Differential Gain and Differential Phase Focused calibrations can sometimes be eliminated using Dill circuits.-. This means that we cannot distinguish between gain and phase shifts causedby the digitizer and those causedby the video circuit. 'g'hze. In practice. Video circuits often include a differential gain and phase specification.. r~-. ov-M- ov~ DUT I channelr ov~ ~-~~.::!. When measuring the differential gain and phase of a video circuit. . What this means in circuit terms is that the AC amplitude and phase shift of the high frequency sine wave have to be unaffected by varying DC offset._<~~~~~ D' . NTSC color TV signals consist of a high frequency sine wave riding on a low frequency intensity signal. once with one DC offset and once with another DC offset... In theory. . Differential phase is defined as the change in phasewith varying DC offset.11. ~. it would seem obvious that we want to digitize a high-frequency sine wave from the circuit's output twice. 10.:. as in the case of differential gain and phase measurements. our digitizer may have a nonideal differential gain and phase of its own. FocusedCalibrations 399 calibration in this case is unnecessary. Any phase shifts caused by the A WG and digitizer therefore cancel out in the final calculation.t 1911lze Measurement 2: negative offset DC blocking capacitor avoids digitizer's differential gain and phase errors../ ~ i Measurement 1: positive offset DvM ovt. It is important that a video channel give the same gain and phase shift at different DC offsets so that the hue and saturation signals are not affected by the slower variations in the brightness signal. Differential gain is defined as the change in AC amplitude with varying DC offset._~ L~":':':'-:"'/ Figure 10. The phaseand amplitude of the high frequency signal determine hue and saturation (color) while the lower frequency signal determinesbrightness._J L~:./ ~.Chapter10 .

707. derive the composite gain and offset of this arrangement.2. Subsequently.05 V at 4 kHz. A simpler technique is to simply block the DC offset of the video circuit output using an RC high-pass filter as shown in Figure 10. Three stages are connected in cascade. From first principles. the digitizer was found to have a gain of 0. and antialiasing filter at 1 kHz are 1.0 V. 1. This would remove any differential gain and phase errors inherent in the A WG. These techniques represent a good starting point for the novice test engineer. A 2. it is certainly not wise to make that assumption.3.1.3. and 4 kHz. the antialiasing filter is connected in the measurement path and the digitizer RMS output now indicates 0. The DC source could be set to the two DC offsets rather than adjusting the DC offset of the A WG signal. Using this technique. an AWG is set to produce a three-tone multitone signal at 2. Next.54 and 3. 10.56 and 3. and 1.471 Vat 2 kHz. What about when four stages are connected in cascade? Extend the formula for N stages connected in cascade? 10. indicates RMS readings of 0. This removes the digitizer's differential gain and differential phase characteristics from the measurement. 0.12.5-V RMS sine wave at 1 kHz is to be . 10. and 0. and 4 kHz from the calibrated data given.6 mY. A calibration sequencedetermined that the amplifier has a gain of 1. The calibration factors associatedwith an A WG.987 V at 4 kHz.400 An Introductionto Mixed-Signal Testand Measurement IC One solution to this problem is to apply a pair of equal-amplitude sine waves to the digitizer with DC offsets corresponding to the two outputs expected from the video circuit. with the antialiasing filter bypassed. In addition. and 1. We have discussed some of the common calibration techniques found in mixed-signal test programs. Focused calibrations are the key to fast. 0.65 V are applied as input.486 Vat 2 kHz. Each tone has an RMS amplitude of 0. Determine the individual gains of the digitizer. 0.98 VN with an offset of -11. Each stage has a gain and an offset.09 V N and an offset of 5. A unity-gain amplifier is used to buffer a signal before it is applied to a digitizer.721 Vat 3 kHz. What is the composite gain and offset for this cascadecombination? Write the calibration equation for this test setup. 3.. The digitizer.998 VN.4. Other focused calibration techniques will have to be learned or even invented as the test engineer's expertise develops.06. We might also want to use an RC blocking circuit terminated to a DC source in the A WG signal path.3 mV. They are also the source of much confusion. and 0. A digitizer produces readings of 0. 10. The difference in digitizer gain and phase can be noted and stored as calibration factors for use during the video circuit output measurements. the digitizer seesthe same DC offset (zero volts) regardlessof the video circuit's DC offset. respectively.6 SUMMARY While it might be reasonable to assume that a multimillion dollar ATE tester is perfectly accurate.5.78 V when two known DC voltage levels of 0. AWG and filter at 2. respectively. Sometimes the tester's accuracy is adequatefor a given test. accurate ATE measurements.11. digitizer.714 V at 3 kHz. Problems 10. respectively. but often the test engineer must improve upon the basic accuracy of the tester using focused calibrations.

43. Subsequently. or an equivalent software package. VDIB=tan(Vjn} A digitizer sampling at 16 kHz captures 64 samples of the output. and 3 kHz is to be generated by an AWG and applied to an ADC. respectively. determine a calibration expression for the Dlli and pass the collected samplesthrough the calibration equation. The measured values at 1. 0. Focused. Next.Using MATLAB. and 3 kHz is to be source to a DAC via the source memory. At a frequency of 1 kHz. determine the signal-to-noise ratio of the output signal. what is the actual RMS value of the DUT output? Assume that the antialiasing filter is connectedin the signal path. the input signal has a phase value of 25 degreesand the output has a phasevalue of -45 degrees. and 0. range Further. what is the gain of the DAC at each frequency? 10.06 LSBs RMS. an FFT was performed on each signal.2. setting the A WG an sourced FFT a 1 kHz signal directly to the value of 1. The input and output signals to a DUT was captured by a digitizer on range setting 1 and setting 2. and 1.. where analysis revealed a phase 10 degrees.998 V RMS. At each frequency. the input signal has a phase value of 25 degreesand the output has a phase digitizer value while of -45 on degrees.13 VN at 1 kHz. The level of each tone should be 800 mV RMS.65 V RMS. A 1 V RMS. I-kHz sinusoidal signal is passedthrough a Dlli circuit whose input-output behavior is described by the equation. respectively..8. I 10. 10. How does it compare if a I-mY RMS random noise component is addedto the collected samples? .53 LSBs RMS. and 799 mY. 2. and 3 kHz are 788. and 41.821. At a frequency of 1 kHz. calculate the gain of the ADC at each frequency. If the digitizer output at each frequency is 1.08 V RMS.What is the phaseshift createdby the DUT? 10..998 VN at 2 kHz. respectively. 0. VDIB.9.987 V N at 3 kHz.Calibrations 401 generated by the A WG. What amplitude should be used to program the A WG? If the digitized value of a DUT is 1. If the corresponding digitized output at each frequency is 41.37 LSBs RMS. Next. ChapterlO . A three-tone multitone signal at 1. the A WG output is measured with a highly accurate RMS voltmeter. the range of the digitizer was change to the second setting where an FFT a!lalysis revealed a phase value of 6 degrees. Perform the same signal-to-noise ratio analysis and compare the result to that obtained previously.What is the phase shift created by the DUT at 1 kHz? 10.5. The input and output signals to a DUT was captured by a digitizer on one range setting and an FFT was performed on each signal. A three-tone multitone signal at 1.02 V RMS. The digitizer was calibrated and has the following calibration scale factors: 1.6. Each tone is to have an amplitude of 1 V RMS. 2.7.

integral nonlinearity (INL) and differential nonlinearity (DNL). an output buffer amplifier. For example. absolute voltage error is consideredto be an intrinsic parameter. In both analog and sampled channels.by contrast. output buffer amplifiers. if that same DAC is used in a voice-band codec to reconstruct voice signals. We care more about its worst-case absolute voltage error. it is common to measure both intrinsic parameters and transmission parameters for characterization." and Chapter 9. and of course the DAC itself. the amplitude and frequency of the sine wave used in a signal-to-distortion test will often affect the measuredresult. Since these errors are determined purely by the quality of the DAC circuitry and not by the nature of the transmitted signal. transmission parametersare determined by the quality of all the channel's subcircuits.. resulting in a set of intrinsic voltage error values. However. signal-to-noise ratio. the signal-to-noise ratio of a DAC channel might be determined by the quality of a low-pass reconstruction filter. For instance. the difference between the actual DC voltage level measuredat a DAC's output and the ideal voltage level is called absolute voltage error. comprising the DAC. and signal to total harmonic distortion. We do not care as much about the DAC's absolute errors as we care about their end effect on the transmission parametersof the composite audio channel.1. Absolute voltage error can be measured at each digital code. They are not dependent on the nature of the test stimulus. "Analog Channel Testing. The production testing strategy is often determined by the end use of the DAC or ADC. etc. Intrinsic parameters are those parametersthat are intrinsic to the circuit itself. ' In this chapter. it is often unnecessaryto perform the full suite of transmission tests and intrinsic tests in production. then we probably do not care about its signal-to-distortion ratio at 1 kHz.-11. such as absolute error. or performance parameters. if a DAC is to be used as a programmable DC voltage reference. are dependenton the nature of the transmitted signal. For example. Unlike digital circuits which can be tested based on what they are L 403 . Transmission parameters. "Sampled Channel Testing. When testing a DAC or ADC. we will focus on the so-called intrinsic parameters of DACs. These parameters are called transmission parameters.1 Intrinsic Parameters versus Transmission Parameters In Chapter 8. then we have a different set of concerns. This example highlights one of the differences between digital testing and specificationoriented mixed-signal testing. On the other hand. since they describe the effect of the analog or sampled channel on the quality of transmitted signals such as voice or modulated data.1 BASICS OF CONVERTERTESTING CHAPTER 11 DAC Testing 11. For example. gain tracking." we discussed common channel parameters such as gain. low-pass filter.

applying the ideal voltage levels for each code and then comparing the actual output code against the expected code. becausean ADC's circuits generaterandom noise and becauseany input signal will include a certain amount of noise. 5 10 15 ----0. While DACs also generaterandom noise. . . . . the code-to-vo1tagetransfer characteristics for a DAC are similar to the vo1tage-to-codecharacteristics of an ADC. In fact. An ADC. 11. Therefore. a DAC produces only one output voltage. We will discuss the probabilistic nature of ADC decision levels and their effect on ADC testing in Chapter 12. etc. . by contrast. (a) DAC code-to-voltage transfer curve (b) ADC voltage-to-code transfer curve. produces the same output code for many different input voltages. For instance.). but it may require a totally different suite of tests depending on its intended functionality in the system-level application. UnfortUnately.1.5 1. video signal generator. flip-flop. unambiguous voltage level for each DAC code. mixed-signal circuits are often tested based on what they do in the system-level application (precision voltage reference.5 DAC 1. . The test engineer might be tempted to test an ADC using the complementary approach. However. voltage. For example. counter.404 1. . it is very important to note that a DAC represents a one-to-one mapping function whereas an ADC represents a many-to-one mapping. This distinction is illustrated in Figure ll.5. .1.since it does .).0 1.l(a) and (b). For each digital input code. a particular analog or mixed-signal subcircuit may be copied from one design to another without change. this noise can be removed through averaging to produce a single. a DAC is often tested by measuring the output voltage corresponding to each digital input code.5 ADC input voltage (b) 0 0 DAC input code (a) Figure 11. this approach is completely inappropriate in most ADC testing cases. the DAC transfer characteristic is truly a one-to-one mapping of codes to voltages.0 output. The difference between DAC and ADC transfer characteristics prevents us from using complementary testing techniques on DACs and ADCs. (NAND gate. 15 ADC 10 output code--- -- -- -- -5-- --- 0. the ADC decision levels representprobable locations of transitions from one code to the next. 00 . An Introductionto Mixed-Signal Testand Measurement IC . many of the conceptspresented are closely tied to ADC testing. Therefore. etc. audio signal reconstruction circuit. .2 Comparison of DACs and ADCs Although this chapter is devoted to DAC testing.

the requirements of the DAC's system-level application also detennine the testing methodology. The DC tests include the usual specifications like gain. There are many different types of DACs.2.635 V:i: 10 mV at digital code + 127. and midscale (VMs) voltage. there are enough similarities that we have to treat the two topics as one.2 BASIC DC TESTS 11. Current output DACs are tested using the same techniques. we will concentratemainly on DAC testing. The dynamic tests are not always perfonned on DACs.11111111- Chapter11 . DAC code errors can be specified as a percentage of the DAC's full-scale range rather than an absolute error. 11. integral nonlinearity (INL).1 Code-Specific Parameters DAC specifications sometimes call for specific voltage levels corresponding to specific digital codes. dynamic tests are common in applications such as video DACs. As previously noted. minimum full-scale (VFs-) voltage. this is not the case. including binary-weighted architectures. Also. resistive divider architectures. this crude testing approach will often fail perfectly good ADCs simply because of gain and offset variations that are within acceptablelimits.1. Although there are many differences in the testing of DACs and ADCs. Each of these DAC architectureshas a unique set of strengthsand weaknesses. Furthennore. where fast settling times and other high-frequency characteristics are key specifications. and differential nonlinearity (DNL). In this chapter. DAC Testing 405 not characterize the location of each ADC decision level.) Alternatively. however. an 8-bit two's complement DAC may specify a voltage level of 1.3. which measure the overall quality of the DAC's code-to-voltage transfer curve. Before we discuss testing methodologies for each type of DAC. Furthennore. monotonicity. They also include converterspecific tests such as absolute error.360 V :i: 10 mV at digital code -128 and a voltage level of 2. there are hybrids of these architectures. However. In Chapter 12 we will see how ADC testing is similar to DAC testing and also how it differs. 11. Each architecture's weaknesses detennines its likely failure mechanisms. The midscale voltage typically corresponds to 0 V in bipolar DACs or a center voltage . pulse-width-modulated (PWM) architectures.3 DAC Failure Mechanisms The novice test engineer may be inclined to think that all N-bit DACs are created equal and are therefore tested using the same techniques. Common code-specific parametersinclude the maximum full-scale (VFS+)voltage. such as the multibit sigma-delta DAC and segmented resistive divider DACs. As we will see. we will concentratemostly on voltage output DACs. offset. the DAC's full-scale range must first be measuredto detennine the appropriate test limits. ~ . using either a current mode DC voltmeter or a calibrated current-to-voltage translation circuit on the device interface board (DIB). etc.2 for a description of converter data fonnats such as unsigned binary and two's complement. power supply sensitivity. In this case. especially those whose purpose is to provide DC or low-frequency signals. and pulse-density-modulated (PDM) architectures (commonly known as sigma-delta DACs). (See Section 9. and these in turn drive the testing methodology. For instance. we first need to outline the DC and dynamic tests commonly perfonned on DACs..

VFS-. Offset. between codes.2. These definitions of offset and gain are approximately correct. and VMS voltages are not in line with the general shapeof the transfer curve. and VFS+voltage outputs while being completely insensitive to variations in all other voltage outputs. 1. This is typically measured by simply measuring the DAC's positive full-scale voltage.VFS-. notice that the gain. in an imperfect DAC.or steps.0 -10 -5 . as it should. T .2 shows a simulated DAC transfer curve for a rather bad 4-bit DAC. and in fact they are sometimes found in data sheets specified exactly this way.2 Full-Scale Range Full-scale range (VFSR) defined as the voltage difference between the maximum voltage and is minimum voltage that can be produced by a DAC. gain for -1.406 An Introductionto Mixed-Signal Testand Measurement IC such as VDd2 in unipolar (single power supply) DACs. They are quite valid in a perfectly linear DAC.1) 11.5 DAC . It is also tempting to define the gain of a DAC as the full-scale range divided by the number of spaces. VFS+. . However. However. Gain Error. It is important to note that although the minimum full-scale voltage is often designated with the VFS-notation.5 Offset based on midpoint code -L outputa voltage -0. it is not necessarily a negative voltage.2. Also. Endpoint/midpoint-referenced andoffset a 4-bitDAC. these definitions are inferior because they are very sensitive to variations in the VFS-. Figure 11. the overall curve has an offset near 0 V. if defined as the full-scale range divided by the number of spaces between codes. does not match the general slope of the curve. then measuring the DAC's negative fullscale voltage. Gain (slope) based on endpoint codes a 5 10 DAC input code Figure 11.3 DC Gain.2.and subtracting VFSR=VFS+-VFS(11. VMS. The problem is that the VFS+. 11. Notice that code 0 does not produce 0 V. and Offset Error It is tempting to say that the DAC's offset is equal to the measuredmidscale voltage. VMS.0 0.

2) The equations slopeand offset can be derivedusingvarioustechniques. % perform best-fit analysis for i=O:N-1. the best-fit line approach is independentofDAC resolution. gaIn =NK 4 -K ) KKK 22 NK3-K) where K) offset=-1--gain-1(11. A best-fit line is commonly defined as the line having the minimum squared errors between its ideal. VAC Testing 407 A less ambiguous definition of gain and offset can be found by computing the best-fit line for these points and then computing the gain and offset of this line. such as the following MATLAB routine: % Store DAC output voltages in vector S % % % Initialize routine k1=O. k2=O. N=length(S). k2 = k2 + S(i+1).! The equations derivedfrom the partialderivativetechnique are . k1 = k1 + i.Chapter11 . the best-fit line is defined by its slope (DAC gain) and offset using a standard linear equation having the form Best_fit_line =gain xi + offset fori=O.One technique for minimizesthe partial derivatives with respect slopeand offset of the squared to errorsbetween the sampleset S and the best-fit line.. For high-resolution DACs with reasonablelinearity.I.. Best_fit_line(i+1) =Gain*i + Offset. = - - k1*k1).. Nevertheless. the errors between these two techniques become very small. end Gain = (N*k4 k1*k2) / (N*k3 Offset k2/N-Gain * (k1/N).N-1 (11. k3=O. Another techniqueis basedon linear regression. end . For a sample set S(i).. evenly spaced samples and the actual DAC output samples.3) N N =L i i=O N-) K2 = L S(i) i=O N-) N-l K3 = i2 L K4 =L i S(i) i=O N-l i=O The derivation details are left as an exercise in the problem set foUnd at the end of this chapter. k4=O. These equations translate very easily into a computer program. where i ranges from 0 to N-I and N is the number of samplesin the sample set. for i=O:N-1. so it is the preferred technique. k4 = k4 + i*S(i+1). k3 = k3 + i*i.

The DAC's offset is defined as the voltage at which the best-fit line crossesthe y axis. Solution: We calculate gain and offset using the previous MATLAB routine.voltage. This gain value is the average gain across all DAC samples. The ideal voltage at the DAC 0 code can be subtracted from this value to calculate the DAC's offset error. -705 mY. Unlike the gain calculated from the full-scale range divided by the number of code transitions. to find the DAC's offset. 195 mY. The ideal gain is equal to 100 mV/bit. The y axis correspondsto DAC code O. 370 mV.4) Likewise. In unsigned binary DACs. This discrepancy arises simply because we cannot use negative index values in MATLAB code arrays such as Bestyt_line(-128). -400 mY.is defined as 6. 825 mV These code levels are shown in Figure 11. in two's complement DACs. Therefore.64 mY. offset. gain error. Calculate the DAC's gain (volts per bit). -75 mY. starting from code -8 and progressing through code +7: -780 mY.35 mV -1 100 mV ) XI00%=9.G= (~-1 G1DEAL ) X100% (11.4) to be 6. Therefore. (11. Gain error. The ideal DAC output at code 0 is 0 V. The program variable Gain representsthe gain of the DAC. 500mV. 120mV. expressedas a percen~. However.35 mV/bit and an offset value of -797. It is based on all samples in the DAC transfer curve and therefore is not especially sensitive to anyone code's location. 445 mY. the slope of the best-fit line representsthe true gain of the DAC. and therefore does not correspond to DAC code O.1 A 4-bit two's complement DAC produces the following set of voltage levels. Example 11.G. The value at this array location is equal to the DAC's offset. one must determine which sample in vector Bestyt_line corresponds-tothe DAC's 0 code.750mV. -325 mY. the best-fit line's calculated offset is not dependenton a single code as it is in the midscale code method. the best-fit line offset representsthe offset of the total sample set. this voltage correspondsto Bestyt_line(l) in the MATLAB routine. -530 mY.this offset value is the offset of the best-fit line. Instead. The DAC's offset error is equal to its offset minus the ideal voltage at this point in the DAC transfer curve. 575 mV.3. resulting in a gain value of 109. 6. The gain error is found from Eq. the value of Bestyt_line(l) corresponds to the DAC's VFs. and offset error. -150 mY. for example. the 0 code point is located at i = 128. not the offset of the DAC at code -8.G= ( 109. .35% Because this DAC uses a two's complement encoding scheme. in volts per bit. -455 mY. In an 8-bit two's complement DAC. the value of the program variable Offset does not correspond to the DAC's offset.408 An Introductionto Mixed-Signal Testand Measurement IC The values in the array Bestyt_line represent samples falling on the least-squared-errorline.

10 such a case. Although it is possible to measurethe approximate LSB size by simply dividing the full-scale range by the number of code transitions. These DACs are commonly used in applications requiring a single power supply.Chapter11 .35 mY.35 mVx8-797. 11.4 LSB Step Size The least significant bit (LSB) step size is defined as the average step size of the DAC transfer curve..16 mV mV DAC offset error = DAC offset = 77. which correspondsto i = 8 DAC offset = gainx8 + offset = 109. the DAC offset and offset error are identical. but the offset error should always be zero. . T -1000 -8 -6 -4 -2 0 2 4 6 8 DAC input code Figure 11. DAC Testing 409 1000 500 DAC output voltage (mV) -500 0 DAC offset .OV = 77. it is more accurate to measure the gain of the best-fit line to calculate the average LSB size. A 4-bit DAC transfer curve and best-fit line. the 4-bit DAC's LSB step size is equal to 109.2. It is equal to the gain of the DAC. when the ideal offset is 0 V.l6mV Clearly. Many DACs have an ideal offset of VDd2 or some other nonzero value.64 = 77.l6mV ideal offset .3. the offset should be nonzero. in volts per bit. Using the results from the previous example. The DAC's offset is found by calculating the best-fit line's value at DAC code 0.

1. What are the gain error and offset error? Ans. using the endpoint method). A 4-bit unsigned binary DAC produces the following set of voltage levels.9%.r this DAC specifies offset and offset using a best-fit line.3 mV/bit. so we have to define figures of merit for their actual transfer curves.The conversion from volts to LSBs is a processcalled normalization. offset.1.e. = 11.9453. the offset error of the transfer curve should be zero. and offset error. VLSB.3357. least ambiguous figures of merit is the DAC's maximum and minimum absolute error.1. 11. Worst-case conditions should be used once they have been determined through characterization of the DAC.0091. The only difference is that a DAC may have different PSS performance depending on the applied digital code.2.3363.1.2.3 TRANSFERCURVE TESTS 11.1453.2 mY.1 using its measured full-scale range (i.8491.3206.1.1.410 11. 1. Gain is also specified using a best-fit line. as described in Section 3.2030.026 V. gain error.5617. ADs. G= 177.4522. .2.0871. starting from code 0 and progressing through to code 15: 1.1 Absolute Error The ideal DAC transfer characteristic or transfer curve is one in which the step size between each output voltage and the next is exactly equal to the desired LSB step size. An absolute error curve is calculated by subtracting the ideal DAC output curve from the actual measured DAC curve. Usually. offset error = 9.6218 The ideal DAC output at code 0 is 1 V and the ideal gain is equal to 200 mV /bit.2.4834.3%. 3. The data sheet fo. Estimate the LSB step size of the DAC described in Exercise 11.1 mY.1 mY.8. physical DACs do not behave in an ideal manner. Calculate the DAC's gain (volts per bit).6529. The values on the absolute error curve can be converted to LSBs by dividing each voltage by the ideal LSB size. PSS for a DAC is therefore identical to the measurement of PSS in any other circuit. a DAC will exhibit the worst PSS performance at its full-scale and/or minus full-scale settings becausethese settings tie the DAC output directly to a voltage derived from the power supply.6925.5 DC PSS An Introduction to Mixed-Signal Testand Measurement IC DAC DC power supply sensitivity (PSS) is easily measured by applying a fixed code to the DAC's input and measuring the DC gain from one of its power supply pins to its output. offset error = 26. LSB=174.9965. One of the simplest.3. Of course. offset = 1. 2. evaluated at code O. 3. L1G -12.2.3. .2. Also. Exercises 11. L1G= -11.3.2.

1.. -4 O. +75 mY. Normalized DACerrorcurve. DAC 1. +25 mY.5 ..4. absolute errors of several LSBs are common. In a simple 4-bit DAC. .. but this is an imaginary DAC designed for instructional purposes. 0.7 and -Q. +95 mY. -2 0 2 4 DAC input code . we can calculate the absolute voltage errors ~(i) as: +20mV. then we can write the normalized absolute error transfer curve ~(i) as ~(i) = S(i)-SIDEAL (i) VLSB (11.5) Example11.4. DAC Testing 411 Mathematically. -25 mV.2 Assuming an ideal gain of 100 mV per LSB and an ideal offset of 0 V at code 0.25 LSBs. calculate the absolute error curve for the 4-bit DAC of the previous example. +45 mY. Solution: The ideal DAC levels are -800. +70 mV. . . -5 mV. -0. respectively. . 6 8 Figure 11. respectively. if we denote the ith value on the ideal and actual transfer curves as SIDEAL(IJ and S(i). this would be considered very bad performance. The larger 2.5 .0 . . Express the results in terms of LSBs. on the other hand. -700. +145 mY. . Dividing each value by the ideal LSB size (100 mY). OmV. ..5 -8 -6 . +120 mY. In highresolution DACs. we get the normalized error C¥rve shown in Figure 11. +700 mY. +150mV. Subtracting these ideal values from the actual values. +50 mV. This curve shows that this DAC's maximum and minimum absolute errors are + 1. +100 mY. +170 mY. +125 mV The maximum absolute error is + 170 mV and the minimum absolute error is -25 mV.Chapter11 . ..0 absolute error (LSBs) .

Therefore. Monotonicity testing requires that we take the discrete first derivative of the transfer curve. 75 mY.3. 75 mY.6) If the derivatives are all positive for a rising ramp input or negative for a falling ramp input. (If the voltage ramp is expectedto decreasewith increasing code values. 11. expressed in fractions of an LSB.3 Verify monotonicity in the previous DAC example.2 Monotonicity A monotonic DAC is one in which each voltage in the transfer curve is larger than the previous voltage. 11. we simply have to make sure that each voltage is less than the previous one. then the DAC is said to be monotonic. 75 mY.) While the 4-bit DAC in the previous examples has a terrible set of absolute errors.3. offset. each step would be exactly 100 mV corresponding to the ideal LSB step size. yielding the following values 75 mY. Example 11. Differential nonlinearity (DNL) is a figure of merit that describes the uniformity of the LSB step sizes between DAC codes. 75 mV Notice that there are only 15 first derivative values. Solution: The first derivative of the DAC transfer curve is calculated. 75 mY. even though there are 16 codes in a 4-bit DAC. This is the nature of the discrete derivative. it is neverthelessmonotonic.3 Differential Nonlinearity Notice that in the monotonicity example the step sizes are not uniform. In a perfect DAC. 175 mY. 75 mY. 55 mY. the DAC is monotonic. since there are one fewer changes in voltage than there are voltages. 175mV. absolute error testing is often replaced by gain. DNL is also known as differential linearity error or DLE for short.412 An Introductionto Mixed-SignalIC Testand Measurement normalized absolute error in high-resolution DACs is a result of the smaller LSB size. DNL is . and linearity testing in highresolution DACs. denotedhere as S' ( i) . 75 mY. according to S'(i)=S(i+l)-S(i) (11. Since each value in this example has the same sign (positive). 175 mY. The DNL curve represents the error in each step size. 195 mY. assuming a rising voltage ramp for increasing codes. 175 mY. 55 mY.

3215 -1.0.0.2735. -0. Best-fit DNL uses the best-fit line's slope to calculate the average LSB size. This technique is less commonly used. as long as the DAC does not exhibit grotesque .5375.4.1477. Assuming an ideal gain of 200 mV/bit and an ideal offset of 1 Vat code 0.1939.3970. The difference is that the best-straight-line method is based on the line that gives the best answer for integral nonlinearity (INL) rather than the line that gives the least squared errors.0. The choice of technique is not terribly important in DNL calculations. DAC Testing 413 Exercises 11. This technique dependson the actual values for the maximum full-scale (VFS+) and minimum full-scale (VFs-) levels.0.3. VLSB) from the derivative result.0. Is the DAC output monotonic? Ans.1308. we can define the LSB size as the ideal DAC step size.0. endpoint. Thus the order of methods from most relaxed to most demanding is best-straight line.. 0.0455. As such it is highly sensitive to errors in these two values.0. subtracting one LSB (i.0. -0.7390 -0.7) VLSB As previously mentioned.1.7545 -1.1488.1915. There are four basic types ofDNL calculation method: best-fit.S (i ). since it accommodates gain errors in the DAC without relying on the values of a few individual voltages.1904. Endpoint DNL is calculated by dividing the full-scale range by the number of transitions. endpoint. we can define the average LSB size in one of three ways.1962. 0. -0. Compute the discrete first derivative of the DAC transfer curve given in Exercise 11.e. Alternatively.1474.5645.0. -0.2254. We can define it as the actual full-scale range divided by the number of code transitions (number of codes minus 1) or we can define the LSB as the slope of the best-fit line.V L". it is the most relaxed specification method of the four..0175 -1.7355 -0. -0. computed by calculating the discrete first derivative of the DACs transfer curve. since it assumesthe DAC's gain is ideal.3185.1333. and best-straight-line.1.0.1316. The choice of LSB calculations depends on what type of DNL calculation we want to perform. Integral nonlinearity will be discussed later in this chapter. 0.1384 The DAC is monotonic since there are no negative values in the discrete derivative. best-fit.0. LSBs C'D (11.8910 11. Normalize the result to 1 LSB. The absolute DNL technique uses the ideal LSB size derived from the ideal maximum and minimum full-scale values.0150. The best-straight-line method is similar to the best-fit line method. then normalizing the result to one LSB DNL(i) = S (i + 1) .Chapter11 .2735 -1.2007. -0. and absolute. 0. Since the best-straight-line method is designed to yield the best possible answer. This is probably the best technique. absolute. It is used only in cases where the DAC or ADC linearity performance is not critical. Any of the three techniques will result in nearly identical results.0. and is therefore less ideal than the best-fit technique.2335. 0.2528.5830 -1. Ans. -0.1418. calculate the absolute error transfer curve for the 4-bit DAC of Exercise 11.

Example 11.783. but the maximum DNL value exceeds the +112 LSB limit. 0.0.6. DNL values of :f:1/2 LSB are usually specified.1. -0. Therefore. was calculated in Example 11.0. 175 mY.314.686. 195 mY. Is this result significantly different from the best-fit calculation? Solution: The first derivative of the transfer curve was calculated in the previous monotonicity example.686.4 Calculate the DNL curve for the 4-bit DAC of the previous examples.0. 0. 75 mY. 75 mV The average LSB size.686. -0.314.1 using the best-fit line calculation. this DAC fails the DNL specification of :f:1/2 LSB.0. -0.686. The choice of technique is actually more important in the integral nonlinearity calculation. The minimum value is within the -1/2 LSB test limit.497. while the minimum DNL value is -0.5 shows the DNL curve for this DAC.686 Subtracting one LSB from each of these values gives us the DNL values for each code transition of this DAC expressedas a fraction of an LSB -0. The first derivative values are 75 mY. A 1% error in the measurementof the LSB size would result in only a 0.6.783.1. The averageLSB size calculated using the endpoint method is given by 1LSB= VFS+-VFSnumber of codes-1 mY) = 825 mV -(-780 16-1 = 107mV .497.6.414 An Introduction to Mixed-Signal TestandMeasurement IC gain or linearity errors.0. -0.503.6. 75 mY.497.0. 55 mY. which is tolerable in most cases. 175 mY. -0.6. The maximum DNL value is +0. Does this DAC pass a :f:1/2 LSB specification for DNL? Use the endpoint method to calculate the averageLSB size.0.783 LSB.503. Use the best-fit line to define the average LSB size. -0. -0. 75 mY.35 mV. -0.1. Dividing each step size by the average LSB size yields the following nonna1ized derivative values (in LSBs) 0.6.686. with typical DAC perfonnance of :f:1/4 LSB for reasonably good DAC designs.314.6.01 LSB error in the DNL results.314. 175 mY. 0. -0.686.0. 75 mY.0.314 Note that there is one fewer DNL value than there are DAC codes. 109.314.1.1.314. 0.314. Figure 11. which we will discussin the next section. 55 mY.686.6. 75 mY.0. 175 mY. 75 mY.

. 0. -0. -0.299. . 0.299.5. DNL -0.299. 0. --J 6 8 DAC input code Figure11.822. -6 -4 -2 .0 -8 . .0 -8 .5. 1.486. 2 . 4 . . -0. which have been normalized to an LSB size of 107 mV -0. Instead of a maximum DNL result of +0. DAC Testing 415 0. -1. -0.636.5. (LSBs) 0 . curve 4-bitDAC DNL for (best-fit method).636. . . 0 2 4 6 8 DAC input code Figure 11.299. . get we slightly different results. .486.299 The corresponding DNL curveis shownin Figure 11. The DNL curve calculated using the endpoint method gives the following values. 0.0 . 0.783 LSB and a minimum .299. -0. . -6 .299. DNLcurvefor 4-bit DAC(endpoint method). 0 . -0.299. -1. .5.6.636. -0.636. . .6. 0 -0. -2 . Using the endpointcalculation. -0.5.-0. DNL (LSBs) .0 0. . -4 .Chapter11 1.

416

An Introductionto Mixed-Signal Testand Measurement IC

DNL of -0.497 LSB, we get +0.822 and -0.486 LSB, respectively. This might be enough of a difference compared to the best-fit technique to warrant concern. Unless the endpoint method is explicitly called for in the data sheet, the best-fit method should be used since it is the least sensitive to abnormalities in anyone DAC voltage.

Exercises 11.5. Calculate the DNL curve for the 4-bit DAC of Exercise 11.1. Use the best-fit line to define the average LSB size. Does this DAC pass a :i:l/2 LSB specification for DNL? Ans.0.0937, -0.2481,0.2714, -0.2622, 0.4259, -0.2002, 0.3170, -0.2577, 0.1320,0.1067 -0.1686, -0.1607, 0.0739, -0.1669, -0.2194; pass 11.6. Calculate the DNL curve for the 4-bit DAC of Exercise 11.1. Use the endpoint method to calculate the averageLSB size. Does this DAC pass a :i:1/2 LSB specification for DNL? Ans. 0.1132 -0.2347, 0.2941 -0.2491,0.4514 -0.1859, 0.3406 -0.2445, 0.1523,0.1264 -0.1537 -0.1457, 0.0931 -0.1520 -0.2054; pass

11.3.4 Integral Nonlinearity The integral nonlinearity curve is a comparison between the actual DAC curve and one of three lines: the best-fit line, the endpoint line, or the ideal DAC line. The INL curve, like the DNL curve, is normalized to the LSB step size. As in the DNL case, the best-fit line is the preferred reference line, since it eliminates sensitivity to individual DAC values. The INL curve can be calculated by subtracting the reference DAC line (best-fit, endpoint, or ideal) from the actual DAC curve, dividing the results by the averageLSB step size according to INL(i)

= S(i)-SREF (i)
VLSB

(11.8)

Note that using the ideal DAC line is equivalent to calculating the absolute error curve. Since a separate absolute error test is often specified, the ideal line is seldom used in INL testing. Instead, the endpoint or best-fit line is generally used. As in DNL testing, we are interested in the maximum and minimum value in the INL curve, which we compare against a test limit such as :i:1/2 LSB.

Example 11.5 Calculate the INL curve for the 4-bit DAC in the previous examples. First use an endpoint calculation, then use a best-fit calculation. Does either result pass a specification of :i:1/2 LSB? Do the two methods produce a significant difference in results?

II_~:!:E
Solution:

Chapter]]

.

DACTesting

417

J
,

Using an endpoint calculation method, the INL curve for the 4-bit DAC of the previous examples is calculated by subtracting a straight line between the VFs-voltage and the VFS+ voltage from the

DAC output curve. The differenceat eachpoint in the DAC curve is divided by the average

f

LSBsize, whichin this case calculated is usinganendpoint method.As in theendpoint DNL
example,the average LSB size is equal to 107 mY. The resultsof the INL calculationsare
(again, thesevalues are expressedin LSBs) 0.0, -0.299, 0.336, 0.037, -0.449, -0.748, -0.112, -0.411, 0.411,0.112,0.748,0.449, -0.037, -0.336, 0.299, 0.0 Figure 11.7 shows this endpoint INL curve. The maximum INL value is +0.748 LSB, and the minimum INL value is -0.748. This DAC does not pass an INL specification of %1/2LSB. Using a best-fit calculation method, the INL curve for the 4-bit DAC of the previous examples is calculated by subtracting the best-fit line from the DAC output curve. Each point in the difference curve is divided by the average LSB size, which in this case is calculated using the best-fit line method. As in the best-fit DNL example, the average LSB size is equal to 109.35mY. The results of the INL calculations are
9.161, -0.153, 0.448, 0.133, -0.364, -0.678, -0.077, -0.392, 0.392,0.077,0.678,0.364, -0.133, -0.448, 0.153, -0.161 value is -0.678. These INL results are better

The maximum value is +0.678, and the minimum

than the endpoint INL values, but still do not pass a %1/2 LSB test limit. The best-fit INL curve is shown in Figure 11.8 for comparison with the endpoint INL curve. The two INL curves are somewhat similar in shape,but the individual INL values are quite different. Remember that the DNL curves for endpoint and best-fit calculations were nearly identical. So, as previously stated, the choice of calculation technique is much more important for INL curves than for DNL curves. Notice also that while an endpoint INL curve always begins and ends at zero, the best-fit curve 1.0

I

.
0.5 INL
(LSBs) 0

.
.

.

.

..
.

.

.

..
4

~
8

-0.5

.
.
-2 0 2 DAC input code

.

.1.0

-8

-6

-4

6

Figure

11.7. INL curve calculated using the endpoint linearity method.

418 1.0

An Introductionto Mixed-SignalIC Testand Measurement

0.5

.

.
.
.

.
.

.

INL
(LSBs) 0

.
-8 -6

-0.5

.
.
-4 -2

.
0 2 DAC input code

.
.
4

.

.
8

-1.0

6

Figure 11.8. INLcurvecalculated usingthe best-fitlinearitymethod. does not necessarily behave this way. A best-fit curve will usually give better INL results than an endpoint INL calculation. This is especially true if the DAC curve exhibits a bowed shapein either the upward or downward direction. The improvement in the INL measurementis another strong argument for using a best-fit approach rather than an absolute or endpoint methoc;l,since the best-fit approach tends to increaseyield.

The INL curve is the integral of the DNL curve, thus the term "integral nonlinearity"; DNL is a measurementof how consistent the step sizes are from one code to the next. INL is therefore a measure of accumulated errors in the step sizes. Thus, if the DNL values are consistently larger than zero for many codes in a row (step sizes are larger than I LSB), the INL curve will exhibit an upward bias. Likewise, if the DNL is less than zero for many codes in a row (step sizes are less than 1 LSB), the INL curve will have a downward bias. Ideally, the positive error in one code's DNL will be balanced by negative errors in surrounding codes and vice versa. If this is true, then the INL curve will tend to remain near zero. If not, the INL curve may exhibit large upward or downward bends, causing INL failures. The INL integration can be implemented using a running sum of the elements of the DNL. The ith element of the INL curve is equal to the sum of the first i-I elements of the DNL curve plus a constant of integration. When using the best-fit method, the constant of integration is equal to the difference between the first DAC output voltage and the corresponding point on the best-fit curve, all normalized to one LSB. When using the endpoint method, the constant of integration is equal to zero. When using the absolute method, the constant is set to the normalized difference between the first DAC output and the ideal output. In any running sum calculation it is important to use high-precision mathematical operations to avoid accumulated math error in the running sum. Mathematically, we can expressthis processas
INL(i)

= L DNL(k)+C
k=O

i-I

(11.9)

~
where

.
C=

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DAC Testing

419

S(O)-Best - fit - line (0) VLSB 0 S(O)-SIDEAL(O)

for best-fit linearity method for endpoint linearity method for absolute linearity method

~~

VLSB

and i=O indicates the DAC level corresponding to VFs-. Conversely, DNL can be calculated by taking the first derivative of the INL curve

DNL(i)=INL'(i)=INL(i+l)-INL(i)

,

(11.10)

This is usually the easiest way to calculate DNL. The first derivative technique works well in DAC testing, but we will see in the next chapter that the DNL curve for an ADC is easier to capture than the INL curve. In ADC testing it is more common to calculate the DNL curve first, and then integrate it to calculate the INL curve. In either case,whether we integrate DNL to get INL or differentiate INL to get DNL, the results are mathematically identical. Integral nonlinearity and differential nonlinearity are sometimes referred to by the names integral linearity error (ILE) and differential linearity error (DLE). However, the terms INL and DNL seem to be more prevalent in data sheets and other literature. We will use the terms INL and DNL throughout this text. 11.3.5 Partial Transfer Curves A customer or systemsengineer may specify that only a portion of a DAC or ADC transfer curve must meet certain specifications. For example, a DAC may be designed so that its VFs-code corresponds to 0 V. However, due to analog circuit clipping as the DAC output signal

Exercises 11.7. Calculate the INL curve for a 4-bit unsigned binary DAC whose DNL curve is describedby the following values (in LSBs) 0.0937, -0.2481, 0.2714, -0.2622, 0.4259, -0.2002, 0.3170, -0.2577, 0.1320, 0.1067, -0.1686, -0.1607, 0.0739, -0.1669, -0.2194 The DAC output for code 0 is 1.0091 V. 177.3 mV /bit and an offset of 1.026 V. Assume that the best-fit line has a gain of

Ans. -0.0959, -0.0022, -0.2503, 0.0210, -0.2412, 0.1847, -0.0155, 0.3016, 0.0438,0.1759,0.2825,0.1139, -0.0467, 0.0272, -0.1397, -0.3591

420

An Introduction to Mixed-SignalIC Testand Measurement

approaches ground, the DAC may clip to a voltage of 100 mY. If the DAC is designed to perform a specific function that never requires voltages below 100 mV, then the customer may not care about this clipping. In such a case, the DAC codes below 100 mV are excluded from the offset, gain, INL, DNL, etc. specifications. The test engineer may then treat these codesas if they do not exist. This type of partial DAC and ADC testing is becoming more common as more DACs and ADCs are designed into custom applications with very specific requirements. General-purpose DACs are unlikely to be specified using partial curves, since the customer's application needsare unknown. 11.3.6 Major Carrier Testing The techniques discussedthus far for measuring INL and DNL are based on a testing approach called all-codes testing. In all-codes testing, all valid codes in the transfer curve are measuredto determine the INL and DNL values. Unfortunately, all-codes testing can be a very timeconsuming process. Depending on the architecture of the DAC, it may be possible to determine the location of each voltage' in the transfer curve without measuring each one explicitly. We will refer to this as selected-codetesting. Selected-codetesting can result in significant test time savings, which of course represents substantial savings in test cost. There are several selected-code testing techniques, the simplest of which is called the major carrier method. Many DACs are designed using an architecture in which a series of binary-weighted resistors or capacitors are used to convert the individual bits of the converter code into binary-weighted currents or voltages. These currents or voltages are summed together to produce the DAC output. For instance, a binary-weighted unsigned binary DAC's output can be described as a sum of binary-weighted voltage or current values, Wo, WI, ..., Wn,multip~ied by the individual bits of the DAC's input code, Do, DI, ..., Dn. The DAC's output value is therefore equal to DAC output =DoWo+~Wi +...+DnWn +DC base (11.11)

where DAC code bits Do - Dn take on the value of 1 or 0 Wi =2Wo Wz = 2Wi

Wn=2Wn-l DC base is the DAC output value with a VFS-input code If this idealized model of the DAC is sufficiently accurate, then we only need to measurethe values of Wo, WI, ..., Wnto predict every voltage in the DACs transfer curve. This DAC testing method is called the major carrier technique. The major carrier approach can be used for ADCs as well as DACs. The assumption of sufficient DAC or ADC model accuracy is only valid if the actual superposition errors of the DAC or ADC are low. This mayor may not be the case. The superposition assumption can only be determined through characterization, comparing the allcodes DAC output levels with the ones generatedby the major carrier method.

pl-

-

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DAC Testing

421

The most straightforward way to measurethe value Wois to set DAC code bit Do to one and all other bits to zero. Likewise, the other major carrier values Wn can be measuredby setting Dn to one and all other bits to zero. However, the resulting output levels are widely different in magnitude. This makes them difficult to measure accurately with a voltmeter, since the voltmeter's range must be adjusted for each measurement. A better approach that alleviates the accuracy problem is to measurethe step size of the major carrier transitions in the DAC curve, which are all approximately 1 LSB in magnitude. A major carrier transition is defined as the voltage (or current) transition between the DAC codes 2n-l and 2n. For example, the transition between binary 00111111 and 01000000 is a major carrier transition. Major carrier transitions can be measured using a voltmeter's sample-and-difference mode, giving highly accurate measurementsof the major carrier transition step sizes. Once the step sizes are known, we can use a series of inductive calculations to find the values of Wo,WI, ..., Wn. We start by realizing that we have actually measuredthe following values: DC base

= measuredDAC

output with minus full-scale code

Vo =Wo Vi = Wj -Wo ,~', V2 =W2-(Wj+WO) V3=W3-(W2+Wj+WO)

Vn= Wn-(Wn-1 +Wn-2 +Wn-3 +...+Wo) The value of the first major transition, Yo,is a direct measurement of the value of Wo(the step size of the least significant bit). The value of Wi can be calculated by rearranging the second
equation: WI = VI + Woo Once the values of Wo and WI are known, the value of W2 is calculated by rearranging the third equation: W2 = V2 + WI + Wo, and so forth. Once the values of Wo- Wo

are known, the complete DAC curve can be reconstructed for each possible combination of input bits Do-Dousing the original model of the DAC described by Eq. (11.11). The major carrier technique can also be used on signed binary and two's complement converters, although the codes corresponding to the major carrier transitions must be chosen to match the converter encoding scheme. For example, the last major transition for our two's complement 4-bit DAC example happensbetween code 1111 (decimal-I) and 0000 (decimal 0). Aside from these minor modifications in code selection, the major carrier technique is the same as the simple unsigned binary approach.

Example 11.6 Using the major carrier technique on the 4-bit DAC example, we measure a DC base of -780 mV setting the DAC to VFs-(binary 1000, or -8). Then we measure the step size between 1000 (-8) and 1001 (-7). The step size is found to be 75 mY. Next we measure the step size between 1001 (-7) and 1010 (-6). This step size is 175 mY. The step size between 1011 (-5) and 1100 (-4) is 55 mV and the step size between 1111 (-1) and 0000 (0) is 195 mV. Determine the values of Wo,WI, W2,and W3. Reconstruct the voltages on the ramp from DAC code -8 to DAC code +7.

422

An Introductionto Mixed-Signal Testand Measurement IC

Solution: Rearranging set of equationsVn= the obtain:
DC baseline = measuredDAC output with VFS- code
Wn -

(Wn-I+Wn-2+Wn-3 + Wo) to solve for Wn,we + ...

.
(11.12)

=-780

mV

Wo=Vo =75 mV
W;

=Vi +Wo=175mV+75mV=250 mV

W2=V2 +W; +Wo =380 mV W3=V3 +W2+W;+WO =900 mV For a two's complement DAC, we have to realize that the most significant bit is inverted in polarity compared to an unsigned binary DAC. Therefore, the DAC model for our 4-bit DAC is given by DAC output =DoWo +~W;
+D2W2 +D;W3 +DC base

Using this two's complement version of the DAC model, the 16 voltage values of the DAC curve are reconstructedas shown in Table 11.1.
~!' ;

I

Table 11.1. DAC Transfer Curve Calculated Using the Major Carrier Technique

DAC Code 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111

Calculation DC Base Wo+DC Base W1+DC Base W1+Wo+DC Base W2+DCBase W2+Wo+DC Base W2+W1+DC Base W2+W1+Wo+DC Base W3+DC Base W3+Wo+DC Base W3+W1+DC Base W3+W1+Wo+DC Base W3+W2+DC Base W3+W2+Wo+DC Base W3+W2+W1+DC Base W3+W2+W1+Wo+DC Base

Output Voltage -780mV -705mV -530mV -455mV -400mV -325mV -150mV -75 mV 120mV 195mV 370mV 445 mV 500mV 575mV 750mV 825mV

11111111..

-

Chapter Testing 11 pAC .

423

Notice that these values are exactly equal to the all-codes results in Figure 11.4. The example DAC was created using a binary-weighted model with perfect superposition; so it is no surprise the major carrier technique works for this imaginary DAC. Real DACs and ADCs often have superposition errors that make the major carrier technique unusable.

11.3.7 Other Selected-Code Techniques Besides the major carrier method, other selected-codetechniques have been developed to reduce the test time associatedwith all-codes testing. The simplest of these is the segmentedmethod. This method only works for certain types of DAC and ADC architectures, such as the 12-bit segmented DAC shown in Figure 11.9. Although most segmented DACs are actually constructed using a different architecture than that in Figure 11.9, this simple architecture is representativeof how segmentedDACs can be tested. The example DAC uses a simple unsigned binary encoding scheme with twelve data bits, D II-DO. It consists of two portions, a 6-bit coarse resolution DAC and a 6-bit [me resolution DAC. The LSB step size of the coarse DAC is equal to the full-scale range of the [me DAC plus one fine DAC LSB. In other words, if the combined 12-bit DAC has an LSB size of VLSB, then the [me DAC also has a step size of VLSB, while the coarse DAC has a step size of 26X VLSB. The output of these two 6-bit DACs can therefore be summed together to produce a 12-bit DAC DAC output =coarseDAC contribution + fine DAC contribution

(11.13)

Both the fine DAC and the coarseDAC are designedusing a resistive divider architecture (see Section 11.5.1), rather than a binary-weighted architecture. Since major carrier testing can only be performed on binary-weighted architectures, an all-codes testing approach must be used to verify the performance of each of the two 6-bit resistive divider DACs. However, we would like to avoid testing each of the 212, or 4096 codes of the composite 12-bit DAC. Using superposition, we will test each of the two 6-bit DACs using an all-codes test. This requires only 2x26, or 128 measurements. We will then combine the results mathematically into a 4096-point all-codes curve using a linear model of the composite DAC. Coarse OAC LSB size = 26XVLSB OAC code
bits 011-06 12-bit ,

OAC code bits 05-00 Fine OAC
LSB size = VLSB

OAC output LSB size = Visa

~

Figure 11.9. Segmented DAC conceptual blockdiagram.~

424

An Introduction to Mixed-Signal Testand Measurement IC

Let us assume that through characterization, it has been determined that this example DAC has excellent superposition. In other words, the step sizes of each DAC are independent of the setting of the other DAC. Also, the summation circuit has been shown to be highly linear. In a case such as this, we can measure the all-codes output curve of the coarse DAC while the fine DAC is set to 0 (i.e., D5-DO = 000000). We store these values into an array VDAc-coARSE;{n), where n takes on the values 0 to 63, corresponding to data bits DI1-D6. Then we can measure the all-codes output curve for the fine DAC while the,coarse DAC is set to 0 (i.e., D11-D6 = 000000). These voltages are stored in the array VDAc-FINE;{n), where n corresponds to data bits D5-DO. Although we have only measureda total of 128 levels, superposition allows us to recreatethe ful14096-point DAC output curve by a simple summation. Each DAC output value VDAc(Z) is equal to the contribution of the coarse DAC plus the contribution of the fine DAC

VDAC

.. (z)=VD~C-FINE AND (z

i AND 111111000000 000000111111)+ VDAC-COARSE 64

(

)

(11.14)

where i ranges from 0 to 4095. Thus a full 4096-point DAC curve can be mathematically reconstructed from only 128 measurementsby evaluating this equation at each value of i from 0 to 4095. Of course, this technique is totally dependent on the architecture of the DAC. It would be inappropriate to use this technique on a nonsegmentedDAC or a segmentedDAC with large superposition errors. A more advanced selected-codes technique was developed at the National Institute of Standardsand Technology (NIST). This technique is useful for all types of DACs and ADCs. It does not make any assumptions about superposition errors or converter architecture. Instead, it uses linear algebra and data collected from production lots to create an empirical model of the DAC or ADC. The empirical model only requires a few selected codes to recreate the entire DAC or ADC transfer curve. Although the details of this technique are beyond the scope of this book, the original NIST paper is listed in the references at the end of this chapter! Another similar technique uses wavelet transforms to predict the overall performance of converters based on a limited number ofmeasurements.3 Again, this topic is beyond the scopeof this book. Before we end this section we would like to point out that an appendix to this chapter lists several MATLAB routines to enable the reader to automatically characterize the DAC's transfer curve according to the methods described in this section.

11.4

DYNAMIC DAC TESTS

11.4.1 Conversion Time (Settling Time) So far we have discussed only low-frequency DAC performance. The DAC DC tests and transfer curve tests measure the DAC's static characteristics, requiring the DAC to stabilize to a stable voltage or current level before each output level measurementis performed. If the DAC's output stabilizes in a few microseconds, then we might step through each output state at a high frequency, but we are still performing static measurementsfor all intents and purposes.

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.

DAC Testing

425

A DAC's perfonnance is also detennined by its dynamic characteristics. One of the most common dynamic tests is settling time, commonly refelTed to as conversion time. Conversion time is defined as the amount of time it takes for a DAC to stabilize to its final static level within a specified error band after a DAC code has been applied. For instance, a DAC's settling time may be defined as 1 IlS to :i:1/2 LSB. This means that the DAC output must stabilize to its final value plus or minus a 1/2 LSB elTor band no more than 1 IlS after the DAC code has been applied. This test definition has one ambiguity. Which DAC codes do we choose to produce the initial and final output levels? The answer is that the DAC must settle from any output level to any other level within the specified time. Of course, to test every possibility, we might have to measuremillions of transitions on a typical DAC. As with any other test, we have to detennine what codes represent the worst-case transitions. Typically settling time will be measured as the DAC transitions from minus full-scale (VFs-) to plus full-scale (VFs+)and vice versa, since these two tests representthe largest voltage swing. The 1/2 LSB example uses an elTor band specification that is referenced to the LSB size. Other commonly used definitions require the DAC output to settle within a certain percentageof the full-scale range, a percentageof the final voltage, or a fixed voltage range. So we might see any of the following specifications: settling time = 1 ~s to :i: 1% of full-scale range

= 1 IlS to:i: 1% of final value settling time = IllS to:i:I mV
settling time The test technique for all these elTor-banddefinitions is the same;we just have to convert the error-band limits to absolute voltage limits before calculating the settling time. The straightforward approach to testing settling time is to digitize the DAC's output as it transitions

Final voltage --- -- ! -

: ,

Errorband
-

i

-

Final voltage --' --': -

j

:: , ,
--

Errorband
+
_.

, - -1 , :
I

1f

, 50%point--- ,--1 -i,
DAC:
output ,: I ,

:
,

If

t

DAC:
output:

,
I
, ,

, -..1
, ,
t
, I

D
write

~ ~r-r--c:
strobe

, ,
I
: ,

:
I

,

+-

DAC
settling time

!! t

I

~

I...:- settling time DAC
(a) referenced to a digital signal; (b) referenced to the DAC

Figure 11.10. DAC settling time measurement output 50% point.

426

An Introductionto Mixed-Signal TestandMeasurement IC

from one code to another and then use the known time period between digitizer samples to calculate the settling time. We measure the final settled voltage, calculate the settled voltage limits (i.e., %1/2 LSB), and then calculate the time between the digital signal transition that initiates a DAC code change and the point at which the DAC first stays within the error band limits, as shown in Figure 11.10(a). In extremely high frequency DACs it is common to define the settling time not from the DAC code change signal's transition but from the time the DAC passesthe 50% point to the time it settles to the specified limits as shown in Figure 11.1O(b). This is easier to calculate, since it only requires us to look at the DAC output, not at the DAC output relative to the digital code.

11.4.2 Overshoot and Undershoot Overshoot and undershoot can also be calculated from the samples collected during the DAC settling time test. These are defined as a percentage of the voltage swing or as an absolute voltage. Figure 11.11 shows a DAC output with 10% overshoot and 2% undershoot on a VFS-to VFS+ transition. 10% overshoot VFS+
~-~~~~~~~~~~ -~

2% undershoot
~---

100% reference ndershoot

VFS-

---

10% overshoot

Figure 11.11. DAC overshoot and undershoot measurements.

11.4.3 Rise Time and Fall Time Rise and fall time can also be measured from the digitized waveform collected during a settling time test. Rise and fall times are typically defined as the time between two markers, one of which is 10% of the way between the initial value and the final value and the other of which is 90% of the way between these values as depicted in Figure 11.12. Other common marker definitions are 20% to 80% and 30% to 70%.

11.4.4 DAC-to-DAC Skew Some types of DACs are designed for use in matched groups. For example, a color palette RAM DAC is a device that is used to produce colors on video monitors. A RAM DAC uses a random accessmemory (RAM) lookup table to turn a single color value into a set of three DAC output values, representing the red, green, and blue intensity of each pixel. These DAC outputs must change almost simultaneously to produce a clean change from one pixel color to the next. The degree of timing mismatch between the three DAC outputs is called DAC-to-DAC skew. It is measured by digitizing each DAC output and comparing the timing of the 50% point of each~

d..-,

Chapter11

.

DAC Testing

427

II

::
II " I

-+114- Falltime
II II II

II

ffJ!I_~~Y~~~~~~

90% t:
I

--

~t

:
I

90%
~~-~~_~_~_~I~~'iJ_:

100%:

reference I

:: 10%
~

II

::
II

i

::

i
::t

10%
:: :--

Initialvoltage --.J L ~~t::
r.:--

R.

Ise Ime

t.

i
I

Final voltage

Figure

11.12.

DAC

rise and fall time

measurements.

Red DAC Green DAC Blue DAC

... -t

/
50% point ---

~
-.:

I

!!+- Green to blue skew
I I

:04- Red to green skew
.

-.; :..- Blue to red skew
skew measurements.

I

I

..

Figure 11.13. DAC-to-DAC

output to the 50% point of the other outputs. There are three skew values (R-G, G-B, and B-R), as illustrated in Figure 11.13. Skew is typically specified as an absolute time value, rather than a signed value.
~

11.4.5 Glitch Energy (Glitch Impulse) Glitch energy, or glitch impulse, is another specification common to high-frequency DACs. It is defined as the total area under the voltage-time curve of the glitches in a DAC's output as it switches across the largest major transition (i.e., 01111111 to 10000000 in an 8-bit DAC) and back again. As shown in Figure 11.14, the glitch area is defmed as the area that falls outside the

428

An Introduction to Mixed-Signal IC Test and Measurement

11'111111
~

Error

Rising

band

glitch

=~========~============== --1r ==- - -=== Negative glitch

energy

edge

-=======================

Major carrier transition 1-LSB swing

osltlve g It Ch
.. I .

~~-~~i;~~~~=

~ .

rated error band. These glitches are caused by a combination of capacitive/inductive ringing in the DAC output and skew between the timing of the digital bits feeding the binary-weighted DAC circuits. The parameter is commonly expressed in picosecond-volts (ps- V) or equivalently, picovolt-seconds (PV-s). (These are not actually units of energy, despite the term glitch energy.) The area under the negative glitches is considered positive area, and should be added to the area under the positive glitches. Both the rising-edge glitch energy and the falling-edge glitch energy should be tested.

P

.

11.4.6

Clock

and

Data

Clock and data feedthrough is another common dynamic DAC specification. It measures the crosstalk from the various clocks and data lines in a mixed-signal circuit that couple into a DAC
output. There are many ways to define this parameter; so it is difficult to list a specific test technique. However, clock and data feedthrough can be measured using a technique similar

Feedthrough

all the other tests in this section. The output of the DAC is digitized with a high-bandwidth digitizer. Then the various types of digital signal feedthrough are analyzed to make sure they are below the defined test limits. The exact test conditions and definition of clock and data feedthrough should be provided in the data sheet. This measurement may require time-domain analysis, frequency-domain analysis, or both.
""n' c

11.5

DAC

ARCHITECTURES

-

t
basic DAC in

11.5.1

Resistive

Divider

There are many different types of DAC architectures, eachwith its own set of strengths and
weaknesses. In this section, we will look at some basic architectures as examples. This is by no means an exhaustive list of every type of DAC, nor is it meant to present section

architectures

in

any

significant

DACs

detail.

The

purpose

of

this

section

is

to

illustrate

DAC

structures

and

their

probable

strengths

and

Perhaps

the

simplest

DAC

architecture

is

weaknesses.

the

resistive

divider

DAC,

Figure 11.15. This type ofDAC uses a series-connectedstring of resistors to produce a set of~

illustrated

some

to

. voltages evenly spaced between VREFand VREF+. Although the resistive divider architecture may be simple to understand.Glitch energy=0. DAC Testing 429 11. . . . .13)+0.. The large silicon area consumed by a high-resolution resistive divider DAC may make this architecture impractical for DACs exceeding seven or eight bits of resolution.5)(-0. . since the value of each resistor in the divider chain can be fabricated with reasonably good .5(0.8 2 x 10-6 The data sheet states that the settling time is 1 J:ls(error band = :I: 20 mY). overshoot=30%. sec .85 J:lS. a l2-bit resistive divider DAC would require 4095 resistors and 4096 switches. ADS. Since the voltage levels produced by a string of resistors in a voltage divider network are always monotonic. o.. This is becauseanyone of the resistors or analog switches can be defective. the resistive divider DAC may be more appealing than other architectures for one reason in particular.01)= 14..6 Chapter11 . selected-codetechniques cannot be used to save test time on resistive divider DACs. For this reason. . .. b I' 0 . The digital input of the DAC determines which of these voltages is connected through an analog switch to a buffer amplifier.. the test time for traditional DAC transfer curve tests may also become unacceptably lengthy.25 ns-V (triangle appoximation). The resistive divider DAC is inherently monotonic and is usually very linear. In addition to the excessive silicon area required to implement a high-resolution resistive divider DAC.(Yes). Ime.3)(0. determine the overshoot of this signal and its rise time. it quickly loses its appeal in highresolution DACs. For low-resolution converters. . T.""'. the resistive divider DAC is monotonic by design. Also.6)(0. transmission parameters such as gain and distortion are not sufficient in themselves to guarantee all the switches and resistors. . . . This is becausethese tests typically do not exercise each of the possible DAC output levels. Also. . .. .. .Exercises 0. Estimate the total glitch energy during the positive-going transition. Does this DAC settle fast enough to meet the settling time specification? Also. ."'. .9. . . .033)+0.5(0. For example. Each additional bit of DAC resolution requires twice as many resistors and analog switches.5(0. Actual settling time = 0. so each and every DAC voltage level must be tested explicitly.. . 1. The step responseof a DAC obtained from an oscilloscope is as follows ~ o. .3 J:lS. rise time=0.'.

.16. Constant step size leads to good DNL characteristics. . Therefore. 11.15.2 Binary-Weighted DACs If the resolution of a DAC exceeds six or seven bits. this type of architecture might be implemented with capacitjve divider networks rather than resistive dividers. Although DNL and monotonicity are low failure modes by design. In fact. tolerance. a binary-weighted DAC often provides a more efficient use of silicon area than the resistive divider architecture. the resistive divider architecture does not necessarily reduce test time. all codes must still be measured to detect defects in any of the resistors or switches.430 AnIntroduction Mixed-Signal Tifst Measurement to IC and Resistive divider chain ~ VREF+ OAC Switch OO 01 SO S1 S2 S3 OAC oupu t t . though it does typically lead to very high yields.16. S3 Resistive divider DAC architecture. . many of the DAC architectures discussedin this section can be implemented with either resistors or capacitors. the size of each DAC step is substantially equal to the other steps. One common binaryweighted architecture is shown in Figure 11. R VREF 2R OAC output Figure 11. SO controlled by OAC code bit DO S1 controlled by OAC code bit 01 etc. This circuit is known as an R/2R resistive ladder DAC.5. As a side note. A 4-bit R/2R resistive ladder DAC. with the understanding that the capacitive versions sharemany of the same general testing characteristics. We will discuss only the resistive version of each converter type. t Inpu d co e control decoder logic VREFFigure 11.

2x/. 9-bit currentsteeringDAC only requiresone more current a sourceand switch than an 8-bit currentsteeringDAC. Binary-weighted architectures providetwo main advantages. I. The least significant bit (LSB) controls the smallest current source. enabling or disabling the 2x/ current value. The current can be converted to voltage using a load resistor. The current-steeringDAC produces a current output rather than a voltage output. Also. PWM DACs adjust their output voltages using a high-frequency pulse train of varying duty cycle.17.6..5. enabling or disabling its output so that it contributes either zero current or current equal to I. -4:.3 PWM DACs Pulse-width modulation (PWM) DACs are very simple DACs that are mostly digital in nature. Another binary-weighted architecture is the current-steering DAC shown in Figure 11. they areefficient in their useof silicon area. Current-steering DAC. First.18 shows a block diagram for a simple PWM DAC. 4x/. LSB Figure 11. Figure 11. as shown. The second to least significant bit controls the next largest current source.3. using very little analog circuitry. The major carrier methodreducesINL and DNL test time. DAC Testing 431 80 controlled by OAC code bit 00 81 controlled by OAC code bit 01 etc. a binary-weighted architecture allows major carrier testing. compared the brute force all-codestesting to method. For example. ..Chapter11 . 8x/.MSB . etc. For instance. Binary-weighted DACs are based on a summation of binary-weighted currents or voltages. the currents in the current switching DAC are set to binary-weighted values. as describedin Section 11.17.assuming summationof the the individual binary-weightedcurrentsor voltagesadd without superposition error.. . 11. The minimum current is equal to 0 and the maximum current is equal to (2N-I)x/ where N is the number of bits in the DAC's input code. The duty cycle controls the amount of time the I-bit DAC spends at the VFS+ level and how much time it spendsat the VFs-level. and so on.

depending on the exact implementation. For this reason.J u-lJ--1I-U-V Voltage near VFS+ ~1_rLJ-~~_-. low-resolution applications where extreme quality is not a concern. These may not be guaranteed to produce monotonic curves. expensive all-codes testing is usually not an option in testing PWM DACs. an analog pulse width generator must be used. INL. such as signal-to-distortion ratio (SID) tests and signal-tonoise ratio (SNR) tests using a small number of samples. assuminga purely digital circuit is to be used.. This requires a very high-frequency clock to drive the duty cycle generator circuits. Depending on the nature of the design architecture. Pulsewidth modulation (PWM)DAC. the filtered output of the one-bit DAC settles to a voltage midway between VFSand VFS+. This shortcut works for DACs in which the INL curve may be bowed or curved. the all-codes INL and DNL testing is replaced by more cost effective channel testing. output = VFSFigure 11. but does not exhibit suddencode-tocode discontinuities.. output = VFS+ Input = 0. Other PWM architectures use analog circuits to generate the varying pulse widths. as long as the digital logic functions correctly. To obtain a high-resolution DAC. is a potential weakness of all PWM DACs. the DNL and monotonicity of some PWM DACs are guaranteed by design. while a duty cycle of 0% high results in a voltage equal to VFS-.n_Jl-IL '~ "' Midscale voltage Voltage near VFs'~ J Input code Master clock I Duty cycle logic DAC output Input = 1. Example applications of PWM DACs include toy speechproducts and talking greeting cards. PWM DACs are similar in nature to resistive divider DACs. PWM DACs can sometimes be tested by sampling a few evenly spacedpoints on the DAC transfer curve to verify good INL characteristics. The pulse duty cycle circuits can then be verified using time measurement techniquesand/or purely digital patterns to verify monotonicity and DNL.432 An Introduction to Mixed-Signal Testa~dMeasurement IC Pulses at modulation frequency Code near +FS Midscale code Code near -FS '. In many PWM DAC architectures. on the other hand. Often. Otherwise. Since extreme low cost is often a concern.18. a PWM DAC must be able to adjust the pulse edges by tiny amounts of time. "'" .. the duty cycle is produced by purely digital circuits driven by a high-frequency master clock.. If the duty cycle approaches50/50. which is much more likely to exhibit variations from DUT to DUT. PWM DACs are typically used in low-cost.The DAC output is therefore proportional to the duty cycle of the digital input to the one-bit DAC.A duty cycle of 100% high results in a voltage equal to VFS+.

A common solution to this modulation ratio problem is provided by the sigma-delta DAC architecture.e. . . . Other texts have explained this architecture in detail. Second-order sigma-delta (pulsedensitymodulation) DAC block diagram. Therefore.20. . The operation of a sigmadelta DAC is another subject that falls outside the scope of this book. for example. Very high-resolution DACs require very high-frequency master clocks to drive the digital counters controlling the width of the digital pulses (i. present technology does not support such a design. or 131 GHz! Clearly. : I : . . . output = VFS+ Input = 0. . :+ . .4.. Since the pulses must be low-pass filtered to generate an analog output. shown in Figure 11. a factor of 100) than the highest frequency in the reconstructed analog signal. output= FS- Figure 11. Input= 0. . I I j : Input: I samples: . I I . output = 1 Input <= 0. I : .Chapter11 11. requires a pulse time resolution of 1/65536thof the period of the pulse waveform. . . Y : : I . . : : I I . the sigma-delta architecture allows a much smaller ratio of master clock to audio bandwidth. we can make some observations about the typical applications and test approaches for sigma-delta DACs without getting into their detailed operation.5 million to one for a 16-bit PWM architecture. . I . A 16-bit PWM DAC. Because the noise-shaping algorithm uses a process called pulse density modulation (PDM). A modulation ratio of only 100 to one (clock rate divided by audio bandwidth) allows 16-bit performance from a sigma-delta architecture. The noise-shaping algorithm reduces noise components in the low-frequency spectrum of the reconstructed signal as depicted in Figure 11. . . . output = FS+ : .4 Sigma-Delta DACs .19. . . DAC Testing 433 One thing in particular limits the resolution of PWM DACs that use purely digital circuits to control pulse widths. I .19.s Fortunately. sigma-delta converters are also known as PDM converters. . output = VFSDAC tput . The noise-shapedsignal can be cleaned up using a low-pass filter to separatethe high-frequency quantization noise from the low-frequency signal. the pulse frequency must be substantially higher (say.5. a 16-bit PWM DAC for audio applications having a 20-kHz bandwidth would require a master clock frequency of 65536x100x20000. . . . Input> 0. duty cycle). Input = 1. Although the digital logic is more complicated than that of a simple PWM DAC. : . I I . output = o Input = 1. compared to a ratio of 6. . The sigma-delta DAC accomplishes this reduction in master clock frequency using a noiseshaping algorithm that moves the quantization noise of the one-bit DAC to high frequencies. . Digital computation circuitry ~ .

Unfiltered sigma-delta DACoutputspectrum.--~0 --:. AC signal creation. with an emphasis on testing these parameters at various signal levels to detect flaws in the inherently nonlinear companding circuits. 0 ~--: 0 0 0 Hz :::.3. ~:::: . They are more commonly used in applications such as low-cost voice compression and decompressionfor use in telephone central offices.434 An Introductionto Mixed-SignalIC T~t andMeasurement ': Sine wave 0 . -60 . The test engineer should consult the design and systems engineersto determine whether or not self-tones should be measuredin a particular application. ~ 0 . These DC levels and the corresponding self-tone frequencies are very predictable. Audio applications such as digital audio and cellular telephony are well suited to sigma-delta technology. Fortunately. . such as the codec discussed in Section 9. For this reason.However. INL and DNL are virtually meaningless in the case of companded DACs and ADCs. ICN.0 0 0 Shaped noise " .-. S/THD. T--0 0 0 -10 ~- : 0 0 - ~ 0 0 ~---.--~-. highquality. In fact. Therefore. Sigma-delta DACs are well suitedfor applications requiringrelatively low-frequency. etc. .. 0 0 o-0 0 .--. since they are controlled by the DAC's sigma-delta algorithm. in as long as these DC levels can be avoided. sigma-delta DACs are somewhat poorly suited to most DC applications becausethey generateinterference signals called self-tones. .20. JI' ~ . The usual test list for companded DACs includes mostly AC sampled channel tests such as SNR. :_:-- Output -20 ~level -30 (dB) -40 -50 ~ 0 1 ~ .-70 -80 0 . ~ . -f. 0 ~ 0 ~ 0 ~ 0 ~ . AC signals. sigma-delta DACs are generally tested for AC parameterssuch as S/THD and SNR rather than the DC transfer curve tests like INL and DNL. since a majority of them occur outside the filter's passband.it is oftenunnecessary measure to DAC self-tones AC applications. Self-tones are low amplitude periodic waves that are generatedby the sigma-delta noise-shaping algorithm itself when certain DC signal levels are applied to the DAC input.--. ~ 0 :--: .5 Companded DACs Companded DACs. are seldom used in DC applications.~ ---0 0 . Most input codes will produce self-tones in the unfiltered DAC output.2. the low-pass reconstruction filter eliminates most self-tones. by contrast. 11. change the DAC input codesoften enough that self-tones do not have a chanceto appear.5. Only certain DC levels produce self-tones that are in the pass band of the low-pass filter.'0'" 0 .:::::::::~:::::::::~:::::::::~::::::::~:::::::::~:::::::::~::::::::::::: Frequency Nyquist frequency (1/2 modulation frequency) Figure 11. DAC self-tones are fairly easy to measure. ~ 0 0 0 ~--.-. 0 ~ ~ 0 .--_: : ---~ ~ ' ~ . ~ 0 ~ . . ~ 0 ~ .

but are instead hybrids of two or more of the basic architectures. ( 11. so even this parameter is frequently guaranteedby design rather than being tested in production.6. and output drive capabilities (output impedance). This gives lower quantization noise and therefore better performance. The multibit DAC may be implemented using a PWM DAC rather than a resistive divider DAC. l ~ ~. The settling time of typical DACs is often many times faster than that required in DC reference applications.3. leading to another hybrid design.II_:!' Chapter11 . Weaknessesin the system-level application must also be understood as well. rather than the transmission parameters outlined in Chapter 9. the INL and DNL of this DAC would be extremely important. secret effective the to testing any DAC is to understand weaknesses of its and design a suite of tests that specifically targets those weaknesses.6 TESTS FOR COMMON DAC APPLICATIONS 11. then its AC transmission parametersare probably unimportant. . It would probably be unnecessaryto measure the I-kHz signal to total harmonic distortion ratio of a DAC whose purpose is to set the level of a cellular telephone's transmitted signal. taking its intended application into consideration. For example. Many DACs are used as simple DC references.5. The test engineer. with the exception of settling time. As the cellular telephone user moves closer or farther away from a cellular base station (the radio antenna tower). However. full-scale range. These may be of importance if the DC level must exhibit low noise. as long as the multibit DAC is very linear. monotonicity. the test list for a given DAC often depends on its intended functionality in the system-level application. An example of this type of DAC usage is the power level control in a cellular telephone.6 Hybrid DAC Architectures Many DACs do not fall into any of the categories listed in this chapter. hybrid designs requires unique testing methodologies. Regardless of the DAC Each of these I~ c architecture. Dynamic tests are not typically performed on DC reference DACs. The transmitted level may be adjusted using a transmit level DAC so that the signal is just strong enough to be received by the base station without draining the cellular telephone's battery unnecessarily. pAC Testing 435 11. DACs used as DC referencesare usually measuredusing the intrinsic parameterslisted in this chapter. Notable exceptions are signal-to-noise ratio and idle channel noise (ICN). For example. If a DAC is only used as a DC (or slow-moving) voltage or current reference. and therefore we might need to measurethe DAC's noise level.7. systems engineer. the cellular telephone's transmitted signal might be corrupted by noise on the output of the transmit level control DAC.1 DC References As previously mentioned. Yet another hybrid DAC example is the segmented DAC example of Section 11. It combines the characteristics of two resistive divider DACs into a single DAC characteristic. a sigma-delta DAC can be built using a resistive divider multibit DAC instead of a simple one-bit DAC. and design engineer should work together closely to define the most efficient test approach for each DAC. ': . as would its absolute errors. the transmitted signal level from the cellular telephone must be adjusted.

DACs can be used to control the intensity and color of pixels in video cathode ray tube (CRT) displays. RGB DACs are typically used in computer monitors. Each DAC controls the intensity of an electron beam.2 Audio Reconstruction Audio reconstruction DACs are those used to reproduce digitized sound. An RGB (red-green-blue) output is controlled by three separate DACs. since their purpose is to reproduce arbitrary audio signals with minimum noise and distortion. which in turn controls the intensity of one of the three primary colors of each pixel as the beam is swept across the CRT. In this application. or other government or industry organization. Dynamic tests such as settling time mayor may not be necessary for data modulation applications. will usually manifest themselves as failures in transmission parameterssuch as signal-to-noise. . The cellular telephone again provides an example of this type of DAC application.. 11. Linearity tests can help track down any transmission parameter failures causedby the DAC. signal-to-distortion. the type of testing required for video DACs depends on the nature of their output. It is often possible to eliminate the intrinsic parametertests once the device is in production. Parameterssuch as these are very application-specific. There are two basic types of video DAC application. ATE vendors are often a good source of expertise and assistancein developing these application-specific tests.3 Data Modulation Data modulation is another purpose to which DACs are often applied. INL and DNL) of audio reconstruction DACs are typically measured only during device characterization. Examples include the voice-band DAC in a cellular telephone and the audio DAC in a PC sound card. keeping only the transmission tests.4 Video Signal Generators As discussed earlier. Data modulation DACs also have very specific parameters such as error vector magnitude (EVM) or phase trajectory error (PTE).6. Any failures in settling time. Dynamic tests are not typically specified or performed on audio DACs. 11. etc. glitch energy. Like the audio reconstruction DACs. The intrinsic parameters (i.6. However. Again. They are usually defined in standards documents published by the IEEE.2). the intrinsic tests are often removed after the transmission parametershave been verified. The IF section of a cellular telephone base-band modulator converts digital data into an analog signal suitable for transmission. However.e. these DACs are typically tested using sine wave or multitone transmission parameter tests. NIST. These DACs are more likely to be tested using the transmission parametersof Chapter 9.436 An Introductionto Mixed-Signal Testand Measurement IC 11. The data sheet should provide references to documents defining application-specific tests such as these.1. similar to those used in modems (see Section 9. The test engineer is responsible for translating the measurementrequirements into ATE-compatible tests that can be performed on a production tester. RGB and NTSC.6. each DAC's output voltage or current directly control the intensity of the beam. and idle channel noise. the intrinsic tests like INL and DNL may be added to a characterization test program to help debug the design.

fall time. The quality of the NTSC video DAC. amplitude. ADC testing is very closely related to DAC testing. We have to select DAC test requirements carefully to guaranteethe necessary quality of the DAC without wasting time with irrelevant or ineffective tests. RGB DACs are tested using the standard intrinsic tests like INL and DNL. and blue electron beams as they sweep across the computer monitor.. rise time.3).. rather than a separateDAC for each color. DAC Testing 437 The NTSC fonnat is used in transmission of standard (i. and dynamic parameters.1. undershoot. Although DACs all perfonn the same basic function (digital-to-analog conversion)..5. signal-to-noise. Clearly this is a totally different DAC application than the RGB DAC application.7 SUMMARY DAC testing is far less straightforward than one might at first assume. INL. "ADC Testing. as well as the many types of ADC architectures and applications the test engineer will likely encounter. while changing its offset. Chapter11 .e.II. and differential phase (see Section 10. differential gain. The picture intensity. and phase of a 3.6. gain. I APPENDIX A.54-MHz sinusoidal wavefonn produced by the DAC. These parameters are important becausethe DAC outputs directly control the rapidly changing beam intensities of the red. .54-MHz sine wave. Many of the DC and intrinsic tests defined in this chapter are very similar to those perfonned on ADCs. and saturation infonnation is contained in the time-varying offset. Any settling time. the architecture of the DAC and its intended application detennine its testing requirements and methodologies. by contrast. This type of DAC is tested with transmission parameters like gain. Chapter 12. and DNL from a given set of samples. vertical lines." explains the various ways the ADC transfer curve can be measured.I MATLAB Routines for DAC Characterization This appendix lists two MATLAB routines that can