®

ISL6261
Data Sheet September 27, 2006 FN9251.1

Single-Phase Core Regulator for IMVP-6® Mobile CPUs
The ISL6261 is a single-phase buck regulator implementing lntel® IMVP-6® protocol, with embedded gate drivers. The heart of the ISL6261 is the patented R3 Technology™, Intersil’s Robust Ripple Regulator modulator. Compared with the traditional multi-phase buck regulator, the R3 Technology™ has faster transient response. This is due to the R3 modulator commanding variable switching frequency during a load transient. lntel® Mobile Voltage Positioning (IMVP) is a smart voltage regulation technology effectively reducing power dissipation in lntel® Pentium processors. To boost battery life, the ISL6261 supports DPRSLRVR (deeper sleep) function and maximizes the efficiency via automatically changing operation modes. At heavy load in the active mode, the regulator commands the continuous conduction mode (CCM) operation. When the CPU enters deeper sleep mode, the ISL6261 enables diode emulation to maximize the efficiency at light load. Asserting the FDE pin of the ISL6261 in deeper sleep mode will further decrease the switching frequency at light load and increase the regulator efficiency. A 7-bit digital-to-analog converter (DAC) allows dynamic adjustment of the core output voltage from 0.300V to 1.500V. The ISL6261 has 0.5% system voltage accuracy over temperature. A unity-gain differential amplifier provides remote voltage sensing at the CPU die. This allows the voltage on the CPU die to be accurately measured and regulated per lntel® IMVP-6 specification. Current sensing can be implemented through either lossless inductor DCR sensing or precise resistor sensing. If DCR sensing is used, an NTC thermistor network will thermally compensates the gain and the time constant variations caused by the inductor DCR change.

Features
• Precision single-phase CORE voltage regulator - 0.5% system accuracy over temperature - Enhanced load line accuracy • Internal gate driver with 2A driving capability • Microprocessor voltage identification input - 7-Bit VID input - 0.300V to 1.500V in 12.5mV steps - Support VID change on-the-fly • Multiple current sensing schemes supported - Lossless inductor DCR current sensing - Precision resistive current sensing • Thermal monitor • User programmable switching frequency • Differential remote voltage sensing at CPU die • Overvoltage, undervoltage, and overcurrent protection • Pb-free plus anneal available (RoHS compliant)

Ordering Information
PART NUMBER (NOTE) ISL6261CRZ ISL6261CRZ-T ISL6261CR7Z PART MARKING ISL6261CRZ ISL6261CRZ TEMP RANGE (°C) PACKAGE PKG. (Pb-FREE) DWG. # L40.6x6

-10 to +100 40 Ld 6x6 QFN

-10 to +100 40 Ld 6x6 L40.6x6 QFN, T&R L48.7x7

ISL6261CR7Z -10 to +100 48 Ld 7x7 QFN

ISL6261CR7Z-T ISL6261CR7Z -10 to +100 48 Ld 7x7 L48.7x7 QFN, T&R ISL6261IRZ ISL6261IRZ-T ISL6261IR7Z ISL6261IR7Z-T ISL6261IRZ ISL6261IRZ ISL6261IR7Z ISL6261IR7Z -40 to +100 40 Ld 6x6 QFN L40.6x6

-40 to +100 40 Ld 6x6 L40.6x6 QFN, T&R -40 to +100 48 Ld 7x7 QFN L48.7x7

-40 to +100 48 Ld 7x7 L48.7x7 QFN, T&R

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.

ISL6261 Pinouts
ISL6261 (40 LD QFN)
DPRSLPVR DPRSTP# CLK_EN PGOOD

VR_ON

VID6

VID5

VID4 32

40 FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB 1 2 3 4 5 6 7 8 9 10 11 VDIFF

39

38

37

36

35

34

33

31 30 VID2 29 VID1 28 VID0 27 VCCP

VID3 26 LGATE 25 VSSP 24 PHASE 23 UGATE 22 BOOT 21 NC 20 VDD VID1 38 37 36 NC 35 NC 34 NC 33 NC 32 NC VID0 31 VCCP 30 LGATE 29 VSSP 28 PHASE 27 UGATE 26 BOOT 25 NC 24 NC 23 NC

3V3

GND PAD (BOTTOM)

12 VSEN

13 RTN

14 DROOP

15 DFB

16 VO

17 VSUM

18 VIN VID3 40 21 VSS

19 VSS 39 22 VDD VID2

ISL6261 (48 LD QFN)
DPRSLPVR DPRSTP# CLK_EN# VR_ON

VID6

VID5 42 19 VSUM

48 PGOOD FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW 1 2 3 4 5 6 7 8 9

47

46

45

44

43

41

GND PAD (BOTTOM)

COMP 10 FB 11 NC 12 13 VDIFF 14 VSEN 15 RTN 16 DROOP 17 DFB 18 VO 20 VIN

2

VID4

3V3

FN9251.1 September 27, 2006

ISL6261
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns) Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ) UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT . . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V HBM ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV

Thermal Information
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 6x6 QFN Package (Notes 1, 2) . . . . . . 33 5.5 7x7 QFN Package (Notes 1, 2) . . . . . . 30 5.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5% Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications
PARAMETER INPUT POWER SUPPLY +5V Supply Current

VDD = 5V, TA = -10°C to +100°C, Unless Otherwise Specified. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

IVDD

VR_ON = 3.3V VR_ON = 0V

3.85

3.1 4.35 4.1

3.6 1 1 1 4.5 -

mA µA µA µA V V

+3.3V Supply Current Battery Supply Current at VIN pin POR (Power-On Reset) Threshold

I3V3 IVIN PORr PORf

No load on CLK_EN# pin VR_ON = 0, VIN = 25V VDD Rising VDD Falling

SYSTEM AND REFERENCES System Accuracy %Error (Vcc_core) No load, close loop, active mode, TA = 0°C to +100°C, VID = 0.75-1.5V VID = 0.5-0.7375V VID = 0.3-0.4875V RBIAS Voltage Boot Voltage Maximum Output Voltage Minimum Output Voltage VID Off State CHANNEL FREQUENCY Nominal Channel Frequency Adjustment Range AMPLIFIERS Droop Amplifier Offset Error Amp DC Gain (Note 3) AV0 -0.3 90 0.3 mV dB fSW RFSET = 7kΩ, Vcomp = 2V 200 333 500 kHz kHz RRBIAS VBOOT VCC_CORE (max) VCC_CORE (min) VID = [0000000] VID = [1100000] VID = [1111111] RRBIAS = 147kΩ -0.5 0.5 %

-8 -15 1.45 1.188 -

1.47 1.2 1.5 0.3 0.0

8 15 1.49 1.212 -

mV mV V V V V V

3

FN9251.1 September 27, 2006

ISL6261 Electrical Specifications PARAMETER Error Amp Gain-Bandwidth Product (Note 3) Error Amp Slew Rate (Note 3) FB Input Current SOFT-START CURRENT Soft-start Current Soft Geyserville Current Soft Deeper Sleep Entry Current Soft Deeper Sleep Exit Current Soft Deeper Sleep Exit Current ISS IGV IC4 IC4EA IC4EB |SOFT .3V) VIH(3. Unless Otherwise Specified.4 1 8.5 1.3V) 2.5V 500mA Sink Current VUGATE_PHASE = 2.1 1.3 1 V V UVf VOL IOH tpgd OVH OVHS IPGOOD = 4mA PGOOD = 3.1 September 27. TA = -10°C to +100°C.5 -240 V µA ms mV V µA mV mV VDDP = 5V. (Continued) SYMBOL GBW SR IIN(FB) CL = 20pF CL = 20pF TEST CONDITIONS MIN TYP 18 5.11 6.58 0.5V 500mA Sink Current VLGATE = 2.8 200 1.5 4 1.5µs I(Rbias) = 10µA DROOP rising above OCSET >120µs VO below set point for >1ms -1 5.8 -3.0 10 MAX 150 UNITS MHz V/µs nA GATE DRIVER DRIVING CAPABILITY (Note 4) UGATE Source Resistance UGATE Source Current UGATE Sink Resistance UGATE Sink Current LGATE Source Resistance LGATE Source Current LGATE Sink Resistance LGATE Sink Current UGATE to PHASE Resistance RSRC(UGATE) ISRC(UGATE) RSNK(UGATE) ISNK(UGATE) RSRC(LGATE) ISRC(LGATE) RSNK(LGATE) ISNK(LGATE) RP(UGATE) 500mA Source Current VUGATE_PHASE = 2. Output Unloaded 20 7 30 15 44 30 ns ns 4 FN9251.5V 500mA Source Current VLGATE = 2.5 1.5 -360 -300 0.1 240 1.3V CLK_EN# Low to PGOOD High VO rising above setpoint >1ms VO rising above setpoint >0. Output Unloaded PVCC = 5V.5 0. DPRSLPVR and PGD_IN Input Low VR_ON.2 3.725 10.REF|>100mV DPRSLPVR = 3.9 Ω A Ω A Ω A Ω A kΩ GATE DRIVER SWITCHING TIMING (Refer to Timing Diagram) UGATE Turn-on Propagation Delay LGATE Turn-on Propagation Delay BOOTSTRAP DIODE Forward Voltage Leakage POWER GOOD and PROTECTION MONITOR PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay Overvoltage Threshold Severe Overvoltage Threshold OCSET Reference Current OC Threshold Offset Undervoltage Threshold (VDIFF-SOFT) LOGIC THRESHOLDS VR_ON. 2006 .43 0.7 10 0.67 1 V μA tPDHU tPDHL PVCC = 5V.675 9.5V 1 2 1 2 1 2 0. Forward Bias Current = 2mA VR = 16V 0.3V DPRSLPVR = 3. DPRSLPVR and PGD_IN Input High VIL(3.5 160 1.3V DPRSLPVR = 0V -46 ±175 -46 36 175 -41 ±200 -41 41 200 -36 ±225 -36 46 225 µA µA µA µA µA VDD = 5V.

PSI# and DPRSTP# Input High Leakage Current of DAC(VID0VID6) and DPRSTP# THERMAL MONITOR NTC Source Current Over-temperature Threshold VR_TT# Low Output Resistance CLK_EN# OUTPUT LEVELS CLK_EN# High Output Voltage CLK_EN# Low Output Voltage NOTES: 3. (Continued) SYMBOL IIL IIH IIL_DPRSLP IIH_DPRSLP DAC(VID0-VID6).17 60 1.4 V V RTT NTC = 1.3V V(NTC) falling I = 20mA 53 1. Guaranteed by characterization.45 0 0. 2006 .18 0.9 3.45 MAX 1 1 0.25 9 µA V VIL(1.0V) VIH(1.2 5 67 1. TA = -10°C to +100°C. VOH VOL 3V3 = 3.7 -1 TYP 0 0 0 0.3 1 UNITS μA μA μA μA V V μA μA Gate Driver Timing Diagram PWM tPDHU tRU UGATE 1V tFU LGATE 1V tRL tPDHL tFL 5 FN9251.1 0.ISL6261 Electrical Specifications PARAMETER Leakage Current on VR_ON and PGD_IN Leakage Current on DPRSLPVR VDD = 5V.0V) IIL IIH DPRSLPVR logic input is low DPRSLPVR logic input is high TEST CONDITIONS Logic input is low Logic input is high DPRSLPVR logic input is low DPRSLPVR logic input is high MIN -1 -1 0.3V. Guaranteed by design. Unless Otherwise Specified. PSI# and DPRSTP# Input Low DAC(VID0-VID6).1 September 27. 4. I = -4mA ICLK_EN# = 4mA 2.

DROOP The output of the droop amplifier.81K = 300kHz). DFB The inverting input of the droop amplifier. VSEN Remote core voltage sense input. Logic high of FDE with logic low of DPRSTP# forces the ISL6261 to operate in diode emulation mode with an increased VW-COMP voltage window. A resistor from this pin to VO sets DROOP voltage limit for OC trip. 6 FN9251. VO An input to the IC that reports the local output voltage. Over-temperature pull-down resistance is 10. The SOFT pin is the non-inverting input of the error amplifier. SOFT A capacitor from this pin to GND pin sets the maximum slew rate of the output voltage.1 September 27. VW A resistor from this pin to COMP programs the switching frequency (eg. OCSET Overcurrent set input. PGD_IN Digital Input. RTN Remote core voltage sense return. 2006 . VDIFF The output of the differential amplifier. VR_TT# Thermal overload output indicator with open-drain output. Suggest connecting to MCH_PWRGD. RBIAS A 147K resistor to VSS sets internal current reference. A 10µA current source is connected internally to this pin. DROOP-VO voltage is the droop voltage. NTC Thermistor input to VR_TT# circuit and a 60µA current source is connected internally to this pin. which indicates that VCC_MCH voltage is within regulation. FB The inverting input of the error amplifier.ISL6261 Functional Pin Description DPRSLPVR DPRSTP# CLK_EN PGOOD VR_ON VID6 VID5 VID4 32 40 FDE PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB 1 2 3 4 5 6 7 8 9 10 11 VDIFF 39 38 37 36 35 34 33 31 30 VID2 29 VID1 28 VID0 27 VCCP VID3 26 LGATE 25 VSSP 24 PHASE 23 UGATE 22 BOOT 21 NC 20 VDD 3V3 GND PAD (BOTTOM) 12 VSEN 13 RTN 14 DROOP 15 DFB 16 VO 17 VSUM 18 VIN 19 VSS FDE Forced diode emulation enable signal. COMP The output of the error amplifier. 6.

VID0. 3V3 3. Connect to controller local ground. Goes active 20µs after PGD_IN is active and Vcore is within 10% of boot voltage. It is used for input voltage feed forward to improve the input line transient performance. 7 FN9251. VSS Signal ground.1 September 27. 2006 . VR_ON VR enable pin. Needs to be pulled up externally by a 680 resistor to VCCP or 1. VIN Power stage input voltage. VID3. A logic high indicates that the microprocessor is in Deeper Sleep Mode and also indicates a slow Vo slew rate with 41μA discharging or charging the SOFT cap. VID2. UGATE The upper-side MOSFET gate signal. DPRSLPVR Deeper sleep enable signal.3V supply voltage for CLK_EN#. NC Not connected. DPRSTP# Deeper sleep slow wake up signal. This pin should connect to the source of upper MOSFET. An internal bootstrap diode is connected to the VCCP pin.9k to 3. VID1.ISL6261 VSUM This pin is connected to one terminal of the capacitor in the current sensing R-C network. BOOT Upper gate driver supply voltage. CLK_EN# Digital output for system PLL clock. VSSP The return path of the lower gate driver. VCCP 5V power supply for the gate driver. Ground this pin in the practical layout. A logic low signal on this pin indicates that the microprocessor is in Deeper Sleep Mode. A logic high signal on this pin enables the regulator. VDD 5V control power supply. PGOOD Power good open-drain output.3V. VID5. VID4. PHASE The phase node. VID6 VID input with VID0 as the least significant bit (LSB) and VID6 as the most significant bit (MSB). LGATE The lower-side MOSFET gate signal.

2006 .RBIAS VR_ON FDE DPRSLPVR DPRSTP# PGD_IN CLK_EN# PGOOD 3V3 VIN VDD VCCP VID0 VIN 60uA FLT PGOOD VCCP Function Block Diagram 8 DAC FAULT AND PGOOD LOGIC SOFT VO 1.22V 10uA VCCP OC VID1 MODE CONTROL PGOOD MONITOR AND LOGIC VID2 VID3 NTC VR_TT# VID4 VID5 VID6 OCSET BOOT ISL6261 VSUM DROOP DFB OC VIN VSOFT FLT UGATE DROOP 1 E/A MODULATOR DRIVER LOGIC VCCP PHASE FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261 VO LGATE 1 VW VSSP VO VSEN RTN VDIFF SOFT FB COMP VW GND VSS FN9251.1 September 27.

1 September 27.3 R4 C4 R5 R6 NTC 3V3 RBIAS VDD VCCP VIN V+5 Vin C8 UGATE BOOT C5 SOFT VR_TT# VID<0:6> DPRSTP# DPRSLPVR VR_TT# C6 PHASE Lo Vo Co VIDs DPRSTP# DPRSLPVR FDE LGATE VSSP MCH_PWRGD CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE PGD_IN CLK_EN# VR_ON PGOOD VSEN R8 VSUM C9 VO R9 NTC Network R7 C3 R2 C7 C2 RTN ISL6261 VW OCSET COMP FB DFB R10 R11 C10 R12 R3 R1 C1 VDIFF DROOP VSS FIGURE 2.ISL6261 Simplified Application Circuit for DCR Current Sensing V+3. ISL6261-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING 9 FN9251. 2006 .

1 September 27.3 R4 C4 R5 R6 NTC 3V3 RBIAS VDD VCCP VIN V+5 Vin C8 UGATE BOOT C5 SOFT VR_TT# VID<0:6> DPRSTP# DPRSLPVR VR_TT# C6 PHASE Lo R sen Vo Co VIDs DPRSTP# DPRSLPVR FDE LGATE VSSP MCH_PWRGD CLK_ENABLE# VR_ON IMVP6_PWRGD VCC-SENSE VSS-SENSE PGD_IN CLK_EN# VR_ON PGOOD VSEN R8 VSUM C9 VO R7 C3 R2 C7 C2 RTN ISL6261 VW OCSET COMP FB DFB R10 R11 C10 R12 R3 R1 C1 VDIFF DROOP VSS FIGURE 3.ISL6261 Simplified Application Circuit for Resistive Current Sensing V+3. 2006 . ISL6261-BASED IMVP-6® SOLUTION WITH RESISTIVE CURRENT SENSING 10 FN9251.

or through a precise resistor in series with the inductor.5% accuracy over the range of 0. which gives the R3™ regulator a faster response than conventional fixed frequency PWM regulators. and the SOFT cap is charged/discharged by approximate 200µA and VO slews at 10mV/μs to the voltage set by the VID pins. as shown in Figures 2 and 3. The inductor current information is fed to the VSUM pin. the ISL6261 has an error amplifier that allows the controller to maintain 0. Unlike conventional hysteretic converters. The ISL6261 modulator internally synthesizes an analog of the inductor ripple current and uses hysteretic comparators on those signals to establish PWM pulses.5V.2V. When using inductor DCR current sensing. VSEN and RTN pins are the inputs to the differential amplifier. Therefore the load current transient results in increased switching frequency. the SOFT ramp will be 2mV/μs for a soft-start time of 600μs. If the SOFT capacitor is 20nF. During this interval.ISL6261 Theory of Operation The ISL6261 is a single-phase regulator implementing Intel® IMVP-6® protocol and includes an integrated gate driver for reduced system cost and board area. Figure 4 shows typical startup timing. 11 FN9251. 2006 . which is the non-inverting input to the droop amplifier.7V to 1. and DROOP-VO voltage is a high-bandwidth analog representation of the inductor current. the regulator always operates in continuous current mode (CCM). Once VO is within 10% of the boot voltage and PGD_IN is HIGH for six PWM cycles (20µs for 300kHz switching frequency). At startup. Intersil’s Robust Ripple Regulator modulator. PGD_IN Latch It should be noted that PGD_IN going low will cause the converter to latch off. as shown in Figure 3. Toggling VR_ON will clear it.5% voltage regulation accuracy throughout the VID range from 0. regardless of the control signals. A true differential amplifier remotely senses the core voltage to precisely control the voltage at the microprocessor die. Toggling PGD_IN won’t clear the latch. The R3™ modulator combines the best features of fixed frequency and hysteretic PWM controllers while eliminating many of their shortcomings. The heart of the ISL6261 is the patented Technology™. This feature allows the converter to respond to other system voltage outages immediately. as shown in Figure 2. The switching frequency of the ISL6261 controller is set by the resistor RFSET between pins VW and COMP.1 September 27.3V logic HIGH threshold. an NTC thermistor is used to compensate the positive temperature coefficient of the copper winding resistance to maintain the load-line accuracy. the output voltage droops from the VID value proportionally to achieve the IMVP-6® load line. Operating on the large-amplitude and noise-free synthesized signals allows the ISL6261 to achieve lower output ripple and lower phase jitter than either conventional hysteretic or fixed frequency PWM controllers. Start-up Timing With the controller’s VDD pin voltage above the POR threshold.5V. and also as the input to the overcurrent protection circuit. In approximately 100μs. the output voltage will be regulated to the value set by the VID inputs per Table 1.75V to 1. the SOFT cap is charged by a 41μA current source. The ISL6261 can sense the inductor current through the intrinsic series resistance of the inductors. The ISL6261 IMVP-6® solution provides optimum steady state and transient performance for microprocessor core voltage regulation applications up to 25A. PGOOD is asserted HIGH. In approximately 7ms. The hysteretic window voltage is with respect to the error amplifier output. SOFT and VO start ramping to the boot voltage of 1. As the load current increases from zero. which is presented in the lntel® IMVP-6® specification. R3 VDD VR_ON 100us SOFT &VO ~20us PGD_IN CLK_EN# ~7ms IMVP-VI PGOOD FIGURE 4. the start-up sequence begins when VR_ON exceeds the 3. The DROOP pin is the output of the droop amplifier. The ISL6261 regulates the output voltage with ±0. CLK_EN# is pulled LOW. SOFT-START WAVEFORMS USING A 20nF SOFT CAPACITOR 10mV/us 2mV/us Vboot Static Operation After the startup sequence. Implementation of diode emulation mode (DEM) operation further enhances system efficiency. This voltage is used as an input to a differential amplifier to achieve the IMVP-6® load line.

0625 1.3875 1.9250 0.0125 1.9375 0.6750 0.6500 0.0500 1.2875 1.3000 1.5250 0.0375 1.6375 0.1625 1.7625 0.5125 0.4750 0.2750 1.9125 0.4625 12 FN9251. VID TABLE FROM INTEL IMVP-6 SPECIFICATION (Continued) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 VID2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vo (V) 0.4250 1.5875 0.7875 0.4500 1.1 September 27.8000 0.3375 1.7750 0.3125 1.1250 1.2125 1.7375 0.7250 0.2000 1.0875 1.8250 0.7500 0.1875 1.3500 1.5625 0.9750 0.5000 0.3750 1.7125 0.4875 1.7000 0.1000 1.9500 0.2375 1.4625 1.0250 1.5500 0.9625 0.9875 TABLE 1.4875 0.3250 1.4750 1.9000 0.4000 1.4125 1.8500 0.1375 1.1500 1.5000 1.6250 0.5375 0.8625 0.1750 1.ISL6261 TABLE 1.6875 0.6625 0. 2006 .0000 0.2625 1.2500 1.8750 0.6125 0.8125 0.4375 1.1125 1.8875 0.8375 0.2250 1.0750 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vo (V) 1.3625 1.6000 0.5750 0.

0000 0.0875 0.3750 0.2625 0.1500 0.2750 0.2000 0.3375 0.0000 0.0625 0.3125 0. VID TABLE FROM INTEL IMVP-6 SPECIFICATION (Continued) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vo (V) 0.0000 0.1250 0.0375 0.ISL6261 TABLE 1.0000 0.3625 0.1875 0.4375 0.2250 0.1375 0.1 September 27.0500 0.1125 0.0000 TABLE 2.2375 0.2125 0.2500 0.4125 0.3500 0.0750 0. 2006 .0125 0.1625 0.0000 0.0000 0. CONTROL SIGNAL TRUTH TABLES FOR OPERATIONAL MODES OF ISL6261 DPRSTP# 0 Control Signal Logic 0 0 1 FDE 0 0 1 x DPRSLPVR 0 1 x x OPERATIONAL MODE Forced CCM Diode Emulation Mode Enhanced Diode Emulation Mode Forced CCM VW-COMP WINDOW VOLTAGE INCREASE 0% 0% 33% 0% 13 FN9251.1750 TABLE 1.4500 0.4000 0.3250 0.3000 0.2875 0.0000 0.0250 0. VID TABLE FROM INTEL IMVP-6 SPECIFICATION (Continued) VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vo (V) 0.4250 0.1000 0.3875 0.

the output voltage will move at a maximum dv/dt of ±10mV/μs for large changes. Upon load release. the ISL6261 will transiently increase the switching frequency to deliver energy to the output more quickly. as shown in Table 2. PGOOD latched low VR_TT# goes high FAULT RESET VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle VDD toggle VR_ON toggle or VDD toggle VR_ON toggle or VDD toggle N/A 14 FN9251. Intersil R3™ commands variable switching frequency during transients to achieve fast response. PGOOD latched low (OV-1. The maximum dv/dt can be used to achieve fast recovery from Deeper Sleep to Active mode. and DPRSLPVR. PGOOD latched low Low-side FET on until Vcore < 0. These control signals can be tied to lntel® IMVP-6® control signals to maintain the optimal system configuration for all IMVP-6® conditions. DPRSTP# = 0 and FDE = 1 enables the enhanced diode emulation mode (EDEM). the PWM pulses during load application are generated earlier. meaning that the regulator operates in CCM in heavy load. which effectively increases the duty cycle and the response speed of the regulator. and tie DPRSLPVR to the corresponding CPU mode signal. FDE. This mode can be used to support the deeper sleep mode of the microprocessor. TABLE 3.7V) Overvoltage fault (+200mV) Undervoltage fault (-300mV) Over-temperature fault (NTC<1. For example: Control signals lasting less than seven switching periods will not enable the diode emulation mode. which increases the VW-COMP window voltage by 33%. the dv/dt moderates to prevent overshoot.ISL6261 High Efficiency Operation Mode The operational modes of the ISL6261 depend on the control signal states of DPRSTP#. FDE. it turns on as a synchronous FET to reduce the conduction loss. This configuration enables EDEM in deeper sleep mode to increase efficiency. The ISL6261 employs carefully designed mode-transition timing to work in concert with the VID changes. This configuration sets the regulator in EDEM all the time. CPU mode-transition sequences often occur in concert with VID changes. 2006 . The ISL6261 is IMVP-6® compliant for DPRSTP# and DPRSLPVR logic. the ILS6261 will transiently decrease the switching frequency to effectively reduce the duty cycle to achieve fast response. If CSOFT = 20nF and DPRSLPVR = 0. The regulator will enter DCM based on load current. This further decreases the switching frequency at light load to boost efficiency in the deeper sleep mode. The slow dv/dt into and out of deeper sleep mode will minimize the audible noise. Dynamic Operation The ISL6261 responds to VID changes by slewing to new voltages with a dv/dt set by the SOFT capacitor and the logic of DPRSLPVR.7V always) PWM tri-state. the output voltage will move at a dv/dt of ±2mV/μs for large changes. In diode emulation mode. Upon load application. The ISL6261 is equipped with internal counters to prevent control signal glitches from triggering unintended mode transitions. High-speed input voltage transients have little effect on the output voltage. and tie DPRSTP# and DPRSLPVR to the corresponding CPU mode signals.1 September 27. Intersil R3™ has an intrinsic voltage feed forward function. Light-load efficiency is increased in both active mode and deeper sleep mode. PGOOD latched low PWM tri-state. DPRSTP# = 0. and operates in DCM in light load. FDE = 0 and DPRSLPVR = 1 enables the ISL6261 to operate in diode emulation mode (DEM) by monitoring the low-side FET current. When DEM is enabled. and DPRSLPVR. FAULT-PROTECTION SUMMARY OF ISL6261 FAULT TYPE Overcurrent fault Way-Overcurrent fault Overvoltage fault (1.18) FAULT DURATION PRIOR TO PROTECTION 120μs < 2μs Immediately 1ms 1ms Immediately PROTECTION ACTIONS PWM tri-state. PGOOD latched low PWM tri-state. the ISL6261 operates in forced CCM. (2) Tie FDE to “1” and DPRSTP# to “0” permanently. when the low-side FET current flows from source to drain. For other combinations of DPRSTP#. If CSOFT = 20nF and DPRSLPVR = 1. therefore eliminating the extra conduction loss. As the output voltage approaches the VID command value. When the current reverses its direction trying to flow from drain to source. the ISL6261 turns off the low-side FET to prevent the output capacitor from discharging through the inductor.85V. the regulator works in automatic discontinuous conduction mode (DCM). then PWM tristate. There are two options: (1) Tie FDE to DPRSLPVR. Compared with steady state operation. DCM in light load decreases the switching frequency to increase efficiency. The ISL6261 operational modes can be set according to CPU mode signals to achieve the best performance.

1 September 27. IZ adds to ISS to get a larger current.ISL6261 Protection The ISL6261 provides overcurrent (OC). IGV is typically 200μA with a minimum of 175μA. Component Selection and Application Soft-Start and Mode Change Slew Rates The ISL6261 commands two different output voltage slew rates for various modes of operation. recycling VDD will reset it. When connected to the SOFT pin. Rdroop is 2. The low-side FETs will remain on until the output voltage drops below approximately 0. SOFT PIN CURRENT SOURCES FOR FAST AND SLOW SLEW RATES ISS is 41μA typical and is used during startup and mode changes. and the logic state on the DPRSLPVR pin.3k.e. If the output voltage again rises above 1. then all the FETs are turned off.7V. depending on the state of the system. Startup or Active mode. the VR_TT# pin is pulled low indicating the need for thermal throttling to the system oversight processor. The fast slew rate enhances the system performance by achieving active mode regulation quickly during the exit of Deeper Sleep Mode. The ISL6261 controls the output voltage slew rate by connecting or disconnecting another internal current source IZ to the SOFT pin. The IMVP-6® specification reveals the critical timing associated with regulating the output voltage. The OCSET resistor sets the overcurrent protection level.2V over-temperature 15 I SS IZ Internal to ISL6261 Error Ampliflier C SOFT V REF FIGURE 5. Overcurrent is detected through the droop voltage. If the voltage on the NTC pin goes below the 1. is 30A. FN9251. Figure 5 shows the circuitry on the SOFT pin. ISS is an internal current source connected to the SOFT pin to charge or discharge CSOFT. Ioc. SLEWRATE. where Rdroop is the load line slope. Equation 1 gives the selection of ROCSET. 1) For example: The desired over current trip level. The gate driver outputs will be tri-stated and PGOOD will go low.1mΩ. so the processor is still protected against the high-side FET leakage while the FETs are commanded off. There are two levels of overvoltage protection and response. A way-overvoltage (WOV) fault is declared immediately when the output voltage exceeds 1. undervoltage (UV) and over-temperature (OT) protections as shown in Table 3. and discharging the SOFT capacitor when the output voltage is commanded to fall. This mechanism provides maximum protection against a shorted high-side FET while preventing the output from ringing below ground. An OV fault is declared when the output voltage exceeds the VID by +200mV for more than 1ms. the non-inverting input of the error amplifier. Toggling VR_ON cannot reset the WOV protection. labelled IGV in the Electrical Specification Table.7V. 2006 . even when other faults are declared. is connected to ground through capacitor CSOFT. Note that a practical core regulator design usually trips OC before it trips UV. Toggling of VR_ON or bringing VDD below 4V will reset the fault latch. The inductor current will decay through the low-side FET body diode.85V. The over-current condition is detected through the droop voltage. overvoltage (OV). The SOFT-START CURRENT section of the Electrical Specification Table shows the specs of these two current sources. i. the protection process repeats. The droop voltage is equal to Icore×Rdroop. A 10μA current source flows out of the OCSET pin and creates a voltage drop across ROCSET (shown as R10 in Figure 2). on the SOFT pin. The SOFT current is bidirectional ⎯ charging the SOFT capacitor when the output voltage is commanded to rise. A way-overcurrent fault will be declared in less than 2µs when the droop voltage exceeds twice the overcurrent set point. The gate driver outputs will be tri-stated and PGOOD will go low. In both cases. The ISL6261 will latch PGOOD low and turn on the low-side FETs. The slow slew rate reduces the inrush current during startup and the audible noise during the entry and the exit of Deeper Sleep Mode. threshold. the UGATE and LGATE outputs will be tri-stated and PGOOD will go low. Undervoltage protection is independent of the overcurrent limit. No other action is taken within the ISL6261. A UV fault is declared when the output voltage is lower than (VID-300mV) for more than 1ms. The WOV detector is active all the time. The SOFT pin. which is designed as described in the “Component Selection and Application” section. ROCSET = I OC × Rdroop 10 μA (EQ. Overcurrent is detected when the droop voltage exceeds the voltage across ROCSET. An overcurrent fault will be declared when the droop voltage exceeds the overcurrent set point for more than 120µs. Equation 1 gives ROCSET = 6. The ISL6261 has a thermal throttling feature.

SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING given in the IMVP-6® specification.015μF will guarantee 10mV/μs SLEWRATE at minimum IGV value.ISL6261 10uA OCSET R ocset I phase Rs R series L DCR Vo Co ESR R par Ropn1 R ntc 0~10 OC VSUM Internal to ISL6261 DROOP DFB DROOP 1 VO VSEN 1000pF 1000pF 330pF R drp1 R drp2 Cn VCC-SENSE VSS-SENSE 1 RTN VDIFF FIGURE 6. This timer allows PGOOD to go high approximately 7ms after CLK_EN# goes low. CSOFT I GV = SLEWRATE (EQ.1 September 27.8 mV μs C SOFT 0. which powers internal circuitry that is solely devoted to the CLK_EN# function.015 μF (EQ. Capacitance on this pin may create instabilities and should be avoided. 2) If SLEWRATE is 10mV/μs. 2006 . CSOFT is calculated as C SOFT = 200 μA (10 mV μs ) = 20 nF (EQ. 3) Choosing 0. The system 3.Processor Die Sensing Remote sensing enables the ISL6261 to regulate the core voltage at a remote sensing point. At startup. through the following equation: Startup Operation . The 3. The ISL6261 triggers an internal timer for the IMVP6_PWRGD signal (PGOOD pin). The VSEN and RTN pins of the ISL6261 are connected to Kelvin sense leads at the die of the processor through the processor socket. This prolongs battery run time. Static Mode of Operation . CMOS logic eliminates the need for an external pull-up resistor on this pin.3V supply should be decoupled to digital ground. CSOFT. for noise immunity. CLK_EN# remains high until 20μs after PGD_IN going high. determines the choice of the SOFT capacitor. 1% tolerance resistor from the RBIAS pin to ground. This choice of CSOFT controls the startup slew rate as well. 4) Selecting Rbias To properly bias the ISL6261. not to analog ground. One should expect the output voltage to slew to the Boot value of 1.CLK_EN# and PGOOD The ISL6261 provides a 3.2V at a rate given by the following equation: dV soft dt = I ss 41μA = = 2. and Vcc-core is regulated at the Boot voltage. The output is a CMOS signal with 4mA sourcing and sinking capability. Do not connect any other components to this pin. as they will negatively impact the performance. Caution should used in layout: This resistor should be placed in the close proximity of the RBIAS pin and be connected to good quality signal ground. and IGV is typically 200μA. This provides a very accurate 10μA current source from which OCSET reference current is derived.3V logic output pin for CLK_EN#. eliminating the loss on the pull-up resistor caused by CLK_EN# being low in normal operation. free of the inconsistencies and the voltage drops due 16 Ropn2 To Processor Socket Kelvin Conections FN9251. Processor die sensing allows the voltage regulator to tightly control the processor voltage at the die. a reference current needs to be derived by connecting a 147k.3V voltage source connects to the 3V3 pin. (The signal names are Vcc_sense and Vss_sense respectively). which compensates for various resistive voltage drops in the power delivery path.

VR_TT# TEMPERATURE HYSTERISIS 17 FN9251.FSET The R3 modulator scheme is not a fixed frequency PWM architecture. Logic_0 T2 T1 T (oC) Voltage Regulator Thermal Throttling lntel® IMVP-6® technology supports thermal throttling of the processor to prevent catastrophic thermal damage to the voltage regulator. signalling a thermal throttle. Since the voltage feedback is sensed at the processor die.33 VR_TT# Logic_1 (EQ. provide voltage feedback from the regulator local output in the absence of the CPU. Ropn1 and Ropn2 are recommended. FIGURE 8. Another option is to place one between VCC-SENSE and the VSEN pin and another between VSS-SENSE and the RTN pin. as shown in Figure 6. It also varies slightly depending on the input and output voltages and output current. The recommended filter resistance range is 0~10Ω so it does not interact with the 50k input resistance of the differential amplifier. Figure 7 shows the circuitry associated with the thermal throttling feature of the ISL6261. If the NTC pin voltage exceeds 1. the comparator output goes high to pull VR_TT# low. As the temperature drops. Proper selection and placement of the NTC thermistor allows for detection of a designated temperature rise by the system. R fset (kΩ ) = ( period(μs) − 0. VR_TT# goes low when the temperature is higher than T1 and goes high when the temperature is lower than T2. Ropn1 and Ropn2. These traces should be laid out as noise sensitive traces. SW1 turns off and SW2 connects to 1. the ISL6261 stretches the switching period. Common mode and differential mode filters are recommended as shown in Figure 6. connected between the VW and COMP pins of the ISL6261.23V SW2 1. For optimum load line regulation performance. SW1 is on and SW2 connects to the 1. In addition. 54uA 6uA Internal to ISL6261 VR_TT# NTC SW1 V NTC R NTC RS 1. The switching frequency increases during the application of a load to improve transient performance. The total current going into the NTC pin is 60µA. Temperature increase will decrease the NTC thermistor resistance. the regulator will drive the output voltage all the way up to damage the output capacitors due to lack of output voltage feedback.20V FIGURE 7. to prevent this potential issue. The ISL6261A features a thermal monitor sensing the voltage across an externally placed negative temperature coefficient (NTC) thermistor. T1 and T2 (T1>T2) are two threshold temperatures.23V. The filter resistor may be inserted between VCC-SENSE and the VSEN pin. VR_TT# will be pulled high. and therefore sets the switching frequency.2V. Figure 8 illustrates the temperature hysteresis feature of VR_TT#. When the NTC pin voltage drops below 1.20V side. 5) In diode emulation mode.20V threshold voltage and the comparator output is low. At low temperature. 2006 . The need of these filters also depends on the actual board layout and the noise environment. VR_TT# is pulled up high by an external resistor. This decreases the NTC pin voltage. which decreases the NTC pin current by 6µA and increases the threshold voltage by 30mV. The voltage on the NTC pin is higher than 1. sets the synthetic ripple window voltage. CIRCUITRY ASSOCIATED WITH THE THERMAL THROTTLING FEATURE Setting the Switching Frequency .29) × 2. which is important in conserving battery power.1 September 27.23V. Diode emulation mode reduces the switching loss at light load. typically ranging 20~100Ω. The VR_TT# signal can be used by the system to change the CPU operation and decrease the power consumption. The Kelvin sense technique provides for extremely tight load line regulation at the processor die side. but this variation is normally less than 10% in continuous conduction mode. if the CPU is not installed. This relationship between the resistance and the switching frequency in CCM is approximately given by the following equation. the NTC pin voltage goes up. Resistor Rfset (R7 in Figure 2). The switching frequency decreases as the load becomes lighter. the traces connecting these two pins to the Kelvin sense leads of the processor should be laid out away from rapidly rising voltage nodes (switching nodes) and other noisy traces.ISL6261 to layouts.

78kΩ 54 μA (EQ. the series resistor can be derived by: Rs = 1. In some cases. 2600k.20V − R NTC (T1 ) = 20kΩ − R NTC_T1 60 μA (EQ. the actual NTC resistance at T2 and the actual T2 temperature can be found in: R NTC (T ) = R NTCTo 1 1 b⋅( − ) T + 273 To + 273 ⋅e (EQ. using Equation 11 is more accurate for 100°C design and the required NTC nominal resistance at 25°C is 438kΩ.42kΩ. 14) One example of using Equations 10.03956 at 100°C and 0. Since T1 = 105°C and T2 = 100°C. the following can be derived: RNTC(T2 ) − RNTC(T1 ) = 2. To is the reference temperature at which the approximation is derived. 8) From Equation 7 and Equation 8. the NTC resistor satisfies the following equation group: (EQ.78kΩ + RNTC _ T 1 T2 _ actual = 1 1 R NTC _ T2 ln( ) + 1 ( 273 + To ) b R NTCTo − 273 (EQ.78kΩ R NTC (T2 ) − R NTC (T1 ) Λ Λ (EQ. For most commercial NTC thermistors. Equation 9 gives the required NTC nominal resistance as R NTC (T1 ) + Rs = R NTC (T2 ) + Rs = 1. The b value of 4700k in Panasonic datasheet only covers up to 85°C. The NTC thermistor should be placed in the spot that gives the best indication of the temperature of the voltage regulator.78kΩ ⋅ e 1 b⋅( ) T2 + 273 b⋅( 1 ) To + 273 (EQ. 11) where R NTC (T ) is the normalized NTC resistance to its nominal value. 11 and 12 to design a thermal throttling circuit with the temperature hysteresis 100°C to 105°C is illustrated as follows.23V = 22. Once the NTC thermistor resistor is determined. 9) Substitution of Equation 6 into Equation 9 yields the required nominal NTC resistor value: Rs = 20kΩ − R NTC _ 105C = 20kΩ − 15. the constant b is not accurate enough to approximate the resistor value. manufacturers provide the resistor ratio information at different temperatures.39kΩ The closest standard value is 4.ISL6261 The NTC thermistor’s resistance is approximately given by the following formula: Once RNTCTo and Rs is designed.20V = 20kΩ 60 μA 1. It is a 0402 package. Equation 13 gives the NTC resistance at T2: RNTCTo = e 2.42k resistor in series. 13) T is the temperature of the NTC thermistor and b is a constant determined by the thermistor material. Furthermore. The closest NTC resistor value from manufacturers is 470kΩ.78kΩ + RNTC _ T 1 = 18. therefore. From the operation principle of VR_TT#.1 September 27. if we use a Panasonic NTC with b = 4700.61kΩ = 4. 10) 1 b⋅( ) T1 + 273 −e RNTC _ T 2 = 2. So Equation 12 gives the series resistance as follows: (EQ.03322 at 105°C. The most commonly used To is 25°C. The part number of the NTC thermistor is ERTJ0EV474J.78kΩ (EQ. 2006 . The normalized resistor value on most NTC thermistor datasheets is based on the value at 25°C. The actual temperature hysteretic window is approximately 105°C to 100°C. The nominal NTC resistor value may be expressed in another way as follows: RNTCTo = Λ 2. there is b = 2750k.39kΩ The NTC branch is designed to have a 470k NTC and a 4. 7) R NTC_To = 431kΩ The NTC thermistor datasheet gives the resistance ratio as 0. 6) RNTC _ T 2 = 2. 12) 18 FN9251. 4500k or 4250k.

Rn represents the NTC network consisting of Rntc. 17) The inductor DCR is a function of the temperature and is approximately given by DCR(T ) = DCR25C ⋅ (1 + 0. Vn. The droop amplifier output voltage divided by the total load current is given by: An R-C network senses the voltage across the inductor to get the inductor current information. Figure 2 shows the DCR sensing method. Equation 15 gives this relationship. the voltage drop across the Rn network. the process to compensate the DCR resistance variation takes several iterative steps.ISL6261 10uA OCSET Rocset VO OC VSUM Rs Internal to ISL6261 DROOP DFB DROOP R drp2 Cn Rseries Rpar Rntc Rn Vdcr Io DCR 1 VO FIGURE 9. Rseries and Rpar. provides a fairly reasonable amount of light load signal from which to derive the droop voltage. it is desired to have: G1 (T ) ⋅ (1 + 0. The first step in droop load line compensation is to choose Rn and Rs such that the correct droop voltage appears even at light loads between the VSUM and VO nodes.00393* (T − 25) (EQ.00393 * (T − 25)) ≅ G1t arg et (EQ. This gain. is set to be 0. For DCR sensing. As a rule of thumb.00393 is the temperature coefficient of the copper. 20) where G1target is the desired ratio of Vn/VDCR.1 September 27. 18) V DCR = I o × DCR (EQ. The NTC network resistor value is dependent on the temperature and is given by: Rdroop = G1(T) ⋅ DCR (T ) ⋅ k droopamp (EQ. To make Rdroop independent of the inductor temperature. The choice of Rs will be discussed in the next section. 16) For different G1 and NTC thermistor preference. Therefore. the gain of Vn to VDCR. is also dependent on the temperature of the NTC thermistor: G1 (T ) = Δ Rn (T ) Rn (T ) + Rs (EQ. 21) Rn (T ) = ( Rseries + Rntc ) ⋅ R par Rseries + Rntc + R par (EQ.00393 * (T − 25)) (EQ.8 times VDCR. R drp1 (Rntc+Rseries) Rpar Rntc+Rseries+Rpar G1. 2006 . Figure 9 shows the simplified model of the droop circuitry. 19 FN9251. 15) in which 0.Static Droop Using DCR Sensing The ISL6261 has an internal differential amplifier to accurately regulate the voltage at the processor die. Intersil provides a design spreadsheet to generate the proper value of Rntc. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DCR SENSING Static Mode of Operation .5-0. The inductor DC current generates a DC voltage drop on the inductor DCR. Rseries. the temperature characteristics G1 is described by: G 1 (T ) = G 1 t arg et (1 + 0. 19) Rdroop is the actual load line slope. Rpar. defined as G1.

If the output voltage decreases when the temperature increases. k droopamp = 1 + Rdrp 2 R drp1 (EQ. and wait for the thermal steady state. The effective resistance is the parallel of Rn and Rs. However. The Vcore response is determined by several factors. the effective resistance on the DFB and VSUM pins should be identical so that the bias current of the droop amplifier does not cause an offset voltage. Good thermal compensation can limit the drift to less than 2mV. It is recommended to adjust Rdrp2 after the system has achieved thermal equilibrium at full load.ISL6261 Rdrp1 (R11 in Figure 2) and Rdrp2 (R12 in Figure 2) sets the droop amplifier gain. Vcore needs to be as square as possible at Icore change.1 September 27. Rdrp 2 = ( Rdroop DCR ⋅ G1(25 o C ) − 1) ⋅ Rdrp1 (EQ. If the voltage droop is 40mV. use Equation 23 to calculate the droop resistances Rdrp1 and Rdrp2. If Cn is not designed correctly. There will be excessive overshoot if a load occurs during this time. the compensator design. Following the evaluation board value and layout of NTC placement will minimize the engineering time. its voltage will be distorted from the actual waveform of the inductor current and worsen the transient response. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS icore Vcore Vcore FIGURE 11. that ratio between the NTC thermistor value and the rest of the resistor divider network has to be increased. one can apply full load current. 22) After determining Rs and Rn networks. The current sensing traces should be routed directly to the inductor pads for accurate DCR voltage drop measurement. which may potentially hurt the CPU reliability. Vcore is sluggish in drooping to its final value. Vcore may sag excessively upon load application to create a system failure. if the max current is 20A. due to layout imperfection. 20 ⎛ R × Rs ⎞ L ⎟ × Cn =⎜ n DCR ⎜ Rn + Rs ⎟ ⎠ ⎝ (EQ. and the effective resistance on the DFB pin is the parallel of Rdrp1 and Rdrp2. Rs and Cn. The effectiveness of the Rn network is sensitive to the coupling coefficient between the NTC thermistor and the inductor.1mV/A per lntel® IMVP-6® specification. The current sensing network consists of Rn. The RC time constant of the current sensing network needs to match the L/DCR time constant of the inductor to get correct representation of the inductor current waveform. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL icore Vcore R drp 2 _ new = 42 mV ( R drp 1 + R drp 2 ) − R drp 1 40 mV (EQ. To verify whether the NTC network successfully compensates the DCR change over temperature. Figure 12 shows the transient response when Cn is too large. 2006 . If Cn is designed correctly. one should apply 20A load current and look for 42mV output voltage droop. and see how much the output voltage deviates from the initial voltage reading. 23) Rdroop is 2. 24) Vcore FIGURE 12. namely the choice of output inductor and output capacitor. according to Equation 22: The droop capacitor refers to Cn in Figure 9. The NTC thermistor should be placed in close proximity of the inductor. Equation 25 shows this equation: Dynamic Mode of Operation – Droop Capacitor Design in DCR Sensing Figure 10 shows the desired waveforms during load transient response. the new value of Rdpr2 is calculated by: icore Vcore ΔIcore ΔVcore Vcore ΔVcore= ΔIcore×Rdroop FIGURE 10. its voltage will be a high-bandwidth analog voltage of the inductor current. the calculated Rdrp2 may still need slight adjustment to achieve optimum load line slope. The effective resistance on the VSUM pin is the parallel of Rs and Rn. Figure 11 shows the transient response when Cn is too small. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE For the best accuracy. For example. and the droop capacitor design. 25) FN9251.

Compared with potential long-term damage on CPU reliability. It is highly recommended to design the compensation such that the regulator output impedance is 2. It is recommended to keep this resistor below 3k. and show the loop gain curves and the regulator output impedance curve. Since the current sensing resistance does not appreciably change with temperature. After the user inputs the parameters in the blue font. 21 FN9251. the calculated Rdrp2 may still need slight adjustment to achieve optimum load line slope. It is recommended to choose the minimum Cn value based on the maximum inductance so only the scenarios of Figures 10 and 12 may happen. The recommended Rs is 100Ω and the recommended Cn is 220pF. then see the actual loop gain curves and the regulator output impedance curve. The output impedance needs to be 2.1mΩ in order to achieve the 2. DCR = 1. Another good option is the NPO/COG (class-I) capacitor. A type-III compensator is recommended to achieve the best performance. 2006 . The loop gain curves need to be stable for regulator stability.1mΩ.45μH 0. It is recommended to adjust Rdrp2 after the system has achieved thermal equilibrium at full load. Excessively high resistance will cause an error to the output voltage regulation due to the bias current flowing in the FB pin. the L/DCR time constant of each individual inductor may not perfectly match the RC time constant of the current sensing network. 26) For example: L = 0. after calculation. 27) Droop using Discrete Resistor Sensing Static/Dynamic Mode of Operation Figure 3 shows a detailed schematic using discrete resistor sensing of the inductor current. the NTC network is not needed for thermal compensation. 30) For example: Rdroop = 2. L C n = DCR Rn × Rs Rn + Rs (EQ. easy calculation gives that Rdrp2 is 1. Vrsen = Rsen ⋅ I o (EQ. If Rsen = 1m and Rdrp1 = 1k. fine-tuning of Cn value may still be needed to account for board parasitics. In order to use such capacitors. Attention needs to be paid in balancing the impedance of droop amplifier.1 September 27. the resistors and thermistors surrounding the droop voltage sensing and droop amplifier need to be scaled up 10X to reduce the capacitance by 10X.1mΩ. So the actual droop is given by ⎛ Rdrp 2 ⎞ ⎟ Rdroop = Rsen ⋅ ⎜1 + ⎜ R ⎟ drp1 ⎠ ⎝ Solving for Rdrp2 yields: (EQ. Figure 13 shows an example of the spreadsheet.0011 = 174nF Cn = parallel(7. So it is desirable to avoid the waveforms shown in Figure 11. Since the current sensing resistor voltage represents the actual inductor current information. Droop is designed the same way as the DCR sensing approach. But the NPO/COG caps are only available in small capacitance values.1mΩ in the entire frequency range to achieve good transient response.4kΩ 0.45μH. However. Rs and Cn simply provide noise filtering.1mΩ. In mass production.4k ) (EQ.1mV/A load line. A low low ESL sensing resistor is strongly recommended. The voltage on the current sensing resistor is given by the following equation: Since the inductance and the DCR typically have 20% and 7% tolerance respectively. The most significant noise comes from the ESL of the current sensing resistor. 29) Dynamic Mode of Operation . Caution needs to be used in choosing the input resistor to the FB pin. The current sensing traces should be routed directly to the current sensing resistor pads for accurate measurement.1k.ISL6261 Solving for Cn yields The user can choose the actual resistor and capacitor values based on the recommendation and input them in the spreadsheet. Rs = 7.3. and Rn = 3. Cn also needs to be a high-grade cap like X7R with low tolerance. an immediate system failure is worse. Intersil provides a spreadsheet to design the compensator parameters.68k . and the impedance curve needs to be equal to or smaller than 2. 28) Equation 21shows the droop amplifier gain.68kΩ. featuring only 5% tolerance and very good thermal characteristics. this effect will make the transient response vary a little bit from board to board.Compensation Parameters The voltage regulator is equivalent to a voltage source equal to VID in series with the output impedance. the spreadsheet will calculate the recommended compensator parameters (in the pink font). Figure 14 shows the equivalent circuit. due to layout imperfections. ⎛ Rdroop ⎞ Rdrp 2 = Rdrp1 ⋅ ⎜ ⎟ ⎜ R − 1⎟ ⎠ ⎝ sen (EQ. It should be noted that.

ISL6261 FIGURE 13. 2006 .1 September 27. AN EXAMPLE OF ISL6261 COMPENSATION SPREADSHEET 22 VSS FN9251.

6V AND VIN3 = 19V FIGURE 16.1 September 27.6V AND VIN3 = 19V FIGURE 18.1V. VIN2 = 12. VID = 1. C Evaluation Board) R drp1 FIGURE 15.7625V. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING Typical Performance (Data Taken on ISL6261 Eval1 Rev.6V AND VIN3 = 19V 23 FN9251. VIN1 = 8V.6V AND VIN3 = 19V FIGURE 17. DEM LOAD LINE AND THE SPEC. DEM EFFICIENCY.7625V. VID = 0.ISL6261 10uA OCSET Rocset VO OC VSUM Rs Internal to ISL6261 DROOP DFB DROOP Vrsen R drp2 Cn I o Rsen 1 VO FIGURE 14. VID = 0. 2006 . VID = 1. VIN1 = 8V. VIN1 = 8V. CCM LOAD LINE AND THE SPEC. CCM EFFICIENCY. VIN1 = 8V. VIN2 = 12. VIN2 = 12.1V. VIN2 = 12.

SOFT-START. VIN2 = 12. VIN1 = 8V.6V AND VIN3 = 19V FIGURE 21. VID = 1. VIN1 = 8V.1V.6V AND VIN3 = 19V 5V/div 0. VIN2 = 12. ENHANCED DEM EFFICIENCY.5V. VIN2 = 12.5V/div 10V/div FIGURE 23. VID = 1. ENHANCED DEM EFFICIENCY. VIN = 19V. Io = 0A. Ch1: VR_ON.6V AND VIN3 = 19V FIGURE 20.7625V. VID = 0.6V AND VIN3 = 19V FIGURE 22. VID = 1. Ch4: PHASE FIGURE 24.1 September 27. ENHANCED DEM LOAD LINE. SOFT-START. C Evaluation Board) (Continued) FIGURE 19. VIN1 = 8V. VIN = 19V. VID = 1.1V. VIN2 = 12. Ch4: PHASE 24 FN9251. 2006 .1V. Ch2: Vo. Ch2: Vo. Ch1: VR_ON.7625V. ENHANCED DEM LOAD LINE. VIN1 = 8V.ISL6261 Typical Performance (Data Taken on ISL6261 Eval1 Rev. VID = 0. Io = 0A.

5V/div 7. Io = 0. VID = 1. VID=1. VIN TRANSIENT TEST. VBOOT TO VID. Ch4: PHASE FIGURE 30.2V/div 0.1mV = 1A). Ch2: Vo. Ch2: Vo. 2006 . Ch3: PGOOD. Ch1: PGD_IN. VIN = 8 19V. Ch2: Vo. VIN = 19V. VIN = 19V. Ch4: PHASE FIGURE 26. VIN = 19V. Ch2: Vo. SHUT DOWN.1V.5A. VID = 1. Ch1: VR_ON. Io = 2A. Io = 2A. Ch3: VIN. Io = 0. SOFT START INRUSH CURRENT.2V/div 5V/div 5V/div 5V/div 10V/div 5V/div FIGURE 25. Ch4: CLK_EN 5V/div 0.5V.5A. Ch1: CLK_EN#.7625V. C Evaluation Board) (Continued) 5V/div 0. Ch3: PGOOD.5V. CLK_EN AND PGOOD ASSERTION DELAY. Io = 2A. VID = 1.1V. Ch1: Vo. Ch3: Vcomp. Ch1: DROOP-VO (2.5ms 5V/div 10V/div FIGURE 27. Io=2A. Ch4: PHASE 25 FN9251. Ch3: CLK_EN#.1 September 27. VID = 0.1V. VBOOT TO VID. Ch4: PHASE FIGURE 29. Ch3: PGOOD. VIN=19V.ISL6261 Typical Performance (Data Taken on ISL6261 Eval1 Rev. Ch1: PGD_IN. Ch4: PHASE FIGURE 28. VID = 1. Ch2: Vo. VIN = 19V.

7A. Io = 2A 20A.9V.6V. Ch4: PHASE 100A/us 50A/us 100A/us 50A/us FIGURE 35. Ch2: Vo. Ch4: PHASE 26 FN9251. VIN = 8V. Io = 2A 20A at 100A/us. VID = 1. LOAD STEP UP RESPONSE IN CCM. 2006 . Ch2: Vo. Ch4: PHASE FIGURE 36. Ch2: Vo. Ch3: Vcomp.7625V. Ch1: Io. Ch3: Vcomp. LFM VID = 0. Ch3: Vcomp.1 September 27.6V. VID TOGGLING. LOAD TRANSIENT RESPONSE IN ENHANCED DEM. LOAD STEP DOWN RESPONSE IN CCM VIN = 8V. LFM VID = 0. Ch1: DPRSTP#.7A.1V. Ch3: Vcomp. Ch2: Vo. Io = 0. HFM VID = 1. Io= 0.ISL6261 Typical Performance (Data Taken on ISL6261 Eval1 Rev.1V. VIN = 12.9V. VID = 1. VIN = 8V. HFM VID = 1. VIN = 12. C4 VID = 0. Ch1: Io. C Evaluation Board) (Continued) FIGURE 31. Ch4: PHASE FIGURE 34. VID = 1. Ch4: PHASE FIGURE 32.1V. Ch2: Vo. Io = 20A 2A at 100A/us. C4 ENTRY/EXIT. Ch4: PHASE 100A/us 50A/us FIGURE 33. Ch1: Io. LOAD TRANSIENT RESPONSE IN CCM VIN = 8V. Ch1: Io. VID = 1. Ch1: SOFT. Io = 2A 20A. FDE = DPRSLPVR.1V. Ch2: Vo.1V. Ch3: Vcomp.1V. Ch3: DPRSLPVR/FDE.

Ch2: Vo. Ch3: Vcomp. Ch1: Io. Accordingly. Ch4: PHASE FIGURE 38.1V. VID = 1. OVERCURRENT PROTECTION. products are manufactured. C Evaluation Board) (Continued) 100A/us 50A/us FIGURE 37. VIN = 12. Intersil Corporation’s quality certifications can be viewed at www.S.6V. Ch4: PHASE FIGURE 40. OVERVOLTAGE (>1. LOAD TRANSIENT RESPONSE IN ENHANCED DEM. software and/or specifications at any time without notice. the reader is cautioned to verify that data sheets are current before placing orders. see www.6V.1 September 27.7V) PROTECTION. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Information furnished by Intersil is believed to be accurate and reliable. VID = 1. Ch3: PGOOD. Ch4: PHASE All Intersil U. Io = 0A 28A. Ch1: Io. For information regarding Intersil Corporation and its products. VIN = 8V. Io = 2A. Ch2: Vo. Ch3: PGOOD.1mV = 1A). 2006 .1V.com 27 FN9251.1V. nor for any infringements of patents or other rights of third parties which may result from its use. VID = 1. Ch1: DROOP-VO (2. VIN = 12.1V. Intersil Corporation reserves the right to make changes in circuit design. Io = 2A 20A.com/design/quality Intersil products are sold by description only.ISL6261 Typical Performance (Data Taken on ISL6261 Eval1 Rev. LOAD TRANSIENT RESPONSE IN ENHANCED DEM. Io = 2A 20A. VID = 1. However. VIN = 8V. Ch3: Vcomp.intersil. no responsibility is assumed by Intersil or its subsidiaries for its use. assembled and tested utilizing ISO9000 quality systems. Ch4: PHASE 120us FIGURE 39.intersil. Ch2: Vo. Ch2: Vo.

22UF P3 C15 DNP C25 0.3V 1X3 D3 C PGOOD PSI# 2 2 1 1 1 1 2 2 3 3 3V3 VID6 VID5 VID4 VID3 VID2 VID1 VID0 J17 J1 P7 P10 P1 SSL_LXA3025IGC 0 P14 R39 10 34 2 DNP P2 2N7002 1 +5V R20 499 C17 P34 C30 2 0.3V PGOOD DPRSLPVR C24 MST7_SPST IN IN IN IN IN IN IN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 5V 3.3V J3 C VCC_PRM 6.3V R33 0 R34 0 R35 0 1 2 VR_ON J19 1 2 2 +5V J16 IN IN VCCSENSE COMP R11 0 C14 0 47PF 2.23K C7 330PF VIN IN VCC_PRM NOTE: RUN LGATE1 TRACE PARALLEL TO TRACE CONNECTING PGND1 AND SOURCE OF Q3 AND Q4.8 7 6 5 4 2 3 1 P13 P16 P18 P19 P20 P23 P24 P25 P27 P28 P31 10K R32 10K R36 10K R37 10K R38 10K R40 10K R41 10K R42 J8 1 1 2 2 2 10 9 8 7 6 IN IN IN D 1 2 3 4 5 6 7 14 13 12 11 10 9 8 U1 R47 100 +3.01UF DNP C29 ISL6261CR 1UF P32 P26 C2 10UF P9 C11 P11 IN P29 VSSSENSE 330PF 0 C6 P15 R12 1000PF IN GND_POWER C18 1000PF 0 VSEN RTN C27 1UF C26 DROOP DFB R15 1K 0.12UF C19 0.015UF C10 R17 DNP R16 DNP C31 RBIAS VR_TT OUT 10UF R4 PGD_IN PGOOD 40 3V3 39 CLK_EN 38 DPRSTP 37 DPRSLPVR 36 VR_ON 35 VID6 34 VID5 33 VID4 32 VID3 31 10UF Q5 C8 147K 1 1 R22 +3. 2006 .57K 10K NTC R31 IN P30 DNP 28 +3.21K R25 IN VCORE R5 VDIFF1 ON 10K R45 1 1 2 2 3 3 0 VR_ON1 R6 10K 1X3 P21 P17 A R7 A DNP R8 DNP 5.1UF C16 0.1 September 27.3V1 IN S1 P33 +3.53K R28 R29 VSUM IN 3. TITLE: REV: P22 ISL6261 EVAL1 CONTROLLER ENGINEER: JIA WEI DRAWN BY: 5 4 3 2 ? DATE: MAR-14-05 SHEET: 1 OF 5 1 8 7 6 FN9251.34K C3 OCSET SOFT U6 LGATE GND_POWER PHASE UGATE BOOT J4 B R43 10K R44 P8 3 1 S4 OFF +3. C Evaluation Board Schematic 6.49K DNP R30 0 R19 R23 C20 11 12 13 14 15 16 17 18 19 20 C23 VDIFF VSEN RTN DROOP DFB VO VSUM VIN VSS VDD B 41 FB EP FDE PGD_IN RBIAS VR_TT NTC SOFT OCSET VW COMP FB VID2 VID1 VID0 VCCP LGATE VSSP PHASE UGATE BOOT NC OUT OUT OUT OUT 30 29 28 27 26 25 24 23 22 21 0.068UF C21 8200PF R27 4.81K C13 1000PF P12 P5 P4 C9 150PF C12 464K R24 390PF 5.3V J2 R46 10 C28 VW 1 2 3 4 5 6 7 8 9 10 R9 ISL6261 DNP R13 ISL6261 Eval1 Rev.3V 3 4 5 1 2 3 4 5 10K R10 10K R14 10K R18 R3 P6 R103 10K R21 10K +3.3V OUT DPRSLPVR PSI# PGD_IN DPRSTP# SD05H0SK FDE VR_ON DPRSLPVR DPRSTP# CLK_EN# J15 1 1 2 2 J10 1UF ON ON ON ON ON D 10K OUT R1 510 3 R2 510 J9 1 12 2 1 GRN RED FDE +3.

2006 8 8 BOOT PHASE 0.1UF J5 P38 VSSSENSE VCCSENSE VSUM OUT R51 7.1UF C91 0.P36 C33 DNP 2 R49 DNP D2 DNP C32 1UF 10UF C4 1 3 5 1 2 10UF C5 10UF C5B R82 56UF R83 3 1 2 56UF C34 0.22UF UGATE LGATE R48 C1 0 P35 7 Q1 IRF7821 IRF7832 7 Q2 Q4 VIN Q3 IRF7821 IRF7832 6 J21 4 4 IN IN 6 OUT J20 4 5 1 1 P37 4 J22 4 BUS WIRE 3 3 TITLE: ISL6261 EVAL1 POWER STAGE ENGINEER: JIA WEI DRAWN BY: DATE: MAR-14-05 SHEET: 2 OF 5 2 A C40 330UF C41 330UF 2 C89 330UF VCORE J14 1 1 OUT OUT C D B .45UH P39 J6 VCC_PRM OUT R53 0 DNP R54 R60 P40 3 1 2 C35 J13 1 0.1UF P41 C45 22UF C51 22UF C57 22UF C63 22UF C69 22UF C71 22UF REV: 1 C42 22UF C50 22UF C56 22UF C62 22UF C68 22UF C39 22UF C49 22UF C55 22UF C61 22UF C67 22UF C43 330UF C44 330UF C90 330UF C38 22UF C48 22UF C54 22UF C60 22UF C66 22UF C70 22UF C37 22UF C47 22UF C53 22UF C59 22UF C65 22UF C36 22UF C46 22UF C52 22UF C58 22UF C64 22UF GND_POWER ISL6261 Eval1 Rev.68K DNP R52 R50 0 L1 0. C Evaluation Board Schematic 29 A C D B IN IN IN IN ISL6261 (Continued) FN9251.1 September 27.

8 7 6 5 4 2 3 1 D AF24 AF21 AF19 AF16 AF13 AF11 AF8 AF6 AF3 AE26 AE23 AE19 AE16 AE14 AE11 AE8 AE4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VCCSENSE B26 D C PSI GTLREF VID6 VID5 VID4 VID3 VID2 VID1 VID0 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S G21 J6 J21 K6 K21 M6 M21 N6 N21 R6 R21 T6 T21 V6 V21 W21 PSI# AE6 OUT AD26 AE2 VID6 AF2 VID5 OUT AE3 VID4 OUT AF4 VID3 OUT AE5 VID2 OUT OUT AF5 VID1 OUT AD6 VID0 OUT AF26 AF25 AF23 AF22 AF1 AE25 AE24 AE22 AE21 AD24 AD23 AD21 AD20 AD4 AD3 AD1 AC26 AC25 AC23 AC22 AC20 AC5 AC4 AC2 AC1 AB25 AB24 AB22 AB21 AB6 AB5 AB3 AB2 AA26 AA24 AA23 AA21 AA6 W22 ISL6261 Eval1 Rev.1 September 27. C Evaluation Board Schematic S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S IN GND_POWER A VSSSENSE OUT A3 A5 A6 A21 A22 A24 A25 B1 B2 B3 B4 B5 B22 B23 B25 C1 C3 C4 C6 C7 C20 C21 C23 C24 C26 D2 D3 D5 D6 D7 D20 D21 D22 D24 D25 E1 E2 E4 E5 E22 E23 E25 E26 F1 F3 F4 F6 F21 F23 F24 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S COMP3 COMP1 COMP2 COMP0 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S W6 W5 W3 W2 V26 V24 V23 V4 V3 U25 U23 U22 U5 U4 U2 T25 T24 T22 T5 T3 T2 R24 R23 R4 R3 R1 P26 P25 P23 P22 P5 P4 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 AE7 F26 G2 G3 G5 G6 G22 G24 G25 H1 H2 H4 H5 H22 H23 H25 H26 J1 J3 J4 J23 J24 J26 K2 K3 K5 K22 K24 K25 L1 L2 L4 L5 L22 L23 L25 L26 M1 M3 M4 M23 M24 M26 N2 N3 N5 N22 N24 N25 P1 P2 30 V1 U26 U1 R26 AA4 AA3 AA1 Y26 Y25 Y23 Y22 Y5 Y4 Y2 Y1 W25 W24 OUT AF7 IN VCORE INTEL_IMPV6 SOCKET1 C INTEL_IMPV6 INTEL_IMPV6 SOCKET1 SOCKET1 ISL6261 B A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AF20 AF18 AF17 AF15 AF14 AF12 AF10 AF9 AE20 AE18 AE17 AE15 AE13 AE12 AE10 AE9 AD18 AD17 AD15 AD14 AD12 AD10 AD9 AD7 AC18 AC17 AC15 AC13 AC12 AC10 AC9 AC7 AB20 AB18 AB17 AB15 AB14 AB12 AB10 AB9 AB7 AA20 AA18 VCCA VCCSENSE VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C2 C5 C8 C11 C14 C16 C19 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F2 F5 F8 F11 F13 F16 F19 F22 F25 G1 G4 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 B (Continued) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AE1 AD25 AD22 AD19 AD16 AD13 AD11 AD8 AD5 AD2 AC24 AC21 AC19 AC16 AC14 AC11 AC8 AC6 AC3 AB26 AB23 AB19 AB16 AB13 AB11 AB8 AB4 AB1 AA25 AA22 AA19 AA16 AA14 AA11 AA8 AA5 AA2 Y24 Y21 Y6 Y3 W26 W23 W4 W1 V25 V22 V5 V2 U24 U21 U6 U3 T26 T23 T4 T1 R25 R22 R5 R2 P24 P21 P6 P3 VSSSENSE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TITLE: A ISL6261 EVAL1 SOCKET ENGINEER: JIA WEI DRAWN BY: 7 6 5 4 3 2 REV: DATE: MAR-14-05 SHEET: 3 OF 5 1 8 FN9251. 2006 .

9K 3 C81 2 10UF 31 C80 1 2 3 4 IN U5 8 1UF VCORE Q15 1 2 4 J23 ISL6261 (Continued) GND_POWER R72 499 2 3 ON OFF 1 2N7002 S5 1 Q14 FN9251. 2006 .12 R71 49.J12 GND_POWER +12V J11 VDD HB HO HS 7 6 5 LO VSS LI HI R74 249 2 1 D1 3 1 HIP2100 R73 249 +12V +12V BAV99 3 2 HUF76129D3S 3 ISL6261 Eval1 Rev.1 R76 0. C Evaluation Board Schematic R75 0.1 September 27.

1UF +3.3V_GEY MODE TRANS Vcc 14 13 12 11 10 B 3 1 2 A2 0.1UF +3.1UF 1 2 D 3 4 J7 6 8 9 10 7 7 A6 A7 A8 GND Y7 12 11 30 31 25 26 27 Y5 Y6 13 OUT OUT OUT OUT 1 2 3 4 5 6 7 14 DIRECT 1 1 2 2 3 3 10K R82 10K R85 10K R88 10K R94 C85 10K R100 15PF 1 3 4 2 G1 A1 G2 Y1 Y2 17 18 19 VCC C73 1UF 1 6 29 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 NC NC RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 VSS VSS OUT OUT OUT OUT OUT OUT OUT VDD VDD 7 28 HCM49 C A2 A3 2 0.3V_GEY 2 3 2 1 BAV99 9 S9 3 A3 Y2 C77 0.01UF P42 R68 10 GND HC540 Y8 11 DNP MST7_SPST A8 Y7 P45 10K R83 10K R86 10K R89 10K R92 10K R95 10K R98 10K R101 ISL6261 U9 1 G1 A1 G2 19 17 VCC 20 +3. 2006 .1UF EVQPA R79 0 R80 0 7 1 2 3 4 5 6 7 4 14 14 13 13 12 12 11 11 10 10 9 9 8 8 2 8 A7 Y6 +3.8 7 6 5 U10 1 2 3 4 5 4 3 2 1 10K R81 10K R84 10K R87 10K R90 10K R93 10K R96 U7 G1 A1 A2 A3 Y2 17 16 10K R99 U2 VCC G2 Y1 Y3 18 19 20 +3.1UF BAV99 R63 10K 4 6 7 9 10 5 5 A4 A5 A6 A8 GND Y7 12 11 Y3 Y4 Y5 14 15 13 16 7 3A 3Y GND EVQPA 6 6A 6Y 5A 5Y 4A 4Y S2 2 4 3 3 4 5 8 2 1 6 DPRSLP S6 1 4 AC04 (Continued) R70 0 R78 0 C75 R66 10K C84 DNP C88 1 R64 10K 10K 10K A R56 R57 R58 10K 10K 10K 10K 6 5 R59 R61 R62 7 R55 10K +3.3V_GEY C74 1 R65 U4 Y1 18 10K 3 3 ISL6261 Eval1 Rev.3V 1 C76 R102 10K 32 6 5 A5 19 20 21 22 23 24 Y4 15 12 13 33 34 1X3 A4 32 35 36 37 42 43 44 1 8 9 10 11 14 15 16 17 VID0 VID1 VID2 VID3 VID4 VID5 VID6 DELAY DPRSLPVR D 14 14 13 13 12 12 11 11 10 10 9 9 8 8 R106 DNP U11 C78 1 2 MST7_SPST HC540 U3 18 Y8 38 39 40 41 2 3 4 5 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 NC NC RA0 RA1 RA2 RA3 RA4 RA5 OSC1 OSC2 MCLR PSI# DPRSTP# PGD_IN VR_ON1 OUT 3 5 4 2 3 C 4 A4 Y3 16 0 1 2 3 4 5 6 7 DNP 1 9 12 EVQPA J28 1 2 2 +3.3V_GEYR69 R104 10K RESETS8 15PF 1 20 +3. ENGINEER: DATE: MAR-14-05 JIA WEI DRAWN BY: SHEET: 5 OF 5 4 3 2 1 8 FN9251.3V_GEY C87 U8 10K R91 10K R97 C79 5 6 8 7 A6 A7 Y6 13 Y5 R105 P43 6 14 7 IN CLK_EN# R67 0 A5 Y4 15 0.3V_GEY J25 1 2 2 DNP HC540 LOOP P44 MST7_SPST Y8 0.3V_GEY 1A 1Y 2A 2Y B A PSI# S7 1 2 4 3 J24 1 2 2 +3.3V_GEY +3.3V_GEY C72 0.1 September 27.3V C86 1UF R77 U12 10K 1 2 14 14 13 13 12 12 11 11 10 10 9 9 8 8 +3. C Evaluation Board Schematic S3 0.1UF PIC16F874 +3.3V_GEY EVQPA PSI# J29 1 1 2 2 REV: TITLE: ISL6261 EVAL1 GEYSERVILLE TRANSITION GEN.

10 ) C ( 40X 0 . 00 MIN. 5. Tiebar shown (if present) is a non-functional feature.50 40 1 6 PIN #1 INDEX AREA 4 .08 C C 0 .15 20 TOP VIEW 40X 0 . DETAIL "X" NOTES: 1. 1 BOTTOM VIEW 11 10 0. 10 ± 0 . Dimensioning and tolerancing conform to AMSE Y14. 23 +0 . 05 SEE DETAIL "X" 0. 6 ) TYPICAL RECOMMENDED LAND PATTERN 0 .6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2.ISL6261 Package Outline Drawing L40.10 M C A B 4 0 . The configuration of the pin #1 identifier is optional.1 September 27.015mm and 0. 15 6. Dimensions in ( ) for Reference Only. Dimensions are in millimeters. tolerance : Decimal ± 0.5m-1994. 0 . 9/06 4X 4. Unless otherwise specified. 23 ) ( 40X 0 . Dimension b applies to the metallized terminal and is measured between . 6. 3.05 4. 33 FN9251.00 A B 6 PIN 1 INDEX AREA 31 30 36X 0. 90 ± 0 . 5 ) SEATING PLANE 0.00 21 (4X) 0. 07 / -0 . 4 ± 0 . 2006 . but must be located within the zone indicated. 1 ( 5 . The pin #1 indentifier may be either a mold or mark feature. 2 REF 5 0 . 8 TYP ) ( 4 . 05 MAX.10 C BASE PLANE SIDE VIEW ( 36X 0 . 2.5 6.30mm from the terminal tip.

10 M C A B 4 0. 5. DETAIL "X" NOTES: 1.5 7. 9/06 4X 5. The configuration of the pin #1 identifier is optional.1 September 27. 90 ± 0 . Dimensions are in millimeters.23 +0.05 BOTTOM VIEW SEE DETAIL "X" 0. 6.ISL6261 Package Outline Drawing L48. 1 13 12 0. 00 MIN. 23 ) ( 48X 0 .015mm and 0.07 / -0.08 C C ( 48X 0 . Dimension b applies to the metallized terminal and is measured between .05 4. but must be located within the zone indicated.30mm from the terminal tip. 1 SIDE VIEW ( 44X 0 .50 48 1 6 PIN #1 INDEX AREA 7. 2 REF 5 0 . 30 ) 0 .10 C BASE PLANE C ( 6 . 60 ) TYPICAL RECOMMENDED LAND PATTERN 0 . 15 25 (4X) 0.5m-1994. 05 MAX. 30 ± 0 . tolerance : Decimal ± 0.00 4. 3. 80 TYP ) ( 4 . Tiebar shown (if present) is a non-functional feature. Dimensioning and tolerancing conform to AMSE Y14. Dimensions in ( ) for Reference Only. The pin #1 indentifier may be either a mold or mark feature.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3. 34 FN9251.00 A B 6 PIN 1 INDEX AREA 37 36 44X 0. 5 ) SEATING PLANE 0. 0 . 40± 0 . 2006 . Unless otherwise specified.15 24 TOP VIEW 48X 0 . 2.