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IsLab |r% z  @/ Analog Integrated Circuit Design COMP-21

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CMOS Comparators
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Kyungpook National University
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-1
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Comparators
t A comparator is used to detect whether a signal is greater or smaller
than zero, or to compare the value of one signal to another.
t The second most widely used components after ampliers.
t Widespread use in A/D converters, data transmission, switching
power regulators.
t Using an opamp for a comparator: too slow but a good example to
discuss design principles for minimizing V
OS
and charge injection.
t Other approaches: multistage comparators, positive-feedback
track-and-latch comparators, fully dierential comparators.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-2
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Using An Opamp for A Comparator
t Using an open-loop opamp for a comparator.
t Slow response time due to slewing and settling time.
t A simple approach.
v
i
+
V
OS
+

v
o
t Limited resolution due to V
OS
of 2 5 mV for typical MOS processes.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-3
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Switched-Capacitor Comparator
t Operation: reset phase (
1
) + comparison phase (
2
).
v
i

2
C

1a

1
v
o
t
1a
is a slightly advanced version of
1
so that charge-injection eects
are reduced to the eect due to only the switch
1a
.
t The opamp must be stable for unity-gain feedback during
1a
.
t The bottom plate of integrated capacitors has more signicant
parasitic capacitance between it and substrate than the top plate.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-4
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t Therefore, the bottom plate is always connected to the less sensitive
node rather than critical node.
t Although used in early ADCs, this opproach is not preferable
nowadays due to slow operation (500 Hz).
t A technique for speeding up (50 times) the comparision time is to
disconnect the compensation capacitor during the comparision phase.
t The input capacitor C is never charged or discharged during
operation, v
C
remains at 0 V. Use a reasonably large C to minimize
charge injection and clock-feedthrough eects.
t If
1
and
2
of switches attached to the bottom plate interchanged,
the comparision operation would be noninverting. But C must be
charged or discharged during reset phase.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-5
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Cancelling Input-Oset Voltage Errors
t The reset phase.
v
i

2
V
OS
+

+
V
OS

1a

1
v
o
t The comparision phase.
v
i

2
V
OS
+

+
V
OS

1a

1
v
o
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-6
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Charge-Injection Errors
t Charge injection (clock feedthrough): unwanted charges is injected
into the circuit when the transistors turn o.
t The comparator with switches: channel charge + overlap C.
v
i
Q
1
C
ov1

2
v
2
v
1
C

+
Q
3

1a
C
ov3
Q
2
C
ov2

1
v
o
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-7
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t Channel charge: V
DS
= 0.
Q
ch
= WLC
ox
(V
GS
V
t
)
t When Q
3
turns o: v
2c
(channel charge) + v
2o
(overlap C).
v
2c
=
Q
ch
/2
C
=
C
ox
W
3
L
3
V
e3
2C
=
C
ox
W
3
L
3
(V
DD
V
tn
)
2C
v
2o
=
v
GS3
C
ov3
C +C
ov3
=
(V
DD
V
SS
)C
ov3
C +C
ov3
v
GS3
C
ov3
C
v
2
Resolution |v
C
| = |v
2c
+ v
2o
| 13 + 10 = 23 mV
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-8
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Making Charge-Injection Signal Independent
t When Q
2
turns o, its charge injection causes a negative glitch at v
1
,
but this will not cause any change in the charge stored in C since the
right side of C is connected to an open node (no current ow).
i = C
dv
C
dt
= 0, v
C
= v
2
v
1
= 0
t Thus, v
2
is unaected by the charge injection of Q
2
. When Q
1
turns
on, v
1
will settle to v
i
regardless of the charge injection of Q
2
. The
charge injection of Q
1
has no eect due to similar reason.
t By turning o
1a
rst, the circuit is aected only by the charge
injection of Q
3
. And the charge injection is signal independent.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-9
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A Clock Generator with Advanced Phases
t Nonoverlapping two-phase clock with phases advanced by two
inverter delays.

1a

1

2a

2
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-10
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Minimizing Errors Due to Charge Injection
t The simplest way is to use larger capacitors, but this would require a
large amount of silicon area: v
C
1/C.
t Integrated capacitors have parasitic capacitances between the bottom
plate and the substrate. This bottom plate capacitance might be
about 20% of the size of the realized capacitor. This capacitor would
have to be driven by the input circuits, which would slow down the
circuits.
A top plate capacitance also exists due primarily to interconnect
capacitance, but it is typically on the order of 1 to 5% of the realized
capacitance.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-11
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t A fully dierential switched-capacitor comparator: the charge
injection of Q
3a
matches that of Q
3b
v
C
/10.

+
+

Q
3a

1a
+
C
Q
2

1
Q
1

2
+
Q
3b

1a

v
o
C
Q
4

1
Q
3

v
i
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-12
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t A multistage switched-capacitor comparator: error voltage storing
(
1
) + eliminating (
2
), the uncompensated error voltage in the
input of the last stage v
C
n
, v
C
1
= charge injection + oset, input
equivalent error voltage v
i
(57 V), refer to clock waveforms.
v
1
(

11
) = A
1
(v
C
1
) = v
C
2
, v
1
(
2
) = A
1
(v
i
+ v
C
1
)
v
2
(
2
) = v
1
(
2
) +v
C
2
= A
1
(v
i
+ v
C
1
) +A
1
v
C
1
= A
1
v
i
v
o
= A
2
(v
2
+ v
C
2
) = A
1
A
2

v
i

v
C
2
A
1

v
i
=
v
C
n
A
1
A
2
A
n1
v
i

2
v
C
1
+
C
1


+
A
1

11

1
v
2
v
1
+
C
2


+
A
2

12
v
o
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-13
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Speed of Multistage Comparators
t A multistage comparator using a cascade of inverters: very high
resolution as combining with fully dierential design techniques.
Although the multistage comparator has speed limitation due to
multiphase clock, it can be reasonably fast and stable because of
high-speed individual stages that have only a 90

phase shift.
t The parasitic load capacitance of the ith stage: except for the last
stage, C
pi
C
o,i
+C
gs,i+1
< 2C
gs,i
for large W if C
gs
C
o
, C
r
.
v
i
A
1
C
p1
A
2
C
p2
A
3
C
p3
v
o
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-14
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t The unity-gain frequency of a single stage i: C
L
= 2C
gs,i
.

ti

g
mi
2C
gs,i
=

T
2
t The transfer function of a single stage: dominant-pole approximation.
A
i
(s)
A
0i
1 +s/
pi
,
pi


ti
A
0i
t The overall transfer function of an n-stage comparator.
A(s) =

A
i
(s)

A
0i
1 +s

1/
pi

A
n
0
1 +sn/
pi
t The overall time constant of an n-stage comparator.

n

pi
=
2nA
0
C
gs
g
m

4nA
0
L
2
3
n
V
e
4 ns
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-15
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Latched Comparators
t A modern high-speed comparator: preamp + track-and-latch stage.
+

+
v
+
i
v

i
Preamplier
track and latch
v
L
v
L
v
L
v
L
v

o
v
+
o
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-16
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t Preampliers: low gain (4 10) for high speed, used for higher
resolution and reduction of kickback eects. Kickback denotes the
charge transfer either into or out of the inputs when the TAL stage
goes from track mode to latch mode. Without a preamplier, cause
very large glitches in the input circuit, especially when the input
impedances are not perfectly matched limited accuracy.
t The track-and-latch stage: amplies the signal further during the
track phase, and then amplies it again during the latch phase by
positive feedback minimizes the total number of gain stages.
t Hysteresis might be eliminated by connecting internal nodes to one of
power supplies or by connecting dierential nodes together
(no memory).
t For high resolution, coupling capacitors and reset switches are
included to eliminate any V
OS
and v
C
errors.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-17
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Latch-Mode Time Constant
t Two back-to-back inverters as a simplied model of a TAL stage in the
latch phase. The inverters can be modelled as a VCCS driving an RC load
for v
x
v
y
.
v
x
v
y
A
v
R
L
v
y
R
L
+
v
x

C
L
A
v
R
L
v
x
R
L
+

C
L
t Node equations by KCL:
L
= R
L
C
L
, v v
x
v
y
.

L
dv
x
dt
+v
x
+A
v
v
y
= 0,
L
dv
y
dt
+v
y
+A
v
v
x
= 0


L
A
v
1

dv
dt

= v
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-18
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t Voltage dierence between the output voltages of inverters.
v = v
0
e
(A
v
1)t/
L
v
0
e
t/
t Latch-mode time constant: C
L
k
1
WLC
ox
, G
m
k
2
g
m
.
=

L
A
v
1

R
L
C
L
A
v
=
C
L
G
m
=
k
1
k
2
L
2

n
V
e
= (2 4)
L
2

n
V
e
t The latch time for a voltage dierence v v
L
(valid logic voltage)
the speed would be limited by preampliers and TAL during track
phase.
t
latch
= ln

v
L
v
0

0.5 ns 1 GHz
t If v
0
is small, the rise time can be larger than the allowed time for
the latch phase undetermined logic value for succeeding circuitry.
This is called metastability. Even when v
0
is large enough, circuit
noise can cause v
0
to become small enough to cause metastability.
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-19
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A Two-Stage Comparator with Digital Output
t Low-impedance nodes and diode-connected loads for high speed, precharging nodes
to eliminate hysteresis, fully dierential comparator.
+

v
o
Latch
Latch

+
v
i
Preamplier
Positive feedback
Digital output
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-20
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A Two-Stage Comparator with Capacitive Coupling
t Capacitive coupling to eliminate V
OS
and charge-injection errors: resolution
v < 0.1 mV at a 2-MHz clock frequency for 5-m technology.

11

11 C
1

2
+
v
i
C
1

1
First SC gain stage
CMFB circuitry

12

12
C
2
C
2
Track
Second gain stage
Track
Positive feedback
Integrated Systems Lab, Kyungpook National University
IsLab |r% z  @/ Analog Integrated Circuit Design COMP-21
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Homework
t Problems: 7.1, 7.6, 7.7, 7.8, 7.11.
t Describe the operation principle and the important properties of the
comparator used in [1].
References
[1] Y. T. Wang and B. Razavi, An 8-Bit 150-MHz CMOS A/D Converter, IEEE J.
of Solid-State Circuits, vol. 35, no. 3, pp. 308317, 2000.
[2] A. Worapisher, J. B. Hughes, and C. Toumazou, Speed and accuracy
enhancement techniques for high-performance switched-current comparators,
IEEE J. of Solid-State Circuits, vol. 36, no. 4, pp. 687690, 2001.
Integrated Systems Lab, Kyungpook National University