Cadence SOC Encounter Tutorial

Cadence SOC Enco n er T orial
Ba ed on P of. Mi cea S an' T o ial a he Uni e i of Vi ginia The follo ing Cadence CAD ool ill be ed in hi o ial:

SOC Enco n er fo backend de ign (floo planning, place and o e, po e and clock di ib ion). Yo ma an o e i i Sim la ion T o ial and Logic S n he i T o ial befo e doing hi ne o ial.

R nning he Cadence backend ool No o ho ld be able o n he Cadence ool . Ne e n Cadence f om o oo di ec o , i c ea e man e a file ha ill cl e o oo . In ead plea e c ea e a di ec o (e.g. cadence, o ho ld ha e hi al ead ) and ano he di ec o fo he de ign (e.g. o ial, ho ld ha e i ), link he lib a file o o di ec o ch ha i ill be ea ie o na iga e o hem, and finall one fo he enco n e file (e.g. enco n e ): <>
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The command e c n e (no &) a no

SOC Enco n e in he fo eg o nd and o

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a p indo :

eeweb.pol .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.html


in m ca e a . hen on Clo e Then click on A o A ign fo he Top Cell a ignmen . in . Fo mo e info ma ion on he a io Cadence ool I enco age o o ead he co e ponding man al . lf./lib) hen click on o 018_ dcell . and finall on Add. click on he men . D ing he eme e o ill ha e o look fo info ma ion in he on-line man al o complemen he (limi ed) info p o ided in he e o ial .. Click on Design -> Import Design.. No e can a ing Enco n e . Spend ome ime b o ing he man al o nde and ha i a ailable (a lo !). Na iga e o he lib di ec o ( ha o j linked in o o o ial di ec o ./lib) hen click on o 025_ dcell . Yo can ge o he men efe ence man al fo Enco n e b p e ing Help on he igh of he Men Ba . Then e need o pecif he ph ical defini ion fo he lib a . make e o click on Add. on he Toolba idge . do ha b clicking on he na iga e b on on he igh of he Common Timing Lib a ie en hich ho ld pop./ n he i . Na iga e o he lib di ec o ( ha o j linked in o o o ial di ec o .p (a an a ide.p he LEF File indo . I a me hi mean o can do RTL n he i in Enco n e di ec l i ho ing RC. e c.. No o need o fill in he Ve ilog ne li ( e he b o e b on on he igh o na iga e o o n he i ed ne li .pol .. hen on Clo e Then e need o pecif he iming defini ion fo he lib a . hen on Clo e eeweb. and finall on Add. in m ca e a . i eem o can al o impo RTL di ec l . Yo can hink of hi o ial a a in b e of he one a ailable nde help. do ha b clicking on he na iga e b on on he igh of he LEF File en hich ho ld pop. i o ld be in e e ing o hi and ee ho i o k ). Yo can al o di ec l acce doc men a /op /cadence/SOC62/doc/enco n e . and he De ign Impo indo ho ld pop.. Fi e need o impo he n he i ed ne li ( he e l of RTL n he i i h RTL Compile ).edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter. no j nominal anal i ). Fo ho e ha an o lea n Enco n e in o mo e dep h he e a e ome eall nice o ial in /op /cadence/SOC62/ ha e/fe/gif / o ial /d mf/ o k_fe.html 2/15 .p he Timing File indo (no e ha mo e ad anced lib a ie ill ha e Ma Timing and Min Timing Lib a ie in o de o be able o do "co ne anal i ".lef.2/12/12 Cadence SOC Encounter Tutorial The indo ha h ee main a ea : Menu Bar ( op) Select Bar ( igh ) Displa Area (middle) Plea e o familia i e o elf i h he main indo . in m ca e acc _ n h.

pol . if hi a a f ll chip de ign.2/12/12 Cadence SOC Encounter Tutorial No mall . Yo De ign Impo pop.p indo ho ld look like hi no e No click on he Ad anced ab a he op follo ed b Po e on he lef . Fill in dd fo Po e Ne and gnd fo G o nd Ne (o of c io i o can check ha indeed he e a e he name of he po e and gnd ne in o Ve ilog ne li b opening he file in a e edi o ). e o ld al o ha e o pecif he I/O pad info ma ion no b he IO A ignmen File.edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter. b fo no ill no e I/O pad . eeweb.html 3/15 .

A c ic Ge e a e F E i a e ce.pol . Ge fa iia ) e ee he de ig hie a ch . De ig I i d .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.2/12/12 Cadence SOC Encounter Tutorial N c ic he IPO/CTS a d fi b f f B ffe Na e/F i a d i f I e e Na e/F i ( i deed he e a e he f i a e b e a i i g he . f e a e he De ig B e idge ( he 4/15 eeweb.html . fc i i i Ba ed ca chec ha F ci a Fi a c ic OK i 7 hf he igh . ih e f he idge . e c. f fie i he ib di ec ).

00).html 5/15 . Since our design is simple and flat there is not much that needs to be done.edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter. eeweb. but in general now is the time to decide how the big blocks that make up the design should be placed with respect to each other.pol .00 (default is 0. Core to Top and Core to Bottom to 100.2/12/12 Cadence SOC Encounter Tutorial Now we need to specif floorplaning information. Also. change Ratio (H/W) to 1. Click on Floorplan -> Specif Floorplan and change Core to Left. Core to Right.

edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.5).2/12/12 Cadence SOC Encounter Tutorial Click on Appl and the floorplan should change to reflect the 100 micron peripher around the core. click Appl again. then to 2.pol .5. It is a good idea to eeweb.html 6/15 . Note how the number of rows in our floorplan changes from 5 (for 1) to 7 (for 2) to 3 (for 0. click Appl . finall back to 1 and click Appl . Now ou can also pla with the aspect ratio on the Specif floorplan window. change that to 0.

Choo e me al 4 and me al 5 i h he id h and pacing of 8 and 1 and i h off e of 1.pol . follo ed b Cancel. and hen fill he pop.p. hen Check (make e he e a e no a ning he e). hen click Appl . making e he b on Appl All i checked (need o do hi one a a ime b adding o li ).2/12/12 Cadence SOC Encounter Tutorial a e o de ign f om ime o ime b Design -> Sa e Design As -> SoCE.. The ne ep i o c ea e he po e and g o nd connec ion . Click on Floorplan -> Connect Global Nets.. No e can finall c ea e he po e di ib ion fo o de ign.p indo connec ing pin dd o global ne dd... Click Appl .. eeweb. and pin gnd o global ne gnd.html 7/15 . hen Cancel o clo e he pop..edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter. b fi o ha e o pecif he ne . Click Po er -> Po er Planning -> Add Rings..

2/12/12 Cadence SOC Encounter Tutorial Click Po er -> Po er Planning -> Add Stripes.. eeweb.edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter... then click Appl .pol . Choose metal 5 with the width and spacing of 8 and 1 and with Y from bottom of 30.html 8/15 . followed b OK.

deselect Pad pins. eeweb.pol . followed b OK..html 9/15 .2/12/12 Cadence SOC Encounter Tutorial Then. in order to route the rest of the power distribution click Ro e -> Special Ro e.. then click Appl ..edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.

html 10/15 .pol .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter. eeweb.2/12/12 Cadence SOC Encounter Tutorial Now our floorplan should look like this.

html 11/15 . A indo ill pop p and in he igh col mn o ho ld ee a line ha a FILL. i i all a good idea o place fill cell o fill in he gap be een o placed anda d cell . click Add follo ed b OK. In o de o a oid DRC e o la e . Selec FILL f om he igh ide... go o Place -> S anda d Cell and Block .2/12/12 Cadence SOC Encounter Tutorial I i ime o place o cell . p e he op Selec b on ne o he Cell Name( ) fo m.. follo ed b OK. and in he indo ha come p.. eeweb. hen click Appl . To do hi .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.pol . go o Place -> Fille -> Add Fille . Click Appl follo ed b OK. In he Add Fille indo o ho ld no ee FILL in he op fo m.

pol .2/12/12 Cadence SOC Encounter Tutorial Now. and click Appl followed b OK.edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter. Finall we can also route our design. eeweb. it looks like a transistor la out) ou will see our placed design. if ou click on the Ph sical View widget (on the right of the second row of the widget menu. right to the left of All Colors.html 12/15 .. go to Ro e -> NanoRo e -> Ro e..

html 13/15 .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.pol .2/12/12 Cadence SOC Encounter Tutorial And now our design should be also routed: eeweb.

2/12/12 Cadence SOC Encounter Tutorial Since we don't have pads in our design the tools route the primar inputs and outputs to the peripher of the floorplan such that the can in principle be connected in a hierarchical fashion to other blocks. and then click OK.pol .. Now that ou have completed the ph sical design of our circuit it is a good idea to verif it b running a DRC check. eeweb..html 14/15 . Make sure there are no violations listed in the terminal window.edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter. To do this in SoC Encounter. select Verif -> Verif Geometr .

hi i he end of he SoC Enco n e o ial.2/12/12 Cadence SOC Encounter Tutorial Cong a la ion .edu/labs/nanovlsi/tutorials/soctutorials/Tutorial_Encounter.html 15/15 .pol . eeweb.

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