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Application 80486™ Secondary Burst Cache Design Brief Using the IDT71024 (as Cache-Data SRAMs AB-06 and the Cache-Tag SRAM)
Integrated Device Technology, Inc.
The objective of this application brief is to highlight the IDT71024 (128K x 8 SRAM) as the Cache-Data SRAM in a 80486based system. This sample design of a zero wait-state secondary cache utilizes IDT71024s as both Cache-Data SRAMs and the Cache-Tag SRAM in a dual-bank interleaved configuration.
The IDT71024 is a 128K x 8 high-performance asynchronous SRAM. Features include Address and Chip Select access times as fast as 15ns, Output Enable access times as fast as 7ns, and industry standard 300- and 400mil package options. This part facilitates the implementation of high-performance secondary caches while using available Cache-Tag SRAMs, PALs, and chipsets for the 80486 processor.
FEATURES OF IDT71024
• 128K x 8 architecture • High Speed Address and Chip Select Access Times – 15, 17, 20ns • High Speed Output Enable Access Times – 7, 8ns • Low power consumption via chip deselect • JEDEC Standard Corner Power/Ground pinout • Available in both 300mil and 400mil 32-pin SOJ packages
• Nine 15ns IDT71024 SRAMs can be used to implement a zero-wait state1Mbyte cache for 50MHz systems • Industry standard function and configuration offers cost effective cache design option versus burst SRAM usage • Fast speeds in standard Corner Power/Ground package offers opportunity to easily upgrade existing designs to higher performance levels • Available 300mil SOJ offers higher board packing density over standard 400mil packages
IDT71024 BLOCK DIAGRAM
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 SO32-2 27 SO32-3 26 P32-3 25 D32-2 24 L32-2 23 22 21 20 19 18 17 VCC A15 CS2
• • •
• • •
1,024,576-BIT MEMORY ARRAY
A13 A8 A9 A11
I/O0 – I/O7
I/O7 I/O6 I/O5 I/O4 I/O3
3065 drw 02
WE OE CS1
3065 drw 01
The IDT logo is a registered trademark of Integrated Device Technology 80486 is a trademark of Intel Corp. ©1993 Integrated Device Technology, Inc.
Address bus derating = 2ns. and control logic delay are used.0ns. and the Output Enable (OE) function is utilized for the subsequent cache accesses of the four address burst sequence.(80486 clock to address:t6 + address bus derating + clock skew + control logic delay + 80486 BRDY setup to clock:t16) Cache-Data Timing: tAA (Leadoff Address Access) = 2 x cycle . Control logic delay = 5ns. The Address Access time (tAA) governs the leadoff data availability.A26 LOGIC 1 A0-15 A16 IDT71024 128K x 8 SRAM I/O0-6 I/O7 A3 WE OE CS I/Os 3 32 Addr IDT71024 128K x 8 SRAM A3 Addr IDT71024 128K x 8 SRAM WE OE CS I/Os 32 A3 3 A3 MEMORY READ/WRITE CONTROL LOGIC DATA CACHE READ/WRITE MAIN MEMORY READ / WRITE 32 D0 .D31 Integrated Device Technology.25ns = 15ns.(12ns + 2ns + 1ns + 5ns + 5ns) tAA(data) = 2 x 20ns . Assumptions: Clock skew = 1ns.A19 A20 A26 7 7 A20 A26 TAG RAM LOGIC 0 Buffer DATA RAMS 16 Buffer 80486 uP A20 . Controller clock to address = 2ns. t16 = 5. tAA ≤ 15ns. tOE ≤ 13ns. 3) SECONDARY CACHE BLOCK DIAGRAM 16 A4 . Integrated Device Technology. Inc. The actual performance of the cache subsystem depends on board layout. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product.0ns. Address buffer delay = 4ns.A26 27 . clock skew. t22 = 4ns. Inc.(80486 clock to address:t6 + address bus derating + address buffer delay + data bus derating + clock skew + 80486 data setup:t22) tOE (OE Access) = 1 x cycle . Estimates for derating.25ns = 15ns. Analysis is performed for critical tag and data RAM timing parameters. is designed for a 50MHz 80486-based system.80486™ Secondary Burst Cache Design Using the IDT71024 (as Cache-Data SRAMs and the Cache-Tag SRAM) APPLCATIONS BRIEF AB-06 1) SECONDARY CACHE PARTS LIST DEVICE 128K x 8 SRAM 128K x 8 SRAM IDT PART # IDT71024 IDT71024 QTY 1 8 33MHz 20ns 20ns 50MHz 15ns 15ns 2) CACHE ANALYSIS AND IMPLEMENTATION This secondary cache.(1ns + 2ns + 4ns) = 20ns . using nine IDT71024s. = 40ns .A19 16 A4 . A dual-bank interleaved data SRAM configuration is used to optimize cache performance.(clock skew + data bus derating + 80486 data setup:t22) 50MHz Timing Analysis: 80486 specs: t6 = 12. Santa Clara. 2975 Stender Way. tOE = 1 x 20ns . tAA(tag) = 2 x 20ns .7ns = 13ns. CA 95054-3090 2 Telephone: (800) 544-SRAM Fax: (408) 754-4547 AB-06-00123 Data Buffer 3065 drw 03 BRDY Comparator SYSTEM BUS A4 A19 A4 A19 Address Buffer ADDR A2 .(12ns + 2ns + 4ns + 2ns + 1ns + 4ns) = 40ns . tAA ≤ 15ns. Critical Timing Equations: Cache-Tag Timing: tAA (Address Access) = 2 x cycle . It is recommended that interconnect simulation of all host bus elements be done to determine the exact performance of a particular design. Data bus derating = 2ns.