# CSSE1000 – Lecture 2

Intro to Logic Gates

School of Information Technology and Electrical Engineering The University of Queensland

Today… Today
 Admin Issues  Introduction to Logic Gates  Circuit Schematics  Boolean Algebra  If you have questions, ask them at any time ti

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OR. yp ) on the “logic family”. depending g y . 1. binary)  ‘0’ – usually small voltage (e. type/size of transistors)  Logic gates  are the building blocks of computers. i. 1 and 0 – Can be called “true” and “false” 5 .g. AND. NOR gates  Inputs and outputs can have only two states. around 0 volts)  ‘1’ – usually larger voltage (e.g.e.: NOT.g.  Each gate has  one or more inputs  exactly one output  perform operations (or functions)  e. NAND.e.5 to 5 volts.Digital Logic Level  Digital circuits  Only two logical levels present (i.

 If A is 1. X is 0 This is the symbol for a NOT gate  Gate’s operation can be represented using a Gate s ope at o ca ep ese ted us g truth table: Input A 0 1 X 1 0 Output  A NOT gate is also called an inverter 6 . X is 1 .NOT Gate – the Simplest Gate  NOT gate – inverts the signal A X  If A is 0.

AND gate  Output is 1 if all inputs are 1.e. the output is 1 Truth Table Logic symbol A B AND X A 0 0 1 1 B 0 1 0 1 X 0 0 0 1  2-input AND gate  The “opposite” is a NAND gate (output is 0 if all inputs are 1) A X A B NAND X B A 0 0 1 1 B 0 1 0 1 7 X 1 1 1 0 Bubble means inversion .  i. if input A and input B p p and input C and … are all 1.

e. if input A or input B p p Truth Table Logic symbol A B OR X A 0 0 1 1 B 0 1 0 1 X 0 1 1 1 or input C or … is 1. the output is 1  2-input OR gate  The “opposite” is a NOR gate (output is 0 if any input is 1) A B OR X A B NOR X A 0 0 1 1 B 0 1 0 1 9 X 1 0 0 0 Bubble means inversion .OR gate  Output is 1 if at least one of the inputs is 1  i.

Exclusive OR gate (XOR)  For a 2-input gate…  Output is 1 if exactly one of the inputs is 1 p y p Truth Table Logic symbol g y A B X A 0 0 1 1 B 0 1 0 1 X 0 1 1 1 0 This entry is the difference between OR and XOR  For > 2 inputs  Output is 1 if an odd number of inputs is 1  Sometimes called the “odd function” 10 .

g. e. e.Logic Functions  Logic functions can be expressed as:  variables. ¯  Rules about how this works called Boolean algebra  Variables and functions can only take on values 0 or 1 12 .g. f functions. ti ABX +.

C) = ABC NOR(A.B) = AB = A.B  OR: plus sign  e.g.B.g.g.B) = A+B 13 . OR(A.B) = A B = Ā + AB ĀB NAND(A.Boolean Algebra conventions  Conventions we’ll use:  Inversion: ¯ (overline) ( )  e. AND(A.) or implied (by adjacency)  e.C) = A+B+C  Other examples:    XOR(A. NOT(A) = Ā  AND: dot(.B.

Summary of Logic Function y g Representations  There are four representations of logic functions (assume function of n inputs) ( p )  Truth table  Lists output for all 2n combinations of inputs – Best to list inputs in a systematic way  Boolean function (or equation)  Describes the conditions under which the function output is 1  Logic Diagram g g  Combination of logic symbols joined by wires  Timing Diagram 14 .

Logic Diagram Conventions Inputs are conventionally on left Outputs are conventionally on right A B M Indicates Electrical Connection No Connection Lines represent electrical g wires. Can be at high or low potential (logic 1 or logic 0 respectively). 15 .

3”. GND = Ground (0V) (e g 5V) 16 . 5V). chip is about 15mm long  74LS00 – has four 2-input NAND gates  Vcc = Power (e.1” x 0.Gates on Integrated Circuits (ICs) VCC 14 13 12 11 10 9 8 1 2 3 4 5 6 7 GND Pin Pi spacing i 0 1” i is 0.g.

g. U2 etc (Other components also labelled) Type of IC given also.Circuit Schematic Diagram  More than a logic diagram. e. a circuit schematic tells you how to build the circuit  You’ll need to draw these for pracs (& prac exam) ICs are labelled U1. g Outputs labelled Connections which aren’t part of the symbol shown separately Pin numbers are given Inputs are labelled 17 . 74LS00 or 74HCT00 yp g .

write down the AND combination of inputs that give that 1  OR these together A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 M 0 0 0 1 0 1 1 1 19 .Logic Function g Implementation  Any logic function can be implemented as the OR of AND combinations of the inputs  Called sum of products  Example:  Consider truth table  For each ‘1’ in the output column 1 column.

Logic Function g Implementation A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 M 0 0 0 1 0 1 1 1 20 .

) ) Equivalent Logic Diagram A B C A 1 A 4 ABC A B C M = ABC + ABC + ABC + ABC B 2 B 5 ABC 8 M 6 ABC C 3 C 7 ABC 21 .Example ( p (cont.

Equivalent Functions  Sum of products does not necessarily produce circuit with minimum number of gates  Can manipulate Boolean function to give an equivalent function  Use rules of Boolean algebra (next slide)  Example: Z = AB + AC = A(B+C) A B AB + AC A B C AC C B +C A(B + C ) AB Fewer gates 22 .

Boolean Identities Name Identity law Null law Idempotent law Inverse law Commutative law Associative law Distributative law Absorption law De Morgan's law 1A = A 0A = 0 AA = A AA = 0 AB = BA (AB)C = A(BC) A + BC = (A + B)(A + C) A(A + B) = A AB = A + B AND form OR form 0+A=A 1+A=1 A+A=A A+A=1 A+B=B+A (A + B) + C = A + (B + C) A(B + C) = AB + AC A + AB = A A + B = AB 23 .

Example  Express Z = A(B+C(A + B)) as a sum of products 24 .

De Morgan Law/Equivalents  AND/OR can be interchanged if you invert the inputs and outputs AB = A+B A+B = AB (a) (b) AB = A+B A+B = AB (c) (d)  Homework: Use truth tables to convince yourself that these are valid 25 .

Equivalent Circuits  All circuits can be constructed from NAND or NOR gates  Examples: p NOT A A A B B  These are called complete gates AND A AB OR A+B A A A B AB A B A+B  Reason: Easier to build NAND and NOR gates from transistors 27 .

XOR Implementation A 0 0 1 1 B 0 1 0 1 XOR 0 1 1 0 A B A B On any wire. you can introduce a bubble at beginning and end A B A B A B A B 28 .

Things To Do This Week     Go through the course profile Do the reading if you haven’t already Do the homework (due at Prac sessions) Sign-up (via session change request form) for  P Prac session i  Tutorial session 30 .