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Final Datasheet, Version 2.06, 2003-02-21

LIN Transceiver TLE 6259-2
LIN Transceiver
TLE 6259-2

Automotive and Industrial

Never

stop

Final Datasheet, Version 2.06, 2003-02-21 LIN Transceiver TLE 6259-2 Automotive and Industrial Never stop thinking.

thinking.

Single-Wire-Transceiver Final Datasheet 1 Overview 1.1 Features • Single-wire transceiver, suitable for LIN

Single-Wire-Transceiver

Final Datasheet

1

Overview

1.1

Features

• Single-wire transceiver, suitable for LIN protocol

• Transmission rate up to 20 kBaud

• Compatible to LIN specification 1.2

• Compatible to ISO 9141 functions

• Very low current consumption in sleep mode

• Control output for voltage regulator

• Bus short to GND protection

• Short circuit proof to ground and battery

• Overtemperature protection

TLE 6259-2

P-DSO-8-3, -6
P-DSO-8-3, -6

P-DSO-8-3, -6

Type

Ordering Code

Package

TLE 6259-2G

Q 67006 - A 9596

P-DSO-8-3

Description

The TLE 6259-2 is a monolithic integrated circuit in a P-DSO-8-3 package. It works as an interface between the protocol controller and the physical bus. The TLE 6259-2 is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. Further it can be used in standard ISO9141 systems. The TLE6259-2 has

a

BUS short to GND feature implemented, to avoid a battery decharge.

In

order to reduce the current consumption, the TLE 6259-2 offers a sleep operation

mode. In this mode a voltage regulator can be controlled to minimize the current

consumption of the whole application. A wake-up caused by a message on the bus, enables the voltage regulator and sets the RxD output LOW until the device is switched

to normal operation mode.

The IC is based on the Smart Power Technology SPT ® which allows bipolar and CMOS control circuitry in accordance with DMOS power devices existing on the same monolithic circuit.

The TLE 6259-2 is designed to withstand the severe conditions of automotive applications.

Final Datasheet TLE 6259-2 1.2 Pin Configuration (top view) RxD 1 8 INH EN 2
Final Datasheet TLE 6259-2
1.2
Pin Configuration (top view)
RxD
1
8
INH
EN
2
7
Vs
Vcc
3
6
Bus
GND
TxD
4
5
P-DSO-8-3
Figure 1
1.3
Pin Definitions and Functions:
Pin No.
Symbol
Function
1
RxD
Receive data output; integrated pull up, LOW in dominant state,
2
EN
Enable input; integrated 30 k pull down, transceiver in normal
operation mode when HIGH
3
V
5V supply input;
CC
4
TxD
Transmit data input; integrated pull up, LOW in dominant state
5
GND
Ground;
6
Bus
Bus output/input; internal 30 k pull up, LOW in dominant state
7
Vs
Battery supply input;
8
INH
Inhibit output; to control a voltage regulator, becomes HIGH
when wake-up via LIN bus occurs
Final Datasheet TLE 6259-2 1.4 Functional Block Diagram Vs 7 8 INH 3 Vcc Mode
Final Datasheet TLE 6259-2
1.4
Functional Block Diagram
Vs
7
8
INH
3
Vcc
Mode
2
EN
Output
30 k
Control
Stage
Driver
30 k
Bus
6
Temp.-
Protection
4
TxD
Filter
1
RxD
Receiver
TLE 6259-2G
5
GND
Figure 2
Final Datasheet TLE 6259-2 1.5 Application Information Start Up Power Up Normal Mode EN INH

Final Datasheet TLE 6259-2

1.5 Application Information

Start Up Power Up Normal Mode EN INH Vcc high high ON EN high EN
Start Up
Power Up
Normal Mode
EN
INH
Vcc
high
high
ON
EN
high
EN
low
Stand-By
EN
INH
RxD
V CC
low
high
low 1)
ON
EN
high
high 3)
ON)
(V CC
Sleep Mode
EN
INH
V CC
Wake Up
low
floating
OFF 2)
t > t WAKE

1) after wake-up via bus 2) ON when INH not connected to voltage regulator 3) after start up

Figure 3: operation mode state diagram

Master Termination

For fail safe reasons, the TLE6259-2 already has a pull up resistor of 30k implemented. To achieve the required timings for the dominant to recessive transition of the bus signal an additional external termination resistor of 1k is required. It is recommended to place this resistor in the master node. To avoid reverse currents from the bus line into the battery supply line in case of an unpowered node, it is recommended to place a diode in series to the external pull up. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1nF in the master node (see figure 6 and 7, application circuit).

External Capacitors

An capacitor of 22µF at the supply voltage input V S buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line.

Final Datasheet TLE 6259-2 The 100nF capacitors close to the V S pins of the

Final Datasheet TLE 6259-2

The 100nF capacitors close to the V S pins of the 6259-2 and the voltage regulator help to improve the EMC behavior of the system.

Sleep Mode

In order to reduce the current consumption the TLE 6259-2 offers a sleep operation mode. This mode is selected by switching the enable input EN low (see figure 3, state diagram). In the sleep mode, a voltage regulator can be controlled via the INH output in order to minimize the current consumption of the whole application. A wake-up caused by a message on the communication bus, automatically enables the voltage regulator by switching the INH output high. In parallel the wake-up is indicated by setting the RxD output LOW. When entering the normal mode this wake-up flag is reset and the RxD output is released to transmit the bus data.

In case the voltage regulator control input is not connected to INH output or the microcontroller is active respectively, the TLE6259-2 can be set in normal operation mode without a wake-up via the communication bus.

Bus Short to GND Feature

The TLE6259-2 also has a BUS short to GND feature implemented, in order to protect the battery from running out of charge. A normal master termination connection like described above, 1k resistor and diode between bus and V S , whould cause a constantly drawn current via this path. The resulting resistance of this short to GND is lower than 1k . To avoid this current during a generator off state, like a parked car, the sleep mode has a bus short to GND feature implemented in the 6259-2. This feature is only applicable, if the master termination is connected with the INH pin, instead of the V S . For a more detailed information see the application circuit in figure 6 and 7.

Final Datasheet TLE 6259-2 2 Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Symbol

Final Datasheet TLE 6259-2

2

Electrical Characteristics

2.1

Absolute Maximum Ratings

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

Voltages

Supply voltage

V

CC

-0.3

6

V

 

Battery supply voltage

V

S

-0.3

40

V

 

Bus input voltage

V

bus

-20

32

V

 

Bus input voltage

V

bus

-20

40

V

t < 1s

Logic voltages at EN, TxD, RxD

V

I

-0.3

V CC +

V

0 V < V CC < 5.5 V

0.3

Input voltages at INH

V

INH

-0.3

V S +

V

 

0.3

Output current at INH

I

INH

 

20

mA

 

Electrostatic discharge voltage at Vs, Bus

V

ESD

-4

4

kV

human body model (100 pF via 1.5 k

Electrostatic discharge voltage

V

ESD

-2

2

kV

human body model (100 pF via 1.5 k

Temperatures

         

Junction temperature

T

j

-40

150

C

Note:

Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.

Final Datasheet TLE 6259-2 2.2 Operating Range Parameter Symbol Limit Values Unit Remarks min. max.

Final Datasheet TLE 6259-2

2.2 Operating Range

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

Supply voltage

V

CC

4.5

5.5

V

 

Battery Supply Voltage

V

S

6

35

V

 

Junction temperature

T

j

– 40

150

C

Thermal Resistances

Junction ambient

R

thj-a

185

K/W

Thermal Shutdown (junction temperature)

 
 

Symbol

Limit Values

Unit

   

min.

typ.

max.

 

Thermal shutdown temp.

T

jSD

150

170

190

C

Thermal shutdown hyst.

T

10

K

Final Datasheet TLE 6259-2 2.3 Electrical Characteristics 4.5 V < V C C < 5.5

Final Datasheet TLE 6259-2

2.3 Electrical Characteristics

4.5 V < V CC < 5.5 V; 6.0 V < V S < 27 V; R L =500 ; V EN > V EN,ON ; -40 °C < T j < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

typ.

max.

Current Consumption

Current consumption inNormal Mode

I

CC

 

0.3

0,7

mA

recessive state;

V TxD = V CC

   

0.4

0.8

mA

dominant state; V TxD = 0 V

I

S

 

0.8

1.5

mA

recessive state, without R load ;

V TxD = V CC

 

1.3

2

mA

dominant state, without R load ; V TxD = 0 V

Current consumption in Standby Mode

I

CC

 

3

10

µA

external VR

activated INH=H

 

I

S

 

18

30

µA

Current consumption in Sleep Mode

I

CC

 

-

-

µA

external VR deactivated INH=L

I

S

 

18

30

µA

Final Datasheet TLE 6259-2 2.3 Electrical Characteristics (cont’d) 4.5 V < V C C <

Final Datasheet TLE 6259-2

2.3 Electrical Characteristics (cont’d)

4.5 V < V CC < 5.5 V; 6.0 V < V S < 27 V; R L =500 ; V EN > V EN,ON ; -40 °C < T j < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

typ.

max.

Receiver Output R D

HIGH level output current

I RD,H

-1.2

-0.8

-0.5

mA

V RD = 0.8 x V CC ,

LOW level output current

I RD,L

0.5

0.8

1.2

mA

V RD = 0.2 x V CC ,

Transmission Input T D

HIGH level input voltage threshold

V

TD,H

 

2.9

0.7

x

V

recessive state

V

CC

TxD input hysteresis

V

TD,hys

300

700

900

mV

 

LOW level input voltage threshold

V

TD,L

0.3

x

2.1

 

V

dominant state

V

CC

TxD pull up current

I

TD

-150

-110

-70

µA

V TxD <0.3Vcc

Enable input (pin EN)

HIGH level input voltage threshold

V

EN,on

 

2.8

0.7

x

V

normal mode

V

CC

LOW level input voltage threshold

V

EN,off

0.3

x

2.2

 

V

low power mode

V

CC

EN input hysteresis

V

EN,hys

300

600

900

mV

 

EN pull down resistance

R

EN

15

30

60

k

 

Inhibit output (pin INH)

Inhibit R on resistance

R

onINH

 

65

120

I INH = - 15 mA

Leakage current

I

INH,lk

- 5.0

 

5.0

µA

sleep mode; V INH = 0 V

Final Datasheet TLE 6259-2 2.3 Electrical Characteristics (cont’d) 4.5 V < V C C <

Final Datasheet TLE 6259-2

2.3 Electrical Characteristics (cont’d)

4.5 V < V CC < 5.5 V; 6.0 V < V S < 27 V; R L =500 ; V EN > V EN,ON ; -40 °C < T j < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

typ.

max.

Bus receiver

Receiver threshold voltage, recessive to dominant edge

V

bus,rd

0.44

0.5

x

 

V

-8V<V bus <V bus,dom

x

V S

V

S

Receiver threshold voltage, dominant to recessive edge

V

bus,dr

 

0.56

0.6

x

V

V bus,rec <V bus <20 V

x

V S

V

S

Receiver hysteresis

V

bus,hys

0.02

0.04

0.1

x

mV

V bus,hys =

x

V S

x

V S

V

S

V bus,rec - V bus,dom

wake-up threshold voltage

V

wake

0.40

x

V S

0.5

V

S

x

0.6

V

S

x

V

 

Bus transmitter

Bus recessive output voltage

V

bus,rec

0.9 x

V

S

 

V

S

V

V TxD = V CC

Bus dominant output voltage

V

bus,dom

   

0.15

V

V TxD = 0 V; 8V<V S <27V

x V S

   

1.2

V

6V<V S <8V

Bus short circuit current

I

bus,sc

40

100

150

mA

V bus,short = 13.5 V

Leakage current

I

bus,lk

-150

-70

 

A

V CC = 0 V, V S = 0 V, V bus = -8 V

 

10

25

A

V CC = 0 V, V S = 0 V, V bus = 20 V

   

10

µA

V LIN =V S =13,5V

Bus pull up resistance

R

bus

20

30

47

k

Normal mode

Lin output current

I

lin

5

30

60

µA

Sleep mode

Final Datasheet TLE 6259-2 2.3 Electrical Characteristics (cont’d) 4.5 V < V C C <

Final Datasheet TLE 6259-2

2.3 Electrical Characteristics (cont’d)

4.5 V < V CC < 5.5 V; 6.0 V < V S < 27 V; R L =500 ; V EN > V EN,ON ; -40 °C < T j < 125 °C; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

typ.

max.

Dynamic Transceiver Characteristics

 

Slope fall time

t

fslope

   

22,5

µs

100% > V bus > 0% C bus = 10 nF; R L =500 V CC = 5 V; V S = 13.5 V

Slope rise time

t

rslope

   

22,5

µs

0% > V bus >10 0% C bus = 10 nF; R L =500 V CC = 5 V; V S = 13.5 V

Slope symmetry

t

slopesym

-5

 

5

µs

t fslope- t rslope

Slope fall time

t

fslope

   

22.5

µs

100% > V bus > 0% C bus = 6,8nF;R L =660

T ambient < 85 °C; V CC = 5 V; V S = 13.5 V

 

Slope rise time

t

rslope

   

22.5

µs

0% > V bus >100% C bus = 6,8nF;R L =660 V CC = 5 V; V S = 13.5 V

Slope symmetry

t

slopesym

-4

 

4

µs

t fslope- t rslope

Propagation delay TxD LOW to bus

t

d(L),T

 

1

3

µs

V CC = 5 V

Propagation delay TxD HIGH to bus

t

d(H),T

 

1

3

µs

V CC = 5 V

Propagation delay bus dominant to RxD LOW

t

d(L),R

 

1

6

µs

V CC = 5V; C RxD = 20pF

Propagation delay bus recessive to RxD HIGH

t

d(H),R

 

1

6

µs

V CC = 5 V; C RxD = 20 pF

Receiver delay symmetry

t

sym,R

-2

 

2

µs

t sym,R = t d(L),R - t d(H),R

Transmitter delay symmetry

t

sym,T

-2

 

2

µs

t sym,T = t d(L),T - t d(H),T

Wake-up delay time

t

wake

30

100

150

µs

T j 125°

     

170

µs

T j 150°

Delay time for change sleep/ stand by mode-normal mode

t

snorm

   

10

µs

 

Delay time for change normal mode - sleep mode

t

nsleep

   

10

µs

 
Final Datasheet TLE 6259-2 3 Diagrams
Final Datasheet TLE 6259-2
3
Diagrams
EN Vs 100 nF INH 1 k TxD Bus RxD 20 pF C bus V
EN
Vs
100 nF
INH
1 k
TxD
Bus
RxD
20 pF
C
bus
V
CC
GND
100 nF

Figure 4: Test circuits

V CC V TxD GND t t t d(L),T d(H),T V S V bus V
V
CC
V
TxD
GND
t
t
t
d(L),T
d(H),T
V
S
V
bus
V bus,rd
V bus,dr
GND
t
t
t
d(L),R
d(H),R
V
CC
0.7*V CC
V
RxD
0.3*V CC
GND
t
t
t
d(L),TR
d(H),TR

Figure 5: Timing diagrams for dynamic characteristics

Final Datasheet TLE 6259-2 4 Application
Final Datasheet TLE 6259-2
4
Application
V LIN bus master node bat TLE 6259-2G Vs EN RxD µP 100 nF 1
V
LIN bus
master node
bat
TLE 6259-2G
Vs
EN
RxD
µP
100 nF
1 k
Bus
TxD
V
INH
1nF
CC
GND
GND
100 nF
100
nF
5V
INH
V
Q
e.g. TLE 4263
22 µF
V
I
GND
22
µF
100 nF
ECU 1
slave node
TLE 6259-2G
Vs
EN
100 nF
RxD
Bus
TxD
µP
V
INH
CC
GND
GND
100 nF
100
nF
5V
V
V
I
Q
e.g. TLE 4278
22 µF
100 nF
GND
22
µF
ECU X

Figure 6 Application circuit with bus short to GND feature applied

Final Datasheet TLE 6259-2 V LIN bus master node bat TLE 6259-2G Vs EN RxD

Final Datasheet TLE 6259-2

V LIN bus master node bat TLE 6259-2G Vs EN RxD µP 100 nF 1
V
LIN bus
master node
bat
TLE 6259-2G
Vs
EN
RxD
µP
100 nF
1 k
Bus
TxD
1nF
V
INH
CC
GND
GND
100 nF
100
nF
5V
INH
V
Q
e.g. TLE 4263
22 µF
V
I
GND
22
µF
100 nF
ECU 1
slave node
TLE 6259-2G
Vs
EN
100 nF
RxD
µP
Bus
TxD
V
INH
CC
GND
GND
100 nF
100
nF
5V
V
V
I
Q
e.g. TLE 4278
100 nF
22 µF
GND
22
µF
ECU X

Figure 7 Application circuit without bus short to GND feature

Final Datasheet TLE 6259-2 5 Package Outlines P-DSO-8-3 (Plastic Dual Small Outline Package) 0.33 ±0.08

Final Datasheet TLE 6259-2

5 Package Outlines

P-DSO-8-3

(Plastic Dual Small Outline Package)

0.33 ±0.08 x 45˚ 1) 4 -0.2 1.27 C 0.1 0.64 ±0.25 +0.1 0.41 -0.05
0.33 ±0.08
x 45˚
1)
4 -0.2
1.27
C
0.1
0.64
±0.25
+0.1
0.41
-0.05
0.2 M
A
C x8
6 ±0.2
8
5
Index
Marking
1
4
A
1)
5
-0.2
0.1 MIN.
(1.5)
1.75 MAX.
+0.05
0.2
-0.01
MAX.8˚

Index Marking (Chamfer)

1)

Does not include plastic or metal protrusion of 0.15 max. per side

Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”.

SMD = Surface Mounted Device

Dimensions in mm

Final Datasheet TLE 6259-2 Edition 1999-10-12 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541

Final Datasheet TLE 6259-2

Edition 1999-10-12

Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 München © Infineon Technologies AG1999 All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer.

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