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Introduction

The preliminary exam (dugga) consists of four questions. The maximum number of points is 5. The maximum allowed time to answer the questions is 30 minutes. Admitted material: none. Good Luck!

1. Boundary scan
Q1. Draw an implementation of a boundary scan cell! (1 point) A1.

Q2. Assume you are to test for Sa0 and Sa1 faults on the interconnection between Chip 1 and Chip 3 on the board design presented in Figure 1. Assume that the following inputs are given: Chip 1: IR-length = 12 bits BSR = 100 bits Chip 2:IR-length = 10 bits BSR = 175 bits Chip 3: IR-length = 15 bits BSR = 80 bits What is the minimal number of TCK cycles required to perform the test? (1 point)

Chip 1 TDI TDO

Chip 2

Chip 3

Figure 1. Board design

A2. To test for Sa0 or Sa1 on the interconnections between Chip 1 and Chip 3, two test patterns are required, and it is necessary for Chip 1 and Chip 3 to execute the EXTEST instruction, while for Chip 2 is important to execute the BYPASS instruction so that the test data that is to be shifted in the boundary scan chain is minimized. The first step to be performed is to set the proper operational codes in the instruction registers for each of the chips. For this a single iteration through the IR-Scan is required. Assuming that the TAP controller is in TLR state, to complete this step and that is to shift in the exact operational codes for each of the chips It is required to shift a bit stream with the size of 12 + 10 + 15 (sum of the size of the instruction register for each chip).

Therefore, it will take 4 TCK to reach Capture-IR state, followed by 37 TCK to shift the bit stream, once the shifting is completed, the TAP controller should progress to Exit1-IR state for 1TCK, and 1 TCK to reach the Update-IR state. So in total 43 TCK are required to execute the first step, i.e. specify the instructions for each of the chips. Next, we need to apply the test data. For each test pattern we need to shift in the test pattern, update and capture. While shifting in the second pattern, we get the responses for the first pattern. To get the responses for the second pattern, it is required to shift in data through the boundary scan chain. In that regard, three iterations of the DR-Scan are required.

TDDC33 Design for Test of Digital Systems

To reach the Select-DR Scan state, 1 TCK is required (observe that prior to this the controller was in the Update-IR state). One more TCK is required to reach the Capture-DR state. After that we need to shift in the test data. Since Chip 1 and Chip 3 are executing EXTEST instruction, the boundary scan register for these two chips will be selected, and the Bypass register will be selected for Chip 2 which is executing the BYPASS instruction. In that regard the amount of bits to be shifted in is equal to 100+1+80=181, and thus 181 TCK are required to shift in the test data. Once the shifting is completed 1 TCK is required to progress to Exit1-DR state and 1 TCK is required to reach Update-DR state. Therefore, one iteration through the DR-Scan takes 1+1+181+1+1=185 TCK. Once the test data are applied and the responses are collected, the TAP controller should reach the Run-Test/Idle state. Observe that the last state that was reached in the DR-Scan is the Update-DR. To reach Run-Test/Idle state from the Update-DR state only one TCK is required (TMS=0). Summing everything together (set the instructions, apply the test data, collect the test responses, reach the Run-Test/Idle state) leads to a total of: 43+3*185 +1=43+555+1=599 TCK.

TDDC33 Design for Test of Digital Systems

Q3. What is the minimal size for the instruction register in a boundary scan implementation? Explain
your answer! (1 point)

A3. Since the instruction register keeps the operational code for the instruction to be executed, the size
of the instruction register will mainly depend on the number of instructions that can be executed. Since here we are only interested in the minimal size of the instruction register, we will only need the mandatory instructions, i.e. EXTEST, BYPASS, SAMPLE and PRELOAD. To code 4 instructions 2 bits are required, thus the minimal size of the instruction register is 2 bits. For example: 00-EXTEST, 11-BYPASS, 10- SAMPLE/PRELOAD

Q4. Determine the validity of the following statements: (2 points)

Statement True The TAP controller in IEEE 1500 consists of 18 different states, unlike the TAP controller in IEEE 1149.1 which consists of only 16 different states The IEEE 1149.1 TAP (Test Access Port) can be used for running interconnection X
tests, flashing flash devices, In-System Programming (ISP) for programmable devices

False X

IEEE 1149.1 can not be used for testing the core logic of the chips since its only purpose is to test the interconnections between the chips The TAP controller can always return to the Test Logic Reset (TLR) state by applying 1 on the TDI pin for at most 5 cycles of TCK IEEE 1500 does not have a finite state machine (TAP controller)

X X

IEEE 1149.1 can be used for testing the core logic of the chips by implementing the optional INTEST instruction The TAP controller can always return to the Test Logic Reset (TLR) state by applying 1 on the TDI TMS pin for at most 5 cycles of TCK

TDDC33 Design for Test of Digital Systems